if_ipwreg.h revision 1.1.1.2
1 /* $FreeBSD: src/sys/dev/ipw/if_ipwreg.h,v 1.1 2005/04/18 18:47:36 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IPW_NTBD 128 31 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 32 #define IPW_NDATA (IPW_NTBD / 2) 33 #define IPW_NRBD 128 34 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 35 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 36 37 #define IPW_CSR_INTR 0x0008 38 #define IPW_CSR_INTR_MASK 0x000c 39 #define IPW_CSR_INDIRECT_ADDR 0x0010 40 #define IPW_CSR_INDIRECT_DATA 0x0014 41 #define IPW_CSR_AUTOINC_ADDR 0x0018 42 #define IPW_CSR_AUTOINC_DATA 0x001c 43 #define IPW_CSR_RST 0x0020 44 #define IPW_CSR_CTL 0x0024 45 #define IPW_CSR_IO 0x0030 46 #define IPW_CSR_TX_BASE 0x0200 47 #define IPW_CSR_TX_SIZE 0x0204 48 #define IPW_CSR_RX_BASE 0x0240 49 #define IPW_CSR_STATUS_BASE 0x0244 50 #define IPW_CSR_RX_SIZE 0x0248 51 #define IPW_CSR_TX_READ 0x0280 52 #define IPW_CSR_RX_READ 0x02a0 53 #define IPW_CSR_TABLE1_BASE 0x0380 54 #define IPW_CSR_TABLE2_BASE 0x0384 55 #define IPW_CSR_TX_WRITE 0x0f80 56 #define IPW_CSR_RX_WRITE 0x0fa0 57 58 /* possible flags for register IPW_CSR_INTR */ 59 #define IPW_INTR_TX_TRANSFER 0x00000001 60 #define IPW_INTR_RX_TRANSFER 0x00000002 61 #define IPW_INTR_STATUS_CHANGE 0x00000010 62 #define IPW_INTR_COMMAND_DONE 0x00010000 63 #define IPW_INTR_FW_INIT_DONE 0x01000000 64 #define IPW_INTR_FATAL_ERROR 0x40000000 65 #define IPW_INTR_PARITY_ERROR 0x80000000 66 67 #define IPW_INTR_MASK \ 68 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 69 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 70 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 71 IPW_INTR_PARITY_ERROR) 72 73 /* possible flags for register IPW_CSR_RST */ 74 #define IPW_RST_PRINCETON_RESET 0x00000001 75 #define IPW_RST_SW_RESET 0x00000080 76 #define IPW_RST_MASTER_DISABLED 0x00000100 77 #define IPW_RST_STOP_MASTER 0x00000200 78 79 /* possible flags for register IPW_CSR_CTL */ 80 #define IPW_CTL_CLOCK_READY 0x00000001 81 #define IPW_CTL_ALLOW_STANDBY 0x00000002 82 #define IPW_CTL_INIT 0x00000004 83 84 /* possible flags for register IPW_CSR_IO */ 85 #define IPW_IO_GPIO1_ENABLE 0x00000008 86 #define IPW_IO_GPIO1_MASK 0x0000000c 87 #define IPW_IO_GPIO3_MASK 0x000000c0 88 #define IPW_IO_LED_OFF 0x00002000 89 #define IPW_IO_RADIO_DISABLED 0x00010000 90 91 #define IPW_STATE_ASSOCIATED 0x0004 92 #define IPW_STATE_ASSOCIATION_LOST 0x0008 93 #define IPW_STATE_SCAN_COMPLETE 0x0020 94 #define IPW_STATE_RADIO_DISABLED 0x0100 95 #define IPW_STATE_DISABLED 0x0200 96 #define IPW_STATE_SCANNING 0x0800 97 98 /* table1 offsets */ 99 #define IPW_INFO_LOCK 480 100 #define IPW_INFO_APS_CNT 604 101 #define IPW_INFO_APS_BASE 608 102 #define IPW_INFO_CARD_DISABLED 628 103 #define IPW_INFO_CURRENT_CHANNEL 756 104 #define IPW_INFO_CURRENT_TX_RATE 768 105 106 /* table2 offsets */ 107 #define IPW_INFO_CURRENT_SSID 48 108 #define IPW_INFO_CURRENT_BSSID 112 109 110 /* supported rates */ 111 #define IPW_RATE_DS1 1 112 #define IPW_RATE_DS2 2 113 #define IPW_RATE_DS5 4 114 #define IPW_RATE_DS11 8 115 116 /* firmware binary image header */ 117 struct ipw_firmware_hdr { 118 u_int32_t version; 119 u_int32_t main_size; /* firmware size */ 120 u_int32_t ucode_size; /* microcode size */ 121 } __packed; 122 123 /* buffer descriptor */ 124 struct ipw_bd { 125 u_int32_t physaddr; 126 u_int32_t len; 127 u_int8_t flags; 128 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 129 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 130 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 131 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 132 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 133 u_int8_t nfrag; /* number of fragments */ 134 u_int8_t reserved[6]; 135 } __packed; 136 137 /* status */ 138 struct ipw_status { 139 u_int32_t len; 140 u_int16_t code; 141 #define IPW_STATUS_CODE_COMMAND 0 142 #define IPW_STATUS_CODE_NEWSTATE 1 143 #define IPW_STATUS_CODE_DATA_802_11 2 144 #define IPW_STATUS_CODE_DATA_802_3 3 145 #define IPW_STATUS_CODE_NOTIFICATION 4 146 u_int8_t flags; 147 #define IPW_STATUS_FLAG_DECRYPTED 0x01 148 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 149 u_int8_t rssi; /* received signal strength indicator */ 150 } __packed; 151 152 /* data header */ 153 struct ipw_hdr { 154 u_int32_t type; 155 #define IPW_HDR_TYPE_SEND 33 156 u_int32_t subtype; 157 u_int8_t encrypted; 158 u_int8_t encrypt; 159 u_int8_t keyidx; 160 u_int8_t keysz; 161 u_int8_t key[IEEE80211_KEYBUF_SIZE]; 162 u_int8_t reserved[10]; 163 u_int8_t src_addr[IEEE80211_ADDR_LEN]; 164 u_int8_t dst_addr[IEEE80211_ADDR_LEN]; 165 u_int16_t fragmentsz; 166 } __packed; 167 168 /* command */ 169 struct ipw_cmd { 170 u_int32_t type; 171 #define IPW_CMD_ENABLE 2 172 #define IPW_CMD_SET_CONFIGURATION 6 173 #define IPW_CMD_SET_ESSID 8 174 #define IPW_CMD_SET_MANDATORY_BSSID 9 175 #define IPW_CMD_SET_MAC_ADDRESS 11 176 #define IPW_CMD_SET_MODE 12 177 #define IPW_CMD_SET_CHANNEL 14 178 #define IPW_CMD_SET_RTS_THRESHOLD 15 179 #define IPW_CMD_SET_FRAG_THRESHOLD 16 180 #define IPW_CMD_SET_POWER_MODE 17 181 #define IPW_CMD_SET_TX_RATES 18 182 #define IPW_CMD_SET_BASIC_TX_RATES 19 183 #define IPW_CMD_SET_WEP_KEY 20 184 #define IPW_CMD_SET_WEP_KEY_INDEX 25 185 #define IPW_CMD_SET_WEP_FLAGS 26 186 #define IPW_CMD_ADD_MULTICAST 27 187 #define IPW_CMD_SET_BEACON_INTERVAL 29 188 #define IPW_CMD_SET_TX_POWER_INDEX 36 189 #define IPW_CMD_BROADCAST_SCAN 43 190 #define IPW_CMD_DISABLE 44 191 #define IPW_CMD_SET_DESIRED_BSSID 45 192 #define IPW_CMD_SET_SCAN_OPTIONS 46 193 #define IPW_CMD_PREPARE_POWER_DOWN 58 194 #define IPW_CMD_DISABLE_PHY 61 195 #define IPW_CMD_SET_SECURITY_INFORMATION 67 196 #define IPW_CMD_SET_WPA_IE 69 197 u_int32_t subtype; 198 u_int32_t seq; 199 u_int32_t len; 200 u_int8_t data[400]; 201 u_int32_t status; 202 u_int8_t reserved[68]; 203 } __packed; 204 205 /* possible values for command IPW_CMD_SET_POWER_MODE */ 206 #define IPW_POWER_MODE_CAM 0 207 #define IPW_POWER_AUTOMATIC 6 208 209 /* possible values for command IPW_CMD_SET_MODE */ 210 #define IPW_MODE_BSS 0 211 #define IPW_MODE_IBSS 1 212 #define IPW_MODE_MONITOR 2 213 214 /* possible flags for command IPW_CMD_SET_WEP_FLAGS */ 215 #define IPW_WEPON 0x8 216 217 /* structure for command IPW_CMD_SET_WEP_KEY */ 218 struct ipw_wep_key { 219 u_int8_t idx; 220 u_int8_t len; 221 u_int8_t key[13]; 222 } __packed; 223 224 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 225 struct ipw_security { 226 u_int32_t ciphers; 227 #define IPW_CIPHER_NONE 0x00000001 228 #define IPW_CIPHER_WEP40 0x00000002 229 #define IPW_CIPHER_TKIP 0x00000004 230 #define IPW_CIPHER_CCMP 0x00000010 231 #define IPW_CIPHER_WEP104 0x00000020 232 #define IPW_CIPHER_CKIP 0x00000040 233 u_int16_t reserved1; 234 u_int8_t authmode; 235 #define IPW_AUTH_OPEN 0 236 #define IPW_AUTH_SHARED 1 237 u_int16_t reserved2; 238 } __packed; 239 240 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 241 struct ipw_scan_options { 242 u_int32_t flags; 243 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 244 #define IPW_SCAN_PASSIVE 0x00000008 245 u_int32_t channels; 246 } __packed; 247 248 /* structure for command IPW_CMD_SET_CONFIGURATION */ 249 struct ipw_configuration { 250 u_int32_t flags; 251 #define IPW_CFG_PROMISCUOUS 0x00000004 252 #define IPW_CFG_PREAMBLE_AUTO 0x00000010 253 #define IPW_CFG_IBSS_AUTO_START 0x00000020 254 #define IPW_CFG_802_1x_ENABLE 0x00004000 255 #define IPW_CFG_BSS_MASK 0x00008000 256 #define IPW_CFG_IBSS_MASK 0x00010000 257 u_int32_t bss_chan; 258 u_int32_t ibss_chan; 259 } __packed; 260 261 /* structure for command IPW_CMD_SET_WPA_IE */ 262 struct ipw_wpa_ie { 263 u_int16_t mask; 264 u_int16_t capinfo; 265 u_int16_t lintval; 266 u_int8_t bssid[IEEE80211_ADDR_LEN]; 267 u_int32_t len; 268 struct ieee80211_ie_wpa ie; 269 } __packed; 270 271 /* element in AP table */ 272 struct ipw_node { 273 u_int32_t reserved1[2]; 274 u_int8_t bssid[IEEE80211_ADDR_LEN]; 275 u_int8_t chan; 276 u_int8_t rates; 277 u_int16_t reserved2; 278 u_int16_t capinfo; 279 u_int16_t reserved3; 280 u_int16_t intval; 281 u_int8_t reserved4[28]; 282 u_int8_t essid[IEEE80211_NWID_LEN]; 283 u_int16_t reserved5; 284 u_int8_t esslen; 285 u_int8_t reserved6[7]; 286 u_int8_t rssi; 287 } __packed; 288 289 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 290 291 #define IPW_MEM_EEPROM_CTL 0x00300040 292 293 #define IPW_EEPROM_RADIO 0x11 294 #define IPW_EEPROM_MAC 0x21 295 #define IPW_EEPROM_CHANNEL_LIST 0x37 296 297 #define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 298 299 #define IPW_EEPROM_C (1 << 0) /* Serial Clock */ 300 #define IPW_EEPROM_S (1 << 1) /* Chip Select */ 301 #define IPW_EEPROM_D (1 << 2) /* Serial data input */ 302 #define IPW_EEPROM_Q (1 << 4) /* Serial data output */ 303 304 #define IPW_EEPROM_SHIFT_D 2 305 #define IPW_EEPROM_SHIFT_Q 4 306 307 /* 308 * control and status registers access macros 309 */ 310 #define CSR_READ_1(sc, reg) \ 311 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 312 313 #define CSR_READ_2(sc, reg) \ 314 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 315 316 #define CSR_READ_4(sc, reg) \ 317 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 318 319 #define CSR_WRITE_1(sc, reg, val) \ 320 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 321 322 #define CSR_WRITE_2(sc, reg, val) \ 323 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 324 325 #define CSR_WRITE_4(sc, reg, val) \ 326 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 327 328 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 329 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 330 (buf), (len)) 331 332 /* 333 * indirect memory space access macros 334 */ 335 #define MEM_WRITE_1(sc, addr, val) do { \ 336 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 337 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 338 } while (/* CONSTCOND */0) 339 340 #define MEM_WRITE_2(sc, addr, val) do { \ 341 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 342 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 343 } while (/* CONSTCOND */0) 344 345 #define MEM_WRITE_4(sc, addr, val) do { \ 346 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 347 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 348 } while (/* CONSTCOND */0) 349 350 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 351 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 352 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 353 } while (/* CONSTCOND */0) 354 355 /* 356 * EEPROM access macro 357 */ 358 #define IPW_EEPROM_CTL(sc, val) do { \ 359 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \ 360 DELAY(IPW_EEPROM_DELAY); \ 361 } while (0) 362
Indexes created Thu Oct 02 14:10:14 GMT 2025