if_ipwreg.h revision 1.2.2.2
1 /* $NetBSD: if_ipwreg.h,v 1.2.2.2 2004/08/25 06:58:05 skrll Exp $ */ 2 /* Id: if_ipwreg.h,v 1.1.2.1 2004/08/19 16:28:26 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004 6 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #define IPW_NTBD 256 32 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 33 #define IPW_NDATA (IPW_NTBD / 2) 34 #define IPW_NRBD 256 35 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 36 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 37 38 #define IPW_CSR_INTR 0x0008 39 #define IPW_CSR_INTR_MASK 0x000c 40 #define IPW_CSR_INDIRECT_ADDR 0x0010 41 #define IPW_CSR_INDIRECT_DATA 0x0014 42 #define IPW_CSR_AUTOINC_ADDR 0x0018 43 #define IPW_CSR_AUTOINC_DATA 0x001c 44 #define IPW_CSR_RST 0x0020 45 #define IPW_CSR_CTL 0x0024 46 #define IPW_CSR_IO 0x0030 47 #define IPW_CSR_TABLE1_BASE 0x0380 48 #define IPW_CSR_TABLE2_BASE 0x0384 49 #define IPW_CSR_RX_BD_BASE 0x0240 50 #define IPW_CSR_RX_STATUS_BASE 0x0244 51 #define IPW_CSR_RX_BD_SIZE 0x0248 52 #define IPW_CSR_RX_READ_INDEX 0x02a0 53 #define IPW_CSR_RX_WRITE_INDEX 0x0fa0 54 #define IPW_CSR_TX_BD_BASE 0x0200 55 #define IPW_CSR_TX_BD_SIZE 0x0204 56 #define IPW_CSR_TX_READ_INDEX 0x0280 57 #define IPW_CSR_TX_WRITE_INDEX 0x0f80 58 59 #define IPW_INTR_TX_TRANSFER 0x00000001 60 #define IPW_INTR_RX_TRANSFER 0x00000002 61 #define IPW_INTR_STATUS_CHANGE 0x00000010 62 #define IPW_INTR_COMMAND_DONE 0x00010000 63 #define IPW_INTR_FW_INIT_DONE 0x01000000 64 #define IPW_INTR_FATAL_ERROR 0x40000000 65 #define IPW_INTR_PARITY_ERROR 0x80000000 66 67 #define IPW_INTR_MASK \ 68 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 69 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 70 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 71 IPW_INTR_PARITY_ERROR) 72 73 /* possible flags for register IPW_CSR_RST */ 74 #define IPW_RST_PRINCETON_RESET 0x00000001 75 #define IPW_RST_SW_RESET 0x00000080 76 #define IPW_RST_MASTER_DISABLED 0x00000100 77 #define IPW_RST_STOP_MASTER 0x00000200 78 79 /* possible flags for register IPW_CSR_CTL */ 80 #define IPW_CTL_CLOCK_READY 0x00000001 81 #define IPW_CTL_ALLOW_STANDBY 0x00000002 82 #define IPW_CTL_INIT_DONE 0x00000004 83 84 /* possible flags for register IPW_CSR_IO */ 85 #define IPW_IO_GPIO1_ENABLE 0x00000008 86 #define IPW_IO_GPIO1_MASK 0x0000000c 87 #define IPW_IO_GPIO3_MASK 0x000000c0 88 #define IPW_IO_LED_OFF 0x00002000 89 #define IPW_IO_RADIO_DISABLED 0x00010000 90 91 #define IPW_STATE_ASSOCIATED 0x0004 92 #define IPW_STATE_ASSOCIATION_LOST 0x0008 93 #define IPW_STATE_SCAN_COMPLETE 0x0020 94 #define IPW_STATE_RADIO_DISABLED 0x0100 95 #define IPW_STATE_DISABLED 0x0200 96 #define IPW_STATE_SCANNING 0x0800 97 98 /* table1 offsets */ 99 #define IPW_INFO_LOCK 480 100 #define IPW_INFO_CARD_DISABLED 628 101 #define IPW_INFO_CURRENT_CHANNEL 756 102 #define IPW_INFO_CURRENT_TX_RATE 768 103 #define IPW_INFO_EEPROM_ADDRESS 816 104 105 /* table2 offsets */ 106 #define IPW_INFO_ADAPTER_MAC 8 107 #define IPW_INFO_CURRENT_SSID 48 108 #define IPW_INFO_CURRENT_BSSID 112 109 110 /* firmware binary image header */ 111 struct ipw_fw_hdr { 112 u_int32_t version; 113 u_int32_t fw_size; /* firmware size */ 114 u_int32_t uc_size; /* microcode size */ 115 } __attribute__((__packed__)); 116 117 /* buffer descriptor */ 118 struct ipw_bd { 119 u_int32_t physaddr; 120 u_int32_t len; 121 u_int8_t flags; 122 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 123 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 124 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 125 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 126 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 127 u_int8_t nfrag; /* number of fragments */ 128 u_int8_t reserved[6]; 129 } __attribute__((__packed__)); 130 131 /* status */ 132 struct ipw_status { 133 u_int32_t len; 134 u_int16_t code; 135 #define IPW_STATUS_CODE_COMMAND 0 136 #define IPW_STATUS_CODE_NEWSTATE 1 137 #define IPW_STATUS_CODE_DATA_802_11 2 138 #define IPW_STATUS_CODE_DATA_802_3 3 139 #define IPW_STATUS_CODE_NOTIFICATION 4 140 u_int8_t flags; 141 #define IPW_STATUS_FLAG_DECRYPTED 0x01 142 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 143 u_int8_t rssi; /* received signal strength indicator */ 144 } __attribute__((__packed__)); 145 146 /* data header */ 147 struct ipw_hdr { 148 u_int32_t type; 149 #define IPW_HDR_TYPE_SEND 33 150 u_int32_t subtype; 151 u_int8_t encrypted; 152 u_int8_t encrypt; 153 u_int8_t keyidx; 154 u_int8_t keysz; 155 u_int8_t key[IEEE80211_KEYBUF_SIZE]; 156 u_int8_t reserved[10]; 157 u_int8_t src_addr[IEEE80211_ADDR_LEN]; 158 u_int8_t dst_addr[IEEE80211_ADDR_LEN]; 159 u_int16_t fragmentsz; 160 } __attribute__((__packed__)); 161 162 /* command */ 163 struct ipw_cmd { 164 u_int32_t type; 165 #define IPW_CMD_ENABLE 2 166 #define IPW_CMD_SET_CONFIGURATION 6 167 #define IPW_CMD_SET_ESSID 8 168 #define IPW_CMD_SET_MANDATORY_BSSID 9 169 #define IPW_CMD_SET_MAC_ADDRESS 11 170 #define IPW_CMD_SET_MODE 12 171 #define IPW_CMD_SET_CHANNEL 14 172 #define IPW_CMD_SET_RTS_THRESHOLD 15 173 #define IPW_CMD_SET_FRAG_THRESHOLD 16 174 #define IPW_CMD_SET_POWER_MODE 17 175 #define IPW_CMD_SET_TX_RATES 18 176 #define IPW_CMD_SET_BASIC_TX_RATES 19 177 #define IPW_CMD_SET_WEP_KEY 20 178 #define IPW_CMD_SET_WEP_KEY_INDEX 25 179 #define IPW_CMD_SET_WEP_FLAGS 26 180 #define IPW_CMD_ADD_MULTICAST 27 181 #define IPW_CMD_SET_BEACON_INTERVAL 29 182 #define IPW_CMD_SET_TX_POWER_INDEX 36 183 #define IPW_CMD_BROADCAST_SCAN 43 184 #define IPW_CMD_DISABLE 44 185 #define IPW_CMD_SET_DESIRED_BSSID 45 186 #define IPW_CMD_SET_SCAN_OPTIONS 46 187 #define IPW_CMD_PREPARE_POWER_DOWN 58 188 #define IPW_CMD_DISABLE_PHY 61 189 #define IPW_CMD_SET_SECURITY_INFORMATION 67 190 u_int32_t subtype; 191 u_int32_t seq; 192 u_int32_t len; 193 u_int8_t data[400]; 194 u_int32_t status; 195 u_int8_t reserved[68]; 196 } __attribute__((__packed__)); 197 198 /* possible values for command IPW_CMD_SET_POWER_MODE */ 199 #define IPW_POWER_MODE_CAM 0 200 #define IPW_POWER_AUTOMATIC 6 201 202 /* possible values for command IPW_CMD_SET_MODE */ 203 #define IPW_MODE_BSS 0 204 #define IPW_MODE_IBSS 1 205 #define IPW_MODE_MONITOR 2 206 207 /* structure for command IPW_CMD_SET_WEP_KEY */ 208 struct ipw_wep_key { 209 u_int8_t idx; 210 u_int8_t len; 211 u_int8_t key[13]; 212 } __attribute__((__packed__)); 213 214 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 215 struct ipw_security { 216 u_int32_t ciphers; 217 #define IPW_CIPHER_NONE 0x00000001 218 #define IPW_CIPHER_WEP40 0x00000002 219 #define IPW_CIPHER_WEP104 0x00000020 220 u_int16_t version; 221 u_int8_t authmode; 222 #define IPW_AUTH_OPEN 0 223 #define IPW_AUTH_SHARED 1 224 u_int8_t replay_counters_number; 225 u_int8_t unicast_using_group; 226 } __attribute__((__packed__)); 227 228 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 229 struct ipw_scan_options { 230 u_int32_t flags; 231 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 232 #define IPW_SCAN_PASSIVE 0x00000008 233 u_int32_t channels; 234 } __attribute__((__packed__)); 235 236 /* structure for command IPW_CMD_SET_CONFIGURATION */ 237 struct ipw_configuration { 238 u_int32_t flags; 239 #define IPW_CFG_PROMISCUOUS 0x00000004 240 #define IPW_CFG_PREAMBLE_LEN 0x00000010 241 #define IPW_CFG_IBSS_AUTO_START 0x00000020 242 #define IPW_CFG_802_1x_ENABLE 0x00004000 243 #define IPW_CFG_BSS_MASK 0x00008000 244 #define IPW_CFG_IBSS_MASK 0x00010000 245 u_int32_t channels; 246 u_int32_t ibss_chan; 247 } __attribute__((__packed__)); 248 249 /* 250 * control and status registers access macros 251 */ 252 #define CSR_READ_1(sc, reg) \ 253 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 254 255 #define CSR_READ_2(sc, reg) \ 256 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 257 258 #define CSR_READ_4(sc, reg) \ 259 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 260 261 #define CSR_WRITE_1(sc, reg, val) \ 262 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 263 264 #define CSR_WRITE_2(sc, reg, val) \ 265 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 266 267 #define CSR_WRITE_4(sc, reg, val) \ 268 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 269 270 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 271 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 272 (buf), (len)); 273 274 /* 275 * indirect memory space access macros 276 */ 277 278 #define MEM_WRITE_1(sc, addr, val) do { \ 279 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 280 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 281 } while (/* CONSTCOND */0) 282 283 #define MEM_WRITE_2(sc, addr, val) do { \ 284 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 285 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 286 } while (/* CONSTCOND */0) 287 288 #define MEM_WRITE_4(sc, addr, val) do { \ 289 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 290 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 291 } while (/* CONSTCOND */0) 292 293 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 294 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 295 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 296 } while (/* CONSTCOND */0) 297
Indexes created Thu Oct 02 14:10:14 GMT 2025