if_ipwreg.h revision 1.3
1 /* $NetBSD: if_ipwreg.h,v 1.3 2004/09/14 00:27:26 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IPW_NTBD 256 31 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 32 #define IPW_NDATA (IPW_NTBD / 2) 33 #define IPW_NRBD 256 34 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 35 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 36 37 #define IPW_CSR_INTR 0x0008 38 #define IPW_CSR_INTR_MASK 0x000c 39 #define IPW_CSR_INDIRECT_ADDR 0x0010 40 #define IPW_CSR_INDIRECT_DATA 0x0014 41 #define IPW_CSR_AUTOINC_ADDR 0x0018 42 #define IPW_CSR_AUTOINC_DATA 0x001c 43 #define IPW_CSR_RST 0x0020 44 #define IPW_CSR_CTL 0x0024 45 #define IPW_CSR_IO 0x0030 46 #define IPW_CSR_TABLE1_BASE 0x0380 47 #define IPW_CSR_TABLE2_BASE 0x0384 48 #define IPW_CSR_RX_BD_BASE 0x0240 49 #define IPW_CSR_RX_STATUS_BASE 0x0244 50 #define IPW_CSR_RX_BD_SIZE 0x0248 51 #define IPW_CSR_RX_READ_INDEX 0x02a0 52 #define IPW_CSR_RX_WRITE_INDEX 0x0fa0 53 #define IPW_CSR_TX_BD_BASE 0x0200 54 #define IPW_CSR_TX_BD_SIZE 0x0204 55 #define IPW_CSR_TX_READ_INDEX 0x0280 56 #define IPW_CSR_TX_WRITE_INDEX 0x0f80 57 58 #define IPW_INTR_TX_TRANSFER 0x00000001 59 #define IPW_INTR_RX_TRANSFER 0x00000002 60 #define IPW_INTR_STATUS_CHANGE 0x00000010 61 #define IPW_INTR_COMMAND_DONE 0x00010000 62 #define IPW_INTR_FW_INIT_DONE 0x01000000 63 #define IPW_INTR_FATAL_ERROR 0x40000000 64 #define IPW_INTR_PARITY_ERROR 0x80000000 65 66 #define IPW_INTR_MASK \ 67 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 68 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 69 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 70 IPW_INTR_PARITY_ERROR) 71 72 /* possible flags for register IPW_CSR_RST */ 73 #define IPW_RST_PRINCETON_RESET 0x00000001 74 #define IPW_RST_SW_RESET 0x00000080 75 #define IPW_RST_MASTER_DISABLED 0x00000100 76 #define IPW_RST_STOP_MASTER 0x00000200 77 78 /* possible flags for register IPW_CSR_CTL */ 79 #define IPW_CTL_CLOCK_READY 0x00000001 80 #define IPW_CTL_ALLOW_STANDBY 0x00000002 81 #define IPW_CTL_INIT_DONE 0x00000004 82 83 /* possible flags for register IPW_CSR_IO */ 84 #define IPW_IO_GPIO1_ENABLE 0x00000008 85 #define IPW_IO_GPIO1_MASK 0x0000000c 86 #define IPW_IO_GPIO3_MASK 0x000000c0 87 #define IPW_IO_LED_OFF 0x00002000 88 #define IPW_IO_RADIO_DISABLED 0x00010000 89 90 #define IPW_STATE_ASSOCIATED 0x0004 91 #define IPW_STATE_ASSOCIATION_LOST 0x0008 92 #define IPW_STATE_SCAN_COMPLETE 0x0020 93 #define IPW_STATE_RADIO_DISABLED 0x0100 94 #define IPW_STATE_DISABLED 0x0200 95 #define IPW_STATE_SCANNING 0x0800 96 97 /* table1 offsets */ 98 #define IPW_INFO_LOCK 480 99 #define IPW_INFO_CARD_DISABLED 628 100 #define IPW_INFO_CURRENT_CHANNEL 756 101 #define IPW_INFO_CURRENT_TX_RATE 768 102 #define IPW_INFO_EEPROM_ADDRESS 816 103 104 /* table2 offsets */ 105 #define IPW_INFO_ADAPTER_MAC 8 106 #define IPW_INFO_CURRENT_SSID 48 107 #define IPW_INFO_CURRENT_BSSID 112 108 109 /* firmware binary image header */ 110 struct ipw_fw_hdr { 111 u_int32_t version; 112 u_int32_t fw_size; /* firmware size */ 113 u_int32_t uc_size; /* microcode size */ 114 } __attribute__((__packed__)); 115 116 /* buffer descriptor */ 117 struct ipw_bd { 118 u_int32_t physaddr; 119 u_int32_t len; 120 u_int8_t flags; 121 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 122 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 123 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 124 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 125 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 126 u_int8_t nfrag; /* number of fragments */ 127 u_int8_t reserved[6]; 128 } __attribute__((__packed__)); 129 130 /* status */ 131 struct ipw_status { 132 u_int32_t len; 133 u_int16_t code; 134 #define IPW_STATUS_CODE_COMMAND 0 135 #define IPW_STATUS_CODE_NEWSTATE 1 136 #define IPW_STATUS_CODE_DATA_802_11 2 137 #define IPW_STATUS_CODE_DATA_802_3 3 138 #define IPW_STATUS_CODE_NOTIFICATION 4 139 u_int8_t flags; 140 #define IPW_STATUS_FLAG_DECRYPTED 0x01 141 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 142 u_int8_t rssi; /* received signal strength indicator */ 143 } __attribute__((__packed__)); 144 145 /* data header */ 146 struct ipw_hdr { 147 u_int32_t type; 148 #define IPW_HDR_TYPE_SEND 33 149 u_int32_t subtype; 150 u_int8_t encrypted; 151 u_int8_t encrypt; 152 u_int8_t keyidx; 153 u_int8_t keysz; 154 u_int8_t key[IEEE80211_KEYBUF_SIZE]; 155 u_int8_t reserved[10]; 156 u_int8_t src_addr[IEEE80211_ADDR_LEN]; 157 u_int8_t dst_addr[IEEE80211_ADDR_LEN]; 158 u_int16_t fragmentsz; 159 } __attribute__((__packed__)); 160 161 /* command */ 162 struct ipw_cmd { 163 u_int32_t type; 164 #define IPW_CMD_ENABLE 2 165 #define IPW_CMD_SET_CONFIGURATION 6 166 #define IPW_CMD_SET_ESSID 8 167 #define IPW_CMD_SET_MANDATORY_BSSID 9 168 #define IPW_CMD_SET_MAC_ADDRESS 11 169 #define IPW_CMD_SET_MODE 12 170 #define IPW_CMD_SET_CHANNEL 14 171 #define IPW_CMD_SET_RTS_THRESHOLD 15 172 #define IPW_CMD_SET_FRAG_THRESHOLD 16 173 #define IPW_CMD_SET_POWER_MODE 17 174 #define IPW_CMD_SET_TX_RATES 18 175 #define IPW_CMD_SET_BASIC_TX_RATES 19 176 #define IPW_CMD_SET_WEP_KEY 20 177 #define IPW_CMD_SET_WEP_KEY_INDEX 25 178 #define IPW_CMD_SET_WEP_FLAGS 26 179 #define IPW_CMD_ADD_MULTICAST 27 180 #define IPW_CMD_SET_BEACON_INTERVAL 29 181 #define IPW_CMD_SET_TX_POWER_INDEX 36 182 #define IPW_CMD_BROADCAST_SCAN 43 183 #define IPW_CMD_DISABLE 44 184 #define IPW_CMD_SET_DESIRED_BSSID 45 185 #define IPW_CMD_SET_SCAN_OPTIONS 46 186 #define IPW_CMD_PREPARE_POWER_DOWN 58 187 #define IPW_CMD_DISABLE_PHY 61 188 #define IPW_CMD_SET_SECURITY_INFORMATION 67 189 u_int32_t subtype; 190 u_int32_t seq; 191 u_int32_t len; 192 u_int8_t data[400]; 193 u_int32_t status; 194 u_int8_t reserved[68]; 195 } __attribute__((__packed__)); 196 197 /* possible values for command IPW_CMD_SET_POWER_MODE */ 198 #define IPW_POWER_MODE_CAM 0 199 #define IPW_POWER_AUTOMATIC 6 200 201 /* possible values for command IPW_CMD_SET_MODE */ 202 #define IPW_MODE_BSS 0 203 #define IPW_MODE_IBSS 1 204 #define IPW_MODE_MONITOR 2 205 206 /* structure for command IPW_CMD_SET_WEP_KEY */ 207 struct ipw_wep_key { 208 u_int8_t idx; 209 u_int8_t len; 210 u_int8_t key[13]; 211 } __attribute__((__packed__)); 212 213 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 214 struct ipw_security { 215 u_int32_t ciphers; 216 #define IPW_CIPHER_NONE 0x00000001 217 #define IPW_CIPHER_WEP40 0x00000002 218 #define IPW_CIPHER_WEP104 0x00000020 219 u_int16_t version; 220 u_int8_t authmode; 221 #define IPW_AUTH_OPEN 0 222 #define IPW_AUTH_SHARED 1 223 u_int8_t replay_counters_number; 224 u_int8_t unicast_using_group; 225 } __attribute__((__packed__)); 226 227 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 228 struct ipw_scan_options { 229 u_int32_t flags; 230 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 231 #define IPW_SCAN_PASSIVE 0x00000008 232 u_int32_t channels; 233 } __attribute__((__packed__)); 234 235 /* structure for command IPW_CMD_SET_CONFIGURATION */ 236 struct ipw_configuration { 237 u_int32_t flags; 238 #define IPW_CFG_PROMISCUOUS 0x00000004 239 #define IPW_CFG_PREAMBLE_LEN 0x00000010 240 #define IPW_CFG_IBSS_AUTO_START 0x00000020 241 #define IPW_CFG_802_1x_ENABLE 0x00004000 242 #define IPW_CFG_BSS_MASK 0x00008000 243 #define IPW_CFG_IBSS_MASK 0x00010000 244 u_int32_t channels; 245 u_int32_t ibss_chan; 246 } __attribute__((__packed__)); 247 248 /* 249 * control and status registers access macros 250 */ 251 #define CSR_READ_1(sc, reg) \ 252 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 253 254 #define CSR_READ_2(sc, reg) \ 255 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 256 257 #define CSR_READ_4(sc, reg) \ 258 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 259 260 #define CSR_WRITE_1(sc, reg, val) \ 261 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 262 263 #define CSR_WRITE_2(sc, reg, val) \ 264 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 265 266 #define CSR_WRITE_4(sc, reg, val) \ 267 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 268 269 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 270 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 271 (buf), (len)); 272 273 /* 274 * indirect memory space access macros 275 */ 276 277 #define MEM_WRITE_1(sc, addr, val) do { \ 278 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 279 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 280 } while (/* CONSTCOND */0) 281 282 #define MEM_WRITE_2(sc, addr, val) do { \ 283 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 284 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 285 } while (/* CONSTCOND */0) 286 287 #define MEM_WRITE_4(sc, addr, val) do { \ 288 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 289 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 290 } while (/* CONSTCOND */0) 291 292 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 293 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 294 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 295 } while (/* CONSTCOND */0) 296
Indexes created Tue Sep 23 14:10:03 GMT 2025