if_iwireg.h revision 1.2.4.2
1 1.2.4.2 skrll /* $NetBSD: if_iwireg.h,v 1.2.4.2 2005/01/17 19:31:24 skrll Exp $ */ 2 1.2.4.2 skrll 3 1.2.4.2 skrll /*- 4 1.2.4.2 skrll * Copyright (c) 2004, 2005 5 1.2.4.2 skrll * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 1.2.4.2 skrll * 7 1.2.4.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.4.2 skrll * modification, are permitted provided that the following conditions 9 1.2.4.2 skrll * are met: 10 1.2.4.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.4.2 skrll * notice unmodified, this list of conditions, and the following 12 1.2.4.2 skrll * disclaimer. 13 1.2.4.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 14 1.2.4.2 skrll * notice, this list of conditions and the following disclaimer in the 15 1.2.4.2 skrll * documentation and/or other materials provided with the distribution. 16 1.2.4.2 skrll * 17 1.2.4.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 1.2.4.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 1.2.4.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 1.2.4.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 1.2.4.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 1.2.4.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 1.2.4.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.2.4.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 1.2.4.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 1.2.4.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 1.2.4.2 skrll * SUCH DAMAGE. 28 1.2.4.2 skrll */ 29 1.2.4.2 skrll 30 1.2.4.2 skrll #define IWI_TX_RING_SIZE 64 31 1.2.4.2 skrll #define IWI_CMD_RING_SIZE 16 32 1.2.4.2 skrll #define IWI_RX_RING_SIZE 32 33 1.2.4.2 skrll 34 1.2.4.2 skrll #define IWI_CSR_INTR 0x0008 35 1.2.4.2 skrll #define IWI_CSR_INTR_MASK 0x000c 36 1.2.4.2 skrll #define IWI_CSR_INDIRECT_ADDR 0x0010 37 1.2.4.2 skrll #define IWI_CSR_INDIRECT_DATA 0x0014 38 1.2.4.2 skrll #define IWI_CSR_AUTOINC_ADDR 0x0018 39 1.2.4.2 skrll #define IWI_CSR_AUTOINC_DATA 0x001c 40 1.2.4.2 skrll #define IWI_CSR_RST 0x0020 41 1.2.4.2 skrll #define IWI_CSR_CTL 0x0024 42 1.2.4.2 skrll #define IWI_CSR_IO 0x0030 43 1.2.4.2 skrll #define IWI_CSR_CMD_BASE 0x0200 44 1.2.4.2 skrll #define IWI_CSR_CMD_SIZE 0x0204 45 1.2.4.2 skrll #define IWI_CSR_TX1_BASE 0x0208 46 1.2.4.2 skrll #define IWI_CSR_TX1_SIZE 0x020c 47 1.2.4.2 skrll #define IWI_CSR_TX2_BASE 0x0210 48 1.2.4.2 skrll #define IWI_CSR_TX2_SIZE 0x0214 49 1.2.4.2 skrll #define IWI_CSR_TX3_BASE 0x0218 50 1.2.4.2 skrll #define IWI_CSR_TX3_SIZE 0x021c 51 1.2.4.2 skrll #define IWI_CSR_TX4_BASE 0x0220 52 1.2.4.2 skrll #define IWI_CSR_TX4_SIZE 0x0224 53 1.2.4.2 skrll #define IWI_CSR_CMD_READ_INDEX 0x0280 54 1.2.4.2 skrll #define IWI_CSR_TX1_READ_INDEX 0x0284 55 1.2.4.2 skrll #define IWI_CSR_TX2_READ_INDEX 0x0288 56 1.2.4.2 skrll #define IWI_CSR_TX3_READ_INDEX 0x028c 57 1.2.4.2 skrll #define IWI_CSR_TX4_READ_INDEX 0x0290 58 1.2.4.2 skrll #define IWI_CSR_RX_READ_INDEX 0x02a0 59 1.2.4.2 skrll #define IWI_CSR_RX_BASE 0x0500 60 1.2.4.2 skrll #define IWI_CSR_TABLE0_SIZE 0x0700 61 1.2.4.2 skrll #define IWI_CSR_TABLE0_BASE 0x0704 62 1.2.4.2 skrll #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 63 1.2.4.2 skrll #define IWI_CSR_CMD_WRITE_INDEX 0x0f80 64 1.2.4.2 skrll #define IWI_CSR_TX1_WRITE_INDEX 0x0f84 65 1.2.4.2 skrll #define IWI_CSR_TX2_WRITE_INDEX 0x0f88 66 1.2.4.2 skrll #define IWI_CSR_TX3_WRITE_INDEX 0x0f8c 67 1.2.4.2 skrll #define IWI_CSR_TX4_WRITE_INDEX 0x0f90 68 1.2.4.2 skrll #define IWI_CSR_RX_WRITE_INDEX 0x0fa0 69 1.2.4.2 skrll #define IWI_CSR_READ_INT 0x0ff4 70 1.2.4.2 skrll 71 1.2.4.2 skrll /* possible flags for IWI_CSR_INTR */ 72 1.2.4.2 skrll #define IWI_INTR_RX_TRANSFER 0x00000002 73 1.2.4.2 skrll #define IWI_INTR_CMD_TRANSFER 0x00000800 74 1.2.4.2 skrll #define IWI_INTR_TX1_TRANSFER 0x00001000 75 1.2.4.2 skrll #define IWI_INTR_TX2_TRANSFER 0x00002000 76 1.2.4.2 skrll #define IWI_INTR_TX3_TRANSFER 0x00004000 77 1.2.4.2 skrll #define IWI_INTR_TX4_TRANSFER 0x00008000 78 1.2.4.2 skrll #define IWI_INTR_FW_INITED 0x01000000 79 1.2.4.2 skrll #define IWI_INTR_RADIO_OFF 0x04000000 80 1.2.4.2 skrll #define IWI_INTR_FATAL_ERROR 0x40000000 81 1.2.4.2 skrll #define IWI_INTR_PARITY_ERROR 0x80000000 82 1.2.4.2 skrll 83 1.2.4.2 skrll #define IWI_INTR_MASK \ 84 1.2.4.2 skrll (IWI_INTR_RX_TRANSFER | IWI_INTR_CMD_TRANSFER | \ 85 1.2.4.2 skrll IWI_INTR_TX1_TRANSFER | IWI_INTR_TX2_TRANSFER | \ 86 1.2.4.2 skrll IWI_INTR_TX3_TRANSFER | IWI_INTR_TX4_TRANSFER | \ 87 1.2.4.2 skrll IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 88 1.2.4.2 skrll IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 89 1.2.4.2 skrll 90 1.2.4.2 skrll /* possible flags for register IWI_CSR_RST */ 91 1.2.4.2 skrll #define IWI_RST_PRINCETON_RESET 0x00000001 92 1.2.4.2 skrll #define IWI_RST_SW_RESET 0x00000080 93 1.2.4.2 skrll #define IWI_RST_MASTER_DISABLED 0x00000100 94 1.2.4.2 skrll #define IWI_RST_STOP_MASTER 0x00000200 95 1.2.4.2 skrll 96 1.2.4.2 skrll /* possible flags for register IWI_CSR_CTL */ 97 1.2.4.2 skrll #define IWI_CTL_CLOCK_READY 0x00000001 98 1.2.4.2 skrll #define IWI_CTL_ALLOW_STANDBY 0x00000002 99 1.2.4.2 skrll #define IWI_CTL_INIT 0x00000004 100 1.2.4.2 skrll 101 1.2.4.2 skrll /* possible flags for register IWI_CSR_IO */ 102 1.2.4.2 skrll #define IWI_IO_RADIO_ENABLED 0x00010000 103 1.2.4.2 skrll 104 1.2.4.2 skrll /* possible flags for IWI_CSR_READ_INT */ 105 1.2.4.2 skrll #define IWI_READ_INT_INIT_HOST 0x20000000 106 1.2.4.2 skrll 107 1.2.4.2 skrll /* table2 offsets */ 108 1.2.4.2 skrll #define IWI_INFO_ADAPTER_MAC 40 109 1.2.4.2 skrll 110 1.2.4.2 skrll /* constants for command blocks */ 111 1.2.4.2 skrll #define IWI_CB_DEFAULT_CTL 0x8cea0000 112 1.2.4.2 skrll #define IWI_CB_MAXDATALEN 8191 113 1.2.4.2 skrll 114 1.2.4.2 skrll /* supported rates */ 115 1.2.4.2 skrll #define IWI_RATE_DS1 10 116 1.2.4.2 skrll #define IWI_RATE_DS2 20 117 1.2.4.2 skrll #define IWI_RATE_DS5 55 118 1.2.4.2 skrll #define IWI_RATE_DS11 110 119 1.2.4.2 skrll #define IWI_RATE_OFDM6 13 120 1.2.4.2 skrll #define IWI_RATE_OFDM9 15 121 1.2.4.2 skrll #define IWI_RATE_OFDM12 5 122 1.2.4.2 skrll #define IWI_RATE_OFDM18 7 123 1.2.4.2 skrll #define IWI_RATE_OFDM24 9 124 1.2.4.2 skrll #define IWI_RATE_OFDM36 11 125 1.2.4.2 skrll #define IWI_RATE_OFDM48 1 126 1.2.4.2 skrll #define IWI_RATE_OFDM54 3 127 1.2.4.2 skrll 128 1.2.4.2 skrll struct iwi_hdr { 129 1.2.4.2 skrll u_int8_t type; 130 1.2.4.2 skrll #define IWI_HDR_TYPE_DATA 0 131 1.2.4.2 skrll #define IWI_HDR_TYPE_COMMAND 1 132 1.2.4.2 skrll #define IWI_HDR_TYPE_NOTIF 3 133 1.2.4.2 skrll #define IWI_HDR_TYPE_FRAME 9 134 1.2.4.2 skrll u_int8_t seq; 135 1.2.4.2 skrll u_int8_t flags; 136 1.2.4.2 skrll #define IWI_HDR_FLAG_IRQ 0x04 137 1.2.4.2 skrll u_int8_t reserved; 138 1.2.4.2 skrll } __attribute__((__packed__)); 139 1.2.4.2 skrll 140 1.2.4.2 skrll struct iwi_notif { 141 1.2.4.2 skrll u_int32_t reserved[2]; 142 1.2.4.2 skrll u_int8_t type; 143 1.2.4.2 skrll #define IWI_NOTIF_TYPE_ASSOCIATION 10 144 1.2.4.2 skrll #define IWI_NOTIF_TYPE_AUTHENTICATION 11 145 1.2.4.2 skrll #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 146 1.2.4.2 skrll #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 147 1.2.4.2 skrll #define IWI_NOTIF_TYPE_BEACON 17 148 1.2.4.2 skrll #define IWI_NOTIF_TYPE_CALIBRATION 20 149 1.2.4.2 skrll #define IWI_NOTIF_TYPE_NOISE 25 150 1.2.4.2 skrll u_int8_t flags; 151 1.2.4.2 skrll u_int16_t len; 152 1.2.4.2 skrll } __attribute__((__packed__)); 153 1.2.4.2 skrll 154 1.2.4.2 skrll /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 155 1.2.4.2 skrll struct iwi_notif_authentication { 156 1.2.4.2 skrll u_int8_t state; 157 1.2.4.2 skrll #define IWI_DEAUTHENTICATED 0 158 1.2.4.2 skrll #define IWI_AUTHENTICATED 9 159 1.2.4.2 skrll } __attribute__((__packed__)); 160 1.2.4.2 skrll 161 1.2.4.2 skrll /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 162 1.2.4.2 skrll struct iwi_notif_association { 163 1.2.4.2 skrll u_int8_t state; 164 1.2.4.2 skrll #define IWI_DEASSOCIATED 0 165 1.2.4.2 skrll #define IWI_ASSOCIATED 12 166 1.2.4.2 skrll struct ieee80211_frame frame; 167 1.2.4.2 skrll u_int16_t capinfo; 168 1.2.4.2 skrll u_int16_t status; 169 1.2.4.2 skrll u_int16_t associd; 170 1.2.4.2 skrll } __attribute__((__packed__)); 171 1.2.4.2 skrll 172 1.2.4.2 skrll /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 173 1.2.4.2 skrll struct iwi_notif_scan_channel { 174 1.2.4.2 skrll u_int8_t nchan; 175 1.2.4.2 skrll u_int8_t reserved[47]; 176 1.2.4.2 skrll } __attribute__((__packed__)); 177 1.2.4.2 skrll 178 1.2.4.2 skrll /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 179 1.2.4.2 skrll struct iwi_notif_scan_complete { 180 1.2.4.2 skrll u_int8_t type; 181 1.2.4.2 skrll u_int8_t nchan; 182 1.2.4.2 skrll u_int8_t status; 183 1.2.4.2 skrll u_int8_t reserved; 184 1.2.4.2 skrll } __attribute__((__packed__)); 185 1.2.4.2 skrll 186 1.2.4.2 skrll /* received frame header */ 187 1.2.4.2 skrll struct iwi_frame { 188 1.2.4.2 skrll u_int32_t reserved1[2]; 189 1.2.4.2 skrll u_int8_t chan; 190 1.2.4.2 skrll u_int8_t status; 191 1.2.4.2 skrll u_int8_t rate; 192 1.2.4.2 skrll u_int8_t rssi; /* receiver signal strength indicator */ 193 1.2.4.2 skrll u_int8_t agc; /* automatic gain control */ 194 1.2.4.2 skrll u_int8_t rssi_dbm; 195 1.2.4.2 skrll u_int16_t signal; 196 1.2.4.2 skrll u_int16_t noise; 197 1.2.4.2 skrll u_int8_t antenna; 198 1.2.4.2 skrll u_int8_t control; 199 1.2.4.2 skrll u_int8_t reserved2[2]; 200 1.2.4.2 skrll u_int16_t len; 201 1.2.4.2 skrll } __attribute__((__packed__)); 202 1.2.4.2 skrll 203 1.2.4.2 skrll /* header for transmission */ 204 1.2.4.2 skrll struct iwi_tx_desc { 205 1.2.4.2 skrll struct iwi_hdr hdr; 206 1.2.4.2 skrll u_int32_t reserved1[2]; 207 1.2.4.2 skrll u_int8_t cmd; 208 1.2.4.2 skrll #define IWI_DATA_CMD_TX 0x0b 209 1.2.4.2 skrll u_int8_t seq; 210 1.2.4.2 skrll u_int16_t len; 211 1.2.4.2 skrll u_int8_t priority; 212 1.2.4.2 skrll u_int8_t flags; 213 1.2.4.2 skrll #define IWI_DATA_FLAG_SHPREAMBLE 0x04 214 1.2.4.2 skrll #define IWI_DATA_FLAG_NO_WEP 0x20 215 1.2.4.2 skrll #define IWI_DATA_FLAG_NEED_ACK 0x80 216 1.2.4.2 skrll u_int8_t xflags; 217 1.2.4.2 skrll u_int8_t wep_txkey; 218 1.2.4.2 skrll u_int8_t wepkey[IEEE80211_KEYBUF_SIZE]; 219 1.2.4.2 skrll u_int8_t rate; 220 1.2.4.2 skrll u_int8_t antenna; 221 1.2.4.2 skrll u_int8_t reserved2[10]; 222 1.2.4.2 skrll 223 1.2.4.2 skrll struct ieee80211_qosframe_addr4 wh; 224 1.2.4.2 skrll u_int32_t iv[2]; 225 1.2.4.2 skrll 226 1.2.4.2 skrll u_int32_t nseg; 227 1.2.4.2 skrll #define IWI_MAX_NSEG 6 228 1.2.4.2 skrll u_int32_t seg_addr[IWI_MAX_NSEG]; 229 1.2.4.2 skrll u_int16_t seg_len[IWI_MAX_NSEG]; 230 1.2.4.2 skrll } __attribute__((__packed__)); 231 1.2.4.2 skrll 232 1.2.4.2 skrll /* command */ 233 1.2.4.2 skrll struct iwi_cmd_desc { 234 1.2.4.2 skrll struct iwi_hdr hdr; 235 1.2.4.2 skrll u_int8_t type; 236 1.2.4.2 skrll #define IWI_CMD_ENABLE 2 237 1.2.4.2 skrll #define IWI_CMD_SET_CONFIGURATION 6 238 1.2.4.2 skrll #define IWI_CMD_SET_ESSID 8 239 1.2.4.2 skrll #define IWI_CMD_SET_MAC_ADDRESS 11 240 1.2.4.2 skrll #define IWI_CMD_SET_RTS_THRESHOLD 15 241 1.2.4.2 skrll #define IWI_CMD_SET_POWER_MODE 17 242 1.2.4.2 skrll #define IWI_CMD_SET_WEP_KEY 18 243 1.2.4.2 skrll #define IWI_CMD_SCAN 20 244 1.2.4.2 skrll #define IWI_CMD_ASSOCIATE 21 245 1.2.4.2 skrll #define IWI_CMD_SET_RATES 22 246 1.2.4.2 skrll #define IWI_CMD_DISABLE 33 247 1.2.4.2 skrll #define IWI_CMD_SET_IV 34 248 1.2.4.2 skrll #define IWI_CMD_SET_TX_POWER 35 249 1.2.4.2 skrll #define IWI_CMD_SET_SENSITIVITY 42 250 1.2.4.2 skrll u_int8_t len; 251 1.2.4.2 skrll u_int16_t reserved; 252 1.2.4.2 skrll u_int8_t data[120]; 253 1.2.4.2 skrll } __attribute__((__packed__)); 254 1.2.4.2 skrll 255 1.2.4.2 skrll /* constants for 'mode' fields */ 256 1.2.4.2 skrll #define IWI_MODE_11A 0 257 1.2.4.2 skrll #define IWI_MODE_11B 1 258 1.2.4.2 skrll #define IWI_MODE_11G 2 259 1.2.4.2 skrll 260 1.2.4.2 skrll /* macro for command IWI_CMD_SET_SENSITIVITY */ 261 1.2.4.2 skrll #define IWI_RSSIDBM2RAW(rssi) ((rssi) - 112) 262 1.2.4.2 skrll 263 1.2.4.2 skrll /* possible values for command IWI_CMD_SET_POWER_MODE */ 264 1.2.4.2 skrll #define IWI_POWER_MODE_CAM 0 265 1.2.4.2 skrll 266 1.2.4.2 skrll /* structure for command IWI_CMD_SET_RATES */ 267 1.2.4.2 skrll struct iwi_rateset { 268 1.2.4.2 skrll u_int8_t mode; 269 1.2.4.2 skrll u_int8_t nrates; 270 1.2.4.2 skrll u_int8_t type; 271 1.2.4.2 skrll #define IWI_RATESET_TYPE_NEGOCIATED 0 272 1.2.4.2 skrll #define IWI_RATESET_TYPE_SUPPORTED 1 273 1.2.4.2 skrll u_int8_t reserved; 274 1.2.4.2 skrll u_int8_t rates[12]; 275 1.2.4.2 skrll } __attribute__((__packed__)); 276 1.2.4.2 skrll 277 1.2.4.2 skrll /* structure for command IWI_CMD_SET_TX_POWER */ 278 1.2.4.2 skrll struct iwi_txpower { 279 1.2.4.2 skrll u_int8_t nchan; 280 1.2.4.2 skrll u_int8_t mode; 281 1.2.4.2 skrll struct { 282 1.2.4.2 skrll u_int8_t chan; 283 1.2.4.2 skrll u_int8_t power; 284 1.2.4.2 skrll #define IWI_TXPOWER_MAX 20 285 1.2.4.2 skrll #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 286 1.2.4.2 skrll } __attribute__((__packed__)) chan[37]; 287 1.2.4.2 skrll } __attribute__((__packed__)); 288 1.2.4.2 skrll 289 1.2.4.2 skrll /* structure for command IWI_CMD_ASSOCIATE */ 290 1.2.4.2 skrll struct iwi_associate { 291 1.2.4.2 skrll u_int8_t chan; 292 1.2.4.2 skrll u_int8_t auth; 293 1.2.4.2 skrll #define IWI_AUTH_OPEN 0 294 1.2.4.2 skrll #define IWI_AUTH_SHARED 1 295 1.2.4.2 skrll #define IWI_AUTH_NONE 3 296 1.2.4.2 skrll u_int8_t type; 297 1.2.4.2 skrll u_int8_t reserved1; 298 1.2.4.2 skrll u_int16_t reserved2; 299 1.2.4.2 skrll u_int8_t plen; 300 1.2.4.2 skrll u_int8_t mode; 301 1.2.4.2 skrll u_int8_t bssid[IEEE80211_ADDR_LEN]; 302 1.2.4.2 skrll u_int8_t tstamp[8]; 303 1.2.4.2 skrll u_int16_t capinfo; 304 1.2.4.2 skrll u_int16_t lintval; 305 1.2.4.2 skrll u_int16_t intval; 306 1.2.4.2 skrll u_int8_t dst[IEEE80211_ADDR_LEN]; 307 1.2.4.2 skrll u_int32_t reserved3; 308 1.2.4.2 skrll u_int16_t reserved4; 309 1.2.4.2 skrll } __attribute__((__packed__)); 310 1.2.4.2 skrll 311 1.2.4.2 skrll /* structure for command IWI_CMD_SCAN */ 312 1.2.4.2 skrll struct iwi_scan { 313 1.2.4.2 skrll u_int8_t type; 314 1.2.4.2 skrll #define IWI_SCAN_TYPE_BROADCAST 3 315 1.2.4.2 skrll u_int16_t intval; 316 1.2.4.2 skrll u_int8_t channels[54]; 317 1.2.4.2 skrll #define IWI_CHAN_5GHZ (0 << 6) 318 1.2.4.2 skrll #define IWI_CHAN_2GHZ (1 << 6) 319 1.2.4.2 skrll u_int8_t reserved[3]; 320 1.2.4.2 skrll } __attribute__((__packed__)); 321 1.2.4.2 skrll 322 1.2.4.2 skrll /* structure for command IWI_CMD_SET_CONFIGURATION */ 323 1.2.4.2 skrll struct iwi_configuration { 324 1.2.4.2 skrll u_int8_t bluetooth_coexistence; 325 1.2.4.2 skrll u_int8_t reserved1; 326 1.2.4.2 skrll u_int8_t answer_broadcast_probe_req; 327 1.2.4.2 skrll u_int8_t allow_invalid_frames; 328 1.2.4.2 skrll u_int8_t multicast_enabled; 329 1.2.4.2 skrll u_int8_t exclude_unicast_unencrypted; 330 1.2.4.2 skrll u_int8_t disable_unicast_decryption; 331 1.2.4.2 skrll u_int8_t exclude_multicast_unencrypted; 332 1.2.4.2 skrll u_int8_t disable_multicast_decryption; 333 1.2.4.2 skrll u_int8_t antenna; 334 1.2.4.2 skrll u_int8_t reserved2; 335 1.2.4.2 skrll u_int8_t bg_autodetection; 336 1.2.4.2 skrll u_int8_t reserved3; 337 1.2.4.2 skrll u_int8_t enable_multicast_filtering; 338 1.2.4.2 skrll u_int8_t bluetooth_threshold; 339 1.2.4.2 skrll u_int8_t reserved4; 340 1.2.4.2 skrll u_int8_t allow_beacon_and_probe_resp; 341 1.2.4.2 skrll u_int8_t allow_mgt; 342 1.2.4.2 skrll u_int8_t noise_reported; 343 1.2.4.2 skrll u_int8_t reserved5; 344 1.2.4.2 skrll } __attribute__((__packed__)); 345 1.2.4.2 skrll 346 1.2.4.2 skrll /* structure for command IWI_CMD_SET_WEP_KEY */ 347 1.2.4.2 skrll struct iwi_wep_key { 348 1.2.4.2 skrll u_int8_t cmd; 349 1.2.4.2 skrll #define IWI_WEP_KEY_CMD_SETKEY 0x08 350 1.2.4.2 skrll u_int8_t seq; 351 1.2.4.2 skrll u_int8_t idx; 352 1.2.4.2 skrll u_int8_t len; 353 1.2.4.2 skrll u_int8_t key[IEEE80211_KEYBUF_SIZE]; 354 1.2.4.2 skrll } __attribute__((__packed__)); 355 1.2.4.2 skrll 356 1.2.4.2 skrll /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 357 1.2.4.2 skrll 358 1.2.4.2 skrll #define IWI_MEM_EEPROM_CTL 0x00300040 359 1.2.4.2 skrll 360 1.2.4.2 skrll #define IWI_EEPROM_MAC 0x21 361 1.2.4.2 skrll 362 1.2.4.2 skrll #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 363 1.2.4.2 skrll 364 1.2.4.2 skrll #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 365 1.2.4.2 skrll #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 366 1.2.4.2 skrll #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 367 1.2.4.2 skrll #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 368 1.2.4.2 skrll 369 1.2.4.2 skrll #define IWI_EEPROM_SHIFT_D 2 370 1.2.4.2 skrll #define IWI_EEPROM_SHIFT_Q 4 371 1.2.4.2 skrll 372 1.2.4.2 skrll /* 373 1.2.4.2 skrll * control and status registers access macros 374 1.2.4.2 skrll */ 375 1.2.4.2 skrll #define CSR_READ_1(sc, reg) \ 376 1.2.4.2 skrll bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 377 1.2.4.2 skrll 378 1.2.4.2 skrll #define CSR_READ_2(sc, reg) \ 379 1.2.4.2 skrll bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 380 1.2.4.2 skrll 381 1.2.4.2 skrll #define CSR_READ_4(sc, reg) \ 382 1.2.4.2 skrll bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 383 1.2.4.2 skrll 384 1.2.4.2 skrll #define CSR_READ_REGION_4(sc, offset, datap, count) \ 385 1.2.4.2 skrll bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 386 1.2.4.2 skrll (datap), (count)) 387 1.2.4.2 skrll 388 1.2.4.2 skrll #define CSR_WRITE_1(sc, reg, val) \ 389 1.2.4.2 skrll bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 390 1.2.4.2 skrll 391 1.2.4.2 skrll #define CSR_WRITE_2(sc, reg, val) \ 392 1.2.4.2 skrll bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 393 1.2.4.2 skrll 394 1.2.4.2 skrll #define CSR_WRITE_4(sc, reg, val) \ 395 1.2.4.2 skrll bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 396 1.2.4.2 skrll 397 1.2.4.2 skrll /* 398 1.2.4.2 skrll * indirect memory space access macros 399 1.2.4.2 skrll */ 400 1.2.4.2 skrll #define MEM_WRITE_1(sc, addr, val) do { \ 401 1.2.4.2 skrll CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 402 1.2.4.2 skrll CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 403 1.2.4.2 skrll } while (/* CONSTCOND */0) 404 1.2.4.2 skrll 405 1.2.4.2 skrll #define MEM_WRITE_2(sc, addr, val) do { \ 406 1.2.4.2 skrll CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 407 1.2.4.2 skrll CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 408 1.2.4.2 skrll } while (/* CONSTCOND */0) 409 1.2.4.2 skrll 410 1.2.4.2 skrll #define MEM_WRITE_4(sc, addr, val) do { \ 411 1.2.4.2 skrll CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 412 1.2.4.2 skrll CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 413 1.2.4.2 skrll } while (/* CONSTCOND */0) 414 1.2.4.2 skrll 415 1.2.4.2 skrll #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 416 1.2.4.2 skrll CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 417 1.2.4.2 skrll CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 418 1.2.4.2 skrll } while (/* CONSTCOND */0) 419 1.2.4.2 skrll 420 1.2.4.2 skrll /* 421 1.2.4.2 skrll * EEPROM access macro 422 1.2.4.2 skrll */ 423 1.2.4.2 skrll #define IWI_EEPROM_CTL(sc, val) do { \ 424 1.2.4.2 skrll MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 425 1.2.4.2 skrll DELAY(IWI_EEPROM_DELAY); \ 426 1.2.4.2 skrll } while (/* CONSTCOND */0) 427
Indexes created Sun Oct 19 16:10:00 GMT 2025