if_iwireg.h revision 1.1.1.1
1 /* $Id: if_iwireg.h,v 1.1.1.1 2005/01/11 18:24:24 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IWI_TX_RING_SIZE 64 31 #define IWI_CMD_RING_SIZE 16 32 #define IWI_RX_RING_SIZE 32 33 34 #define IWI_CSR_INTR 0x0008 35 #define IWI_CSR_INTR_MASK 0x000c 36 #define IWI_CSR_INDIRECT_ADDR 0x0010 37 #define IWI_CSR_INDIRECT_DATA 0x0014 38 #define IWI_CSR_AUTOINC_ADDR 0x0018 39 #define IWI_CSR_AUTOINC_DATA 0x001c 40 #define IWI_CSR_RST 0x0020 41 #define IWI_CSR_CTL 0x0024 42 #define IWI_CSR_IO 0x0030 43 #define IWI_CSR_CMD_BASE 0x0200 44 #define IWI_CSR_CMD_SIZE 0x0204 45 #define IWI_CSR_TX1_BASE 0x0208 46 #define IWI_CSR_TX1_SIZE 0x020c 47 #define IWI_CSR_TX2_BASE 0x0210 48 #define IWI_CSR_TX2_SIZE 0x0214 49 #define IWI_CSR_TX3_BASE 0x0218 50 #define IWI_CSR_TX3_SIZE 0x021c 51 #define IWI_CSR_TX4_BASE 0x0220 52 #define IWI_CSR_TX4_SIZE 0x0224 53 #define IWI_CSR_CMD_READ_INDEX 0x0280 54 #define IWI_CSR_TX1_READ_INDEX 0x0284 55 #define IWI_CSR_TX2_READ_INDEX 0x0288 56 #define IWI_CSR_TX3_READ_INDEX 0x028c 57 #define IWI_CSR_TX4_READ_INDEX 0x0290 58 #define IWI_CSR_RX_READ_INDEX 0x02a0 59 #define IWI_CSR_RX_BASE 0x0500 60 #define IWI_CSR_TABLE0_SIZE 0x0700 61 #define IWI_CSR_TABLE0_BASE 0x0704 62 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 63 #define IWI_CSR_CMD_WRITE_INDEX 0x0f80 64 #define IWI_CSR_TX1_WRITE_INDEX 0x0f84 65 #define IWI_CSR_TX2_WRITE_INDEX 0x0f88 66 #define IWI_CSR_TX3_WRITE_INDEX 0x0f8c 67 #define IWI_CSR_TX4_WRITE_INDEX 0x0f90 68 #define IWI_CSR_RX_WRITE_INDEX 0x0fa0 69 #define IWI_CSR_READ_INT 0x0ff4 70 71 /* possible flags for IWI_CSR_INTR */ 72 #define IWI_INTR_RX_TRANSFER 0x00000002 73 #define IWI_INTR_CMD_TRANSFER 0x00000800 74 #define IWI_INTR_TX1_TRANSFER 0x00001000 75 #define IWI_INTR_TX2_TRANSFER 0x00002000 76 #define IWI_INTR_TX3_TRANSFER 0x00004000 77 #define IWI_INTR_TX4_TRANSFER 0x00008000 78 #define IWI_INTR_FW_INITED 0x01000000 79 #define IWI_INTR_RADIO_OFF 0x04000000 80 #define IWI_INTR_FATAL_ERROR 0x40000000 81 #define IWI_INTR_PARITY_ERROR 0x80000000 82 83 #define IWI_INTR_MASK \ 84 (IWI_INTR_RX_TRANSFER | IWI_INTR_CMD_TRANSFER | \ 85 IWI_INTR_TX1_TRANSFER | IWI_INTR_TX2_TRANSFER | \ 86 IWI_INTR_TX3_TRANSFER | IWI_INTR_TX4_TRANSFER | \ 87 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 88 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 89 90 /* possible flags for register IWI_CSR_RST */ 91 #define IWI_RST_PRINCETON_RESET 0x00000001 92 #define IWI_RST_SW_RESET 0x00000080 93 #define IWI_RST_MASTER_DISABLED 0x00000100 94 #define IWI_RST_STOP_MASTER 0x00000200 95 96 /* possible flags for register IWI_CSR_CTL */ 97 #define IWI_CTL_CLOCK_READY 0x00000001 98 #define IWI_CTL_ALLOW_STANDBY 0x00000002 99 #define IWI_CTL_INIT 0x00000004 100 101 /* possible flags for register IWI_CSR_IO */ 102 #define IWI_IO_RADIO_ENABLED 0x00010000 103 104 /* possible flags for IWI_CSR_READ_INT */ 105 #define IWI_READ_INT_INIT_HOST 0x20000000 106 107 /* table2 offsets */ 108 #define IWI_INFO_ADAPTER_MAC 40 109 110 /* constants for command blocks */ 111 #define IWI_CB_DEFAULT_CTL 0x8cea0000 112 #define IWI_CB_MAXDATALEN 8191 113 114 /* supported rates */ 115 #define IWI_RATE_DS1 10 116 #define IWI_RATE_DS2 20 117 #define IWI_RATE_DS5 55 118 #define IWI_RATE_DS11 110 119 #define IWI_RATE_OFDM6 13 120 #define IWI_RATE_OFDM9 15 121 #define IWI_RATE_OFDM12 5 122 #define IWI_RATE_OFDM18 7 123 #define IWI_RATE_OFDM24 9 124 #define IWI_RATE_OFDM36 11 125 #define IWI_RATE_OFDM48 1 126 #define IWI_RATE_OFDM54 3 127 128 struct iwi_hdr { 129 u_int8_t type; 130 #define IWI_HDR_TYPE_DATA 0 131 #define IWI_HDR_TYPE_COMMAND 1 132 #define IWI_HDR_TYPE_NOTIF 3 133 #define IWI_HDR_TYPE_FRAME 9 134 u_int8_t seq; 135 u_int8_t flags; 136 #define IWI_HDR_FLAG_IRQ 0x04 137 u_int8_t reserved; 138 } __attribute__((__packed__)); 139 140 struct iwi_notif { 141 u_int32_t reserved[2]; 142 u_int8_t type; 143 #define IWI_NOTIF_TYPE_ASSOCIATION 10 144 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 145 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 146 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 147 #define IWI_NOTIF_TYPE_BEACON 17 148 #define IWI_NOTIF_TYPE_CALIBRATION 20 149 #define IWI_NOTIF_TYPE_NOISE 25 150 u_int8_t flags; 151 u_int16_t len; 152 } __attribute__((__packed__)); 153 154 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 155 struct iwi_notif_authentication { 156 u_int8_t state; 157 #define IWI_DEAUTHENTICATED 0 158 #define IWI_AUTHENTICATED 9 159 } __attribute__((__packed__)); 160 161 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 162 struct iwi_notif_association { 163 u_int8_t state; 164 #define IWI_DEASSOCIATED 0 165 #define IWI_ASSOCIATED 12 166 struct ieee80211_frame frame; 167 u_int16_t capinfo; 168 u_int16_t status; 169 u_int16_t associd; 170 } __attribute__((__packed__)); 171 172 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 173 struct iwi_notif_scan_channel { 174 u_int8_t nchan; 175 u_int8_t reserved[47]; 176 } __attribute__((__packed__)); 177 178 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 179 struct iwi_notif_scan_complete { 180 u_int8_t type; 181 u_int8_t nchan; 182 u_int8_t status; 183 u_int8_t reserved; 184 } __attribute__((__packed__)); 185 186 /* received frame header */ 187 struct iwi_frame { 188 u_int32_t reserved1[2]; 189 u_int8_t chan; 190 u_int8_t status; 191 u_int8_t rate; 192 u_int8_t rssi; /* receiver signal strength indicator */ 193 u_int8_t agc; /* automatic gain control */ 194 u_int8_t rssi_dbm; 195 u_int16_t signal; 196 u_int16_t noise; 197 u_int8_t antenna; 198 u_int8_t control; 199 u_int8_t reserved2[2]; 200 u_int16_t len; 201 } __attribute__((__packed__)); 202 203 /* header for transmission */ 204 struct iwi_tx_desc { 205 struct iwi_hdr hdr; 206 u_int32_t reserved1[2]; 207 u_int8_t cmd; 208 #define IWI_DATA_CMD_TX 0x0b 209 u_int8_t seq; 210 u_int16_t len; 211 u_int8_t priority; 212 u_int8_t flags; 213 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 214 #define IWI_DATA_FLAG_NO_WEP 0x20 215 #define IWI_DATA_FLAG_NEED_ACK 0x80 216 u_int8_t xflags; 217 u_int8_t wep_txkey; 218 u_int8_t wepkey[IEEE80211_KEYBUF_SIZE]; 219 u_int8_t rate; 220 u_int8_t antenna; 221 u_int8_t reserved2[10]; 222 223 struct ieee80211_qosframe_addr4 wh; 224 u_int32_t iv[2]; 225 226 u_int32_t nseg; 227 #define IWI_MAX_NSEG 6 228 u_int32_t seg_addr[IWI_MAX_NSEG]; 229 u_int16_t seg_len[IWI_MAX_NSEG]; 230 } __attribute__((__packed__)); 231 232 /* command */ 233 struct iwi_cmd_desc { 234 struct iwi_hdr hdr; 235 u_int8_t type; 236 #define IWI_CMD_ENABLE 2 237 #define IWI_CMD_SET_CONFIGURATION 6 238 #define IWI_CMD_SET_ESSID 8 239 #define IWI_CMD_SET_MAC_ADDRESS 11 240 #define IWI_CMD_SET_RTS_THRESHOLD 15 241 #define IWI_CMD_SET_POWER_MODE 17 242 #define IWI_CMD_SET_WEP_KEY 18 243 #define IWI_CMD_SCAN 20 244 #define IWI_CMD_ASSOCIATE 21 245 #define IWI_CMD_SET_RATES 22 246 #define IWI_CMD_DISABLE 33 247 #define IWI_CMD_SET_IV 34 248 #define IWI_CMD_SET_TX_POWER 35 249 #define IWI_CMD_SET_SENSITIVITY 42 250 u_int8_t len; 251 u_int16_t reserved; 252 u_int8_t data[120]; 253 } __attribute__((__packed__)); 254 255 /* constants for 'mode' fields */ 256 #define IWI_MODE_11A 0 257 #define IWI_MODE_11B 1 258 #define IWI_MODE_11G 2 259 260 /* macro for command IWI_CMD_SET_SENSITIVITY */ 261 #define IWI_RSSIDBM2RAW(rssi) ((rssi) - 112) 262 263 /* possible values for command IWI_CMD_SET_POWER_MODE */ 264 #define IWI_POWER_MODE_CAM 0 265 266 /* structure for command IWI_CMD_SET_RATES */ 267 struct iwi_rateset { 268 u_int8_t mode; 269 u_int8_t nrates; 270 u_int8_t type; 271 #define IWI_RATESET_TYPE_NEGOCIATED 0 272 #define IWI_RATESET_TYPE_SUPPORTED 1 273 u_int8_t reserved; 274 u_int8_t rates[12]; 275 } __attribute__((__packed__)); 276 277 /* structure for command IWI_CMD_SET_TX_POWER */ 278 struct iwi_txpower { 279 u_int8_t nchan; 280 u_int8_t mode; 281 struct { 282 u_int8_t chan; 283 u_int8_t power; 284 #define IWI_TXPOWER_MAX 20 285 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 286 } __attribute__((__packed__)) chan[37]; 287 } __attribute__((__packed__)); 288 289 /* structure for command IWI_CMD_ASSOCIATE */ 290 struct iwi_associate { 291 u_int8_t chan; 292 u_int8_t auth; 293 #define IWI_AUTH_OPEN 0 294 #define IWI_AUTH_SHARED 1 295 #define IWI_AUTH_NONE 3 296 u_int8_t type; 297 u_int8_t reserved1; 298 u_int16_t reserved2; 299 u_int8_t plen; 300 u_int8_t mode; 301 u_int8_t bssid[IEEE80211_ADDR_LEN]; 302 u_int8_t tstamp[8]; 303 u_int16_t capinfo; 304 u_int16_t lintval; 305 u_int16_t intval; 306 u_int8_t dst[IEEE80211_ADDR_LEN]; 307 u_int32_t reserved3; 308 u_int16_t reserved4; 309 } __attribute__((__packed__)); 310 311 /* structure for command IWI_CMD_SCAN */ 312 struct iwi_scan { 313 u_int8_t type; 314 #define IWI_SCAN_TYPE_BROADCAST 3 315 u_int16_t intval; 316 u_int8_t channels[54]; 317 #define IWI_CHAN_5GHZ (0 << 6) 318 #define IWI_CHAN_2GHZ (1 << 6) 319 u_int8_t reserved[3]; 320 } __attribute__((__packed__)); 321 322 /* structure for command IWI_CMD_SET_CONFIGURATION */ 323 struct iwi_configuration { 324 u_int8_t bluetooth_coexistence; 325 u_int8_t reserved1; 326 u_int8_t answer_broadcast_probe_req; 327 u_int8_t allow_invalid_frames; 328 u_int8_t multicast_enabled; 329 u_int8_t exclude_unicast_unencrypted; 330 u_int8_t disable_unicast_decryption; 331 u_int8_t exclude_multicast_unencrypted; 332 u_int8_t disable_multicast_decryption; 333 u_int8_t antenna; 334 u_int8_t reserved2; 335 u_int8_t bg_autodetection; 336 u_int8_t reserved3; 337 u_int8_t enable_multicast_filtering; 338 u_int8_t bluetooth_threshold; 339 u_int8_t reserved4; 340 u_int8_t allow_beacon_and_probe_resp; 341 u_int8_t allow_mgt; 342 u_int8_t noise_reported; 343 u_int8_t reserved5; 344 } __attribute__((__packed__)); 345 346 /* structure for command IWI_CMD_SET_WEP_KEY */ 347 struct iwi_wep_key { 348 u_int8_t cmd; 349 #define IWI_WEP_KEY_CMD_SETKEY 0x08 350 u_int8_t seq; 351 u_int8_t idx; 352 u_int8_t len; 353 u_int8_t key[IEEE80211_KEYBUF_SIZE]; 354 } __attribute__((__packed__)); 355 356 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 357 358 #define IWI_MEM_EEPROM_CTL 0x00300040 359 360 #define IWI_EEPROM_MAC 0x21 361 362 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 363 364 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 365 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 366 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 367 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 368 369 #define IWI_EEPROM_SHIFT_D 2 370 #define IWI_EEPROM_SHIFT_Q 4 371 372 /* 373 * control and status registers access macros 374 */ 375 #define CSR_READ_1(sc, reg) \ 376 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 377 378 #define CSR_READ_2(sc, reg) \ 379 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 380 381 #define CSR_READ_4(sc, reg) \ 382 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 383 384 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 385 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 386 (datap), (count)) 387 388 #define CSR_WRITE_1(sc, reg, val) \ 389 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 390 391 #define CSR_WRITE_2(sc, reg, val) \ 392 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 393 394 #define CSR_WRITE_4(sc, reg, val) \ 395 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 396 397 /* 398 * indirect memory space access macros 399 */ 400 #define MEM_WRITE_1(sc, addr, val) do { \ 401 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 402 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 403 } while (/* CONSTCOND */0) 404 405 #define MEM_WRITE_2(sc, addr, val) do { \ 406 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 407 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 408 } while (/* CONSTCOND */0) 409 410 #define MEM_WRITE_4(sc, addr, val) do { \ 411 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 412 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 413 } while (/* CONSTCOND */0) 414 415 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 416 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 417 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 418 } while (/* CONSTCOND */0) 419 420 /* 421 * EEPROM access macro 422 */ 423 #define IWI_EEPROM_CTL(sc, val) do { \ 424 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 425 DELAY(IWI_EEPROM_DELAY); \ 426 } while (/* CONSTCOND */0) 427
Indexes created Wed Oct 15 16:09:53 GMT 2025