if_iwireg.h revision 1.15
1 /* $NetBSD: if_iwireg.h,v 1.15 2005/11/29 13:57:00 rpaulo Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IWI_CMD_RING_COUNT 16 31 #define IWI_TX_RING_COUNT 64 32 #define IWI_RX_RING_COUNT 32 33 34 #define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) 35 #define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) 36 37 #define IWI_CSR_INTR 0x0008 38 #define IWI_CSR_INTR_MASK 0x000c 39 #define IWI_CSR_INDIRECT_ADDR 0x0010 40 #define IWI_CSR_INDIRECT_DATA 0x0014 41 #define IWI_CSR_AUTOINC_ADDR 0x0018 42 #define IWI_CSR_AUTOINC_DATA 0x001c 43 #define IWI_CSR_RST 0x0020 44 #define IWI_CSR_CTL 0x0024 45 #define IWI_CSR_IO 0x0030 46 #define IWI_CSR_CMD_BASE 0x0200 47 #define IWI_CSR_CMD_SIZE 0x0204 48 #define IWI_CSR_TX1_BASE 0x0208 49 #define IWI_CSR_TX1_SIZE 0x020c 50 #define IWI_CSR_TX2_BASE 0x0210 51 #define IWI_CSR_TX2_SIZE 0x0214 52 #define IWI_CSR_TX3_BASE 0x0218 53 #define IWI_CSR_TX3_SIZE 0x021c 54 #define IWI_CSR_TX4_BASE 0x0220 55 #define IWI_CSR_TX4_SIZE 0x0224 56 #define IWI_CSR_CMD_RIDX 0x0280 57 #define IWI_CSR_TX1_RIDX 0x0284 58 #define IWI_CSR_TX2_RIDX 0x0288 59 #define IWI_CSR_TX3_RIDX 0x028c 60 #define IWI_CSR_TX4_RIDX 0x0290 61 #define IWI_CSR_RX_RIDX 0x02a0 62 #define IWI_CSR_RX_BASE 0x0500 63 #define IWI_CSR_ERRORLOG 0x0610 64 #define IWI_CSR_TABLE0_SIZE 0x0700 65 #define IWI_CSR_TABLE0_BASE 0x0704 66 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 67 #define IWI_CSR_NODE_BASE 0x0c0c 68 #define IWI_CSR_CMD_WIDX 0x0f80 69 #define IWI_CSR_TX1_WIDX 0x0f84 70 #define IWI_CSR_TX2_WIDX 0x0f88 71 #define IWI_CSR_TX3_WIDX 0x0f8c 72 #define IWI_CSR_TX4_WIDX 0x0f90 73 #define IWI_CSR_RX_WIDX 0x0fa0 74 #define IWI_CSR_READ_INT 0x0ff4 75 76 /* possible flags for IWI_CSR_INTR */ 77 #define IWI_INTR_RX_DONE 0x00000002 78 #define IWI_INTR_CMD_DONE 0x00000800 79 #define IWI_INTR_TX1_DONE 0x00001000 80 #define IWI_INTR_TX2_DONE 0x00002000 81 #define IWI_INTR_TX3_DONE 0x00004000 82 #define IWI_INTR_TX4_DONE 0x00008000 83 #define IWI_INTR_FW_INITED 0x01000000 84 #define IWI_INTR_RADIO_OFF 0x04000000 85 #define IWI_INTR_FATAL_ERROR 0x40000000 86 #define IWI_INTR_PARITY_ERROR 0x80000000 87 88 #define IWI_INTR_MASK \ 89 (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | \ 90 IWI_INTR_TX1_DONE | IWI_INTR_TX2_DONE | \ 91 IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ 92 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 93 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 94 95 /* possible flags for register IWI_CSR_RST */ 96 #define IWI_RST_PRINCETON_RESET 0x00000001 97 #define IWI_RST_SW_RESET 0x00000080 98 #define IWI_RST_MASTER_DISABLED 0x00000100 99 #define IWI_RST_STOP_MASTER 0x00000200 100 101 /* possible flags for register IWI_CSR_CTL */ 102 #define IWI_CTL_CLOCK_READY 0x00000001 103 #define IWI_CTL_ALLOW_STANDBY 0x00000002 104 #define IWI_CTL_INIT 0x00000004 105 106 /* possible flags for register IWI_CSR_IO */ 107 #define IWI_IO_RADIO_ENABLED 0x00010000 108 109 /* possible flags for IWI_CSR_READ_INT */ 110 #define IWI_READ_INT_INIT_HOST 0x20000000 111 112 /* error log definitions */ 113 struct iwi_error { 114 uint32_t type; 115 uint32_t reserved2; 116 uint32_t reserved3; 117 uint32_t reserved4; 118 uint32_t reserved5; 119 uint32_t reserved6; 120 uint32_t reserved7; 121 } __attribute__((__packed__)); 122 123 /* table2 offsets */ 124 #define IWI_INFO_ADAPTER_MAC 40 125 126 /* constants for command blocks */ 127 #define IWI_CB_DEFAULT_CTL 0x8cea0000 128 #define IWI_CB_MAXDATALEN 8191 129 130 /* supported rates */ 131 #define IWI_RATE_DS1 10 132 #define IWI_RATE_DS2 20 133 #define IWI_RATE_DS5 55 134 #define IWI_RATE_DS11 110 135 #define IWI_RATE_OFDM6 13 136 #define IWI_RATE_OFDM9 15 137 #define IWI_RATE_OFDM12 5 138 #define IWI_RATE_OFDM18 7 139 #define IWI_RATE_OFDM24 9 140 #define IWI_RATE_OFDM36 11 141 #define IWI_RATE_OFDM48 1 142 #define IWI_RATE_OFDM54 3 143 144 struct iwi_hdr { 145 uint8_t type; 146 #define IWI_HDR_TYPE_DATA 0 147 #define IWI_HDR_TYPE_COMMAND 1 148 #define IWI_HDR_TYPE_NOTIF 3 149 #define IWI_HDR_TYPE_FRAME 9 150 151 uint8_t seq; 152 uint8_t flags; 153 #define IWI_HDR_FLAG_IRQ 0x04 154 155 uint8_t reserved; 156 } __attribute__((__packed__)); 157 158 struct iwi_notif { 159 uint32_t reserved[2]; 160 uint8_t type; 161 #define IWI_NOTIF_TYPE_ASSOCIATION 10 162 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 163 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 164 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 165 #define IWI_NOTIF_TYPE_BEACON 17 166 #define IWI_NOTIF_TYPE_CALIBRATION 20 167 #define IWI_NOTIF_TYPE_NOISE 25 168 169 uint8_t flags; 170 uint16_t len; 171 } __attribute__((__packed__)); 172 173 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 174 struct iwi_notif_authentication { 175 uint8_t state; 176 #define IWI_DEAUTHENTICATED 0 177 #define IWI_AUTHENTICATED 9 178 } __attribute__((__packed__)); 179 180 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 181 struct iwi_notif_association { 182 uint8_t state; 183 #define IWI_DEASSOCIATED 0 184 #define IWI_ASSOCIATED 12 185 186 struct ieee80211_frame frame; 187 uint16_t capinfo; 188 uint16_t status; 189 uint16_t associd; 190 } __attribute__((__packed__)); 191 192 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 193 struct iwi_notif_scan_channel { 194 uint8_t nchan; 195 uint8_t reserved[47]; 196 } __attribute__((__packed__)); 197 198 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 199 struct iwi_notif_scan_complete { 200 uint8_t type; 201 uint8_t nchan; 202 uint8_t status; 203 uint8_t reserved; 204 } __attribute__((__packed__)); 205 206 /* received frame header */ 207 struct iwi_frame { 208 uint32_t reserved1[2]; 209 uint8_t chan; 210 uint8_t status; 211 uint8_t rate; 212 uint8_t rssi; /* receiver signal strength indicator */ 213 uint8_t agc; /* automatic gain control */ 214 uint8_t rssi_dbm; 215 uint16_t signal; 216 uint16_t noise; 217 uint8_t antenna; 218 uint8_t control; 219 uint8_t reserved2[2]; 220 uint16_t len; 221 } __attribute__((__packed__)); 222 223 /* header for transmission */ 224 struct iwi_tx_desc { 225 struct iwi_hdr hdr; 226 uint32_t reserved1; 227 uint8_t station; 228 uint8_t reserved2[3]; 229 uint8_t cmd; 230 #define IWI_DATA_CMD_TX 0x0b 231 232 uint8_t seq; 233 uint16_t len; 234 uint8_t priority; 235 uint8_t flags; 236 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 237 #define IWI_DATA_FLAG_NO_WEP 0x20 238 #define IWI_DATA_FLAG_NEED_ACK 0x80 239 240 uint8_t xflags; 241 #define IWI_DATA_XFLAG_QOS 0x10 242 243 uint8_t wep_txkey; 244 uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 245 uint8_t rate; 246 uint8_t antenna; 247 uint8_t reserved3[10]; 248 struct ieee80211_qosframe_addr4 wh; 249 uint32_t iv; 250 uint32_t eiv; 251 uint32_t nseg; 252 #define IWI_MAX_NSEG 6 253 254 uint32_t seg_addr[IWI_MAX_NSEG]; 255 uint16_t seg_len[IWI_MAX_NSEG]; 256 } __attribute__((__packed__)); 257 258 /* command */ 259 struct iwi_cmd_desc { 260 struct iwi_hdr hdr; 261 uint8_t type; 262 #define IWI_CMD_ENABLE 2 263 #define IWI_CMD_SET_CONFIGURATION 6 264 #define IWI_CMD_SET_ESSID 8 265 #define IWI_CMD_SET_MAC_ADDRESS 11 266 #define IWI_CMD_SET_RTS_THRESHOLD 15 267 #define IWI_CMD_SET_FRAG_THRESHOLD 16 268 #define IWI_CMD_SET_POWER_MODE 17 269 #define IWI_CMD_SET_WEP_KEY 18 270 #define IWI_CMD_ASSOCIATE 21 271 #define IWI_CMD_SET_RATES 22 272 #define IWI_CMD_ABORT_SCAN 23 273 #define IWI_CMD_SET_WME_PARAMS 25 274 #define IWI_CMD_SCAN_V2 26 275 #define IWI_CMD_SET_OPTIE 31 276 #define IWI_CMD_DISABLE 33 277 #define IWI_CMD_SET_IV 34 278 #define IWI_CMD_SET_TX_POWER 35 279 #define IWI_CMD_SET_SENSITIVITY 42 280 #define IWI_CMD_SET_WMEIE 84 281 282 uint8_t len; 283 uint16_t reserved; 284 uint8_t data[120]; 285 } __attribute__((__packed__)); 286 287 /* node information (IBSS) */ 288 struct iwi_ibssnode { 289 uint8_t bssid[IEEE80211_ADDR_LEN]; 290 uint8_t reserved[2]; 291 } __packed; 292 293 /* constants for 'mode' fields */ 294 #define IWI_MODE_11A 0 295 #define IWI_MODE_11B 1 296 #define IWI_MODE_11G 2 297 298 /* possible values for command IWI_CMD_SET_POWER_MODE */ 299 #define IWI_POWER_MODE_CAM 0 300 301 /* structure for command IWI_CMD_SET_RATES */ 302 struct iwi_rateset { 303 uint8_t mode; 304 uint8_t nrates; 305 uint8_t type; 306 #define IWI_RATESET_TYPE_NEGOTIATED 0 307 #define IWI_RATESET_TYPE_SUPPORTED 1 308 309 uint8_t reserved; 310 uint8_t rates[12]; 311 } __attribute__((__packed__)); 312 313 /* structure for command IWI_CMD_SET_TX_POWER */ 314 struct iwi_txpower { 315 uint8_t nchan; 316 uint8_t mode; 317 struct { 318 uint8_t chan; 319 uint8_t power; 320 #define IWI_TXPOWER_MAX 20 321 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 322 } __attribute__((__packed__)) chan[37]; 323 } __attribute__((__packed__)); 324 325 /* structure for command IWI_CMD_ASSOCIATE */ 326 struct iwi_associate { 327 uint8_t chan; 328 uint8_t auth; 329 #define IWI_AUTH_OPEN 0 330 #define IWI_AUTH_SHARED 1 331 #define IWI_AUTH_NONE 3 332 333 uint8_t type; 334 uint8_t reserved1; 335 uint16_t policy; 336 #define IWI_POLICY_WME 1 337 #define IWI_POLICY_WPA 2 338 339 uint8_t plen; 340 uint8_t mode; 341 uint8_t bssid[IEEE80211_ADDR_LEN]; 342 uint8_t tstamp[8]; 343 uint16_t capinfo; 344 uint16_t lintval; 345 uint16_t intval; 346 uint8_t dst[IEEE80211_ADDR_LEN]; 347 uint32_t reserved3; 348 uint16_t reserved4; 349 } __attribute__((__packed__)); 350 351 #define IWI_SCAN_CHANNELS 54 352 353 #define IWI_SCAN_TYPE_FIRST_BEACON 0 354 #define IWI_SCAN_TYPE_PASSIVE 1 355 #define IWI_SCAN_TYPE_ACTIVE_DIRECT 2 356 #define IWI_SCAN_TYPE_ACTIVE_BROADCAST 3 357 #define IWI_SCAN_TYPE_ACTIVE_BDIRECT 4 358 #define IWI_SCAN_TYPES 5 359 360 #define iwi_scan_type_set(s, i, t) \ 361 do { \ 362 if ((i) % 2 == 0) \ 363 (s).type[(i) / 2].lsn = (t); \ 364 else \ 365 (s).type[(i) / 2].msn = (t); \ 366 } while(0) 367 368 /* structure for command IWI_CMD_SCAN_V2 */ 369 struct iwi_scan_v2 { 370 u_int32_t fsidx; 371 u_int8_t channels[IWI_SCAN_CHANNELS]; 372 #define IWI_CHAN_5GHZ (0 << 6) 373 #define IWI_CHAN_2GHZ (1 << 6) 374 375 struct { 376 #if _BYTE_ORDER == _LITTLE_ENDIAN 377 u_int8_t msn:4; 378 u_int8_t lsn:4; 379 #else 380 u_int8_t lsn:4; 381 u_int8_t msn:4; 382 #endif 383 } __attribute__ ((__packed__)) type[IWI_SCAN_CHANNELS / 2]; 384 385 u_int8_t reserved1; 386 u_int16_t dwelltime[IWI_SCAN_TYPES]; 387 388 } __attribute__ ((__packed__)); 389 390 /* structure for command IWI_CMD_SET_CONFIGURATION */ 391 struct iwi_configuration { 392 uint8_t bluetooth_coexistence; 393 uint8_t reserved1; 394 uint8_t answer_pbreq; 395 uint8_t allow_invalid_frames; 396 uint8_t multicast_enabled; 397 uint8_t drop_unicast_unencrypted; 398 uint8_t disable_unicast_decryption; 399 uint8_t drop_multicast_unencrypted; 400 uint8_t disable_multicast_decryption; 401 uint8_t antenna; 402 uint8_t reserved2; 403 uint8_t use_protection; 404 uint8_t protection_ctsonly; 405 uint8_t enable_multicast_filtering; 406 uint8_t bluetooth_threshold; 407 uint8_t reserved4; 408 uint8_t allow_beacon_and_probe_resp; 409 uint8_t allow_mgt; 410 uint8_t noise_reported; 411 uint8_t reserved5; 412 } __attribute__((__packed__)); 413 414 /* structure for command IWI_CMD_SET_WEP_KEY */ 415 struct iwi_wep_key { 416 uint8_t cmd; 417 #define IWI_WEP_KEY_CMD_SETKEY 0x08 418 419 uint8_t seq; 420 uint8_t idx; 421 uint8_t len; 422 uint8_t key[IEEE80211_KEYBUF_SIZE]; 423 } __attribute__((__packed__)); 424 425 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 426 427 /* structure for command IWI_CMD_SET_WME_PARAMS */ 428 struct iwi_wme_params { 429 uint16_t cwmin[WME_NUM_AC]; 430 uint16_t cwmax[WME_NUM_AC]; 431 uint8_t aifsn[WME_NUM_AC]; 432 uint8_t acm[WME_NUM_AC]; 433 uint16_t burst[WME_NUM_AC]; 434 } __packed; 435 436 #define IWI_MEM_START_ADDR 0x00300000 437 438 #define IWI_MEM_EEPROM_CTL (IWI_MEM_START_ADDR + 0x40) 439 #define IWI_MEM_EVENT_CTL (IWI_MEM_START_ADDR + 0x04) 440 441 /* 442 * led control bits 443 */ 444 #define IWI_LED_ACTIVITY 0x00000010 445 #define IWI_LED_ASSOCIATED 0x00000020 446 #define IWI_LED_OFDM 0x00000040 447 448 #define IWI_LED_MASK (IWI_LED_ACTIVITY | \ 449 IWI_LED_ASSOCIATED | \ 450 IWI_LED_OFDM) 451 452 #define IWI_LED_OFF(sc) \ 453 do { \ 454 MEM_WRITE_4(sc, IWI_MEM_EVENT_CTL, ~IWI_LED_MASK); \ 455 } while (/* CONSTCOND */ 0) 456 457 458 #define IWI_EEPROM_MAC 0x21 459 #define IWI_EEPROM_NIC_TYPE 0x25 460 461 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 462 463 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 464 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 465 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 466 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 467 468 #define IWI_EEPROM_SHIFT_D 2 469 #define IWI_EEPROM_SHIFT_Q 4 470 471 /* 472 * control and status registers access macros 473 */ 474 #define CSR_READ_1(sc, reg) \ 475 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 476 477 #define CSR_READ_2(sc, reg) \ 478 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 479 480 #define CSR_READ_4(sc, reg) \ 481 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 482 483 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 484 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 485 (datap), (count)) 486 487 #define CSR_WRITE_1(sc, reg, val) \ 488 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 489 490 #define CSR_WRITE_2(sc, reg, val) \ 491 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 492 493 #define CSR_WRITE_4(sc, reg, val) \ 494 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 495 496 #define CSR_WRITE_REGION_1(sc, offset, datap, count) \ 497 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 498 (datap), (count)) 499 500 /* 501 * indirect memory space access macros 502 */ 503 #define MEM_WRITE_1(sc, addr, val) do { \ 504 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 505 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 506 } while (/* CONSTCOND */0) 507 508 #define MEM_WRITE_2(sc, addr, val) do { \ 509 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 510 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 511 } while (/* CONSTCOND */0) 512 513 #define MEM_WRITE_4(sc, addr, val) do { \ 514 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 515 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 516 } while (/* CONSTCOND */0) 517 518 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 519 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 520 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 521 } while (/* CONSTCOND */0) 522 523 /* 524 * EEPROM access macro 525 */ 526 #define IWI_EEPROM_CTL(sc, val) do { \ 527 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 528 DELAY(IWI_EEPROM_DELAY); \ 529 } while (/* CONSTCOND */0) 530
Indexes created Mon Sep 29 21:09:56 GMT 2025