if_iwireg.h revision 1.16
1 /* $NetBSD: if_iwireg.h,v 1.16 2006/08/09 11:35:59 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini (at) free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IWI_CMD_RING_COUNT 16 31 #define IWI_TX_RING_COUNT 64 32 #define IWI_RX_RING_COUNT 32 33 34 #define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) 35 #define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) 36 37 #define IWI_CSR_INTR 0x0008 38 #define IWI_CSR_INTR_MASK 0x000c 39 #define IWI_CSR_INDIRECT_ADDR 0x0010 40 #define IWI_CSR_INDIRECT_DATA 0x0014 41 #define IWI_CSR_AUTOINC_ADDR 0x0018 42 #define IWI_CSR_AUTOINC_DATA 0x001c 43 #define IWI_CSR_RST 0x0020 44 #define IWI_CSR_CTL 0x0024 45 #define IWI_CSR_IO 0x0030 46 #define IWI_CSR_CMD_BASE 0x0200 47 #define IWI_CSR_CMD_SIZE 0x0204 48 #define IWI_CSR_TX1_BASE 0x0208 49 #define IWI_CSR_TX1_SIZE 0x020c 50 #define IWI_CSR_TX2_BASE 0x0210 51 #define IWI_CSR_TX2_SIZE 0x0214 52 #define IWI_CSR_TX3_BASE 0x0218 53 #define IWI_CSR_TX3_SIZE 0x021c 54 #define IWI_CSR_TX4_BASE 0x0220 55 #define IWI_CSR_TX4_SIZE 0x0224 56 #define IWI_CSR_CMD_RIDX 0x0280 57 #define IWI_CSR_TX1_RIDX 0x0284 58 #define IWI_CSR_TX2_RIDX 0x0288 59 #define IWI_CSR_TX3_RIDX 0x028c 60 #define IWI_CSR_TX4_RIDX 0x0290 61 #define IWI_CSR_RX_RIDX 0x02a0 62 #define IWI_CSR_RX_BASE 0x0500 63 #define IWI_CSR_ERRORLOG 0x0610 64 #define IWI_CSR_TABLE0_SIZE 0x0700 65 #define IWI_CSR_TABLE0_BASE 0x0704 66 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 67 #define IWI_CSR_NODE_BASE 0x0c0c 68 #define IWI_CSR_CMD_WIDX 0x0f80 69 #define IWI_CSR_TX1_WIDX 0x0f84 70 #define IWI_CSR_TX2_WIDX 0x0f88 71 #define IWI_CSR_TX3_WIDX 0x0f8c 72 #define IWI_CSR_TX4_WIDX 0x0f90 73 #define IWI_CSR_RX_WIDX 0x0fa0 74 #define IWI_CSR_READ_INT 0x0ff4 75 76 /* possible flags for IWI_CSR_INTR */ 77 #define IWI_INTR_RX_DONE 0x00000002 78 #define IWI_INTR_CMD_DONE 0x00000800 79 #define IWI_INTR_TX1_DONE 0x00001000 80 #define IWI_INTR_TX2_DONE 0x00002000 81 #define IWI_INTR_TX3_DONE 0x00004000 82 #define IWI_INTR_TX4_DONE 0x00008000 83 #define IWI_INTR_FW_INITED 0x01000000 84 #define IWI_INTR_RADIO_OFF 0x04000000 85 #define IWI_INTR_FATAL_ERROR 0x40000000 86 #define IWI_INTR_PARITY_ERROR 0x80000000 87 88 #define IWI_INTR_MASK \ 89 (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | \ 90 IWI_INTR_TX1_DONE | IWI_INTR_TX2_DONE | \ 91 IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ 92 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 93 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 94 95 /* possible flags for register IWI_CSR_RST */ 96 #define IWI_RST_PRINCETON_RESET 0x00000001 97 #define IWI_RST_SW_RESET 0x00000080 98 #define IWI_RST_MASTER_DISABLED 0x00000100 99 #define IWI_RST_STOP_MASTER 0x00000200 100 101 /* possible flags for register IWI_CSR_CTL */ 102 #define IWI_CTL_CLOCK_READY 0x00000001 103 #define IWI_CTL_ALLOW_STANDBY 0x00000002 104 #define IWI_CTL_INIT 0x00000004 105 106 /* possible flags for register IWI_CSR_IO */ 107 #define IWI_IO_RADIO_ENABLED 0x00010000 108 109 /* possible flags for IWI_CSR_READ_INT */ 110 #define IWI_READ_INT_INIT_HOST 0x20000000 111 112 /* error log definitions */ 113 struct iwi_error { 114 uint32_t type; 115 uint32_t reserved2; 116 uint32_t reserved3; 117 uint32_t reserved4; 118 uint32_t reserved5; 119 uint32_t reserved6; 120 uint32_t reserved7; 121 } __attribute__((__packed__)); 122 123 /* table2 offsets */ 124 #define IWI_INFO_ADAPTER_MAC 40 125 126 /* constants for command blocks */ 127 #define IWI_CB_DEFAULT_CTL 0x8cea0000 128 #define IWI_CB_MAXDATALEN 8191 129 130 /* supported rates */ 131 #define IWI_RATE_DS1 10 132 #define IWI_RATE_DS2 20 133 #define IWI_RATE_DS5 55 134 #define IWI_RATE_DS11 110 135 #define IWI_RATE_OFDM6 13 136 #define IWI_RATE_OFDM9 15 137 #define IWI_RATE_OFDM12 5 138 #define IWI_RATE_OFDM18 7 139 #define IWI_RATE_OFDM24 9 140 #define IWI_RATE_OFDM36 11 141 #define IWI_RATE_OFDM48 1 142 #define IWI_RATE_OFDM54 3 143 144 /* firmware binary image header */ 145 struct iwi_firmware_hdr { 146 uint32_t version; 147 uint32_t mode; 148 } __attribute__((__packed__)); 149 150 struct iwi_hdr { 151 uint8_t type; 152 #define IWI_HDR_TYPE_DATA 0 153 #define IWI_HDR_TYPE_COMMAND 1 154 #define IWI_HDR_TYPE_NOTIF 3 155 #define IWI_HDR_TYPE_FRAME 9 156 157 uint8_t seq; 158 uint8_t flags; 159 #define IWI_HDR_FLAG_IRQ 0x04 160 161 uint8_t reserved; 162 } __attribute__((__packed__)); 163 164 struct iwi_notif { 165 uint32_t reserved[2]; 166 uint8_t type; 167 #define IWI_NOTIF_TYPE_ASSOCIATION 10 168 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 169 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 170 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 171 #define IWI_NOTIF_TYPE_BEACON 17 172 #define IWI_NOTIF_TYPE_CALIBRATION 20 173 #define IWI_NOTIF_TYPE_NOISE 25 174 175 uint8_t flags; 176 uint16_t len; 177 } __attribute__((__packed__)); 178 179 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 180 struct iwi_notif_authentication { 181 uint8_t state; 182 #define IWI_DEAUTHENTICATED 0 183 #define IWI_AUTHENTICATED 9 184 } __attribute__((__packed__)); 185 186 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 187 struct iwi_notif_association { 188 uint8_t state; 189 #define IWI_DEASSOCIATED 0 190 #define IWI_ASSOCIATED 12 191 192 struct ieee80211_frame frame; 193 uint16_t capinfo; 194 uint16_t status; 195 uint16_t associd; 196 } __attribute__((__packed__)); 197 198 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 199 struct iwi_notif_scan_channel { 200 uint8_t nchan; 201 uint8_t reserved[47]; 202 } __attribute__((__packed__)); 203 204 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 205 struct iwi_notif_scan_complete { 206 uint8_t type; 207 uint8_t nchan; 208 uint8_t status; 209 uint8_t reserved; 210 } __attribute__((__packed__)); 211 212 /* received frame header */ 213 struct iwi_frame { 214 uint32_t reserved1[2]; 215 uint8_t chan; 216 uint8_t status; 217 uint8_t rate; 218 uint8_t rssi; /* receiver signal strength indicator */ 219 uint8_t agc; /* automatic gain control */ 220 uint8_t rssi_dbm; 221 uint16_t signal; 222 uint16_t noise; 223 uint8_t antenna; 224 uint8_t control; 225 uint8_t reserved2[2]; 226 uint16_t len; 227 } __attribute__((__packed__)); 228 229 /* header for transmission */ 230 struct iwi_tx_desc { 231 struct iwi_hdr hdr; 232 uint32_t reserved1; 233 uint8_t station; 234 uint8_t reserved2[3]; 235 uint8_t cmd; 236 #define IWI_DATA_CMD_TX 0x0b 237 238 uint8_t seq; 239 uint16_t len; 240 uint8_t priority; 241 uint8_t flags; 242 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 243 #define IWI_DATA_FLAG_NO_WEP 0x20 244 #define IWI_DATA_FLAG_NEED_ACK 0x80 245 246 uint8_t xflags; 247 #define IWI_DATA_XFLAG_QOS 0x10 248 249 uint8_t wep_txkey; 250 uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 251 uint8_t rate; 252 uint8_t antenna; 253 uint8_t reserved3[10]; 254 struct ieee80211_qosframe_addr4 wh; 255 uint32_t iv; 256 uint32_t eiv; 257 uint32_t nseg; 258 #define IWI_MAX_NSEG 6 259 260 uint32_t seg_addr[IWI_MAX_NSEG]; 261 uint16_t seg_len[IWI_MAX_NSEG]; 262 } __attribute__((__packed__)); 263 264 /* command */ 265 struct iwi_cmd_desc { 266 struct iwi_hdr hdr; 267 uint8_t type; 268 #define IWI_CMD_ENABLE 2 269 #define IWI_CMD_SET_CONFIGURATION 6 270 #define IWI_CMD_SET_ESSID 8 271 #define IWI_CMD_SET_MAC_ADDRESS 11 272 #define IWI_CMD_SET_RTS_THRESHOLD 15 273 #define IWI_CMD_SET_FRAG_THRESHOLD 16 274 #define IWI_CMD_SET_POWER_MODE 17 275 #define IWI_CMD_SET_WEP_KEY 18 276 #define IWI_CMD_ASSOCIATE 21 277 #define IWI_CMD_SET_RATES 22 278 #define IWI_CMD_ABORT_SCAN 23 279 #define IWI_CMD_SET_WME_PARAMS 25 280 #define IWI_CMD_SCAN_V2 26 281 #define IWI_CMD_SET_OPTIE 31 282 #define IWI_CMD_DISABLE 33 283 #define IWI_CMD_SET_IV 34 284 #define IWI_CMD_SET_TX_POWER 35 285 #define IWI_CMD_SET_SENSITIVITY 42 286 #define IWI_CMD_SET_WMEIE 84 287 288 uint8_t len; 289 uint16_t reserved; 290 uint8_t data[120]; 291 } __attribute__((__packed__)); 292 293 /* node information (IBSS) */ 294 struct iwi_ibssnode { 295 uint8_t bssid[IEEE80211_ADDR_LEN]; 296 uint8_t reserved[2]; 297 } __packed; 298 299 /* constants for 'mode' fields */ 300 #define IWI_MODE_11A 0 301 #define IWI_MODE_11B 1 302 #define IWI_MODE_11G 2 303 304 /* possible values for command IWI_CMD_SET_POWER_MODE */ 305 #define IWI_POWER_MODE_CAM 0 306 307 /* structure for command IWI_CMD_SET_RATES */ 308 struct iwi_rateset { 309 uint8_t mode; 310 uint8_t nrates; 311 uint8_t type; 312 #define IWI_RATESET_TYPE_NEGOTIATED 0 313 #define IWI_RATESET_TYPE_SUPPORTED 1 314 315 uint8_t reserved; 316 uint8_t rates[12]; 317 } __attribute__((__packed__)); 318 319 /* structure for command IWI_CMD_SET_TX_POWER */ 320 struct iwi_txpower { 321 uint8_t nchan; 322 uint8_t mode; 323 struct { 324 uint8_t chan; 325 uint8_t power; 326 #define IWI_TXPOWER_MAX 20 327 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 328 } __attribute__((__packed__)) chan[37]; 329 } __attribute__((__packed__)); 330 331 /* structure for command IWI_CMD_ASSOCIATE */ 332 struct iwi_associate { 333 uint8_t chan; 334 uint8_t auth; 335 #define IWI_AUTH_OPEN 0 336 #define IWI_AUTH_SHARED 1 337 #define IWI_AUTH_NONE 3 338 339 uint8_t type; 340 uint8_t reserved1; 341 uint16_t policy; 342 #define IWI_POLICY_WME 1 343 #define IWI_POLICY_WPA 2 344 345 uint8_t plen; 346 uint8_t mode; 347 uint8_t bssid[IEEE80211_ADDR_LEN]; 348 uint8_t tstamp[8]; 349 uint16_t capinfo; 350 uint16_t lintval; 351 uint16_t intval; 352 uint8_t dst[IEEE80211_ADDR_LEN]; 353 uint32_t reserved3; 354 uint16_t reserved4; 355 } __attribute__((__packed__)); 356 357 #define IWI_SCAN_CHANNELS 54 358 359 #define IWI_SCAN_TYPE_FIRST_BEACON 0 360 #define IWI_SCAN_TYPE_PASSIVE 1 361 #define IWI_SCAN_TYPE_ACTIVE_DIRECT 2 362 #define IWI_SCAN_TYPE_ACTIVE_BROADCAST 3 363 #define IWI_SCAN_TYPE_ACTIVE_BDIRECT 4 364 #define IWI_SCAN_TYPES 5 365 366 #define iwi_scan_type_set(s, i, t) \ 367 do { \ 368 if ((i) % 2 == 0) \ 369 (s).type[(i) / 2].lsn = (t); \ 370 else \ 371 (s).type[(i) / 2].msn = (t); \ 372 } while(0) 373 374 /* structure for command IWI_CMD_SCAN_V2 */ 375 struct iwi_scan_v2 { 376 u_int32_t fsidx; 377 u_int8_t channels[IWI_SCAN_CHANNELS]; 378 #define IWI_CHAN_5GHZ (0 << 6) 379 #define IWI_CHAN_2GHZ (1 << 6) 380 381 struct { 382 #if _BYTE_ORDER == _LITTLE_ENDIAN 383 u_int8_t msn:4; 384 u_int8_t lsn:4; 385 #else 386 u_int8_t lsn:4; 387 u_int8_t msn:4; 388 #endif 389 } __attribute__ ((__packed__)) type[IWI_SCAN_CHANNELS / 2]; 390 391 u_int8_t reserved1; 392 u_int16_t dwelltime[IWI_SCAN_TYPES]; 393 394 } __attribute__ ((__packed__)); 395 396 /* structure for command IWI_CMD_SET_CONFIGURATION */ 397 struct iwi_configuration { 398 uint8_t bluetooth_coexistence; 399 uint8_t reserved1; 400 uint8_t answer_pbreq; 401 uint8_t allow_invalid_frames; 402 uint8_t multicast_enabled; 403 uint8_t drop_unicast_unencrypted; 404 uint8_t disable_unicast_decryption; 405 uint8_t drop_multicast_unencrypted; 406 uint8_t disable_multicast_decryption; 407 uint8_t antenna; 408 uint8_t reserved2; 409 uint8_t use_protection; 410 uint8_t protection_ctsonly; 411 uint8_t enable_multicast_filtering; 412 uint8_t bluetooth_threshold; 413 uint8_t reserved4; 414 uint8_t allow_beacon_and_probe_resp; 415 uint8_t allow_mgt; 416 uint8_t noise_reported; 417 uint8_t reserved5; 418 } __attribute__((__packed__)); 419 420 /* structure for command IWI_CMD_SET_WEP_KEY */ 421 struct iwi_wep_key { 422 uint8_t cmd; 423 #define IWI_WEP_KEY_CMD_SETKEY 0x08 424 425 uint8_t seq; 426 uint8_t idx; 427 uint8_t len; 428 uint8_t key[IEEE80211_KEYBUF_SIZE]; 429 } __attribute__((__packed__)); 430 431 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 432 433 /* structure for command IWI_CMD_SET_WME_PARAMS */ 434 struct iwi_wme_params { 435 uint16_t cwmin[WME_NUM_AC]; 436 uint16_t cwmax[WME_NUM_AC]; 437 uint8_t aifsn[WME_NUM_AC]; 438 uint8_t acm[WME_NUM_AC]; 439 uint16_t burst[WME_NUM_AC]; 440 } __packed; 441 442 #define IWI_MEM_START_ADDR 0x00300000 443 444 #define IWI_MEM_EEPROM_CTL (IWI_MEM_START_ADDR + 0x40) 445 #define IWI_MEM_EVENT_CTL (IWI_MEM_START_ADDR + 0x04) 446 447 /* 448 * led control bits 449 */ 450 #define IWI_LED_ACTIVITY 0x00000010 451 #define IWI_LED_ASSOCIATED 0x00000020 452 #define IWI_LED_OFDM 0x00000040 453 454 #define IWI_LED_MASK (IWI_LED_ACTIVITY | \ 455 IWI_LED_ASSOCIATED | \ 456 IWI_LED_OFDM) 457 458 #define IWI_LED_OFF(sc) \ 459 do { \ 460 MEM_WRITE_4(sc, IWI_MEM_EVENT_CTL, ~IWI_LED_MASK); \ 461 } while (/* CONSTCOND */ 0) 462 463 464 #define IWI_EEPROM_MAC 0x21 465 #define IWI_EEPROM_NIC_TYPE 0x25 466 467 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 468 469 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 470 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 471 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 472 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 473 474 #define IWI_EEPROM_SHIFT_D 2 475 #define IWI_EEPROM_SHIFT_Q 4 476 477 /* 478 * control and status registers access macros 479 */ 480 #define CSR_READ_1(sc, reg) \ 481 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 482 483 #define CSR_READ_2(sc, reg) \ 484 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 485 486 #define CSR_READ_4(sc, reg) \ 487 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 488 489 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 490 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 491 (datap), (count)) 492 493 #define CSR_WRITE_1(sc, reg, val) \ 494 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 495 496 #define CSR_WRITE_2(sc, reg, val) \ 497 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 498 499 #define CSR_WRITE_4(sc, reg, val) \ 500 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 501 502 #define CSR_WRITE_REGION_1(sc, offset, datap, count) \ 503 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 504 (datap), (count)) 505 506 /* 507 * indirect memory space access macros 508 */ 509 #define MEM_WRITE_1(sc, addr, val) do { \ 510 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 511 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 512 } while (/* CONSTCOND */0) 513 514 #define MEM_WRITE_2(sc, addr, val) do { \ 515 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 516 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 517 } while (/* CONSTCOND */0) 518 519 #define MEM_WRITE_4(sc, addr, val) do { \ 520 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 521 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 522 } while (/* CONSTCOND */0) 523 524 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 525 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 526 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 527 } while (/* CONSTCOND */0) 528 529 /* 530 * EEPROM access macro 531 */ 532 #define IWI_EEPROM_CTL(sc, val) do { \ 533 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 534 DELAY(IWI_EEPROM_DELAY); \ 535 } while (/* CONSTCOND */0) 536
Indexes created Mon Sep 29 21:09:56 GMT 2025