if_iwn.c revision 1.36
1 /* $NetBSD: if_iwn.c,v 1.36 2010/01/19 22:07:00 pooka Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.49 2009/03/29 21:53:52 sthen Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini (at) free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Intel Wireless WiFi Link 4965 and Intel WiFi Link 5000 Series 23 * 802.11 network adapters. 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.36 2010/01/19 22:07:00 pooka Exp $"); 27 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/sysctl.h> 32 #include <sys/mbuf.h> 33 #include <sys/kernel.h> 34 #include <sys/socket.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/mutex.h> 38 #include <sys/conf.h> 39 #include <sys/kauth.h> 40 #include <sys/callout.h> 41 42 #include <machine/bus.h> 43 #include <machine/endian.h> 44 #include <machine/intr.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <net/if_ether.h> 61 #include <netinet/ip.h> 62 63 #include <net80211/ieee80211_var.h> 64 #include <net80211/ieee80211_amrr.h> 65 #include <net80211/ieee80211_radiotap.h> 66 67 #include <dev/firmload.h> 68 69 #include <dev/pci/if_iwnreg.h> 70 #include <dev/pci/if_iwnvar.h> 71 72 static const pci_product_id_t iwn_devices[] = { 73 PCI_PRODUCT_INTEL_PRO_WL_4965AGN_1, 74 PCI_PRODUCT_INTEL_PRO_WL_4965AGN_2, 75 PCI_PRODUCT_INTEL_PRO_WL_5100AGN_1, 76 PCI_PRODUCT_INTEL_PRO_WL_5100AGN_2, 77 #ifdef notyet 78 PCI_PRODUCT_INTEL_PRO_WL_5150AGN_1, 79 PCI_PRODUCT_INTEL_PRO_WL_5150AGN_2, 80 #endif 81 PCI_PRODUCT_INTEL_PRO_WL_5300AGN_1, 82 PCI_PRODUCT_INTEL_PRO_WL_5300AGN_2, 83 PCI_PRODUCT_INTEL_PRO_WL_5350AGN_1, 84 PCI_PRODUCT_INTEL_PRO_WL_5350AGN_2, 85 #ifdef notyet 86 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 87 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 93 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 94 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 95 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_1, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_2, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6000_4, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_1, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6050_3, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6050_4, 104 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 105 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 106 #endif 107 }; 108 109 /* 110 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 111 */ 112 static const struct ieee80211_rateset iwn_rateset_11a = 113 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 114 115 static const struct ieee80211_rateset iwn_rateset_11b = 116 { 4, { 2, 4, 11, 22 } }; 117 118 static const struct ieee80211_rateset iwn_rateset_11g = 119 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 120 121 122 static int iwn_match(device_t , struct cfdata *, void *); 123 static void iwn_attach(device_t , device_t, void *); 124 static int iwn_detach(device_t, int); 125 126 const struct iwn_hal *iwn_hal_attach(struct iwn_softc *); 127 static int iwn_nic_lock(struct iwn_softc *); 128 static int iwn_eeprom_lock(struct iwn_softc *); 129 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 130 static void iwn_radiotap_attach(struct iwn_softc *); 131 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 132 void **, bus_size_t, bus_size_t, int); 133 static void iwn_dma_contig_free(struct iwn_dma_info *); 134 static int iwn_alloc_sched(struct iwn_softc *); 135 static void iwn_free_sched(struct iwn_softc *); 136 static int iwn_alloc_kw(struct iwn_softc *); 137 static void iwn_free_kw(struct iwn_softc *); 138 static int iwn_alloc_fwmem(struct iwn_softc *); 139 static void iwn_free_fwmem(struct iwn_softc *); 140 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 141 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 142 static int iwn_alloc_rpool(struct iwn_softc *); 143 static void iwn_free_rpool(struct iwn_softc *); 144 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 145 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 146 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 147 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 148 int, int); 149 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 150 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 151 static int iwn_read_eeprom(struct iwn_softc *); 152 static void iwn4965_read_eeprom(struct iwn_softc *); 153 static void iwn5000_read_eeprom(struct iwn_softc *); 154 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 155 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 156 static void iwn_newassoc(struct ieee80211_node *, int); 157 static int iwn_media_change(struct ifnet *); 158 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 159 static void iwn_iter_func(void *, struct ieee80211_node *); 160 static void iwn_calib_timeout(void *); 161 #if 0 162 static int iwn_ccmp_decap(struct iwn_softc *, struct mbuf *, 163 struct ieee80211_key *); 164 #endif 165 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *); 166 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 167 struct iwn_rx_data *); 168 static void iwn5000_rx_calib_results(struct iwn_softc *, 169 struct iwn_rx_desc *, struct iwn_rx_data *); 170 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 171 struct iwn_rx_data *); 172 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 173 struct iwn_rx_data *); 174 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 177 uint8_t); 178 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 179 static void iwn_notif_intr(struct iwn_softc *); 180 static void iwn_wakeup_intr(struct iwn_softc *); 181 static void iwn_fatal_intr(struct iwn_softc *); 182 static int iwn_intr(void *); 183 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 184 uint16_t); 185 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 186 uint16_t); 187 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 188 static int iwn_tx(struct iwn_softc *, struct mbuf *, 189 struct ieee80211_node *, int); 190 static void iwn_start(struct ifnet *); 191 static void iwn_watchdog(struct ifnet *); 192 static int iwn_ioctl(struct ifnet *, u_long, void *); 193 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 194 static int iwn_wme_update(struct ieee80211com *); 195 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 196 int); 197 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 198 int); 199 static int iwn_set_link_quality(struct iwn_softc *, 200 struct ieee80211_node *); 201 static int iwn_add_broadcast_node(struct iwn_softc *, int); 202 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 203 static int iwn_set_critical_temp(struct iwn_softc *); 204 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 205 //static void iwn4965_power_calibration(struct iwn_softc *, int); 206 static int iwn4965_set_txpower(struct iwn_softc *, int); 207 static int iwn5000_set_txpower(struct iwn_softc *, int); 208 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 209 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 210 static int iwn_get_noise(const struct iwn_rx_general_stats *); 211 static int iwn4965_get_temperature(struct iwn_softc *); 212 static int iwn5000_get_temperature(struct iwn_softc *); 213 static int iwn_init_sensitivity(struct iwn_softc *); 214 static void iwn_collect_noise(struct iwn_softc *, 215 const struct iwn_rx_general_stats *); 216 static int iwn4965_init_gains(struct iwn_softc *); 217 static int iwn5000_init_gains(struct iwn_softc *); 218 static int iwn4965_set_gains(struct iwn_softc *); 219 static int iwn5000_set_gains(struct iwn_softc *); 220 static void iwn_tune_sensitivity(struct iwn_softc *, 221 const struct iwn_rx_stats *); 222 static int iwn_send_sensitivity(struct iwn_softc *); 223 // XXX static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 224 static int iwn_config(struct iwn_softc *); 225 static int iwn_scan(struct iwn_softc *, uint16_t); 226 static int iwn_auth(struct iwn_softc *); 227 static int iwn_run(struct iwn_softc *); 228 #ifdef notyet 229 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 230 struct ieee80211_key *); 231 #endif 232 #ifndef IEEE80211_NO_HT 233 static int iwn_ampdu_rx_start(struct ieee80211com *, 234 struct ieee80211_node *, uint8_t, uint16_t); 235 static void iwn_ampdu_rx_stop(struct ieee80211com *, 236 struct ieee80211_node *, uint8_t, uint16_t); 237 static int iwn_ampdu_tx_start(struct ieee80211com *, 238 struct ieee80211_node *, uint8_t, uint16_t); 239 static void iwn_ampdu_tx_stop(struct ieee80211com *, 240 struct ieee80211_node *, uint8_t, uint16_t); 241 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 242 struct ieee80211_node *, uint8_t, uint16_t); 243 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 244 uint8_t, uint16_t); 245 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 246 struct ieee80211_node *, uint8_t, uint16_t); 247 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 248 uint8_t, uint16_t); 249 #endif 250 static int iwn5000_query_calibration(struct iwn_softc *); 251 static int iwn5000_send_calibration(struct iwn_softc *); 252 static int iwn4965_post_alive(struct iwn_softc *); 253 static int iwn5000_post_alive(struct iwn_softc *); 254 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 255 int); 256 static int iwn4965_load_firmware(struct iwn_softc *); 257 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 258 const uint8_t *, int); 259 static int iwn5000_load_firmware(struct iwn_softc *); 260 static int iwn_read_firmware(struct iwn_softc *); 261 static int iwn_clock_wait(struct iwn_softc *); 262 static int iwn4965_apm_init(struct iwn_softc *); 263 static int iwn5000_apm_init(struct iwn_softc *); 264 static void iwn_apm_stop_master(struct iwn_softc *); 265 static void iwn_apm_stop(struct iwn_softc *); 266 static int iwn4965_nic_config(struct iwn_softc *); 267 static int iwn5000_nic_config(struct iwn_softc *); 268 static int iwn_hw_init(struct iwn_softc *); 269 static void iwn_hw_stop(struct iwn_softc *); 270 static int iwn_init(struct ifnet *); 271 static void iwn_stop(struct ifnet *, int); 272 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 273 static bool iwn_resume(device_t, pmf_qual_t); 274 275 #define IWN_DEBUG 276 #ifdef IWN_DEBUG 277 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 278 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 279 int iwn_debug = 0; 280 #else 281 #define DPRINTF(x) 282 #define DPRINTFN(n, x) 283 #endif 284 #ifdef IWN_DEBUG 285 static void iwn4965_print_power_group(struct iwn_softc *, int); 286 #endif 287 288 static const struct iwn_hal iwn4965_hal = { 289 iwn4965_load_firmware, 290 iwn4965_read_eeprom, 291 iwn4965_post_alive, 292 iwn4965_apm_init, 293 iwn4965_nic_config, 294 iwn4965_update_sched, 295 iwn4965_get_temperature, 296 iwn4965_get_rssi, 297 iwn4965_set_txpower, 298 iwn4965_init_gains, 299 iwn4965_set_gains, 300 iwn4965_add_node, 301 iwn4965_tx_done, 302 #ifndef IEEE80211_NO_HT 303 iwn4965_ampdu_tx_start, 304 iwn4965_ampdu_tx_stop, 305 #endif 306 &iwn4965_sensitivity_limits, 307 IWN4965_NTXQUEUES, 308 IWN4965_ID_BROADCAST, 309 IWN4965_RXONSZ, 310 IWN4965_SCHEDSZ, 311 IWN4965_FW_TEXT_MAXSZ, 312 IWN4965_FW_DATA_MAXSZ, 313 IWN4965_FWSZ, 314 IWN4965_SCHED_TXFACT 315 }; 316 317 static const struct iwn_hal iwn5000_hal = { 318 iwn5000_load_firmware, 319 iwn5000_read_eeprom, 320 iwn5000_post_alive, 321 iwn5000_apm_init, 322 iwn5000_nic_config, 323 iwn5000_update_sched, 324 iwn5000_get_temperature, 325 iwn5000_get_rssi, 326 iwn5000_set_txpower, 327 iwn5000_init_gains, 328 iwn5000_set_gains, 329 iwn5000_add_node, 330 iwn5000_tx_done, 331 #ifndef IEEE80211_NO_HT 332 iwn5000_ampdu_tx_start, 333 iwn5000_ampdu_tx_stop, 334 #endif 335 &iwn5000_sensitivity_limits, 336 IWN5000_NTXQUEUES, 337 IWN5000_ID_BROADCAST, 338 IWN5000_RXONSZ, 339 IWN5000_SCHEDSZ, 340 IWN5000_FW_TEXT_MAXSZ, 341 IWN5000_FW_DATA_MAXSZ, 342 IWN5000_FWSZ, 343 IWN5000_SCHED_TXFACT 344 }; 345 346 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 347 iwn_detach, NULL); 348 349 350 static int 351 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 352 { 353 struct pci_attach_args *pa = aux; 354 size_t i; 355 356 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 357 return 0; 358 359 for (i = 0; i < __arraycount(iwn_devices); i++) 360 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 361 return 1; 362 363 return 0; 364 } 365 366 static void 367 iwn_attach(device_t parent __unused, device_t self, void *aux) 368 { 369 struct iwn_softc *sc = device_private(self); 370 struct ieee80211com *ic = &sc->sc_ic; 371 struct ifnet *ifp = &sc->sc_ec.ec_if; 372 struct pci_attach_args *pa = aux; 373 const struct iwn_hal *hal; 374 const char *intrstr; 375 char devinfo[256]; 376 pci_intr_handle_t ih; 377 pcireg_t memtype, reg; 378 int i, error, revision; 379 380 sc->sc_dev = self; 381 sc->sc_pct = pa->pa_pc; 382 sc->sc_pcitag = pa->pa_tag; 383 384 callout_init(&sc->calib_to, 0); 385 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 386 387 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 388 revision = PCI_REVISION(pa->pa_class); 389 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 390 391 /* 392 * Get the offset of the PCI Express Capability Structure in PCI 393 * Configuration Space (the vendor driver hard-codes it as E0h.) 394 */ 395 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 396 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 397 if (error == 0) { 398 aprint_error_dev(self, "PCIe capability structure not found!\n"); 399 return; 400 } 401 402 /* Clear device-specific "PCI retry timeout" register (41h). */ 403 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 404 reg &= ~0xff00; 405 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 406 407 /* enable bus-mastering */ 408 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 409 reg |= PCI_COMMAND_MASTER_ENABLE; 410 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 411 412 /* map the register window */ 413 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 414 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 415 &sc->sc_sh, NULL, &sc->sc_sz); 416 if (error != 0) { 417 aprint_error_dev(self, "could not map memory space\n"); 418 return; 419 } 420 #if 1 421 sc->sc_dmat = pa->pa_dmat; 422 #else 423 /* XXX may not be needed */ 424 if (bus_dmatag_subregion(pa->pa_dmat, 0, 3 << 30, 425 &(sc->sc_dmat), BUS_DMA_NOWAIT) != 0) { 426 aprint_error_dev(self, 427 "WARNING: failed to restrict dma range, " 428 "falling back to parent bus dma range\n"); 429 sc->sc_dmat = pa->pa_dmat; 430 } 431 #endif 432 433 /* Install interrupt handler. */ 434 if (pci_intr_map(pa, &ih) != 0) { 435 aprint_error_dev(self, "could not map interrupt\n"); 436 return; 437 } 438 intrstr = pci_intr_string(sc->sc_pct, ih); 439 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 440 441 if (sc->sc_ih == NULL) { 442 aprint_error_dev(self, "could not establish interrupt"); 443 if (intrstr != NULL) 444 aprint_error(" at %s", intrstr); 445 aprint_error("\n"); 446 return; 447 } 448 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 449 450 /* Attach Hardware Abstraction Layer. */ 451 if ((hal = iwn_hal_attach(sc)) == NULL) 452 return; 453 454 /* Power ON adapter. */ 455 if ((error = hal->apm_init(sc)) != 0) { 456 aprint_error_dev(self, "could not power ON adapter\n"); 457 return; 458 } 459 460 /* Read MAC address, channels, etc from EEPROM. */ 461 if ((error = iwn_read_eeprom(sc)) != 0) { 462 aprint_error_dev(self, "could not read EEPROM\n"); 463 return; 464 } 465 466 /* Allocate DMA memory for firmware transfers. */ 467 if ((error = iwn_alloc_fwmem(sc)) != 0) { 468 aprint_error_dev(self, 469 "could not allocate memory for firmware\n"); 470 return; 471 } 472 473 /* Allocate "Keep Warm" page. */ 474 if ((error = iwn_alloc_kw(sc)) != 0) { 475 aprint_error_dev(self, "could not allocate keep warm page\n"); 476 goto fail1; 477 } 478 479 /* Allocate TX scheduler "rings". */ 480 if ((error = iwn_alloc_sched(sc)) != 0) { 481 aprint_error_dev(self, 482 "could not allocate TX scheduler rings\n"); 483 goto fail2; 484 } 485 486 /* Allocate RX buffers. */ 487 if ((error = iwn_alloc_rpool(sc)) != 0) { 488 aprint_error_dev(self, "could not allocate RX buffers\n"); 489 goto fail3; 490 } 491 492 /* Allocate TX rings (16 on 4965AGN, 20 on 5000.) */ 493 for (i = 0; i < hal->ntxqs; i++) { 494 struct iwn_tx_ring *txq = &sc->txq[i]; 495 error = iwn_alloc_tx_ring(sc, txq, IWN_TX_RING_COUNT, i); 496 if (error != 0) { 497 aprint_error_dev(self, 498 "could not allocate TX ring %d\n", i); 499 goto fail4; 500 } 501 } 502 503 /* Allocate RX ring. */ 504 if (iwn_alloc_rx_ring(sc, &sc->rxq) != 0) { 505 aprint_error_dev(self, "could not allocate RX ring\n"); 506 goto fail4; 507 } 508 509 /* Power OFF adapter. */ 510 iwn_apm_stop(sc); 511 /* Clear pending interrupts. */ 512 IWN_WRITE(sc, IWN_INT, 0xffffffff); 513 514 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", sc->ntxchains, 515 sc->nrxchains, sc->eeprom_domain, ether_sprintf(ic->ic_myaddr)); 516 517 /* Initialization firmware has not been loaded yet. */ 518 sc->sc_flags |= IWN_FLAG_FIRST_BOOT; 519 520 /* Set the state of the RF kill switch */ 521 sc->sc_radio = (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL); 522 523 ic->ic_ifp = ifp; 524 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 525 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 526 ic->ic_state = IEEE80211_S_INIT; 527 528 /* Set device capabilities. */ 529 ic->ic_caps = 530 IEEE80211_C_IBSS | /* IBSS mode support */ 531 IEEE80211_C_WPA | /* 802.11i */ 532 IEEE80211_C_MONITOR | /* monitor mode supported */ 533 IEEE80211_C_TXPMGT | /* tx power management */ 534 IEEE80211_C_SHSLOT | /* short slot time supported */ 535 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 536 IEEE80211_C_WME; /* 802.11e */ 537 538 /* Set supported rates. */ 539 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 540 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 541 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 542 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 543 } 544 545 /* IBSS channel undefined for now. */ 546 ic->ic_ibss_chan = &ic->ic_channels[0]; 547 548 memset(ic->ic_des_essid, 0, IEEE80211_NWID_LEN); 549 ic->ic_des_esslen = 0; 550 551 ifp->if_softc = sc; 552 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 553 ifp->if_stop = iwn_stop; 554 ifp->if_init = iwn_init; 555 ifp->if_ioctl = iwn_ioctl; 556 ifp->if_start = iwn_start; 557 ifp->if_watchdog = iwn_watchdog; 558 IFQ_SET_READY(&ifp->if_snd); 559 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 560 561 if_attach(ifp); 562 ieee80211_ifattach(ic); 563 ic->ic_node_alloc = iwn_node_alloc; 564 ic->ic_newassoc = iwn_newassoc; 565 ic->ic_wme.wme_update = iwn_wme_update; 566 #ifdef notyet 567 ic->ic_updateedca = iwn_updateedca; 568 ic->ic_set_key = iwn_set_key; 569 ic->ic_delete_key = iwn_delete_key; 570 #endif 571 #ifndef IEEE80211_NO_HT 572 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 573 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 574 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 575 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 576 #endif 577 578 /* Override 802.11 state transition machine. */ 579 sc->sc_newstate = ic->ic_newstate; 580 ic->ic_newstate = iwn_newstate; 581 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 582 583 sc->amrr.amrr_min_success_threshold = 1; 584 sc->amrr.amrr_max_success_threshold = 15; 585 586 if (pmf_device_register(self, NULL, iwn_resume)) 587 pmf_class_network_register(self, ifp); 588 else 589 aprint_error_dev(self, "couldn't establish power handler\n"); 590 591 iwn_radiotap_attach(sc); 592 593 ieee80211_announce(ic); 594 595 return; 596 597 /* Free allocated memory if something failed during attachment. */ 598 fail4: while (--i >= 0) 599 iwn_free_tx_ring(sc, &sc->txq[i]); 600 iwn_free_rpool(sc); 601 fail3: iwn_free_sched(sc); 602 fail2: iwn_free_kw(sc); 603 fail1: iwn_free_fwmem(sc); 604 } 605 606 static int 607 iwn_detach(device_t self, int flags __unused) 608 { 609 struct iwn_softc *sc = device_private(self); 610 struct ifnet *ifp = sc->sc_ic.ic_ifp; 611 int ac; 612 613 iwn_stop(ifp, 1); 614 if (ifp != NULL) 615 bpf_ops->bpf_detach(ifp); 616 ieee80211_ifdetach(&sc->sc_ic); 617 if (ifp != NULL) 618 if_detach(ifp); 619 620 for (ac = 0; ac < sc->sc_hal->ntxqs; ac++) 621 iwn_free_tx_ring(sc, &sc->txq[ac]); 622 iwn_free_rx_ring(sc, &sc->rxq); 623 iwn_free_rpool(sc); 624 iwn_free_sched(sc); 625 626 if (sc->sc_ih != NULL) { 627 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 628 sc->sc_ih = NULL; 629 } 630 631 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 632 633 return 0; 634 } 635 636 const struct iwn_hal * 637 iwn_hal_attach(struct iwn_softc *sc) 638 { 639 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 640 641 switch (sc->hw_type) { 642 case IWN_HW_REV_TYPE_4965: 643 sc->sc_hal = &iwn4965_hal; 644 sc->fwname = "iwlwifi-4965-1.ucode"; 645 sc->critical_temp = IWN_CTOK(110); 646 sc->txantmsk = IWN_ANT_A | IWN_ANT_B; 647 sc->rxantmsk = IWN_ANT_ABC; 648 sc->ntxchains = 2; 649 sc->nrxchains = 3; 650 break; 651 case IWN_HW_REV_TYPE_5100: 652 sc->sc_hal = &iwn5000_hal; 653 sc->fwname = "iwlwifi-5000-1.ucode"; 654 sc->critical_temp = 110; 655 sc->txantmsk = IWN_ANT_B; 656 sc->rxantmsk = IWN_ANT_A | IWN_ANT_B; 657 sc->ntxchains = 1; 658 sc->nrxchains = 2; 659 break; 660 case IWN_HW_REV_TYPE_5150: 661 sc->sc_hal = &iwn5000_hal; 662 sc->fwname = "iwlwifi-5150-1.ucode"; 663 /* NB: critical temperature will be read from EEPROM. */ 664 sc->txantmsk = IWN_ANT_A; 665 sc->rxantmsk = IWN_ANT_A | IWN_ANT_B; 666 sc->ntxchains = 1; 667 sc->nrxchains = 2; 668 break; 669 case IWN_HW_REV_TYPE_5300: 670 case IWN_HW_REV_TYPE_5350: 671 sc->sc_hal = &iwn5000_hal; 672 sc->fwname = "iwlwifi-5000-1.ucode"; 673 sc->critical_temp = 110; 674 sc->txantmsk = sc->rxantmsk = IWN_ANT_ABC; 675 sc->ntxchains = sc->nrxchains = 3; 676 break; 677 #ifdef notyet 678 case IWN_HW_REV_TYPE_1000: 679 sc->sc_hal = &iwn5000_hal; 680 sc->fwname = "iwn-1000"; 681 sc->critical_temp = 110; 682 sc->txantmsk = IWN_ANT_A; 683 sc->rxantmsk = IWN_ANT_A | IWN_ANT_B; 684 sc->ntxchains = 1; 685 sc->nrxchains = 2; 686 break; 687 case IWN_HW_REV_TYPE_6000: 688 sc->sc_hal = &iwn5000_hal; 689 sc->fwname = "iwn-6000"; 690 sc->critical_temp = 110; 691 sc->txantmsk = IWN_ANT_ABC; 692 sc->rxantmsk = IWN_ANT_ABC; 693 sc->ntxchains = 3; 694 sc->nrxchains = 3; 695 break; 696 case IWN_HW_REV_TYPE_6050: 697 sc->sc_hal = &iwn5000_hal; 698 sc->fwname = "iwn-6050"; 699 sc->critical_temp = 110; 700 sc->txantmsk = IWN_ANT_ABC; 701 sc->rxantmsk = IWN_ANT_ABC; 702 sc->ntxchains = 3; 703 sc->nrxchains = 3; 704 break; 705 #endif 706 default: 707 printf(": adapter type %d not supported\n", sc->hw_type); 708 return NULL; 709 } 710 return sc->sc_hal; 711 } 712 713 #if 0 714 /* 715 * Attach the adapter's on-board thermal sensor to the sensors framework. 716 */ 717 void 718 iwn_sensor_attach(struct iwn_softc *sc) 719 { 720 strlcpy(sc->sensordev.xname, sc->sc_dev.dv_xname, 721 sizeof sc->sensordev.xname); 722 sc->sensor.type = SENSOR_TEMP; 723 /* Temperature is not valid unless interface is up. */ 724 sc->sensor.value = 0; 725 sc->sensor.flags = SENSOR_FINVALID; 726 sensor_attach(&sc->sensordev, &sc->sensor); 727 sensordev_install(&sc->sensordev); 728 } 729 #endif /* 0 */ 730 731 /* 732 * Attach the interface to 802.11 radiotap. 733 */ 734 static void 735 iwn_radiotap_attach(struct iwn_softc *sc) 736 { 737 struct ifnet *ifp = sc->sc_ic.ic_ifp; 738 739 bpf_ops->bpf_attach(ifp, DLT_IEEE802_11_RADIO, 740 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 741 &sc->sc_drvbpf); 742 743 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 744 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 745 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 746 747 sc->sc_txtap_len = sizeof sc->sc_txtapu; 748 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 749 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 750 } 751 752 #if 0 /* XXX */ 753 /* 754 * Build a beacon frame that the firmware will broadcast periodically in 755 * IBSS or HostAP modes. 756 */ 757 static int 758 iwn_setup_beacon(struct iwn_softc *sc, struct ieee80211_node *ni) 759 { 760 struct ieee80211com *ic = &sc->sc_ic; 761 struct iwn_tx_ring *ring = &sc->txq[4]; 762 struct iwn_tx_desc *desc; 763 struct iwn_tx_data *data; 764 struct iwn_tx_cmd *cmd; 765 struct iwn_cmd_beacon *bcn; 766 struct ieee80211_beacon_offsets bo; 767 struct mbuf *m0; 768 bus_addr_t paddr; 769 int error; 770 771 desc = &ring->desc[ring->cur]; 772 data = &ring->data[ring->cur]; 773 m0 = ieee80211_beacon_alloc(ic, ni, &bo); 774 if (m0 == NULL) { 775 aprint_error_dev(sc->sc_dev, "could not allocate beacon frame\n" 776 ); 777 return ENOMEM; 778 } 779 cmd = &ring->cmd[ring->cur]; 780 cmd->code = IWN_CMD_SET_BEACON; 781 cmd->flags = 0; 782 cmd->qid = ring->qid; 783 cmd->idx = ring->cur; 784 785 bcn = (struct iwn_cmd_beacon *)cmd->data; 786 memset(bcn, 0, sizeof (struct iwn_cmd_beacon)); 787 bcn->id = sc->sc_hal->broadcast_id; 788 bcn->lifetime = htole32(IWN_LIFETIME_INFINITE); 789 bcn->len = htole16(m0->m_pkthdr.len); 790 #if 0 791 XXX 792 bcn->rate = (ic->ic_curmode == IEEE80211_MODE_11A) ? 793 iwn_plcp_signal(12) : iwn_plcp_signal(2); 794 #endif 795 bcn->flags2 = 0x2; /* RATE_MCS_CCK_MSK */ 796 bcn->flags = htole32(IWN_TX_AUTO_SEQ | IWN_TX_INSERT_TSTAMP; 797 // XXX | IWN_TX_USE_NODE_RATE); 798 799 /* save and trim IEEE802.11 header */ 800 m_copydata(m0, 0, sizeof (struct ieee80211_frame), (void *)&bcn->wh); 801 m_adj(m0, sizeof (struct ieee80211_frame)); 802 803 /* assume beacon frame is contiguous */ 804 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 805 BUS_DMA_READ | BUS_DMA_NOWAIT); 806 if (error) { 807 aprint_error_dev(sc->sc_dev, "could not map beacon\n"); 808 m_freem(m0); 809 return error; 810 } 811 812 data->m = m0; 813 814 /* first scatter/gather segment is used by the beacon command */ 815 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd); 816 817 IWN_SET_DESC_NSEGS(desc, 2); 818 IWN_SET_DESC_SEG(desc, 0, paddr , 4 + sizeof(struct iwn_cmd_beacon)); 819 IWN_SET_DESC_SEG(desc, 1, data->map->dm_segs[0].ds_addr, 820 data->map->dm_segs[1].ds_len); 821 822 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 823 data->map->dm_mapsize /* calc? */, BUS_DMASYNC_PREWRITE); 824 825 /* kick cmd ring */ 826 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 827 IWN_WRITE(sc, IWN_TX_WIDX, ring->qid << 8 | ring->cur); 828 return 0; 829 } 830 #endif 831 832 static int 833 iwn_nic_lock(struct iwn_softc *sc) 834 { 835 int ntries; 836 837 /* Request exclusive access to NIC. */ 838 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 839 840 /* Spin until we actually get the lock. */ 841 for (ntries = 0; ntries < 1000; ntries++) { 842 if ((IWN_READ(sc, IWN_GP_CNTRL) & 843 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 844 IWN_GP_CNTRL_MAC_ACCESS_ENA) 845 return 0; 846 DELAY(10); 847 } 848 return ETIMEDOUT; 849 } 850 851 static __inline void 852 iwn_nic_unlock(struct iwn_softc *sc) 853 { 854 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 855 } 856 857 static __inline uint32_t 858 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 859 { 860 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 861 return IWN_READ(sc, IWN_PRPH_RDATA); 862 } 863 864 static __inline void 865 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 866 { 867 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 868 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 869 } 870 871 static __inline void 872 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 873 { 874 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 875 } 876 877 static __inline void 878 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 879 { 880 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 881 } 882 883 static __inline void 884 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 885 const uint32_t *data, int count) 886 { 887 for (; count > 0; count--, data++, addr += 4) 888 iwn_prph_write(sc, addr, *data); 889 } 890 891 static __inline uint32_t 892 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 893 { 894 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 895 return IWN_READ(sc, IWN_MEM_RDATA); 896 } 897 898 static __inline void 899 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 900 { 901 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 902 IWN_WRITE(sc, IWN_MEM_WDATA, data); 903 } 904 905 static __inline void 906 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 907 { 908 uint32_t tmp; 909 910 tmp = iwn_mem_read(sc, addr & ~3); 911 if (addr & 3) 912 tmp = (tmp & 0x0000ffff) | data << 16; 913 else 914 tmp = (tmp & 0xffff0000) | data; 915 iwn_mem_write(sc, addr & ~3, tmp); 916 } 917 918 static __inline void 919 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 920 int count) 921 { 922 for (; count > 0; count--, addr += 4) 923 *data++ = iwn_mem_read(sc, addr); 924 } 925 926 static __inline void 927 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 928 int count) 929 { 930 for (; count > 0; count--, addr += 4) 931 iwn_mem_write(sc, addr, val); 932 } 933 934 static int 935 iwn_eeprom_lock(struct iwn_softc *sc) 936 { 937 int i, ntries; 938 939 for (i = 0; i < 100; i++) { 940 /* Request exclusive access to EEPROM. */ 941 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 942 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 943 944 /* Spin until we actually get the lock. */ 945 for (ntries = 0; ntries < 100; ntries++) { 946 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 947 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 948 return 0; 949 DELAY(10); 950 } 951 } 952 return ETIMEDOUT; 953 } 954 955 static __inline void 956 iwn_eeprom_unlock(struct iwn_softc *sc) 957 { 958 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 959 } 960 961 static int 962 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 963 { 964 uint8_t *out = data; 965 uint32_t val; 966 int ntries; 967 968 for (; count > 0; count -= 2, addr++) { 969 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 970 IWN_CLRBITS(sc, IWN_EEPROM, IWN_EEPROM_CMD); 971 972 for (ntries = 0; ntries < 10; ntries++) { 973 val = IWN_READ(sc, IWN_EEPROM); 974 if (val & IWN_EEPROM_READ_VALID) 975 break; 976 DELAY(5); 977 } 978 if (ntries == 10) { 979 aprint_error_dev(sc->sc_dev, "could not read EEPROM\n"); 980 return ETIMEDOUT; 981 } 982 *out++ = val >> 16; 983 if (count > 1) 984 *out++ = val >> 24; 985 } 986 return 0; 987 } 988 989 static int 990 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 991 bus_size_t size, bus_size_t alignment, int flags) 992 { 993 int nsegs, error; 994 995 dma->tag = tag; 996 dma->size = size; 997 998 error = bus_dmamap_create(tag, size, 1, size, 0, flags, &dma->map); 999 if (error != 0) 1000 goto fail; 1001 1002 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1003 flags); 1004 if (error != 0) 1005 goto fail; 1006 1007 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, flags); 1008 if (error != 0) 1009 goto fail; 1010 1011 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, flags); 1012 if (error != 0) 1013 goto fail; 1014 1015 memset(dma->vaddr, 0, size); 1016 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1017 1018 dma->paddr = dma->map->dm_segs[0].ds_addr; 1019 if (kvap != NULL) 1020 *kvap = dma->vaddr; 1021 1022 return 0; 1023 1024 fail: iwn_dma_contig_free(dma); 1025 return error; 1026 } 1027 1028 static void 1029 iwn_dma_contig_free(struct iwn_dma_info *dma) 1030 { 1031 if (dma->map != NULL) { 1032 if (dma->vaddr != NULL) { 1033 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1034 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1035 bus_dmamap_unload(dma->tag, dma->map); 1036 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1037 bus_dmamem_free(dma->tag, &dma->seg, 1); 1038 dma->vaddr = NULL; 1039 } 1040 bus_dmamap_destroy(dma->tag, dma->map); 1041 dma->map = NULL; 1042 } 1043 } 1044 1045 static int 1046 iwn_alloc_sched(struct iwn_softc *sc) 1047 { 1048 int error; 1049 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1050 error = iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1051 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT); 1052 if (error != 0) 1053 aprint_error_dev(sc->sc_dev, 1054 "could not allocate shared area DMA memory\n"); 1055 return error; 1056 } 1057 1058 static void 1059 iwn_free_sched(struct iwn_softc *sc) 1060 { 1061 iwn_dma_contig_free(&sc->sched_dma); 1062 } 1063 1064 static int 1065 iwn_alloc_kw(struct iwn_softc *sc) 1066 { 1067 /* "Keep Warm" page must be aligned on a 16-byte boundary. */ 1068 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1069 4096, BUS_DMA_NOWAIT); 1070 } 1071 1072 static void 1073 iwn_free_kw(struct iwn_softc *sc) 1074 { 1075 iwn_dma_contig_free(&sc->kw_dma); 1076 } 1077 1078 static int 1079 iwn_alloc_fwmem(struct iwn_softc *sc) 1080 { 1081 int error; 1082 /* Must be aligned on a 16-byte boundary. */ 1083 error = iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1084 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT); 1085 if (error != 0) { 1086 aprint_error_dev(sc->sc_dev, 1087 "could not allocate firmware transfer area DMA memory\n"); 1088 } 1089 return error; 1090 } 1091 1092 static void 1093 iwn_free_fwmem(struct iwn_softc *sc) 1094 { 1095 iwn_dma_contig_free(&sc->fw_dma); 1096 } 1097 1098 static struct iwn_rbuf * 1099 iwn_alloc_rbuf(struct iwn_softc *sc) 1100 { 1101 struct iwn_rbuf *rbuf; 1102 mutex_enter(&sc->rxq.freelist_mtx); 1103 1104 rbuf = SLIST_FIRST(&sc->rxq.freelist); 1105 if (rbuf != NULL) { 1106 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 1107 sc->rxq.nb_free_entries --; 1108 } 1109 mutex_exit(&sc->rxq.freelist_mtx); 1110 return rbuf; 1111 } 1112 1113 /* 1114 * This is called automatically by the network stack when the mbuf to which 1115 * our RX buffer is attached is freed. 1116 */ 1117 static void 1118 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 1119 { 1120 struct iwn_rbuf *rbuf = arg; 1121 struct iwn_softc *sc = rbuf->sc; 1122 1123 /* Put the RX buffer back in the free list. */ 1124 mutex_enter(&sc->rxq.freelist_mtx); 1125 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 1126 mutex_exit(&sc->rxq.freelist_mtx); 1127 1128 sc->rxq.nb_free_entries ++; 1129 if (__predict_true(m != NULL)) 1130 pool_cache_put(mb_cache, m); 1131 } 1132 1133 static int 1134 iwn_alloc_rpool(struct iwn_softc *sc) 1135 { 1136 struct iwn_rx_ring *ring = &sc->rxq; 1137 struct iwn_rbuf *rbuf; 1138 int i, error; 1139 1140 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 1141 1142 /* Allocate a big chunk of DMA'able memory... */ 1143 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 1144 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE, BUS_DMA_NOWAIT); 1145 if (error != 0) { 1146 aprint_error_dev(sc->sc_dev, 1147 "could not allocate RX buffers DMA memory\n"); 1148 return error; 1149 } 1150 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 1151 SLIST_INIT(&ring->freelist); 1152 for (i = 0; i < IWN_RBUF_COUNT; i++) { 1153 rbuf = &ring->rbuf[i]; 1154 1155 rbuf->sc = sc; /* Backpointer for callbacks. */ 1156 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 1157 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 1158 1159 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 1160 } 1161 ring->nb_free_entries = IWN_RBUF_COUNT; 1162 return 0; 1163 } 1164 1165 static void 1166 iwn_free_rpool(struct iwn_softc *sc) 1167 { 1168 iwn_dma_contig_free(&sc->rxq.buf_dma); 1169 } 1170 1171 static int 1172 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1173 { 1174 struct iwn_rx_data *data; 1175 bus_size_t size; 1176 struct iwn_rbuf *rbuf; 1177 int i, error; 1178 1179 ring->cur = 0; 1180 1181 /* Allocate RX descriptors (256-byte aligned.) */ 1182 size = IWN_RX_RING_COUNT * sizeof (struct iwn_rx_desc); 1183 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1184 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1185 if (error != 0) { 1186 aprint_error_dev(sc->sc_dev, 1187 "could not allocate RX ring DMA memory\n"); 1188 goto fail; 1189 } 1190 1191 /* Allocate RX status area (16-byte aligned.) */ 1192 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1193 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16, 1194 BUS_DMA_NOWAIT); 1195 if (error != 0) { 1196 aprint_error_dev(sc->sc_dev, 1197 "could not allocate RX status DMA memory\n"); 1198 goto fail; 1199 } 1200 1201 /* 1202 * Allocate and map RX buffers. 1203 */ 1204 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1205 data = &ring->data[i]; 1206 1207 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1208 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT, &data->map); 1209 if (error != 0) { 1210 aprint_error_dev(sc->sc_dev, 1211 "could not create RX buf DMA map\n"); 1212 goto fail; 1213 } 1214 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 1215 if (data->m == NULL) { 1216 aprint_error_dev(sc->sc_dev, 1217 "could not allocate RX mbuf\n"); 1218 error = ENOMEM; 1219 goto fail; 1220 } 1221 if ((rbuf = iwn_alloc_rbuf(sc)) == NULL) { 1222 m_freem(data->m); 1223 data->m = NULL; 1224 aprint_error_dev(sc->sc_dev, 1225 "could not allocate RX buffer\n"); 1226 error = ENOMEM; 1227 goto fail; 1228 } 1229 /* Attach RX buffer to mbuf header. */ 1230 MEXTADD(data->m, rbuf->vaddr, IWN_RBUF_SIZE, 0, iwn_free_rbuf, 1231 rbuf); 1232 data->m->m_flags |= M_EXT_RW; 1233 error = bus_dmamap_load(sc->sc_dmat, data->map, 1234 data->m->m_ext.ext_buf, IWN_RBUF_SIZE, NULL, 1235 BUS_DMA_NOWAIT); 1236 if (error != 0) { 1237 aprint_error_dev(sc->sc_dev, "can't not map mbuf" 1238 " (error %d)\n", error); 1239 goto fail; 1240 } 1241 1242 /* Set physical address of RX buffer (256-byte aligned.) */ 1243 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1244 } 1245 1246 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1247 0, ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1248 1249 return 0; 1250 1251 fail: iwn_free_rx_ring(sc, ring); 1252 return error; 1253 } 1254 1255 static void 1256 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1257 { 1258 int ntries; 1259 1260 if (iwn_nic_lock(sc) == 0) { 1261 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1262 for (ntries = 0; ntries < 1000; ntries++) { 1263 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1264 IWN_FH_RX_STATUS_IDLE) 1265 break; 1266 DELAY(10); 1267 } 1268 iwn_nic_unlock(sc); 1269 } 1270 ring->cur = 0; 1271 sc->last_rx_valid = 0; 1272 } 1273 1274 static void 1275 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1276 { 1277 int i; 1278 1279 iwn_dma_contig_free(&ring->desc_dma); 1280 iwn_dma_contig_free(&ring->stat_dma); 1281 1282 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1283 struct iwn_rx_data *data = &ring->data[i]; 1284 1285 if (data->m != NULL) { 1286 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1287 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1288 bus_dmamap_unload(sc->sc_dmat, data->map); 1289 m_freem(data->m); 1290 } 1291 if (data->map != NULL) 1292 bus_dmamap_destroy(sc->sc_dmat, data->map); 1293 } 1294 } 1295 1296 static int 1297 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int count, 1298 int qid) 1299 { 1300 bus_addr_t paddr; 1301 struct iwn_tx_data *data; 1302 int i, error, size; 1303 1304 ring->qid = qid; 1305 ring->count = count; 1306 ring->queued = 0; 1307 ring->cur = 0; 1308 1309 /* Allocate TX descriptors (256-byte aligned.) */ 1310 size = count * sizeof (struct iwn_tx_desc); 1311 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1312 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT); 1313 if (error != 0) { 1314 aprint_error_dev(sc->sc_dev, 1315 "could not allocate TX ring DMA memory\n"); 1316 goto fail; 1317 } 1318 /* 1319 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1320 * to allocate commands space for other rings. 1321 * XXX Do we really need to allocate descriptors for other rings? 1322 */ 1323 if (qid > 4) 1324 return 0; 1325 1326 size = count * sizeof (struct iwn_tx_cmd); 1327 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1328 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT); 1329 if (error != 0) { 1330 aprint_error_dev(sc->sc_dev, 1331 "could not allocate TX cmd DMA memory\n"); 1332 goto fail; 1333 } 1334 1335 paddr = ring->cmd_dma.paddr; 1336 1337 for (i = 0; i < count; i++) { 1338 data = &ring->data[i]; 1339 1340 data->cmd_paddr = paddr; 1341 data->scratch_paddr = paddr + 12; 1342 paddr += sizeof (struct iwn_tx_cmd); 1343 1344 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1345 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1346 &data->map); 1347 if (error != 0) { 1348 aprint_error_dev(sc->sc_dev, 1349 "could not create TX buf DMA map\n"); 1350 goto fail; 1351 } 1352 } 1353 return 0; 1354 1355 fail: iwn_free_tx_ring(sc, ring); 1356 return error; 1357 } 1358 1359 static void 1360 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1361 { 1362 struct iwn_tx_data *data; 1363 uint32_t tmp; 1364 int i, ntries; 1365 1366 if (iwn_nic_lock(sc) == 0) { 1367 IWN_WRITE(sc, IWN_FH_TX_CONFIG(ring->qid), 0); 1368 for (ntries = 0; ntries < 200; ntries++) { 1369 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 1370 if ((tmp & IWN_FH_TX_STATUS_IDLE(ring->qid)) == 1371 IWN_FH_TX_STATUS_IDLE(ring->qid)) 1372 break; 1373 DELAY(10); 1374 } 1375 iwn_nic_unlock(sc); 1376 } 1377 for (i = 0; i < ring->count; i++) { 1378 data = &ring->data[i]; 1379 1380 if (data->m != NULL) { 1381 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1382 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1383 bus_dmamap_unload(sc->sc_dmat, data->map); 1384 m_freem(data->m); 1385 data->m = NULL; 1386 } 1387 } 1388 /* Clear TX descriptors. */ 1389 memset(ring->desc, 0, ring->desc_dma.size); 1390 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1391 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1392 sc->qfullmsk &= ~(1 << ring->qid); 1393 ring->queued = 0; 1394 ring->cur = 0; 1395 } 1396 1397 static void 1398 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1399 { 1400 struct iwn_tx_data *data; 1401 int i; 1402 1403 iwn_dma_contig_free(&ring->desc_dma); 1404 iwn_dma_contig_free(&ring->cmd_dma); 1405 1406 if (ring->data != NULL) { 1407 for (i = 0; i < ring->count; i++) { 1408 data = &ring->data[i]; 1409 1410 if (data->m != NULL) { 1411 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1412 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1413 bus_dmamap_unload(sc->sc_dmat, data->map); 1414 m_freem(data->m); 1415 } 1416 if (data->map != NULL) 1417 bus_dmamap_destroy(sc->sc_dmat, data->map); 1418 } 1419 free(ring->data, M_DEVBUF); 1420 } 1421 } 1422 1423 static int 1424 iwn_read_eeprom(struct iwn_softc *sc) 1425 { 1426 const struct iwn_hal *hal = sc->sc_hal; 1427 struct ieee80211com *ic = &sc->sc_ic; 1428 uint16_t val; 1429 int error; 1430 1431 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x6) == 0) { 1432 aprint_error_dev(sc->sc_dev, "bad EEPROM signature\n"); 1433 return EIO; 1434 } 1435 if ((error = iwn_eeprom_lock(sc)) != 0) { 1436 aprint_error_dev(sc->sc_dev, 1437 "could not lock EEPROM (error=%d)\n", error); 1438 return error; 1439 } 1440 1441 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1442 sc->rfcfg = le16toh(val); 1443 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1444 1445 /* Read MAC address. */ 1446 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1447 1448 /* Read adapter-specific information from EEPROM. */ 1449 hal->read_eeprom(sc); 1450 1451 iwn_eeprom_unlock(sc); 1452 return 0; 1453 } 1454 1455 static void 1456 iwn4965_read_eeprom(struct iwn_softc *sc) 1457 { 1458 uint32_t addr; 1459 uint16_t val; 1460 int i; 1461 1462 /* Read regulatory domain (4 ASCII characters.) */ 1463 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1464 1465 /* Read the list of authorized channels (20MHz ones only.) */ 1466 for (i = 0; i < 5; i++) { 1467 addr = iwn4965_regulatory_bands[i]; 1468 iwn_read_eeprom_channels(sc, i, addr); 1469 } 1470 1471 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1472 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1473 sc->maxpwr2GHz = val & 0xff; 1474 sc->maxpwr5GHz = val >> 8; 1475 /* Check that EEPROM values are within valid range. */ 1476 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1477 sc->maxpwr5GHz = 38; 1478 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1479 sc->maxpwr2GHz = 38; 1480 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1481 1482 /* Read samples for each TX power group. */ 1483 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1484 sizeof sc->bands); 1485 1486 /* Read voltage at which samples were taken. */ 1487 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1488 sc->eeprom_voltage = (int16_t)le16toh(val); 1489 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1490 1491 #ifdef IWN_DEBUG 1492 /* Print samples. */ 1493 if (iwn_debug > 0) { 1494 for (i = 0; i < IWN_NBANDS; i++) 1495 iwn4965_print_power_group(sc, i); 1496 } 1497 #endif 1498 } 1499 1500 #ifdef IWN_DEBUG 1501 static void 1502 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1503 { 1504 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1505 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1506 int j, c; 1507 1508 printf("===band %d===\n", i); 1509 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1510 printf("chan1 num=%d\n", chans[0].num); 1511 for (c = 0; c < 2; c++) { 1512 for (j = 0; j < IWN_NSAMPLES; j++) { 1513 printf("chain %d, sample %d: temp=%d gain=%d " 1514 "power=%d pa_det=%d\n", c, j, 1515 chans[0].samples[c][j].temp, 1516 chans[0].samples[c][j].gain, 1517 chans[0].samples[c][j].power, 1518 chans[0].samples[c][j].pa_det); 1519 } 1520 } 1521 printf("chan2 num=%d\n", chans[1].num); 1522 for (c = 0; c < 2; c++) { 1523 for (j = 0; j < IWN_NSAMPLES; j++) { 1524 printf("chain %d, sample %d: temp=%d gain=%d " 1525 "power=%d pa_det=%d\n", c, j, 1526 chans[1].samples[c][j].temp, 1527 chans[1].samples[c][j].gain, 1528 chans[1].samples[c][j].power, 1529 chans[1].samples[c][j].pa_det); 1530 } 1531 } 1532 } 1533 #endif 1534 1535 static void 1536 iwn5000_read_eeprom(struct iwn_softc *sc) 1537 { 1538 int32_t temp, volt, delta; 1539 uint32_t base, addr; 1540 uint16_t val; 1541 int i; 1542 1543 /* Read regulatory domain (4 ASCII characters.) */ 1544 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1545 base = le16toh(val); 1546 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1547 sc->eeprom_domain, 4); 1548 1549 /* Read the list of authorized channels (20MHz ones only.) */ 1550 for (i = 0; i < 5; i++) { 1551 addr = base + iwn5000_regulatory_bands[i]; 1552 iwn_read_eeprom_channels(sc, i, addr); 1553 } 1554 1555 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1556 base = le16toh(val); 1557 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1558 /* Compute critical temperature (in Kelvin.) */ 1559 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1560 temp = le16toh(val); 1561 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1562 volt = le16toh(val); 1563 delta = temp - (volt / -5); 1564 sc->critical_temp = (IWN_CTOK(110) - delta) * -5; 1565 DPRINTF(("temp=%d volt=%d delta=%dK\n", 1566 temp, volt, delta)); 1567 } else { 1568 /* Read crystal calibration. */ 1569 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1570 &sc->eeprom_crystal, sizeof (uint32_t)); 1571 DPRINTF(("crystal calibration 0x%08x\n", 1572 le32toh(sc->eeprom_crystal))); 1573 } 1574 } 1575 1576 static void 1577 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1578 { 1579 struct ieee80211com *ic = &sc->sc_ic; 1580 const struct iwn_chan_band *band = &iwn_bands[n]; 1581 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1582 uint8_t chan; 1583 int i; 1584 1585 iwn_read_prom_data(sc, addr, channels, 1586 band->nchan * sizeof (struct iwn_eeprom_chan)); 1587 1588 for (i = 0; i < band->nchan; i++) { 1589 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1590 continue; 1591 1592 chan = band->chan[i]; 1593 1594 if (n == 0) { /* 2GHz band */ 1595 ic->ic_channels[chan].ic_freq = 1596 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1597 ic->ic_channels[chan].ic_flags = 1598 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1599 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1600 1601 } else { /* 5GHz band */ 1602 /* 1603 * Some adapters support channels 7, 8, 11 and 12 1604 * both in the 2GHz and 4.9GHz bands. 1605 * Because of limitations in our net80211 layer, 1606 * we don't support them in the 4.9GHz band. 1607 */ 1608 if (chan <= 14) 1609 continue; 1610 1611 ic->ic_channels[chan].ic_freq = 1612 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1613 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1614 /* We have at least one valid 5GHz channel. */ 1615 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1616 } 1617 1618 /* Is active scan allowed on this channel? */ 1619 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1620 ic->ic_channels[chan].ic_flags |= 1621 IEEE80211_CHAN_PASSIVE; 1622 } 1623 1624 /* Save maximum allowed TX power for this channel. */ 1625 sc->maxpwr[chan] = channels[i].maxpwr; 1626 1627 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1628 chan, channels[i].flags, sc->maxpwr[chan])); 1629 } 1630 } 1631 1632 /*ARGUSED*/ 1633 static struct ieee80211_node * 1634 iwn_node_alloc(struct ieee80211_node_table *nt __unused) 1635 { 1636 struct iwn_node *wn; 1637 1638 wn = malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1639 return (struct ieee80211_node *)wn; 1640 } 1641 1642 static void 1643 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1644 { 1645 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1646 struct iwn_node *wn = (void *)ni; 1647 uint8_t rate; 1648 int ridx, i; 1649 1650 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1651 1652 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1653 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1654 /* Map 802.11 rate to HW rate index. */ 1655 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1656 if (iwn_rates[ridx].rate == rate) 1657 break; 1658 wn->ridx[i] = ridx; 1659 /* Initial TX rate <= 24Mbps. */ 1660 if (rate <= 48) 1661 ni->ni_txrate = i; 1662 } 1663 } 1664 1665 static int 1666 iwn_media_change(struct ifnet *ifp) 1667 { 1668 struct iwn_softc *sc = ifp->if_softc; 1669 struct ieee80211com *ic = &sc->sc_ic; 1670 uint8_t rate, ridx; 1671 int error; 1672 1673 error = ieee80211_media_change(ifp); 1674 if (error != ENETRESET) 1675 return error; 1676 1677 if (ic->ic_fixed_rate != -1) { 1678 rate = ic->ic_sup_rates[ic->ic_curmode]. 1679 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1680 /* Map 802.11 rate to HW rate index. */ 1681 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1682 if (iwn_rates[ridx].rate == rate) 1683 break; 1684 sc->fixed_ridx = ridx; 1685 } 1686 1687 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1688 (IFF_UP | IFF_RUNNING)) { 1689 iwn_stop(ifp, 0); 1690 error = iwn_init(ifp); 1691 } 1692 return error; 1693 } 1694 1695 static int 1696 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1697 { 1698 struct ifnet *ifp = ic->ic_ifp; 1699 struct iwn_softc *sc = ifp->if_softc; 1700 int error; 1701 1702 callout_stop(&sc->calib_to); 1703 1704 switch (nstate) { 1705 case IEEE80211_S_SCAN: 1706 if (sc->is_scanning) 1707 break; 1708 1709 sc->is_scanning = true; 1710 ieee80211_node_table_reset(&ic->ic_scan); 1711 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1712 1713 /* Make the link LED blink while we're scanning. */ 1714 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1715 1716 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1717 aprint_error_dev(sc->sc_dev, 1718 "could not initiate scan\n"); 1719 return error; 1720 } 1721 ic->ic_state = nstate; 1722 return 0; 1723 1724 case IEEE80211_S_ASSOC: 1725 if (ic->ic_state != IEEE80211_S_RUN) 1726 break; 1727 /* FALLTHROUGH */ 1728 case IEEE80211_S_AUTH: 1729 /* Reset state to handle reassociations correctly. */ 1730 sc->rxon.associd = 0; 1731 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1732 sc->calib.state = IWN_CALIB_STATE_INIT; 1733 1734 if ((error = iwn_auth(sc)) != 0) { 1735 aprint_error_dev(sc->sc_dev, 1736 "could not move to auth state\n"); 1737 return error; 1738 } 1739 break; 1740 1741 case IEEE80211_S_RUN: 1742 if ((error = iwn_run(sc)) != 0) { 1743 aprint_error_dev(sc->sc_dev, 1744 "could not move to run state\n"); 1745 return error; 1746 } 1747 break; 1748 1749 case IEEE80211_S_INIT: 1750 sc->is_scanning = false; 1751 sc->calib.state = IWN_CALIB_STATE_INIT; 1752 break; 1753 } 1754 1755 return sc->sc_newstate(ic, nstate, arg); 1756 } 1757 1758 static void 1759 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1760 { 1761 struct iwn_softc *sc = arg; 1762 struct iwn_node *wn = (struct iwn_node *)ni; 1763 1764 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1765 } 1766 1767 static void 1768 iwn_calib_timeout(void *arg) 1769 { 1770 struct iwn_softc *sc = arg; 1771 struct ieee80211com *ic = &sc->sc_ic; 1772 int s; 1773 1774 if (ic->ic_fixed_rate == -1) { 1775 s = splnet(); 1776 if (ic->ic_opmode == IEEE80211_M_STA) 1777 iwn_iter_func(sc, ic->ic_bss); 1778 else 1779 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1780 splx(s); 1781 } 1782 /* Force automatic TX power calibration every 60 secs. */ 1783 if (++sc->calib_cnt >= 120) { 1784 uint32_t flags = 0; 1785 1786 DPRINTF(("sending request for statistics\n")); 1787 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1788 sizeof flags, 1); 1789 sc->calib_cnt = 0; 1790 } 1791 /* Automatic rate control triggered every 500ms. */ 1792 callout_schedule(&sc->calib_to, hz/2); 1793 } 1794 1795 #if 0 1796 static int 1797 iwn_ccmp_decap(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_key *k) 1798 { 1799 struct ieee80211_frame *wh; 1800 uint64_t pn, *prsc; 1801 uint8_t *ivp; 1802 uint8_t tid; 1803 int hdrlen; 1804 1805 wh = mtod(m, struct ieee80211_frame *); 1806 hdrlen = ieee80211_get_hdrlen(wh); 1807 ivp = (uint8_t *)wh + hdrlen; 1808 1809 /* Check that ExtIV bit is be set. */ 1810 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) { 1811 DPRINTF(("CCMP decap ExtIV not set\n")); 1812 return 1; 1813 } 1814 tid = ieee80211_has_qos(wh) ? 1815 ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1816 prsc = &k->k_rsc[tid]; 1817 1818 /* Extract the 48-bit PN from the CCMP header. */ 1819 pn = (uint64_t)ivp[0] | 1820 (uint64_t)ivp[1] << 8 | 1821 (uint64_t)ivp[4] << 16 | 1822 (uint64_t)ivp[5] << 24 | 1823 (uint64_t)ivp[6] << 32 | 1824 (uint64_t)ivp[7] << 40; 1825 if (pn <= *prsc) { 1826 /* 1827 * Not necessarily a replayed frame since we did not check 1828 * the sequence number of the 802.11 header yet. 1829 */ 1830 DPRINTF(("CCMP replayed\n")); 1831 return 1; 1832 } 1833 /* Update last seen packet number. */ 1834 *prsc = pn; 1835 1836 /* Clear Protected bit and strip IV. */ 1837 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1838 memmove(mtod(m, char *) + IEEE80211_CCMP_HDRLEN, wh, hdrlen); 1839 m_adj(m, IEEE80211_CCMP_HDRLEN); 1840 /* Strip MIC. */ 1841 m_adj(m, -IEEE80211_CCMP_MICLEN); 1842 return 0; 1843 } 1844 #endif 1845 1846 /* 1847 * Process an RX_PHY firmware notification. This is usually immediately 1848 * followed by an MPDU_RX_DONE notification. 1849 */ 1850 void 1851 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc) 1852 { 1853 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1854 1855 DPRINTFN(2, ("received PHY stats\n")); 1856 bus_dmamap_sync(sc->sc_dmat, sc->rxq.buf_dma.map, 1857 (vaddr_t)stat - (vaddr_t)sc->rxq.buf_dma.vaddr, sizeof (*stat), 1858 BUS_DMASYNC_POSTREAD); 1859 1860 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1861 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1862 sc->last_rx_valid = 1; 1863 } 1864 1865 /* 1866 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1867 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1868 */ 1869 void 1870 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1871 struct iwn_rx_data *data) 1872 { 1873 const struct iwn_hal *hal = sc->sc_hal; 1874 struct ieee80211com *ic = &sc->sc_ic; 1875 struct ifnet *ifp = ic->ic_ifp; 1876 struct iwn_rx_ring *ring = &sc->rxq; 1877 struct iwn_rbuf *rbuf; 1878 struct ieee80211_frame *wh; 1879 struct ieee80211_node *ni; 1880 struct mbuf *m, *m1; 1881 struct iwn_rx_stat *stat; 1882 char * head; 1883 uint32_t flags; 1884 int len, rssi, error; 1885 1886 if (desc->type == IWN_MPDU_RX_DONE) { 1887 /* Check for prior RX_PHY notification. */ 1888 if (!sc->last_rx_valid) { 1889 DPRINTF(("missing RX_PHY\n")); 1890 ifp->if_ierrors++; 1891 return; 1892 } 1893 sc->last_rx_valid = 0; 1894 stat = &sc->last_rx_stat; 1895 } else 1896 stat = (struct iwn_rx_stat *)(desc + 1); 1897 1898 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1899 BUS_DMASYNC_POSTREAD); 1900 1901 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1902 aprint_error_dev(sc->sc_dev, "invalid RX statistic header\n"); 1903 ifp->if_ierrors++; 1904 return; 1905 } 1906 if (desc->type == IWN_MPDU_RX_DONE) { 1907 struct iwn_rx_mpdu *mpdu = 1908 (struct iwn_rx_mpdu *)(desc + 1); 1909 head = (char *)(mpdu + 1); 1910 len = le16toh(mpdu->len); 1911 } else { 1912 head = (char *)(stat + 1) + stat->cfg_phy_len; 1913 len = le16toh(stat->len); 1914 } 1915 1916 flags = le32toh(*(uint32_t *)(head + len)); 1917 1918 /* Discard frames with a bad FCS early. */ 1919 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 1920 DPRINTFN(2, ("RX flags error %x\n", flags)); 1921 ifp->if_ierrors++; 1922 return; 1923 } 1924 /* Discard frames that are too short. */ 1925 if (len < sizeof (struct ieee80211_frame)) { 1926 DPRINTF(("frame too short: %d\n", len)); 1927 ic->ic_stats.is_rx_tooshort++; 1928 ifp->if_ierrors++; 1929 return; 1930 } 1931 1932 /* 1933 * See comment in if_wpi.c:wpi_rx_intr() about locking 1934 * nb_free_entries here. In short: it's not required. 1935 */ 1936 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1937 if (m1 == NULL) { 1938 ic->ic_stats.is_rx_nobuf++; 1939 ifp->if_ierrors++; 1940 return; 1941 } 1942 if (sc->rxq.nb_free_entries <= 0) { 1943 ic->ic_stats.is_rx_nobuf++; 1944 ifp->if_ierrors++; 1945 m_freem(m1); 1946 return; 1947 } 1948 rbuf = iwn_alloc_rbuf(sc); 1949 /* Attach RX buffer to mbuf header. */ 1950 MEXTADD(m1, rbuf->vaddr, IWN_RBUF_SIZE, 0, iwn_free_rbuf, 1951 rbuf); 1952 m1->m_flags |= M_EXT_RW; 1953 bus_dmamap_unload(sc->sc_dmat, data->map); 1954 1955 error = bus_dmamap_load(sc->sc_dmat, data->map, m1->m_ext.ext_buf, 1956 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT); 1957 if (error != 0) { 1958 m_freem(m1); 1959 1960 /* Try to reload the old mbuf. */ 1961 error = bus_dmamap_load(sc->sc_dmat, data->map, 1962 data->m->m_ext.ext_buf, IWN_RBUF_SIZE, NULL, 1963 BUS_DMA_NOWAIT); 1964 if (error != 0) { 1965 panic("%s: could not load old RX mbuf", 1966 device_xname(sc->sc_dev)); 1967 } 1968 /* Physical address may have changed. */ 1969 ring->desc[ring->cur] = 1970 htole32(data->map->dm_segs[0].ds_addr >> 8); 1971 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1972 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1973 BUS_DMASYNC_PREWRITE); 1974 ifp->if_ierrors++; 1975 return; 1976 } 1977 m = data->m; 1978 data->m = m1; 1979 1980 /* Update RX descriptor. */ 1981 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1982 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1983 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1984 BUS_DMASYNC_PREWRITE); 1985 1986 /* Finalize mbuf. */ 1987 m->m_pkthdr.rcvif = ifp; 1988 m->m_data = head; 1989 m->m_pkthdr.len = m->m_len = len; 1990 1991 /* Grab a reference to the source node. */ 1992 wh = mtod(m, struct ieee80211_frame *); 1993 ni = ieee80211_find_rxnode(ic,(struct ieee80211_frame_min *)wh); 1994 1995 #if 0 1996 rxi.rxi_flags = 0; 1997 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1998 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 1999 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 2000 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 2001 if ((flags & IWN_RX_CIPHER_MASK) != IWN_RX_CIPHER_CCMP) { 2002 ic->ic_stats.is_ccmp_dec_errs++; 2003 ifp->if_ierrors++; 2004 return; 2005 } 2006 /* Check whether decryption was successful or not. */ 2007 if ((desc->type == IWN_MPDU_RX_DONE && 2008 (flags & (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) != 2009 (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) || 2010 (desc->type != IWN_MPDU_RX_DONE && 2011 (flags & IWN_RX_DECRYPT_MASK) != IWN_RX_DECRYPT_OK)) { 2012 DPRINTF(("CCMP decryption failed 0x%x\n", flags)); 2013 ic->ic_stats.is_ccmp_dec_errs++; 2014 ifp->if_ierrors++; 2015 return; 2016 } 2017 if (iwn_ccmp_decap(sc, m, &ni->ni_pairwise_key) != 0) { 2018 ifp->if_ierrors++; 2019 return; 2020 } 2021 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2022 } 2023 #endif 2024 2025 rssi = hal->get_rssi(stat); 2026 if (ic->ic_state == IEEE80211_S_SCAN) 2027 iwn_fix_channel(ic, m); 2028 2029 if (sc->sc_drvbpf != NULL) { 2030 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2031 2032 tap->wr_flags = 0; 2033 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2034 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2035 tap->wr_chan_freq = 2036 htole16(ic->ic_channels[stat->chan].ic_freq); 2037 tap->wr_chan_flags = 2038 htole16(ic->ic_channels[stat->chan].ic_flags); 2039 tap->wr_dbm_antsignal = (int8_t)rssi; 2040 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2041 tap->wr_tsft = stat->tstamp; 2042 switch (stat->rate) { 2043 /* CCK rates. */ 2044 case 10: tap->wr_rate = 2; break; 2045 case 20: tap->wr_rate = 4; break; 2046 case 55: tap->wr_rate = 11; break; 2047 case 110: tap->wr_rate = 22; break; 2048 /* OFDM rates. */ 2049 case 0xd: tap->wr_rate = 12; break; 2050 case 0xf: tap->wr_rate = 18; break; 2051 case 0x5: tap->wr_rate = 24; break; 2052 case 0x7: tap->wr_rate = 36; break; 2053 case 0x9: tap->wr_rate = 48; break; 2054 case 0xb: tap->wr_rate = 72; break; 2055 case 0x1: tap->wr_rate = 96; break; 2056 case 0x3: tap->wr_rate = 108; break; 2057 /* Unknown rate: should not happen. */ 2058 default: tap->wr_rate = 0; 2059 } 2060 2061 bpf_ops->bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2062 } 2063 2064 /* Send the frame to the 802.11 layer. */ 2065 ieee80211_input(ic, m, ni, rssi, 0); 2066 2067 /* Node is no longer needed. */ 2068 ieee80211_free_node(ni); 2069 } 2070 2071 /* 2072 * Process a CALIBRATION_RESULT notification sent by the initialization 2073 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2074 */ 2075 void 2076 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2077 struct iwn_rx_data *data) 2078 { 2079 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2080 int len, idx = -1; 2081 2082 /* Runtime firmware should not send such a notification. */ 2083 if (!(sc->sc_flags & IWN_FLAG_FIRST_BOOT)) 2084 return; 2085 2086 len = (le32toh(desc->len) & 0x3fff) - 4; 2087 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2088 BUS_DMASYNC_POSTREAD); 2089 2090 switch (calib->code) { 2091 case IWN5000_PHY_CALIB_DC: 2092 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 2093 idx = 0; 2094 break; 2095 case IWN5000_PHY_CALIB_LO: 2096 idx = 1; 2097 break; 2098 case IWN5000_PHY_CALIB_TX_IQ: 2099 idx = 2; 2100 break; 2101 case IWN5000_PHY_CALIB_TX_IQ_PERD: 2102 if (sc->hw_type != IWN_HW_REV_TYPE_5150) 2103 idx = 3; 2104 break; 2105 case IWN5000_PHY_CALIB_BASE_BAND: 2106 idx = 4; 2107 break; 2108 } 2109 if (idx == -1) /* Ignore other results. */ 2110 return; 2111 2112 /* Save calibration result. */ 2113 if (sc->calibcmd[idx].buf != NULL) 2114 free(sc->calibcmd[idx].buf, M_DEVBUF); 2115 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2116 if (sc->calibcmd[idx].buf == NULL) { 2117 DPRINTF(("not enough memory for calibration result %d\n", 2118 calib->code)); 2119 return; 2120 } 2121 DPRINTF(("saving calibration result code=%d len=%d\n", 2122 calib->code, len)); 2123 sc->calibcmd[idx].len = len; 2124 memcpy(sc->calibcmd[idx].buf, calib, len); 2125 } 2126 2127 2128 /* 2129 * XXX: Hack to set the current channel to the value advertised in beacons or 2130 * probe responses. Only used during AP detection. 2131 * XXX: Duplicated from if_iwi.c 2132 */ 2133 static void 2134 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 2135 { 2136 struct ieee80211_frame *wh; 2137 uint8_t subtype; 2138 uint8_t *frm, *efrm; 2139 2140 wh = mtod(m, struct ieee80211_frame *); 2141 2142 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 2143 return; 2144 2145 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2146 2147 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 2148 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2149 return; 2150 2151 frm = (uint8_t *)(wh + 1); 2152 efrm = mtod(m, uint8_t *) + m->m_len; 2153 2154 frm += 12; /* skip tstamp, bintval and capinfo fields */ 2155 while (frm < efrm) { 2156 if (*frm == IEEE80211_ELEMID_DSPARMS) 2157 #if IEEE80211_CHAN_MAX < 255 2158 if (frm[2] <= IEEE80211_CHAN_MAX) 2159 #endif 2160 ic->ic_curchan = &ic->ic_channels[frm[2]]; 2161 2162 frm += frm[1] + 2; 2163 } 2164 } 2165 2166 2167 /* 2168 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2169 * The latter is sent by the firmware after each received beacon. 2170 */ 2171 static void 2172 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2173 struct iwn_rx_data *data) 2174 { 2175 struct ieee80211com *ic = &sc->sc_ic; 2176 struct iwn_calib_state *calib = &sc->calib; 2177 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2178 2179 /* Ignore statistics received during a scan. */ 2180 if (ic->ic_state != IEEE80211_S_RUN) 2181 return; 2182 2183 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2184 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2185 2186 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2187 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2188 2189 #if 0 2190 /* Test if temperature has changed. */ 2191 if (stats->general.temp != sc->rawtemp) { 2192 /* Convert "raw" temperature to degC. */ 2193 sc->rawtemp = stats->general.temp; 2194 temp = hal->get_temperature(sc); 2195 DPRINTFN(2, ("temperature=%dC\n", temp)); 2196 2197 /* Update temperature sensor. */ 2198 sc->sensor.value = IWN_CTOMUK(temp); 2199 sc->sensor.flags &= ~SENSOR_FINVALID; 2200 2201 /* Update TX power if need be (4965AGN only.) */ 2202 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2203 iwn4965_power_calibration(sc, temp); 2204 } 2205 #endif 2206 2207 if (desc->type != IWN_BEACON_STATISTICS) 2208 return; /* Reply to a statistics request. */ 2209 2210 sc->noise = iwn_get_noise(&stats->rx.general); 2211 2212 /* Test that RSSI and noise are present in stats report. */ 2213 if (le32toh(stats->rx.general.flags) != 1) { 2214 DPRINTF(("received statistics without RSSI\n")); 2215 return; 2216 } 2217 2218 if (calib->state == IWN_CALIB_STATE_ASSOC) 2219 iwn_collect_noise(sc, &stats->rx.general); 2220 else if (calib->state == IWN_CALIB_STATE_RUN) 2221 iwn_tune_sensitivity(sc, &stats->rx); 2222 } 2223 2224 /* 2225 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2226 * and 5000 adapters have different incompatible TX status formats. 2227 */ 2228 static void 2229 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2230 struct iwn_rx_data *data) 2231 { 2232 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2233 2234 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2235 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2236 iwn_tx_done(sc, desc, stat->retrycnt, le32toh(stat->status) & 0xff); 2237 } 2238 2239 static void 2240 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2241 struct iwn_rx_data *data) 2242 { 2243 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2244 2245 /* Reset TX scheduler slot. */ 2246 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2247 2248 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2249 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2250 iwn_tx_done(sc, desc, stat->retrycnt, le16toh(stat->status) & 0xff); 2251 } 2252 2253 /* 2254 * Adapter-independent backend for TX_DONE firmware notifications. 2255 */ 2256 static void 2257 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int retrycnt, 2258 uint8_t status) 2259 { 2260 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2261 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2262 struct iwn_tx_data *data = &ring->data[desc->idx]; 2263 struct iwn_node *wn = (struct iwn_node *)data->ni; 2264 2265 /* Update rate control statistics. */ 2266 wn->amn.amn_txcnt++; 2267 if (retrycnt > 0) 2268 wn->amn.amn_retrycnt++; 2269 2270 if (status != 1 && status != 2) 2271 ifp->if_oerrors++; 2272 else 2273 ifp->if_opackets++; 2274 2275 /* Unmap and free mbuf. */ 2276 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2277 BUS_DMASYNC_POSTWRITE); 2278 bus_dmamap_unload(sc->sc_dmat, data->map); 2279 m_freem(data->m); 2280 data->m = NULL; 2281 ieee80211_free_node(data->ni); 2282 data->ni = NULL; 2283 2284 sc->sc_tx_timer = 0; 2285 if (--ring->queued < IWN_TX_RING_LOMARK) { 2286 sc->qfullmsk &= ~(1 << ring->qid); 2287 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2288 ifp->if_flags &= ~IFF_OACTIVE; 2289 iwn_start(ifp); 2290 } 2291 } 2292 } 2293 2294 /* 2295 * Process a "command done" firmware notification. This is where we wakeup 2296 * processes waiting for a synchronous command completion. 2297 */ 2298 static void 2299 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2300 { 2301 struct iwn_tx_ring *ring = &sc->txq[4]; 2302 struct iwn_tx_data *data; 2303 2304 if ((desc->qid & 0xf) != 4) 2305 return; /* Not a command ack. */ 2306 2307 data = &ring->data[desc->idx]; 2308 2309 /* If the command was mapped in an mbuf, free it. */ 2310 if (data->m != NULL) { 2311 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2312 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2313 bus_dmamap_unload(sc->sc_dmat, data->map); 2314 m_freem(data->m); 2315 data->m = NULL; 2316 } 2317 wakeup(&ring->desc[desc->idx]); 2318 } 2319 2320 /* 2321 * Process an INT_FH_RX or INT_SW_RX interrupt. 2322 */ 2323 static void 2324 iwn_microcode_ready(struct iwn_softc *sc, struct iwn_ucode_info *uc) 2325 { 2326 2327 /* The microcontroller is ready */ 2328 DPRINTF(("microcode alive notification version=%d.%d " 2329 "subtype=%x alive=%x\n", uc->major, uc->minor, 2330 uc->subtype, le32toh(uc->valid))); 2331 2332 2333 if (le32toh(uc->valid) != 1) { 2334 aprint_error_dev(sc->sc_dev, "microcontroller initialization " 2335 "failed\n"); 2336 return; 2337 } 2338 if (uc->subtype == IWN_UCODE_INIT) { 2339 /* save microcontroller's report */ 2340 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2341 } 2342 /* Save the address of the error log in SRAM. */ 2343 sc->errptr = le32toh(uc->errptr); 2344 } 2345 2346 static void 2347 iwn_notif_intr(struct iwn_softc *sc) 2348 { 2349 struct ieee80211com *ic = &sc->sc_ic; 2350 struct ifnet *ifp = ic->ic_ifp; 2351 struct iwn_rx_data *data; 2352 struct iwn_rx_desc *desc; 2353 uint16_t hw; 2354 2355 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2356 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2357 2358 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2359 2360 /* 2361 * If the radio is disabled then down the interface and stop 2362 * processing - scan the queue for a microcode load command 2363 * result. It is the only thing that we can do with the radio 2364 * off. 2365 */ 2366 if (!sc->sc_radio) { 2367 while (sc->rxq.cur != hw) { 2368 data = &sc->rxq.data[sc->rxq.cur]; 2369 desc = (void *)data->m->m_ext.ext_buf; 2370 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2371 sizeof(*desc), BUS_DMASYNC_POSTREAD); 2372 if (desc->type == IWN_UC_READY) { 2373 iwn_microcode_ready(sc, 2374 (struct iwn_ucode_info *)(desc + 1)); 2375 } else if (desc->type == IWN_STATE_CHANGED) { 2376 uint32_t *status = (uint32_t *)(desc + 1); 2377 2378 /* enabled/disabled notification */ 2379 DPRINTF(("state changed to %x\n", 2380 le32toh(*status))); 2381 2382 sc->sc_radio = !(le32toh(*status) & 1); 2383 } 2384 2385 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2386 } 2387 2388 if (!sc->sc_radio) { 2389 iwn_stop(ifp, 1); 2390 } 2391 2392 return; 2393 } 2394 2395 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2396 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2397 2398 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2399 while (sc->rxq.cur != hw) { 2400 data = &sc->rxq.data[sc->rxq.cur]; 2401 desc = (void *)data->m->m_ext.ext_buf; 2402 2403 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2404 BUS_DMASYNC_POSTREAD); 2405 2406 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2407 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2408 2409 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2410 iwn_cmd_done(sc, desc); 2411 2412 switch (desc->type) { 2413 case IWN_RX_PHY: 2414 iwn_rx_phy(sc, desc); 2415 break; 2416 2417 case IWN_RX_DONE: /* 4965AGN only. */ 2418 case IWN_MPDU_RX_DONE: 2419 /* An 802.11 frame has been received. */ 2420 iwn_rx_done(sc, desc, data); 2421 break; 2422 2423 case IWN_TX_DONE: 2424 /* An 802.11 frame has been transmitted. */ 2425 sc->sc_hal->tx_done(sc, desc, data); 2426 break; 2427 2428 case IWN_RX_STATISTICS: 2429 case IWN_BEACON_STATISTICS: 2430 iwn_rx_statistics(sc, desc, data); 2431 break; 2432 2433 case IWN_BEACON_MISSED: 2434 { 2435 struct iwn_beacon_missed *miss = 2436 (struct iwn_beacon_missed *)(desc + 1); 2437 2438 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2439 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2440 /* 2441 * If more than 5 consecutive beacons are missed, 2442 * reinitialize the sensitivity state machine. 2443 */ 2444 DPRINTF(("beacons missed %d/%d\n", 2445 le32toh(miss->consecutive), le32toh(miss->total))); 2446 if (ic->ic_state == IEEE80211_S_RUN && 2447 le32toh(miss->consecutive) > 5) 2448 (void)iwn_init_sensitivity(sc); 2449 break; 2450 } 2451 case IWN_UC_READY: 2452 { 2453 iwn_microcode_ready(sc, 2454 (struct iwn_ucode_info *)(desc + 1)); 2455 break; 2456 } 2457 case IWN_STATE_CHANGED: 2458 { 2459 uint32_t *status = (uint32_t *)(desc + 1); 2460 2461 /* Enabled/disabled notification. */ 2462 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2463 sizeof (*status), BUS_DMASYNC_POSTREAD); 2464 DPRINTF(("state changed to %x\n", le32toh(*status))); 2465 2466 sc->sc_radio = !(le32toh(*status) & 1); 2467 2468 if (le32toh(*status) & 1) { 2469 /* The radio button has to be pushed. */ 2470 aprint_error_dev(sc->sc_dev, 2471 "Radio transmitter is off\n"); 2472 /* Turn the interface down. */ 2473 iwn_stop(ifp, 1); 2474 return; /* No further processing. */ 2475 } 2476 break; 2477 } 2478 case IWN_START_SCAN: 2479 { 2480 struct iwn_start_scan *scan = 2481 (struct iwn_start_scan *)(desc + 1); 2482 2483 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2484 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2485 DPRINTFN(2, ("scanning channel %d status %x\n", 2486 scan->chan, le32toh(scan->status))); 2487 2488 /* Fix current channel. */ 2489 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2490 break; 2491 } 2492 case IWN_STOP_SCAN: 2493 { 2494 struct iwn_stop_scan *scan = 2495 (struct iwn_stop_scan *)(desc + 1); 2496 2497 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2498 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2499 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2500 scan->nchan, scan->status, scan->chan)); 2501 2502 if (scan->status == 1 && scan->chan <= 14 && 2503 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2504 /* 2505 * We just finished scanning 2GHz channels, 2506 * start scanning 5GHz ones. 2507 */ 2508 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2509 break; 2510 } 2511 sc->is_scanning = false; 2512 ieee80211_end_scan(ic); 2513 break; 2514 } 2515 case IWN5000_CALIBRATION_RESULT: 2516 iwn5000_rx_calib_results(sc, desc, data); 2517 break; 2518 2519 case IWN5000_CALIBRATION_DONE: 2520 wakeup(sc); 2521 break; 2522 } 2523 2524 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2525 } 2526 2527 /* Tell the firmware what we have processed. */ 2528 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2529 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2530 } 2531 2532 /* 2533 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2534 * from power-down sleep mode. 2535 */ 2536 static void 2537 iwn_wakeup_intr(struct iwn_softc *sc) 2538 { 2539 int qid; 2540 2541 DPRINTF(("ucode wakeup from power-down sleep\n")); 2542 2543 /* Wakeup RX and TX rings. */ 2544 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2545 for (qid = 0; qid < 6; qid++) { 2546 struct iwn_tx_ring *ring = &sc->txq[qid]; 2547 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2548 } 2549 } 2550 2551 /* 2552 * Dump the error log of the firmware when a firmware panic occurs. Although 2553 * we can't debug the firmware because it is neither open source nor free, it 2554 * can help us to identify certain classes of problems. 2555 */ 2556 void 2557 iwn_fatal_intr(struct iwn_softc *sc) 2558 { 2559 const struct iwn_hal *hal = sc->sc_hal; 2560 struct iwn_fw_dump dump; 2561 int i; 2562 2563 /* Check that the error log address is valid. */ 2564 if (sc->errptr < IWN_FW_DATA_BASE || 2565 sc->errptr + sizeof (dump) > 2566 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2567 aprint_error_dev(sc->sc_dev, 2568 "bad firmware error log address 0x%08x\n", sc->errptr); 2569 return; 2570 } 2571 if (iwn_nic_lock(sc) != 0) { 2572 aprint_error_dev(sc->sc_dev, 2573 "could not read firmware error log\n"); 2574 return; 2575 } 2576 /* Read firmware error log from SRAM. */ 2577 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2578 sizeof (dump) / sizeof (uint32_t)); 2579 iwn_nic_unlock(sc); 2580 2581 if (dump.valid == 0) { 2582 aprint_error_dev(sc->sc_dev, "firmware error log is empty\n"); 2583 return; 2584 } 2585 printf("firmware error log:\n"); 2586 #if 0 2587 printf(" error type = \"%s\" (0x%08X)\n", 2588 (dump.id < nitems(iwn_fw_errmsg)) ? 2589 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2590 dump.id); 2591 #endif 2592 printf(" program counter = 0x%08X\n", dump.pc); 2593 printf(" source line = 0x%08X\n", dump.src_line); 2594 printf(" error data = 0x%08X%08X\n", 2595 dump.error_data[0], dump.error_data[1]); 2596 printf(" branch link = 0x%08X%08X\n", 2597 dump.branch_link[0], dump.branch_link[1]); 2598 printf(" interrupt link = 0x%08X%08X\n", 2599 dump.interrupt_link[0], dump.interrupt_link[1]); 2600 printf(" time = %u\n", dump.time[0]); 2601 2602 /* Dump driver status (TX and RX rings) while we're here. */ 2603 printf("driver status:\n"); 2604 for (i = 0; i < hal->ntxqs; i++) { 2605 struct iwn_tx_ring *ring = &sc->txq[i]; 2606 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2607 i, ring->qid, ring->cur, ring->queued); 2608 } 2609 printf(" rx ring: cur=%d\n", sc->rxq.cur); 2610 printf(" 802.11 state %d\n", sc->sc_ic.ic_state); 2611 } 2612 2613 static int 2614 iwn_intr(void *arg) 2615 { 2616 struct iwn_softc *sc = arg; 2617 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2618 uint32_t r1, r2; 2619 2620 /* Disable interrupts. */ 2621 IWN_WRITE(sc, IWN_MASK, 0); 2622 2623 r1 = IWN_READ(sc, IWN_INT); 2624 r2 = IWN_READ(sc, IWN_FH_INT); 2625 2626 if (r1 == 0 && r2 == 0) { 2627 if (ifp->if_flags & IFF_UP) 2628 IWN_WRITE(sc, IWN_MASK, IWN_INT_MASK); 2629 return 0; /* Interrupt not for us. */ 2630 } 2631 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2632 return 0; /* Hardware gone! */ 2633 2634 /* Acknowledge interrupts. */ 2635 IWN_WRITE(sc, IWN_INT, r1); 2636 IWN_WRITE(sc, IWN_FH_INT, r2); 2637 2638 if (r1 & IWN_INT_RF_TOGGLED) { 2639 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 2640 aprint_error_dev(sc->sc_dev, "RF switch: radio %s\n", 2641 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2642 sc->sc_radio = (tmp & IWN_GP_CNTRL_RFKILL); 2643 } 2644 if (r1 & IWN_INT_CT_REACHED) { 2645 aprint_error_dev(sc->sc_dev, "critical temperature reached!\n"); 2646 /* XXX Reduce TX power? */ 2647 } 2648 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2649 aprint_error_dev(sc->sc_dev, "fatal firmware error\n"); 2650 /* Dump firmware error log and stop. */ 2651 iwn_fatal_intr(sc); 2652 iwn_stop(sc->sc_ic.ic_ifp, 1); 2653 return 1; 2654 } 2655 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) || 2656 (r2 & IWN_FH_INT_RX)) 2657 iwn_notif_intr(sc); 2658 2659 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) 2660 wakeup(sc); /* FH DMA transfer completed. */ 2661 2662 if (r1 & IWN_INT_ALIVE) 2663 wakeup(sc); /* Firmware is alive. */ 2664 2665 if (r1 & IWN_INT_WAKEUP) 2666 iwn_wakeup_intr(sc); 2667 2668 /* Re-enable interrupts. */ 2669 if (ifp->if_flags & IFF_UP) 2670 IWN_WRITE(sc, IWN_MASK, IWN_INT_MASK); 2671 2672 return 1; 2673 } 2674 2675 /* 2676 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2677 * 5000 adapters use a slightly different format.) 2678 */ 2679 static void 2680 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2681 uint16_t len) 2682 { 2683 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2684 2685 *w = htole16(len + 8); 2686 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2687 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2688 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2689 if (idx < IWN_SCHED_WINSZ) { 2690 *(w + IWN_TX_RING_COUNT) = *w; 2691 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2692 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2693 (char *)(void *)sc->sched_dma.vaddr, 2694 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2695 } 2696 } 2697 2698 static void 2699 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2700 uint16_t len) 2701 { 2702 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2703 2704 *w = htole16(id << 12 | (len + 8)); 2705 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2706 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2707 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2708 if (idx < IWN_SCHED_WINSZ) { 2709 *(w + IWN_TX_RING_COUNT) = *w; 2710 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2711 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2712 (char *)(void *)sc->sched_dma.vaddr, 2713 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2714 } 2715 } 2716 2717 static void 2718 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2719 { 2720 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2721 2722 *w = (*w & htole16(0xf000)) | htole16(1); 2723 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2724 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2725 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2726 if (idx < IWN_SCHED_WINSZ) { 2727 *(w + IWN_TX_RING_COUNT) = *w; 2728 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2729 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2730 (char *)(void *)sc->sched_dma.vaddr, 2731 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2732 } 2733 } 2734 2735 static int 2736 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2737 { 2738 const struct iwn_hal *hal = sc->sc_hal; 2739 struct ieee80211com *ic = &sc->sc_ic; 2740 struct iwn_node *wn = (void *)ni; 2741 struct iwn_tx_ring *ring; 2742 struct iwn_tx_desc *desc; 2743 struct iwn_tx_data *data; 2744 struct iwn_tx_cmd *cmd; 2745 struct iwn_cmd_data *tx; 2746 const struct iwn_rate *rinfo; 2747 struct ieee80211_frame *wh; 2748 struct ieee80211_key *k = NULL; 2749 const struct chanAccParams *cap; 2750 struct mbuf *m1; 2751 uint32_t flags; 2752 u_int hdrlen; 2753 bus_dma_segment_t *seg; 2754 uint8_t ridx, txant, type; 2755 int i, totlen, error, pad, noack; 2756 2757 wh = mtod(m, struct ieee80211_frame *); 2758 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2759 2760 /* JAF XXX two lines above were not in wpi. check we don't duplicate this */ 2761 2762 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2763 hdrlen = sizeof (struct ieee80211_qosframe); 2764 cap = &ic->ic_wme.wme_chanParams; 2765 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2766 } else { 2767 hdrlen = sizeof (struct ieee80211_frame); 2768 noack = 0; 2769 } 2770 2771 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2772 k = ieee80211_crypto_encap(ic, ni, m); 2773 if (k == NULL) { 2774 m_freem(m); 2775 return ENOBUFS; 2776 } 2777 /* packet header may have moved, reset our local pointer */ 2778 wh = mtod(m, struct ieee80211_frame *); 2779 } 2780 2781 ring = &sc->txq[ac]; 2782 desc = &ring->desc[ring->cur]; 2783 data = &ring->data[ring->cur]; 2784 2785 /* Choose a TX rate index. */ 2786 if (type == IEEE80211_FC0_TYPE_MGT) { 2787 /* mgmt frames are sent at the lowest available bit-rate */ 2788 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2789 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2790 } else { 2791 if (ic->ic_fixed_rate != -1) { 2792 ridx = sc->fixed_ridx; 2793 } else 2794 ridx = wn->ridx[ni->ni_txrate]; 2795 } 2796 rinfo = &iwn_rates[ridx]; 2797 2798 if (sc->sc_drvbpf != NULL) { 2799 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2800 2801 tap->wt_flags = 0; 2802 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2803 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2804 tap->wt_rate = rinfo->rate; 2805 tap->wt_hwqueue = ac; 2806 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2807 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2808 2809 bpf_ops->bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2810 } 2811 2812 totlen = m->m_pkthdr.len; 2813 2814 /* Encrypt the frame if need be. */ 2815 #ifdef IEEE80211_FC1_PROTECTED 2816 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2817 /* Retrieve key for TX. */ 2818 k = ieee80211_get_txkey(ic, wh, ni); 2819 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 2820 /* Do software encryption. */ 2821 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 2822 return ENOBUFS; 2823 /* 802.11 header may have moved. */ 2824 wh = mtod(m, struct ieee80211_frame *); 2825 totlen = m->m_pkthdr.len; 2826 2827 } else /* HW appends CCMP MIC. */ 2828 totlen += IEEE80211_CCMP_HDRLEN; 2829 } 2830 #endif 2831 2832 /* Prepare TX firmware command. */ 2833 cmd = &ring->cmd[ring->cur]; 2834 cmd->code = IWN_CMD_TX_DATA; 2835 cmd->flags = 0; 2836 cmd->qid = ring->qid; 2837 cmd->idx = ring->cur; 2838 2839 tx = (struct iwn_cmd_data *)cmd->data; 2840 /* NB: No need to clear tx, all fields are reinitialized here. */ 2841 tx->scratch = 0; /* clear "scratch" area */ 2842 2843 flags = 0; 2844 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2845 flags |= IWN_TX_NEED_ACK; 2846 } else if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) 2847 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 2848 2849 #ifdef notyet 2850 if ((wh->i_fc[0] & 2851 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2852 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2853 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2854 #endif 2855 2856 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2857 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2858 2859 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2860 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2861 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2862 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2863 flags |= IWN_TX_NEED_RTS; 2864 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2865 ridx >= IWN_RIDX_OFDM6) { 2866 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2867 flags |= IWN_TX_NEED_CTS; 2868 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2869 flags |= IWN_TX_NEED_RTS; 2870 } 2871 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2872 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2873 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2874 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2875 flags |= IWN_TX_NEED_PROTECTION; 2876 } else 2877 flags |= IWN_TX_FULL_TXOP; 2878 } 2879 } 2880 2881 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2882 type != IEEE80211_FC0_TYPE_DATA) 2883 tx->id = hal->broadcast_id; 2884 else 2885 tx->id = wn->id; 2886 2887 if (type == IEEE80211_FC0_TYPE_MGT) { 2888 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2889 2890 #ifndef IEEE80211_STA_ONLY 2891 /* Tell HW to set timestamp in probe responses. */ 2892 if ((subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) || 2893 (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ)) 2894 flags |= IWN_TX_INSERT_TSTAMP; 2895 #endif 2896 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2897 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ || 2898 subtype == IEEE80211_FC0_SUBTYPE_AUTH || 2899 subtype == IEEE80211_FC0_SUBTYPE_DEAUTH) { 2900 flags &= ~IWN_TX_NEED_RTS; 2901 flags |= IWN_TX_NEED_CTS; 2902 tx->timeout = htole16(3); 2903 } else 2904 tx->timeout = htole16(2); 2905 } else 2906 tx->timeout = htole16(0); 2907 2908 if (hdrlen & 3) { 2909 /* First segment's length must be a multiple of 4. */ 2910 flags |= IWN_TX_NEED_PADDING; 2911 pad = 4 - (hdrlen & 3); 2912 } else 2913 pad = 0; 2914 2915 #if 0 2916 if (type == IEEE80211_FC0_TYPE_CTL) { 2917 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2918 2919 /* tell h/w to set timestamp in probe responses */ 2920 if (subtype == 0x0080) /* linux says this is "back request" */ 2921 /* linux says (1 << 6) is IMM_BA_RSP_MASK */ 2922 flags |= (IWN_TX_NEED_ACK | (1 << 6)); 2923 } 2924 #endif 2925 2926 tx->len = htole16(totlen); 2927 tx->tid = 0/* tid */; 2928 tx->rts_ntries = 60; 2929 tx->data_ntries = 15; 2930 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2931 tx->plcp = rinfo->plcp; 2932 tx->rflags = rinfo->flags; 2933 if (tx->id == hal->broadcast_id) { 2934 /* Group or management frame. */ 2935 tx->linkq = 0; 2936 /* XXX Alternate between antenna A and B? */ 2937 txant = IWN_LSB(sc->txantmsk); 2938 tx->rflags |= IWN_RFLAG_ANT(txant); 2939 } else { 2940 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2941 flags |= IWN_TX_LINKQ; /* enable MRR */ 2942 } 2943 /* Set physical address of "scratch area". */ 2944 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2945 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2946 2947 /* Copy 802.11 header in TX command. */ 2948 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2949 2950 /* Trim 802.11 header. */ 2951 m_adj(m, hdrlen); 2952 tx->security = 0; 2953 2954 #ifdef notyet 2955 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 2956 /* Trim 802.11 header and prepend CCMP IV. */ 2957 m_adj(m, hdrlen - IEEE80211_CCMP_HDRLEN); 2958 ivp = mtod(m, uint8_t *); 2959 k->k_tsc++; 2960 ivp[0] = k->k_tsc; 2961 ivp[1] = k->k_tsc >> 8; 2962 ivp[2] = 0; 2963 ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 2964 ivp[4] = k->k_tsc >> 16; 2965 ivp[5] = k->k_tsc >> 24; 2966 ivp[6] = k->k_tsc >> 32; 2967 ivp[7] = k->k_tsc >> 40; 2968 2969 tx->security = IWN_CIPHER_CCMP; 2970 /* XXX flags |= IWN_TX_AMPDU_CCMP; */ 2971 memcpy(tx->key, k->k_key, k->k_len); 2972 2973 /* TX scheduler includes CCMP MIC len w/5000 Series. */ 2974 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 2975 totlen += IEEE80211_CCMP_MICLEN; 2976 } else { 2977 /* Trim 802.11 header. */ 2978 m_adj(m, hdrlen); 2979 tx->security = 0; 2980 } 2981 #endif 2982 tx->flags = htole32(flags); 2983 2984 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2985 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2986 if (error != 0 && error != EFBIG) { 2987 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 2988 error); 2989 m_freem(m); 2990 return error; 2991 } 2992 if (error != 0) { 2993 /* Too many DMA segments, linearize mbuf. */ 2994 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2995 if (m1 == NULL) { 2996 m_freem(m); 2997 return ENOBUFS; 2998 } 2999 if (m->m_pkthdr.len > MHLEN) { 3000 MCLGET(m1, M_DONTWAIT); 3001 if (!(m1->m_flags & M_EXT)) { 3002 m_freem(m); 3003 m_freem(m1); 3004 return ENOBUFS; 3005 } 3006 } 3007 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 3008 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3009 m_freem(m); 3010 m = m1; 3011 3012 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3013 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 3014 if (error != 0) { 3015 aprint_error_dev(sc->sc_dev, 3016 "could not map mbuf (error %d)\n", error); 3017 m_freem(m); 3018 return error; 3019 } 3020 } 3021 3022 data->m = m; 3023 data->ni = ni; 3024 3025 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3026 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3027 3028 /* Fill TX descriptor. */ 3029 desc->nsegs = 1 + data->map->dm_nsegs; 3030 /* First DMA segment is used by the TX command. */ 3031 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3032 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3033 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3034 /* Other DMA segments are for data payload. */ 3035 seg = data->map->dm_segs; 3036 for (i = 1; i <= data->map->dm_nsegs; i++) { 3037 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3038 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3039 seg->ds_len << 4); 3040 seg++; 3041 } 3042 3043 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3044 BUS_DMASYNC_PREWRITE); 3045 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3046 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3047 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3048 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3049 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3050 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3051 3052 /* Update TX scheduler. */ 3053 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3054 3055 /* Kick TX ring. */ 3056 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3057 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3058 3059 /* Mark TX ring as full if we reach a certain threshold. */ 3060 if (++ring->queued > IWN_TX_RING_HIMARK) 3061 sc->qfullmsk |= 1 << ring->qid; 3062 3063 return 0; 3064 } 3065 3066 static void 3067 iwn_start(struct ifnet *ifp) 3068 { 3069 struct iwn_softc *sc = ifp->if_softc; 3070 struct ieee80211com *ic = &sc->sc_ic; 3071 struct ieee80211_node *ni; 3072 struct ether_header *eh; 3073 struct mbuf *m; 3074 int ac; 3075 3076 DPRINTFN(5, ("iwn_start enter\n")); 3077 3078 /* 3079 * net80211 may still try to send management frames even if the 3080 * IFF_RUNNING flag is not set... Also, don't bother if the radio 3081 * is not enabled. 3082 */ 3083 if (((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) || 3084 !sc->sc_radio) 3085 return; 3086 3087 for (;;) { 3088 if (sc->qfullmsk != 0) { 3089 ifp->if_flags |= IFF_OACTIVE; 3090 break; 3091 } 3092 /* Send pending management frames first. */ 3093 IF_DEQUEUE(&ic->ic_mgtq, m); 3094 if (m != NULL) { 3095 ni = (void *)m->m_pkthdr.rcvif; 3096 ac = 0; 3097 goto sendit; 3098 } 3099 if (ic->ic_state != IEEE80211_S_RUN) 3100 break; 3101 3102 /* Encapsulate and send data frames. */ 3103 IFQ_DEQUEUE(&ifp->if_snd, m); 3104 if (m == NULL) 3105 break; 3106 if (m->m_len < sizeof (*eh) && 3107 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3108 ifp->if_oerrors++; 3109 continue; 3110 } 3111 eh = mtod(m, struct ether_header *); 3112 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3113 if (ni == NULL) { 3114 m_freem(m); 3115 ifp->if_oerrors++; 3116 continue; 3117 } 3118 /* classify mbuf so we can find which tx ring to use */ 3119 if (ieee80211_classify(ic, m, ni) != 0) { 3120 m_freem(m); 3121 ieee80211_free_node(ni); 3122 ifp->if_oerrors++; 3123 continue; 3124 } 3125 3126 /* no QoS encapsulation for EAPOL frames */ 3127 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3128 M_WME_GETAC(m) : WME_AC_BE; 3129 if (ifp->if_bpf != NULL) 3130 bpf_ops->bpf_mtap(ifp->if_bpf, m); 3131 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3132 ieee80211_free_node(ni); 3133 ifp->if_oerrors++; 3134 continue; 3135 } 3136 sendit: 3137 if (ic->ic_rawbpf != NULL) 3138 bpf_ops->bpf_mtap(ic->ic_rawbpf, m); 3139 if (iwn_tx(sc, m, ni, ac) != 0) { 3140 ieee80211_free_node(ni); 3141 ifp->if_oerrors++; 3142 continue; 3143 } 3144 3145 sc->sc_tx_timer = 5; 3146 ifp->if_timer = 1; 3147 } 3148 } 3149 3150 static void 3151 iwn_watchdog(struct ifnet *ifp) 3152 { 3153 struct iwn_softc *sc = ifp->if_softc; 3154 3155 ifp->if_timer = 0; 3156 3157 if (sc->sc_tx_timer > 0) { 3158 if (--sc->sc_tx_timer == 0) { 3159 aprint_error_dev(sc->sc_dev, "device timeout\n"); 3160 iwn_stop(ifp, 1); 3161 ifp->if_oerrors++; 3162 return; 3163 } 3164 ifp->if_timer = 1; 3165 } 3166 3167 ieee80211_watchdog(&sc->sc_ic); 3168 } 3169 3170 static int 3171 iwn_ioctl(struct ifnet *ifp, u_long cmd, void* data) 3172 { 3173 #define IS_RUNNING(ifp) \ 3174 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 3175 3176 struct iwn_softc *sc = ifp->if_softc; 3177 struct ieee80211com *ic = &sc->sc_ic; 3178 int s, error = 0; 3179 3180 s = splnet(); 3181 3182 switch (cmd) { 3183 case SIOCSIFADDR: 3184 /* FALLTHROUGH */ 3185 case SIOCSIFFLAGS: 3186 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3187 break; 3188 if (ifp->if_flags & IFF_UP) { 3189 /* 3190 * resync the radio state just in case we missed 3191 * and event. 3192 */ 3193 sc->sc_radio = 3194 (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL); 3195 3196 if (!sc->sc_radio) { 3197 error = EBUSY; /* XXX not really but same as els 3198 ewhere in driver */ 3199 if (ifp->if_flags & IFF_RUNNING) 3200 iwn_stop(ifp, 1); 3201 } else if (!(ifp->if_flags & IFF_RUNNING)) 3202 error = iwn_init(ifp); 3203 } else { 3204 if (ifp->if_flags & IFF_RUNNING) 3205 iwn_stop(ifp, 1); 3206 } 3207 break; 3208 3209 case SIOCADDMULTI: 3210 case SIOCDELMULTI: 3211 /* XXX no h/w multicast filter? --dyoung */ 3212 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3213 /* setup multicast filter, etc */ 3214 error = 0; 3215 } 3216 break; 3217 3218 #if 0 3219 case SIOCS80211POWER: 3220 error = ieee80211_ioctl(ifp, cmd, data); 3221 if (error != ENETRESET) 3222 break; 3223 if (ic->ic_state == IEEE80211_S_RUN && 3224 sc->calib.state == IWN_CALIB_STATE_RUN) { 3225 if (ic->ic_flags & IEEE80211_F_PMGTON) 3226 error = iwn_set_pslevel(sc, 0, 3, 0); 3227 else /* back to CAM */ 3228 error = iwn_set_pslevel(sc, 0, 0, 0); 3229 } else { 3230 /* Defer until transition to IWN_CALIB_STATE_RUN. */ 3231 error = 0; 3232 } 3233 break; 3234 #endif 3235 3236 default: 3237 error = ieee80211_ioctl(ic, cmd, data); 3238 } 3239 3240 if (error == ENETRESET) { 3241 error = 0; 3242 if (IS_RUNNING(ifp) && 3243 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) { 3244 iwn_stop(ifp, 0); 3245 error = iwn_init(ifp); 3246 } 3247 } 3248 splx(s); 3249 return error; 3250 #undef IS_RUNNING 3251 } 3252 3253 /* 3254 * Send a command to the firmware. 3255 */ 3256 static int 3257 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3258 { 3259 const struct iwn_hal *hal = sc->sc_hal; 3260 struct iwn_tx_ring *ring = &sc->txq[4]; 3261 struct iwn_tx_desc *desc; 3262 struct iwn_tx_data *data; 3263 struct iwn_tx_cmd *cmd; 3264 struct mbuf *m; 3265 bus_addr_t paddr; 3266 int totlen, error; 3267 3268 desc = &ring->desc[ring->cur]; 3269 data = &ring->data[ring->cur]; 3270 totlen = 4 + size; 3271 3272 if (size > sizeof cmd->data) { 3273 /* Command is too large to fit in a descriptor. */ 3274 if (totlen > MCLBYTES) 3275 return EINVAL; 3276 MGETHDR(m, M_DONTWAIT, MT_DATA); 3277 if (m == NULL) 3278 return ENOMEM; 3279 if (totlen > MHLEN) { 3280 MCLGET(m, M_DONTWAIT); 3281 if (!(m->m_flags & M_EXT)) { 3282 m_freem(m); 3283 return ENOMEM; 3284 } 3285 } 3286 cmd = mtod(m, struct iwn_tx_cmd *); 3287 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3288 NULL, BUS_DMA_NOWAIT); 3289 if (error != 0) { 3290 m_freem(m); 3291 return error; 3292 } 3293 data->m = m; 3294 paddr = data->map->dm_segs[0].ds_addr; 3295 } else { 3296 cmd = &ring->cmd[ring->cur]; 3297 paddr = data->cmd_paddr; 3298 } 3299 3300 cmd->code = code; 3301 cmd->flags = 0; 3302 cmd->qid = ring->qid; 3303 cmd->idx = ring->cur; 3304 memcpy(cmd->data, buf, size); 3305 3306 desc->nsegs = 1; 3307 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3308 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3309 3310 if (size > sizeof cmd->data) { 3311 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3312 BUS_DMASYNC_PREWRITE); 3313 } else { 3314 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3315 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3316 totlen, BUS_DMASYNC_PREWRITE); 3317 } 3318 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3319 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3320 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3321 3322 /* Update TX scheduler. */ 3323 hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3324 3325 /* Kick command ring. */ 3326 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3327 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3328 3329 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3330 } 3331 3332 static int 3333 iwn_add_node(struct iwn_softc *sc, struct ieee80211_node *ni, bool broadcast, 3334 bool async, uint32_t htflags) 3335 { 3336 const struct iwn_hal *hal = sc->sc_hal; 3337 struct iwn_node_info node; 3338 int error; 3339 3340 error = 0; 3341 3342 memset(&node, 0, sizeof node); 3343 if (broadcast == true) { 3344 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3345 node.id = hal->broadcast_id; 3346 DPRINTF(("adding broadcast node\n")); 3347 } else { 3348 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 3349 node.id = IWN_ID_BSS; 3350 node.htflags = htole32(htflags); 3351 DPRINTF(("adding BSS node\n")); 3352 } 3353 if ((error = hal->add_node(sc, &node, async)) != 0) { 3354 aprint_error_dev(sc->sc_dev, "could not add %s node\n", 3355 (broadcast == 1)? "broadcast" : "BSS"); 3356 return error; 3357 } 3358 DPRINTF(("setting link quality for node %d\n", node.id)); 3359 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 3360 aprint_error_dev(sc->sc_dev, 3361 "could not setup MRR for %s node\n", 3362 (broadcast == 1)? "broadcast" : "BSS"); 3363 return error; 3364 } 3365 if ((error = iwn_init_sensitivity(sc)) != 0) { 3366 aprint_error_dev(sc->sc_dev, "could not set sensitivity\n"); 3367 return error; 3368 } 3369 3370 return error; 3371 } 3372 3373 3374 static int 3375 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3376 { 3377 struct iwn4965_node_info hnode; 3378 char *src, *dst; 3379 3380 /* 3381 * We use the node structure for 5000 Series internally (it is 3382 * a superset of the one for 4965AGN). We thus copy the common 3383 * fields before sending the command. 3384 */ 3385 src = (char *)node; 3386 dst = (char *)&hnode; 3387 memcpy(dst, src, 48); 3388 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3389 memcpy(dst + 48, src + 72, 20); 3390 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3391 } 3392 3393 static int 3394 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3395 { 3396 /* Direct mapping. */ 3397 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3398 } 3399 3400 static int 3401 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3402 { 3403 struct iwn_node *wn = (void *)ni; 3404 struct ieee80211_rateset *rs = &ni->ni_rates; 3405 struct iwn_cmd_link_quality linkq; 3406 const struct iwn_rate *rinfo; 3407 uint8_t txant; 3408 int i, txrate; 3409 3410 /* Use the first valid TX antenna. */ 3411 txant = IWN_LSB(sc->txantmsk); 3412 3413 memset(&linkq, 0, sizeof linkq); 3414 linkq.id = wn->id; 3415 linkq.antmsk_1stream = txant; 3416 linkq.antmsk_2stream = IWN_ANT_A | IWN_ANT_B; 3417 linkq.ampdu_max = 64; 3418 linkq.ampdu_threshold = 3; 3419 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3420 3421 /* Start at highest available bit-rate. */ 3422 txrate = rs->rs_nrates - 1; 3423 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3424 rinfo = &iwn_rates[wn->ridx[txrate]]; 3425 linkq.retry[i].plcp = rinfo->plcp; 3426 linkq.retry[i].rflags = rinfo->flags; 3427 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3428 /* Next retry at immediate lower bit-rate. */ 3429 if (txrate > 0) 3430 txrate--; 3431 } 3432 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3433 } 3434 3435 /* 3436 * Broadcast node is used to send group-addressed and management frames. 3437 */ 3438 static int 3439 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3440 { 3441 const struct iwn_hal *hal = sc->sc_hal; 3442 struct iwn_node_info node; 3443 struct iwn_cmd_link_quality linkq; 3444 const struct iwn_rate *rinfo; 3445 uint8_t txant; 3446 int i, error; 3447 3448 memset(&node, 0, sizeof node); 3449 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3450 node.id = hal->broadcast_id; 3451 DPRINTF(("adding broadcast node\n")); 3452 if ((error = hal->add_node(sc, &node, async)) != 0) 3453 return error; 3454 3455 /* Use the first valid TX antenna. */ 3456 txant = IWN_LSB(sc->txantmsk); 3457 3458 memset(&linkq, 0, sizeof linkq); 3459 linkq.id = hal->broadcast_id; 3460 linkq.antmsk_1stream = txant; 3461 linkq.antmsk_2stream = IWN_ANT_A | IWN_ANT_B; 3462 linkq.ampdu_max = 64; 3463 linkq.ampdu_threshold = 3; 3464 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3465 3466 /* Use lowest mandatory bit-rate. */ 3467 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3468 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3469 linkq.retry[0].plcp = rinfo->plcp; 3470 linkq.retry[0].rflags = rinfo->flags; 3471 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3472 /* Use same bit-rate for all TX retries. */ 3473 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3474 linkq.retry[i].plcp = linkq.retry[0].plcp; 3475 linkq.retry[i].rflags = linkq.retry[0].rflags; 3476 } 3477 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3478 } 3479 3480 #ifdef notyet 3481 static void 3482 iwn_updateedca(struct ieee80211com *ic) 3483 { 3484 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 3485 struct iwn_softc *sc = ic->ic_softc; 3486 struct iwn_edca_params cmd; 3487 int aci; 3488 3489 memset(&cmd, 0, sizeof cmd); 3490 cmd.flags = htole32(IWN_EDCA_UPDATE); 3491 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 3492 const struct ieee80211_edca_ac_params *ac = 3493 &ic->ic_edca_ac[aci]; 3494 cmd.ac[aci].aifsn = ac->ac_aifsn; 3495 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin)); 3496 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax)); 3497 cmd.ac[aci].txoplimit = 3498 htole16(IEEE80211_TXOP_TO_US(ac->ac_txoplimit)); 3499 } 3500 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 3501 #undef IWN_EXP2 3502 } 3503 #endif 3504 3505 static void 3506 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3507 { 3508 struct iwn_cmd_led led; 3509 3510 /* Clear microcode LED ownership. */ 3511 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3512 3513 led.which = which; 3514 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3515 led.off = off; 3516 led.on = on; 3517 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3518 } 3519 3520 /* 3521 * Set the critical temperature at which the firmware will notify us. 3522 */ 3523 static int 3524 iwn_set_critical_temp(struct iwn_softc *sc) 3525 { 3526 struct iwn_critical_temp crit; 3527 3528 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3529 3530 memset(&crit, 0, sizeof crit); 3531 crit.tempR = htole32(sc->critical_temp); 3532 DPRINTF(("setting critical temperature to %u\n", sc->critical_temp)); 3533 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3534 } 3535 3536 static int 3537 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3538 { 3539 struct iwn_cmd_timing cmd; 3540 uint64_t val, mod; 3541 3542 memset(&cmd, 0, sizeof cmd); 3543 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3544 cmd.bintval = htole16(ni->ni_intval); 3545 cmd.lintval = htole16(10); 3546 3547 /* Compute remaining time until next beacon. */ 3548 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3549 mod = le64toh(cmd.tstamp) % val; 3550 cmd.binitval = htole32((uint32_t)(val - mod)); 3551 3552 DPRINTF(("timing bintval=%u, tstamp=%llu, init=%u\n", 3553 ni->ni_intval, (unsigned long long)le64toh(cmd.tstamp), 3554 (uint32_t)(val - mod))); 3555 3556 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3557 } 3558 3559 #if 0 3560 static void 3561 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3562 { 3563 /* Adjust TX power if need be (delta >= 3 degC.) */ 3564 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3565 if (abs(temp - sc->temp) >= 3) { 3566 /* Record temperature of last calibration. */ 3567 sc->temp = temp; 3568 (void)iwn4965_set_txpower(sc, 1); 3569 } 3570 } 3571 #endif 3572 3573 /* 3574 * Set TX power for current channel (each rate has its own power settings). 3575 * This function takes into account the regulatory information from EEPROM, 3576 * the current temperature and the current voltage. 3577 */ 3578 static int 3579 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3580 { 3581 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3582 #define fdivround(a, b, n) \ 3583 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3584 /* Linear interpolation. */ 3585 #define interpolate(x, x1, y1, x2, y2, n) \ 3586 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3587 3588 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3589 struct ieee80211com *ic = &sc->sc_ic; 3590 struct iwn_ucode_info *uc = &sc->ucode_info; 3591 struct ieee80211_channel *ch; 3592 struct iwn4965_cmd_txpower cmd; 3593 struct iwn4965_eeprom_chan_samples *chans; 3594 const uint8_t *rf_gain, *dsp_gain; 3595 int32_t vdiff, tdiff; 3596 int i, c, grp, maxpwr; 3597 uint8_t chan; 3598 3599 /* Retrieve current channel from last RXON. */ 3600 chan = sc->rxon.chan; 3601 DPRINTF(("setting TX power for channel %d\n", chan)); 3602 ch = &ic->ic_channels[chan]; 3603 3604 memset(&cmd, 0, sizeof cmd); 3605 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3606 cmd.chan = chan; 3607 3608 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3609 maxpwr = sc->maxpwr5GHz; 3610 rf_gain = iwn4965_rf_gain_5ghz; 3611 dsp_gain = iwn4965_dsp_gain_5ghz; 3612 } else { 3613 maxpwr = sc->maxpwr2GHz; 3614 rf_gain = iwn4965_rf_gain_2ghz; 3615 dsp_gain = iwn4965_dsp_gain_2ghz; 3616 } 3617 3618 /* Compute voltage compensation. */ 3619 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3620 if (vdiff > 0) 3621 vdiff *= 2; 3622 if (abs(vdiff) > 2) 3623 vdiff = 0; 3624 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3625 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3626 3627 /* Get channel's attenuation group. */ 3628 if (chan <= 20) /* 1-20 */ 3629 grp = 4; 3630 else if (chan <= 43) /* 34-43 */ 3631 grp = 0; 3632 else if (chan <= 70) /* 44-70 */ 3633 grp = 1; 3634 else if (chan <= 124) /* 71-124 */ 3635 grp = 2; 3636 else /* 125-200 */ 3637 grp = 3; 3638 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3639 3640 /* Get channel's sub-band. */ 3641 for (i = 0; i < IWN_NBANDS; i++) 3642 if (sc->bands[i].lo != 0 && 3643 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3644 break; 3645 chans = sc->bands[i].chans; 3646 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3647 3648 for (c = 0; c < 2; c++) { 3649 uint8_t power, gain, temp; 3650 int maxchpwr, pwr, ridx, idx; 3651 3652 power = interpolate(chan, 3653 chans[0].num, chans[0].samples[c][1].power, 3654 chans[1].num, chans[1].samples[c][1].power, 1); 3655 gain = interpolate(chan, 3656 chans[0].num, chans[0].samples[c][1].gain, 3657 chans[1].num, chans[1].samples[c][1].gain, 1); 3658 temp = interpolate(chan, 3659 chans[0].num, chans[0].samples[c][1].temp, 3660 chans[1].num, chans[1].samples[c][1].temp, 1); 3661 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3662 c, power, gain, temp)); 3663 3664 /* Compute temperature compensation. */ 3665 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3666 DPRINTF(("temperature compensation=%d (current=%d, " 3667 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3668 3669 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3670 maxchpwr = sc->maxpwr[chan] * 2; 3671 if ((ridx / 8) & 1) 3672 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3673 3674 pwr = maxpwr; 3675 3676 /* Adjust TX power based on rate. */ 3677 if ((ridx % 8) == 5) 3678 pwr -= 15; /* OFDM48: -7.5dB */ 3679 else if ((ridx % 8) == 6) 3680 pwr -= 17; /* OFDM54: -8.5dB */ 3681 else if ((ridx % 8) == 7) 3682 pwr -= 20; /* OFDM60: -10dB */ 3683 else 3684 pwr -= 10; /* Others: -5dB */ 3685 3686 /* Do not exceed channel's max TX power. */ 3687 if (pwr > maxchpwr) 3688 pwr = maxchpwr; 3689 3690 idx = gain - (pwr - power) - tdiff - vdiff; 3691 if ((ridx / 8) & 1) /* MIMO */ 3692 idx += (int32_t)le32toh(uc->atten[grp][c]); 3693 3694 if (cmd.band == 0) 3695 idx += 9; /* 5GHz */ 3696 if (ridx == IWN_RIDX_MAX) 3697 idx += 5; /* CCK */ 3698 3699 /* Make sure idx stays in a valid range. */ 3700 if (idx < 0) 3701 idx = 0; 3702 else if (idx > IWN4965_MAX_PWR_INDEX) 3703 idx = IWN4965_MAX_PWR_INDEX; 3704 3705 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3706 c, ridx, idx)); 3707 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3708 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3709 } 3710 } 3711 3712 DPRINTF(("setting TX power for chan %d\n", chan)); 3713 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3714 3715 #undef interpolate 3716 #undef fdivround 3717 } 3718 3719 static int 3720 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3721 { 3722 struct iwn5000_cmd_txpower cmd; 3723 3724 /* 3725 * TX power calibration is handled automatically by the firmware 3726 * for 5000 Series. 3727 */ 3728 memset(&cmd, 0, sizeof cmd); 3729 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3730 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3731 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3732 DPRINTF(("setting TX power\n")); 3733 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3734 } 3735 3736 /* 3737 * Retrieve the maximum RSSI (in dBm) among receivers. 3738 */ 3739 static int 3740 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3741 { 3742 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3743 uint8_t mask, agc; 3744 int rssi; 3745 3746 mask = (le16toh(phy->antenna) >> 4) & 0x7; 3747 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3748 3749 rssi = 0; 3750 if (mask & IWN_ANT_A) 3751 rssi = MAX(rssi, phy->rssi[0]); 3752 if (mask & IWN_ANT_B) 3753 rssi = MAX(rssi, phy->rssi[2]); 3754 if (mask & IWN_ANT_C) 3755 rssi = MAX(rssi, phy->rssi[4]); 3756 3757 return rssi - agc - IWN_RSSI_TO_DBM; 3758 } 3759 3760 static int 3761 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3762 { 3763 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3764 uint8_t agc; 3765 int rssi; 3766 3767 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3768 3769 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3770 le16toh(phy->rssi[1]) & 0xff); 3771 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3772 3773 return rssi - agc - IWN_RSSI_TO_DBM; 3774 } 3775 3776 /* 3777 * Retrieve the average noise (in dBm) among receivers. 3778 */ 3779 static int 3780 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3781 { 3782 int i, total, nbant, noise; 3783 3784 total = nbant = 0; 3785 for (i = 0; i < 3; i++) { 3786 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3787 continue; 3788 total += noise; 3789 nbant++; 3790 } 3791 /* There should be at least one antenna but check anyway. */ 3792 return (nbant == 0) ? -127 : (total / nbant) - 107; 3793 } 3794 3795 /* 3796 * Compute temperature (in degC) from last received statistics. 3797 */ 3798 static int 3799 iwn4965_get_temperature(struct iwn_softc *sc) 3800 { 3801 struct iwn_ucode_info *uc = &sc->ucode_info; 3802 int32_t r1, r2, r3, r4, temp; 3803 3804 r1 = le32toh(uc->temp[0].chan20MHz); 3805 r2 = le32toh(uc->temp[1].chan20MHz); 3806 r3 = le32toh(uc->temp[2].chan20MHz); 3807 r4 = le32toh(sc->rawtemp); 3808 3809 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 3810 return 0; 3811 3812 /* Sign-extend 23-bit R4 value to 32-bit. */ 3813 r4 = (r4 << 8) >> 8; 3814 /* Compute temperature in Kelvin. */ 3815 temp = (259 * (r4 - r2)) / (r3 - r1); 3816 temp = (temp * 97) / 100 + 8; 3817 3818 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3819 return IWN_KTOC(temp); 3820 } 3821 3822 static int 3823 iwn5000_get_temperature(struct iwn_softc *sc) 3824 { 3825 /* 3826 * Temperature is not used by the driver for 5000 Series because 3827 * TX power calibration is handled by firmware. We export it to 3828 * users through the sensor framework though. 3829 */ 3830 return le32toh(sc->rawtemp); 3831 } 3832 3833 /* 3834 * Initialize sensitivity calibration state machine. 3835 */ 3836 static int 3837 iwn_init_sensitivity(struct iwn_softc *sc) 3838 { 3839 const struct iwn_hal *hal = sc->sc_hal; 3840 struct iwn_calib_state *calib = &sc->calib; 3841 uint32_t flags; 3842 int error; 3843 3844 /* Reset calibration state machine. */ 3845 memset(calib, 0, sizeof (*calib)); 3846 calib->state = IWN_CALIB_STATE_INIT; 3847 calib->cck_state = IWN_CCK_STATE_HIFA; 3848 /* Set initial correlation values. */ 3849 calib->ofdm_x1 = hal->limits->min_ofdm_x1; 3850 calib->ofdm_mrc_x1 = hal->limits->min_ofdm_mrc_x1; 3851 calib->ofdm_x4 = 90; 3852 calib->ofdm_mrc_x4 = hal->limits->min_ofdm_mrc_x4; 3853 calib->cck_x4 = 125; 3854 calib->cck_mrc_x4 = hal->limits->min_cck_mrc_x4; 3855 calib->energy_cck = hal->limits->energy_cck; 3856 3857 /* Write initial sensitivity. */ 3858 if ((error = iwn_send_sensitivity(sc)) != 0) 3859 return error; 3860 3861 /* Write initial gains. */ 3862 if ((error = hal->init_gains(sc)) != 0) 3863 return error; 3864 3865 /* Request statistics at each beacon interval. */ 3866 flags = 0; 3867 DPRINTF(("sending request for statistics\n")); 3868 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3869 } 3870 3871 /* 3872 * Collect noise and RSSI statistics for the first 20 beacons received 3873 * after association and use them to determine connected antennas and 3874 * to set differential gains. 3875 */ 3876 static void 3877 iwn_collect_noise(struct iwn_softc *sc, 3878 const struct iwn_rx_general_stats *stats) 3879 { 3880 const struct iwn_hal *hal = sc->sc_hal; 3881 struct iwn_calib_state *calib = &sc->calib; 3882 uint32_t val; 3883 int i; 3884 3885 /* Accumulate RSSI and noise for all 3 antennas. */ 3886 for (i = 0; i < 3; i++) { 3887 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3888 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3889 } 3890 /* NB: We update differential gains only once after 20 beacons. */ 3891 if (++calib->nbeacons < 20) 3892 return; 3893 3894 /* Determine highest average RSSI. */ 3895 val = MAX(calib->rssi[0], calib->rssi[1]); 3896 val = MAX(calib->rssi[2], val); 3897 3898 /* Determine which antennas are connected. */ 3899 sc->antmsk = 0; 3900 for (i = 0; i < 3; i++) 3901 if (val - calib->rssi[i] <= 15 * 20) 3902 sc->antmsk |= 1 << i; 3903 /* If none of the TX antennas are connected, keep at least one. */ 3904 if ((sc->antmsk & sc->txantmsk) == 0) 3905 sc->antmsk |= IWN_LSB(sc->txantmsk); 3906 3907 (void)hal->set_gains(sc); 3908 calib->state = IWN_CALIB_STATE_RUN; 3909 3910 #ifdef notyet 3911 /* XXX Disable RX chains with no antennas connected. */ 3912 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->antmsk)); 3913 (void)iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 3914 3915 /* Enable power-saving mode if requested by user. */ 3916 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3917 (void)iwn_set_pslevel(sc, 0, 3, 1); 3918 #endif 3919 } 3920 3921 static int 3922 iwn4965_init_gains(struct iwn_softc *sc) 3923 { 3924 struct iwn_phy_calib_gain cmd; 3925 3926 memset(&cmd, 0, sizeof cmd); 3927 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3928 /* Differential gains initially set to 0 for all 3 antennas. */ 3929 DPRINTF(("setting initial differential gains\n")); 3930 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3931 } 3932 3933 static int 3934 iwn5000_init_gains(struct iwn_softc *sc) 3935 { 3936 struct iwn_phy_calib cmd; 3937 3938 if (sc->hw_type == IWN_HW_REV_TYPE_6000 || 3939 sc->hw_type == IWN_HW_REV_TYPE_6050) 3940 return 0; 3941 3942 memset(&cmd, 0, sizeof cmd); 3943 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3944 cmd.ngroups = 1; 3945 cmd.isvalid = 1; 3946 DPRINTF(("setting initial differential gains\n")); 3947 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3948 } 3949 3950 static int 3951 iwn4965_set_gains(struct iwn_softc *sc) 3952 { 3953 struct iwn_calib_state *calib = &sc->calib; 3954 struct iwn_phy_calib_gain cmd; 3955 int i, delta, noise; 3956 3957 /* Get minimal noise among connected antennas. */ 3958 noise = INT_MAX; /* NB: There's at least one antenna. */ 3959 for (i = 0; i < 3; i++) 3960 if (sc->antmsk & (1 << i)) 3961 noise = MIN(calib->noise[i], noise); 3962 3963 memset(&cmd, 0, sizeof cmd); 3964 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3965 /* Set differential gains for connected antennas. */ 3966 for (i = 0; i < 3; i++) { 3967 if (sc->antmsk & (1 << i)) { 3968 /* Compute attenuation (in unit of 1.5dB). */ 3969 delta = (noise - (int32_t)calib->noise[i]) / 30; 3970 /* NB: delta <= 0 */ 3971 /* Limit to [-4.5dB,0]. */ 3972 cmd.gain[i] = MIN(abs(delta), 3); 3973 if (delta < 0) 3974 cmd.gain[i] |= 1 << 2; /* sign bit */ 3975 } 3976 } 3977 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3978 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->antmsk)); 3979 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3980 } 3981 3982 static int 3983 iwn5000_set_gains(struct iwn_softc *sc) 3984 { 3985 struct iwn_calib_state *calib = &sc->calib; 3986 struct iwn_phy_calib_gain cmd; 3987 int i, delta; 3988 3989 if (sc->hw_type == IWN_HW_REV_TYPE_6000 || 3990 sc->hw_type == IWN_HW_REV_TYPE_6050) 3991 return 0; 3992 3993 memset(&cmd, 0, sizeof cmd); 3994 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3995 cmd.ngroups = 1; 3996 cmd.isvalid = 1; 3997 /* Set differential gains for antennas B and C. */ 3998 for (i = 1; i < 3; i++) { 3999 if (sc->antmsk & (1 << i)) { 4000 /* The delta is relative to antenna A. */ 4001 delta = ((int32_t)calib->noise[0] - 4002 (int32_t)calib->noise[i]) / 30; 4003 /* Limit to [-4.5dB,+4.5dB]. */ 4004 cmd.gain[i - 1] = MIN(abs(delta), 3); 4005 if (delta < 0) 4006 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4007 } 4008 } 4009 DPRINTF(("setting differential gains Ant B/C: %x/%x (%x)\n", 4010 cmd.gain[0], cmd.gain[1], sc->antmsk)); 4011 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4012 } 4013 4014 /* 4015 * Tune RF RX sensitivity based on the number of false alarms detected 4016 * during the last beacon period. 4017 */ 4018 static void 4019 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4020 { 4021 #define inc(val, inc, max) \ 4022 if ((val) < (max)) { \ 4023 if ((val) < (max) - (inc)) \ 4024 (val) += (inc); \ 4025 else \ 4026 (val) = (max); \ 4027 needs_update = 1; \ 4028 } 4029 #define dec(val, dec, min) \ 4030 if ((val) > (min)) { \ 4031 if ((val) > (min) + (dec)) \ 4032 (val) -= (dec); \ 4033 else \ 4034 (val) = (min); \ 4035 needs_update = 1; \ 4036 } 4037 4038 const struct iwn_hal *hal = sc->sc_hal; 4039 const struct iwn_sensitivity_limits *limits = hal->limits; 4040 struct iwn_calib_state *calib = &sc->calib; 4041 uint32_t val, rxena, fa; 4042 uint32_t energy[3], energy_min; 4043 uint8_t noise[3], noise_ref; 4044 int i, needs_update = 0; 4045 4046 /* Check that we've been enabled long enough. */ 4047 if ((rxena = le32toh(stats->general.load)) == 0) 4048 return; 4049 4050 /* Compute number of false alarms since last call for OFDM. */ 4051 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4052 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4053 fa *= 200 * 1024; /* 200TU */ 4054 4055 /* Save counters values for next call. */ 4056 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4057 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4058 4059 if (fa > 50 * rxena) { 4060 /* High false alarm count, decrease sensitivity. */ 4061 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4062 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4063 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4064 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4065 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4066 4067 } else if (fa < 5 * rxena) { 4068 /* Low false alarm count, increase sensitivity. */ 4069 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4070 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4071 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4072 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4073 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4074 } 4075 4076 /* Compute maximum noise among 3 receivers. */ 4077 for (i = 0; i < 3; i++) 4078 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4079 val = MAX(noise[0], noise[1]); 4080 val = MAX(noise[2], val); 4081 /* Insert it into our samples table. */ 4082 calib->noise_samples[calib->cur_noise_sample] = val; 4083 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4084 4085 /* Compute maximum noise among last 20 samples. */ 4086 noise_ref = calib->noise_samples[0]; 4087 for (i = 1; i < 20; i++) 4088 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4089 4090 /* Compute maximum energy among 3 receivers. */ 4091 for (i = 0; i < 3; i++) 4092 energy[i] = le32toh(stats->general.energy[i]); 4093 val = MIN(energy[0], energy[1]); 4094 val = MIN(energy[2], val); 4095 /* Insert it into our samples table. */ 4096 calib->energy_samples[calib->cur_energy_sample] = val; 4097 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4098 4099 /* Compute minimum energy among last 10 samples. */ 4100 energy_min = calib->energy_samples[0]; 4101 for (i = 1; i < 10; i++) 4102 energy_min = MAX(energy_min, calib->energy_samples[i]); 4103 energy_min += 6; 4104 4105 /* Compute number of false alarms since last call for CCK. */ 4106 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4107 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4108 fa *= 200 * 1024; /* 200TU */ 4109 4110 /* Save counters values for next call. */ 4111 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4112 calib->fa_cck = le32toh(stats->cck.fa); 4113 4114 if (fa > 50 * rxena) { 4115 /* High false alarm count, decrease sensitivity. */ 4116 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4117 calib->cck_state = IWN_CCK_STATE_HIFA; 4118 calib->low_fa = 0; 4119 4120 if (calib->cck_x4 > 160) { 4121 calib->noise_ref = noise_ref; 4122 if (calib->energy_cck > 2) 4123 dec(calib->energy_cck, 2, energy_min); 4124 } 4125 if (calib->cck_x4 < 160) { 4126 calib->cck_x4 = 161; 4127 needs_update = 1; 4128 } else 4129 inc(calib->cck_x4, 3, limits->max_cck_x4); 4130 4131 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4132 4133 } else if (fa < 5 * rxena) { 4134 /* Low false alarm count, increase sensitivity. */ 4135 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4136 calib->cck_state = IWN_CCK_STATE_LOFA; 4137 calib->low_fa++; 4138 4139 if (calib->cck_state != IWN_CCK_STATE_INIT && 4140 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4141 calib->low_fa > 100)) { 4142 inc(calib->energy_cck, 2, limits->min_energy_cck); 4143 dec(calib->cck_x4, 3, limits->min_cck_x4); 4144 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4145 } 4146 } else { 4147 /* Not worth to increase or decrease sensitivity. */ 4148 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4149 calib->low_fa = 0; 4150 calib->noise_ref = noise_ref; 4151 4152 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4153 /* Previous interval had many false alarms. */ 4154 dec(calib->energy_cck, 8, energy_min); 4155 } 4156 calib->cck_state = IWN_CCK_STATE_INIT; 4157 } 4158 4159 if (needs_update) 4160 (void)iwn_send_sensitivity(sc); 4161 #undef dec 4162 #undef inc 4163 } 4164 4165 static int 4166 iwn_send_sensitivity(struct iwn_softc *sc) 4167 { 4168 const struct iwn_hal *hal = sc->sc_hal; 4169 struct iwn_calib_state *calib = &sc->calib; 4170 struct iwn_sensitivity_cmd cmd; 4171 4172 memset(&cmd, 0, sizeof cmd); 4173 cmd.which = IWN_SENSITIVITY_WORKTBL; 4174 /* OFDM modulation. */ 4175 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4176 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4177 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4178 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4179 cmd.energy_ofdm = htole16(hal->limits->energy_ofdm); 4180 cmd.energy_ofdm_th = htole16(62); 4181 /* CCK modulation. */ 4182 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4183 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4184 cmd.energy_cck = htole16(calib->energy_cck); 4185 /* Barker modulation: use default values. */ 4186 cmd.corr_barker = htole16(190); 4187 cmd.corr_barker_mrc = htole16(390); 4188 4189 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4190 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4191 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4192 calib->energy_cck)); 4193 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4194 } 4195 4196 #if 0 4197 /* 4198 * Set STA mode power saving level (between 0 and 5). 4199 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4200 */ 4201 static int 4202 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4203 { 4204 struct iwn_pmgt_cmd cmd; 4205 const struct iwn_pmgt *pmgt; 4206 uint32_t umax, skip_dtim; 4207 pcireg_t reg; 4208 int i; 4209 4210 /* Select which PS parameters to use. */ 4211 if (dtim <= 2) 4212 pmgt = &iwn_pmgt[0][level]; 4213 else if (dtim <= 10) 4214 pmgt = &iwn_pmgt[1][level]; 4215 else 4216 pmgt = &iwn_pmgt[2][level]; 4217 4218 memset(&cmd, 0, sizeof cmd); 4219 if (level != 0) /* not CAM */ 4220 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4221 if (level == 5) 4222 cmd.flags |= htole16(IWN_PS_FAST_PD); 4223 /* Retrieve PCIe Active State Power Management (ASPM). */ 4224 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4225 sc->sc_cap_off + PCI_PCIE_LCSR); 4226 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4227 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4228 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4229 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4230 4231 if (dtim == 0) { 4232 dtim = 1; 4233 skip_dtim = 0; 4234 } else 4235 skip_dtim = pmgt->skip_dtim; 4236 if (skip_dtim != 0) { 4237 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4238 umax = pmgt->intval[4]; 4239 if (umax == (uint32_t)-1) 4240 umax = dtim * (skip_dtim + 1); 4241 else if (umax > dtim) 4242 umax = (umax / dtim) * dtim; 4243 } else 4244 umax = dtim; 4245 for (i = 0; i < 5; i++) 4246 cmd.intval[i] = htole32(MIN(umax, pmgt->intval[i])); 4247 4248 DPRINTF(("setting power saving level to %d\n", level)); 4249 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4250 } 4251 #endif 4252 4253 static int 4254 iwn_config(struct iwn_softc *sc) 4255 { 4256 const struct iwn_hal *hal = sc->sc_hal; 4257 struct ieee80211com *ic = &sc->sc_ic; 4258 struct ifnet *ifp = ic->ic_ifp; 4259 struct iwn_bluetooth bluetooth; 4260 uint16_t rxchain; 4261 int error; 4262 struct iwn_pmgt_cmd power; 4263 4264 4265 #if 0 4266 /* Set power saving level to CAM during initialization. */ 4267 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4268 aprint_error_dev(sc->sc_dev, 4269 "could not set power saving level\n"); 4270 return error; 4271 } 4272 #else 4273 /* set power mode */ 4274 memset(&power, 0, sizeof power); 4275 power.flags = htole16(/*IWN_POWER_CAM*/0 | 0x8); 4276 DPRINTF(("setting power mode\n")); 4277 error = iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &power, sizeof power, 0); 4278 if (error != 0) { 4279 aprint_error_dev(sc->sc_dev, "could not set power mode\n"); 4280 return error; 4281 } 4282 #endif 4283 4284 /* Configure bluetooth coexistence. */ 4285 memset(&bluetooth, 0, sizeof bluetooth); 4286 bluetooth.flags = 3; 4287 bluetooth.lead = 0xaa; 4288 bluetooth.kill = 1; 4289 DPRINTF(("configuring bluetooth coexistence\n")); 4290 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4291 if (error != 0) { 4292 aprint_error_dev(sc->sc_dev, 4293 "could not configure bluetooth coexistence\n"); 4294 return error; 4295 } 4296 4297 /* Configure adapter. */ 4298 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4299 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4300 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4301 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4302 /* Set default channel. */ 4303 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 4304 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4305 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4306 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4307 switch (ic->ic_opmode) { 4308 case IEEE80211_M_STA: 4309 sc->rxon.mode = IWN_MODE_STA; 4310 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4311 break; 4312 case IEEE80211_M_MONITOR: 4313 sc->rxon.mode = IWN_MODE_MONITOR; 4314 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4315 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4316 break; 4317 default: 4318 /* Should not get there. */ 4319 break; 4320 } 4321 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4322 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4323 sc->rxon.ht_single_mask = 0xff; 4324 sc->rxon.ht_dual_mask = 0xff; 4325 rxchain = IWN_RXCHAIN_VALID(IWN_ANT_ABC) | IWN_RXCHAIN_IDLE_COUNT(2) | 4326 IWN_RXCHAIN_MIMO_COUNT(2); 4327 sc->rxon.rxchain = htole16(rxchain); 4328 DPRINTF(("setting configuration\n")); 4329 #ifdef notdef 4330 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4331 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4332 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4333 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4334 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 4335 #endif 4336 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4337 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4338 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 0); 4339 if (error != 0) { 4340 aprint_error_dev(sc->sc_dev, "configure command failed\n"); 4341 return error; 4342 } 4343 4344 /* Configuration has changed, set TX power accordingly. */ 4345 if ((error = hal->set_txpower(sc, 0)) != 0) { 4346 aprint_error_dev(sc->sc_dev, "could not set TX power\n"); 4347 return error; 4348 } 4349 4350 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4351 aprint_error_dev(sc->sc_dev, "could not add broadcast node\n"); 4352 return error; 4353 } 4354 4355 if ((error = iwn_set_critical_temp(sc)) != 0) { 4356 aprint_error_dev(sc->sc_dev, 4357 "could not set critical temperature\n"); 4358 return error; 4359 } 4360 return 0; 4361 } 4362 4363 static int 4364 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4365 { 4366 struct ieee80211com *ic = &sc->sc_ic; 4367 struct iwn_scan_hdr *hdr; 4368 struct iwn_cmd_data *tx; 4369 struct iwn_scan_chan *chan; 4370 struct ieee80211_frame *wh; 4371 struct ieee80211_rateset *rs; 4372 struct ieee80211_channel *c; 4373 enum ieee80211_phymode mode; 4374 uint8_t *buf, *frm; 4375 uint16_t rxchain; 4376 uint8_t txant; 4377 int buflen, error, nrates; 4378 4379 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4380 if (buf == NULL) { 4381 aprint_error_dev(sc->sc_dev, 4382 "could not allocate buffer for scan command\n"); 4383 return ENOMEM; 4384 } 4385 hdr = (struct iwn_scan_hdr *)buf; 4386 /* 4387 * Move to the next channel if no frames are received within 10ms 4388 * after sending the probe request. 4389 */ 4390 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4391 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4392 4393 /* Select antennas for scanning. */ 4394 rxchain = IWN_RXCHAIN_FORCE | IWN_RXCHAIN_VALID(IWN_ANT_ABC) | 4395 IWN_RXCHAIN_MIMO(IWN_ANT_ABC); 4396 if ((flags & IEEE80211_CHAN_5GHZ) && 4397 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4398 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4399 rxchain |= IWN_RXCHAIN_SEL(IWN_ANT_B | IWN_ANT_C); 4400 } else /* Use all available RX antennas. */ 4401 rxchain |= IWN_RXCHAIN_SEL(IWN_ANT_ABC); 4402 hdr->rxchain = htole16(rxchain); 4403 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4404 4405 tx = &(hdr->tx_cmd); 4406 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4407 tx->id = sc->sc_hal->broadcast_id; 4408 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4409 4410 if (flags & IEEE80211_CHAN_5GHZ) { 4411 hdr->crc_threshold = htole16(1); 4412 /* Send probe requests at 6Mbps. */ 4413 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4414 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4415 } else { 4416 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4417 /* Send probe requests at 1Mbps. */ 4418 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4419 tx->rflags = IWN_RFLAG_CCK; 4420 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4421 } 4422 /* Use the first valid TX antenna. */ 4423 txant = IWN_LSB(sc->txantmsk); 4424 tx->rflags |= IWN_RFLAG_ANT(txant); 4425 4426 if (ic->ic_des_esslen != 0) { 4427 hdr->scan_essid[0].id = IEEE80211_ELEMID_SSID; 4428 hdr->scan_essid[0].len = ic->ic_des_esslen; 4429 memcpy(hdr->scan_essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4430 } 4431 /* 4432 * Build a probe request frame. Most of the following code is a 4433 * copy & paste of what is done in net80211. 4434 */ 4435 wh = &(hdr->wh); 4436 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4437 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4438 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4439 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4440 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4441 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4442 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4443 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4444 4445 frm = &(hdr->data[0]); 4446 /* add empty SSID IE */ 4447 *frm++ = IEEE80211_ELEMID_SSID; 4448 *frm++ = 0; 4449 4450 mode = ieee80211_chan2mode(ic, ic->ic_ibss_chan); 4451 rs = &ic->ic_sup_rates[mode]; 4452 4453 /* add supported rates IE */ 4454 *frm++ = IEEE80211_ELEMID_RATES; 4455 nrates = rs->rs_nrates; 4456 if (nrates > IEEE80211_RATE_SIZE) 4457 nrates = IEEE80211_RATE_SIZE; 4458 *frm++ = nrates; 4459 memcpy(frm, rs->rs_rates, nrates); 4460 frm += nrates; 4461 4462 if (rs->rs_nrates > IEEE80211_RATE_SIZE) { 4463 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 4464 *frm++ = IEEE80211_ELEMID_XRATES; 4465 *frm++ = nrates; 4466 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 4467 frm += nrates; 4468 } 4469 4470 /* Set length of probe request. */ 4471 tx->len = htole16(frm - (uint8_t *)wh); 4472 4473 chan = (struct iwn_scan_chan *)frm; 4474 for (c = &ic->ic_channels[1]; 4475 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4476 if ((c->ic_flags & flags) != flags) 4477 continue; 4478 4479 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4480 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4481 chan->flags = 0; 4482 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4483 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4484 if (ic->ic_des_esslen != 0) 4485 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4486 chan->dsp_gain = 0x6e; 4487 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4488 chan->rf_gain = 0x3b; 4489 chan->active = htole16(24); 4490 chan->passive = htole16(110); 4491 } else { 4492 chan->rf_gain = 0x28; 4493 chan->active = htole16(36); 4494 chan->passive = htole16(120); 4495 } 4496 hdr->nchan++; 4497 chan++; 4498 } 4499 4500 buflen = (uint8_t *)chan - buf; 4501 hdr->len = htole16(buflen); 4502 4503 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4504 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4505 free(buf, M_DEVBUF); 4506 return error; 4507 } 4508 4509 static int 4510 iwn_auth(struct iwn_softc *sc) 4511 { 4512 const struct iwn_hal *hal = sc->sc_hal; 4513 struct ieee80211com *ic = &sc->sc_ic; 4514 struct ieee80211_node *ni = ic->ic_bss; 4515 int error; 4516 4517 sc->calib.state = IWN_CALIB_STATE_INIT; 4518 4519 /* Update adapter's configuration. */ 4520 sc->rxon.associd = 0; 4521 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4522 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan)); 4523 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4524 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4525 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4526 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4527 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4528 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4529 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4530 switch (ic->ic_curmode) { 4531 case IEEE80211_MODE_11A: 4532 sc->rxon.cck_mask = 0; 4533 sc->rxon.ofdm_mask = 0x15; 4534 break; 4535 case IEEE80211_MODE_11B: 4536 sc->rxon.cck_mask = 0x03; 4537 sc->rxon.ofdm_mask = 0; 4538 break; 4539 default: /* Assume 802.11b/g. */ 4540 sc->rxon.cck_mask = 0x0f; 4541 sc->rxon.ofdm_mask = 0x15; 4542 break; 4543 } 4544 #if 1 4545 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4546 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4547 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 4548 if (error != 0) { 4549 aprint_error_dev(sc->sc_dev, "could not configure\n"); 4550 return error; 4551 } 4552 4553 /* Configuration has changed, set TX power accordingly. */ 4554 if ((error = hal->set_txpower(sc, 1)) != 0) { 4555 aprint_error_dev(sc->sc_dev, "could not set TX power\n"); 4556 return error; 4557 } 4558 /* 4559 * Reconfiguring RXON clears the firmware's nodes table so we must 4560 * add the broadcast node again. 4561 */ 4562 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4563 aprint_error_dev(sc->sc_dev, "could not add broadcast node\n"); 4564 return error; 4565 } 4566 #else 4567 /* iwn_enable_tsf(sc, ni);*/ 4568 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4569 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4570 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4571 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4572 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 4573 4574 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4575 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4576 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 4577 if (error != 0) { 4578 aprint_error_dev(sc->sc_dev, "could not configure\n"); 4579 return error; 4580 } 4581 4582 /* Configuration has changed, set TX power accordingly. */ 4583 if ((error = hal->set_txpower(sc, 1)) != 0) { 4584 aprint_error_dev(sc->sc_dev, "could not set TX power\n"); 4585 return error; 4586 } 4587 /* 4588 * Reconfiguring RXON clears the firmware's nodes table so we must 4589 * add the broadcast node again. 4590 */ 4591 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4592 aprint_error_dev(sc->sc_dev, "could not add broadcast node\n"); 4593 return error; 4594 } 4595 /* add BSS node */ 4596 DPRINTF(("adding BSS node from auth\n")); 4597 if ((error = iwn_add_node(sc, ni, false, true, 0)) != 0) 4598 return error; 4599 4600 if (ic->ic_opmode == IEEE80211_M_STA) { 4601 /* fake a join to init the tx rate */ 4602 iwn_newassoc(ni, 1); 4603 } 4604 4605 if ((error = iwn_init_sensitivity(sc)) != 0) { 4606 aprint_error_dev(sc->sc_dev, "could not set sensitivity\n"); 4607 return error; 4608 } 4609 #endif 4610 return 0; 4611 } 4612 4613 static int 4614 iwn_run(struct iwn_softc *sc) 4615 { 4616 const struct iwn_hal *hal = sc->sc_hal; 4617 struct ieee80211com *ic = &sc->sc_ic; 4618 struct ieee80211_node *ni = ic->ic_bss; 4619 int error; 4620 4621 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4622 /* Link LED blinks while monitoring. */ 4623 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4624 return 0; 4625 } 4626 if ((error = iwn_set_timing(sc, ni)) != 0) { 4627 aprint_error_dev(sc->sc_dev, "could not set timing\n"); 4628 return error; 4629 } 4630 4631 /* Update adapter's configuration. */ 4632 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4633 /* Short preamble and slot time are negotiated when associating. */ 4634 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4635 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4636 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4637 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4638 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4639 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4640 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4641 error = iwn_cmd(sc, IWN_CMD_CONFIGURE, &sc->rxon, hal->rxonsz, 1); 4642 if (error != 0) { 4643 aprint_error_dev(sc->sc_dev, 4644 "could not update configuration\n"); 4645 return error; 4646 } 4647 4648 /* Configuration has changed, set TX power accordingly. */ 4649 if ((error = hal->set_txpower(sc, 1)) != 0) { 4650 aprint_error_dev(sc->sc_dev, "could not set TX power\n"); 4651 return error; 4652 } 4653 4654 /* Fake a join to initialize the TX rate. */ 4655 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4656 iwn_newassoc(ni, 1); 4657 4658 /* Add BSS node. */ 4659 iwn_add_node(sc, ni, false, true, 0); 4660 /* Start periodic calibration timer. */ 4661 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4662 sc->calib_cnt = 0; 4663 callout_schedule(&sc->calib_to, hz / 2); 4664 4665 /* Link LED always on while associated. */ 4666 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4667 return 0; 4668 } 4669 4670 static int 4671 iwn_wme_update(struct ieee80211com *ic) 4672 { 4673 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4674 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4675 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4676 const struct wmeParams *wmep; 4677 struct iwn_edca_params cmd; 4678 int ac; 4679 4680 /* don't override default WME values if WME is not actually enabled */ 4681 if (!(ic->ic_flags & IEEE80211_F_WME)) 4682 return 0; 4683 cmd.flags = 0; 4684 for (ac = 0; ac < WME_NUM_AC; ac++) { 4685 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4686 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4687 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4688 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4689 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4690 4691 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4692 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4693 cmd.ac[ac].cwmin, 4694 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4695 } 4696 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4697 #undef IWN_USEC 4698 #undef IWN_EXP2 4699 } 4700 4701 #if 0 4702 /* 4703 * We support CCMP hardware encryption/decryption of unicast frames only. 4704 * HW support for TKIP really sucks. We should let TKIP die anyway. 4705 */ 4706 static int 4707 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4708 struct ieee80211_key *k) 4709 { 4710 struct iwn_softc *sc = ic->ic_softc; 4711 const struct iwn_hal *hal = sc->sc_hal; 4712 struct iwn_node *wn = (void *)ni; 4713 struct iwn_node_info node; 4714 uint16_t kflags; 4715 4716 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4717 k->k_cipher != IEEE80211_CIPHER_CCMP) 4718 return ieee80211_set_key(ic, ni, k); 4719 4720 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4721 if (k->k_flags & IEEE80211_KEY_GROUP) 4722 kflags |= IWN_KFLAG_GROUP; 4723 4724 memset(&node, 0, sizeof node); 4725 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4726 hal->broadcast_id : wn->id; 4727 node.control = IWN_NODE_UPDATE; 4728 node.flags = IWN_FLAG_SET_KEY; 4729 node.kflags = htole16(kflags); 4730 node.kid = k->k_id; 4731 memcpy(node.key, k->k_key, k->k_len); 4732 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4733 return hal->add_node(sc, &node, 1); 4734 } 4735 4736 static void 4737 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4738 struct ieee80211_key *k) 4739 { 4740 struct iwn_softc *sc = ic->ic_softc; 4741 const struct iwn_hal *hal = sc->sc_hal; 4742 struct iwn_node *wn = (void *)ni; 4743 struct iwn_node_info node; 4744 4745 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4746 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4747 /* See comment about other ciphers above. */ 4748 ieee80211_delete_key(ic, ni, k); 4749 return; 4750 } 4751 if (ic->ic_state != IEEE80211_S_RUN) 4752 return; /* Nothing to do. */ 4753 memset(&node, 0, sizeof node); 4754 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4755 hal->broadcast_id : wn->id; 4756 node.control = IWN_NODE_UPDATE; 4757 node.flags = IWN_FLAG_SET_KEY; 4758 node.kflags = htole16(IWN_KFLAG_INVALID); 4759 node.kid = 0xff; 4760 DPRINTF(("delete keys for node %d\n", node.id)); 4761 (void)hal->add_node(sc, &node, 1); 4762 } 4763 #endif 4764 4765 #ifndef IEEE80211_NO_HT 4766 /* 4767 * This function is called by upper layer when a ADDBA request is received 4768 * from another STA and before the ADDBA response is sent. 4769 */ 4770 static int 4771 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4772 uint8_t tid, uint16_t ssn) 4773 { 4774 struct iwn_softc *sc = ic->ic_softc; 4775 struct iwn_node *wn = (void *)ni; 4776 struct iwn_node_info node; 4777 4778 memset(&node, 0, sizeof node); 4779 node.id = wn->id; 4780 node.control = IWN_NODE_UPDATE; 4781 node.flags = IWN_FLAG_SET_ADDBA; 4782 node.addba_tid = tid; 4783 node.addba_ssn = htole16(ssn); 4784 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, ssn)); 4785 return sc->sc_hal->add_node(sc, &node, 1); 4786 } 4787 4788 /* 4789 * This function is called by upper layer on teardown of an HT-immediate 4790 * Block Ack (eg. uppon receipt of a DELBA frame.) 4791 */ 4792 static void 4793 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4794 uint8_t tid, uint16_t ssn) 4795 { 4796 struct iwn_softc *sc = ic->ic_softc; 4797 struct iwn_node *wn = (void *)ni; 4798 struct iwn_node_info node; 4799 4800 memset(&node, 0, sizeof node); 4801 node.id = wn->id; 4802 node.control = IWN_NODE_UPDATE; 4803 node.flags = IWN_FLAG_SET_DELBA; 4804 node.delba_tid = tid; 4805 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4806 (void)sc->sc_hal->add_node(sc, &node, 1); 4807 } 4808 4809 /* 4810 * This function is called by upper layer when a ADDBA response is received 4811 * from another STA. 4812 */ 4813 static int 4814 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4815 uint8_t tid, uint16_t ssn) 4816 { 4817 struct iwn_softc *sc = ic->ic_softc; 4818 const struct iwn_hal *hal = sc->sc_hal; 4819 struct iwn_node *wn = (void *)ni; 4820 struct iwn_node_info node; 4821 int error; 4822 4823 /* Enable TX for the specified RA/TID. */ 4824 wn->disable_tid &= ~(1 << tid); 4825 memset(&node, 0, sizeof node); 4826 node.id = wn->id; 4827 node.control = IWN_NODE_UPDATE; 4828 node.flags = IWN_FLAG_SET_DISABLE_TID; 4829 node.disable_tid = htole16(wn->disable_tid); 4830 error = hal->add_node(sc, &node, 1); 4831 if (error != 0) 4832 return error; 4833 4834 if ((error = iwn_nic_lock(sc)) != 0) 4835 return error; 4836 hal->ampdu_tx_start(sc, ni, tid, ssn); 4837 iwn_nic_unlock(sc); 4838 return 0; 4839 } 4840 4841 static void 4842 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4843 uint8_t tid, uint16_t ssn) 4844 { 4845 struct iwn_softc *sc = ic->ic_softc; 4846 4847 if (iwn_nic_lock(sc) != 0) 4848 return; 4849 sc->sc_hal->ampdu_tx_stop(sc, tid, ssn); 4850 iwn_nic_unlock(sc); 4851 } 4852 4853 static void 4854 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4855 uint8_t tid, uint16_t ssn) 4856 { 4857 struct iwn_node *wn = (void *)ni; 4858 int qid = 7 + tid; 4859 4860 /* Stop TX scheduler while we're changing its configuration. */ 4861 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4862 IWN4965_TXQ_STATUS_CHGACT); 4863 4864 /* Assign RA/TID translation to the queue. */ 4865 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4866 wn->id << 4 | tid); 4867 4868 /* Enable chain mode for the queue. */ 4869 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4870 4871 /* Set starting sequence number from the ADDBA request. */ 4872 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4873 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4874 4875 /* Set scheduler window size. */ 4876 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4877 IWN_SCHED_WINSZ); 4878 /* Set scheduler frame limit. */ 4879 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4880 IWN_SCHED_LIMIT << 16); 4881 4882 /* Enable interrupts for the queue. */ 4883 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4884 4885 /* Mark the queue as active. */ 4886 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4887 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4888 iwn_tid2fifo[tid] << 1); 4889 } 4890 4891 static void 4892 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4893 { 4894 int qid = 7 + tid; 4895 4896 /* Stop TX scheduler while we're changing its configuration. */ 4897 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4898 IWN4965_TXQ_STATUS_CHGACT); 4899 4900 /* Set starting sequence number from the ADDBA request. */ 4901 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4902 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4903 4904 /* Disable interrupts for the queue. */ 4905 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4906 4907 /* Mark the queue as inactive. */ 4908 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4909 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4910 } 4911 4912 static void 4913 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4914 uint8_t tid, uint16_t ssn) 4915 { 4916 struct iwn_node *wn = (void *)ni; 4917 int qid = 10 + tid; 4918 4919 /* Stop TX scheduler while we're changing its configuration. */ 4920 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4921 IWN5000_TXQ_STATUS_CHGACT); 4922 4923 /* Assign RA/TID translation to the queue. */ 4924 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4925 wn->id << 4 | tid); 4926 4927 /* Enable chain mode for the queue. */ 4928 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4929 4930 /* Enable aggregation for the queue. */ 4931 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4932 4933 /* Set starting sequence number from the ADDBA request. */ 4934 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4935 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4936 4937 /* Set scheduler window size and frame limit. */ 4938 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4939 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4940 4941 /* Enable interrupts for the queue. */ 4942 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4943 4944 /* Mark the queue as active. */ 4945 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4946 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4947 } 4948 4949 static void 4950 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4951 { 4952 int qid = 10 + tid; 4953 4954 /* Stop TX scheduler while we're changing its configuration. */ 4955 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4956 IWN5000_TXQ_STATUS_CHGACT); 4957 4958 /* Disable aggregation for the queue. */ 4959 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4960 4961 /* Set starting sequence number from the ADDBA request. */ 4962 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ssn); 4963 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4964 4965 /* Disable interrupts for the queue. */ 4966 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4967 4968 /* Mark the queue as inactive. */ 4969 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4970 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4971 } 4972 #endif /* 0 */ 4973 4974 /* 4975 * Query calibration tables from the initialization firmware. We do this 4976 * only once at first boot. Called from a process context. 4977 */ 4978 static int 4979 iwn5000_query_calibration(struct iwn_softc *sc) 4980 { 4981 struct iwn5000_calib_config cmd; 4982 int error; 4983 4984 memset(&cmd, 0, sizeof cmd); 4985 cmd.ucode.once.enable = 0xffffffff; 4986 cmd.ucode.once.start = 0xffffffff; 4987 cmd.ucode.once.send = 0xffffffff; 4988 cmd.ucode.flags = 0xffffffff; 4989 DPRINTF(("sending calibration query\n")); 4990 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4991 if (error != 0) 4992 return error; 4993 4994 /* Wait at most two seconds for calibration to complete. */ 4995 return tsleep(sc, PCATCH, "iwncal", 2 * hz); 4996 } 4997 4998 /* 4999 * Send calibration results to the runtime firmware. These results were 5000 * obtained on first boot from the initialization firmware. 5001 */ 5002 static int 5003 iwn5000_send_calibration(struct iwn_softc *sc) 5004 { 5005 int idx, error; 5006 5007 for (idx = 0; idx < 5; idx++) { 5008 if (sc->calibcmd[idx].buf == NULL) 5009 continue; /* No results available. */ 5010 DPRINTF(("send calibration result idx=%d len=%d\n", 5011 idx, sc->calibcmd[idx].len)); 5012 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5013 sc->calibcmd[idx].len, 0); 5014 if (error != 0) { 5015 aprint_error_dev(sc->sc_dev, 5016 "could not send calibration result\n"); 5017 return error; 5018 } 5019 } 5020 return 0; 5021 } 5022 5023 /* 5024 * This function is called after the runtime firmware notifies us of its 5025 * readiness (called in a process context.) 5026 */ 5027 static int 5028 iwn4965_post_alive(struct iwn_softc *sc) 5029 { 5030 int error, qid; 5031 5032 if ((error = iwn_nic_lock(sc)) != 0) 5033 return error; 5034 5035 /* Clear TX scheduler's state in SRAM. */ 5036 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5037 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5038 IWN4965_SCHED_CTX_LEN); 5039 5040 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5041 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5042 5043 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5044 5045 /* Disable chain mode for all our 16 queues. */ 5046 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5047 5048 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5049 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5050 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5051 5052 /* Set scheduler window size. */ 5053 iwn_mem_write(sc, sc->sched_base + 5054 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5055 /* Set scheduler frame limit. */ 5056 iwn_mem_write(sc, sc->sched_base + 5057 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5058 IWN_SCHED_LIMIT << 16); 5059 } 5060 5061 /* Enable interrupts for all our 16 queues. */ 5062 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5063 /* Identify TX FIFO rings (0-7). */ 5064 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5065 5066 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5067 for (qid = 0; qid < 7; qid++) { 5068 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5069 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5070 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5071 } 5072 iwn_nic_unlock(sc); 5073 return 0; 5074 } 5075 5076 /* 5077 * This function is called after the initialization or runtime firmware 5078 * notifies us of its readiness (called in a process context.) 5079 */ 5080 static int 5081 iwn5000_post_alive(struct iwn_softc *sc) 5082 { 5083 struct iwn5000_wimax_coex wimax; 5084 int error, qid; 5085 5086 if ((error = iwn_nic_lock(sc)) != 0) 5087 return error; 5088 5089 /* Clear TX scheduler's state in SRAM. */ 5090 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5091 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5092 IWN5000_SCHED_CTX_LEN); 5093 5094 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5095 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5096 5097 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5098 5099 /* Enable chain mode for all our 20 queues. */ 5100 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffff); 5101 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5102 5103 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5104 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5105 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5106 5107 iwn_mem_write(sc, sc->sched_base + 5108 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5109 /* Set scheduler window size and frame limit. */ 5110 iwn_mem_write(sc, sc->sched_base + 5111 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5112 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5113 } 5114 5115 /* Enable interrupts for all our 20 queues. */ 5116 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5117 /* Identify TX FIFO rings (0-7). */ 5118 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5119 5120 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5121 for (qid = 0; qid < 7; qid++) { 5122 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5123 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5124 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5125 } 5126 iwn_nic_unlock(sc); 5127 5128 /* Configure WiMAX (IEEE 802.16e) coexistence. */ 5129 memset(&wimax, 0, sizeof wimax); 5130 DPRINTF(("Configuring WiMAX coexistence\n")); 5131 error = iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5132 if (error != 0) { 5133 aprint_error_dev(sc->sc_dev, 5134 "could not configure WiMAX coexistence\n"); 5135 return error; 5136 } 5137 5138 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5139 struct iwn5000_phy_calib_crystal cmd; 5140 5141 /* Perform crystal calibration. */ 5142 memset(&cmd, 0, sizeof cmd); 5143 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5144 cmd.ngroups = 1; 5145 cmd.isvalid = 1; 5146 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5147 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5148 DPRINTF(("sending crystal calibration %d, %d\n", 5149 cmd.cap_pin[0], cmd.cap_pin[1])); 5150 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5151 if (error != 0) { 5152 aprint_error_dev(sc->sc_dev, 5153 "crystal calibration failed\n"); 5154 return error; 5155 } 5156 } 5157 if (sc->sc_flags & IWN_FLAG_FIRST_BOOT) { 5158 /* Query calibration from the initialization firmware. */ 5159 if ((error = iwn5000_query_calibration(sc)) != 0) { 5160 aprint_error_dev(sc->sc_dev, 5161 "could not query calibration\n"); 5162 return error; 5163 } 5164 /* 5165 * We have the calibration results now so we can skip 5166 * loading the initialization firmware next time. 5167 */ 5168 sc->sc_flags &= ~IWN_FLAG_FIRST_BOOT; 5169 5170 /* Reboot (call ourselves recursively!) */ 5171 iwn_hw_stop(sc); 5172 error = iwn_hw_init(sc); 5173 } else { 5174 /* Send calibration results to runtime firmware. */ 5175 error = iwn5000_send_calibration(sc); 5176 } 5177 return error; 5178 } 5179 5180 /* 5181 * The firmware boot code is small and is intended to be copied directly into 5182 * the NIC internal memory (no DMA transfer.) 5183 */ 5184 static int 5185 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5186 { 5187 int error, ntries; 5188 5189 size /= sizeof (uint32_t); 5190 5191 if ((error = iwn_nic_lock(sc)) != 0) 5192 return error; 5193 5194 /* Copy microcode image into NIC memory. */ 5195 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5196 (const uint32_t *)ucode, size); 5197 5198 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5199 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5200 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5201 5202 /* Start boot load now. */ 5203 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5204 5205 /* Wait for transfer to complete. */ 5206 for (ntries = 0; ntries < 1000; ntries++) { 5207 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5208 IWN_BSM_WR_CTRL_START)) 5209 break; 5210 DELAY(10); 5211 } 5212 if (ntries == 1000) { 5213 aprint_error_dev(sc->sc_dev, "could not load boot firmware\n"); 5214 iwn_nic_unlock(sc); 5215 return ETIMEDOUT; 5216 } 5217 5218 /* Enable boot after power up. */ 5219 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5220 5221 iwn_nic_unlock(sc); 5222 return 0; 5223 } 5224 5225 static int 5226 iwn4965_load_firmware(struct iwn_softc *sc) 5227 { 5228 struct iwn_fw_info *fw = &sc->fw; 5229 struct iwn_dma_info *dma = &sc->fw_dma; 5230 int error; 5231 5232 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5233 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5234 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5235 BUS_DMASYNC_PREWRITE); 5236 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5237 fw->init.text, fw->init.textsz); 5238 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5239 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5240 5241 /* Tell adapter where to find initialization sections. */ 5242 if ((error = iwn_nic_lock(sc)) != 0) 5243 return error; 5244 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5245 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5246 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5247 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5248 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5249 iwn_nic_unlock(sc); 5250 5251 /* Load firmware boot code. */ 5252 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5253 if (error != 0) { 5254 aprint_error_dev(sc->sc_dev, "could not load boot firmware\n"); 5255 return error; 5256 } 5257 /* Now press "execute". */ 5258 IWN_WRITE(sc, IWN_RESET, 0); 5259 5260 /* Wait at most one second for first alive notification. */ 5261 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5262 aprint_error_dev(sc->sc_dev, 5263 "timeout waiting for adapter to initialize %d\n", error); 5264 return error; 5265 } 5266 5267 /* Retrieve current temperature for initial TX power calibration. */ 5268 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5269 sc->temp = iwn4965_get_temperature(sc); 5270 5271 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5272 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5273 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5274 BUS_DMASYNC_PREWRITE); 5275 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5276 fw->main.text, fw->main.textsz); 5277 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5278 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5279 5280 /* Tell adapter where to find runtime sections. */ 5281 if ((error = iwn_nic_lock(sc)) != 0) 5282 return error; 5283 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5284 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5285 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5286 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5287 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5288 IWN_FW_UPDATED | fw->main.textsz); 5289 iwn_nic_unlock(sc); 5290 5291 return 0; 5292 } 5293 5294 static int 5295 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5296 const uint8_t *section, int size) 5297 { 5298 struct iwn_dma_info *dma = &sc->fw_dma; 5299 int error; 5300 5301 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5302 memcpy(dma->vaddr, section, size); 5303 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5304 5305 if ((error = iwn_nic_lock(sc)) != 0) 5306 return error; 5307 5308 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_CHNL), 5309 IWN_FH_TX_CONFIG_DMA_PAUSE); 5310 5311 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_CHNL), dst); 5312 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_CHNL), 5313 IWN_LOADDR(dma->paddr)); 5314 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_CHNL), 5315 IWN_HIADDR(dma->paddr) << 28 | size); 5316 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_CHNL), 5317 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5318 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5319 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5320 5321 /* Kick Flow Handler to start DMA transfer. */ 5322 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_CHNL), 5323 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5324 5325 iwn_nic_unlock(sc); 5326 5327 /* Wait at most five seconds for FH DMA transfer to complete. */ 5328 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5329 } 5330 5331 static int 5332 iwn5000_load_firmware(struct iwn_softc *sc) 5333 { 5334 struct iwn_fw_part *fw; 5335 int error; 5336 5337 /* Load the initialization firmware on first boot only. */ 5338 fw = (sc->sc_flags & IWN_FLAG_FIRST_BOOT) ? 5339 &sc->fw.init : &sc->fw.main; 5340 5341 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5342 fw->text, fw->textsz); 5343 if (error != 0) { 5344 aprint_error_dev(sc->sc_dev, 5345 "could not load firmware %s section\n", 5346 ".text"); 5347 return error; 5348 } 5349 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5350 fw->data, fw->datasz); 5351 if (error != 0) { 5352 aprint_error_dev(sc->sc_dev, 5353 "could not load firmware %s section\n", 5354 ".data"); 5355 return error; 5356 } 5357 5358 /* Now press "execute". */ 5359 IWN_WRITE(sc, IWN_RESET, 0); 5360 return 0; 5361 } 5362 5363 static int 5364 iwn_read_firmware(struct iwn_softc *sc) 5365 { 5366 const struct iwn_hal *hal = sc->sc_hal; 5367 struct iwn_fw_info *fw = &sc->fw; 5368 struct iwn_firmware_hdr hdr; 5369 firmware_handle_t fwh; 5370 size_t size; 5371 int error; 5372 5373 /* Read firmware image from filesystem. */ 5374 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5375 aprint_error_dev(sc->sc_dev, 5376 "could not read firmware file %s\n", sc->fwname); 5377 return error; 5378 } 5379 size = firmware_get_size(fwh); 5380 if (size < sizeof (hdr)) { 5381 aprint_error_dev(sc->sc_dev, 5382 "truncated firmware header: %zu bytes\n", size); 5383 error = EINVAL; 5384 goto fail2; 5385 } 5386 /* Extract firmware header information. */ 5387 if ((error = firmware_read(fwh, 0, &hdr, 5388 sizeof (struct iwn_firmware_hdr))) != 0) { 5389 aprint_error_dev(sc->sc_dev, "can't get firmware header\n"); 5390 goto fail2; 5391 } 5392 fw->main.textsz = le32toh(hdr.main_textsz); 5393 fw->main.datasz = le32toh(hdr.main_datasz); 5394 fw->init.textsz = le32toh(hdr.init_textsz); 5395 fw->init.datasz = le32toh(hdr.init_datasz); 5396 fw->boot.textsz = le32toh(hdr.boot_textsz); 5397 fw->boot.datasz = 0; 5398 5399 /* Sanity-check firmware header. */ 5400 if (fw->main.textsz > hal->fw_text_maxsz || 5401 fw->main.datasz > hal->fw_data_maxsz || 5402 fw->init.textsz > hal->fw_text_maxsz || 5403 fw->init.datasz > hal->fw_data_maxsz || 5404 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5405 (fw->boot.textsz & 3) != 0) { 5406 aprint_error_dev(sc->sc_dev, "invalid firmware header\n"); 5407 error = EINVAL; 5408 goto fail2; 5409 } 5410 5411 /* Check that all firmware sections fit. */ 5412 if (size < sizeof (hdr) + fw->main.textsz + fw->main.datasz + 5413 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5414 aprint_error_dev(sc->sc_dev, 5415 "firmware file too short: %zu bytes\n", size); 5416 error = EINVAL; 5417 goto fail2; 5418 } 5419 fw->data = firmware_malloc(size); 5420 if (fw->data == NULL) { 5421 aprint_error_dev(sc->sc_dev, 5422 "not enough memory to stock firmware\n"); 5423 error = ENOMEM; 5424 goto fail2; 5425 } 5426 if ((error = firmware_read(fwh, 0, fw->data, size)) != 0) { 5427 aprint_error_dev(sc->sc_dev, "can't get firmware\n"); 5428 goto fail3; 5429 } 5430 5431 /* Get pointers to firmware sections. */ 5432 fw->main.text = fw->data + sizeof (struct iwn_firmware_hdr); 5433 fw->main.data = fw->main.text + fw->main.textsz; 5434 fw->init.text = fw->main.data + fw->main.datasz; 5435 fw->init.data = fw->init.text + fw->init.textsz; 5436 fw->boot.text = fw->init.data + fw->init.datasz; 5437 5438 return 0; 5439 fail3: firmware_free(fw->data, size); 5440 fail2: firmware_close(fwh); 5441 return error; 5442 } 5443 5444 static int 5445 iwn_clock_wait(struct iwn_softc *sc) 5446 { 5447 int ntries; 5448 5449 /* Set "initialization complete" bit. */ 5450 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5451 5452 /* Wait for clock stabilization. */ 5453 for (ntries = 0; ntries < 25000; ntries++) { 5454 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5455 return 0; 5456 DELAY(100); 5457 } 5458 aprint_error_dev(sc->sc_dev, 5459 "timeout waiting for clock stabilization\n"); 5460 return ETIMEDOUT; 5461 } 5462 5463 static int 5464 iwn4965_apm_init(struct iwn_softc *sc) 5465 { 5466 int error; 5467 5468 /* Disable L0s. */ 5469 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5470 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5471 5472 if ((error = iwn_clock_wait(sc)) != 0) 5473 return error; 5474 5475 if ((error = iwn_nic_lock(sc)) != 0) 5476 return error; 5477 /* Enable DMA. */ 5478 iwn_prph_write(sc, IWN_APMG_CLK_CTRL, 5479 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5480 DELAY(20); 5481 /* Disable L1. */ 5482 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5483 iwn_nic_unlock(sc); 5484 5485 return 0; 5486 } 5487 5488 static int 5489 iwn5000_apm_init(struct iwn_softc *sc) 5490 { 5491 int error; 5492 5493 /* Disable L0s. */ 5494 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5495 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5496 5497 /* Set Flow Handler wait threshold to the maximum. */ 5498 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5499 5500 /* Enable HAP to move adapter from L1a to L0s. */ 5501 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5502 5503 if (sc->hw_type != IWN_HW_REV_TYPE_6000 && 5504 sc->hw_type != IWN_HW_REV_TYPE_6050) 5505 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5506 5507 if ((error = iwn_clock_wait(sc)) != 0) 5508 return error; 5509 5510 if ((error = iwn_nic_lock(sc)) != 0) 5511 return error; 5512 /* Enable DMA. */ 5513 iwn_prph_write(sc, IWN_APMG_CLK_CTRL, IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5514 DELAY(20); 5515 /* Disable L1. */ 5516 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5517 iwn_nic_unlock(sc); 5518 5519 return 0; 5520 } 5521 5522 static void 5523 iwn_apm_stop_master(struct iwn_softc *sc) 5524 { 5525 int ntries; 5526 5527 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5528 for (ntries = 0; ntries < 100; ntries++) { 5529 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5530 return; 5531 DELAY(10); 5532 } 5533 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 5534 } 5535 5536 static void 5537 iwn_apm_stop(struct iwn_softc *sc) 5538 { 5539 iwn_apm_stop_master(sc); 5540 5541 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5542 DELAY(10); 5543 /* Clear "initialization complete" bit. */ 5544 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5545 } 5546 5547 static int 5548 iwn4965_nic_config(struct iwn_softc *sc) 5549 { 5550 pcireg_t reg; 5551 5552 /* Retrieve PCIe Active State Power Management (ASPM). */ 5553 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5554 sc->sc_cap_off + PCI_PCIE_LCSR); 5555 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5556 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5557 else 5558 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5559 5560 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5561 /* 5562 * I don't believe this to be correct but this is what the 5563 * vendor driver is doing. Probably the bits should not be 5564 * shifted in IWN_RFCFG_*. 5565 */ 5566 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5567 IWN_RFCFG_TYPE(sc->rfcfg) | 5568 IWN_RFCFG_STEP(sc->rfcfg) | 5569 IWN_RFCFG_DASH(sc->rfcfg)); 5570 } 5571 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5572 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5573 return 0; 5574 } 5575 5576 static int 5577 iwn5000_nic_config(struct iwn_softc *sc) 5578 { 5579 int error; 5580 pcireg_t reg; 5581 5582 /* Retrieve PCIe Active State Power Management (ASPM). */ 5583 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5584 sc->sc_cap_off + PCI_PCIE_LCSR); 5585 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5586 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5587 else 5588 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5589 5590 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5591 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5592 IWN_RFCFG_TYPE(sc->rfcfg) | 5593 IWN_RFCFG_STEP(sc->rfcfg) | 5594 IWN_RFCFG_DASH(sc->rfcfg)); 5595 } 5596 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5597 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5598 5599 if ((error = iwn_nic_lock(sc)) != 0) 5600 return error; 5601 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5602 iwn_nic_unlock(sc); 5603 return 0; 5604 } 5605 5606 static int 5607 iwn_hw_init(struct iwn_softc *sc) 5608 { 5609 const struct iwn_hal *hal = sc->sc_hal; 5610 int error, qid; 5611 5612 /* Clear pending interrupts. */ 5613 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5614 5615 if ((error = hal->apm_init(sc)) != 0) { 5616 aprint_error_dev(sc->sc_dev, "could not power ON adapter\n"); 5617 return error; 5618 } 5619 5620 /* Select VMAIN power source. */ 5621 if ((error = iwn_nic_lock(sc)) != 0) 5622 return error; 5623 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5624 iwn_nic_unlock(sc); 5625 5626 /* Perform adapter-specific initialization. */ 5627 if ((error = hal->nic_config(sc)) != 0) 5628 return error; 5629 5630 /* Initialize RX ring. */ 5631 if ((error = iwn_nic_lock(sc)) != 0) 5632 return error; 5633 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5634 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5635 /* Set physical address of RX ring (256-byte aligned.) */ 5636 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5637 /* Set physical address of RX status (16-byte aligned.) */ 5638 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5639 /* Enable RX. */ 5640 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5641 IWN_FH_RX_CONFIG_ENA | 5642 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5643 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5644 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5645 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5646 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5647 iwn_nic_unlock(sc); 5648 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5649 5650 if ((error = iwn_nic_lock(sc)) != 0) 5651 return error; 5652 5653 /* Initialize TX scheduler. */ 5654 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5655 5656 /* Set physical address of "keep warm" page (16-byte aligned.) */ 5657 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5658 5659 /* Initialize TX rings. */ 5660 for (qid = 0; qid < hal->ntxqs; qid++) { 5661 struct iwn_tx_ring *txq = &sc->txq[qid]; 5662 5663 /* Set physical address of TX ring (256-byte aligned.) */ 5664 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5665 txq->desc_dma.paddr >> 8); 5666 /* Enable TX for this ring. */ 5667 IWN_WRITE(sc, IWN_FH_TX_CONFIG(qid), 5668 IWN_FH_TX_CONFIG_DMA_ENA | 5669 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5670 } 5671 iwn_nic_unlock(sc); 5672 5673 /* Clear "radio off" and "commands blocked" bits. */ 5674 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5675 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5676 5677 /* Clear pending interrupts. */ 5678 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5679 /* Enable interrupt coalescing. */ 5680 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5681 /* Enable interrupts. */ 5682 IWN_WRITE(sc, IWN_MASK, IWN_INT_MASK); 5683 5684 /* _Really_ make sure "radio off" bit is cleared! */ 5685 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5686 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5687 5688 if ((error = hal->load_firmware(sc)) != 0) { 5689 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 5690 return error; 5691 } 5692 /* Wait at most one second for firmware alive notification. */ 5693 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5694 aprint_error_dev(sc->sc_dev, 5695 "timeout waiting for adapter to initialize %d\n" ,error); 5696 return error; 5697 } 5698 /* Do post-firmware initialization. */ 5699 return hal->post_alive(sc); 5700 } 5701 5702 static void 5703 iwn_hw_stop(struct iwn_softc *sc) 5704 { 5705 const struct iwn_hal *hal = sc->sc_hal; 5706 int qid; 5707 5708 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5709 5710 /* Disable interrupts. */ 5711 IWN_WRITE(sc, IWN_MASK, 0); 5712 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5713 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5714 5715 /* Make sure we no longer hold the NIC lock. */ 5716 iwn_nic_unlock(sc); 5717 5718 /* Stop TX scheduler. */ 5719 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5720 5721 /* Stop all TX rings. */ 5722 for (qid = 0; qid < hal->ntxqs; qid++) 5723 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5724 5725 /* Stop RX ring. */ 5726 iwn_reset_rx_ring(sc, &sc->rxq); 5727 5728 if (iwn_nic_lock(sc) == 0) { 5729 iwn_prph_write(sc, IWN_APMG_CLK_DIS, IWN_APMG_CLK_DMA_RQT); 5730 iwn_nic_unlock(sc); 5731 } 5732 DELAY(5); 5733 /* Power OFF adapter. */ 5734 iwn_apm_stop(sc); 5735 } 5736 5737 static int 5738 iwn_init(struct ifnet *ifp) 5739 { 5740 struct iwn_softc *sc = ifp->if_softc; 5741 struct ieee80211com *ic = &sc->sc_ic; 5742 int error; 5743 5744 /* Check that the radio is not disabled by hardware switch. */ 5745 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5746 aprint_error_dev(sc->sc_dev, 5747 "radio is disabled by hardware switch\n"); 5748 sc->sc_radio = false; 5749 error = EPERM; /* :-) */ 5750 goto fail; 5751 } 5752 sc->sc_radio = true; 5753 5754 /* Read firmware images from the filesystem. */ 5755 if ((error = iwn_read_firmware(sc)) != 0) { 5756 aprint_error_dev(sc->sc_dev, "could not read firmware\n"); 5757 goto fail; 5758 } 5759 5760 /* Initialize hardware and upload firmware. */ 5761 error = iwn_hw_init(sc); 5762 free(sc->fw.data, M_DEVBUF); 5763 if (error != 0) { 5764 aprint_error_dev(sc->sc_dev, "could not initialize hardware\n"); 5765 goto fail; 5766 } 5767 5768 /* Configure adapter now that it is ready. */ 5769 if ((error = iwn_config(sc)) != 0) { 5770 aprint_error_dev(sc->sc_dev, "could not configure device\n"); 5771 goto fail; 5772 } 5773 5774 ifp->if_flags &= ~IFF_OACTIVE; 5775 ifp->if_flags |= IFF_RUNNING; 5776 5777 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 5778 if (ic->ic_opmode != IEEE80211_ROAMING_MANUAL) 5779 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5780 } else 5781 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5782 5783 return 0; 5784 5785 fail: iwn_stop(ifp, 1); 5786 return error; 5787 } 5788 5789 static void 5790 iwn_stop(struct ifnet *ifp, int disable) 5791 { 5792 struct iwn_softc *sc = ifp->if_softc; 5793 struct ieee80211com *ic = &sc->sc_ic; 5794 5795 ifp->if_timer = sc->sc_tx_timer = 0; 5796 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5797 5798 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5799 5800 /* Power OFF hardware. */ 5801 iwn_hw_stop(sc); 5802 5803 #if 0 5804 /* Temperature sensor is no longer valid. */ 5805 sc->sensor.value = 0; 5806 sc->sensor.flags |= SENSOR_FINVALID; 5807 #endif 5808 } 5809 5810 static bool 5811 iwn_resume(device_t dv, pmf_qual_t qual) 5812 { 5813 #if 0 5814 struct iwn_softc *sc = device_private(dv); 5815 5816 (void)iwn_reset(sc); 5817 #endif 5818 5819 return true; 5820 } 5821
Indexes created Mon Sep 29 03:10:08 GMT 2025