if_iwn.c revision 1.44
1 /* $NetBSD: if_iwn.c,v 1.44 2010/05/02 02:06:15 christos Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.88 2010/04/10 08:37:36 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.44 2010/05/02 02:06:15 christos Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 /* XXX Avoid sensor code (correct option for NetBSD too?) */ 31 #undef SMALL_KERNEL 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <machine/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 /* XXX From old NetBSD iwn driver (used by pcidevs) */ 80 PCI_PRODUCT_INTEL_PRO_WL_4965AGN_1, 81 PCI_PRODUCT_INTEL_PRO_WL_4965AGN_2, 82 PCI_PRODUCT_INTEL_PRO_WL_5100AGN_1, 83 PCI_PRODUCT_INTEL_PRO_WL_5100AGN_2, 84 PCI_PRODUCT_INTEL_PRO_WL_5300AGN_1, 85 PCI_PRODUCT_INTEL_PRO_WL_5300AGN_2, 86 PCI_PRODUCT_INTEL_PRO_WL_5350AGN_1, 87 PCI_PRODUCT_INTEL_PRO_WL_5350AGN_2, 88 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 89 #if 0 90 /* XXX From new OpenBSD iwn driver (not in pcidevs) */ 91 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 107 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 108 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 109 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 110 #endif 111 }; 112 113 /* 114 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 115 */ 116 static const struct ieee80211_rateset iwn_rateset_11a = 117 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 118 119 static const struct ieee80211_rateset iwn_rateset_11b = 120 { 4, { 2, 4, 11, 22 } }; 121 122 static const struct ieee80211_rateset iwn_rateset_11g = 123 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 124 125 static int iwn_match(device_t , struct cfdata *, void *); 126 static void iwn_attach(device_t , device_t , void *); 127 const struct iwn_hal *iwn_hal_attach(struct iwn_softc *, pci_product_id_t pid); 128 #ifndef SMALL_KERNEL 129 static void iwn_sensor_attach(struct iwn_softc *); 130 #endif 131 static void iwn_radiotap_attach(struct iwn_softc *); 132 static int iwn_detach(device_t , int); 133 #if 0 134 static void iwn_power(int, void *); 135 #endif 136 static bool iwn_resume(device_t, const pmf_qual_t *); 137 static int iwn_nic_lock(struct iwn_softc *); 138 static int iwn_eeprom_lock(struct iwn_softc *); 139 static int iwn_init_otprom(struct iwn_softc *); 140 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 141 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 142 void **, bus_size_t, bus_size_t); 143 static void iwn_dma_contig_free(struct iwn_dma_info *); 144 static int iwn_alloc_sched(struct iwn_softc *); 145 static void iwn_free_sched(struct iwn_softc *); 146 static int iwn_alloc_kw(struct iwn_softc *); 147 static void iwn_free_kw(struct iwn_softc *); 148 static int iwn_alloc_ict(struct iwn_softc *); 149 static void iwn_free_ict(struct iwn_softc *); 150 static int iwn_alloc_fwmem(struct iwn_softc *); 151 static void iwn_free_fwmem(struct iwn_softc *); 152 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 153 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 154 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 155 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 156 int); 157 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 158 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 159 static void iwn5000_ict_reset(struct iwn_softc *); 160 static int iwn_read_eeprom(struct iwn_softc *); 161 static void iwn4965_read_eeprom(struct iwn_softc *); 162 #ifdef IWN_DEBUG 163 static void iwn4965_print_power_group(struct iwn_softc *, int); 164 #endif 165 static void iwn5000_read_eeprom(struct iwn_softc *); 166 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 167 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 168 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 169 static void iwn_newassoc(struct ieee80211_node *, int); 170 static int iwn_media_change(struct ifnet *); 171 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 172 static void iwn_iter_func(void *, struct ieee80211_node *); 173 static void iwn_calib_timeout(void *); 174 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 #ifndef IEEE80211_NO_HT 179 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 180 struct iwn_rx_data *); 181 #endif 182 static void iwn5000_rx_calib_results(struct iwn_softc *, 183 struct iwn_rx_desc *, struct iwn_rx_data *); 184 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 185 struct iwn_rx_data *); 186 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 187 struct iwn_rx_data *); 188 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 189 struct iwn_rx_data *); 190 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 191 uint8_t); 192 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 193 static void iwn_notif_intr(struct iwn_softc *); 194 static void iwn_wakeup_intr(struct iwn_softc *); 195 static void iwn_fatal_intr(struct iwn_softc *); 196 static int iwn_intr(void *); 197 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 198 uint16_t); 199 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 200 uint16_t); 201 #ifdef notyet 202 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 203 #endif 204 static int iwn_tx(struct iwn_softc *, struct mbuf *, 205 struct ieee80211_node *, int); 206 static void iwn_start(struct ifnet *); 207 static void iwn_watchdog(struct ifnet *); 208 static int iwn_ioctl(struct ifnet *, u_long, void *); 209 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 210 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 211 int); 212 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 213 int); 214 static int iwn_set_link_quality(struct iwn_softc *, 215 struct ieee80211_node *); 216 static int iwn_add_broadcast_node(struct iwn_softc *, int); 217 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 218 static int iwn_set_critical_temp(struct iwn_softc *); 219 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 220 static void iwn4965_power_calibration(struct iwn_softc *, int); 221 static int iwn4965_set_txpower(struct iwn_softc *, int); 222 static int iwn5000_set_txpower(struct iwn_softc *, int); 223 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 224 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 225 static int iwn_get_noise(const struct iwn_rx_general_stats *); 226 static int iwn4965_get_temperature(struct iwn_softc *); 227 static int iwn5000_get_temperature(struct iwn_softc *); 228 static int iwn_init_sensitivity(struct iwn_softc *); 229 static void iwn_collect_noise(struct iwn_softc *, 230 const struct iwn_rx_general_stats *); 231 static int iwn4965_init_gains(struct iwn_softc *); 232 static int iwn5000_init_gains(struct iwn_softc *); 233 static int iwn4965_set_gains(struct iwn_softc *); 234 static int iwn5000_set_gains(struct iwn_softc *); 235 static void iwn_tune_sensitivity(struct iwn_softc *, 236 const struct iwn_rx_stats *); 237 static int iwn_send_sensitivity(struct iwn_softc *); 238 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 239 static int iwn_config(struct iwn_softc *); 240 static int iwn_scan(struct iwn_softc *, uint16_t); 241 static int iwn_auth(struct iwn_softc *); 242 static int iwn_run(struct iwn_softc *); 243 #ifdef IWN_HWCRYPTO 244 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 245 struct ieee80211_key *); 246 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 247 struct ieee80211_key *); 248 #endif 249 static int iwn_wme_update(struct ieee80211com *); 250 #ifndef IEEE80211_NO_HT 251 static int iwn_ampdu_rx_start(struct ieee80211com *, 252 struct ieee80211_node *, uint8_t); 253 static void iwn_ampdu_rx_stop(struct ieee80211com *, 254 struct ieee80211_node *, uint8_t); 255 static int iwn_ampdu_tx_start(struct ieee80211com *, 256 struct ieee80211_node *, uint8_t); 257 static void iwn_ampdu_tx_stop(struct ieee80211com *, 258 struct ieee80211_node *, uint8_t); 259 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 260 struct ieee80211_node *, uint8_t, uint16_t); 261 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 262 uint8_t, uint16_t); 263 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 264 struct ieee80211_node *, uint8_t, uint16_t); 265 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 266 uint8_t, uint16_t); 267 #endif 268 static int iwn5000_query_calibration(struct iwn_softc *); 269 static int iwn5000_send_calibration(struct iwn_softc *); 270 static int iwn5000_send_wimax_coex(struct iwn_softc *); 271 static int iwn4965_post_alive(struct iwn_softc *); 272 static int iwn5000_post_alive(struct iwn_softc *); 273 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 274 int); 275 static int iwn4965_load_firmware(struct iwn_softc *); 276 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 277 const uint8_t *, int); 278 static int iwn5000_load_firmware(struct iwn_softc *); 279 static int iwn_read_firmware(struct iwn_softc *); 280 static int iwn_clock_wait(struct iwn_softc *); 281 static int iwn_apm_init(struct iwn_softc *); 282 static void iwn_apm_stop_master(struct iwn_softc *); 283 static void iwn_apm_stop(struct iwn_softc *); 284 static int iwn4965_nic_config(struct iwn_softc *); 285 static int iwn5000_nic_config(struct iwn_softc *); 286 static int iwn_hw_prepare(struct iwn_softc *); 287 static int iwn_hw_init(struct iwn_softc *); 288 static void iwn_hw_stop(struct iwn_softc *); 289 static int iwn_init(struct ifnet *); 290 static void iwn_stop(struct ifnet *, int); 291 292 /* XXX MCLGETI alternative */ 293 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 294 struct ifnet *, u_int); 295 #ifdef IWN_USE_RBUF 296 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 297 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 298 static int iwn_alloc_rpool(struct iwn_softc *); 299 static void iwn_free_rpool(struct iwn_softc *); 300 #endif 301 302 /* XXX needed by iwn_scan */ 303 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 304 static u_int8_t *ieee80211_add_rates(u_int8_t *, 305 const struct ieee80211_rateset *); 306 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 307 const struct ieee80211_rateset *); 308 309 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 310 311 #ifdef IWN_DEBUG 312 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 313 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 314 int iwn_debug = 0; 315 #else 316 #define DPRINTF(x) 317 #define DPRINTFN(n, x) 318 #endif 319 320 static const struct iwn_hal iwn4965_hal = { 321 iwn4965_load_firmware, 322 iwn4965_read_eeprom, 323 iwn4965_post_alive, 324 iwn4965_nic_config, 325 iwn4965_update_sched, 326 iwn4965_get_temperature, 327 iwn4965_get_rssi, 328 iwn4965_set_txpower, 329 iwn4965_init_gains, 330 iwn4965_set_gains, 331 iwn4965_add_node, 332 iwn4965_tx_done, 333 #ifndef IEEE80211_NO_HT 334 iwn4965_ampdu_tx_start, 335 iwn4965_ampdu_tx_stop, 336 #endif 337 IWN4965_NTXQUEUES, 338 IWN4965_NDMACHNLS, 339 IWN4965_ID_BROADCAST, 340 IWN4965_RXONSZ, 341 IWN4965_SCHEDSZ, 342 IWN4965_FW_TEXT_MAXSZ, 343 IWN4965_FW_DATA_MAXSZ, 344 IWN4965_FWSZ, 345 IWN4965_SCHED_TXFACT 346 }; 347 348 static const struct iwn_hal iwn5000_hal = { 349 iwn5000_load_firmware, 350 iwn5000_read_eeprom, 351 iwn5000_post_alive, 352 iwn5000_nic_config, 353 iwn5000_update_sched, 354 iwn5000_get_temperature, 355 iwn5000_get_rssi, 356 iwn5000_set_txpower, 357 iwn5000_init_gains, 358 iwn5000_set_gains, 359 iwn5000_add_node, 360 iwn5000_tx_done, 361 #ifndef IEEE80211_NO_HT 362 iwn5000_ampdu_tx_start, 363 iwn5000_ampdu_tx_stop, 364 #endif 365 IWN5000_NTXQUEUES, 366 IWN5000_NDMACHNLS, 367 IWN5000_ID_BROADCAST, 368 IWN5000_RXONSZ, 369 IWN5000_SCHEDSZ, 370 IWN5000_FW_TEXT_MAXSZ, 371 IWN5000_FW_DATA_MAXSZ, 372 IWN5000_FWSZ, 373 IWN5000_SCHED_TXFACT 374 }; 375 376 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 377 iwn_detach, NULL); 378 379 static int 380 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 381 { 382 struct pci_attach_args *pa = aux; 383 size_t i; 384 385 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 386 return 0; 387 388 for (i = 0; i < __arraycount(iwn_devices); i++) 389 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 390 return 1; 391 392 return 0; 393 } 394 395 static void 396 iwn_attach(device_t parent __unused, device_t self, void *aux) 397 { 398 struct iwn_softc *sc = device_private(self); 399 struct ieee80211com *ic = &sc->sc_ic; 400 struct ifnet *ifp = &sc->sc_ec.ec_if; 401 struct pci_attach_args *pa = aux; 402 const struct iwn_hal *hal; 403 const char *intrstr; 404 char devinfo[256]; 405 pci_intr_handle_t ih; 406 pcireg_t memtype, reg; 407 int i, error; 408 int revision; 409 410 sc->sc_dev = self; 411 sc->sc_pct = pa->pa_pc; 412 sc->sc_pcitag = pa->pa_tag; 413 sc->sc_dmat = pa->pa_dmat; 414 415 callout_init(&sc->calib_to, 0); 416 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 417 418 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 419 revision = PCI_REVISION(pa->pa_class); 420 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 421 422 /* 423 * Get the offset of the PCI Express Capability Structure in PCI 424 * Configuration Space. 425 */ 426 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 427 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 428 if (error == 0) { 429 aprint_error(": PCIe capability structure not found!\n"); 430 return; 431 } 432 433 /* Clear device-specific "PCI retry timeout" register (41h). */ 434 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 435 reg &= ~0xff00; 436 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 437 438 /* Enable bus-mastering and hardware bug workaround. */ 439 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 440 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 441 reg |= PCI_COMMAND_MASTER_ENABLE; 442 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 443 DPRINTF(("PCIe INTx Disable set\n")); 444 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 445 } 446 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 447 448 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 449 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 450 &sc->sc_sh, NULL, &sc->sc_sz); 451 if (error != 0) { 452 aprint_error(": can't map mem space\n"); 453 return; 454 } 455 456 /* Install interrupt handler. */ 457 if (pci_intr_map(pa, &ih) != 0) { 458 aprint_error(": can't map interrupt\n"); 459 return; 460 } 461 intrstr = pci_intr_string(sc->sc_pct, ih); 462 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 463 if (sc->sc_ih == NULL) { 464 aprint_error(": can't establish interrupt"); 465 if (intrstr != NULL) 466 aprint_error(" at %s", intrstr); 467 aprint_error("\n"); 468 return; 469 } 470 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 471 472 /* Attach Hardware Abstraction Layer. */ 473 hal = iwn_hal_attach(sc, PCI_PRODUCT(pa->pa_id)); 474 if (hal == NULL) 475 return; 476 477 if ((error = iwn_hw_prepare(sc)) != 0) { 478 aprint_error(": hardware not ready\n"); 479 return; 480 } 481 482 /* Read MAC address, channels, etc from EEPROM. */ 483 if ((error = iwn_read_eeprom(sc)) != 0) { 484 aprint_error(": could not read EEPROM\n"); 485 return; 486 } 487 488 /* Allocate DMA memory for firmware transfers. */ 489 if ((error = iwn_alloc_fwmem(sc)) != 0) { 490 aprint_error(": could not allocate memory for firmware\n"); 491 return; 492 } 493 494 /* Allocate "Keep Warm" page. */ 495 if ((error = iwn_alloc_kw(sc)) != 0) { 496 aprint_error(": could not allocate keep warm page\n"); 497 goto fail1; 498 } 499 500 /* Allocate ICT table for 5000 Series. */ 501 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 502 (error = iwn_alloc_ict(sc)) != 0) { 503 aprint_error(": could not allocate ICT table\n"); 504 goto fail2; 505 } 506 507 /* Allocate TX scheduler "rings". */ 508 if ((error = iwn_alloc_sched(sc)) != 0) { 509 aprint_error(": could not allocate TX scheduler rings\n"); 510 goto fail3; 511 } 512 513 #ifdef IWN_USE_RBUF 514 /* Allocate RX buffers. */ 515 if ((error = iwn_alloc_rpool(sc)) != 0) { 516 aprint_error_dev(self, "could not allocate RX buffers\n"); 517 goto fail3; 518 } 519 #endif 520 521 /* Allocate TX rings (16 on 4965AGN, 20 on 5000.) */ 522 for (i = 0; i < hal->ntxqs; i++) { 523 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 524 aprint_error(": could not allocate TX ring %d\n", i); 525 goto fail4; 526 } 527 } 528 529 /* Allocate RX ring. */ 530 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 531 aprint_error(": could not allocate RX ring\n"); 532 goto fail4; 533 } 534 535 /* Clear pending interrupts. */ 536 IWN_WRITE(sc, IWN_INT, 0xffffffff); 537 538 /* Count the number of available chains. */ 539 sc->ntxchains = 540 ((sc->txchainmask >> 2) & 1) + 541 ((sc->txchainmask >> 1) & 1) + 542 ((sc->txchainmask >> 0) & 1); 543 sc->nrxchains = 544 ((sc->rxchainmask >> 2) & 1) + 545 ((sc->rxchainmask >> 1) & 1) + 546 ((sc->rxchainmask >> 0) & 1); 547 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 548 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 549 ether_sprintf(ic->ic_myaddr)); 550 551 ic->ic_ifp = ifp; 552 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 553 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 554 ic->ic_state = IEEE80211_S_INIT; 555 556 /* Set device capabilities. */ 557 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 558 * and IEEE80211_C_PMGT too. */ 559 ic->ic_caps = 560 IEEE80211_C_IBSS | /* IBSS mode support */ 561 IEEE80211_C_WPA | /* 802.11i */ 562 IEEE80211_C_MONITOR | /* monitor mode supported */ 563 IEEE80211_C_TXPMGT | /* tx power management */ 564 IEEE80211_C_SHSLOT | /* short slot time supported */ 565 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 566 IEEE80211_C_WME; /* 802.11e */ 567 568 #ifndef IEEE80211_NO_HT 569 /* Set HT capabilities. */ 570 ic->ic_htcaps = 571 #if IWN_RBUF_SIZE == 8192 572 IEEE80211_HTCAP_AMSDU7935 | 573 #endif 574 IEEE80211_HTCAP_CBW20_40 | 575 IEEE80211_HTCAP_SGI20 | 576 IEEE80211_HTCAP_SGI40; 577 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 578 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 579 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 580 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 581 else 582 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 583 #endif /* !IEEE80211_NO_HT */ 584 585 /* Set supported legacy rates. */ 586 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 587 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 588 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 589 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 590 } 591 #ifndef IEEE80211_NO_HT 592 /* Set supported HT rates. */ 593 ic->ic_sup_mcs[0] = 0xff; 594 if (sc->nrxchains > 1) /* MCS 0-7 */ 595 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 596 if (sc->nrxchains > 2) 597 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 598 #endif 599 600 /* IBSS channel undefined for now. */ 601 ic->ic_ibss_chan = &ic->ic_channels[0]; 602 603 ifp->if_softc = sc; 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_init = iwn_init; 606 ifp->if_ioctl = iwn_ioctl; 607 ifp->if_start = iwn_start; 608 ifp->if_watchdog = iwn_watchdog; 609 IFQ_SET_READY(&ifp->if_snd); 610 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 611 612 if_attach(ifp); 613 ieee80211_ifattach(ic); 614 ic->ic_node_alloc = iwn_node_alloc; 615 ic->ic_newassoc = iwn_newassoc; 616 #ifdef IWN_HWCRYPTO 617 ic->ic_crypto.cs_key_set = iwn_set_key; 618 ic->ic_crypto.cs_key_delete = iwn_delete_key; 619 #endif 620 ic->ic_wme.wme_update = iwn_wme_update; 621 #ifndef IEEE80211_NO_HT 622 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 623 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 624 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 625 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 626 #endif 627 628 /* Override 802.11 state transition machine. */ 629 sc->sc_newstate = ic->ic_newstate; 630 ic->ic_newstate = iwn_newstate; 631 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 632 633 sc->amrr.amrr_min_success_threshold = 1; 634 sc->amrr.amrr_max_success_threshold = 15; 635 636 #ifndef SMALL_KERNEL 637 iwn_sensor_attach(sc); 638 #endif 639 iwn_radiotap_attach(sc); 640 641 /* 642 * XXX for NetBSD, OpenBSD timeout_set replaced by 643 * callout_init and callout_setfunc, above. 644 */ 645 646 if (pmf_device_register(self, NULL, iwn_resume)) 647 pmf_class_network_register(self, ifp); 648 else 649 aprint_error_dev(self, "couldn't establish power handler\n"); 650 651 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 652 ieee80211_announce(ic); 653 654 return; 655 656 /* Free allocated memory if something failed during attachment. */ 657 fail4: while (--i >= 0) 658 iwn_free_tx_ring(sc, &sc->txq[i]); 659 #ifdef IWN_USE_RBUF 660 iwn_free_rpool(sc); 661 #endif 662 iwn_free_sched(sc); 663 fail3: if (sc->ict != NULL) 664 iwn_free_ict(sc); 665 fail2: iwn_free_kw(sc); 666 fail1: iwn_free_fwmem(sc); 667 } 668 669 const struct iwn_hal * 670 iwn_hal_attach(struct iwn_softc *sc, pci_product_id_t pid) 671 { 672 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 673 674 switch (sc->hw_type) { 675 case IWN_HW_REV_TYPE_4965: 676 sc->sc_hal = &iwn4965_hal; 677 sc->limits = &iwn4965_sensitivity_limits; 678 sc->fwname = "iwlwifi-4965-2.ucode"; 679 sc->txchainmask = IWN_ANT_AB; 680 sc->rxchainmask = IWN_ANT_ABC; 681 break; 682 case IWN_HW_REV_TYPE_5100: 683 sc->sc_hal = &iwn5000_hal; 684 sc->limits = &iwn5000_sensitivity_limits; 685 sc->fwname = "iwlwifi-5000-2.ucode"; 686 sc->txchainmask = IWN_ANT_B; 687 sc->rxchainmask = IWN_ANT_AB; 688 break; 689 case IWN_HW_REV_TYPE_5150: 690 sc->sc_hal = &iwn5000_hal; 691 sc->limits = &iwn5150_sensitivity_limits; 692 sc->fwname = "iwlwifi-5150-2.ucode"; 693 sc->txchainmask = IWN_ANT_A; 694 sc->rxchainmask = IWN_ANT_AB; 695 break; 696 case IWN_HW_REV_TYPE_5300: 697 case IWN_HW_REV_TYPE_5350: 698 sc->sc_hal = &iwn5000_hal; 699 sc->limits = &iwn5000_sensitivity_limits; 700 sc->fwname = "iwlwifi-5000-2.ucode"; 701 sc->txchainmask = IWN_ANT_ABC; 702 sc->rxchainmask = IWN_ANT_ABC; 703 break; 704 case IWN_HW_REV_TYPE_1000: 705 sc->sc_hal = &iwn5000_hal; 706 sc->limits = &iwn1000_sensitivity_limits; 707 sc->fwname = "iwlwifi-1000-3.ucode"; 708 sc->txchainmask = IWN_ANT_A; 709 sc->rxchainmask = IWN_ANT_AB; 710 break; 711 case IWN_HW_REV_TYPE_6000: 712 sc->sc_hal = &iwn5000_hal; 713 sc->limits = &iwn6000_sensitivity_limits; 714 sc->fwname = "iwlwifi-6000-4.ucode"; 715 switch (pid) { 716 /* XXX not yet defined for NetBSD (not in pcidevs) */ 717 #ifdef PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 718 case PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1: 719 case PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2: 720 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 721 sc->txchainmask = IWN_ANT_BC; 722 sc->rxchainmask = IWN_ANT_BC; 723 break; 724 #endif 725 default: 726 sc->txchainmask = IWN_ANT_ABC; 727 sc->rxchainmask = IWN_ANT_ABC; 728 break; 729 } 730 break; 731 case IWN_HW_REV_TYPE_6050: 732 sc->sc_hal = &iwn5000_hal; 733 sc->limits = &iwn6000_sensitivity_limits; 734 sc->fwname = "iwlwifi-6050-2.ucode"; 735 sc->txchainmask = IWN_ANT_AB; 736 sc->rxchainmask = IWN_ANT_AB; 737 break; 738 case IWN_HW_REV_TYPE_6005: 739 sc->sc_hal = &iwn5000_hal; 740 sc->limits = &iwn6000_sensitivity_limits; 741 sc->fwname = "iwlwifi-6005-2.ucode"; 742 sc->txchainmask = IWN_ANT_AB; 743 sc->rxchainmask = IWN_ANT_AB; 744 break; 745 default: 746 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 747 return NULL; 748 } 749 return sc->sc_hal; 750 } 751 752 #ifndef SMALL_KERNEL 753 /* 754 * Attach the adapter on-board thermal sensor to the sensors framework. 755 */ 756 static void 757 iwn_sensor_attach(struct iwn_softc *sc) 758 { 759 int error; 760 761 sc->sc_sensor.units = ENVSYS_STEMP; 762 #if 0 763 /* XXX something like this ought to work */ 764 sc->sc_sensor.flags = ENVSYS_FMONLIMITS | ENVSYS_FMONNOTSUPP; 765 sc->sc_sensor.limits.sel_critmax = IWN_CTOK(110); 766 #endif 767 strlcpy((sc->sc_sensor.desc), "TEMP", sizeof(sc->sc_sensor.desc)); 768 769 /* Temperature is not valid unless interface is up. */ 770 sc->sc_sensor.value_cur = 0; 771 sc->sc_sensor.state = ENVSYS_SINVALID; 772 773 sc->sc_sme = sysmon_envsys_create(); 774 775 /* Initialize sensor */ 776 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 777 sysmon_envsys_destroy(sc->sc_sme); 778 return; 779 } 780 781 /* 782 * Hook into the System Monitor. 783 */ 784 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 785 sc->sc_sme->sme_flags = SME_DISABLE_REFRESH; 786 787 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 788 aprint_error_dev(sc->sc_dev, 789 "unable to register with sysmon (%d)\n", error); 790 sysmon_envsys_destroy(sc->sc_sme); 791 return; 792 } 793 } 794 #endif 795 796 /* 797 * Attach the interface to 802.11 radiotap. 798 */ 799 static void 800 iwn_radiotap_attach(struct iwn_softc *sc) 801 { 802 struct ifnet *ifp = sc->sc_ic.ic_ifp; 803 804 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 805 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 806 &sc->sc_drvbpf); 807 808 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 809 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 810 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 811 812 sc->sc_txtap_len = sizeof sc->sc_txtapu; 813 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 814 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 815 } 816 817 static int 818 iwn_detach(device_t self, int flags __unused) 819 { 820 struct iwn_softc *sc = device_private(self); 821 struct ifnet *ifp = sc->sc_ic.ic_ifp; 822 int qid; 823 824 callout_stop(&sc->calib_to); 825 826 /* Uninstall interrupt handler. */ 827 if (sc->sc_ih != NULL) 828 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 829 830 /* Free DMA resources. */ 831 iwn_free_rx_ring(sc, &sc->rxq); 832 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) 833 iwn_free_tx_ring(sc, &sc->txq[qid]); 834 #ifdef IWN_USE_RBUF 835 iwn_free_rpool(sc); 836 #endif 837 iwn_free_sched(sc); 838 iwn_free_kw(sc); 839 if (sc->ict != NULL) 840 iwn_free_ict(sc); 841 iwn_free_fwmem(sc); 842 843 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 844 845 #ifndef SMALL_KERNEL 846 /* Detach the thermal sensor. */ 847 sysmon_envsys_sensor_detach(sc->sc_sme, &sc->sc_sensor); 848 sysmon_envsys_destroy(sc->sc_sme); 849 #endif 850 851 ieee80211_ifdetach(&sc->sc_ic); 852 if_detach(ifp); 853 854 return 0; 855 } 856 857 #if 0 858 /* 859 * XXX Investigate if clearing the PCI retry timeout could eliminate 860 * the repeated scan calls. Also the calls to if_init and if_start 861 * are similar to the effect of adding the call to ifioctl_common . 862 */ 863 static void 864 iwn_power(int why, void *arg) 865 { 866 struct iwn_softc *sc = arg; 867 struct ifnet *ifp; 868 pcireg_t reg; 869 int s; 870 871 if (why != PWR_RESUME) 872 return; 873 874 /* Clear device-specific "PCI retry timeout" register (41h). */ 875 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 876 reg &= ~0xff00; 877 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 878 879 s = splnet(); 880 ifp = &sc->sc_ic.ic_if; 881 if (ifp->if_flags & IFF_UP) { 882 ifp->if_init(ifp); 883 if (ifp->if_flags & IFF_RUNNING) 884 ifp->if_start(ifp); 885 } 886 splx(s); 887 } 888 #endif 889 890 static bool 891 iwn_resume(device_t dv, const pmf_qual_t *qual) 892 { 893 return true; 894 } 895 896 static int 897 iwn_nic_lock(struct iwn_softc *sc) 898 { 899 int ntries; 900 901 /* Request exclusive access to NIC. */ 902 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 903 904 /* Spin until we actually get the lock. */ 905 for (ntries = 0; ntries < 1000; ntries++) { 906 if ((IWN_READ(sc, IWN_GP_CNTRL) & 907 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 908 IWN_GP_CNTRL_MAC_ACCESS_ENA) 909 return 0; 910 DELAY(10); 911 } 912 return ETIMEDOUT; 913 } 914 915 static __inline void 916 iwn_nic_unlock(struct iwn_softc *sc) 917 { 918 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 919 } 920 921 static __inline uint32_t 922 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 923 { 924 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 925 IWN_BARRIER_READ_WRITE(sc); 926 return IWN_READ(sc, IWN_PRPH_RDATA); 927 } 928 929 static __inline void 930 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 931 { 932 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 933 IWN_BARRIER_WRITE(sc); 934 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 935 } 936 937 static __inline void 938 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 939 { 940 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 941 } 942 943 static __inline void 944 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 945 { 946 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 947 } 948 949 static __inline void 950 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 951 const uint32_t *data, int count) 952 { 953 for (; count > 0; count--, data++, addr += 4) 954 iwn_prph_write(sc, addr, *data); 955 } 956 957 static __inline uint32_t 958 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 959 { 960 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 961 IWN_BARRIER_READ_WRITE(sc); 962 return IWN_READ(sc, IWN_MEM_RDATA); 963 } 964 965 static __inline void 966 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 967 { 968 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 969 IWN_BARRIER_WRITE(sc); 970 IWN_WRITE(sc, IWN_MEM_WDATA, data); 971 } 972 973 static __inline void 974 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 975 { 976 uint32_t tmp; 977 978 tmp = iwn_mem_read(sc, addr & ~3); 979 if (addr & 3) 980 tmp = (tmp & 0x0000ffff) | data << 16; 981 else 982 tmp = (tmp & 0xffff0000) | data; 983 iwn_mem_write(sc, addr & ~3, tmp); 984 } 985 986 static __inline void 987 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 988 int count) 989 { 990 for (; count > 0; count--, addr += 4) 991 *data++ = iwn_mem_read(sc, addr); 992 } 993 994 static __inline void 995 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 996 int count) 997 { 998 for (; count > 0; count--, addr += 4) 999 iwn_mem_write(sc, addr, val); 1000 } 1001 1002 static int 1003 iwn_eeprom_lock(struct iwn_softc *sc) 1004 { 1005 int i, ntries; 1006 1007 for (i = 0; i < 100; i++) { 1008 /* Request exclusive access to EEPROM. */ 1009 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1010 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1011 1012 /* Spin until we actually get the lock. */ 1013 for (ntries = 0; ntries < 100; ntries++) { 1014 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1015 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1016 return 0; 1017 DELAY(10); 1018 } 1019 } 1020 return ETIMEDOUT; 1021 } 1022 1023 static __inline void 1024 iwn_eeprom_unlock(struct iwn_softc *sc) 1025 { 1026 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1027 } 1028 1029 /* 1030 * Initialize access by host to One Time Programmable ROM. 1031 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1032 */ 1033 static int 1034 iwn_init_otprom(struct iwn_softc *sc) 1035 { 1036 uint16_t prev = 0, base, next; 1037 int count, error; 1038 1039 /* Wait for clock stabilization before accessing prph. */ 1040 if ((error = iwn_clock_wait(sc)) != 0) 1041 return error; 1042 1043 if ((error = iwn_nic_lock(sc)) != 0) 1044 return error; 1045 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1046 DELAY(5); 1047 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1048 iwn_nic_unlock(sc); 1049 1050 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1051 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1052 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1053 IWN_RESET_LINK_PWR_MGMT_DIS); 1054 } 1055 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1056 /* Clear ECC status. */ 1057 IWN_SETBITS(sc, IWN_OTP_GP, 1058 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1059 1060 /* 1061 * Find the block before last block (contains the EEPROM image) 1062 * for HW without OTP shadow RAM. 1063 */ 1064 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1065 /* Switch to absolute addressing mode. */ 1066 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1067 base = 0; 1068 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1069 error = iwn_read_prom_data(sc, base, &next, 2); 1070 if (error != 0) 1071 return error; 1072 if (next == 0) /* End of linked-list. */ 1073 break; 1074 prev = base; 1075 base = le16toh(next); 1076 } 1077 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1078 return EIO; 1079 /* Skip "next" word. */ 1080 sc->prom_base = prev + 1; 1081 } 1082 return 0; 1083 } 1084 1085 static int 1086 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1087 { 1088 uint8_t *out = data; 1089 uint32_t val, tmp; 1090 int ntries; 1091 1092 addr += sc->prom_base; 1093 for (; count > 0; count -= 2, addr++) { 1094 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1095 for (ntries = 0; ntries < 10; ntries++) { 1096 val = IWN_READ(sc, IWN_EEPROM); 1097 if (val & IWN_EEPROM_READ_VALID) 1098 break; 1099 DELAY(5); 1100 } 1101 if (ntries == 10) { 1102 aprint_error_dev(sc->sc_dev, 1103 "timeout reading ROM at 0x%x\n", addr); 1104 return ETIMEDOUT; 1105 } 1106 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1107 /* OTPROM, check for ECC errors. */ 1108 tmp = IWN_READ(sc, IWN_OTP_GP); 1109 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1110 aprint_error_dev(sc->sc_dev, 1111 "OTPROM ECC error at 0x%x\n", addr); 1112 return EIO; 1113 } 1114 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1115 /* Correctable ECC error, clear bit. */ 1116 IWN_SETBITS(sc, IWN_OTP_GP, 1117 IWN_OTP_GP_ECC_CORR_STTS); 1118 } 1119 } 1120 *out++ = val >> 16; 1121 if (count > 1) 1122 *out++ = val >> 24; 1123 } 1124 return 0; 1125 } 1126 1127 static int 1128 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1129 bus_size_t size, bus_size_t alignment) 1130 { 1131 int nsegs, error; 1132 1133 dma->tag = tag; 1134 dma->size = size; 1135 1136 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1137 &dma->map); 1138 if (error != 0) 1139 goto fail; 1140 1141 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1142 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1143 if (error != 0) 1144 goto fail; 1145 1146 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1147 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1148 if (error != 0) 1149 goto fail; 1150 1151 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1152 BUS_DMA_NOWAIT); 1153 if (error != 0) 1154 goto fail; 1155 1156 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1157 memset(dma->vaddr, 0, size); 1158 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1159 1160 dma->paddr = dma->map->dm_segs[0].ds_addr; 1161 if (kvap != NULL) 1162 *kvap = dma->vaddr; 1163 1164 return 0; 1165 1166 fail: iwn_dma_contig_free(dma); 1167 return error; 1168 } 1169 1170 static void 1171 iwn_dma_contig_free(struct iwn_dma_info *dma) 1172 { 1173 if (dma->map != NULL) { 1174 if (dma->vaddr != NULL) { 1175 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1176 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1177 bus_dmamap_unload(dma->tag, dma->map); 1178 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1179 bus_dmamem_free(dma->tag, &dma->seg, 1); 1180 dma->vaddr = NULL; 1181 } 1182 bus_dmamap_destroy(dma->tag, dma->map); 1183 dma->map = NULL; 1184 } 1185 } 1186 1187 static int 1188 iwn_alloc_sched(struct iwn_softc *sc) 1189 { 1190 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1191 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1192 (void **)&sc->sched, sc->sc_hal->schedsz, 1024); 1193 } 1194 1195 static void 1196 iwn_free_sched(struct iwn_softc *sc) 1197 { 1198 iwn_dma_contig_free(&sc->sched_dma); 1199 } 1200 1201 static int 1202 iwn_alloc_kw(struct iwn_softc *sc) 1203 { 1204 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1205 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1206 4096); 1207 } 1208 1209 static void 1210 iwn_free_kw(struct iwn_softc *sc) 1211 { 1212 iwn_dma_contig_free(&sc->kw_dma); 1213 } 1214 1215 static int 1216 iwn_alloc_ict(struct iwn_softc *sc) 1217 { 1218 /* ICT table must be aligned on a 4KB boundary. */ 1219 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1220 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1221 } 1222 1223 static void 1224 iwn_free_ict(struct iwn_softc *sc) 1225 { 1226 iwn_dma_contig_free(&sc->ict_dma); 1227 } 1228 1229 static int 1230 iwn_alloc_fwmem(struct iwn_softc *sc) 1231 { 1232 /* Must be aligned on a 16-byte boundary. */ 1233 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1234 sc->sc_hal->fwsz, 16); 1235 } 1236 1237 static void 1238 iwn_free_fwmem(struct iwn_softc *sc) 1239 { 1240 iwn_dma_contig_free(&sc->fw_dma); 1241 } 1242 1243 static int 1244 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1245 { 1246 bus_size_t size; 1247 int i, error; 1248 1249 ring->cur = 0; 1250 1251 /* Allocate RX descriptors (256-byte aligned.) */ 1252 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1253 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1254 (void **)&ring->desc, size, 256); 1255 if (error != 0) { 1256 aprint_error_dev(sc->sc_dev, 1257 "could not allocate RX ring DMA memory\n"); 1258 goto fail; 1259 } 1260 1261 /* Allocate RX status area (16-byte aligned.) */ 1262 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1263 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1264 if (error != 0) { 1265 aprint_error_dev(sc->sc_dev, 1266 "could not allocate RX status DMA memory\n"); 1267 goto fail; 1268 } 1269 1270 /* 1271 * Allocate and map RX buffers. 1272 */ 1273 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1274 struct iwn_rx_data *data = &ring->data[i]; 1275 1276 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1277 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1278 &data->map); 1279 if (error != 0) { 1280 aprint_error_dev(sc->sc_dev, 1281 "could not create RX buf DMA map\n"); 1282 goto fail; 1283 } 1284 1285 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1286 if (data->m == NULL) { 1287 aprint_error_dev(sc->sc_dev, 1288 "could not allocate RX mbuf\n"); 1289 error = ENOBUFS; 1290 goto fail; 1291 } 1292 1293 error = bus_dmamap_load(sc->sc_dmat, data->map, 1294 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1295 BUS_DMA_NOWAIT | BUS_DMA_READ); 1296 if (error != 0) { 1297 aprint_error_dev(sc->sc_dev, 1298 "can't not map mbuf (error %d)\n", error); 1299 goto fail; 1300 } 1301 1302 /* Set physical address of RX buffer (256-byte aligned.) */ 1303 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1304 } 1305 1306 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1307 BUS_DMASYNC_PREWRITE); 1308 1309 return 0; 1310 1311 fail: iwn_free_rx_ring(sc, ring); 1312 return error; 1313 } 1314 1315 static void 1316 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1317 { 1318 int ntries; 1319 1320 if (iwn_nic_lock(sc) == 0) { 1321 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1322 for (ntries = 0; ntries < 1000; ntries++) { 1323 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1324 IWN_FH_RX_STATUS_IDLE) 1325 break; 1326 DELAY(10); 1327 } 1328 iwn_nic_unlock(sc); 1329 } 1330 ring->cur = 0; 1331 sc->last_rx_valid = 0; 1332 } 1333 1334 static void 1335 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1336 { 1337 int i; 1338 1339 iwn_dma_contig_free(&ring->desc_dma); 1340 iwn_dma_contig_free(&ring->stat_dma); 1341 1342 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1343 struct iwn_rx_data *data = &ring->data[i]; 1344 1345 if (data->m != NULL) { 1346 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1347 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1348 bus_dmamap_unload(sc->sc_dmat, data->map); 1349 m_freem(data->m); 1350 } 1351 if (data->map != NULL) 1352 bus_dmamap_destroy(sc->sc_dmat, data->map); 1353 } 1354 } 1355 1356 static int 1357 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1358 { 1359 bus_addr_t paddr; 1360 bus_size_t size; 1361 int i, error; 1362 1363 ring->qid = qid; 1364 ring->queued = 0; 1365 ring->cur = 0; 1366 1367 /* Allocate TX descriptors (256-byte aligned.) */ 1368 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1369 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1370 (void **)&ring->desc, size, 256); 1371 if (error != 0) { 1372 aprint_error_dev(sc->sc_dev, 1373 "could not allocate TX ring DMA memory\n"); 1374 goto fail; 1375 } 1376 /* 1377 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1378 * to allocate commands space for other rings. 1379 * XXX Do we really need to allocate descriptors for other rings? 1380 */ 1381 if (qid > 4) 1382 return 0; 1383 1384 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1385 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1386 (void **)&ring->cmd, size, 4); 1387 if (error != 0) { 1388 aprint_error_dev(sc->sc_dev, 1389 "could not allocate TX cmd DMA memory\n"); 1390 goto fail; 1391 } 1392 1393 paddr = ring->cmd_dma.paddr; 1394 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1395 struct iwn_tx_data *data = &ring->data[i]; 1396 1397 data->cmd_paddr = paddr; 1398 data->scratch_paddr = paddr + 12; 1399 paddr += sizeof (struct iwn_tx_cmd); 1400 1401 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1402 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1403 &data->map); 1404 if (error != 0) { 1405 aprint_error_dev(sc->sc_dev, 1406 "could not create TX buf DMA map\n"); 1407 goto fail; 1408 } 1409 } 1410 return 0; 1411 1412 fail: iwn_free_tx_ring(sc, ring); 1413 return error; 1414 } 1415 1416 static void 1417 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1418 { 1419 int i; 1420 1421 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1422 struct iwn_tx_data *data = &ring->data[i]; 1423 1424 if (data->m != NULL) { 1425 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1426 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1427 bus_dmamap_unload(sc->sc_dmat, data->map); 1428 m_freem(data->m); 1429 data->m = NULL; 1430 } 1431 } 1432 /* Clear TX descriptors. */ 1433 memset(ring->desc, 0, ring->desc_dma.size); 1434 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1435 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1436 sc->qfullmsk &= ~(1 << ring->qid); 1437 ring->queued = 0; 1438 ring->cur = 0; 1439 } 1440 1441 static void 1442 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1443 { 1444 int i; 1445 1446 iwn_dma_contig_free(&ring->desc_dma); 1447 iwn_dma_contig_free(&ring->cmd_dma); 1448 1449 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1450 struct iwn_tx_data *data = &ring->data[i]; 1451 1452 if (data->m != NULL) { 1453 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1454 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1455 bus_dmamap_unload(sc->sc_dmat, data->map); 1456 m_freem(data->m); 1457 } 1458 if (data->map != NULL) 1459 bus_dmamap_destroy(sc->sc_dmat, data->map); 1460 } 1461 } 1462 1463 static void 1464 iwn5000_ict_reset(struct iwn_softc *sc) 1465 { 1466 /* Disable interrupts. */ 1467 IWN_WRITE(sc, IWN_INT_MASK, 0); 1468 1469 /* Reset ICT table. */ 1470 memset(sc->ict, 0, IWN_ICT_SIZE); 1471 sc->ict_cur = 0; 1472 1473 /* Set physical address of ICT table (4KB aligned.) */ 1474 DPRINTF(("enabling ICT\n")); 1475 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1476 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1477 1478 /* Enable periodic RX interrupt. */ 1479 sc->int_mask |= IWN_INT_RX_PERIODIC; 1480 /* Switch to ICT interrupt mode in driver. */ 1481 sc->sc_flags |= IWN_FLAG_USE_ICT; 1482 1483 /* Re-enable interrupts. */ 1484 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1485 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1486 } 1487 1488 static int 1489 iwn_read_eeprom(struct iwn_softc *sc) 1490 { 1491 const struct iwn_hal *hal = sc->sc_hal; 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 uint16_t val; 1494 int error; 1495 1496 /* Check whether adapter has an EEPROM or an OTPROM. */ 1497 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1498 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1499 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1500 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1501 "OTPROM" : "EEPROM")); 1502 1503 /* Adapter has to be powered on for EEPROM access to work. */ 1504 if ((error = iwn_apm_init(sc)) != 0) { 1505 aprint_error_dev(sc->sc_dev, 1506 "could not power ON adapter\n"); 1507 return error; 1508 } 1509 1510 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1511 aprint_error_dev(sc->sc_dev, 1512 "bad ROM signature\n"); 1513 return EIO; 1514 } 1515 if ((error = iwn_eeprom_lock(sc)) != 0) { 1516 aprint_error_dev(sc->sc_dev, 1517 "could not lock ROM (error=%d)\n", error); 1518 return error; 1519 } 1520 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1521 if ((error = iwn_init_otprom(sc)) != 0) { 1522 aprint_error_dev(sc->sc_dev, 1523 "could not initialize OTPROM\n"); 1524 return error; 1525 } 1526 } 1527 1528 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1529 sc->rfcfg = le16toh(val); 1530 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1531 1532 /* Read MAC address. */ 1533 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1534 1535 /* Read adapter-specific information from EEPROM. */ 1536 hal->read_eeprom(sc); 1537 1538 iwn_apm_stop(sc); /* Power OFF adapter. */ 1539 1540 iwn_eeprom_unlock(sc); 1541 return 0; 1542 } 1543 1544 static void 1545 iwn4965_read_eeprom(struct iwn_softc *sc) 1546 { 1547 uint32_t addr; 1548 uint16_t val; 1549 int i; 1550 1551 /* Read regulatory domain (4 ASCII characters.) */ 1552 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1553 1554 /* Read the list of authorized channels (20MHz ones only.) */ 1555 for (i = 0; i < 5; i++) { 1556 addr = iwn4965_regulatory_bands[i]; 1557 iwn_read_eeprom_channels(sc, i, addr); 1558 } 1559 1560 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1561 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1562 sc->maxpwr2GHz = val & 0xff; 1563 sc->maxpwr5GHz = val >> 8; 1564 /* Check that EEPROM values are within valid range. */ 1565 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1566 sc->maxpwr5GHz = 38; 1567 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1568 sc->maxpwr2GHz = 38; 1569 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1570 1571 /* Read samples for each TX power group. */ 1572 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1573 sizeof sc->bands); 1574 1575 /* Read voltage at which samples were taken. */ 1576 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1577 sc->eeprom_voltage = (int16_t)le16toh(val); 1578 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1579 1580 #ifdef IWN_DEBUG 1581 /* Print samples. */ 1582 if (iwn_debug > 0) { 1583 for (i = 0; i < IWN_NBANDS; i++) 1584 iwn4965_print_power_group(sc, i); 1585 } 1586 #endif 1587 } 1588 1589 #ifdef IWN_DEBUG 1590 static void 1591 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1592 { 1593 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1594 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1595 int j, c; 1596 1597 aprint_normal("===band %d===\n", i); 1598 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1599 aprint_normal("chan1 num=%d\n", chans[0].num); 1600 for (c = 0; c < 2; c++) { 1601 for (j = 0; j < IWN_NSAMPLES; j++) { 1602 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1603 "power=%d pa_det=%d\n", c, j, 1604 chans[0].samples[c][j].temp, 1605 chans[0].samples[c][j].gain, 1606 chans[0].samples[c][j].power, 1607 chans[0].samples[c][j].pa_det); 1608 } 1609 } 1610 aprint_normal("chan2 num=%d\n", chans[1].num); 1611 for (c = 0; c < 2; c++) { 1612 for (j = 0; j < IWN_NSAMPLES; j++) { 1613 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1614 "power=%d pa_det=%d\n", c, j, 1615 chans[1].samples[c][j].temp, 1616 chans[1].samples[c][j].gain, 1617 chans[1].samples[c][j].power, 1618 chans[1].samples[c][j].pa_det); 1619 } 1620 } 1621 } 1622 #endif 1623 1624 static void 1625 iwn5000_read_eeprom(struct iwn_softc *sc) 1626 { 1627 struct iwn5000_eeprom_calib_hdr hdr; 1628 int32_t temp, volt; 1629 uint32_t base, addr; 1630 uint16_t val; 1631 int i; 1632 1633 /* Read regulatory domain (4 ASCII characters.) */ 1634 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1635 base = le16toh(val); 1636 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1637 sc->eeprom_domain, 4); 1638 1639 /* Read the list of authorized channels (20MHz ones only.) */ 1640 for (i = 0; i < 5; i++) { 1641 addr = base + iwn5000_regulatory_bands[i]; 1642 iwn_read_eeprom_channels(sc, i, addr); 1643 } 1644 1645 /* Read enhanced TX power information for 6000 Series. */ 1646 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1647 iwn_read_eeprom_enhinfo(sc); 1648 1649 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1650 base = le16toh(val); 1651 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1652 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1653 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1654 sc->calib_ver = hdr.version; 1655 1656 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1657 /* Compute temperature offset. */ 1658 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1659 temp = le16toh(val); 1660 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1661 volt = le16toh(val); 1662 sc->temp_off = temp - (volt / -5); 1663 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1664 temp, volt, sc->temp_off)); 1665 } else { 1666 /* Read crystal calibration. */ 1667 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1668 &sc->eeprom_crystal, sizeof (uint32_t)); 1669 DPRINTF(("crystal calibration 0x%08x\n", 1670 le32toh(sc->eeprom_crystal))); 1671 } 1672 } 1673 1674 static void 1675 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1676 { 1677 struct ieee80211com *ic = &sc->sc_ic; 1678 const struct iwn_chan_band *band = &iwn_bands[n]; 1679 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1680 uint8_t chan; 1681 int i; 1682 1683 iwn_read_prom_data(sc, addr, channels, 1684 band->nchan * sizeof (struct iwn_eeprom_chan)); 1685 1686 for (i = 0; i < band->nchan; i++) { 1687 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1688 continue; 1689 1690 chan = band->chan[i]; 1691 1692 if (n == 0) { /* 2GHz band */ 1693 ic->ic_channels[chan].ic_freq = 1694 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1695 ic->ic_channels[chan].ic_flags = 1696 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1697 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1698 1699 } else { /* 5GHz band */ 1700 /* 1701 * Some adapters support channels 7, 8, 11 and 12 1702 * both in the 2GHz and 4.9GHz bands. 1703 * Because of limitations in our net80211 layer, 1704 * we don't support them in the 4.9GHz band. 1705 */ 1706 if (chan <= 14) 1707 continue; 1708 1709 ic->ic_channels[chan].ic_freq = 1710 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1711 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1712 /* We have at least one valid 5GHz channel. */ 1713 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1714 } 1715 1716 /* Is active scan allowed on this channel? */ 1717 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1718 ic->ic_channels[chan].ic_flags |= 1719 IEEE80211_CHAN_PASSIVE; 1720 } 1721 1722 /* Save maximum allowed TX power for this channel. */ 1723 sc->maxpwr[chan] = channels[i].maxpwr; 1724 1725 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1726 chan, channels[i].flags, sc->maxpwr[chan])); 1727 } 1728 } 1729 1730 static void 1731 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1732 { 1733 struct iwn_eeprom_enhinfo enhinfo[35]; 1734 uint16_t val, base; 1735 int8_t maxpwr; 1736 int i; 1737 1738 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1739 base = le16toh(val); 1740 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1741 enhinfo, sizeof enhinfo); 1742 1743 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1744 for (i = 0; i < __arraycount(enhinfo); i++) { 1745 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1746 continue; /* Skip invalid entries. */ 1747 1748 maxpwr = 0; 1749 if (sc->txchainmask & IWN_ANT_A) 1750 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1751 if (sc->txchainmask & IWN_ANT_B) 1752 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1753 if (sc->txchainmask & IWN_ANT_C) 1754 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1755 if (sc->ntxchains == 2) 1756 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1757 else if (sc->ntxchains == 3) 1758 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1759 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1760 1761 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1762 sc->enh_maxpwr[i] = maxpwr; 1763 } 1764 } 1765 1766 static struct ieee80211_node * 1767 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1768 { 1769 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1770 } 1771 1772 static void 1773 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1774 { 1775 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1776 struct iwn_node *wn = (void *)ni; 1777 uint8_t rate; 1778 int ridx, i; 1779 1780 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1781 /* Start at lowest available bit-rate, AMRR will raise. */ 1782 ni->ni_txrate = 0; 1783 1784 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1785 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1786 /* Map 802.11 rate to HW rate index. */ 1787 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1788 if (iwn_rates[ridx].rate == rate) 1789 break; 1790 wn->ridx[i] = ridx; 1791 } 1792 } 1793 1794 static int 1795 iwn_media_change(struct ifnet *ifp) 1796 { 1797 struct iwn_softc *sc = ifp->if_softc; 1798 struct ieee80211com *ic = &sc->sc_ic; 1799 uint8_t rate, ridx; 1800 int error; 1801 1802 error = ieee80211_media_change(ifp); 1803 if (error != ENETRESET) 1804 return error; 1805 1806 if (ic->ic_fixed_rate != -1) { 1807 rate = ic->ic_sup_rates[ic->ic_curmode]. 1808 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1809 /* Map 802.11 rate to HW rate index. */ 1810 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1811 if (iwn_rates[ridx].rate == rate) 1812 break; 1813 sc->fixed_ridx = ridx; 1814 } 1815 1816 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1817 (IFF_UP | IFF_RUNNING)) { 1818 iwn_stop(ifp, 0); 1819 error = iwn_init(ifp); 1820 } 1821 return error; 1822 } 1823 1824 static int 1825 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1826 { 1827 struct ifnet *ifp = ic->ic_ifp; 1828 struct iwn_softc *sc = ifp->if_softc; 1829 int error; 1830 1831 callout_stop(&sc->calib_to); 1832 1833 switch (nstate) { 1834 case IEEE80211_S_SCAN: 1835 /* XXX Do not abort a running scan. */ 1836 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1837 aprint_error_dev(sc->sc_dev, 1838 "scan request while scanning ignored\n"); 1839 break; 1840 } 1841 1842 /* XXX Not sure if call and flags are needed. */ 1843 ieee80211_node_table_reset(&ic->ic_scan); 1844 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1845 sc->sc_flags |= IWN_FLAG_SCANNING; 1846 1847 /* Make the link LED blink while we're scanning. */ 1848 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1849 1850 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1851 aprint_error_dev(sc->sc_dev, 1852 "could not initiate scan\n"); 1853 return error; 1854 } 1855 ic->ic_state = nstate; 1856 return 0; 1857 1858 case IEEE80211_S_ASSOC: 1859 if (ic->ic_state != IEEE80211_S_RUN) 1860 break; 1861 /* FALLTHROUGH */ 1862 case IEEE80211_S_AUTH: 1863 /* Reset state to handle reassociations correctly. */ 1864 sc->rxon.associd = 0; 1865 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1866 sc->calib.state = IWN_CALIB_STATE_INIT; 1867 1868 if ((error = iwn_auth(sc)) != 0) { 1869 aprint_error_dev(sc->sc_dev, 1870 "could not move to auth state\n"); 1871 return error; 1872 } 1873 break; 1874 1875 case IEEE80211_S_RUN: 1876 if ((error = iwn_run(sc)) != 0) { 1877 aprint_error_dev(sc->sc_dev, 1878 "could not move to run state\n"); 1879 return error; 1880 } 1881 break; 1882 1883 case IEEE80211_S_INIT: 1884 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1885 sc->calib.state = IWN_CALIB_STATE_INIT; 1886 break; 1887 } 1888 1889 return sc->sc_newstate(ic, nstate, arg); 1890 } 1891 1892 static void 1893 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1894 { 1895 struct iwn_softc *sc = arg; 1896 struct iwn_node *wn = (struct iwn_node *)ni; 1897 1898 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1899 } 1900 1901 static void 1902 iwn_calib_timeout(void *arg) 1903 { 1904 struct iwn_softc *sc = arg; 1905 struct ieee80211com *ic = &sc->sc_ic; 1906 int s; 1907 1908 s = splnet(); 1909 if (ic->ic_fixed_rate == -1) { 1910 if (ic->ic_opmode == IEEE80211_M_STA) 1911 iwn_iter_func(sc, ic->ic_bss); 1912 else 1913 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1914 } 1915 /* Force automatic TX power calibration every 60 secs. */ 1916 if (++sc->calib_cnt >= 120) { 1917 uint32_t flags = 0; 1918 1919 DPRINTF(("sending request for statistics\n")); 1920 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1921 sizeof flags, 1); 1922 sc->calib_cnt = 0; 1923 } 1924 splx(s); 1925 1926 /* Automatic rate control triggered every 500ms. */ 1927 callout_schedule(&sc->calib_to, hz/2); 1928 } 1929 1930 /* 1931 * Process an RX_PHY firmware notification. This is usually immediately 1932 * followed by an MPDU_RX_DONE notification. 1933 */ 1934 static void 1935 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1936 struct iwn_rx_data *data) 1937 { 1938 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1939 1940 DPRINTFN(2, ("received PHY stats\n")); 1941 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1942 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1943 1944 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1945 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1946 sc->last_rx_valid = 1; 1947 } 1948 1949 /* 1950 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1951 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1952 */ 1953 static void 1954 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1955 struct iwn_rx_data *data) 1956 { 1957 const struct iwn_hal *hal = sc->sc_hal; 1958 struct ieee80211com *ic = &sc->sc_ic; 1959 struct ifnet *ifp = ic->ic_ifp; 1960 struct iwn_rx_ring *ring = &sc->rxq; 1961 struct ieee80211_frame *wh; 1962 struct ieee80211_node *ni; 1963 struct mbuf *m, *m1; 1964 struct iwn_rx_stat *stat; 1965 char *head; 1966 uint32_t flags; 1967 int error, len, rssi; 1968 1969 if (desc->type == IWN_MPDU_RX_DONE) { 1970 /* Check for prior RX_PHY notification. */ 1971 if (!sc->last_rx_valid) { 1972 DPRINTF(("missing RX_PHY\n")); 1973 ifp->if_ierrors++; 1974 return; 1975 } 1976 sc->last_rx_valid = 0; 1977 stat = &sc->last_rx_stat; 1978 } else 1979 stat = (struct iwn_rx_stat *)(desc + 1); 1980 1981 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1982 BUS_DMASYNC_POSTREAD); 1983 1984 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1985 aprint_error_dev(sc->sc_dev, 1986 "invalid RX statistic header\n"); 1987 ifp->if_ierrors++; 1988 return; 1989 } 1990 if (desc->type == IWN_MPDU_RX_DONE) { 1991 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1992 head = (char *)(mpdu + 1); 1993 len = le16toh(mpdu->len); 1994 } else { 1995 head = (char *)(stat + 1) + stat->cfg_phy_len; 1996 len = le16toh(stat->len); 1997 } 1998 1999 flags = le32toh(*(uint32_t *)(head + len)); 2000 2001 /* Discard frames with a bad FCS early. */ 2002 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2003 DPRINTFN(2, ("RX flags error %x\n", flags)); 2004 ifp->if_ierrors++; 2005 return; 2006 } 2007 /* Discard frames that are too short. */ 2008 if (len < sizeof (*wh)) { 2009 DPRINTF(("frame too short: %d\n", len)); 2010 ic->ic_stats.is_rx_tooshort++; 2011 ifp->if_ierrors++; 2012 return; 2013 } 2014 2015 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2016 if (m1 == NULL) { 2017 ic->ic_stats.is_rx_nobuf++; 2018 ifp->if_ierrors++; 2019 return; 2020 } 2021 bus_dmamap_unload(sc->sc_dmat, data->map); 2022 2023 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2024 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2025 if (error != 0) { 2026 m_freem(m1); 2027 2028 /* Try to reload the old mbuf. */ 2029 error = bus_dmamap_load(sc->sc_dmat, data->map, 2030 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2031 BUS_DMA_NOWAIT | BUS_DMA_READ); 2032 if (error != 0) { 2033 panic("%s: could not load old RX mbuf", 2034 device_xname(sc->sc_dev)); 2035 } 2036 /* Physical address may have changed. */ 2037 ring->desc[ring->cur] = 2038 htole32(data->map->dm_segs[0].ds_addr >> 8); 2039 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2040 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2041 BUS_DMASYNC_PREWRITE); 2042 ifp->if_ierrors++; 2043 return; 2044 } 2045 2046 m = data->m; 2047 data->m = m1; 2048 /* Update RX descriptor. */ 2049 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2050 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2051 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2052 BUS_DMASYNC_PREWRITE); 2053 2054 /* Finalize mbuf. */ 2055 m->m_pkthdr.rcvif = ifp; 2056 m->m_data = head; 2057 m->m_pkthdr.len = m->m_len = len; 2058 2059 /* Grab a reference to the source node. */ 2060 wh = mtod(m, struct ieee80211_frame *); 2061 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2062 2063 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2064 /* NetBSD does decryption in ieee80211_input. */ 2065 2066 rssi = hal->get_rssi(stat); 2067 2068 /* XXX Added for NetBSD: scans never stop without it */ 2069 if (ic->ic_state == IEEE80211_S_SCAN) 2070 iwn_fix_channel(ic, m); 2071 2072 if (sc->sc_drvbpf != NULL) { 2073 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2074 2075 tap->wr_flags = 0; 2076 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2077 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2078 tap->wr_chan_freq = 2079 htole16(ic->ic_channels[stat->chan].ic_freq); 2080 tap->wr_chan_flags = 2081 htole16(ic->ic_channels[stat->chan].ic_flags); 2082 tap->wr_dbm_antsignal = (int8_t)rssi; 2083 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2084 tap->wr_tsft = stat->tstamp; 2085 switch (stat->rate) { 2086 /* CCK rates. */ 2087 case 10: tap->wr_rate = 2; break; 2088 case 20: tap->wr_rate = 4; break; 2089 case 55: tap->wr_rate = 11; break; 2090 case 110: tap->wr_rate = 22; break; 2091 /* OFDM rates. */ 2092 case 0xd: tap->wr_rate = 12; break; 2093 case 0xf: tap->wr_rate = 18; break; 2094 case 0x5: tap->wr_rate = 24; break; 2095 case 0x7: tap->wr_rate = 36; break; 2096 case 0x9: tap->wr_rate = 48; break; 2097 case 0xb: tap->wr_rate = 72; break; 2098 case 0x1: tap->wr_rate = 96; break; 2099 case 0x3: tap->wr_rate = 108; break; 2100 /* Unknown rate: should not happen. */ 2101 default: tap->wr_rate = 0; 2102 } 2103 2104 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2105 } 2106 2107 /* Send the frame to the 802.11 layer. */ 2108 ieee80211_input(ic, m, ni, rssi, 0); 2109 2110 /* Node is no longer needed. */ 2111 ieee80211_free_node(ni); 2112 } 2113 2114 #ifndef IEEE80211_NO_HT 2115 /* Process an incoming Compressed BlockAck. */ 2116 static void 2117 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2118 struct iwn_rx_data *data) 2119 { 2120 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2121 struct iwn_tx_ring *txq; 2122 2123 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2124 BUS_DMASYNC_POSTREAD); 2125 2126 txq = &sc->txq[le16toh(ba->qid)]; 2127 /* XXX TBD */ 2128 } 2129 #endif 2130 2131 /* 2132 * Process a CALIBRATION_RESULT notification sent by the initialization 2133 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2134 */ 2135 static void 2136 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2137 struct iwn_rx_data *data) 2138 { 2139 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2140 int len, idx = -1; 2141 2142 /* Runtime firmware should not send such a notification. */ 2143 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2144 return; 2145 2146 len = (le32toh(desc->len) & 0x3fff) - 4; 2147 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2148 BUS_DMASYNC_POSTREAD); 2149 2150 switch (calib->code) { 2151 case IWN5000_PHY_CALIB_DC: 2152 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2153 sc->hw_type == IWN_HW_REV_TYPE_6050) 2154 idx = 0; 2155 break; 2156 case IWN5000_PHY_CALIB_LO: 2157 idx = 1; 2158 break; 2159 case IWN5000_PHY_CALIB_TX_IQ: 2160 idx = 2; 2161 break; 2162 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2163 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2164 sc->hw_type != IWN_HW_REV_TYPE_5150) 2165 idx = 3; 2166 break; 2167 case IWN5000_PHY_CALIB_BASE_BAND: 2168 idx = 4; 2169 break; 2170 } 2171 if (idx == -1) /* Ignore other results. */ 2172 return; 2173 2174 /* Save calibration result. */ 2175 if (sc->calibcmd[idx].buf != NULL) 2176 free(sc->calibcmd[idx].buf, M_DEVBUF); 2177 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2178 if (sc->calibcmd[idx].buf == NULL) { 2179 DPRINTF(("not enough memory for calibration result %d\n", 2180 calib->code)); 2181 return; 2182 } 2183 DPRINTF(("saving calibration result code=%d len=%d\n", 2184 calib->code, len)); 2185 sc->calibcmd[idx].len = len; 2186 memcpy(sc->calibcmd[idx].buf, calib, len); 2187 } 2188 2189 /* 2190 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2191 * The latter is sent by the firmware after each received beacon. 2192 */ 2193 static void 2194 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2195 struct iwn_rx_data *data) 2196 { 2197 const struct iwn_hal *hal = sc->sc_hal; 2198 struct ieee80211com *ic = &sc->sc_ic; 2199 struct iwn_calib_state *calib = &sc->calib; 2200 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2201 int temp; 2202 2203 /* Ignore statistics received during a scan. */ 2204 if (ic->ic_state != IEEE80211_S_RUN) 2205 return; 2206 2207 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2208 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2209 2210 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2211 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2212 2213 /* Test if temperature has changed. */ 2214 if (stats->general.temp != sc->rawtemp) { 2215 /* Convert "raw" temperature to degC. */ 2216 sc->rawtemp = stats->general.temp; 2217 temp = hal->get_temperature(sc); 2218 DPRINTFN(2, ("temperature=%dC\n", temp)); 2219 2220 #ifndef SMALL_KERNEL 2221 /* Update temperature sensor. */ 2222 sc->sc_sensor.value_cur = IWN_CTOMUK(temp); 2223 sc->sc_sensor.state = ENVSYS_SVALID; 2224 #endif 2225 2226 /* Update TX power if need be (4965AGN only.) */ 2227 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2228 iwn4965_power_calibration(sc, temp); 2229 } 2230 2231 if (desc->type != IWN_BEACON_STATISTICS) 2232 return; /* Reply to a statistics request. */ 2233 2234 sc->noise = iwn_get_noise(&stats->rx.general); 2235 2236 /* Test that RSSI and noise are present in stats report. */ 2237 if (le32toh(stats->rx.general.flags) != 1) { 2238 DPRINTF(("received statistics without RSSI\n")); 2239 return; 2240 } 2241 2242 if (calib->state == IWN_CALIB_STATE_ASSOC) 2243 iwn_collect_noise(sc, &stats->rx.general); 2244 else if (calib->state == IWN_CALIB_STATE_RUN) 2245 iwn_tune_sensitivity(sc, &stats->rx); 2246 } 2247 2248 /* 2249 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2250 * and 5000 adapters have different incompatible TX status formats. 2251 */ 2252 static void 2253 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2254 struct iwn_rx_data *data) 2255 { 2256 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2257 2258 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2259 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2260 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2261 } 2262 2263 static void 2264 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2265 struct iwn_rx_data *data) 2266 { 2267 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2268 2269 #ifdef notyet 2270 /* Reset TX scheduler slot. */ 2271 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2272 #endif 2273 2274 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2275 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2276 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2277 } 2278 2279 /* 2280 * Adapter-independent backend for TX_DONE firmware notifications. 2281 */ 2282 static void 2283 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2284 uint8_t status) 2285 { 2286 struct ieee80211com *ic = &sc->sc_ic; 2287 struct ifnet *ifp = ic->ic_ifp; 2288 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2289 struct iwn_tx_data *data = &ring->data[desc->idx]; 2290 struct iwn_node *wn = (struct iwn_node *)data->ni; 2291 2292 /* Update rate control statistics. */ 2293 wn->amn.amn_txcnt++; 2294 if (ackfailcnt > 0) 2295 wn->amn.amn_retrycnt++; 2296 2297 if (status != 1 && status != 2) 2298 ifp->if_oerrors++; 2299 else 2300 ifp->if_opackets++; 2301 2302 /* Unmap and free mbuf. */ 2303 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2304 BUS_DMASYNC_POSTWRITE); 2305 bus_dmamap_unload(sc->sc_dmat, data->map); 2306 m_freem(data->m); 2307 data->m = NULL; 2308 ieee80211_free_node(data->ni); 2309 data->ni = NULL; 2310 2311 sc->sc_tx_timer = 0; 2312 if (--ring->queued < IWN_TX_RING_LOMARK) { 2313 sc->qfullmsk &= ~(1 << ring->qid); 2314 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2315 ifp->if_flags &= ~IFF_OACTIVE; 2316 (*ifp->if_start)(ifp); 2317 } 2318 } 2319 } 2320 2321 /* 2322 * Process a "command done" firmware notification. This is where we wakeup 2323 * processes waiting for a synchronous command completion. 2324 */ 2325 static void 2326 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2327 { 2328 struct iwn_tx_ring *ring = &sc->txq[4]; 2329 struct iwn_tx_data *data; 2330 2331 if ((desc->qid & 0xf) != 4) 2332 return; /* Not a command ack. */ 2333 2334 data = &ring->data[desc->idx]; 2335 2336 /* If the command was mapped in an mbuf, free it. */ 2337 if (data->m != NULL) { 2338 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2339 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2340 bus_dmamap_unload(sc->sc_dmat, data->map); 2341 m_freem(data->m); 2342 data->m = NULL; 2343 } 2344 wakeup(&ring->desc[desc->idx]); 2345 } 2346 2347 /* 2348 * Process an INT_FH_RX or INT_SW_RX interrupt. 2349 */ 2350 static void 2351 iwn_notif_intr(struct iwn_softc *sc) 2352 { 2353 struct ieee80211com *ic = &sc->sc_ic; 2354 struct ifnet *ifp = ic->ic_ifp; 2355 uint16_t hw; 2356 2357 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2358 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2359 2360 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2361 while (sc->rxq.cur != hw) { 2362 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2363 struct iwn_rx_desc *desc; 2364 2365 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2366 BUS_DMASYNC_POSTREAD); 2367 desc = mtod(data->m, struct iwn_rx_desc *); 2368 2369 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2370 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2371 2372 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2373 iwn_cmd_done(sc, desc); 2374 2375 switch (desc->type) { 2376 case IWN_RX_PHY: 2377 iwn_rx_phy(sc, desc, data); 2378 break; 2379 2380 case IWN_RX_DONE: /* 4965AGN only. */ 2381 case IWN_MPDU_RX_DONE: 2382 /* An 802.11 frame has been received. */ 2383 iwn_rx_done(sc, desc, data); 2384 break; 2385 #ifndef IEEE80211_NO_HT 2386 case IWN_RX_COMPRESSED_BA: 2387 /* A Compressed BlockAck has been received. */ 2388 iwn_rx_compressed_ba(sc, desc, data); 2389 break; 2390 #endif 2391 case IWN_TX_DONE: 2392 /* An 802.11 frame has been transmitted. */ 2393 sc->sc_hal->tx_done(sc, desc, data); 2394 break; 2395 2396 case IWN_RX_STATISTICS: 2397 case IWN_BEACON_STATISTICS: 2398 iwn_rx_statistics(sc, desc, data); 2399 break; 2400 2401 case IWN_BEACON_MISSED: 2402 { 2403 struct iwn_beacon_missed *miss = 2404 (struct iwn_beacon_missed *)(desc + 1); 2405 2406 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2407 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2408 /* 2409 * If more than 5 consecutive beacons are missed, 2410 * reinitialize the sensitivity state machine. 2411 */ 2412 DPRINTF(("beacons missed %d/%d\n", 2413 le32toh(miss->consecutive), le32toh(miss->total))); 2414 if (ic->ic_state == IEEE80211_S_RUN && 2415 le32toh(miss->consecutive) > 5) 2416 (void)iwn_init_sensitivity(sc); 2417 break; 2418 } 2419 case IWN_UC_READY: 2420 { 2421 struct iwn_ucode_info *uc = 2422 (struct iwn_ucode_info *)(desc + 1); 2423 2424 /* The microcontroller is ready. */ 2425 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2426 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2427 DPRINTF(("microcode alive notification version=%d.%d " 2428 "subtype=%x alive=%x\n", uc->major, uc->minor, 2429 uc->subtype, le32toh(uc->valid))); 2430 2431 if (le32toh(uc->valid) != 1) { 2432 aprint_error_dev(sc->sc_dev, 2433 "microcontroller initialization " 2434 "failed\n"); 2435 break; 2436 } 2437 if (uc->subtype == IWN_UCODE_INIT) { 2438 /* Save microcontroller report. */ 2439 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2440 } 2441 /* Save the address of the error log in SRAM. */ 2442 sc->errptr = le32toh(uc->errptr); 2443 break; 2444 } 2445 case IWN_STATE_CHANGED: 2446 { 2447 uint32_t *status = (uint32_t *)(desc + 1); 2448 2449 /* Enabled/disabled notification. */ 2450 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2451 sizeof (*status), BUS_DMASYNC_POSTREAD); 2452 DPRINTF(("state changed to %x\n", le32toh(*status))); 2453 2454 if (le32toh(*status) & 1) { 2455 /* The radio button has to be pushed. */ 2456 aprint_error_dev(sc->sc_dev, 2457 "Radio transmitter is off\n"); 2458 /* Turn the interface down. */ 2459 ifp->if_flags &= ~IFF_UP; 2460 iwn_stop(ifp, 1); 2461 return; /* No further processing. */ 2462 } 2463 break; 2464 } 2465 case IWN_START_SCAN: 2466 { 2467 struct iwn_start_scan *scan = 2468 (struct iwn_start_scan *)(desc + 1); 2469 2470 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2471 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2472 DPRINTFN(2, ("scanning channel %d status %x\n", 2473 scan->chan, le32toh(scan->status))); 2474 2475 /* Fix current channel. */ 2476 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2477 break; 2478 } 2479 case IWN_STOP_SCAN: 2480 { 2481 struct iwn_stop_scan *scan = 2482 (struct iwn_stop_scan *)(desc + 1); 2483 2484 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2485 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2486 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2487 scan->nchan, scan->status, scan->chan)); 2488 2489 if (scan->status == 1 && scan->chan <= 14 && 2490 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2491 /* 2492 * We just finished scanning 2GHz channels, 2493 * start scanning 5GHz ones. 2494 */ 2495 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2496 break; 2497 } 2498 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2499 ieee80211_end_scan(ic); 2500 break; 2501 } 2502 case IWN5000_CALIBRATION_RESULT: 2503 iwn5000_rx_calib_results(sc, desc, data); 2504 break; 2505 2506 case IWN5000_CALIBRATION_DONE: 2507 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2508 wakeup(sc); 2509 break; 2510 } 2511 2512 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2513 } 2514 2515 /* Tell the firmware what we have processed. */ 2516 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2517 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2518 } 2519 2520 /* 2521 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2522 * from power-down sleep mode. 2523 */ 2524 static void 2525 iwn_wakeup_intr(struct iwn_softc *sc) 2526 { 2527 int qid; 2528 2529 DPRINTF(("ucode wakeup from power-down sleep\n")); 2530 2531 /* Wakeup RX and TX rings. */ 2532 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2533 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2534 struct iwn_tx_ring *ring = &sc->txq[qid]; 2535 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2536 } 2537 } 2538 2539 /* 2540 * Dump the error log of the firmware when a firmware panic occurs. Although 2541 * we can't debug the firmware because it is neither open source nor free, it 2542 * can help us to identify certain classes of problems. 2543 */ 2544 static void 2545 iwn_fatal_intr(struct iwn_softc *sc) 2546 { 2547 const struct iwn_hal *hal = sc->sc_hal; 2548 struct iwn_fw_dump dump; 2549 int i; 2550 2551 /* Force a complete recalibration on next init. */ 2552 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2553 2554 /* Check that the error log address is valid. */ 2555 if (sc->errptr < IWN_FW_DATA_BASE || 2556 sc->errptr + sizeof (dump) > 2557 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2558 aprint_error_dev(sc->sc_dev, 2559 "bad firmware error log address 0x%08x\n", sc->errptr); 2560 return; 2561 } 2562 if (iwn_nic_lock(sc) != 0) { 2563 aprint_error_dev(sc->sc_dev, 2564 "could not read firmware error log\n"); 2565 return; 2566 } 2567 /* Read firmware error log from SRAM. */ 2568 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2569 sizeof (dump) / sizeof (uint32_t)); 2570 iwn_nic_unlock(sc); 2571 2572 if (dump.valid == 0) { 2573 aprint_error_dev(sc->sc_dev, 2574 "firmware error log is empty\n"); 2575 return; 2576 } 2577 aprint_error("firmware error log:\n"); 2578 aprint_error(" error type = \"%s\" (0x%08X)\n", 2579 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2580 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2581 dump.id); 2582 aprint_error(" program counter = 0x%08X\n", dump.pc); 2583 aprint_error(" source line = 0x%08X\n", dump.src_line); 2584 aprint_error(" error data = 0x%08X%08X\n", 2585 dump.error_data[0], dump.error_data[1]); 2586 aprint_error(" branch link = 0x%08X%08X\n", 2587 dump.branch_link[0], dump.branch_link[1]); 2588 aprint_error(" interrupt link = 0x%08X%08X\n", 2589 dump.interrupt_link[0], dump.interrupt_link[1]); 2590 aprint_error(" time = %u\n", dump.time[0]); 2591 2592 /* Dump driver status (TX and RX rings) while we're here. */ 2593 aprint_error("driver status:\n"); 2594 for (i = 0; i < hal->ntxqs; i++) { 2595 struct iwn_tx_ring *ring = &sc->txq[i]; 2596 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2597 i, ring->qid, ring->cur, ring->queued); 2598 } 2599 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2600 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2601 } 2602 2603 static int 2604 iwn_intr(void *arg) 2605 { 2606 struct iwn_softc *sc = arg; 2607 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2608 uint32_t r1, r2, tmp; 2609 2610 /* Disable interrupts. */ 2611 IWN_WRITE(sc, IWN_INT_MASK, 0); 2612 2613 /* Read interrupts from ICT (fast) or from registers (slow). */ 2614 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2615 tmp = 0; 2616 while (sc->ict[sc->ict_cur] != 0) { 2617 tmp |= sc->ict[sc->ict_cur]; 2618 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2619 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2620 } 2621 tmp = le32toh(tmp); 2622 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2623 tmp = 0; 2624 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2625 tmp |= 0x8000; 2626 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2627 r2 = 0; /* Unused. */ 2628 } else { 2629 r1 = IWN_READ(sc, IWN_INT); 2630 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2631 return 0; /* Hardware gone! */ 2632 r2 = IWN_READ(sc, IWN_FH_INT); 2633 } 2634 if (r1 == 0 && r2 == 0) { 2635 if (ifp->if_flags & IFF_UP) 2636 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2637 return 0; /* Interrupt not for us. */ 2638 } 2639 2640 /* Acknowledge interrupts. */ 2641 IWN_WRITE(sc, IWN_INT, r1); 2642 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2643 IWN_WRITE(sc, IWN_FH_INT, r2); 2644 2645 if (r1 & IWN_INT_RF_TOGGLED) { 2646 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2647 aprint_error_dev(sc->sc_dev, 2648 "RF switch: radio %s\n", 2649 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2650 } 2651 if (r1 & IWN_INT_CT_REACHED) { 2652 aprint_error_dev(sc->sc_dev, 2653 "critical temperature reached!\n"); 2654 } 2655 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2656 aprint_error_dev(sc->sc_dev, 2657 "fatal firmware error\n"); 2658 /* Dump firmware error log and stop. */ 2659 iwn_fatal_intr(sc); 2660 ifp->if_flags &= ~IFF_UP; 2661 iwn_stop(ifp, 1); 2662 return 1; 2663 } 2664 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2665 (r2 & IWN_FH_INT_RX)) { 2666 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2667 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2668 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2669 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2670 IWN_INT_PERIODIC_DIS); 2671 iwn_notif_intr(sc); 2672 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2673 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2674 IWN_INT_PERIODIC_ENA); 2675 } 2676 } else 2677 iwn_notif_intr(sc); 2678 } 2679 2680 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2681 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2682 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2683 wakeup(sc); /* FH DMA transfer completed. */ 2684 } 2685 2686 if (r1 & IWN_INT_ALIVE) 2687 wakeup(sc); /* Firmware is alive. */ 2688 2689 if (r1 & IWN_INT_WAKEUP) 2690 iwn_wakeup_intr(sc); 2691 2692 /* Re-enable interrupts. */ 2693 if (ifp->if_flags & IFF_UP) 2694 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2695 2696 return 1; 2697 } 2698 2699 /* 2700 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2701 * 5000 adapters use a slightly different format.) 2702 */ 2703 static void 2704 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2705 uint16_t len) 2706 { 2707 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2708 2709 *w = htole16(len + 8); 2710 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2711 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2712 sizeof (uint16_t), 2713 BUS_DMASYNC_PREWRITE); 2714 if (idx < IWN_SCHED_WINSZ) { 2715 *(w + IWN_TX_RING_COUNT) = *w; 2716 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2717 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2718 (char *)(void *)sc->sched_dma.vaddr, 2719 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2720 } 2721 } 2722 2723 static void 2724 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2725 uint16_t len) 2726 { 2727 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2728 2729 *w = htole16(id << 12 | (len + 8)); 2730 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2731 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2732 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2733 if (idx < IWN_SCHED_WINSZ) { 2734 *(w + IWN_TX_RING_COUNT) = *w; 2735 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2736 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2737 (char *)(void *)sc->sched_dma.vaddr, 2738 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2739 } 2740 } 2741 2742 #ifdef notyet 2743 static void 2744 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2745 { 2746 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2747 2748 *w = (*w & htole16(0xf000)) | htole16(1); 2749 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2750 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2751 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2752 if (idx < IWN_SCHED_WINSZ) { 2753 *(w + IWN_TX_RING_COUNT) = *w; 2754 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2755 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2756 (char *)(void *)sc->sched_dma.vaddr, 2757 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2758 } 2759 } 2760 #endif 2761 2762 static int 2763 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2764 { 2765 const struct iwn_hal *hal = sc->sc_hal; 2766 struct ieee80211com *ic = &sc->sc_ic; 2767 struct iwn_node *wn = (void *)ni; 2768 struct iwn_tx_ring *ring; 2769 struct iwn_tx_desc *desc; 2770 struct iwn_tx_data *data; 2771 struct iwn_tx_cmd *cmd; 2772 struct iwn_cmd_data *tx; 2773 const struct iwn_rate *rinfo; 2774 struct ieee80211_frame *wh; 2775 struct ieee80211_key *k = NULL; 2776 struct mbuf *m1; 2777 uint32_t flags; 2778 u_int hdrlen; 2779 bus_dma_segment_t *seg; 2780 uint8_t tid, ridx, txant, type; 2781 int i, totlen, error, pad; 2782 2783 const struct chanAccParams *cap; 2784 int noack; 2785 int hdrlen2; 2786 2787 wh = mtod(m, struct ieee80211_frame *); 2788 hdrlen = ieee80211_anyhdrsize(wh); 2789 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2790 2791 hdrlen2 = (IEEE80211_QOS_HAS_SEQ(wh)) ? 2792 sizeof (struct ieee80211_qosframe) : 2793 sizeof (struct ieee80211_frame); 2794 2795 if (hdrlen != hdrlen2) 2796 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2797 hdrlen, hdrlen2); 2798 2799 /* XXX OpenBSD sets a different tid when using QOS */ 2800 tid = 0; 2801 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2802 cap = &ic->ic_wme.wme_chanParams; 2803 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2804 } 2805 else 2806 noack = 0; 2807 2808 ring = &sc->txq[ac]; 2809 desc = &ring->desc[ring->cur]; 2810 data = &ring->data[ring->cur]; 2811 2812 /* Choose a TX rate index. */ 2813 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2814 type != IEEE80211_FC0_TYPE_DATA) { 2815 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2816 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2817 } else if (ic->ic_fixed_rate != -1) { 2818 ridx = sc->fixed_ridx; 2819 } else 2820 ridx = wn->ridx[ni->ni_txrate]; 2821 rinfo = &iwn_rates[ridx]; 2822 2823 /* Encrypt the frame if need be. */ 2824 /* 2825 * XXX For now, NetBSD swaps the encryption and bpf sections 2826 * in order to match old code and other drivers. Tests with 2827 * tcpdump indicates that the order is irrelevant, however, 2828 * as bpf produces unencrypted data for both ordering choices. 2829 */ 2830 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2831 k = ieee80211_crypto_encap(ic, ni, m); 2832 if (k == NULL) { 2833 m_freem(m); 2834 return ENOBUFS; 2835 } 2836 /* Packet header may have moved, reset our local pointer. */ 2837 wh = mtod(m, struct ieee80211_frame *); 2838 } 2839 totlen = m->m_pkthdr.len; 2840 2841 if (sc->sc_drvbpf != NULL) { 2842 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2843 2844 tap->wt_flags = 0; 2845 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2846 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2847 tap->wt_rate = rinfo->rate; 2848 tap->wt_hwqueue = ac; 2849 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2850 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2851 2852 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2853 } 2854 2855 /* Prepare TX firmware command. */ 2856 cmd = &ring->cmd[ring->cur]; 2857 cmd->code = IWN_CMD_TX_DATA; 2858 cmd->flags = 0; 2859 cmd->qid = ring->qid; 2860 cmd->idx = ring->cur; 2861 2862 tx = (struct iwn_cmd_data *)cmd->data; 2863 /* NB: No need to clear tx, all fields are reinitialized here. */ 2864 tx->scratch = 0; /* clear "scratch" area */ 2865 2866 flags = 0; 2867 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2868 /* Unicast frame, check if an ACK is expected. */ 2869 if (!noack) 2870 flags |= IWN_TX_NEED_ACK; 2871 } 2872 2873 #ifdef notyet 2874 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2875 if ((wh->i_fc[0] & 2876 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2877 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2878 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2879 #endif 2880 2881 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2882 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2883 2884 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2885 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2886 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2887 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2888 flags |= IWN_TX_NEED_RTS; 2889 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2890 ridx >= IWN_RIDX_OFDM6) { 2891 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2892 flags |= IWN_TX_NEED_CTS; 2893 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2894 flags |= IWN_TX_NEED_RTS; 2895 } 2896 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2897 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2898 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2899 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2900 flags |= IWN_TX_NEED_PROTECTION; 2901 } else 2902 flags |= IWN_TX_FULL_TXOP; 2903 } 2904 } 2905 2906 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2907 type != IEEE80211_FC0_TYPE_DATA) 2908 tx->id = hal->broadcast_id; 2909 else 2910 tx->id = wn->id; 2911 2912 if (type == IEEE80211_FC0_TYPE_MGT) { 2913 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2914 2915 #ifndef IEEE80211_STA_ONLY 2916 /* Tell HW to set timestamp in probe responses. */ 2917 /* XXX NetBSD rev 1.11 added probe requests here but */ 2918 /* probe requests do not take timestamps (from Bergamini). */ 2919 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2920 flags |= IWN_TX_INSERT_TSTAMP; 2921 #endif 2922 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2923 /* changes here. These are not needed (from Bergamini). */ 2924 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2925 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2926 tx->timeout = htole16(3); 2927 else 2928 tx->timeout = htole16(2); 2929 } else 2930 tx->timeout = htole16(0); 2931 2932 if (hdrlen & 3) { 2933 /* First segment's length must be a multiple of 4. */ 2934 flags |= IWN_TX_NEED_PADDING; 2935 pad = 4 - (hdrlen & 3); 2936 } else 2937 pad = 0; 2938 2939 tx->len = htole16(totlen); 2940 tx->tid = tid; 2941 tx->rts_ntries = 60; 2942 tx->data_ntries = 15; 2943 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2944 tx->plcp = rinfo->plcp; 2945 tx->rflags = rinfo->flags; 2946 if (tx->id == hal->broadcast_id) { 2947 /* Group or management frame. */ 2948 tx->linkq = 0; 2949 /* XXX Alternate between antenna A and B? */ 2950 txant = IWN_LSB(sc->txchainmask); 2951 tx->rflags |= IWN_RFLAG_ANT(txant); 2952 } else { 2953 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2954 flags |= IWN_TX_LINKQ; /* enable MRR */ 2955 } 2956 /* Set physical address of "scratch area". */ 2957 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2958 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2959 2960 /* Copy 802.11 header in TX command. */ 2961 /* XXX NetBSD changed this in rev 1.20 */ 2962 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2963 2964 /* Trim 802.11 header. */ 2965 m_adj(m, hdrlen); 2966 tx->security = 0; 2967 tx->flags = htole32(flags); 2968 2969 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2970 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2971 if (error != 0) { 2972 if (error != EFBIG) { 2973 aprint_error_dev(sc->sc_dev, 2974 "can't map mbuf (error %d)\n", error); 2975 m_freem(m); 2976 return error; 2977 } 2978 /* Too many DMA segments, linearize mbuf. */ 2979 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2980 if (m1 == NULL) { 2981 m_freem(m); 2982 return ENOBUFS; 2983 } 2984 if (m->m_pkthdr.len > MHLEN) { 2985 MCLGET(m1, M_DONTWAIT); 2986 if (!(m1->m_flags & M_EXT)) { 2987 m_freem(m); 2988 m_freem(m1); 2989 return ENOBUFS; 2990 } 2991 } 2992 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2993 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2994 m_freem(m); 2995 m = m1; 2996 2997 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2998 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2999 if (error != 0) { 3000 aprint_error_dev(sc->sc_dev, 3001 "can't map mbuf (error %d)\n", error); 3002 m_freem(m); 3003 return error; 3004 } 3005 } 3006 3007 data->m = m; 3008 data->ni = ni; 3009 3010 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3011 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3012 3013 /* Fill TX descriptor. */ 3014 desc->nsegs = 1 + data->map->dm_nsegs; 3015 /* First DMA segment is used by the TX command. */ 3016 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3017 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3018 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3019 /* Other DMA segments are for data payload. */ 3020 seg = data->map->dm_segs; 3021 for (i = 1; i <= data->map->dm_nsegs; i++) { 3022 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3023 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3024 seg->ds_len << 4); 3025 seg++; 3026 } 3027 3028 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3029 BUS_DMASYNC_PREWRITE); 3030 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3031 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3032 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3033 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3034 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3035 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3036 3037 #ifdef notyet 3038 /* Update TX scheduler. */ 3039 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3040 #endif 3041 3042 /* Kick TX ring. */ 3043 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3044 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3045 3046 /* Mark TX ring as full if we reach a certain threshold. */ 3047 if (++ring->queued > IWN_TX_RING_HIMARK) 3048 sc->qfullmsk |= 1 << ring->qid; 3049 3050 return 0; 3051 } 3052 3053 static void 3054 iwn_start(struct ifnet *ifp) 3055 { 3056 struct iwn_softc *sc = ifp->if_softc; 3057 struct ieee80211com *ic = &sc->sc_ic; 3058 struct ieee80211_node *ni; 3059 struct ether_header *eh; 3060 struct mbuf *m; 3061 int ac; 3062 3063 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3064 return; 3065 3066 for (;;) { 3067 if (sc->qfullmsk != 0) { 3068 ifp->if_flags |= IFF_OACTIVE; 3069 break; 3070 } 3071 /* Send pending management frames first. */ 3072 IF_DEQUEUE(&ic->ic_mgtq, m); 3073 if (m != NULL) { 3074 ni = (void *)m->m_pkthdr.rcvif; 3075 ac = 0; 3076 goto sendit; 3077 } 3078 if (ic->ic_state != IEEE80211_S_RUN) 3079 break; 3080 3081 /* Encapsulate and send data frames. */ 3082 IFQ_DEQUEUE(&ifp->if_snd, m); 3083 if (m == NULL) 3084 break; 3085 if (m->m_len < sizeof (*eh) && 3086 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3087 ifp->if_oerrors++; 3088 continue; 3089 } 3090 eh = mtod(m, struct ether_header *); 3091 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3092 if (ni == NULL) { 3093 m_freem(m); 3094 ifp->if_oerrors++; 3095 continue; 3096 } 3097 /* classify mbuf so we can find which tx ring to use */ 3098 if (ieee80211_classify(ic, m, ni) != 0) { 3099 m_freem(m); 3100 ieee80211_free_node(ni); 3101 ifp->if_oerrors++; 3102 continue; 3103 } 3104 3105 /* No QoS encapsulation for EAPOL frames. */ 3106 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3107 M_WME_GETAC(m) : WME_AC_BE; 3108 3109 bpf_mtap(ifp, m); 3110 3111 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3112 ieee80211_free_node(ni); 3113 ifp->if_oerrors++; 3114 continue; 3115 } 3116 sendit: 3117 bpf_mtap3(ic->ic_rawbpf, m); 3118 3119 if (iwn_tx(sc, m, ni, ac) != 0) { 3120 ieee80211_free_node(ni); 3121 ifp->if_oerrors++; 3122 continue; 3123 } 3124 3125 sc->sc_tx_timer = 5; 3126 ifp->if_timer = 1; 3127 } 3128 } 3129 3130 static void 3131 iwn_watchdog(struct ifnet *ifp) 3132 { 3133 struct iwn_softc *sc = ifp->if_softc; 3134 3135 ifp->if_timer = 0; 3136 3137 if (sc->sc_tx_timer > 0) { 3138 if (--sc->sc_tx_timer == 0) { 3139 aprint_error_dev(sc->sc_dev, 3140 "device timeout\n"); 3141 ifp->if_flags &= ~IFF_UP; 3142 iwn_stop(ifp, 1); 3143 ifp->if_oerrors++; 3144 return; 3145 } 3146 ifp->if_timer = 1; 3147 } 3148 3149 ieee80211_watchdog(&sc->sc_ic); 3150 } 3151 3152 static int 3153 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3154 { 3155 struct iwn_softc *sc = ifp->if_softc; 3156 struct ieee80211com *ic = &sc->sc_ic; 3157 struct ifaddr *ifa; 3158 const struct sockaddr *sa; 3159 int s, error = 0; 3160 3161 s = splnet(); 3162 3163 switch (cmd) { 3164 case SIOCSIFADDR: 3165 ifa = (struct ifaddr *)data; 3166 ifp->if_flags |= IFF_UP; 3167 #ifdef INET 3168 if (ifa->ifa_addr->sa_family == AF_INET) 3169 arp_ifinit(&ic->ic_ac, ifa); 3170 #endif 3171 /* FALLTHROUGH */ 3172 case SIOCSIFFLAGS: 3173 /* XXX Added as it is in every NetBSD driver */ 3174 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3175 break; 3176 if (ifp->if_flags & IFF_UP) { 3177 if (!(ifp->if_flags & IFF_RUNNING)) 3178 error = iwn_init(ifp); 3179 } else { 3180 if (ifp->if_flags & IFF_RUNNING) 3181 iwn_stop(ifp, 1); 3182 } 3183 break; 3184 3185 case SIOCADDMULTI: 3186 case SIOCDELMULTI: 3187 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3188 error = (cmd == SIOCADDMULTI) ? 3189 ether_addmulti(sa, &sc->sc_ec) : 3190 ether_delmulti(sa, &sc->sc_ec); 3191 3192 if (error == ENETRESET) 3193 error = 0; 3194 break; 3195 3196 default: 3197 error = ieee80211_ioctl(ic, cmd, data); 3198 } 3199 3200 if (error == ENETRESET) { 3201 error = 0; 3202 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3203 (IFF_UP | IFF_RUNNING)) { 3204 iwn_stop(ifp, 0); 3205 error = iwn_init(ifp); 3206 } 3207 } 3208 splx(s); 3209 return error; 3210 } 3211 3212 /* 3213 * Send a command to the firmware. 3214 */ 3215 static int 3216 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3217 { 3218 struct iwn_tx_ring *ring = &sc->txq[4]; 3219 struct iwn_tx_desc *desc; 3220 struct iwn_tx_data *data; 3221 struct iwn_tx_cmd *cmd; 3222 struct mbuf *m; 3223 bus_addr_t paddr; 3224 int totlen, error; 3225 3226 desc = &ring->desc[ring->cur]; 3227 data = &ring->data[ring->cur]; 3228 totlen = 4 + size; 3229 3230 if (size > sizeof cmd->data) { 3231 /* Command is too large to fit in a descriptor. */ 3232 if (totlen > MCLBYTES) 3233 return EINVAL; 3234 MGETHDR(m, M_DONTWAIT, MT_DATA); 3235 if (m == NULL) 3236 return ENOMEM; 3237 if (totlen > MHLEN) { 3238 MCLGET(m, M_DONTWAIT); 3239 if (!(m->m_flags & M_EXT)) { 3240 m_freem(m); 3241 return ENOMEM; 3242 } 3243 } 3244 cmd = mtod(m, struct iwn_tx_cmd *); 3245 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3246 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3247 if (error != 0) { 3248 m_freem(m); 3249 return error; 3250 } 3251 data->m = m; 3252 paddr = data->map->dm_segs[0].ds_addr; 3253 } else { 3254 cmd = &ring->cmd[ring->cur]; 3255 paddr = data->cmd_paddr; 3256 } 3257 3258 cmd->code = code; 3259 cmd->flags = 0; 3260 cmd->qid = ring->qid; 3261 cmd->idx = ring->cur; 3262 memcpy(cmd->data, buf, size); 3263 3264 desc->nsegs = 1; 3265 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3266 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3267 3268 if (size > sizeof cmd->data) { 3269 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3270 BUS_DMASYNC_PREWRITE); 3271 } else { 3272 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3273 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3274 totlen, BUS_DMASYNC_PREWRITE); 3275 } 3276 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3277 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3278 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3279 3280 #ifdef notyet 3281 /* Update TX scheduler. */ 3282 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3283 #endif 3284 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3285 3286 /* Kick command ring. */ 3287 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3288 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3289 3290 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3291 } 3292 3293 static int 3294 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3295 { 3296 struct iwn4965_node_info hnode; 3297 char *src, *dst; 3298 3299 /* 3300 * We use the node structure for 5000 Series internally (it is 3301 * a superset of the one for 4965AGN). We thus copy the common 3302 * fields before sending the command. 3303 */ 3304 src = (char *)node; 3305 dst = (char *)&hnode; 3306 memcpy(dst, src, 48); 3307 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3308 memcpy(dst + 48, src + 72, 20); 3309 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3310 } 3311 3312 static int 3313 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3314 { 3315 /* Direct mapping. */ 3316 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3317 } 3318 3319 static int 3320 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3321 { 3322 struct iwn_node *wn = (void *)ni; 3323 struct ieee80211_rateset *rs = &ni->ni_rates; 3324 struct iwn_cmd_link_quality linkq; 3325 const struct iwn_rate *rinfo; 3326 uint8_t txant; 3327 int i, txrate; 3328 3329 /* Use the first valid TX antenna. */ 3330 txant = IWN_LSB(sc->txchainmask); 3331 3332 memset(&linkq, 0, sizeof linkq); 3333 linkq.id = wn->id; 3334 linkq.antmsk_1stream = txant; 3335 linkq.antmsk_2stream = IWN_ANT_AB; 3336 linkq.ampdu_max = 31; 3337 linkq.ampdu_threshold = 3; 3338 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3339 3340 /* Start at highest available bit-rate. */ 3341 txrate = rs->rs_nrates - 1; 3342 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3343 rinfo = &iwn_rates[wn->ridx[txrate]]; 3344 linkq.retry[i].plcp = rinfo->plcp; 3345 linkq.retry[i].rflags = rinfo->flags; 3346 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3347 /* Next retry at immediate lower bit-rate. */ 3348 if (txrate > 0) 3349 txrate--; 3350 } 3351 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3352 } 3353 3354 /* 3355 * Broadcast node is used to send group-addressed and management frames. 3356 */ 3357 static int 3358 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3359 { 3360 const struct iwn_hal *hal = sc->sc_hal; 3361 struct iwn_node_info node; 3362 struct iwn_cmd_link_quality linkq; 3363 const struct iwn_rate *rinfo; 3364 uint8_t txant; 3365 int i, error; 3366 3367 memset(&node, 0, sizeof node); 3368 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3369 node.id = hal->broadcast_id; 3370 DPRINTF(("adding broadcast node\n")); 3371 if ((error = hal->add_node(sc, &node, async)) != 0) 3372 return error; 3373 3374 /* Use the first valid TX antenna. */ 3375 txant = IWN_LSB(sc->txchainmask); 3376 3377 memset(&linkq, 0, sizeof linkq); 3378 linkq.id = hal->broadcast_id; 3379 linkq.antmsk_1stream = txant; 3380 linkq.antmsk_2stream = IWN_ANT_AB; 3381 linkq.ampdu_max = 64; 3382 linkq.ampdu_threshold = 3; 3383 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3384 3385 /* Use lowest mandatory bit-rate. */ 3386 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3387 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3388 linkq.retry[0].plcp = rinfo->plcp; 3389 linkq.retry[0].rflags = rinfo->flags; 3390 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3391 /* Use same bit-rate for all TX retries. */ 3392 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3393 linkq.retry[i].plcp = linkq.retry[0].plcp; 3394 linkq.retry[i].rflags = linkq.retry[0].rflags; 3395 } 3396 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3397 } 3398 3399 static void 3400 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3401 { 3402 struct iwn_cmd_led led; 3403 3404 /* Clear microcode LED ownership. */ 3405 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3406 3407 led.which = which; 3408 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3409 led.off = off; 3410 led.on = on; 3411 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3412 } 3413 3414 /* 3415 * Set the critical temperature at which the firmware will stop the radio 3416 * and notify us. 3417 */ 3418 static int 3419 iwn_set_critical_temp(struct iwn_softc *sc) 3420 { 3421 struct iwn_critical_temp crit; 3422 int32_t temp; 3423 3424 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3425 3426 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3427 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3428 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3429 temp = IWN_CTOK(110); 3430 else 3431 temp = 110; 3432 memset(&crit, 0, sizeof crit); 3433 crit.tempR = htole32(temp); 3434 DPRINTF(("setting critical temperature to %d\n", temp)); 3435 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3436 } 3437 3438 static int 3439 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3440 { 3441 struct iwn_cmd_timing cmd; 3442 uint64_t val, mod; 3443 3444 memset(&cmd, 0, sizeof cmd); 3445 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3446 cmd.bintval = htole16(ni->ni_intval); 3447 cmd.lintval = htole16(10); 3448 3449 /* Compute remaining time until next beacon. */ 3450 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3451 mod = le64toh(cmd.tstamp) % val; 3452 cmd.binitval = htole32((uint32_t)(val - mod)); 3453 3454 DPRINTF(("timing bintval=%u, tstamp=%zu, init=%u\n", 3455 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3456 3457 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3458 } 3459 3460 static void 3461 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3462 { 3463 /* Adjust TX power if need be (delta >= 3 degC.) */ 3464 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3465 if (abs(temp - sc->temp) >= 3) { 3466 /* Record temperature of last calibration. */ 3467 sc->temp = temp; 3468 (void)iwn4965_set_txpower(sc, 1); 3469 } 3470 } 3471 3472 /* 3473 * Set TX power for current channel (each rate has its own power settings). 3474 * This function takes into account the regulatory information from EEPROM, 3475 * the current temperature and the current voltage. 3476 */ 3477 static int 3478 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3479 { 3480 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3481 #define fdivround(a, b, n) \ 3482 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3483 /* Linear interpolation. */ 3484 #define interpolate(x, x1, y1, x2, y2, n) \ 3485 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3486 3487 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3488 struct ieee80211com *ic = &sc->sc_ic; 3489 struct iwn_ucode_info *uc = &sc->ucode_info; 3490 struct ieee80211_channel *ch; 3491 struct iwn4965_cmd_txpower cmd; 3492 struct iwn4965_eeprom_chan_samples *chans; 3493 const uint8_t *rf_gain, *dsp_gain; 3494 int32_t vdiff, tdiff; 3495 int i, c, grp, maxpwr; 3496 uint8_t chan; 3497 3498 /* Retrieve current channel from last RXON. */ 3499 chan = sc->rxon.chan; 3500 DPRINTF(("setting TX power for channel %d\n", chan)); 3501 ch = &ic->ic_channels[chan]; 3502 3503 memset(&cmd, 0, sizeof cmd); 3504 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3505 cmd.chan = chan; 3506 3507 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3508 maxpwr = sc->maxpwr5GHz; 3509 rf_gain = iwn4965_rf_gain_5ghz; 3510 dsp_gain = iwn4965_dsp_gain_5ghz; 3511 } else { 3512 maxpwr = sc->maxpwr2GHz; 3513 rf_gain = iwn4965_rf_gain_2ghz; 3514 dsp_gain = iwn4965_dsp_gain_2ghz; 3515 } 3516 3517 /* Compute voltage compensation. */ 3518 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3519 if (vdiff > 0) 3520 vdiff *= 2; 3521 if (abs(vdiff) > 2) 3522 vdiff = 0; 3523 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3524 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3525 3526 /* Get channel attenuation group. */ 3527 if (chan <= 20) /* 1-20 */ 3528 grp = 4; 3529 else if (chan <= 43) /* 34-43 */ 3530 grp = 0; 3531 else if (chan <= 70) /* 44-70 */ 3532 grp = 1; 3533 else if (chan <= 124) /* 71-124 */ 3534 grp = 2; 3535 else /* 125-200 */ 3536 grp = 3; 3537 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3538 3539 /* Get channel sub-band. */ 3540 for (i = 0; i < IWN_NBANDS; i++) 3541 if (sc->bands[i].lo != 0 && 3542 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3543 break; 3544 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3545 return EINVAL; 3546 chans = sc->bands[i].chans; 3547 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3548 3549 for (c = 0; c < 2; c++) { 3550 uint8_t power, gain, temp; 3551 int maxchpwr, pwr, ridx, idx; 3552 3553 power = interpolate(chan, 3554 chans[0].num, chans[0].samples[c][1].power, 3555 chans[1].num, chans[1].samples[c][1].power, 1); 3556 gain = interpolate(chan, 3557 chans[0].num, chans[0].samples[c][1].gain, 3558 chans[1].num, chans[1].samples[c][1].gain, 1); 3559 temp = interpolate(chan, 3560 chans[0].num, chans[0].samples[c][1].temp, 3561 chans[1].num, chans[1].samples[c][1].temp, 1); 3562 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3563 c, power, gain, temp)); 3564 3565 /* Compute temperature compensation. */ 3566 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3567 DPRINTF(("temperature compensation=%d (current=%d, " 3568 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3569 3570 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3571 /* Convert dBm to half-dBm. */ 3572 maxchpwr = sc->maxpwr[chan] * 2; 3573 if ((ridx / 8) & 1) 3574 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3575 3576 pwr = maxpwr; 3577 3578 /* Adjust TX power based on rate. */ 3579 if ((ridx % 8) == 5) 3580 pwr -= 15; /* OFDM48: -7.5dB */ 3581 else if ((ridx % 8) == 6) 3582 pwr -= 17; /* OFDM54: -8.5dB */ 3583 else if ((ridx % 8) == 7) 3584 pwr -= 20; /* OFDM60: -10dB */ 3585 else 3586 pwr -= 10; /* Others: -5dB */ 3587 3588 /* Do not exceed channel max TX power. */ 3589 if (pwr > maxchpwr) 3590 pwr = maxchpwr; 3591 3592 idx = gain - (pwr - power) - tdiff - vdiff; 3593 if ((ridx / 8) & 1) /* MIMO */ 3594 idx += (int32_t)le32toh(uc->atten[grp][c]); 3595 3596 if (cmd.band == 0) 3597 idx += 9; /* 5GHz */ 3598 if (ridx == IWN_RIDX_MAX) 3599 idx += 5; /* CCK */ 3600 3601 /* Make sure idx stays in a valid range. */ 3602 if (idx < 0) 3603 idx = 0; 3604 else if (idx > IWN4965_MAX_PWR_INDEX) 3605 idx = IWN4965_MAX_PWR_INDEX; 3606 3607 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3608 c, ridx, idx)); 3609 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3610 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3611 } 3612 } 3613 3614 DPRINTF(("setting TX power for chan %d\n", chan)); 3615 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3616 3617 #undef interpolate 3618 #undef fdivround 3619 } 3620 3621 static int 3622 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3623 { 3624 struct iwn5000_cmd_txpower cmd; 3625 3626 /* 3627 * TX power calibration is handled automatically by the firmware 3628 * for 5000 Series. 3629 */ 3630 memset(&cmd, 0, sizeof cmd); 3631 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3632 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3633 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3634 DPRINTF(("setting TX power\n")); 3635 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3636 } 3637 3638 /* 3639 * Retrieve the maximum RSSI (in dBm) among receivers. 3640 */ 3641 static int 3642 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3643 { 3644 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3645 uint8_t mask, agc; 3646 int rssi; 3647 3648 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3649 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3650 3651 rssi = 0; 3652 if (mask & IWN_ANT_A) 3653 rssi = MAX(rssi, phy->rssi[0]); 3654 if (mask & IWN_ANT_B) 3655 rssi = MAX(rssi, phy->rssi[2]); 3656 if (mask & IWN_ANT_C) 3657 rssi = MAX(rssi, phy->rssi[4]); 3658 3659 return rssi - agc - IWN_RSSI_TO_DBM; 3660 } 3661 3662 static int 3663 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3664 { 3665 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3666 uint8_t agc; 3667 int rssi; 3668 3669 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3670 3671 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3672 le16toh(phy->rssi[1]) & 0xff); 3673 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3674 3675 return rssi - agc - IWN_RSSI_TO_DBM; 3676 } 3677 3678 /* 3679 * Retrieve the average noise (in dBm) among receivers. 3680 */ 3681 static int 3682 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3683 { 3684 int i, total, nbant, noise; 3685 3686 total = nbant = 0; 3687 for (i = 0; i < 3; i++) { 3688 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3689 continue; 3690 total += noise; 3691 nbant++; 3692 } 3693 /* There should be at least one antenna but check anyway. */ 3694 return (nbant == 0) ? -127 : (total / nbant) - 107; 3695 } 3696 3697 /* 3698 * Compute temperature (in degC) from last received statistics. 3699 */ 3700 static int 3701 iwn4965_get_temperature(struct iwn_softc *sc) 3702 { 3703 struct iwn_ucode_info *uc = &sc->ucode_info; 3704 int32_t r1, r2, r3, r4, temp; 3705 3706 r1 = le32toh(uc->temp[0].chan20MHz); 3707 r2 = le32toh(uc->temp[1].chan20MHz); 3708 r3 = le32toh(uc->temp[2].chan20MHz); 3709 r4 = le32toh(sc->rawtemp); 3710 3711 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 3712 return 0; 3713 3714 /* Sign-extend 23-bit R4 value to 32-bit. */ 3715 r4 = (r4 << 8) >> 8; 3716 /* Compute temperature in Kelvin. */ 3717 temp = (259 * (r4 - r2)) / (r3 - r1); 3718 temp = (temp * 97) / 100 + 8; 3719 3720 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3721 return IWN_KTOC(temp); 3722 } 3723 3724 static int 3725 iwn5000_get_temperature(struct iwn_softc *sc) 3726 { 3727 int32_t temp; 3728 3729 /* 3730 * Temperature is not used by the driver for 5000 Series because 3731 * TX power calibration is handled by firmware. We export it to 3732 * users through the sensor framework though. 3733 */ 3734 temp = le32toh(sc->rawtemp); 3735 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3736 temp = (temp / -5) + sc->temp_off; 3737 temp = IWN_KTOC(temp); 3738 } 3739 return temp; 3740 } 3741 3742 /* 3743 * Initialize sensitivity calibration state machine. 3744 */ 3745 static int 3746 iwn_init_sensitivity(struct iwn_softc *sc) 3747 { 3748 const struct iwn_hal *hal = sc->sc_hal; 3749 struct iwn_calib_state *calib = &sc->calib; 3750 uint32_t flags; 3751 int error; 3752 3753 /* Reset calibration state machine. */ 3754 memset(calib, 0, sizeof (*calib)); 3755 calib->state = IWN_CALIB_STATE_INIT; 3756 calib->cck_state = IWN_CCK_STATE_HIFA; 3757 /* Set initial correlation values. */ 3758 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3759 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3760 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3761 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3762 calib->cck_x4 = 125; 3763 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3764 calib->energy_cck = sc->limits->energy_cck; 3765 3766 /* Write initial sensitivity. */ 3767 if ((error = iwn_send_sensitivity(sc)) != 0) 3768 return error; 3769 3770 /* Write initial gains. */ 3771 if ((error = hal->init_gains(sc)) != 0) 3772 return error; 3773 3774 /* Request statistics at each beacon interval. */ 3775 flags = 0; 3776 DPRINTF(("sending request for statistics\n")); 3777 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3778 } 3779 3780 /* 3781 * Collect noise and RSSI statistics for the first 20 beacons received 3782 * after association and use them to determine connected antennas and 3783 * to set differential gains. 3784 */ 3785 static void 3786 iwn_collect_noise(struct iwn_softc *sc, 3787 const struct iwn_rx_general_stats *stats) 3788 { 3789 const struct iwn_hal *hal = sc->sc_hal; 3790 struct iwn_calib_state *calib = &sc->calib; 3791 uint32_t val; 3792 int i; 3793 3794 /* Accumulate RSSI and noise for all 3 antennas. */ 3795 for (i = 0; i < 3; i++) { 3796 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3797 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3798 } 3799 /* NB: We update differential gains only once after 20 beacons. */ 3800 if (++calib->nbeacons < 20) 3801 return; 3802 3803 /* Determine highest average RSSI. */ 3804 val = MAX(calib->rssi[0], calib->rssi[1]); 3805 val = MAX(calib->rssi[2], val); 3806 3807 /* Determine which antennas are connected. */ 3808 sc->chainmask = sc->rxchainmask; 3809 for (i = 0; i < 3; i++) 3810 if (val - calib->rssi[i] > 15 * 20) 3811 sc->chainmask &= ~(1 << i); 3812 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3813 sc->rxchainmask, sc->chainmask)); 3814 3815 /* If none of the TX antennas are connected, keep at least one. */ 3816 if ((sc->chainmask & sc->txchainmask) == 0) 3817 sc->chainmask |= IWN_LSB(sc->txchainmask); 3818 3819 (void)hal->set_gains(sc); 3820 calib->state = IWN_CALIB_STATE_RUN; 3821 3822 #ifdef notyet 3823 /* XXX Disable RX chains with no antennas connected. */ 3824 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3825 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 3826 #endif 3827 3828 /* Enable power-saving mode if requested by user. */ 3829 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3830 (void)iwn_set_pslevel(sc, 0, 3, 1); 3831 } 3832 3833 static int 3834 iwn4965_init_gains(struct iwn_softc *sc) 3835 { 3836 struct iwn_phy_calib_gain cmd; 3837 3838 memset(&cmd, 0, sizeof cmd); 3839 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3840 /* Differential gains initially set to 0 for all 3 antennas. */ 3841 DPRINTF(("setting initial differential gains\n")); 3842 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3843 } 3844 3845 static int 3846 iwn5000_init_gains(struct iwn_softc *sc) 3847 { 3848 struct iwn_phy_calib cmd; 3849 3850 memset(&cmd, 0, sizeof cmd); 3851 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3852 cmd.ngroups = 1; 3853 cmd.isvalid = 1; 3854 DPRINTF(("setting initial differential gains\n")); 3855 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3856 } 3857 3858 static int 3859 iwn4965_set_gains(struct iwn_softc *sc) 3860 { 3861 struct iwn_calib_state *calib = &sc->calib; 3862 struct iwn_phy_calib_gain cmd; 3863 int i, delta, noise; 3864 3865 /* Get minimal noise among connected antennas. */ 3866 noise = INT_MAX; /* NB: There's at least one antenna. */ 3867 for (i = 0; i < 3; i++) 3868 if (sc->chainmask & (1 << i)) 3869 noise = MIN(calib->noise[i], noise); 3870 3871 memset(&cmd, 0, sizeof cmd); 3872 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3873 /* Set differential gains for connected antennas. */ 3874 for (i = 0; i < 3; i++) { 3875 if (sc->chainmask & (1 << i)) { 3876 /* Compute attenuation (in unit of 1.5dB). */ 3877 delta = (noise - (int32_t)calib->noise[i]) / 30; 3878 /* NB: delta <= 0 */ 3879 /* Limit to [-4.5dB,0]. */ 3880 cmd.gain[i] = MIN(abs(delta), 3); 3881 if (delta < 0) 3882 cmd.gain[i] |= 1 << 2; /* sign bit */ 3883 } 3884 } 3885 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3886 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3887 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3888 } 3889 3890 static int 3891 iwn5000_set_gains(struct iwn_softc *sc) 3892 { 3893 struct iwn_calib_state *calib = &sc->calib; 3894 struct iwn_phy_calib_gain cmd; 3895 int i, ant, div, delta; 3896 3897 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3898 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3899 3900 memset(&cmd, 0, sizeof cmd); 3901 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3902 cmd.ngroups = 1; 3903 cmd.isvalid = 1; 3904 /* Get first available RX antenna as referential. */ 3905 ant = IWN_LSB(sc->rxchainmask); 3906 /* Set differential gains for other antennas. */ 3907 for (i = ant + 1; i < 3; i++) { 3908 if (sc->chainmask & (1 << i)) { 3909 /* The delta is relative to antenna "ant". */ 3910 delta = ((int32_t)calib->noise[ant] - 3911 (int32_t)calib->noise[i]) / div; 3912 /* Limit to [-4.5dB,+4.5dB]. */ 3913 cmd.gain[i - 1] = MIN(abs(delta), 3); 3914 if (delta < 0) 3915 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3916 } 3917 } 3918 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3919 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3920 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3921 } 3922 3923 /* 3924 * Tune RF RX sensitivity based on the number of false alarms detected 3925 * during the last beacon period. 3926 */ 3927 static void 3928 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3929 { 3930 #define inc(val, inc, max) \ 3931 if ((val) < (max)) { \ 3932 if ((val) < (max) - (inc)) \ 3933 (val) += (inc); \ 3934 else \ 3935 (val) = (max); \ 3936 needs_update = 1; \ 3937 } 3938 #define dec(val, dec, min) \ 3939 if ((val) > (min)) { \ 3940 if ((val) > (min) + (dec)) \ 3941 (val) -= (dec); \ 3942 else \ 3943 (val) = (min); \ 3944 needs_update = 1; \ 3945 } 3946 3947 const struct iwn_sensitivity_limits *limits = sc->limits; 3948 struct iwn_calib_state *calib = &sc->calib; 3949 uint32_t val, rxena, fa; 3950 uint32_t energy[3], energy_min; 3951 uint8_t noise[3], noise_ref; 3952 int i, needs_update = 0; 3953 3954 /* Check that we've been enabled long enough. */ 3955 if ((rxena = le32toh(stats->general.load)) == 0) 3956 return; 3957 3958 /* Compute number of false alarms since last call for OFDM. */ 3959 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3960 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3961 fa *= 200 * 1024; /* 200TU */ 3962 3963 /* Save counters values for next call. */ 3964 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3965 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3966 3967 if (fa > 50 * rxena) { 3968 /* High false alarm count, decrease sensitivity. */ 3969 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3970 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3971 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3972 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3973 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3974 3975 } else if (fa < 5 * rxena) { 3976 /* Low false alarm count, increase sensitivity. */ 3977 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3978 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3979 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3980 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3981 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3982 } 3983 3984 /* Compute maximum noise among 3 receivers. */ 3985 for (i = 0; i < 3; i++) 3986 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 3987 val = MAX(noise[0], noise[1]); 3988 val = MAX(noise[2], val); 3989 /* Insert it into our samples table. */ 3990 calib->noise_samples[calib->cur_noise_sample] = val; 3991 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3992 3993 /* Compute maximum noise among last 20 samples. */ 3994 noise_ref = calib->noise_samples[0]; 3995 for (i = 1; i < 20; i++) 3996 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 3997 3998 /* Compute maximum energy among 3 receivers. */ 3999 for (i = 0; i < 3; i++) 4000 energy[i] = le32toh(stats->general.energy[i]); 4001 val = MIN(energy[0], energy[1]); 4002 val = MIN(energy[2], val); 4003 /* Insert it into our samples table. */ 4004 calib->energy_samples[calib->cur_energy_sample] = val; 4005 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4006 4007 /* Compute minimum energy among last 10 samples. */ 4008 energy_min = calib->energy_samples[0]; 4009 for (i = 1; i < 10; i++) 4010 energy_min = MAX(energy_min, calib->energy_samples[i]); 4011 energy_min += 6; 4012 4013 /* Compute number of false alarms since last call for CCK. */ 4014 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4015 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4016 fa *= 200 * 1024; /* 200TU */ 4017 4018 /* Save counters values for next call. */ 4019 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4020 calib->fa_cck = le32toh(stats->cck.fa); 4021 4022 if (fa > 50 * rxena) { 4023 /* High false alarm count, decrease sensitivity. */ 4024 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4025 calib->cck_state = IWN_CCK_STATE_HIFA; 4026 calib->low_fa = 0; 4027 4028 if (calib->cck_x4 > 160) { 4029 calib->noise_ref = noise_ref; 4030 if (calib->energy_cck > 2) 4031 dec(calib->energy_cck, 2, energy_min); 4032 } 4033 if (calib->cck_x4 < 160) { 4034 calib->cck_x4 = 161; 4035 needs_update = 1; 4036 } else 4037 inc(calib->cck_x4, 3, limits->max_cck_x4); 4038 4039 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4040 4041 } else if (fa < 5 * rxena) { 4042 /* Low false alarm count, increase sensitivity. */ 4043 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4044 calib->cck_state = IWN_CCK_STATE_LOFA; 4045 calib->low_fa++; 4046 4047 if (calib->cck_state != IWN_CCK_STATE_INIT && 4048 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4049 calib->low_fa > 100)) { 4050 inc(calib->energy_cck, 2, limits->min_energy_cck); 4051 dec(calib->cck_x4, 3, limits->min_cck_x4); 4052 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4053 } 4054 } else { 4055 /* Not worth to increase or decrease sensitivity. */ 4056 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4057 calib->low_fa = 0; 4058 calib->noise_ref = noise_ref; 4059 4060 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4061 /* Previous interval had many false alarms. */ 4062 dec(calib->energy_cck, 8, energy_min); 4063 } 4064 calib->cck_state = IWN_CCK_STATE_INIT; 4065 } 4066 4067 if (needs_update) 4068 (void)iwn_send_sensitivity(sc); 4069 #undef dec 4070 #undef inc 4071 } 4072 4073 static int 4074 iwn_send_sensitivity(struct iwn_softc *sc) 4075 { 4076 struct iwn_calib_state *calib = &sc->calib; 4077 struct iwn_sensitivity_cmd cmd; 4078 4079 memset(&cmd, 0, sizeof cmd); 4080 cmd.which = IWN_SENSITIVITY_WORKTBL; 4081 /* OFDM modulation. */ 4082 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4083 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4084 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4085 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4086 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4087 cmd.energy_ofdm_th = htole16(62); 4088 /* CCK modulation. */ 4089 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4090 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4091 cmd.energy_cck = htole16(calib->energy_cck); 4092 /* Barker modulation: use default values. */ 4093 cmd.corr_barker = htole16(190); 4094 cmd.corr_barker_mrc = htole16(390); 4095 4096 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4097 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4098 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4099 calib->energy_cck)); 4100 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4101 } 4102 4103 /* 4104 * Set STA mode power saving level (between 0 and 5). 4105 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4106 */ 4107 static int 4108 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4109 { 4110 struct iwn_pmgt_cmd cmd; 4111 const struct iwn_pmgt *pmgt; 4112 uint32_t maxp, skip_dtim; 4113 pcireg_t reg; 4114 int i; 4115 4116 /* Select which PS parameters to use. */ 4117 if (dtim <= 2) 4118 pmgt = &iwn_pmgt[0][level]; 4119 else if (dtim <= 10) 4120 pmgt = &iwn_pmgt[1][level]; 4121 else 4122 pmgt = &iwn_pmgt[2][level]; 4123 4124 memset(&cmd, 0, sizeof cmd); 4125 if (level != 0) /* not CAM */ 4126 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4127 if (level == 5) 4128 cmd.flags |= htole16(IWN_PS_FAST_PD); 4129 /* Retrieve PCIe Active State Power Management (ASPM). */ 4130 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4131 sc->sc_cap_off + PCI_PCIE_LCSR); 4132 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4133 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4134 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4135 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4136 4137 if (dtim == 0) { 4138 dtim = 1; 4139 skip_dtim = 0; 4140 } else 4141 skip_dtim = pmgt->skip_dtim; 4142 if (skip_dtim != 0) { 4143 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4144 maxp = pmgt->intval[4]; 4145 if (maxp == (uint32_t)-1) 4146 maxp = dtim * (skip_dtim + 1); 4147 else if (maxp > dtim) 4148 maxp = (maxp / dtim) * dtim; 4149 } else 4150 maxp = dtim; 4151 for (i = 0; i < 5; i++) 4152 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4153 4154 DPRINTF(("setting power saving level to %d\n", level)); 4155 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4156 } 4157 4158 static int 4159 iwn_config(struct iwn_softc *sc) 4160 { 4161 const struct iwn_hal *hal = sc->sc_hal; 4162 struct ieee80211com *ic = &sc->sc_ic; 4163 struct ifnet *ifp = ic->ic_ifp; 4164 struct iwn_bluetooth bluetooth; 4165 uint32_t txmask; 4166 uint16_t rxchain; 4167 int error; 4168 4169 /* Configure valid TX chains for 5000 Series. */ 4170 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4171 txmask = htole32(sc->txchainmask); 4172 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4173 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4174 sizeof txmask, 0); 4175 if (error != 0) { 4176 aprint_error_dev(sc->sc_dev, 4177 "could not configure valid TX chains\n"); 4178 return error; 4179 } 4180 } 4181 4182 /* Configure bluetooth coexistence. */ 4183 memset(&bluetooth, 0, sizeof bluetooth); 4184 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4185 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4186 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4187 DPRINTF(("configuring bluetooth coexistence\n")); 4188 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4189 if (error != 0) { 4190 aprint_error_dev(sc->sc_dev, 4191 "could not configure bluetooth coexistence\n"); 4192 return error; 4193 } 4194 4195 /* Set mode, channel, RX filter and enable RX. */ 4196 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4197 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4198 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4199 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4200 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4201 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4202 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4203 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4204 switch (ic->ic_opmode) { 4205 case IEEE80211_M_STA: 4206 sc->rxon.mode = IWN_MODE_STA; 4207 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4208 break; 4209 case IEEE80211_M_MONITOR: 4210 sc->rxon.mode = IWN_MODE_MONITOR; 4211 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4212 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4213 break; 4214 default: 4215 /* Should not get there. */ 4216 break; 4217 } 4218 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4219 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4220 sc->rxon.ht_single_mask = 0xff; 4221 sc->rxon.ht_dual_mask = 0xff; 4222 sc->rxon.ht_triple_mask = 0xff; 4223 rxchain = 4224 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4225 IWN_RXCHAIN_MIMO_COUNT(2) | 4226 IWN_RXCHAIN_IDLE_COUNT(2); 4227 sc->rxon.rxchain = htole16(rxchain); 4228 DPRINTF(("setting configuration\n")); 4229 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4230 if (error != 0) { 4231 aprint_error_dev(sc->sc_dev, 4232 "RXON command failed\n"); 4233 return error; 4234 } 4235 4236 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4237 aprint_error_dev(sc->sc_dev, 4238 "could not add broadcast node\n"); 4239 return error; 4240 } 4241 4242 /* Configuration has changed, set TX power accordingly. */ 4243 if ((error = hal->set_txpower(sc, 0)) != 0) { 4244 aprint_error_dev(sc->sc_dev, 4245 "could not set TX power\n"); 4246 return error; 4247 } 4248 4249 if ((error = iwn_set_critical_temp(sc)) != 0) { 4250 aprint_error_dev(sc->sc_dev, 4251 "could not set critical temperature\n"); 4252 return error; 4253 } 4254 4255 /* Set power saving level to CAM during initialization. */ 4256 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4257 aprint_error_dev(sc->sc_dev, 4258 "could not set power saving level\n"); 4259 return error; 4260 } 4261 return 0; 4262 } 4263 4264 static int 4265 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4266 { 4267 struct ieee80211com *ic = &sc->sc_ic; 4268 struct iwn_scan_hdr *hdr; 4269 struct iwn_cmd_data *tx; 4270 struct iwn_scan_essid *essid; 4271 struct iwn_scan_chan *chan; 4272 struct ieee80211_frame *wh; 4273 struct ieee80211_rateset *rs; 4274 struct ieee80211_channel *c; 4275 uint8_t *buf, *frm; 4276 uint16_t rxchain; 4277 uint8_t txant; 4278 int buflen, error; 4279 4280 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4281 if (buf == NULL) { 4282 aprint_error_dev(sc->sc_dev, 4283 "could not allocate buffer for scan command\n"); 4284 return ENOMEM; 4285 } 4286 hdr = (struct iwn_scan_hdr *)buf; 4287 /* 4288 * Move to the next channel if no frames are received within 10ms 4289 * after sending the probe request. 4290 */ 4291 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4292 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4293 4294 /* Select antennas for scanning. */ 4295 rxchain = 4296 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4297 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4298 IWN_RXCHAIN_DRIVER_FORCE; 4299 if ((flags & IEEE80211_CHAN_5GHZ) && 4300 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4301 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4302 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4303 } else /* Use all available RX antennas. */ 4304 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4305 hdr->rxchain = htole16(rxchain); 4306 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4307 4308 tx = (struct iwn_cmd_data *)(hdr + 1); 4309 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4310 tx->id = sc->sc_hal->broadcast_id; 4311 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4312 4313 if (flags & IEEE80211_CHAN_5GHZ) { 4314 hdr->crc_threshold = htole16(1); 4315 /* Send probe requests at 6Mbps. */ 4316 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4317 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4318 } else { 4319 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4320 /* Send probe requests at 1Mbps. */ 4321 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4322 tx->rflags = IWN_RFLAG_CCK; 4323 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4324 } 4325 /* Use the first valid TX antenna. */ 4326 txant = IWN_LSB(sc->txchainmask); 4327 tx->rflags |= IWN_RFLAG_ANT(txant); 4328 4329 essid = (struct iwn_scan_essid *)(tx + 1); 4330 if (ic->ic_des_esslen != 0) { 4331 essid[0].id = IEEE80211_ELEMID_SSID; 4332 essid[0].len = ic->ic_des_esslen; 4333 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4334 } 4335 /* 4336 * Build a probe request frame. Most of the following code is a 4337 * copy & paste of what is done in net80211. 4338 */ 4339 wh = (struct ieee80211_frame *)(essid + 20); 4340 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4341 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4342 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4343 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4344 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4345 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4346 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4347 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4348 4349 frm = (uint8_t *)(wh + 1); 4350 frm = ieee80211_add_ssid(frm, NULL, 0); 4351 frm = ieee80211_add_rates(frm, rs); 4352 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4353 frm = ieee80211_add_xrates(frm, rs); 4354 4355 /* Set length of probe request. */ 4356 tx->len = htole16(frm - (uint8_t *)wh); 4357 4358 chan = (struct iwn_scan_chan *)frm; 4359 for (c = &ic->ic_channels[1]; 4360 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4361 if ((c->ic_flags & flags) != flags) 4362 continue; 4363 4364 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4365 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4366 chan->flags = 0; 4367 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4368 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4369 if (ic->ic_des_esslen != 0) 4370 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4371 chan->dsp_gain = 0x6e; 4372 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4373 chan->rf_gain = 0x3b; 4374 chan->active = htole16(24); 4375 chan->passive = htole16(110); 4376 } else { 4377 chan->rf_gain = 0x28; 4378 chan->active = htole16(36); 4379 chan->passive = htole16(120); 4380 } 4381 hdr->nchan++; 4382 chan++; 4383 } 4384 4385 buflen = (uint8_t *)chan - buf; 4386 hdr->len = htole16(buflen); 4387 4388 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4389 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4390 free(buf, M_DEVBUF); 4391 return error; 4392 } 4393 4394 static int 4395 iwn_auth(struct iwn_softc *sc) 4396 { 4397 const struct iwn_hal *hal = sc->sc_hal; 4398 struct ieee80211com *ic = &sc->sc_ic; 4399 struct ieee80211_node *ni = ic->ic_bss; 4400 int error; 4401 4402 /* Update adapter configuration. */ 4403 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4404 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4405 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4406 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4407 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4408 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4409 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4410 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4411 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4412 switch (ic->ic_curmode) { 4413 case IEEE80211_MODE_11A: 4414 sc->rxon.cck_mask = 0; 4415 sc->rxon.ofdm_mask = 0x15; 4416 break; 4417 case IEEE80211_MODE_11B: 4418 sc->rxon.cck_mask = 0x03; 4419 sc->rxon.ofdm_mask = 0; 4420 break; 4421 default: /* Assume 802.11b/g. */ 4422 sc->rxon.cck_mask = 0x0f; 4423 sc->rxon.ofdm_mask = 0x15; 4424 } 4425 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4426 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4427 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4428 if (error != 0) { 4429 aprint_error_dev(sc->sc_dev, 4430 "RXON command failed\n"); 4431 return error; 4432 } 4433 4434 /* Configuration has changed, set TX power accordingly. */ 4435 if ((error = hal->set_txpower(sc, 1)) != 0) { 4436 aprint_error_dev(sc->sc_dev, 4437 "could not set TX power\n"); 4438 return error; 4439 } 4440 /* 4441 * Reconfiguring RXON clears the firmware nodes table so we must 4442 * add the broadcast node again. 4443 */ 4444 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4445 aprint_error_dev(sc->sc_dev, 4446 "could not add broadcast node\n"); 4447 return error; 4448 } 4449 return 0; 4450 } 4451 4452 static int 4453 iwn_run(struct iwn_softc *sc) 4454 { 4455 const struct iwn_hal *hal = sc->sc_hal; 4456 struct ieee80211com *ic = &sc->sc_ic; 4457 struct ieee80211_node *ni = ic->ic_bss; 4458 struct iwn_node_info node; 4459 int error; 4460 4461 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4462 /* Link LED blinks while monitoring. */ 4463 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4464 return 0; 4465 } 4466 if ((error = iwn_set_timing(sc, ni)) != 0) { 4467 aprint_error_dev(sc->sc_dev, 4468 "could not set timing\n"); 4469 return error; 4470 } 4471 4472 /* Update adapter configuration. */ 4473 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4474 /* Short preamble and slot time are negotiated when associating. */ 4475 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4476 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4477 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4478 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4479 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4480 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4481 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4482 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4483 if (error != 0) { 4484 aprint_error_dev(sc->sc_dev, 4485 "could not update configuration\n"); 4486 return error; 4487 } 4488 4489 /* Configuration has changed, set TX power accordingly. */ 4490 if ((error = hal->set_txpower(sc, 1)) != 0) { 4491 aprint_error_dev(sc->sc_dev, 4492 "could not set TX power\n"); 4493 return error; 4494 } 4495 4496 /* Fake a join to initialize the TX rate. */ 4497 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4498 iwn_newassoc(ni, 1); 4499 4500 /* Add BSS node. */ 4501 memset(&node, 0, sizeof node); 4502 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4503 node.id = IWN_ID_BSS; 4504 #ifdef notyet 4505 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4506 IWN_AMDPU_DENSITY(5)); /* 2us */ 4507 #endif 4508 DPRINTF(("adding BSS node\n")); 4509 error = hal->add_node(sc, &node, 1); 4510 if (error != 0) { 4511 aprint_error_dev(sc->sc_dev, 4512 "could not add BSS node\n"); 4513 return error; 4514 } 4515 DPRINTF(("setting link quality for node %d\n", node.id)); 4516 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4517 aprint_error_dev(sc->sc_dev, 4518 "could not setup link quality for node %d\n", node.id); 4519 return error; 4520 } 4521 4522 if ((error = iwn_init_sensitivity(sc)) != 0) { 4523 aprint_error_dev(sc->sc_dev, 4524 "could not set sensitivity\n"); 4525 return error; 4526 } 4527 /* Start periodic calibration timer. */ 4528 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4529 sc->calib_cnt = 0; 4530 callout_schedule(&sc->calib_to, hz/2); 4531 4532 /* Link LED always on while associated. */ 4533 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4534 return 0; 4535 } 4536 4537 #ifdef IWN_HWCRYPTO 4538 /* 4539 * We support CCMP hardware encryption/decryption of unicast frames only. 4540 * HW support for TKIP really sucks. We should let TKIP die anyway. 4541 */ 4542 static int 4543 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4544 struct ieee80211_key *k) 4545 { 4546 struct iwn_softc *sc = ic->ic_softc; 4547 const struct iwn_hal *hal = sc->sc_hal; 4548 struct iwn_node *wn = (void *)ni; 4549 struct iwn_node_info node; 4550 uint16_t kflags; 4551 4552 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4553 k->k_cipher != IEEE80211_CIPHER_CCMP) 4554 return ieee80211_set_key(ic, ni, k); 4555 4556 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4557 if (k->k_flags & IEEE80211_KEY_GROUP) 4558 kflags |= IWN_KFLAG_GROUP; 4559 4560 memset(&node, 0, sizeof node); 4561 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4562 hal->broadcast_id : wn->id; 4563 node.control = IWN_NODE_UPDATE; 4564 node.flags = IWN_FLAG_SET_KEY; 4565 node.kflags = htole16(kflags); 4566 node.kid = k->k_id; 4567 memcpy(node.key, k->k_key, k->k_len); 4568 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4569 return hal->add_node(sc, &node, 1); 4570 } 4571 4572 static void 4573 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4574 struct ieee80211_key *k) 4575 { 4576 struct iwn_softc *sc = ic->ic_softc; 4577 const struct iwn_hal *hal = sc->sc_hal; 4578 struct iwn_node *wn = (void *)ni; 4579 struct iwn_node_info node; 4580 4581 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4582 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4583 /* See comment about other ciphers above. */ 4584 ieee80211_delete_key(ic, ni, k); 4585 return; 4586 } 4587 if (ic->ic_state != IEEE80211_S_RUN) 4588 return; /* Nothing to do. */ 4589 memset(&node, 0, sizeof node); 4590 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4591 hal->broadcast_id : wn->id; 4592 node.control = IWN_NODE_UPDATE; 4593 node.flags = IWN_FLAG_SET_KEY; 4594 node.kflags = htole16(IWN_KFLAG_INVALID); 4595 node.kid = 0xff; 4596 DPRINTF(("delete keys for node %d\n", node.id)); 4597 (void)hal->add_node(sc, &node, 1); 4598 } 4599 #endif 4600 4601 /* XXX Added for NetBSD (copied from rev 1.39). */ 4602 4603 static int 4604 iwn_wme_update(struct ieee80211com *ic) 4605 { 4606 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4607 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4608 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4609 const struct wmeParams *wmep; 4610 struct iwn_edca_params cmd; 4611 int ac; 4612 4613 /* don't override default WME values if WME is not actually enabled */ 4614 if (!(ic->ic_flags & IEEE80211_F_WME)) 4615 return 0; 4616 cmd.flags = 0; 4617 for (ac = 0; ac < WME_NUM_AC; ac++) { 4618 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4619 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4620 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4621 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4622 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4623 4624 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4625 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4626 cmd.ac[ac].cwmin, 4627 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4628 } 4629 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4630 #undef IWN_USEC 4631 #undef IWN_EXP2 4632 } 4633 4634 #ifndef IEEE80211_NO_HT 4635 /* 4636 * This function is called by upper layer when an ADDBA request is received 4637 * from another STA and before the ADDBA response is sent. 4638 */ 4639 static int 4640 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4641 uint8_t tid) 4642 { 4643 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4644 struct iwn_softc *sc = ic->ic_softc; 4645 struct iwn_node *wn = (void *)ni; 4646 struct iwn_node_info node; 4647 4648 memset(&node, 0, sizeof node); 4649 node.id = wn->id; 4650 node.control = IWN_NODE_UPDATE; 4651 node.flags = IWN_FLAG_SET_ADDBA; 4652 node.addba_tid = tid; 4653 node.addba_ssn = htole16(ba->ba_winstart); 4654 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4655 ba->ba_winstart)); 4656 return sc->sc_hal->add_node(sc, &node, 1); 4657 } 4658 4659 /* 4660 * This function is called by upper layer on teardown of an HT-immediate 4661 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 4662 */ 4663 static void 4664 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4665 uint8_t tid) 4666 { 4667 struct iwn_softc *sc = ic->ic_softc; 4668 struct iwn_node *wn = (void *)ni; 4669 struct iwn_node_info node; 4670 4671 memset(&node, 0, sizeof node); 4672 node.id = wn->id; 4673 node.control = IWN_NODE_UPDATE; 4674 node.flags = IWN_FLAG_SET_DELBA; 4675 node.delba_tid = tid; 4676 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4677 (void)sc->sc_hal->add_node(sc, &node, 1); 4678 } 4679 4680 /* 4681 * This function is called by upper layer when an ADDBA response is received 4682 * from another STA. 4683 */ 4684 static int 4685 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4686 uint8_t tid) 4687 { 4688 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4689 struct iwn_softc *sc = ic->ic_softc; 4690 const struct iwn_hal *hal = sc->sc_hal; 4691 struct iwn_node *wn = (void *)ni; 4692 struct iwn_node_info node; 4693 int error; 4694 4695 /* Enable TX for the specified RA/TID. */ 4696 wn->disable_tid &= ~(1 << tid); 4697 memset(&node, 0, sizeof node); 4698 node.id = wn->id; 4699 node.control = IWN_NODE_UPDATE; 4700 node.flags = IWN_FLAG_SET_DISABLE_TID; 4701 node.disable_tid = htole16(wn->disable_tid); 4702 error = hal->add_node(sc, &node, 1); 4703 if (error != 0) 4704 return error; 4705 4706 if ((error = iwn_nic_lock(sc)) != 0) 4707 return error; 4708 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4709 iwn_nic_unlock(sc); 4710 return 0; 4711 } 4712 4713 static void 4714 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4715 uint8_t tid) 4716 { 4717 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4718 struct iwn_softc *sc = ic->ic_softc; 4719 4720 if (iwn_nic_lock(sc) != 0) 4721 return; 4722 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4723 iwn_nic_unlock(sc); 4724 } 4725 4726 static void 4727 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4728 uint8_t tid, uint16_t ssn) 4729 { 4730 struct iwn_node *wn = (void *)ni; 4731 int qid = 7 + tid; 4732 4733 /* Stop TX scheduler while we're changing its configuration. */ 4734 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4735 IWN4965_TXQ_STATUS_CHGACT); 4736 4737 /* Assign RA/TID translation to the queue. */ 4738 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4739 wn->id << 4 | tid); 4740 4741 /* Enable chain-building mode for the queue. */ 4742 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4743 4744 /* Set starting sequence number from the ADDBA request. */ 4745 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4746 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4747 4748 /* Set scheduler window size. */ 4749 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4750 IWN_SCHED_WINSZ); 4751 /* Set scheduler frame limit. */ 4752 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4753 IWN_SCHED_LIMIT << 16); 4754 4755 /* Enable interrupts for the queue. */ 4756 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4757 4758 /* Mark the queue as active. */ 4759 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4760 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4761 iwn_tid2fifo[tid] << 1); 4762 } 4763 4764 static void 4765 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4766 { 4767 int qid = 7 + tid; 4768 4769 /* Stop TX scheduler while we're changing its configuration. */ 4770 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4771 IWN4965_TXQ_STATUS_CHGACT); 4772 4773 /* Set starting sequence number from the ADDBA request. */ 4774 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4775 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4776 4777 /* Disable interrupts for the queue. */ 4778 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4779 4780 /* Mark the queue as inactive. */ 4781 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4782 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4783 } 4784 4785 static void 4786 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4787 uint8_t tid, uint16_t ssn) 4788 { 4789 struct iwn_node *wn = (void *)ni; 4790 int qid = 10 + tid; 4791 4792 /* Stop TX scheduler while we're changing its configuration. */ 4793 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4794 IWN5000_TXQ_STATUS_CHGACT); 4795 4796 /* Assign RA/TID translation to the queue. */ 4797 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4798 wn->id << 4 | tid); 4799 4800 /* Enable chain-building mode for the queue. */ 4801 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4802 4803 /* Enable aggregation for the queue. */ 4804 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4805 4806 /* Set starting sequence number from the ADDBA request. */ 4807 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4808 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4809 4810 /* Set scheduler window size and frame limit. */ 4811 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4812 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4813 4814 /* Enable interrupts for the queue. */ 4815 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4816 4817 /* Mark the queue as active. */ 4818 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4819 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4820 } 4821 4822 static void 4823 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4824 { 4825 int qid = 10 + tid; 4826 4827 /* Stop TX scheduler while we're changing its configuration. */ 4828 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4829 IWN5000_TXQ_STATUS_CHGACT); 4830 4831 /* Disable aggregation for the queue. */ 4832 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4833 4834 /* Set starting sequence number from the ADDBA request. */ 4835 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4836 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4837 4838 /* Disable interrupts for the queue. */ 4839 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4840 4841 /* Mark the queue as inactive. */ 4842 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4843 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4844 } 4845 #endif /* !IEEE80211_NO_HT */ 4846 4847 /* 4848 * Query calibration tables from the initialization firmware. We do this 4849 * only once at first boot. Called from a process context. 4850 */ 4851 static int 4852 iwn5000_query_calibration(struct iwn_softc *sc) 4853 { 4854 struct iwn5000_calib_config cmd; 4855 int error; 4856 4857 memset(&cmd, 0, sizeof cmd); 4858 cmd.ucode.once.enable = 0xffffffff; 4859 cmd.ucode.once.start = 0xffffffff; 4860 cmd.ucode.once.send = 0xffffffff; 4861 cmd.ucode.flags = 0xffffffff; 4862 DPRINTF(("sending calibration query\n")); 4863 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4864 if (error != 0) 4865 return error; 4866 4867 /* Wait at most two seconds for calibration to complete. */ 4868 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4869 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4870 return error; 4871 } 4872 4873 /* 4874 * Send calibration results to the runtime firmware. These results were 4875 * obtained on first boot from the initialization firmware. 4876 */ 4877 static int 4878 iwn5000_send_calibration(struct iwn_softc *sc) 4879 { 4880 int idx, error; 4881 4882 for (idx = 0; idx < 5; idx++) { 4883 if (sc->calibcmd[idx].buf == NULL) 4884 continue; /* No results available. */ 4885 DPRINTF(("send calibration result idx=%d len=%d\n", 4886 idx, sc->calibcmd[idx].len)); 4887 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4888 sc->calibcmd[idx].len, 0); 4889 if (error != 0) { 4890 aprint_error_dev(sc->sc_dev, 4891 "could not send calibration result\n"); 4892 return error; 4893 } 4894 } 4895 return 0; 4896 } 4897 4898 static int 4899 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4900 { 4901 struct iwn5000_wimax_coex wimax; 4902 4903 #ifdef notyet 4904 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4905 /* Enable WiMAX coexistence for combo adapters. */ 4906 wimax.flags = 4907 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4908 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4909 IWN_WIMAX_COEX_STA_TABLE_VALID | 4910 IWN_WIMAX_COEX_ENABLE; 4911 memcpy(wimax.events, iwn6050_wimax_events, 4912 sizeof iwn6050_wimax_events); 4913 } else 4914 #endif 4915 { 4916 /* Disable WiMAX coexistence. */ 4917 wimax.flags = 0; 4918 memset(wimax.events, 0, sizeof wimax.events); 4919 } 4920 DPRINTF(("Configuring WiMAX coexistence\n")); 4921 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4922 } 4923 4924 /* 4925 * This function is called after the runtime firmware notifies us of its 4926 * readiness (called in a process context.) 4927 */ 4928 static int 4929 iwn4965_post_alive(struct iwn_softc *sc) 4930 { 4931 int error, qid; 4932 4933 if ((error = iwn_nic_lock(sc)) != 0) 4934 return error; 4935 4936 /* Clear TX scheduler state in SRAM. */ 4937 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4938 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4939 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 4940 4941 /* Set physical address of TX scheduler rings (1KB aligned.) */ 4942 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4943 4944 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4945 4946 /* Disable chain mode for all our 16 queues. */ 4947 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4948 4949 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4950 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4951 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4952 4953 /* Set scheduler window size. */ 4954 iwn_mem_write(sc, sc->sched_base + 4955 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4956 /* Set scheduler frame limit. */ 4957 iwn_mem_write(sc, sc->sched_base + 4958 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4959 IWN_SCHED_LIMIT << 16); 4960 } 4961 4962 /* Enable interrupts for all our 16 queues. */ 4963 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4964 /* Identify TX FIFO rings (0-7). */ 4965 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4966 4967 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4968 for (qid = 0; qid < 7; qid++) { 4969 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4970 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4971 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4972 } 4973 iwn_nic_unlock(sc); 4974 return 0; 4975 } 4976 4977 /* 4978 * This function is called after the initialization or runtime firmware 4979 * notifies us of its readiness (called in a process context.) 4980 */ 4981 static int 4982 iwn5000_post_alive(struct iwn_softc *sc) 4983 { 4984 int error, qid; 4985 4986 /* Switch to using ICT interrupt mode. */ 4987 iwn5000_ict_reset(sc); 4988 4989 if ((error = iwn_nic_lock(sc)) != 0) 4990 return error; 4991 4992 /* Clear TX scheduler state in SRAM. */ 4993 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4994 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 4995 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 4996 4997 /* Set physical address of TX scheduler rings (1KB aligned.) */ 4998 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4999 5000 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5001 5002 /* Enable chain mode for all queues, except command queue. */ 5003 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5004 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5005 5006 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5007 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5008 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5009 5010 iwn_mem_write(sc, sc->sched_base + 5011 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5012 /* Set scheduler window size and frame limit. */ 5013 iwn_mem_write(sc, sc->sched_base + 5014 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5015 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5016 } 5017 5018 /* Enable interrupts for all our 20 queues. */ 5019 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5020 /* Identify TX FIFO rings (0-7). */ 5021 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5022 5023 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5024 for (qid = 0; qid < 7; qid++) { 5025 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5026 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5027 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5028 } 5029 iwn_nic_unlock(sc); 5030 5031 /* Configure WiMAX coexistence for combo adapters. */ 5032 error = iwn5000_send_wimax_coex(sc); 5033 if (error != 0) { 5034 aprint_error_dev(sc->sc_dev, 5035 "could not configure WiMAX coexistence\n"); 5036 return error; 5037 } 5038 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5039 struct iwn5000_phy_calib_crystal cmd; 5040 5041 /* Perform crystal calibration. */ 5042 memset(&cmd, 0, sizeof cmd); 5043 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5044 cmd.ngroups = 1; 5045 cmd.isvalid = 1; 5046 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5047 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5048 DPRINTF(("sending crystal calibration %d, %d\n", 5049 cmd.cap_pin[0], cmd.cap_pin[1])); 5050 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5051 if (error != 0) { 5052 aprint_error_dev(sc->sc_dev, 5053 "crystal calibration failed\n"); 5054 return error; 5055 } 5056 } 5057 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5058 /* Query calibration from the initialization firmware. */ 5059 if ((error = iwn5000_query_calibration(sc)) != 0) { 5060 aprint_error_dev(sc->sc_dev, 5061 "could not query calibration\n"); 5062 return error; 5063 } 5064 /* 5065 * We have the calibration results now, reboot with the 5066 * runtime firmware (call ourselves recursively!) 5067 */ 5068 iwn_hw_stop(sc); 5069 error = iwn_hw_init(sc); 5070 } else { 5071 /* Send calibration results to runtime firmware. */ 5072 error = iwn5000_send_calibration(sc); 5073 } 5074 return error; 5075 } 5076 5077 /* 5078 * The firmware boot code is small and is intended to be copied directly into 5079 * the NIC internal memory (no DMA transfer.) 5080 */ 5081 static int 5082 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5083 { 5084 int error, ntries; 5085 5086 size /= sizeof (uint32_t); 5087 5088 if ((error = iwn_nic_lock(sc)) != 0) 5089 return error; 5090 5091 /* Copy microcode image into NIC memory. */ 5092 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5093 (const uint32_t *)ucode, size); 5094 5095 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5096 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5097 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5098 5099 /* Start boot load now. */ 5100 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5101 5102 /* Wait for transfer to complete. */ 5103 for (ntries = 0; ntries < 1000; ntries++) { 5104 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5105 IWN_BSM_WR_CTRL_START)) 5106 break; 5107 DELAY(10); 5108 } 5109 if (ntries == 1000) { 5110 aprint_error_dev(sc->sc_dev, 5111 "could not load boot firmware\n"); 5112 iwn_nic_unlock(sc); 5113 return ETIMEDOUT; 5114 } 5115 5116 /* Enable boot after power up. */ 5117 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5118 5119 iwn_nic_unlock(sc); 5120 return 0; 5121 } 5122 5123 static int 5124 iwn4965_load_firmware(struct iwn_softc *sc) 5125 { 5126 struct iwn_fw_info *fw = &sc->fw; 5127 struct iwn_dma_info *dma = &sc->fw_dma; 5128 int error; 5129 5130 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5131 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5132 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5133 BUS_DMASYNC_PREWRITE); 5134 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5135 fw->init.text, fw->init.textsz); 5136 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5137 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5138 5139 /* Tell adapter where to find initialization sections. */ 5140 if ((error = iwn_nic_lock(sc)) != 0) 5141 return error; 5142 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5143 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5144 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5145 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5146 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5147 iwn_nic_unlock(sc); 5148 5149 /* Load firmware boot code. */ 5150 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5151 if (error != 0) { 5152 aprint_error_dev(sc->sc_dev, 5153 "could not load boot firmware\n"); 5154 return error; 5155 } 5156 /* Now press "execute". */ 5157 IWN_WRITE(sc, IWN_RESET, 0); 5158 5159 /* Wait at most one second for first alive notification. */ 5160 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5161 aprint_error_dev(sc->sc_dev, 5162 "timeout waiting for adapter to initialize\n"); 5163 return error; 5164 } 5165 5166 /* Retrieve current temperature for initial TX power calibration. */ 5167 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5168 sc->temp = iwn4965_get_temperature(sc); 5169 5170 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5171 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5172 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5173 BUS_DMASYNC_PREWRITE); 5174 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5175 fw->main.text, fw->main.textsz); 5176 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5177 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5178 5179 /* Tell adapter where to find runtime sections. */ 5180 if ((error = iwn_nic_lock(sc)) != 0) 5181 return error; 5182 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5183 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5184 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5185 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5186 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5187 IWN_FW_UPDATED | fw->main.textsz); 5188 iwn_nic_unlock(sc); 5189 5190 return 0; 5191 } 5192 5193 static int 5194 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5195 const uint8_t *section, int size) 5196 { 5197 struct iwn_dma_info *dma = &sc->fw_dma; 5198 int error; 5199 5200 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5201 memcpy(dma->vaddr, section, size); 5202 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5203 5204 if ((error = iwn_nic_lock(sc)) != 0) 5205 return error; 5206 5207 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5208 IWN_FH_TX_CONFIG_DMA_PAUSE); 5209 5210 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5211 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5212 IWN_LOADDR(dma->paddr)); 5213 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5214 IWN_HIADDR(dma->paddr) << 28 | size); 5215 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5216 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5217 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5218 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5219 5220 /* Kick Flow Handler to start DMA transfer. */ 5221 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5222 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5223 5224 iwn_nic_unlock(sc); 5225 5226 /* Wait at most five seconds for FH DMA transfer to complete. */ 5227 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5228 } 5229 5230 static int 5231 iwn5000_load_firmware(struct iwn_softc *sc) 5232 { 5233 struct iwn_fw_part *fw; 5234 int error; 5235 5236 /* Load the initialization firmware on first boot only. */ 5237 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5238 &sc->fw.main : &sc->fw.init; 5239 5240 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5241 fw->text, fw->textsz); 5242 if (error != 0) { 5243 aprint_error_dev(sc->sc_dev, 5244 "could not load firmware %s section\n", ".text"); 5245 return error; 5246 } 5247 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5248 fw->data, fw->datasz); 5249 if (error != 0) { 5250 aprint_error_dev(sc->sc_dev, 5251 "could not load firmware %s section\n", ".data"); 5252 return error; 5253 } 5254 5255 /* Now press "execute". */ 5256 IWN_WRITE(sc, IWN_RESET, 0); 5257 return 0; 5258 } 5259 5260 static int 5261 iwn_read_firmware(struct iwn_softc *sc) 5262 { 5263 const struct iwn_hal *hal = sc->sc_hal; 5264 struct iwn_fw_info *fw = &sc->fw; 5265 firmware_handle_t fwh; 5266 const uint32_t *ptr; 5267 uint32_t rev; 5268 size_t size; 5269 int error; 5270 5271 /* Initialize for error returns */ 5272 fw->data = NULL; 5273 fw->datasz = 0; 5274 5275 /* Open firmware image. */ 5276 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5277 aprint_error_dev(sc->sc_dev, 5278 "could not get firmware handle %s\n", sc->fwname); 5279 return error; 5280 } 5281 size = firmware_get_size(fwh); 5282 if (size < 28) { 5283 aprint_error_dev(sc->sc_dev, 5284 "truncated firmware header: %zu bytes\n", size); 5285 firmware_close(fwh); 5286 return EINVAL; 5287 } 5288 5289 /* Read the firmware. */ 5290 fw->data = firmware_malloc(size); 5291 if (fw->data == NULL) { 5292 aprint_error_dev(sc->sc_dev, 5293 "not enough memory to stock firmware %s\n", sc->fwname); 5294 firmware_close(fwh); 5295 return ENOMEM; 5296 } 5297 error = firmware_read(fwh, 0, fw->data, size); 5298 firmware_close(fwh); 5299 fw->datasz = size; 5300 if (error != 0) { 5301 aprint_error_dev(sc->sc_dev, 5302 "could not read firmware %s\n", sc->fwname); 5303 goto out; 5304 } 5305 5306 /* Process firmware header. */ 5307 ptr = (const uint32_t *)fw->data; 5308 rev = le32toh(*ptr++); 5309 /* Check firmware API version. */ 5310 if (IWN_FW_API(rev) <= 1) { 5311 aprint_error_dev(sc->sc_dev, 5312 "bad firmware, need API version >=2\n"); 5313 goto out; 5314 } 5315 if (IWN_FW_API(rev) >= 3) { 5316 /* Skip build number (version 2 header). */ 5317 size -= 4; 5318 ptr++; 5319 } 5320 fw->main.textsz = le32toh(*ptr++); 5321 fw->main.datasz = le32toh(*ptr++); 5322 fw->init.textsz = le32toh(*ptr++); 5323 fw->init.datasz = le32toh(*ptr++); 5324 fw->boot.textsz = le32toh(*ptr++); 5325 size -= 24; 5326 5327 /* Sanity-check firmware header. */ 5328 if (fw->main.textsz > hal->fw_text_maxsz || 5329 fw->main.datasz > hal->fw_data_maxsz || 5330 fw->init.textsz > hal->fw_text_maxsz || 5331 fw->init.datasz > hal->fw_data_maxsz || 5332 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5333 (fw->boot.textsz & 3) != 0) { 5334 aprint_error_dev(sc->sc_dev, 5335 "invalid firmware header\n"); 5336 goto out; 5337 } 5338 5339 /* Check that all firmware sections fit. */ 5340 if (fw->main.textsz + fw->main.datasz + fw->init.textsz + 5341 fw->init.datasz + fw->boot.textsz > size) { 5342 aprint_error_dev(sc->sc_dev, 5343 "firmware file too short: %zu bytes\n", size); 5344 goto out; 5345 } 5346 5347 /* Get pointers to firmware sections. */ 5348 fw->main.text = (const uint8_t *)ptr; 5349 fw->main.data = fw->main.text + fw->main.textsz; 5350 fw->init.text = fw->main.data + fw->main.datasz; 5351 fw->init.data = fw->init.text + fw->init.textsz; 5352 fw->boot.text = fw->init.data + fw->init.datasz; 5353 5354 return 0; 5355 out: 5356 firmware_free(fw->data, fw->datasz); 5357 fw->data = NULL; 5358 fw->datasz = 0; 5359 return error ? error : EINVAL; 5360 } 5361 5362 static int 5363 iwn_clock_wait(struct iwn_softc *sc) 5364 { 5365 int ntries; 5366 5367 /* Set "initialization complete" bit. */ 5368 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5369 5370 /* Wait for clock stabilization. */ 5371 for (ntries = 0; ntries < 2500; ntries++) { 5372 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5373 return 0; 5374 DELAY(10); 5375 } 5376 aprint_error_dev(sc->sc_dev, 5377 "timeout waiting for clock stabilization\n"); 5378 return ETIMEDOUT; 5379 } 5380 5381 static int 5382 iwn_apm_init(struct iwn_softc *sc) 5383 { 5384 pcireg_t reg; 5385 int error; 5386 5387 /* Disable L0s exit timer (NMI bug workaround.) */ 5388 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5389 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5390 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5391 5392 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5393 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5394 5395 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5396 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5397 5398 /* Retrieve PCIe Active State Power Management (ASPM). */ 5399 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5400 sc->sc_cap_off + PCI_PCIE_LCSR); 5401 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5402 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5403 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5404 else 5405 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5406 5407 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5408 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5409 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5410 5411 /* Wait for clock stabilization before accessing prph. */ 5412 if ((error = iwn_clock_wait(sc)) != 0) 5413 return error; 5414 5415 if ((error = iwn_nic_lock(sc)) != 0) 5416 return error; 5417 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5418 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5419 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5420 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5421 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5422 } else { 5423 /* Enable DMA. */ 5424 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5425 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5426 } 5427 DELAY(20); 5428 /* Disable L1-Active. */ 5429 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5430 iwn_nic_unlock(sc); 5431 5432 return 0; 5433 } 5434 5435 static void 5436 iwn_apm_stop_master(struct iwn_softc *sc) 5437 { 5438 int ntries; 5439 5440 /* Stop busmaster DMA activity. */ 5441 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5442 for (ntries = 0; ntries < 100; ntries++) { 5443 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5444 return; 5445 DELAY(10); 5446 } 5447 aprint_error_dev(sc->sc_dev, 5448 "timeout waiting for master\n"); 5449 } 5450 5451 static void 5452 iwn_apm_stop(struct iwn_softc *sc) 5453 { 5454 iwn_apm_stop_master(sc); 5455 5456 /* Reset the entire device. */ 5457 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5458 DELAY(10); 5459 /* Clear "initialization complete" bit. */ 5460 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5461 } 5462 5463 static int 5464 iwn4965_nic_config(struct iwn_softc *sc) 5465 { 5466 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5467 /* 5468 * I don't believe this to be correct but this is what the 5469 * vendor driver is doing. Probably the bits should not be 5470 * shifted in IWN_RFCFG_*. 5471 */ 5472 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5473 IWN_RFCFG_TYPE(sc->rfcfg) | 5474 IWN_RFCFG_STEP(sc->rfcfg) | 5475 IWN_RFCFG_DASH(sc->rfcfg)); 5476 } 5477 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5478 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5479 return 0; 5480 } 5481 5482 static int 5483 iwn5000_nic_config(struct iwn_softc *sc) 5484 { 5485 uint32_t tmp; 5486 int error; 5487 5488 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5489 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5490 IWN_RFCFG_TYPE(sc->rfcfg) | 5491 IWN_RFCFG_STEP(sc->rfcfg) | 5492 IWN_RFCFG_DASH(sc->rfcfg)); 5493 } 5494 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5495 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5496 5497 if ((error = iwn_nic_lock(sc)) != 0) 5498 return error; 5499 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5500 5501 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5502 /* 5503 * Select first Switching Voltage Regulator (1.32V) to 5504 * solve a stability issue related to noisy DC2DC line 5505 * in the silicon of 1000 Series. 5506 */ 5507 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5508 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5509 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5510 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5511 } 5512 iwn_nic_unlock(sc); 5513 5514 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5515 /* Use internal power amplifier only. */ 5516 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5517 } 5518 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) { 5519 /* Indicate that ROM calibration version is >=6. */ 5520 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5521 } 5522 return 0; 5523 } 5524 5525 /* 5526 * Take NIC ownership over Intel Active Management Technology (AMT). 5527 */ 5528 static int 5529 iwn_hw_prepare(struct iwn_softc *sc) 5530 { 5531 int ntries; 5532 5533 /* Check if hardware is ready. */ 5534 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5535 for (ntries = 0; ntries < 5; ntries++) { 5536 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5537 IWN_HW_IF_CONFIG_NIC_READY) 5538 return 0; 5539 DELAY(10); 5540 } 5541 5542 /* Hardware not ready, force into ready state. */ 5543 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5544 for (ntries = 0; ntries < 15000; ntries++) { 5545 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5546 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5547 break; 5548 DELAY(10); 5549 } 5550 if (ntries == 15000) 5551 return ETIMEDOUT; 5552 5553 /* Hardware should be ready now. */ 5554 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5555 for (ntries = 0; ntries < 5; ntries++) { 5556 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5557 IWN_HW_IF_CONFIG_NIC_READY) 5558 return 0; 5559 DELAY(10); 5560 } 5561 return ETIMEDOUT; 5562 } 5563 5564 static int 5565 iwn_hw_init(struct iwn_softc *sc) 5566 { 5567 const struct iwn_hal *hal = sc->sc_hal; 5568 int error, chnl, qid; 5569 5570 /* Clear pending interrupts. */ 5571 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5572 5573 if ((error = iwn_apm_init(sc)) != 0) { 5574 aprint_error_dev(sc->sc_dev, 5575 "could not power ON adapter\n"); 5576 return error; 5577 } 5578 5579 /* Select VMAIN power source. */ 5580 if ((error = iwn_nic_lock(sc)) != 0) 5581 return error; 5582 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5583 iwn_nic_unlock(sc); 5584 5585 /* Perform adapter-specific initialization. */ 5586 if ((error = hal->nic_config(sc)) != 0) 5587 return error; 5588 5589 /* Initialize RX ring. */ 5590 if ((error = iwn_nic_lock(sc)) != 0) 5591 return error; 5592 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5593 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5594 /* Set physical address of RX ring (256-byte aligned.) */ 5595 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5596 /* Set physical address of RX status (16-byte aligned.) */ 5597 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5598 /* Enable RX. */ 5599 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5600 IWN_FH_RX_CONFIG_ENA | 5601 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5602 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5603 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5604 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5605 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5606 iwn_nic_unlock(sc); 5607 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5608 5609 if ((error = iwn_nic_lock(sc)) != 0) 5610 return error; 5611 5612 /* Initialize TX scheduler. */ 5613 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5614 5615 /* Set physical address of "keep warm" page (16-byte aligned.) */ 5616 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5617 5618 /* Initialize TX rings. */ 5619 for (qid = 0; qid < hal->ntxqs; qid++) { 5620 struct iwn_tx_ring *txq = &sc->txq[qid]; 5621 5622 /* Set physical address of TX ring (256-byte aligned.) */ 5623 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5624 txq->desc_dma.paddr >> 8); 5625 } 5626 iwn_nic_unlock(sc); 5627 5628 /* Enable DMA channels. */ 5629 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5630 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5631 IWN_FH_TX_CONFIG_DMA_ENA | 5632 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5633 } 5634 5635 /* Clear "radio off" and "commands blocked" bits. */ 5636 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5637 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5638 5639 /* Clear pending interrupts. */ 5640 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5641 /* Enable interrupt coalescing. */ 5642 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5643 /* Enable interrupts. */ 5644 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5645 5646 /* _Really_ make sure "radio off" bit is cleared! */ 5647 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5648 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5649 5650 if ((error = hal->load_firmware(sc)) != 0) { 5651 aprint_error_dev(sc->sc_dev, 5652 "could not load firmware\n"); 5653 return error; 5654 } 5655 /* Wait at most one second for firmware alive notification. */ 5656 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5657 aprint_error_dev(sc->sc_dev, 5658 "timeout waiting for adapter to initialize\n"); 5659 return error; 5660 } 5661 /* Do post-firmware initialization. */ 5662 return hal->post_alive(sc); 5663 } 5664 5665 static void 5666 iwn_hw_stop(struct iwn_softc *sc) 5667 { 5668 const struct iwn_hal *hal = sc->sc_hal; 5669 int chnl, qid, ntries; 5670 uint32_t tmp; 5671 5672 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5673 5674 /* Disable interrupts. */ 5675 IWN_WRITE(sc, IWN_INT_MASK, 0); 5676 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5677 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5678 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5679 5680 /* Make sure we no longer hold the NIC lock. */ 5681 iwn_nic_unlock(sc); 5682 5683 /* Stop TX scheduler. */ 5684 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5685 5686 /* Stop all DMA channels. */ 5687 if (iwn_nic_lock(sc) == 0) { 5688 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5689 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5690 for (ntries = 0; ntries < 200; ntries++) { 5691 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 5692 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 5693 IWN_FH_TX_STATUS_IDLE(chnl)) 5694 break; 5695 DELAY(10); 5696 } 5697 } 5698 iwn_nic_unlock(sc); 5699 } 5700 5701 /* Stop RX ring. */ 5702 iwn_reset_rx_ring(sc, &sc->rxq); 5703 5704 /* Reset all TX rings. */ 5705 for (qid = 0; qid < hal->ntxqs; qid++) 5706 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5707 5708 if (iwn_nic_lock(sc) == 0) { 5709 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5710 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5711 iwn_nic_unlock(sc); 5712 } 5713 DELAY(5); 5714 /* Power OFF adapter. */ 5715 iwn_apm_stop(sc); 5716 } 5717 5718 static int 5719 iwn_init(struct ifnet *ifp) 5720 { 5721 struct iwn_softc *sc = ifp->if_softc; 5722 struct ieee80211com *ic = &sc->sc_ic; 5723 int error; 5724 5725 if ((error = iwn_hw_prepare(sc)) != 0) { 5726 aprint_error_dev(sc->sc_dev, 5727 "hardware not ready\n"); 5728 goto fail; 5729 } 5730 5731 /* Check that the radio is not disabled by hardware switch. */ 5732 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5733 aprint_error_dev(sc->sc_dev, 5734 "radio is disabled by hardware switch\n"); 5735 error = EPERM; /* :-) */ 5736 goto fail; 5737 } 5738 5739 /* Read firmware images from the filesystem. */ 5740 if ((error = iwn_read_firmware(sc)) != 0) { 5741 aprint_error_dev(sc->sc_dev, 5742 "could not read firmware\n"); 5743 goto fail; 5744 } 5745 5746 /* Initialize interrupt mask to default value. */ 5747 sc->int_mask = IWN_INT_MASK_DEF; 5748 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5749 5750 /* Initialize hardware and upload firmware. */ 5751 KASSERT(sc->fw.data != NULL && sc->fw.datasz > 0); 5752 error = iwn_hw_init(sc); 5753 firmware_free(sc->fw.data, sc->fw.datasz); 5754 sc->fw.data = NULL; 5755 sc->fw.datasz = 0; 5756 if (error != 0) { 5757 aprint_error_dev(sc->sc_dev, 5758 "could not initialize hardware\n"); 5759 goto fail; 5760 } 5761 5762 /* Configure adapter now that it is ready. */ 5763 if ((error = iwn_config(sc)) != 0) { 5764 aprint_error_dev(sc->sc_dev, 5765 "could not configure device\n"); 5766 goto fail; 5767 } 5768 5769 ifp->if_flags &= ~IFF_OACTIVE; 5770 ifp->if_flags |= IFF_RUNNING; 5771 5772 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5773 ieee80211_begin_scan(ic, 0); 5774 else 5775 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5776 5777 return 0; 5778 5779 fail: iwn_stop(ifp, 1); 5780 return error; 5781 } 5782 5783 static void 5784 iwn_stop(struct ifnet *ifp, int disable) 5785 { 5786 struct iwn_softc *sc = ifp->if_softc; 5787 struct ieee80211com *ic = &sc->sc_ic; 5788 5789 ifp->if_timer = sc->sc_tx_timer = 0; 5790 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5791 5792 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5793 5794 /* Power OFF hardware. */ 5795 iwn_hw_stop(sc); 5796 5797 #ifndef SMALL_KERNEL 5798 /* Temperature sensor is no longer valid. */ 5799 sc->sc_sensor.value_cur = 0; 5800 sc->sc_sensor.state = ENVSYS_SINVALID; 5801 #endif 5802 } 5803 5804 /* 5805 * XXX MCLGETI alternative 5806 * 5807 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5808 * as long as there are available free buffers then it uses MEXTMALLOC., 5809 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5810 * The MCLGET4K code is used for testing an alternative mbuf cache. 5811 */ 5812 5813 static struct mbuf * 5814 MCLGETIalt(struct iwn_softc *sc, int how, 5815 struct ifnet *ifp __unused, u_int size) 5816 { 5817 struct mbuf *m; 5818 #ifdef IWN_USE_RBUF 5819 struct iwn_rbuf *rbuf; 5820 #endif 5821 5822 MGETHDR(m, how, MT_DATA); 5823 if (m == NULL) 5824 return NULL; 5825 5826 #ifdef IWN_USE_RBUF 5827 if (sc->rxq.nb_free_entries > 0 && 5828 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 5829 /* Attach buffer to mbuf header. */ 5830 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 5831 m->m_flags |= M_EXT_RW; 5832 } 5833 else { 5834 MEXTMALLOC(m, size, how); 5835 if ((m->m_flags & M_EXT) == 0) { 5836 m_freem(m); 5837 return NULL; 5838 } 5839 } 5840 5841 #else 5842 #ifdef MCLGET4K 5843 if (size == 4096) 5844 MCLGET4K(m, how); 5845 else 5846 panic("size must be 4k"); 5847 #else 5848 MEXTMALLOC(m, size, how); 5849 #endif 5850 if ((m->m_flags & M_EXT) == 0) { 5851 m_freem(m); 5852 return NULL; 5853 } 5854 #endif 5855 5856 return m; 5857 } 5858 5859 #ifdef IWN_USE_RBUF 5860 static struct iwn_rbuf * 5861 iwn_alloc_rbuf(struct iwn_softc *sc) 5862 { 5863 struct iwn_rbuf *rbuf; 5864 mutex_enter(&sc->rxq.freelist_mtx); 5865 5866 rbuf = SLIST_FIRST(&sc->rxq.freelist); 5867 if (rbuf != NULL) { 5868 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 5869 sc->rxq.nb_free_entries --; 5870 } 5871 mutex_exit(&sc->rxq.freelist_mtx); 5872 return rbuf; 5873 } 5874 5875 /* 5876 * This is called automatically by the network stack when the mbuf to which 5877 * our RX buffer is attached is freed. 5878 */ 5879 static void 5880 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 5881 { 5882 struct iwn_rbuf *rbuf = arg; 5883 struct iwn_softc *sc = rbuf->sc; 5884 5885 /* Put the RX buffer back in the free list. */ 5886 mutex_enter(&sc->rxq.freelist_mtx); 5887 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 5888 mutex_exit(&sc->rxq.freelist_mtx); 5889 5890 sc->rxq.nb_free_entries ++; 5891 if (__predict_true(m != NULL)) 5892 pool_cache_put(mb_cache, m); 5893 } 5894 5895 static int 5896 iwn_alloc_rpool(struct iwn_softc *sc) 5897 { 5898 struct iwn_rx_ring *ring = &sc->rxq; 5899 struct iwn_rbuf *rbuf; 5900 int i, error; 5901 5902 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 5903 5904 /* Allocate a big chunk of DMA'able memory... */ 5905 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 5906 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 5907 if (error != 0) { 5908 aprint_error_dev(sc->sc_dev, 5909 "could not allocate RX buffers DMA memory\n"); 5910 return error; 5911 } 5912 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 5913 SLIST_INIT(&ring->freelist); 5914 for (i = 0; i < IWN_RBUF_COUNT; i++) { 5915 rbuf = &ring->rbuf[i]; 5916 5917 rbuf->sc = sc; /* Backpointer for callbacks. */ 5918 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 5919 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 5920 5921 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 5922 } 5923 ring->nb_free_entries = IWN_RBUF_COUNT; 5924 return 0; 5925 } 5926 5927 static void 5928 iwn_free_rpool(struct iwn_softc *sc) 5929 { 5930 iwn_dma_contig_free(&sc->rxq.buf_dma); 5931 } 5932 #endif 5933 5934 /* 5935 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 5936 * Copyright (c) 2001 Atsushi Onoe 5937 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 5938 * Copyright (c) 2007-2009 Damien Bergamini 5939 * All rights reserved. 5940 */ 5941 5942 /* 5943 * Add an SSID element to a frame (see 7.3.2.1). 5944 */ 5945 static u_int8_t * 5946 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 5947 { 5948 *frm++ = IEEE80211_ELEMID_SSID; 5949 *frm++ = len; 5950 memcpy(frm, ssid, len); 5951 return frm + len; 5952 } 5953 5954 /* 5955 * Add a supported rates element to a frame (see 7.3.2.2). 5956 */ 5957 static u_int8_t * 5958 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 5959 { 5960 int nrates; 5961 5962 *frm++ = IEEE80211_ELEMID_RATES; 5963 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 5964 *frm++ = nrates; 5965 memcpy(frm, rs->rs_rates, nrates); 5966 return frm + nrates; 5967 } 5968 5969 /* 5970 * Add an extended supported rates element to a frame (see 7.3.2.14). 5971 */ 5972 static u_int8_t * 5973 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 5974 { 5975 int nrates; 5976 5977 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 5978 5979 *frm++ = IEEE80211_ELEMID_XRATES; 5980 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 5981 *frm++ = nrates; 5982 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 5983 return frm + nrates; 5984 } 5985 5986 /* 5987 * XXX: Hack to set the current channel to the value advertised in beacons or 5988 * probe responses. Only used during AP detection. 5989 * XXX: Duplicated from if_iwi.c 5990 */ 5991 static void 5992 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 5993 { 5994 struct ieee80211_frame *wh; 5995 uint8_t subtype; 5996 uint8_t *frm, *efrm; 5997 5998 wh = mtod(m, struct ieee80211_frame *); 5999 6000 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6001 return; 6002 6003 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6004 6005 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6006 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6007 return; 6008 6009 frm = (uint8_t *)(wh + 1); 6010 efrm = mtod(m, uint8_t *) + m->m_len; 6011 6012 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6013 while (frm < efrm) { 6014 if (*frm == IEEE80211_ELEMID_DSPARMS) 6015 #if IEEE80211_CHAN_MAX < 255 6016 if (frm[2] <= IEEE80211_CHAN_MAX) 6017 #endif 6018 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6019 6020 frm += frm[1] + 2; 6021 } 6022 } 6023 6024
Indexes created Mon Sep 29 03:10:08 GMT 2025