if_iwn.c revision 1.46
1 /* $NetBSD: if_iwn.c,v 1.46 2010/06/18 21:10:23 christos Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.96 2010/05/13 09:25:03 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.46 2010/06/18 21:10:23 christos Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 /* XXX Avoid sensor code (correct option for NetBSD too?) */ 31 #undef SMALL_KERNEL 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/proc.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <machine/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 84 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 99 #ifdef notyet 100 /* 101 * XXX NetBSD: the 6005A replaces the two 6005, above 102 * (see OpenBSD rev 1.96). 103 */ 104 PCI_PRODUCT_INTEL_WIFI_LINK_6005A_2X2_1, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6005A_2X2_2, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_1X1_1, 107 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_1X1_2, 108 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_1, 109 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_2, 110 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_3 111 #endif 112 }; 113 114 /* 115 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 116 */ 117 static const struct ieee80211_rateset iwn_rateset_11a = 118 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 119 120 static const struct ieee80211_rateset iwn_rateset_11b = 121 { 4, { 2, 4, 11, 22 } }; 122 123 static const struct ieee80211_rateset iwn_rateset_11g = 124 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 125 126 static int iwn_match(device_t , struct cfdata *, void *); 127 static void iwn_attach(device_t , device_t , void *); 128 const struct iwn_hal *iwn_hal_attach(struct iwn_softc *, pci_product_id_t pid); 129 #ifndef SMALL_KERNEL 130 static void iwn_sensor_attach(struct iwn_softc *); 131 #endif 132 static void iwn_radiotap_attach(struct iwn_softc *); 133 static int iwn_detach(device_t , int); 134 #if 0 135 static void iwn_power(int, void *); 136 #endif 137 static bool iwn_resume(device_t, const pmf_qual_t *); 138 static int iwn_nic_lock(struct iwn_softc *); 139 static int iwn_eeprom_lock(struct iwn_softc *); 140 static int iwn_init_otprom(struct iwn_softc *); 141 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 142 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 143 void **, bus_size_t, bus_size_t); 144 static void iwn_dma_contig_free(struct iwn_dma_info *); 145 static int iwn_alloc_sched(struct iwn_softc *); 146 static void iwn_free_sched(struct iwn_softc *); 147 static int iwn_alloc_kw(struct iwn_softc *); 148 static void iwn_free_kw(struct iwn_softc *); 149 static int iwn_alloc_ict(struct iwn_softc *); 150 static void iwn_free_ict(struct iwn_softc *); 151 static int iwn_alloc_fwmem(struct iwn_softc *); 152 static void iwn_free_fwmem(struct iwn_softc *); 153 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 154 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 155 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 156 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 157 int); 158 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 159 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 160 static void iwn5000_ict_reset(struct iwn_softc *); 161 static int iwn_read_eeprom(struct iwn_softc *); 162 static void iwn4965_read_eeprom(struct iwn_softc *); 163 #ifdef IWN_DEBUG 164 static void iwn4965_print_power_group(struct iwn_softc *, int); 165 #endif 166 static void iwn5000_read_eeprom(struct iwn_softc *); 167 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 168 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 169 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 170 static void iwn_newassoc(struct ieee80211_node *, int); 171 static int iwn_media_change(struct ifnet *); 172 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 173 static void iwn_iter_func(void *, struct ieee80211_node *); 174 static void iwn_calib_timeout(void *); 175 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 176 struct iwn_rx_data *); 177 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 178 struct iwn_rx_data *); 179 #ifndef IEEE80211_NO_HT 180 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 181 struct iwn_rx_data *); 182 #endif 183 static void iwn5000_rx_calib_results(struct iwn_softc *, 184 struct iwn_rx_desc *, struct iwn_rx_data *); 185 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 186 struct iwn_rx_data *); 187 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 188 struct iwn_rx_data *); 189 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 190 struct iwn_rx_data *); 191 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 192 uint8_t); 193 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 194 static void iwn_notif_intr(struct iwn_softc *); 195 static void iwn_wakeup_intr(struct iwn_softc *); 196 static void iwn_fatal_intr(struct iwn_softc *); 197 static int iwn_intr(void *); 198 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 199 uint16_t); 200 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 201 uint16_t); 202 #ifdef notyet 203 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 204 #endif 205 static int iwn_tx(struct iwn_softc *, struct mbuf *, 206 struct ieee80211_node *, int); 207 static void iwn_start(struct ifnet *); 208 static void iwn_watchdog(struct ifnet *); 209 static int iwn_ioctl(struct ifnet *, u_long, void *); 210 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 211 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 212 int); 213 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 214 int); 215 static int iwn_set_link_quality(struct iwn_softc *, 216 struct ieee80211_node *); 217 static int iwn_add_broadcast_node(struct iwn_softc *, int); 218 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 219 static int iwn_set_critical_temp(struct iwn_softc *); 220 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 221 static void iwn4965_power_calibration(struct iwn_softc *, int); 222 static int iwn4965_set_txpower(struct iwn_softc *, int); 223 static int iwn5000_set_txpower(struct iwn_softc *, int); 224 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 225 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 226 static int iwn_get_noise(const struct iwn_rx_general_stats *); 227 static int iwn4965_get_temperature(struct iwn_softc *); 228 static int iwn5000_get_temperature(struct iwn_softc *); 229 static int iwn_init_sensitivity(struct iwn_softc *); 230 static void iwn_collect_noise(struct iwn_softc *, 231 const struct iwn_rx_general_stats *); 232 static int iwn4965_init_gains(struct iwn_softc *); 233 static int iwn5000_init_gains(struct iwn_softc *); 234 static int iwn4965_set_gains(struct iwn_softc *); 235 static int iwn5000_set_gains(struct iwn_softc *); 236 static void iwn_tune_sensitivity(struct iwn_softc *, 237 const struct iwn_rx_stats *); 238 static int iwn_send_sensitivity(struct iwn_softc *); 239 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 240 static int iwn_config(struct iwn_softc *); 241 static int iwn_scan(struct iwn_softc *, uint16_t); 242 static int iwn_auth(struct iwn_softc *); 243 static int iwn_run(struct iwn_softc *); 244 #ifdef IWN_HWCRYPTO 245 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 246 struct ieee80211_key *); 247 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 248 struct ieee80211_key *); 249 #endif 250 static int iwn_wme_update(struct ieee80211com *); 251 #ifndef IEEE80211_NO_HT 252 static int iwn_ampdu_rx_start(struct ieee80211com *, 253 struct ieee80211_node *, uint8_t); 254 static void iwn_ampdu_rx_stop(struct ieee80211com *, 255 struct ieee80211_node *, uint8_t); 256 static int iwn_ampdu_tx_start(struct ieee80211com *, 257 struct ieee80211_node *, uint8_t); 258 static void iwn_ampdu_tx_stop(struct ieee80211com *, 259 struct ieee80211_node *, uint8_t); 260 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 261 struct ieee80211_node *, uint8_t, uint16_t); 262 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 263 uint8_t, uint16_t); 264 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 265 struct ieee80211_node *, uint8_t, uint16_t); 266 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 267 uint8_t, uint16_t); 268 #endif 269 static int iwn5000_query_calibration(struct iwn_softc *); 270 static int iwn5000_send_calibration(struct iwn_softc *); 271 static int iwn5000_send_wimax_coex(struct iwn_softc *); 272 static int iwn4965_post_alive(struct iwn_softc *); 273 static int iwn5000_post_alive(struct iwn_softc *); 274 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 275 int); 276 static int iwn4965_load_firmware(struct iwn_softc *); 277 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 278 const uint8_t *, int); 279 static int iwn_read_firmware_leg(struct iwn_softc *, 280 struct iwn_fw_info *); 281 static int iwn_read_firmware_tlv(struct iwn_softc *, 282 struct iwn_fw_info *, uint16_t); 283 static int iwn5000_load_firmware(struct iwn_softc *); 284 static int iwn_read_firmware(struct iwn_softc *); 285 static int iwn_clock_wait(struct iwn_softc *); 286 static int iwn_apm_init(struct iwn_softc *); 287 static void iwn_apm_stop_master(struct iwn_softc *); 288 static void iwn_apm_stop(struct iwn_softc *); 289 static int iwn4965_nic_config(struct iwn_softc *); 290 static int iwn5000_nic_config(struct iwn_softc *); 291 static int iwn_hw_prepare(struct iwn_softc *); 292 static int iwn_hw_init(struct iwn_softc *); 293 static void iwn_hw_stop(struct iwn_softc *); 294 static int iwn_init(struct ifnet *); 295 static void iwn_stop(struct ifnet *, int); 296 297 /* XXX MCLGETI alternative */ 298 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 299 struct ifnet *, u_int); 300 #ifdef IWN_USE_RBUF 301 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 302 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 303 static int iwn_alloc_rpool(struct iwn_softc *); 304 static void iwn_free_rpool(struct iwn_softc *); 305 #endif 306 307 /* XXX needed by iwn_scan */ 308 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 309 static u_int8_t *ieee80211_add_rates(u_int8_t *, 310 const struct ieee80211_rateset *); 311 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 312 const struct ieee80211_rateset *); 313 314 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 315 316 #ifdef IWN_DEBUG 317 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 318 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 319 int iwn_debug = 0; 320 #else 321 #define DPRINTF(x) 322 #define DPRINTFN(n, x) 323 #endif 324 325 static const struct iwn_hal iwn4965_hal = { 326 iwn4965_load_firmware, 327 iwn4965_read_eeprom, 328 iwn4965_post_alive, 329 iwn4965_nic_config, 330 iwn4965_update_sched, 331 iwn4965_get_temperature, 332 iwn4965_get_rssi, 333 iwn4965_set_txpower, 334 iwn4965_init_gains, 335 iwn4965_set_gains, 336 iwn4965_add_node, 337 iwn4965_tx_done, 338 #ifndef IEEE80211_NO_HT 339 iwn4965_ampdu_tx_start, 340 iwn4965_ampdu_tx_stop, 341 #endif 342 IWN4965_NTXQUEUES, 343 IWN4965_NDMACHNLS, 344 IWN4965_ID_BROADCAST, 345 IWN4965_RXONSZ, 346 IWN4965_SCHEDSZ, 347 IWN4965_FW_TEXT_MAXSZ, 348 IWN4965_FW_DATA_MAXSZ, 349 IWN4965_FWSZ, 350 IWN4965_SCHED_TXFACT 351 }; 352 353 static const struct iwn_hal iwn5000_hal = { 354 iwn5000_load_firmware, 355 iwn5000_read_eeprom, 356 iwn5000_post_alive, 357 iwn5000_nic_config, 358 iwn5000_update_sched, 359 iwn5000_get_temperature, 360 iwn5000_get_rssi, 361 iwn5000_set_txpower, 362 iwn5000_init_gains, 363 iwn5000_set_gains, 364 iwn5000_add_node, 365 iwn5000_tx_done, 366 #ifndef IEEE80211_NO_HT 367 iwn5000_ampdu_tx_start, 368 iwn5000_ampdu_tx_stop, 369 #endif 370 IWN5000_NTXQUEUES, 371 IWN5000_NDMACHNLS, 372 IWN5000_ID_BROADCAST, 373 IWN5000_RXONSZ, 374 IWN5000_SCHEDSZ, 375 IWN5000_FW_TEXT_MAXSZ, 376 IWN5000_FW_DATA_MAXSZ, 377 IWN5000_FWSZ, 378 IWN5000_SCHED_TXFACT 379 }; 380 381 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 382 iwn_detach, NULL); 383 384 static int 385 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 386 { 387 struct pci_attach_args *pa = aux; 388 size_t i; 389 390 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 391 return 0; 392 393 for (i = 0; i < __arraycount(iwn_devices); i++) 394 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 395 return 1; 396 397 return 0; 398 } 399 400 static void 401 iwn_attach(device_t parent __unused, device_t self, void *aux) 402 { 403 struct iwn_softc *sc = device_private(self); 404 struct ieee80211com *ic = &sc->sc_ic; 405 struct ifnet *ifp = &sc->sc_ec.ec_if; 406 struct pci_attach_args *pa = aux; 407 const struct iwn_hal *hal; 408 const char *intrstr; 409 char devinfo[256]; 410 pci_intr_handle_t ih; 411 pcireg_t memtype, reg; 412 int i, error; 413 int revision; 414 415 sc->sc_dev = self; 416 sc->sc_pct = pa->pa_pc; 417 sc->sc_pcitag = pa->pa_tag; 418 sc->sc_dmat = pa->pa_dmat; 419 420 callout_init(&sc->calib_to, 0); 421 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 422 423 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 424 revision = PCI_REVISION(pa->pa_class); 425 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 426 427 /* 428 * Get the offset of the PCI Express Capability Structure in PCI 429 * Configuration Space. 430 */ 431 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 432 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 433 if (error == 0) { 434 aprint_error(": PCIe capability structure not found!\n"); 435 return; 436 } 437 438 /* Clear device-specific "PCI retry timeout" register (41h). */ 439 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 440 reg &= ~0xff00; 441 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 442 443 /* Enable bus-mastering and hardware bug workaround. */ 444 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 445 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 446 reg |= PCI_COMMAND_MASTER_ENABLE; 447 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 448 DPRINTF(("PCIe INTx Disable set\n")); 449 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 450 } 451 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 452 453 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 454 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 455 &sc->sc_sh, NULL, &sc->sc_sz); 456 if (error != 0) { 457 aprint_error(": can't map mem space\n"); 458 return; 459 } 460 461 /* Install interrupt handler. */ 462 if (pci_intr_map(pa, &ih) != 0) { 463 aprint_error(": can't map interrupt\n"); 464 return; 465 } 466 intrstr = pci_intr_string(sc->sc_pct, ih); 467 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 468 if (sc->sc_ih == NULL) { 469 aprint_error(": can't establish interrupt"); 470 if (intrstr != NULL) 471 aprint_error(" at %s", intrstr); 472 aprint_error("\n"); 473 return; 474 } 475 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 476 477 /* Attach Hardware Abstraction Layer. */ 478 hal = iwn_hal_attach(sc, PCI_PRODUCT(pa->pa_id)); 479 if (hal == NULL) 480 return; 481 482 if ((error = iwn_hw_prepare(sc)) != 0) { 483 aprint_error(": hardware not ready\n"); 484 return; 485 } 486 487 /* Read MAC address, channels, etc from EEPROM. */ 488 if ((error = iwn_read_eeprom(sc)) != 0) { 489 aprint_error(": could not read EEPROM\n"); 490 return; 491 } 492 493 /* Allocate DMA memory for firmware transfers. */ 494 if ((error = iwn_alloc_fwmem(sc)) != 0) { 495 aprint_error(": could not allocate memory for firmware\n"); 496 return; 497 } 498 499 /* Allocate "Keep Warm" page. */ 500 if ((error = iwn_alloc_kw(sc)) != 0) { 501 aprint_error(": could not allocate keep warm page\n"); 502 goto fail1; 503 } 504 505 /* Allocate ICT table for 5000 Series. */ 506 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 507 (error = iwn_alloc_ict(sc)) != 0) { 508 aprint_error(": could not allocate ICT table\n"); 509 goto fail2; 510 } 511 512 /* Allocate TX scheduler "rings". */ 513 if ((error = iwn_alloc_sched(sc)) != 0) { 514 aprint_error(": could not allocate TX scheduler rings\n"); 515 goto fail3; 516 } 517 518 #ifdef IWN_USE_RBUF 519 /* Allocate RX buffers. */ 520 if ((error = iwn_alloc_rpool(sc)) != 0) { 521 aprint_error_dev(self, "could not allocate RX buffers\n"); 522 goto fail3; 523 } 524 #endif 525 526 /* Allocate TX rings (16 on 4965AGN, 20 on 5000.) */ 527 for (i = 0; i < hal->ntxqs; i++) { 528 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 529 aprint_error(": could not allocate TX ring %d\n", i); 530 goto fail4; 531 } 532 } 533 534 /* Allocate RX ring. */ 535 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 536 aprint_error(": could not allocate RX ring\n"); 537 goto fail4; 538 } 539 540 /* Clear pending interrupts. */ 541 IWN_WRITE(sc, IWN_INT, 0xffffffff); 542 543 /* Count the number of available chains. */ 544 sc->ntxchains = 545 ((sc->txchainmask >> 2) & 1) + 546 ((sc->txchainmask >> 1) & 1) + 547 ((sc->txchainmask >> 0) & 1); 548 sc->nrxchains = 549 ((sc->rxchainmask >> 2) & 1) + 550 ((sc->rxchainmask >> 1) & 1) + 551 ((sc->rxchainmask >> 0) & 1); 552 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 553 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 554 ether_sprintf(ic->ic_myaddr)); 555 556 ic->ic_ifp = ifp; 557 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 558 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 559 ic->ic_state = IEEE80211_S_INIT; 560 561 /* Set device capabilities. */ 562 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 563 * and IEEE80211_C_PMGT too. */ 564 ic->ic_caps = 565 IEEE80211_C_IBSS | /* IBSS mode support */ 566 IEEE80211_C_WPA | /* 802.11i */ 567 IEEE80211_C_MONITOR | /* monitor mode supported */ 568 IEEE80211_C_TXPMGT | /* tx power management */ 569 IEEE80211_C_SHSLOT | /* short slot time supported */ 570 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 571 IEEE80211_C_WME; /* 802.11e */ 572 573 #ifndef IEEE80211_NO_HT 574 /* Set HT capabilities. */ 575 ic->ic_htcaps = 576 #if IWN_RBUF_SIZE == 8192 577 IEEE80211_HTCAP_AMSDU7935 | 578 #endif 579 IEEE80211_HTCAP_CBW20_40 | 580 IEEE80211_HTCAP_SGI20 | 581 IEEE80211_HTCAP_SGI40; 582 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 583 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 584 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 585 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 586 else 587 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 588 #endif /* !IEEE80211_NO_HT */ 589 590 /* Set supported legacy rates. */ 591 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 592 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 593 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 594 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 595 } 596 #ifndef IEEE80211_NO_HT 597 /* Set supported HT rates. */ 598 ic->ic_sup_mcs[0] = 0xff; 599 if (sc->nrxchains > 1) /* MCS 0-7 */ 600 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 601 if (sc->nrxchains > 2) 602 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 603 #endif 604 605 /* IBSS channel undefined for now. */ 606 ic->ic_ibss_chan = &ic->ic_channels[0]; 607 608 ifp->if_softc = sc; 609 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 610 ifp->if_init = iwn_init; 611 ifp->if_ioctl = iwn_ioctl; 612 ifp->if_start = iwn_start; 613 ifp->if_watchdog = iwn_watchdog; 614 IFQ_SET_READY(&ifp->if_snd); 615 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 616 617 if_attach(ifp); 618 ieee80211_ifattach(ic); 619 ic->ic_node_alloc = iwn_node_alloc; 620 ic->ic_newassoc = iwn_newassoc; 621 #ifdef IWN_HWCRYPTO 622 ic->ic_crypto.cs_key_set = iwn_set_key; 623 ic->ic_crypto.cs_key_delete = iwn_delete_key; 624 #endif 625 ic->ic_wme.wme_update = iwn_wme_update; 626 #ifndef IEEE80211_NO_HT 627 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 628 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 629 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 630 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 631 #endif 632 633 /* Override 802.11 state transition machine. */ 634 sc->sc_newstate = ic->ic_newstate; 635 ic->ic_newstate = iwn_newstate; 636 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 637 638 sc->amrr.amrr_min_success_threshold = 1; 639 sc->amrr.amrr_max_success_threshold = 15; 640 641 #ifndef SMALL_KERNEL 642 iwn_sensor_attach(sc); 643 #endif 644 iwn_radiotap_attach(sc); 645 646 /* 647 * XXX for NetBSD, OpenBSD timeout_set replaced by 648 * callout_init and callout_setfunc, above. 649 */ 650 651 if (pmf_device_register(self, NULL, iwn_resume)) 652 pmf_class_network_register(self, ifp); 653 else 654 aprint_error_dev(self, "couldn't establish power handler\n"); 655 656 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 657 ieee80211_announce(ic); 658 659 return; 660 661 /* Free allocated memory if something failed during attachment. */ 662 fail4: while (--i >= 0) 663 iwn_free_tx_ring(sc, &sc->txq[i]); 664 #ifdef IWN_USE_RBUF 665 iwn_free_rpool(sc); 666 #endif 667 iwn_free_sched(sc); 668 fail3: if (sc->ict != NULL) 669 iwn_free_ict(sc); 670 fail2: iwn_free_kw(sc); 671 fail1: iwn_free_fwmem(sc); 672 } 673 674 const struct iwn_hal * 675 iwn_hal_attach(struct iwn_softc *sc, pci_product_id_t pid) 676 { 677 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 678 679 switch (sc->hw_type) { 680 case IWN_HW_REV_TYPE_4965: 681 sc->sc_hal = &iwn4965_hal; 682 sc->limits = &iwn4965_sensitivity_limits; 683 sc->fwname = "iwlwifi-4965-2.ucode"; 684 sc->txchainmask = IWN_ANT_AB; 685 sc->rxchainmask = IWN_ANT_ABC; 686 break; 687 case IWN_HW_REV_TYPE_5100: 688 sc->sc_hal = &iwn5000_hal; 689 sc->limits = &iwn5000_sensitivity_limits; 690 sc->fwname = "iwlwifi-5000-2.ucode"; 691 sc->txchainmask = IWN_ANT_B; 692 sc->rxchainmask = IWN_ANT_AB; 693 break; 694 case IWN_HW_REV_TYPE_5150: 695 sc->sc_hal = &iwn5000_hal; 696 sc->limits = &iwn5150_sensitivity_limits; 697 sc->fwname = "iwlwifi-5150-2.ucode"; 698 sc->txchainmask = IWN_ANT_A; 699 sc->rxchainmask = IWN_ANT_AB; 700 break; 701 case IWN_HW_REV_TYPE_5300: 702 case IWN_HW_REV_TYPE_5350: 703 sc->sc_hal = &iwn5000_hal; 704 sc->limits = &iwn5000_sensitivity_limits; 705 sc->fwname = "iwlwifi-5000-2.ucode"; 706 sc->txchainmask = IWN_ANT_ABC; 707 sc->rxchainmask = IWN_ANT_ABC; 708 break; 709 case IWN_HW_REV_TYPE_1000: 710 sc->sc_hal = &iwn5000_hal; 711 sc->limits = &iwn1000_sensitivity_limits; 712 sc->fwname = "iwlwifi-1000-3.ucode"; 713 sc->txchainmask = IWN_ANT_A; 714 sc->rxchainmask = IWN_ANT_AB; 715 break; 716 case IWN_HW_REV_TYPE_6000: 717 sc->sc_hal = &iwn5000_hal; 718 sc->limits = &iwn6000_sensitivity_limits; 719 sc->fwname = "iwlwifi-6000-4.ucode"; 720 switch (pid) { 721 case PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1: 722 case PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2: 723 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 724 sc->txchainmask = IWN_ANT_BC; 725 sc->rxchainmask = IWN_ANT_BC; 726 break; 727 default: 728 sc->txchainmask = IWN_ANT_ABC; 729 sc->rxchainmask = IWN_ANT_ABC; 730 break; 731 } 732 break; 733 case IWN_HW_REV_TYPE_6050: 734 sc->sc_hal = &iwn5000_hal; 735 sc->limits = &iwn6000_sensitivity_limits; 736 sc->fwname = "iwlwifi-6050-2.ucode"; 737 sc->txchainmask = IWN_ANT_AB; 738 sc->rxchainmask = IWN_ANT_AB; 739 break; 740 case IWN_HW_REV_TYPE_6005: 741 sc->sc_hal = &iwn5000_hal; 742 sc->limits = &iwn6000_sensitivity_limits; 743 sc->fwname = "iwlwifi-6005-2.ucode"; 744 sc->txchainmask = IWN_ANT_AB; 745 sc->rxchainmask = IWN_ANT_AB; 746 break; 747 default: 748 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 749 return NULL; 750 } 751 return sc->sc_hal; 752 } 753 754 #ifndef SMALL_KERNEL 755 /* 756 * Attach the adapter on-board thermal sensor to the sensors framework. 757 */ 758 static void 759 iwn_sensor_attach(struct iwn_softc *sc) 760 { 761 int error; 762 763 sc->sc_sensor.units = ENVSYS_STEMP; 764 #if 0 765 /* XXX something like this ought to work */ 766 sc->sc_sensor.flags = ENVSYS_FMONLIMITS | ENVSYS_FMONNOTSUPP; 767 sc->sc_sensor.limits.sel_critmax = IWN_CTOK(110); 768 #endif 769 strlcpy((sc->sc_sensor.desc), "TEMP", sizeof(sc->sc_sensor.desc)); 770 771 /* Temperature is not valid unless interface is up. */ 772 sc->sc_sensor.value_cur = 0; 773 sc->sc_sensor.state = ENVSYS_SINVALID; 774 775 sc->sc_sme = sysmon_envsys_create(); 776 777 /* Initialize sensor */ 778 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 779 sysmon_envsys_destroy(sc->sc_sme); 780 return; 781 } 782 783 /* 784 * Hook into the System Monitor. 785 */ 786 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 787 sc->sc_sme->sme_flags = SME_DISABLE_REFRESH; 788 789 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 790 aprint_error_dev(sc->sc_dev, 791 "unable to register with sysmon (%d)\n", error); 792 sysmon_envsys_destroy(sc->sc_sme); 793 return; 794 } 795 } 796 #endif 797 798 /* 799 * Attach the interface to 802.11 radiotap. 800 */ 801 static void 802 iwn_radiotap_attach(struct iwn_softc *sc) 803 { 804 struct ifnet *ifp = sc->sc_ic.ic_ifp; 805 806 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 807 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 808 &sc->sc_drvbpf); 809 810 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 811 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 812 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 813 814 sc->sc_txtap_len = sizeof sc->sc_txtapu; 815 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 816 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 817 } 818 819 static int 820 iwn_detach(device_t self, int flags __unused) 821 { 822 struct iwn_softc *sc = device_private(self); 823 struct ifnet *ifp = sc->sc_ic.ic_ifp; 824 int qid; 825 826 callout_stop(&sc->calib_to); 827 828 /* Uninstall interrupt handler. */ 829 if (sc->sc_ih != NULL) 830 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 831 832 /* Free DMA resources. */ 833 iwn_free_rx_ring(sc, &sc->rxq); 834 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) 835 iwn_free_tx_ring(sc, &sc->txq[qid]); 836 #ifdef IWN_USE_RBUF 837 iwn_free_rpool(sc); 838 #endif 839 iwn_free_sched(sc); 840 iwn_free_kw(sc); 841 if (sc->ict != NULL) 842 iwn_free_ict(sc); 843 iwn_free_fwmem(sc); 844 845 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 846 847 #ifndef SMALL_KERNEL 848 /* Detach the thermal sensor. */ 849 sysmon_envsys_sensor_detach(sc->sc_sme, &sc->sc_sensor); 850 sysmon_envsys_destroy(sc->sc_sme); 851 #endif 852 853 ieee80211_ifdetach(&sc->sc_ic); 854 if_detach(ifp); 855 856 return 0; 857 } 858 859 #if 0 860 /* 861 * XXX Investigate if clearing the PCI retry timeout could eliminate 862 * the repeated scan calls. Also the calls to if_init and if_start 863 * are similar to the effect of adding the call to ifioctl_common . 864 */ 865 static void 866 iwn_power(int why, void *arg) 867 { 868 struct iwn_softc *sc = arg; 869 struct ifnet *ifp; 870 pcireg_t reg; 871 int s; 872 873 if (why != PWR_RESUME) 874 return; 875 876 /* Clear device-specific "PCI retry timeout" register (41h). */ 877 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 878 reg &= ~0xff00; 879 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 880 881 s = splnet(); 882 ifp = &sc->sc_ic.ic_if; 883 if (ifp->if_flags & IFF_UP) { 884 ifp->if_init(ifp); 885 if (ifp->if_flags & IFF_RUNNING) 886 ifp->if_start(ifp); 887 } 888 splx(s); 889 } 890 #endif 891 892 static bool 893 iwn_resume(device_t dv, const pmf_qual_t *qual) 894 { 895 return true; 896 } 897 898 static int 899 iwn_nic_lock(struct iwn_softc *sc) 900 { 901 int ntries; 902 903 /* Request exclusive access to NIC. */ 904 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 905 906 /* Spin until we actually get the lock. */ 907 for (ntries = 0; ntries < 1000; ntries++) { 908 if ((IWN_READ(sc, IWN_GP_CNTRL) & 909 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 910 IWN_GP_CNTRL_MAC_ACCESS_ENA) 911 return 0; 912 DELAY(10); 913 } 914 return ETIMEDOUT; 915 } 916 917 static __inline void 918 iwn_nic_unlock(struct iwn_softc *sc) 919 { 920 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 921 } 922 923 static __inline uint32_t 924 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 925 { 926 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 927 IWN_BARRIER_READ_WRITE(sc); 928 return IWN_READ(sc, IWN_PRPH_RDATA); 929 } 930 931 static __inline void 932 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 933 { 934 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 935 IWN_BARRIER_WRITE(sc); 936 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 937 } 938 939 static __inline void 940 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 941 { 942 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 943 } 944 945 static __inline void 946 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 947 { 948 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 949 } 950 951 static __inline void 952 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 953 const uint32_t *data, int count) 954 { 955 for (; count > 0; count--, data++, addr += 4) 956 iwn_prph_write(sc, addr, *data); 957 } 958 959 static __inline uint32_t 960 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 961 { 962 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 963 IWN_BARRIER_READ_WRITE(sc); 964 return IWN_READ(sc, IWN_MEM_RDATA); 965 } 966 967 static __inline void 968 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 969 { 970 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 971 IWN_BARRIER_WRITE(sc); 972 IWN_WRITE(sc, IWN_MEM_WDATA, data); 973 } 974 975 static __inline void 976 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 977 { 978 uint32_t tmp; 979 980 tmp = iwn_mem_read(sc, addr & ~3); 981 if (addr & 3) 982 tmp = (tmp & 0x0000ffff) | data << 16; 983 else 984 tmp = (tmp & 0xffff0000) | data; 985 iwn_mem_write(sc, addr & ~3, tmp); 986 } 987 988 static __inline void 989 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 990 int count) 991 { 992 for (; count > 0; count--, addr += 4) 993 *data++ = iwn_mem_read(sc, addr); 994 } 995 996 static __inline void 997 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 998 int count) 999 { 1000 for (; count > 0; count--, addr += 4) 1001 iwn_mem_write(sc, addr, val); 1002 } 1003 1004 static int 1005 iwn_eeprom_lock(struct iwn_softc *sc) 1006 { 1007 int i, ntries; 1008 1009 for (i = 0; i < 100; i++) { 1010 /* Request exclusive access to EEPROM. */ 1011 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1012 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1013 1014 /* Spin until we actually get the lock. */ 1015 for (ntries = 0; ntries < 100; ntries++) { 1016 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1017 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1018 return 0; 1019 DELAY(10); 1020 } 1021 } 1022 return ETIMEDOUT; 1023 } 1024 1025 static __inline void 1026 iwn_eeprom_unlock(struct iwn_softc *sc) 1027 { 1028 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1029 } 1030 1031 /* 1032 * Initialize access by host to One Time Programmable ROM. 1033 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1034 */ 1035 static int 1036 iwn_init_otprom(struct iwn_softc *sc) 1037 { 1038 uint16_t prev = 0, base, next; 1039 int count, error; 1040 1041 /* Wait for clock stabilization before accessing prph. */ 1042 if ((error = iwn_clock_wait(sc)) != 0) 1043 return error; 1044 1045 if ((error = iwn_nic_lock(sc)) != 0) 1046 return error; 1047 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1048 DELAY(5); 1049 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1050 iwn_nic_unlock(sc); 1051 1052 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1053 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1054 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1055 IWN_RESET_LINK_PWR_MGMT_DIS); 1056 } 1057 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1058 /* Clear ECC status. */ 1059 IWN_SETBITS(sc, IWN_OTP_GP, 1060 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1061 1062 /* 1063 * Find the block before last block (contains the EEPROM image) 1064 * for HW without OTP shadow RAM. 1065 */ 1066 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1067 /* Switch to absolute addressing mode. */ 1068 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1069 base = 0; 1070 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1071 error = iwn_read_prom_data(sc, base, &next, 2); 1072 if (error != 0) 1073 return error; 1074 if (next == 0) /* End of linked-list. */ 1075 break; 1076 prev = base; 1077 base = le16toh(next); 1078 } 1079 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1080 return EIO; 1081 /* Skip "next" word. */ 1082 sc->prom_base = prev + 1; 1083 } 1084 return 0; 1085 } 1086 1087 static int 1088 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1089 { 1090 uint8_t *out = data; 1091 uint32_t val, tmp; 1092 int ntries; 1093 1094 addr += sc->prom_base; 1095 for (; count > 0; count -= 2, addr++) { 1096 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1097 for (ntries = 0; ntries < 10; ntries++) { 1098 val = IWN_READ(sc, IWN_EEPROM); 1099 if (val & IWN_EEPROM_READ_VALID) 1100 break; 1101 DELAY(5); 1102 } 1103 if (ntries == 10) { 1104 aprint_error_dev(sc->sc_dev, 1105 "timeout reading ROM at 0x%x\n", addr); 1106 return ETIMEDOUT; 1107 } 1108 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1109 /* OTPROM, check for ECC errors. */ 1110 tmp = IWN_READ(sc, IWN_OTP_GP); 1111 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1112 aprint_error_dev(sc->sc_dev, 1113 "OTPROM ECC error at 0x%x\n", addr); 1114 return EIO; 1115 } 1116 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1117 /* Correctable ECC error, clear bit. */ 1118 IWN_SETBITS(sc, IWN_OTP_GP, 1119 IWN_OTP_GP_ECC_CORR_STTS); 1120 } 1121 } 1122 *out++ = val >> 16; 1123 if (count > 1) 1124 *out++ = val >> 24; 1125 } 1126 return 0; 1127 } 1128 1129 static int 1130 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1131 bus_size_t size, bus_size_t alignment) 1132 { 1133 int nsegs, error; 1134 1135 dma->tag = tag; 1136 dma->size = size; 1137 1138 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1139 &dma->map); 1140 if (error != 0) 1141 goto fail; 1142 1143 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1144 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1145 if (error != 0) 1146 goto fail; 1147 1148 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1149 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1150 if (error != 0) 1151 goto fail; 1152 1153 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1154 BUS_DMA_NOWAIT); 1155 if (error != 0) 1156 goto fail; 1157 1158 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1159 memset(dma->vaddr, 0, size); 1160 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1161 1162 dma->paddr = dma->map->dm_segs[0].ds_addr; 1163 if (kvap != NULL) 1164 *kvap = dma->vaddr; 1165 1166 return 0; 1167 1168 fail: iwn_dma_contig_free(dma); 1169 return error; 1170 } 1171 1172 static void 1173 iwn_dma_contig_free(struct iwn_dma_info *dma) 1174 { 1175 if (dma->map != NULL) { 1176 if (dma->vaddr != NULL) { 1177 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1178 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1179 bus_dmamap_unload(dma->tag, dma->map); 1180 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1181 bus_dmamem_free(dma->tag, &dma->seg, 1); 1182 dma->vaddr = NULL; 1183 } 1184 bus_dmamap_destroy(dma->tag, dma->map); 1185 dma->map = NULL; 1186 } 1187 } 1188 1189 static int 1190 iwn_alloc_sched(struct iwn_softc *sc) 1191 { 1192 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1193 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1194 (void **)&sc->sched, sc->sc_hal->schedsz, 1024); 1195 } 1196 1197 static void 1198 iwn_free_sched(struct iwn_softc *sc) 1199 { 1200 iwn_dma_contig_free(&sc->sched_dma); 1201 } 1202 1203 static int 1204 iwn_alloc_kw(struct iwn_softc *sc) 1205 { 1206 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1207 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1208 4096); 1209 } 1210 1211 static void 1212 iwn_free_kw(struct iwn_softc *sc) 1213 { 1214 iwn_dma_contig_free(&sc->kw_dma); 1215 } 1216 1217 static int 1218 iwn_alloc_ict(struct iwn_softc *sc) 1219 { 1220 /* ICT table must be aligned on a 4KB boundary. */ 1221 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1222 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1223 } 1224 1225 static void 1226 iwn_free_ict(struct iwn_softc *sc) 1227 { 1228 iwn_dma_contig_free(&sc->ict_dma); 1229 } 1230 1231 static int 1232 iwn_alloc_fwmem(struct iwn_softc *sc) 1233 { 1234 /* Must be aligned on a 16-byte boundary. */ 1235 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1236 sc->sc_hal->fwsz, 16); 1237 } 1238 1239 static void 1240 iwn_free_fwmem(struct iwn_softc *sc) 1241 { 1242 iwn_dma_contig_free(&sc->fw_dma); 1243 } 1244 1245 static int 1246 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1247 { 1248 bus_size_t size; 1249 int i, error; 1250 1251 ring->cur = 0; 1252 1253 /* Allocate RX descriptors (256-byte aligned.) */ 1254 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1255 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1256 (void **)&ring->desc, size, 256); 1257 if (error != 0) { 1258 aprint_error_dev(sc->sc_dev, 1259 "could not allocate RX ring DMA memory\n"); 1260 goto fail; 1261 } 1262 1263 /* Allocate RX status area (16-byte aligned.) */ 1264 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1265 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1266 if (error != 0) { 1267 aprint_error_dev(sc->sc_dev, 1268 "could not allocate RX status DMA memory\n"); 1269 goto fail; 1270 } 1271 1272 /* 1273 * Allocate and map RX buffers. 1274 */ 1275 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1276 struct iwn_rx_data *data = &ring->data[i]; 1277 1278 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1279 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1280 &data->map); 1281 if (error != 0) { 1282 aprint_error_dev(sc->sc_dev, 1283 "could not create RX buf DMA map\n"); 1284 goto fail; 1285 } 1286 1287 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1288 if (data->m == NULL) { 1289 aprint_error_dev(sc->sc_dev, 1290 "could not allocate RX mbuf\n"); 1291 error = ENOBUFS; 1292 goto fail; 1293 } 1294 1295 error = bus_dmamap_load(sc->sc_dmat, data->map, 1296 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1297 BUS_DMA_NOWAIT | BUS_DMA_READ); 1298 if (error != 0) { 1299 aprint_error_dev(sc->sc_dev, 1300 "can't not map mbuf (error %d)\n", error); 1301 goto fail; 1302 } 1303 1304 /* Set physical address of RX buffer (256-byte aligned.) */ 1305 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1306 } 1307 1308 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1309 BUS_DMASYNC_PREWRITE); 1310 1311 return 0; 1312 1313 fail: iwn_free_rx_ring(sc, ring); 1314 return error; 1315 } 1316 1317 static void 1318 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1319 { 1320 int ntries; 1321 1322 if (iwn_nic_lock(sc) == 0) { 1323 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1324 for (ntries = 0; ntries < 1000; ntries++) { 1325 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1326 IWN_FH_RX_STATUS_IDLE) 1327 break; 1328 DELAY(10); 1329 } 1330 iwn_nic_unlock(sc); 1331 } 1332 ring->cur = 0; 1333 sc->last_rx_valid = 0; 1334 } 1335 1336 static void 1337 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1338 { 1339 int i; 1340 1341 iwn_dma_contig_free(&ring->desc_dma); 1342 iwn_dma_contig_free(&ring->stat_dma); 1343 1344 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1345 struct iwn_rx_data *data = &ring->data[i]; 1346 1347 if (data->m != NULL) { 1348 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1349 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1350 bus_dmamap_unload(sc->sc_dmat, data->map); 1351 m_freem(data->m); 1352 } 1353 if (data->map != NULL) 1354 bus_dmamap_destroy(sc->sc_dmat, data->map); 1355 } 1356 } 1357 1358 static int 1359 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1360 { 1361 bus_addr_t paddr; 1362 bus_size_t size; 1363 int i, error; 1364 1365 ring->qid = qid; 1366 ring->queued = 0; 1367 ring->cur = 0; 1368 1369 /* Allocate TX descriptors (256-byte aligned.) */ 1370 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1371 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1372 (void **)&ring->desc, size, 256); 1373 if (error != 0) { 1374 aprint_error_dev(sc->sc_dev, 1375 "could not allocate TX ring DMA memory\n"); 1376 goto fail; 1377 } 1378 /* 1379 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1380 * to allocate commands space for other rings. 1381 * XXX Do we really need to allocate descriptors for other rings? 1382 */ 1383 if (qid > 4) 1384 return 0; 1385 1386 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1387 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1388 (void **)&ring->cmd, size, 4); 1389 if (error != 0) { 1390 aprint_error_dev(sc->sc_dev, 1391 "could not allocate TX cmd DMA memory\n"); 1392 goto fail; 1393 } 1394 1395 paddr = ring->cmd_dma.paddr; 1396 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1397 struct iwn_tx_data *data = &ring->data[i]; 1398 1399 data->cmd_paddr = paddr; 1400 data->scratch_paddr = paddr + 12; 1401 paddr += sizeof (struct iwn_tx_cmd); 1402 1403 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1404 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1405 &data->map); 1406 if (error != 0) { 1407 aprint_error_dev(sc->sc_dev, 1408 "could not create TX buf DMA map\n"); 1409 goto fail; 1410 } 1411 } 1412 return 0; 1413 1414 fail: iwn_free_tx_ring(sc, ring); 1415 return error; 1416 } 1417 1418 static void 1419 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1420 { 1421 int i; 1422 1423 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1424 struct iwn_tx_data *data = &ring->data[i]; 1425 1426 if (data->m != NULL) { 1427 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1428 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1429 bus_dmamap_unload(sc->sc_dmat, data->map); 1430 m_freem(data->m); 1431 data->m = NULL; 1432 } 1433 } 1434 /* Clear TX descriptors. */ 1435 memset(ring->desc, 0, ring->desc_dma.size); 1436 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1437 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1438 sc->qfullmsk &= ~(1 << ring->qid); 1439 ring->queued = 0; 1440 ring->cur = 0; 1441 } 1442 1443 static void 1444 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1445 { 1446 int i; 1447 1448 iwn_dma_contig_free(&ring->desc_dma); 1449 iwn_dma_contig_free(&ring->cmd_dma); 1450 1451 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1452 struct iwn_tx_data *data = &ring->data[i]; 1453 1454 if (data->m != NULL) { 1455 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1456 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1457 bus_dmamap_unload(sc->sc_dmat, data->map); 1458 m_freem(data->m); 1459 } 1460 if (data->map != NULL) 1461 bus_dmamap_destroy(sc->sc_dmat, data->map); 1462 } 1463 } 1464 1465 static void 1466 iwn5000_ict_reset(struct iwn_softc *sc) 1467 { 1468 /* Disable interrupts. */ 1469 IWN_WRITE(sc, IWN_INT_MASK, 0); 1470 1471 /* Reset ICT table. */ 1472 memset(sc->ict, 0, IWN_ICT_SIZE); 1473 sc->ict_cur = 0; 1474 1475 /* Set physical address of ICT table (4KB aligned.) */ 1476 DPRINTF(("enabling ICT\n")); 1477 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1478 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1479 1480 /* Enable periodic RX interrupt. */ 1481 sc->int_mask |= IWN_INT_RX_PERIODIC; 1482 /* Switch to ICT interrupt mode in driver. */ 1483 sc->sc_flags |= IWN_FLAG_USE_ICT; 1484 1485 /* Re-enable interrupts. */ 1486 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1487 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1488 } 1489 1490 static int 1491 iwn_read_eeprom(struct iwn_softc *sc) 1492 { 1493 const struct iwn_hal *hal = sc->sc_hal; 1494 struct ieee80211com *ic = &sc->sc_ic; 1495 uint16_t val; 1496 int error; 1497 1498 /* Check whether adapter has an EEPROM or an OTPROM. */ 1499 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1500 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1501 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1502 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1503 "OTPROM" : "EEPROM")); 1504 1505 /* Adapter has to be powered on for EEPROM access to work. */ 1506 if ((error = iwn_apm_init(sc)) != 0) { 1507 aprint_error_dev(sc->sc_dev, 1508 "could not power ON adapter\n"); 1509 return error; 1510 } 1511 1512 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1513 aprint_error_dev(sc->sc_dev, 1514 "bad ROM signature\n"); 1515 return EIO; 1516 } 1517 if ((error = iwn_eeprom_lock(sc)) != 0) { 1518 aprint_error_dev(sc->sc_dev, 1519 "could not lock ROM (error=%d)\n", error); 1520 return error; 1521 } 1522 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1523 if ((error = iwn_init_otprom(sc)) != 0) { 1524 aprint_error_dev(sc->sc_dev, 1525 "could not initialize OTPROM\n"); 1526 return error; 1527 } 1528 } 1529 1530 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1531 sc->rfcfg = le16toh(val); 1532 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1533 1534 /* Read MAC address. */ 1535 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1536 1537 /* Read adapter-specific information from EEPROM. */ 1538 hal->read_eeprom(sc); 1539 1540 iwn_apm_stop(sc); /* Power OFF adapter. */ 1541 1542 iwn_eeprom_unlock(sc); 1543 return 0; 1544 } 1545 1546 static void 1547 iwn4965_read_eeprom(struct iwn_softc *sc) 1548 { 1549 uint32_t addr; 1550 uint16_t val; 1551 int i; 1552 1553 /* Read regulatory domain (4 ASCII characters.) */ 1554 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1555 1556 /* Read the list of authorized channels (20MHz ones only.) */ 1557 for (i = 0; i < 5; i++) { 1558 addr = iwn4965_regulatory_bands[i]; 1559 iwn_read_eeprom_channels(sc, i, addr); 1560 } 1561 1562 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1563 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1564 sc->maxpwr2GHz = val & 0xff; 1565 sc->maxpwr5GHz = val >> 8; 1566 /* Check that EEPROM values are within valid range. */ 1567 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1568 sc->maxpwr5GHz = 38; 1569 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1570 sc->maxpwr2GHz = 38; 1571 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1572 1573 /* Read samples for each TX power group. */ 1574 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1575 sizeof sc->bands); 1576 1577 /* Read voltage at which samples were taken. */ 1578 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1579 sc->eeprom_voltage = (int16_t)le16toh(val); 1580 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1581 1582 #ifdef IWN_DEBUG 1583 /* Print samples. */ 1584 if (iwn_debug > 0) { 1585 for (i = 0; i < IWN_NBANDS; i++) 1586 iwn4965_print_power_group(sc, i); 1587 } 1588 #endif 1589 } 1590 1591 #ifdef IWN_DEBUG 1592 static void 1593 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1594 { 1595 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1596 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1597 int j, c; 1598 1599 aprint_normal("===band %d===\n", i); 1600 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1601 aprint_normal("chan1 num=%d\n", chans[0].num); 1602 for (c = 0; c < 2; c++) { 1603 for (j = 0; j < IWN_NSAMPLES; j++) { 1604 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1605 "power=%d pa_det=%d\n", c, j, 1606 chans[0].samples[c][j].temp, 1607 chans[0].samples[c][j].gain, 1608 chans[0].samples[c][j].power, 1609 chans[0].samples[c][j].pa_det); 1610 } 1611 } 1612 aprint_normal("chan2 num=%d\n", chans[1].num); 1613 for (c = 0; c < 2; c++) { 1614 for (j = 0; j < IWN_NSAMPLES; j++) { 1615 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1616 "power=%d pa_det=%d\n", c, j, 1617 chans[1].samples[c][j].temp, 1618 chans[1].samples[c][j].gain, 1619 chans[1].samples[c][j].power, 1620 chans[1].samples[c][j].pa_det); 1621 } 1622 } 1623 } 1624 #endif 1625 1626 static void 1627 iwn5000_read_eeprom(struct iwn_softc *sc) 1628 { 1629 struct iwn5000_eeprom_calib_hdr hdr; 1630 int32_t temp, volt; 1631 uint32_t base, addr; 1632 uint16_t val; 1633 int i; 1634 1635 /* Read regulatory domain (4 ASCII characters.) */ 1636 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1637 base = le16toh(val); 1638 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1639 sc->eeprom_domain, 4); 1640 1641 /* Read the list of authorized channels (20MHz ones only.) */ 1642 for (i = 0; i < 5; i++) { 1643 addr = base + iwn5000_regulatory_bands[i]; 1644 iwn_read_eeprom_channels(sc, i, addr); 1645 } 1646 1647 /* Read enhanced TX power information for 6000 Series. */ 1648 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1649 iwn_read_eeprom_enhinfo(sc); 1650 1651 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1652 base = le16toh(val); 1653 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1654 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1655 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1656 sc->calib_ver = hdr.version; 1657 1658 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1659 /* Compute temperature offset. */ 1660 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1661 temp = le16toh(val); 1662 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1663 volt = le16toh(val); 1664 sc->temp_off = temp - (volt / -5); 1665 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1666 temp, volt, sc->temp_off)); 1667 } else { 1668 /* Read crystal calibration. */ 1669 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1670 &sc->eeprom_crystal, sizeof (uint32_t)); 1671 DPRINTF(("crystal calibration 0x%08x\n", 1672 le32toh(sc->eeprom_crystal))); 1673 } 1674 } 1675 1676 static void 1677 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1678 { 1679 struct ieee80211com *ic = &sc->sc_ic; 1680 const struct iwn_chan_band *band = &iwn_bands[n]; 1681 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1682 uint8_t chan; 1683 int i; 1684 1685 iwn_read_prom_data(sc, addr, channels, 1686 band->nchan * sizeof (struct iwn_eeprom_chan)); 1687 1688 for (i = 0; i < band->nchan; i++) { 1689 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1690 continue; 1691 1692 chan = band->chan[i]; 1693 1694 if (n == 0) { /* 2GHz band */ 1695 ic->ic_channels[chan].ic_freq = 1696 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1697 ic->ic_channels[chan].ic_flags = 1698 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1699 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1700 1701 } else { /* 5GHz band */ 1702 /* 1703 * Some adapters support channels 7, 8, 11 and 12 1704 * both in the 2GHz and 4.9GHz bands. 1705 * Because of limitations in our net80211 layer, 1706 * we don't support them in the 4.9GHz band. 1707 */ 1708 if (chan <= 14) 1709 continue; 1710 1711 ic->ic_channels[chan].ic_freq = 1712 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1713 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1714 /* We have at least one valid 5GHz channel. */ 1715 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1716 } 1717 1718 /* Is active scan allowed on this channel? */ 1719 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1720 ic->ic_channels[chan].ic_flags |= 1721 IEEE80211_CHAN_PASSIVE; 1722 } 1723 1724 /* Save maximum allowed TX power for this channel. */ 1725 sc->maxpwr[chan] = channels[i].maxpwr; 1726 1727 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1728 chan, channels[i].flags, sc->maxpwr[chan])); 1729 } 1730 } 1731 1732 static void 1733 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1734 { 1735 struct iwn_eeprom_enhinfo enhinfo[35]; 1736 uint16_t val, base; 1737 int8_t maxpwr; 1738 int i; 1739 1740 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1741 base = le16toh(val); 1742 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1743 enhinfo, sizeof enhinfo); 1744 1745 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1746 for (i = 0; i < __arraycount(enhinfo); i++) { 1747 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1748 continue; /* Skip invalid entries. */ 1749 1750 maxpwr = 0; 1751 if (sc->txchainmask & IWN_ANT_A) 1752 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1753 if (sc->txchainmask & IWN_ANT_B) 1754 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1755 if (sc->txchainmask & IWN_ANT_C) 1756 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1757 if (sc->ntxchains == 2) 1758 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1759 else if (sc->ntxchains == 3) 1760 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1761 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1762 1763 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1764 sc->enh_maxpwr[i] = maxpwr; 1765 } 1766 } 1767 1768 static struct ieee80211_node * 1769 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1770 { 1771 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1772 } 1773 1774 static void 1775 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1776 { 1777 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1778 struct iwn_node *wn = (void *)ni; 1779 uint8_t rate; 1780 int ridx, i; 1781 1782 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1783 /* Start at lowest available bit-rate, AMRR will raise. */ 1784 ni->ni_txrate = 0; 1785 1786 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1787 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1788 /* Map 802.11 rate to HW rate index. */ 1789 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1790 if (iwn_rates[ridx].rate == rate) 1791 break; 1792 wn->ridx[i] = ridx; 1793 } 1794 } 1795 1796 static int 1797 iwn_media_change(struct ifnet *ifp) 1798 { 1799 struct iwn_softc *sc = ifp->if_softc; 1800 struct ieee80211com *ic = &sc->sc_ic; 1801 uint8_t rate, ridx; 1802 int error; 1803 1804 error = ieee80211_media_change(ifp); 1805 if (error != ENETRESET) 1806 return error; 1807 1808 if (ic->ic_fixed_rate != -1) { 1809 rate = ic->ic_sup_rates[ic->ic_curmode]. 1810 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1811 /* Map 802.11 rate to HW rate index. */ 1812 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1813 if (iwn_rates[ridx].rate == rate) 1814 break; 1815 sc->fixed_ridx = ridx; 1816 } 1817 1818 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1819 (IFF_UP | IFF_RUNNING)) { 1820 iwn_stop(ifp, 0); 1821 error = iwn_init(ifp); 1822 } 1823 return error; 1824 } 1825 1826 static int 1827 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1828 { 1829 struct ifnet *ifp = ic->ic_ifp; 1830 struct iwn_softc *sc = ifp->if_softc; 1831 int error; 1832 1833 callout_stop(&sc->calib_to); 1834 1835 switch (nstate) { 1836 case IEEE80211_S_SCAN: 1837 /* XXX Do not abort a running scan. */ 1838 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1839 aprint_error_dev(sc->sc_dev, 1840 "scan request while scanning ignored\n"); 1841 break; 1842 } 1843 1844 /* XXX Not sure if call and flags are needed. */ 1845 ieee80211_node_table_reset(&ic->ic_scan); 1846 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1847 sc->sc_flags |= IWN_FLAG_SCANNING; 1848 1849 /* Make the link LED blink while we're scanning. */ 1850 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1851 1852 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1853 aprint_error_dev(sc->sc_dev, 1854 "could not initiate scan\n"); 1855 return error; 1856 } 1857 ic->ic_state = nstate; 1858 return 0; 1859 1860 case IEEE80211_S_ASSOC: 1861 if (ic->ic_state != IEEE80211_S_RUN) 1862 break; 1863 /* FALLTHROUGH */ 1864 case IEEE80211_S_AUTH: 1865 /* Reset state to handle reassociations correctly. */ 1866 sc->rxon.associd = 0; 1867 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1868 sc->calib.state = IWN_CALIB_STATE_INIT; 1869 1870 if ((error = iwn_auth(sc)) != 0) { 1871 aprint_error_dev(sc->sc_dev, 1872 "could not move to auth state\n"); 1873 return error; 1874 } 1875 break; 1876 1877 case IEEE80211_S_RUN: 1878 if ((error = iwn_run(sc)) != 0) { 1879 aprint_error_dev(sc->sc_dev, 1880 "could not move to run state\n"); 1881 return error; 1882 } 1883 break; 1884 1885 case IEEE80211_S_INIT: 1886 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1887 sc->calib.state = IWN_CALIB_STATE_INIT; 1888 break; 1889 } 1890 1891 return sc->sc_newstate(ic, nstate, arg); 1892 } 1893 1894 static void 1895 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1896 { 1897 struct iwn_softc *sc = arg; 1898 struct iwn_node *wn = (struct iwn_node *)ni; 1899 1900 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1901 } 1902 1903 static void 1904 iwn_calib_timeout(void *arg) 1905 { 1906 struct iwn_softc *sc = arg; 1907 struct ieee80211com *ic = &sc->sc_ic; 1908 int s; 1909 1910 s = splnet(); 1911 if (ic->ic_fixed_rate == -1) { 1912 if (ic->ic_opmode == IEEE80211_M_STA) 1913 iwn_iter_func(sc, ic->ic_bss); 1914 else 1915 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1916 } 1917 /* Force automatic TX power calibration every 60 secs. */ 1918 if (++sc->calib_cnt >= 120) { 1919 uint32_t flags = 0; 1920 1921 DPRINTF(("sending request for statistics\n")); 1922 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1923 sizeof flags, 1); 1924 sc->calib_cnt = 0; 1925 } 1926 splx(s); 1927 1928 /* Automatic rate control triggered every 500ms. */ 1929 callout_schedule(&sc->calib_to, hz/2); 1930 } 1931 1932 /* 1933 * Process an RX_PHY firmware notification. This is usually immediately 1934 * followed by an MPDU_RX_DONE notification. 1935 */ 1936 static void 1937 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1938 struct iwn_rx_data *data) 1939 { 1940 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1941 1942 DPRINTFN(2, ("received PHY stats\n")); 1943 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1944 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1945 1946 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1947 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1948 sc->last_rx_valid = 1; 1949 } 1950 1951 /* 1952 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1953 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1954 */ 1955 static void 1956 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1957 struct iwn_rx_data *data) 1958 { 1959 const struct iwn_hal *hal = sc->sc_hal; 1960 struct ieee80211com *ic = &sc->sc_ic; 1961 struct ifnet *ifp = ic->ic_ifp; 1962 struct iwn_rx_ring *ring = &sc->rxq; 1963 struct ieee80211_frame *wh; 1964 struct ieee80211_node *ni; 1965 struct mbuf *m, *m1; 1966 struct iwn_rx_stat *stat; 1967 char *head; 1968 uint32_t flags; 1969 int error, len, rssi; 1970 1971 if (desc->type == IWN_MPDU_RX_DONE) { 1972 /* Check for prior RX_PHY notification. */ 1973 if (!sc->last_rx_valid) { 1974 DPRINTF(("missing RX_PHY\n")); 1975 ifp->if_ierrors++; 1976 return; 1977 } 1978 sc->last_rx_valid = 0; 1979 stat = &sc->last_rx_stat; 1980 } else 1981 stat = (struct iwn_rx_stat *)(desc + 1); 1982 1983 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1984 BUS_DMASYNC_POSTREAD); 1985 1986 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1987 aprint_error_dev(sc->sc_dev, 1988 "invalid RX statistic header\n"); 1989 ifp->if_ierrors++; 1990 return; 1991 } 1992 if (desc->type == IWN_MPDU_RX_DONE) { 1993 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1994 head = (char *)(mpdu + 1); 1995 len = le16toh(mpdu->len); 1996 } else { 1997 head = (char *)(stat + 1) + stat->cfg_phy_len; 1998 len = le16toh(stat->len); 1999 } 2000 2001 flags = le32toh(*(uint32_t *)(head + len)); 2002 2003 /* Discard frames with a bad FCS early. */ 2004 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2005 DPRINTFN(2, ("RX flags error %x\n", flags)); 2006 ifp->if_ierrors++; 2007 return; 2008 } 2009 /* Discard frames that are too short. */ 2010 if (len < sizeof (*wh)) { 2011 DPRINTF(("frame too short: %d\n", len)); 2012 ic->ic_stats.is_rx_tooshort++; 2013 ifp->if_ierrors++; 2014 return; 2015 } 2016 2017 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2018 if (m1 == NULL) { 2019 ic->ic_stats.is_rx_nobuf++; 2020 ifp->if_ierrors++; 2021 return; 2022 } 2023 bus_dmamap_unload(sc->sc_dmat, data->map); 2024 2025 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2026 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2027 if (error != 0) { 2028 m_freem(m1); 2029 2030 /* Try to reload the old mbuf. */ 2031 error = bus_dmamap_load(sc->sc_dmat, data->map, 2032 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2033 BUS_DMA_NOWAIT | BUS_DMA_READ); 2034 if (error != 0) { 2035 panic("%s: could not load old RX mbuf", 2036 device_xname(sc->sc_dev)); 2037 } 2038 /* Physical address may have changed. */ 2039 ring->desc[ring->cur] = 2040 htole32(data->map->dm_segs[0].ds_addr >> 8); 2041 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2042 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2043 BUS_DMASYNC_PREWRITE); 2044 ifp->if_ierrors++; 2045 return; 2046 } 2047 2048 m = data->m; 2049 data->m = m1; 2050 /* Update RX descriptor. */ 2051 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2052 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2053 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2054 BUS_DMASYNC_PREWRITE); 2055 2056 /* Finalize mbuf. */ 2057 m->m_pkthdr.rcvif = ifp; 2058 m->m_data = head; 2059 m->m_pkthdr.len = m->m_len = len; 2060 2061 /* Grab a reference to the source node. */ 2062 wh = mtod(m, struct ieee80211_frame *); 2063 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2064 2065 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2066 /* NetBSD does decryption in ieee80211_input. */ 2067 2068 rssi = hal->get_rssi(stat); 2069 2070 /* XXX Added for NetBSD: scans never stop without it */ 2071 if (ic->ic_state == IEEE80211_S_SCAN) 2072 iwn_fix_channel(ic, m); 2073 2074 if (sc->sc_drvbpf != NULL) { 2075 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2076 2077 tap->wr_flags = 0; 2078 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2079 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2080 tap->wr_chan_freq = 2081 htole16(ic->ic_channels[stat->chan].ic_freq); 2082 tap->wr_chan_flags = 2083 htole16(ic->ic_channels[stat->chan].ic_flags); 2084 tap->wr_dbm_antsignal = (int8_t)rssi; 2085 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2086 tap->wr_tsft = stat->tstamp; 2087 switch (stat->rate) { 2088 /* CCK rates. */ 2089 case 10: tap->wr_rate = 2; break; 2090 case 20: tap->wr_rate = 4; break; 2091 case 55: tap->wr_rate = 11; break; 2092 case 110: tap->wr_rate = 22; break; 2093 /* OFDM rates. */ 2094 case 0xd: tap->wr_rate = 12; break; 2095 case 0xf: tap->wr_rate = 18; break; 2096 case 0x5: tap->wr_rate = 24; break; 2097 case 0x7: tap->wr_rate = 36; break; 2098 case 0x9: tap->wr_rate = 48; break; 2099 case 0xb: tap->wr_rate = 72; break; 2100 case 0x1: tap->wr_rate = 96; break; 2101 case 0x3: tap->wr_rate = 108; break; 2102 /* Unknown rate: should not happen. */ 2103 default: tap->wr_rate = 0; 2104 } 2105 2106 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2107 } 2108 2109 /* Send the frame to the 802.11 layer. */ 2110 ieee80211_input(ic, m, ni, rssi, 0); 2111 2112 /* Node is no longer needed. */ 2113 ieee80211_free_node(ni); 2114 } 2115 2116 #ifndef IEEE80211_NO_HT 2117 /* Process an incoming Compressed BlockAck. */ 2118 static void 2119 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2120 struct iwn_rx_data *data) 2121 { 2122 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2123 struct iwn_tx_ring *txq; 2124 2125 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2126 BUS_DMASYNC_POSTREAD); 2127 2128 txq = &sc->txq[le16toh(ba->qid)]; 2129 /* XXX TBD */ 2130 } 2131 #endif 2132 2133 /* 2134 * Process a CALIBRATION_RESULT notification sent by the initialization 2135 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2136 */ 2137 static void 2138 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2139 struct iwn_rx_data *data) 2140 { 2141 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2142 int len, idx = -1; 2143 2144 /* Runtime firmware should not send such a notification. */ 2145 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2146 return; 2147 2148 len = (le32toh(desc->len) & 0x3fff) - 4; 2149 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2150 BUS_DMASYNC_POSTREAD); 2151 2152 switch (calib->code) { 2153 case IWN5000_PHY_CALIB_DC: 2154 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2155 sc->hw_type == IWN_HW_REV_TYPE_6050) 2156 idx = 0; 2157 break; 2158 case IWN5000_PHY_CALIB_LO: 2159 idx = 1; 2160 break; 2161 case IWN5000_PHY_CALIB_TX_IQ: 2162 idx = 2; 2163 break; 2164 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2165 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2166 sc->hw_type != IWN_HW_REV_TYPE_5150) 2167 idx = 3; 2168 break; 2169 case IWN5000_PHY_CALIB_BASE_BAND: 2170 idx = 4; 2171 break; 2172 } 2173 if (idx == -1) /* Ignore other results. */ 2174 return; 2175 2176 /* Save calibration result. */ 2177 if (sc->calibcmd[idx].buf != NULL) 2178 free(sc->calibcmd[idx].buf, M_DEVBUF); 2179 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2180 if (sc->calibcmd[idx].buf == NULL) { 2181 DPRINTF(("not enough memory for calibration result %d\n", 2182 calib->code)); 2183 return; 2184 } 2185 DPRINTF(("saving calibration result code=%d len=%d\n", 2186 calib->code, len)); 2187 sc->calibcmd[idx].len = len; 2188 memcpy(sc->calibcmd[idx].buf, calib, len); 2189 } 2190 2191 /* 2192 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2193 * The latter is sent by the firmware after each received beacon. 2194 */ 2195 static void 2196 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2197 struct iwn_rx_data *data) 2198 { 2199 const struct iwn_hal *hal = sc->sc_hal; 2200 struct ieee80211com *ic = &sc->sc_ic; 2201 struct iwn_calib_state *calib = &sc->calib; 2202 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2203 int temp; 2204 2205 /* Ignore statistics received during a scan. */ 2206 if (ic->ic_state != IEEE80211_S_RUN) 2207 return; 2208 2209 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2210 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2211 2212 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2213 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2214 2215 /* Test if temperature has changed. */ 2216 if (stats->general.temp != sc->rawtemp) { 2217 /* Convert "raw" temperature to degC. */ 2218 sc->rawtemp = stats->general.temp; 2219 temp = hal->get_temperature(sc); 2220 DPRINTFN(2, ("temperature=%dC\n", temp)); 2221 2222 #ifndef SMALL_KERNEL 2223 /* Update temperature sensor. */ 2224 sc->sc_sensor.value_cur = IWN_CTOMUK(temp); 2225 sc->sc_sensor.state = ENVSYS_SVALID; 2226 #endif 2227 2228 /* Update TX power if need be (4965AGN only.) */ 2229 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2230 iwn4965_power_calibration(sc, temp); 2231 } 2232 2233 if (desc->type != IWN_BEACON_STATISTICS) 2234 return; /* Reply to a statistics request. */ 2235 2236 sc->noise = iwn_get_noise(&stats->rx.general); 2237 2238 /* Test that RSSI and noise are present in stats report. */ 2239 if (le32toh(stats->rx.general.flags) != 1) { 2240 DPRINTF(("received statistics without RSSI\n")); 2241 return; 2242 } 2243 2244 if (calib->state == IWN_CALIB_STATE_ASSOC) 2245 iwn_collect_noise(sc, &stats->rx.general); 2246 else if (calib->state == IWN_CALIB_STATE_RUN) 2247 iwn_tune_sensitivity(sc, &stats->rx); 2248 } 2249 2250 /* 2251 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2252 * and 5000 adapters have different incompatible TX status formats. 2253 */ 2254 static void 2255 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2256 struct iwn_rx_data *data) 2257 { 2258 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2259 2260 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2261 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2262 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2263 } 2264 2265 static void 2266 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2267 struct iwn_rx_data *data) 2268 { 2269 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2270 2271 #ifdef notyet 2272 /* Reset TX scheduler slot. */ 2273 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2274 #endif 2275 2276 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2277 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2278 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2279 } 2280 2281 /* 2282 * Adapter-independent backend for TX_DONE firmware notifications. 2283 */ 2284 static void 2285 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2286 uint8_t status) 2287 { 2288 struct ieee80211com *ic = &sc->sc_ic; 2289 struct ifnet *ifp = ic->ic_ifp; 2290 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2291 struct iwn_tx_data *data = &ring->data[desc->idx]; 2292 struct iwn_node *wn = (struct iwn_node *)data->ni; 2293 2294 /* Update rate control statistics. */ 2295 wn->amn.amn_txcnt++; 2296 if (ackfailcnt > 0) 2297 wn->amn.amn_retrycnt++; 2298 2299 if (status != 1 && status != 2) 2300 ifp->if_oerrors++; 2301 else 2302 ifp->if_opackets++; 2303 2304 /* Unmap and free mbuf. */ 2305 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2306 BUS_DMASYNC_POSTWRITE); 2307 bus_dmamap_unload(sc->sc_dmat, data->map); 2308 m_freem(data->m); 2309 data->m = NULL; 2310 ieee80211_free_node(data->ni); 2311 data->ni = NULL; 2312 2313 sc->sc_tx_timer = 0; 2314 if (--ring->queued < IWN_TX_RING_LOMARK) { 2315 sc->qfullmsk &= ~(1 << ring->qid); 2316 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2317 ifp->if_flags &= ~IFF_OACTIVE; 2318 (*ifp->if_start)(ifp); 2319 } 2320 } 2321 } 2322 2323 /* 2324 * Process a "command done" firmware notification. This is where we wakeup 2325 * processes waiting for a synchronous command completion. 2326 */ 2327 static void 2328 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2329 { 2330 struct iwn_tx_ring *ring = &sc->txq[4]; 2331 struct iwn_tx_data *data; 2332 2333 if ((desc->qid & 0xf) != 4) 2334 return; /* Not a command ack. */ 2335 2336 data = &ring->data[desc->idx]; 2337 2338 /* If the command was mapped in an mbuf, free it. */ 2339 if (data->m != NULL) { 2340 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2341 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2342 bus_dmamap_unload(sc->sc_dmat, data->map); 2343 m_freem(data->m); 2344 data->m = NULL; 2345 } 2346 wakeup(&ring->desc[desc->idx]); 2347 } 2348 2349 /* 2350 * Process an INT_FH_RX or INT_SW_RX interrupt. 2351 */ 2352 static void 2353 iwn_notif_intr(struct iwn_softc *sc) 2354 { 2355 struct ieee80211com *ic = &sc->sc_ic; 2356 struct ifnet *ifp = ic->ic_ifp; 2357 uint16_t hw; 2358 2359 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2360 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2361 2362 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2363 while (sc->rxq.cur != hw) { 2364 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2365 struct iwn_rx_desc *desc; 2366 2367 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2368 BUS_DMASYNC_POSTREAD); 2369 desc = mtod(data->m, struct iwn_rx_desc *); 2370 2371 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2372 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2373 2374 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2375 iwn_cmd_done(sc, desc); 2376 2377 switch (desc->type) { 2378 case IWN_RX_PHY: 2379 iwn_rx_phy(sc, desc, data); 2380 break; 2381 2382 case IWN_RX_DONE: /* 4965AGN only. */ 2383 case IWN_MPDU_RX_DONE: 2384 /* An 802.11 frame has been received. */ 2385 iwn_rx_done(sc, desc, data); 2386 break; 2387 #ifndef IEEE80211_NO_HT 2388 case IWN_RX_COMPRESSED_BA: 2389 /* A Compressed BlockAck has been received. */ 2390 iwn_rx_compressed_ba(sc, desc, data); 2391 break; 2392 #endif 2393 case IWN_TX_DONE: 2394 /* An 802.11 frame has been transmitted. */ 2395 sc->sc_hal->tx_done(sc, desc, data); 2396 break; 2397 2398 case IWN_RX_STATISTICS: 2399 case IWN_BEACON_STATISTICS: 2400 iwn_rx_statistics(sc, desc, data); 2401 break; 2402 2403 case IWN_BEACON_MISSED: 2404 { 2405 struct iwn_beacon_missed *miss = 2406 (struct iwn_beacon_missed *)(desc + 1); 2407 2408 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2409 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2410 /* 2411 * If more than 5 consecutive beacons are missed, 2412 * reinitialize the sensitivity state machine. 2413 */ 2414 DPRINTF(("beacons missed %d/%d\n", 2415 le32toh(miss->consecutive), le32toh(miss->total))); 2416 if (ic->ic_state == IEEE80211_S_RUN && 2417 le32toh(miss->consecutive) > 5) 2418 (void)iwn_init_sensitivity(sc); 2419 break; 2420 } 2421 case IWN_UC_READY: 2422 { 2423 struct iwn_ucode_info *uc = 2424 (struct iwn_ucode_info *)(desc + 1); 2425 2426 /* The microcontroller is ready. */ 2427 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2428 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2429 DPRINTF(("microcode alive notification version=%d.%d " 2430 "subtype=%x alive=%x\n", uc->major, uc->minor, 2431 uc->subtype, le32toh(uc->valid))); 2432 2433 if (le32toh(uc->valid) != 1) { 2434 aprint_error_dev(sc->sc_dev, 2435 "microcontroller initialization " 2436 "failed\n"); 2437 break; 2438 } 2439 if (uc->subtype == IWN_UCODE_INIT) { 2440 /* Save microcontroller report. */ 2441 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2442 } 2443 /* Save the address of the error log in SRAM. */ 2444 sc->errptr = le32toh(uc->errptr); 2445 break; 2446 } 2447 case IWN_STATE_CHANGED: 2448 { 2449 uint32_t *status = (uint32_t *)(desc + 1); 2450 2451 /* Enabled/disabled notification. */ 2452 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2453 sizeof (*status), BUS_DMASYNC_POSTREAD); 2454 DPRINTF(("state changed to %x\n", le32toh(*status))); 2455 2456 if (le32toh(*status) & 1) { 2457 /* The radio button has to be pushed. */ 2458 aprint_error_dev(sc->sc_dev, 2459 "Radio transmitter is off\n"); 2460 /* Turn the interface down. */ 2461 ifp->if_flags &= ~IFF_UP; 2462 iwn_stop(ifp, 1); 2463 return; /* No further processing. */ 2464 } 2465 break; 2466 } 2467 case IWN_START_SCAN: 2468 { 2469 struct iwn_start_scan *scan = 2470 (struct iwn_start_scan *)(desc + 1); 2471 2472 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2473 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2474 DPRINTFN(2, ("scanning channel %d status %x\n", 2475 scan->chan, le32toh(scan->status))); 2476 2477 /* Fix current channel. */ 2478 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2479 break; 2480 } 2481 case IWN_STOP_SCAN: 2482 { 2483 struct iwn_stop_scan *scan = 2484 (struct iwn_stop_scan *)(desc + 1); 2485 2486 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2487 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2488 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2489 scan->nchan, scan->status, scan->chan)); 2490 2491 if (scan->status == 1 && scan->chan <= 14 && 2492 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2493 /* 2494 * We just finished scanning 2GHz channels, 2495 * start scanning 5GHz ones. 2496 */ 2497 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2498 break; 2499 } 2500 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2501 ieee80211_end_scan(ic); 2502 break; 2503 } 2504 case IWN5000_CALIBRATION_RESULT: 2505 iwn5000_rx_calib_results(sc, desc, data); 2506 break; 2507 2508 case IWN5000_CALIBRATION_DONE: 2509 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2510 wakeup(sc); 2511 break; 2512 } 2513 2514 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2515 } 2516 2517 /* Tell the firmware what we have processed. */ 2518 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2519 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2520 } 2521 2522 /* 2523 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2524 * from power-down sleep mode. 2525 */ 2526 static void 2527 iwn_wakeup_intr(struct iwn_softc *sc) 2528 { 2529 int qid; 2530 2531 DPRINTF(("ucode wakeup from power-down sleep\n")); 2532 2533 /* Wakeup RX and TX rings. */ 2534 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2535 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2536 struct iwn_tx_ring *ring = &sc->txq[qid]; 2537 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2538 } 2539 } 2540 2541 /* 2542 * Dump the error log of the firmware when a firmware panic occurs. Although 2543 * we can't debug the firmware because it is neither open source nor free, it 2544 * can help us to identify certain classes of problems. 2545 */ 2546 static void 2547 iwn_fatal_intr(struct iwn_softc *sc) 2548 { 2549 const struct iwn_hal *hal = sc->sc_hal; 2550 struct iwn_fw_dump dump; 2551 int i; 2552 2553 /* Force a complete recalibration on next init. */ 2554 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2555 2556 /* Check that the error log address is valid. */ 2557 if (sc->errptr < IWN_FW_DATA_BASE || 2558 sc->errptr + sizeof (dump) > 2559 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2560 aprint_error_dev(sc->sc_dev, 2561 "bad firmware error log address 0x%08x\n", sc->errptr); 2562 return; 2563 } 2564 if (iwn_nic_lock(sc) != 0) { 2565 aprint_error_dev(sc->sc_dev, 2566 "could not read firmware error log\n"); 2567 return; 2568 } 2569 /* Read firmware error log from SRAM. */ 2570 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2571 sizeof (dump) / sizeof (uint32_t)); 2572 iwn_nic_unlock(sc); 2573 2574 if (dump.valid == 0) { 2575 aprint_error_dev(sc->sc_dev, 2576 "firmware error log is empty\n"); 2577 return; 2578 } 2579 aprint_error("firmware error log:\n"); 2580 aprint_error(" error type = \"%s\" (0x%08X)\n", 2581 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2582 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2583 dump.id); 2584 aprint_error(" program counter = 0x%08X\n", dump.pc); 2585 aprint_error(" source line = 0x%08X\n", dump.src_line); 2586 aprint_error(" error data = 0x%08X%08X\n", 2587 dump.error_data[0], dump.error_data[1]); 2588 aprint_error(" branch link = 0x%08X%08X\n", 2589 dump.branch_link[0], dump.branch_link[1]); 2590 aprint_error(" interrupt link = 0x%08X%08X\n", 2591 dump.interrupt_link[0], dump.interrupt_link[1]); 2592 aprint_error(" time = %u\n", dump.time[0]); 2593 2594 /* Dump driver status (TX and RX rings) while we're here. */ 2595 aprint_error("driver status:\n"); 2596 for (i = 0; i < hal->ntxqs; i++) { 2597 struct iwn_tx_ring *ring = &sc->txq[i]; 2598 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2599 i, ring->qid, ring->cur, ring->queued); 2600 } 2601 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2602 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2603 } 2604 2605 static int 2606 iwn_intr(void *arg) 2607 { 2608 struct iwn_softc *sc = arg; 2609 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2610 uint32_t r1, r2, tmp; 2611 2612 /* Disable interrupts. */ 2613 IWN_WRITE(sc, IWN_INT_MASK, 0); 2614 2615 /* Read interrupts from ICT (fast) or from registers (slow). */ 2616 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2617 tmp = 0; 2618 while (sc->ict[sc->ict_cur] != 0) { 2619 tmp |= sc->ict[sc->ict_cur]; 2620 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2621 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2622 } 2623 tmp = le32toh(tmp); 2624 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2625 tmp = 0; 2626 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2627 tmp |= 0x8000; 2628 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2629 r2 = 0; /* Unused. */ 2630 } else { 2631 r1 = IWN_READ(sc, IWN_INT); 2632 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2633 return 0; /* Hardware gone! */ 2634 r2 = IWN_READ(sc, IWN_FH_INT); 2635 } 2636 if (r1 == 0 && r2 == 0) { 2637 if (ifp->if_flags & IFF_UP) 2638 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2639 return 0; /* Interrupt not for us. */ 2640 } 2641 2642 /* Acknowledge interrupts. */ 2643 IWN_WRITE(sc, IWN_INT, r1); 2644 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2645 IWN_WRITE(sc, IWN_FH_INT, r2); 2646 2647 if (r1 & IWN_INT_RF_TOGGLED) { 2648 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2649 aprint_error_dev(sc->sc_dev, 2650 "RF switch: radio %s\n", 2651 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2652 } 2653 if (r1 & IWN_INT_CT_REACHED) { 2654 aprint_error_dev(sc->sc_dev, 2655 "critical temperature reached!\n"); 2656 } 2657 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2658 aprint_error_dev(sc->sc_dev, 2659 "fatal firmware error\n"); 2660 /* Dump firmware error log and stop. */ 2661 iwn_fatal_intr(sc); 2662 ifp->if_flags &= ~IFF_UP; 2663 iwn_stop(ifp, 1); 2664 return 1; 2665 } 2666 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2667 (r2 & IWN_FH_INT_RX)) { 2668 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2669 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2670 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2671 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2672 IWN_INT_PERIODIC_DIS); 2673 iwn_notif_intr(sc); 2674 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2675 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2676 IWN_INT_PERIODIC_ENA); 2677 } 2678 } else 2679 iwn_notif_intr(sc); 2680 } 2681 2682 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2683 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2684 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2685 wakeup(sc); /* FH DMA transfer completed. */ 2686 } 2687 2688 if (r1 & IWN_INT_ALIVE) 2689 wakeup(sc); /* Firmware is alive. */ 2690 2691 if (r1 & IWN_INT_WAKEUP) 2692 iwn_wakeup_intr(sc); 2693 2694 /* Re-enable interrupts. */ 2695 if (ifp->if_flags & IFF_UP) 2696 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2697 2698 return 1; 2699 } 2700 2701 /* 2702 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2703 * 5000 adapters use a slightly different format.) 2704 */ 2705 static void 2706 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2707 uint16_t len) 2708 { 2709 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2710 2711 *w = htole16(len + 8); 2712 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2713 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2714 sizeof (uint16_t), 2715 BUS_DMASYNC_PREWRITE); 2716 if (idx < IWN_SCHED_WINSZ) { 2717 *(w + IWN_TX_RING_COUNT) = *w; 2718 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2719 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2720 (char *)(void *)sc->sched_dma.vaddr, 2721 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2722 } 2723 } 2724 2725 static void 2726 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2727 uint16_t len) 2728 { 2729 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2730 2731 *w = htole16(id << 12 | (len + 8)); 2732 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2733 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2734 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2735 if (idx < IWN_SCHED_WINSZ) { 2736 *(w + IWN_TX_RING_COUNT) = *w; 2737 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2738 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2739 (char *)(void *)sc->sched_dma.vaddr, 2740 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2741 } 2742 } 2743 2744 #ifdef notyet 2745 static void 2746 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2747 { 2748 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2749 2750 *w = (*w & htole16(0xf000)) | htole16(1); 2751 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2752 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2753 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2754 if (idx < IWN_SCHED_WINSZ) { 2755 *(w + IWN_TX_RING_COUNT) = *w; 2756 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2757 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2758 (char *)(void *)sc->sched_dma.vaddr, 2759 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2760 } 2761 } 2762 #endif 2763 2764 static int 2765 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2766 { 2767 const struct iwn_hal *hal = sc->sc_hal; 2768 struct ieee80211com *ic = &sc->sc_ic; 2769 struct iwn_node *wn = (void *)ni; 2770 struct iwn_tx_ring *ring; 2771 struct iwn_tx_desc *desc; 2772 struct iwn_tx_data *data; 2773 struct iwn_tx_cmd *cmd; 2774 struct iwn_cmd_data *tx; 2775 const struct iwn_rate *rinfo; 2776 struct ieee80211_frame *wh; 2777 struct ieee80211_key *k = NULL; 2778 struct mbuf *m1; 2779 uint32_t flags; 2780 u_int hdrlen; 2781 bus_dma_segment_t *seg; 2782 uint8_t tid, ridx, txant, type; 2783 int i, totlen, error, pad; 2784 2785 const struct chanAccParams *cap; 2786 int noack; 2787 int hdrlen2; 2788 2789 wh = mtod(m, struct ieee80211_frame *); 2790 hdrlen = ieee80211_anyhdrsize(wh); 2791 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2792 2793 hdrlen2 = (IEEE80211_QOS_HAS_SEQ(wh)) ? 2794 sizeof (struct ieee80211_qosframe) : 2795 sizeof (struct ieee80211_frame); 2796 2797 if (hdrlen != hdrlen2) 2798 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2799 hdrlen, hdrlen2); 2800 2801 /* XXX OpenBSD sets a different tid when using QOS */ 2802 tid = 0; 2803 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2804 cap = &ic->ic_wme.wme_chanParams; 2805 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2806 } 2807 else 2808 noack = 0; 2809 2810 ring = &sc->txq[ac]; 2811 desc = &ring->desc[ring->cur]; 2812 data = &ring->data[ring->cur]; 2813 2814 /* Choose a TX rate index. */ 2815 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2816 type != IEEE80211_FC0_TYPE_DATA) { 2817 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2818 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2819 } else if (ic->ic_fixed_rate != -1) { 2820 ridx = sc->fixed_ridx; 2821 } else 2822 ridx = wn->ridx[ni->ni_txrate]; 2823 rinfo = &iwn_rates[ridx]; 2824 2825 /* Encrypt the frame if need be. */ 2826 /* 2827 * XXX For now, NetBSD swaps the encryption and bpf sections 2828 * in order to match old code and other drivers. Tests with 2829 * tcpdump indicates that the order is irrelevant, however, 2830 * as bpf produces unencrypted data for both ordering choices. 2831 */ 2832 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2833 k = ieee80211_crypto_encap(ic, ni, m); 2834 if (k == NULL) { 2835 m_freem(m); 2836 return ENOBUFS; 2837 } 2838 /* Packet header may have moved, reset our local pointer. */ 2839 wh = mtod(m, struct ieee80211_frame *); 2840 } 2841 totlen = m->m_pkthdr.len; 2842 2843 if (sc->sc_drvbpf != NULL) { 2844 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2845 2846 tap->wt_flags = 0; 2847 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2848 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2849 tap->wt_rate = rinfo->rate; 2850 tap->wt_hwqueue = ac; 2851 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2852 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2853 2854 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2855 } 2856 2857 /* Prepare TX firmware command. */ 2858 cmd = &ring->cmd[ring->cur]; 2859 cmd->code = IWN_CMD_TX_DATA; 2860 cmd->flags = 0; 2861 cmd->qid = ring->qid; 2862 cmd->idx = ring->cur; 2863 2864 tx = (struct iwn_cmd_data *)cmd->data; 2865 /* NB: No need to clear tx, all fields are reinitialized here. */ 2866 tx->scratch = 0; /* clear "scratch" area */ 2867 2868 flags = 0; 2869 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2870 /* Unicast frame, check if an ACK is expected. */ 2871 if (!noack) 2872 flags |= IWN_TX_NEED_ACK; 2873 } 2874 2875 #ifdef notyet 2876 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2877 if ((wh->i_fc[0] & 2878 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2879 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2880 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2881 #endif 2882 2883 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2884 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2885 2886 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2887 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2888 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2889 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2890 flags |= IWN_TX_NEED_RTS; 2891 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2892 ridx >= IWN_RIDX_OFDM6) { 2893 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2894 flags |= IWN_TX_NEED_CTS; 2895 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2896 flags |= IWN_TX_NEED_RTS; 2897 } 2898 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2899 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2900 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2901 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2902 flags |= IWN_TX_NEED_PROTECTION; 2903 } else 2904 flags |= IWN_TX_FULL_TXOP; 2905 } 2906 } 2907 2908 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2909 type != IEEE80211_FC0_TYPE_DATA) 2910 tx->id = hal->broadcast_id; 2911 else 2912 tx->id = wn->id; 2913 2914 if (type == IEEE80211_FC0_TYPE_MGT) { 2915 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2916 2917 #ifndef IEEE80211_STA_ONLY 2918 /* Tell HW to set timestamp in probe responses. */ 2919 /* XXX NetBSD rev 1.11 added probe requests here but */ 2920 /* probe requests do not take timestamps (from Bergamini). */ 2921 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2922 flags |= IWN_TX_INSERT_TSTAMP; 2923 #endif 2924 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2925 /* changes here. These are not needed (from Bergamini). */ 2926 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2927 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2928 tx->timeout = htole16(3); 2929 else 2930 tx->timeout = htole16(2); 2931 } else 2932 tx->timeout = htole16(0); 2933 2934 if (hdrlen & 3) { 2935 /* First segment's length must be a multiple of 4. */ 2936 flags |= IWN_TX_NEED_PADDING; 2937 pad = 4 - (hdrlen & 3); 2938 } else 2939 pad = 0; 2940 2941 tx->len = htole16(totlen); 2942 tx->tid = tid; 2943 tx->rts_ntries = 60; 2944 tx->data_ntries = 15; 2945 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2946 tx->plcp = rinfo->plcp; 2947 tx->rflags = rinfo->flags; 2948 if (tx->id == hal->broadcast_id) { 2949 /* Group or management frame. */ 2950 tx->linkq = 0; 2951 /* XXX Alternate between antenna A and B? */ 2952 txant = IWN_LSB(sc->txchainmask); 2953 tx->rflags |= IWN_RFLAG_ANT(txant); 2954 } else { 2955 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2956 flags |= IWN_TX_LINKQ; /* enable MRR */ 2957 } 2958 /* Set physical address of "scratch area". */ 2959 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2960 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2961 2962 /* Copy 802.11 header in TX command. */ 2963 /* XXX NetBSD changed this in rev 1.20 */ 2964 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2965 2966 /* Trim 802.11 header. */ 2967 m_adj(m, hdrlen); 2968 tx->security = 0; 2969 tx->flags = htole32(flags); 2970 2971 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2972 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2973 if (error != 0) { 2974 if (error != EFBIG) { 2975 aprint_error_dev(sc->sc_dev, 2976 "can't map mbuf (error %d)\n", error); 2977 m_freem(m); 2978 return error; 2979 } 2980 /* Too many DMA segments, linearize mbuf. */ 2981 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2982 if (m1 == NULL) { 2983 m_freem(m); 2984 return ENOBUFS; 2985 } 2986 if (m->m_pkthdr.len > MHLEN) { 2987 MCLGET(m1, M_DONTWAIT); 2988 if (!(m1->m_flags & M_EXT)) { 2989 m_freem(m); 2990 m_freem(m1); 2991 return ENOBUFS; 2992 } 2993 } 2994 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2995 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2996 m_freem(m); 2997 m = m1; 2998 2999 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3000 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3001 if (error != 0) { 3002 aprint_error_dev(sc->sc_dev, 3003 "can't map mbuf (error %d)\n", error); 3004 m_freem(m); 3005 return error; 3006 } 3007 } 3008 3009 data->m = m; 3010 data->ni = ni; 3011 3012 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3013 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3014 3015 /* Fill TX descriptor. */ 3016 desc->nsegs = 1 + data->map->dm_nsegs; 3017 /* First DMA segment is used by the TX command. */ 3018 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3019 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3020 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3021 /* Other DMA segments are for data payload. */ 3022 seg = data->map->dm_segs; 3023 for (i = 1; i <= data->map->dm_nsegs; i++) { 3024 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3025 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3026 seg->ds_len << 4); 3027 seg++; 3028 } 3029 3030 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3031 BUS_DMASYNC_PREWRITE); 3032 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3033 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3034 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3035 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3036 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3037 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3038 3039 #ifdef notyet 3040 /* Update TX scheduler. */ 3041 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3042 #endif 3043 3044 /* Kick TX ring. */ 3045 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3046 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3047 3048 /* Mark TX ring as full if we reach a certain threshold. */ 3049 if (++ring->queued > IWN_TX_RING_HIMARK) 3050 sc->qfullmsk |= 1 << ring->qid; 3051 3052 return 0; 3053 } 3054 3055 static void 3056 iwn_start(struct ifnet *ifp) 3057 { 3058 struct iwn_softc *sc = ifp->if_softc; 3059 struct ieee80211com *ic = &sc->sc_ic; 3060 struct ieee80211_node *ni; 3061 struct ether_header *eh; 3062 struct mbuf *m; 3063 int ac; 3064 3065 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3066 return; 3067 3068 for (;;) { 3069 if (sc->qfullmsk != 0) { 3070 ifp->if_flags |= IFF_OACTIVE; 3071 break; 3072 } 3073 /* Send pending management frames first. */ 3074 IF_DEQUEUE(&ic->ic_mgtq, m); 3075 if (m != NULL) { 3076 ni = (void *)m->m_pkthdr.rcvif; 3077 ac = 0; 3078 goto sendit; 3079 } 3080 if (ic->ic_state != IEEE80211_S_RUN) 3081 break; 3082 3083 /* Encapsulate and send data frames. */ 3084 IFQ_DEQUEUE(&ifp->if_snd, m); 3085 if (m == NULL) 3086 break; 3087 if (m->m_len < sizeof (*eh) && 3088 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3089 ifp->if_oerrors++; 3090 continue; 3091 } 3092 eh = mtod(m, struct ether_header *); 3093 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3094 if (ni == NULL) { 3095 m_freem(m); 3096 ifp->if_oerrors++; 3097 continue; 3098 } 3099 /* classify mbuf so we can find which tx ring to use */ 3100 if (ieee80211_classify(ic, m, ni) != 0) { 3101 m_freem(m); 3102 ieee80211_free_node(ni); 3103 ifp->if_oerrors++; 3104 continue; 3105 } 3106 3107 /* No QoS encapsulation for EAPOL frames. */ 3108 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3109 M_WME_GETAC(m) : WME_AC_BE; 3110 3111 bpf_mtap(ifp, m); 3112 3113 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3114 ieee80211_free_node(ni); 3115 ifp->if_oerrors++; 3116 continue; 3117 } 3118 sendit: 3119 bpf_mtap3(ic->ic_rawbpf, m); 3120 3121 if (iwn_tx(sc, m, ni, ac) != 0) { 3122 ieee80211_free_node(ni); 3123 ifp->if_oerrors++; 3124 continue; 3125 } 3126 3127 sc->sc_tx_timer = 5; 3128 ifp->if_timer = 1; 3129 } 3130 } 3131 3132 static void 3133 iwn_watchdog(struct ifnet *ifp) 3134 { 3135 struct iwn_softc *sc = ifp->if_softc; 3136 3137 ifp->if_timer = 0; 3138 3139 if (sc->sc_tx_timer > 0) { 3140 if (--sc->sc_tx_timer == 0) { 3141 aprint_error_dev(sc->sc_dev, 3142 "device timeout\n"); 3143 ifp->if_flags &= ~IFF_UP; 3144 iwn_stop(ifp, 1); 3145 ifp->if_oerrors++; 3146 return; 3147 } 3148 ifp->if_timer = 1; 3149 } 3150 3151 ieee80211_watchdog(&sc->sc_ic); 3152 } 3153 3154 static int 3155 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3156 { 3157 struct iwn_softc *sc = ifp->if_softc; 3158 struct ieee80211com *ic = &sc->sc_ic; 3159 struct ifaddr *ifa; 3160 const struct sockaddr *sa; 3161 int s, error = 0; 3162 3163 s = splnet(); 3164 /* 3165 * Prevent processes from entering this function while another 3166 * process is tsleep'ing in it. 3167 */ 3168 if (sc->sc_flags & IWN_FLAG_BUSY) { 3169 switch (cmd) { 3170 case SIOCSIFADDR: 3171 /* FALLTHROUGH */ 3172 case SIOCSIFFLAGS: 3173 splx(s); 3174 aprint_normal_dev(sc->sc_dev, 3175 "ioctl while busy cmd = 0x%lx\n", cmd); 3176 return EBUSY; 3177 } 3178 } 3179 sc->sc_flags |= IWN_FLAG_BUSY; 3180 3181 switch (cmd) { 3182 case SIOCSIFADDR: 3183 ifa = (struct ifaddr *)data; 3184 ifp->if_flags |= IFF_UP; 3185 #ifdef INET 3186 if (ifa->ifa_addr->sa_family == AF_INET) 3187 arp_ifinit(&ic->ic_ac, ifa); 3188 #endif 3189 /* FALLTHROUGH */ 3190 case SIOCSIFFLAGS: 3191 /* XXX Added as it is in every NetBSD driver */ 3192 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3193 break; 3194 if (ifp->if_flags & IFF_UP) { 3195 if (!(ifp->if_flags & IFF_RUNNING)) 3196 error = iwn_init(ifp); 3197 } else { 3198 if (ifp->if_flags & IFF_RUNNING) 3199 iwn_stop(ifp, 1); 3200 } 3201 break; 3202 3203 case SIOCADDMULTI: 3204 case SIOCDELMULTI: 3205 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3206 error = (cmd == SIOCADDMULTI) ? 3207 ether_addmulti(sa, &sc->sc_ec) : 3208 ether_delmulti(sa, &sc->sc_ec); 3209 3210 if (error == ENETRESET) 3211 error = 0; 3212 break; 3213 3214 default: 3215 error = ieee80211_ioctl(ic, cmd, data); 3216 } 3217 3218 if (error == ENETRESET) { 3219 error = 0; 3220 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3221 (IFF_UP | IFF_RUNNING)) { 3222 iwn_stop(ifp, 0); 3223 error = iwn_init(ifp); 3224 } 3225 } 3226 3227 sc->sc_flags &= ~IWN_FLAG_BUSY; 3228 splx(s); 3229 return error; 3230 } 3231 3232 /* 3233 * Send a command to the firmware. 3234 */ 3235 static int 3236 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3237 { 3238 struct iwn_tx_ring *ring = &sc->txq[4]; 3239 struct iwn_tx_desc *desc; 3240 struct iwn_tx_data *data; 3241 struct iwn_tx_cmd *cmd; 3242 struct mbuf *m; 3243 bus_addr_t paddr; 3244 int totlen, error; 3245 3246 desc = &ring->desc[ring->cur]; 3247 data = &ring->data[ring->cur]; 3248 totlen = 4 + size; 3249 3250 if (size > sizeof cmd->data) { 3251 /* Command is too large to fit in a descriptor. */ 3252 if (totlen > MCLBYTES) 3253 return EINVAL; 3254 MGETHDR(m, M_DONTWAIT, MT_DATA); 3255 if (m == NULL) 3256 return ENOMEM; 3257 if (totlen > MHLEN) { 3258 MCLGET(m, M_DONTWAIT); 3259 if (!(m->m_flags & M_EXT)) { 3260 m_freem(m); 3261 return ENOMEM; 3262 } 3263 } 3264 cmd = mtod(m, struct iwn_tx_cmd *); 3265 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3266 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3267 if (error != 0) { 3268 m_freem(m); 3269 return error; 3270 } 3271 data->m = m; 3272 paddr = data->map->dm_segs[0].ds_addr; 3273 } else { 3274 cmd = &ring->cmd[ring->cur]; 3275 paddr = data->cmd_paddr; 3276 } 3277 3278 cmd->code = code; 3279 cmd->flags = 0; 3280 cmd->qid = ring->qid; 3281 cmd->idx = ring->cur; 3282 memcpy(cmd->data, buf, size); 3283 3284 desc->nsegs = 1; 3285 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3286 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3287 3288 if (size > sizeof cmd->data) { 3289 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3290 BUS_DMASYNC_PREWRITE); 3291 } else { 3292 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3293 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3294 totlen, BUS_DMASYNC_PREWRITE); 3295 } 3296 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3297 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3298 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3299 3300 #ifdef notyet 3301 /* Update TX scheduler. */ 3302 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3303 #endif 3304 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3305 3306 /* Kick command ring. */ 3307 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3308 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3309 3310 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3311 } 3312 3313 static int 3314 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3315 { 3316 struct iwn4965_node_info hnode; 3317 char *src, *dst; 3318 3319 /* 3320 * We use the node structure for 5000 Series internally (it is 3321 * a superset of the one for 4965AGN). We thus copy the common 3322 * fields before sending the command. 3323 */ 3324 src = (char *)node; 3325 dst = (char *)&hnode; 3326 memcpy(dst, src, 48); 3327 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3328 memcpy(dst + 48, src + 72, 20); 3329 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3330 } 3331 3332 static int 3333 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3334 { 3335 /* Direct mapping. */ 3336 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3337 } 3338 3339 static int 3340 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3341 { 3342 struct iwn_node *wn = (void *)ni; 3343 struct ieee80211_rateset *rs = &ni->ni_rates; 3344 struct iwn_cmd_link_quality linkq; 3345 const struct iwn_rate *rinfo; 3346 uint8_t txant; 3347 int i, txrate; 3348 3349 /* Use the first valid TX antenna. */ 3350 txant = IWN_LSB(sc->txchainmask); 3351 3352 memset(&linkq, 0, sizeof linkq); 3353 linkq.id = wn->id; 3354 linkq.antmsk_1stream = txant; 3355 linkq.antmsk_2stream = IWN_ANT_AB; 3356 linkq.ampdu_max = 31; 3357 linkq.ampdu_threshold = 3; 3358 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3359 3360 /* Start at highest available bit-rate. */ 3361 txrate = rs->rs_nrates - 1; 3362 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3363 rinfo = &iwn_rates[wn->ridx[txrate]]; 3364 linkq.retry[i].plcp = rinfo->plcp; 3365 linkq.retry[i].rflags = rinfo->flags; 3366 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3367 /* Next retry at immediate lower bit-rate. */ 3368 if (txrate > 0) 3369 txrate--; 3370 } 3371 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3372 } 3373 3374 /* 3375 * Broadcast node is used to send group-addressed and management frames. 3376 */ 3377 static int 3378 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3379 { 3380 const struct iwn_hal *hal = sc->sc_hal; 3381 struct iwn_node_info node; 3382 struct iwn_cmd_link_quality linkq; 3383 const struct iwn_rate *rinfo; 3384 uint8_t txant; 3385 int i, error; 3386 3387 memset(&node, 0, sizeof node); 3388 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3389 node.id = hal->broadcast_id; 3390 DPRINTF(("adding broadcast node\n")); 3391 if ((error = hal->add_node(sc, &node, async)) != 0) 3392 return error; 3393 3394 /* Use the first valid TX antenna. */ 3395 txant = IWN_LSB(sc->txchainmask); 3396 3397 memset(&linkq, 0, sizeof linkq); 3398 linkq.id = hal->broadcast_id; 3399 linkq.antmsk_1stream = txant; 3400 linkq.antmsk_2stream = IWN_ANT_AB; 3401 linkq.ampdu_max = 64; 3402 linkq.ampdu_threshold = 3; 3403 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3404 3405 /* Use lowest mandatory bit-rate. */ 3406 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3407 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3408 linkq.retry[0].plcp = rinfo->plcp; 3409 linkq.retry[0].rflags = rinfo->flags; 3410 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3411 /* Use same bit-rate for all TX retries. */ 3412 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3413 linkq.retry[i].plcp = linkq.retry[0].plcp; 3414 linkq.retry[i].rflags = linkq.retry[0].rflags; 3415 } 3416 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3417 } 3418 3419 static void 3420 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3421 { 3422 struct iwn_cmd_led led; 3423 3424 /* Clear microcode LED ownership. */ 3425 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3426 3427 led.which = which; 3428 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3429 led.off = off; 3430 led.on = on; 3431 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3432 } 3433 3434 /* 3435 * Set the critical temperature at which the firmware will stop the radio 3436 * and notify us. 3437 */ 3438 static int 3439 iwn_set_critical_temp(struct iwn_softc *sc) 3440 { 3441 struct iwn_critical_temp crit; 3442 int32_t temp; 3443 3444 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3445 3446 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3447 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3448 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3449 temp = IWN_CTOK(110); 3450 else 3451 temp = 110; 3452 memset(&crit, 0, sizeof crit); 3453 crit.tempR = htole32(temp); 3454 DPRINTF(("setting critical temperature to %d\n", temp)); 3455 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3456 } 3457 3458 static int 3459 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3460 { 3461 struct iwn_cmd_timing cmd; 3462 uint64_t val, mod; 3463 3464 memset(&cmd, 0, sizeof cmd); 3465 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3466 cmd.bintval = htole16(ni->ni_intval); 3467 cmd.lintval = htole16(10); 3468 3469 /* Compute remaining time until next beacon. */ 3470 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3471 mod = le64toh(cmd.tstamp) % val; 3472 cmd.binitval = htole32((uint32_t)(val - mod)); 3473 3474 DPRINTF(("timing bintval=%u, tstamp=%zu, init=%u\n", 3475 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3476 3477 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3478 } 3479 3480 static void 3481 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3482 { 3483 /* Adjust TX power if need be (delta >= 3 degC.) */ 3484 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3485 if (abs(temp - sc->temp) >= 3) { 3486 /* Record temperature of last calibration. */ 3487 sc->temp = temp; 3488 (void)iwn4965_set_txpower(sc, 1); 3489 } 3490 } 3491 3492 /* 3493 * Set TX power for current channel (each rate has its own power settings). 3494 * This function takes into account the regulatory information from EEPROM, 3495 * the current temperature and the current voltage. 3496 */ 3497 static int 3498 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3499 { 3500 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3501 #define fdivround(a, b, n) \ 3502 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3503 /* Linear interpolation. */ 3504 #define interpolate(x, x1, y1, x2, y2, n) \ 3505 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3506 3507 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3508 struct ieee80211com *ic = &sc->sc_ic; 3509 struct iwn_ucode_info *uc = &sc->ucode_info; 3510 struct ieee80211_channel *ch; 3511 struct iwn4965_cmd_txpower cmd; 3512 struct iwn4965_eeprom_chan_samples *chans; 3513 const uint8_t *rf_gain, *dsp_gain; 3514 int32_t vdiff, tdiff; 3515 int i, c, grp, maxpwr; 3516 uint8_t chan; 3517 3518 /* Retrieve current channel from last RXON. */ 3519 chan = sc->rxon.chan; 3520 DPRINTF(("setting TX power for channel %d\n", chan)); 3521 ch = &ic->ic_channels[chan]; 3522 3523 memset(&cmd, 0, sizeof cmd); 3524 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3525 cmd.chan = chan; 3526 3527 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3528 maxpwr = sc->maxpwr5GHz; 3529 rf_gain = iwn4965_rf_gain_5ghz; 3530 dsp_gain = iwn4965_dsp_gain_5ghz; 3531 } else { 3532 maxpwr = sc->maxpwr2GHz; 3533 rf_gain = iwn4965_rf_gain_2ghz; 3534 dsp_gain = iwn4965_dsp_gain_2ghz; 3535 } 3536 3537 /* Compute voltage compensation. */ 3538 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3539 if (vdiff > 0) 3540 vdiff *= 2; 3541 if (abs(vdiff) > 2) 3542 vdiff = 0; 3543 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3544 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3545 3546 /* Get channel attenuation group. */ 3547 if (chan <= 20) /* 1-20 */ 3548 grp = 4; 3549 else if (chan <= 43) /* 34-43 */ 3550 grp = 0; 3551 else if (chan <= 70) /* 44-70 */ 3552 grp = 1; 3553 else if (chan <= 124) /* 71-124 */ 3554 grp = 2; 3555 else /* 125-200 */ 3556 grp = 3; 3557 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3558 3559 /* Get channel sub-band. */ 3560 for (i = 0; i < IWN_NBANDS; i++) 3561 if (sc->bands[i].lo != 0 && 3562 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3563 break; 3564 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3565 return EINVAL; 3566 chans = sc->bands[i].chans; 3567 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3568 3569 for (c = 0; c < 2; c++) { 3570 uint8_t power, gain, temp; 3571 int maxchpwr, pwr, ridx, idx; 3572 3573 power = interpolate(chan, 3574 chans[0].num, chans[0].samples[c][1].power, 3575 chans[1].num, chans[1].samples[c][1].power, 1); 3576 gain = interpolate(chan, 3577 chans[0].num, chans[0].samples[c][1].gain, 3578 chans[1].num, chans[1].samples[c][1].gain, 1); 3579 temp = interpolate(chan, 3580 chans[0].num, chans[0].samples[c][1].temp, 3581 chans[1].num, chans[1].samples[c][1].temp, 1); 3582 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3583 c, power, gain, temp)); 3584 3585 /* Compute temperature compensation. */ 3586 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3587 DPRINTF(("temperature compensation=%d (current=%d, " 3588 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3589 3590 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3591 /* Convert dBm to half-dBm. */ 3592 maxchpwr = sc->maxpwr[chan] * 2; 3593 if ((ridx / 8) & 1) 3594 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3595 3596 pwr = maxpwr; 3597 3598 /* Adjust TX power based on rate. */ 3599 if ((ridx % 8) == 5) 3600 pwr -= 15; /* OFDM48: -7.5dB */ 3601 else if ((ridx % 8) == 6) 3602 pwr -= 17; /* OFDM54: -8.5dB */ 3603 else if ((ridx % 8) == 7) 3604 pwr -= 20; /* OFDM60: -10dB */ 3605 else 3606 pwr -= 10; /* Others: -5dB */ 3607 3608 /* Do not exceed channel max TX power. */ 3609 if (pwr > maxchpwr) 3610 pwr = maxchpwr; 3611 3612 idx = gain - (pwr - power) - tdiff - vdiff; 3613 if ((ridx / 8) & 1) /* MIMO */ 3614 idx += (int32_t)le32toh(uc->atten[grp][c]); 3615 3616 if (cmd.band == 0) 3617 idx += 9; /* 5GHz */ 3618 if (ridx == IWN_RIDX_MAX) 3619 idx += 5; /* CCK */ 3620 3621 /* Make sure idx stays in a valid range. */ 3622 if (idx < 0) 3623 idx = 0; 3624 else if (idx > IWN4965_MAX_PWR_INDEX) 3625 idx = IWN4965_MAX_PWR_INDEX; 3626 3627 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3628 c, ridx, idx)); 3629 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3630 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3631 } 3632 } 3633 3634 DPRINTF(("setting TX power for chan %d\n", chan)); 3635 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3636 3637 #undef interpolate 3638 #undef fdivround 3639 } 3640 3641 static int 3642 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3643 { 3644 struct iwn5000_cmd_txpower cmd; 3645 3646 /* 3647 * TX power calibration is handled automatically by the firmware 3648 * for 5000 Series. 3649 */ 3650 memset(&cmd, 0, sizeof cmd); 3651 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3652 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3653 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3654 DPRINTF(("setting TX power\n")); 3655 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3656 } 3657 3658 /* 3659 * Retrieve the maximum RSSI (in dBm) among receivers. 3660 */ 3661 static int 3662 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3663 { 3664 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3665 uint8_t mask, agc; 3666 int rssi; 3667 3668 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3669 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3670 3671 rssi = 0; 3672 if (mask & IWN_ANT_A) 3673 rssi = MAX(rssi, phy->rssi[0]); 3674 if (mask & IWN_ANT_B) 3675 rssi = MAX(rssi, phy->rssi[2]); 3676 if (mask & IWN_ANT_C) 3677 rssi = MAX(rssi, phy->rssi[4]); 3678 3679 return rssi - agc - IWN_RSSI_TO_DBM; 3680 } 3681 3682 static int 3683 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3684 { 3685 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3686 uint8_t agc; 3687 int rssi; 3688 3689 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3690 3691 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3692 le16toh(phy->rssi[1]) & 0xff); 3693 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3694 3695 return rssi - agc - IWN_RSSI_TO_DBM; 3696 } 3697 3698 /* 3699 * Retrieve the average noise (in dBm) among receivers. 3700 */ 3701 static int 3702 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3703 { 3704 int i, total, nbant, noise; 3705 3706 total = nbant = 0; 3707 for (i = 0; i < 3; i++) { 3708 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3709 continue; 3710 total += noise; 3711 nbant++; 3712 } 3713 /* There should be at least one antenna but check anyway. */ 3714 return (nbant == 0) ? -127 : (total / nbant) - 107; 3715 } 3716 3717 /* 3718 * Compute temperature (in degC) from last received statistics. 3719 */ 3720 static int 3721 iwn4965_get_temperature(struct iwn_softc *sc) 3722 { 3723 struct iwn_ucode_info *uc = &sc->ucode_info; 3724 int32_t r1, r2, r3, r4, temp; 3725 3726 r1 = le32toh(uc->temp[0].chan20MHz); 3727 r2 = le32toh(uc->temp[1].chan20MHz); 3728 r3 = le32toh(uc->temp[2].chan20MHz); 3729 r4 = le32toh(sc->rawtemp); 3730 3731 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 3732 return 0; 3733 3734 /* Sign-extend 23-bit R4 value to 32-bit. */ 3735 r4 = (r4 << 8) >> 8; 3736 /* Compute temperature in Kelvin. */ 3737 temp = (259 * (r4 - r2)) / (r3 - r1); 3738 temp = (temp * 97) / 100 + 8; 3739 3740 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3741 return IWN_KTOC(temp); 3742 } 3743 3744 static int 3745 iwn5000_get_temperature(struct iwn_softc *sc) 3746 { 3747 int32_t temp; 3748 3749 /* 3750 * Temperature is not used by the driver for 5000 Series because 3751 * TX power calibration is handled by firmware. We export it to 3752 * users through the sensor framework though. 3753 */ 3754 temp = le32toh(sc->rawtemp); 3755 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3756 temp = (temp / -5) + sc->temp_off; 3757 temp = IWN_KTOC(temp); 3758 } 3759 return temp; 3760 } 3761 3762 /* 3763 * Initialize sensitivity calibration state machine. 3764 */ 3765 static int 3766 iwn_init_sensitivity(struct iwn_softc *sc) 3767 { 3768 const struct iwn_hal *hal = sc->sc_hal; 3769 struct iwn_calib_state *calib = &sc->calib; 3770 uint32_t flags; 3771 int error; 3772 3773 /* Reset calibration state machine. */ 3774 memset(calib, 0, sizeof (*calib)); 3775 calib->state = IWN_CALIB_STATE_INIT; 3776 calib->cck_state = IWN_CCK_STATE_HIFA; 3777 /* Set initial correlation values. */ 3778 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3779 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3780 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3781 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3782 calib->cck_x4 = 125; 3783 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3784 calib->energy_cck = sc->limits->energy_cck; 3785 3786 /* Write initial sensitivity. */ 3787 if ((error = iwn_send_sensitivity(sc)) != 0) 3788 return error; 3789 3790 /* Write initial gains. */ 3791 if ((error = hal->init_gains(sc)) != 0) 3792 return error; 3793 3794 /* Request statistics at each beacon interval. */ 3795 flags = 0; 3796 DPRINTF(("sending request for statistics\n")); 3797 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3798 } 3799 3800 /* 3801 * Collect noise and RSSI statistics for the first 20 beacons received 3802 * after association and use them to determine connected antennas and 3803 * to set differential gains. 3804 */ 3805 static void 3806 iwn_collect_noise(struct iwn_softc *sc, 3807 const struct iwn_rx_general_stats *stats) 3808 { 3809 const struct iwn_hal *hal = sc->sc_hal; 3810 struct iwn_calib_state *calib = &sc->calib; 3811 uint32_t val; 3812 int i; 3813 3814 /* Accumulate RSSI and noise for all 3 antennas. */ 3815 for (i = 0; i < 3; i++) { 3816 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3817 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3818 } 3819 /* NB: We update differential gains only once after 20 beacons. */ 3820 if (++calib->nbeacons < 20) 3821 return; 3822 3823 /* Determine highest average RSSI. */ 3824 val = MAX(calib->rssi[0], calib->rssi[1]); 3825 val = MAX(calib->rssi[2], val); 3826 3827 /* Determine which antennas are connected. */ 3828 sc->chainmask = sc->rxchainmask; 3829 for (i = 0; i < 3; i++) 3830 if (val - calib->rssi[i] > 15 * 20) 3831 sc->chainmask &= ~(1 << i); 3832 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3833 sc->rxchainmask, sc->chainmask)); 3834 3835 /* If none of the TX antennas are connected, keep at least one. */ 3836 if ((sc->chainmask & sc->txchainmask) == 0) 3837 sc->chainmask |= IWN_LSB(sc->txchainmask); 3838 3839 (void)hal->set_gains(sc); 3840 calib->state = IWN_CALIB_STATE_RUN; 3841 3842 #ifdef notyet 3843 /* XXX Disable RX chains with no antennas connected. */ 3844 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3845 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 3846 #endif 3847 3848 /* Enable power-saving mode if requested by user. */ 3849 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3850 (void)iwn_set_pslevel(sc, 0, 3, 1); 3851 } 3852 3853 static int 3854 iwn4965_init_gains(struct iwn_softc *sc) 3855 { 3856 struct iwn_phy_calib_gain cmd; 3857 3858 memset(&cmd, 0, sizeof cmd); 3859 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3860 /* Differential gains initially set to 0 for all 3 antennas. */ 3861 DPRINTF(("setting initial differential gains\n")); 3862 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3863 } 3864 3865 static int 3866 iwn5000_init_gains(struct iwn_softc *sc) 3867 { 3868 struct iwn_phy_calib cmd; 3869 3870 memset(&cmd, 0, sizeof cmd); 3871 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3872 cmd.ngroups = 1; 3873 cmd.isvalid = 1; 3874 DPRINTF(("setting initial differential gains\n")); 3875 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3876 } 3877 3878 static int 3879 iwn4965_set_gains(struct iwn_softc *sc) 3880 { 3881 struct iwn_calib_state *calib = &sc->calib; 3882 struct iwn_phy_calib_gain cmd; 3883 int i, delta, noise; 3884 3885 /* Get minimal noise among connected antennas. */ 3886 noise = INT_MAX; /* NB: There's at least one antenna. */ 3887 for (i = 0; i < 3; i++) 3888 if (sc->chainmask & (1 << i)) 3889 noise = MIN(calib->noise[i], noise); 3890 3891 memset(&cmd, 0, sizeof cmd); 3892 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3893 /* Set differential gains for connected antennas. */ 3894 for (i = 0; i < 3; i++) { 3895 if (sc->chainmask & (1 << i)) { 3896 /* Compute attenuation (in unit of 1.5dB). */ 3897 delta = (noise - (int32_t)calib->noise[i]) / 30; 3898 /* NB: delta <= 0 */ 3899 /* Limit to [-4.5dB,0]. */ 3900 cmd.gain[i] = MIN(abs(delta), 3); 3901 if (delta < 0) 3902 cmd.gain[i] |= 1 << 2; /* sign bit */ 3903 } 3904 } 3905 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3906 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3907 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3908 } 3909 3910 static int 3911 iwn5000_set_gains(struct iwn_softc *sc) 3912 { 3913 struct iwn_calib_state *calib = &sc->calib; 3914 struct iwn_phy_calib_gain cmd; 3915 int i, ant, div, delta; 3916 3917 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3918 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3919 3920 memset(&cmd, 0, sizeof cmd); 3921 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3922 cmd.ngroups = 1; 3923 cmd.isvalid = 1; 3924 /* Get first available RX antenna as referential. */ 3925 ant = IWN_LSB(sc->rxchainmask); 3926 /* Set differential gains for other antennas. */ 3927 for (i = ant + 1; i < 3; i++) { 3928 if (sc->chainmask & (1 << i)) { 3929 /* The delta is relative to antenna "ant". */ 3930 delta = ((int32_t)calib->noise[ant] - 3931 (int32_t)calib->noise[i]) / div; 3932 /* Limit to [-4.5dB,+4.5dB]. */ 3933 cmd.gain[i - 1] = MIN(abs(delta), 3); 3934 if (delta < 0) 3935 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3936 } 3937 } 3938 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3939 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3940 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3941 } 3942 3943 /* 3944 * Tune RF RX sensitivity based on the number of false alarms detected 3945 * during the last beacon period. 3946 */ 3947 static void 3948 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3949 { 3950 #define inc(val, inc, max) \ 3951 if ((val) < (max)) { \ 3952 if ((val) < (max) - (inc)) \ 3953 (val) += (inc); \ 3954 else \ 3955 (val) = (max); \ 3956 needs_update = 1; \ 3957 } 3958 #define dec(val, dec, min) \ 3959 if ((val) > (min)) { \ 3960 if ((val) > (min) + (dec)) \ 3961 (val) -= (dec); \ 3962 else \ 3963 (val) = (min); \ 3964 needs_update = 1; \ 3965 } 3966 3967 const struct iwn_sensitivity_limits *limits = sc->limits; 3968 struct iwn_calib_state *calib = &sc->calib; 3969 uint32_t val, rxena, fa; 3970 uint32_t energy[3], energy_min; 3971 uint8_t noise[3], noise_ref; 3972 int i, needs_update = 0; 3973 3974 /* Check that we've been enabled long enough. */ 3975 if ((rxena = le32toh(stats->general.load)) == 0) 3976 return; 3977 3978 /* Compute number of false alarms since last call for OFDM. */ 3979 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3980 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3981 fa *= 200 * 1024; /* 200TU */ 3982 3983 /* Save counters values for next call. */ 3984 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3985 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3986 3987 if (fa > 50 * rxena) { 3988 /* High false alarm count, decrease sensitivity. */ 3989 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3990 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3991 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3992 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3993 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3994 3995 } else if (fa < 5 * rxena) { 3996 /* Low false alarm count, increase sensitivity. */ 3997 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3998 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3999 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4000 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4001 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4002 } 4003 4004 /* Compute maximum noise among 3 receivers. */ 4005 for (i = 0; i < 3; i++) 4006 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4007 val = MAX(noise[0], noise[1]); 4008 val = MAX(noise[2], val); 4009 /* Insert it into our samples table. */ 4010 calib->noise_samples[calib->cur_noise_sample] = val; 4011 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4012 4013 /* Compute maximum noise among last 20 samples. */ 4014 noise_ref = calib->noise_samples[0]; 4015 for (i = 1; i < 20; i++) 4016 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4017 4018 /* Compute maximum energy among 3 receivers. */ 4019 for (i = 0; i < 3; i++) 4020 energy[i] = le32toh(stats->general.energy[i]); 4021 val = MIN(energy[0], energy[1]); 4022 val = MIN(energy[2], val); 4023 /* Insert it into our samples table. */ 4024 calib->energy_samples[calib->cur_energy_sample] = val; 4025 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4026 4027 /* Compute minimum energy among last 10 samples. */ 4028 energy_min = calib->energy_samples[0]; 4029 for (i = 1; i < 10; i++) 4030 energy_min = MAX(energy_min, calib->energy_samples[i]); 4031 energy_min += 6; 4032 4033 /* Compute number of false alarms since last call for CCK. */ 4034 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4035 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4036 fa *= 200 * 1024; /* 200TU */ 4037 4038 /* Save counters values for next call. */ 4039 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4040 calib->fa_cck = le32toh(stats->cck.fa); 4041 4042 if (fa > 50 * rxena) { 4043 /* High false alarm count, decrease sensitivity. */ 4044 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4045 calib->cck_state = IWN_CCK_STATE_HIFA; 4046 calib->low_fa = 0; 4047 4048 if (calib->cck_x4 > 160) { 4049 calib->noise_ref = noise_ref; 4050 if (calib->energy_cck > 2) 4051 dec(calib->energy_cck, 2, energy_min); 4052 } 4053 if (calib->cck_x4 < 160) { 4054 calib->cck_x4 = 161; 4055 needs_update = 1; 4056 } else 4057 inc(calib->cck_x4, 3, limits->max_cck_x4); 4058 4059 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4060 4061 } else if (fa < 5 * rxena) { 4062 /* Low false alarm count, increase sensitivity. */ 4063 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4064 calib->cck_state = IWN_CCK_STATE_LOFA; 4065 calib->low_fa++; 4066 4067 if (calib->cck_state != IWN_CCK_STATE_INIT && 4068 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4069 calib->low_fa > 100)) { 4070 inc(calib->energy_cck, 2, limits->min_energy_cck); 4071 dec(calib->cck_x4, 3, limits->min_cck_x4); 4072 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4073 } 4074 } else { 4075 /* Not worth to increase or decrease sensitivity. */ 4076 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4077 calib->low_fa = 0; 4078 calib->noise_ref = noise_ref; 4079 4080 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4081 /* Previous interval had many false alarms. */ 4082 dec(calib->energy_cck, 8, energy_min); 4083 } 4084 calib->cck_state = IWN_CCK_STATE_INIT; 4085 } 4086 4087 if (needs_update) 4088 (void)iwn_send_sensitivity(sc); 4089 #undef dec 4090 #undef inc 4091 } 4092 4093 static int 4094 iwn_send_sensitivity(struct iwn_softc *sc) 4095 { 4096 struct iwn_calib_state *calib = &sc->calib; 4097 struct iwn_sensitivity_cmd cmd; 4098 4099 memset(&cmd, 0, sizeof cmd); 4100 cmd.which = IWN_SENSITIVITY_WORKTBL; 4101 /* OFDM modulation. */ 4102 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4103 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4104 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4105 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4106 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4107 cmd.energy_ofdm_th = htole16(62); 4108 /* CCK modulation. */ 4109 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4110 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4111 cmd.energy_cck = htole16(calib->energy_cck); 4112 /* Barker modulation: use default values. */ 4113 cmd.corr_barker = htole16(190); 4114 cmd.corr_barker_mrc = htole16(390); 4115 4116 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4117 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4118 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4119 calib->energy_cck)); 4120 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4121 } 4122 4123 /* 4124 * Set STA mode power saving level (between 0 and 5). 4125 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4126 */ 4127 static int 4128 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4129 { 4130 struct iwn_pmgt_cmd cmd; 4131 const struct iwn_pmgt *pmgt; 4132 uint32_t maxp, skip_dtim; 4133 pcireg_t reg; 4134 int i; 4135 4136 /* Select which PS parameters to use. */ 4137 if (dtim <= 2) 4138 pmgt = &iwn_pmgt[0][level]; 4139 else if (dtim <= 10) 4140 pmgt = &iwn_pmgt[1][level]; 4141 else 4142 pmgt = &iwn_pmgt[2][level]; 4143 4144 memset(&cmd, 0, sizeof cmd); 4145 if (level != 0) /* not CAM */ 4146 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4147 if (level == 5) 4148 cmd.flags |= htole16(IWN_PS_FAST_PD); 4149 /* Retrieve PCIe Active State Power Management (ASPM). */ 4150 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4151 sc->sc_cap_off + PCI_PCIE_LCSR); 4152 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4153 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4154 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4155 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4156 4157 if (dtim == 0) { 4158 dtim = 1; 4159 skip_dtim = 0; 4160 } else 4161 skip_dtim = pmgt->skip_dtim; 4162 if (skip_dtim != 0) { 4163 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4164 maxp = pmgt->intval[4]; 4165 if (maxp == (uint32_t)-1) 4166 maxp = dtim * (skip_dtim + 1); 4167 else if (maxp > dtim) 4168 maxp = (maxp / dtim) * dtim; 4169 } else 4170 maxp = dtim; 4171 for (i = 0; i < 5; i++) 4172 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4173 4174 DPRINTF(("setting power saving level to %d\n", level)); 4175 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4176 } 4177 4178 static int 4179 iwn_config(struct iwn_softc *sc) 4180 { 4181 const struct iwn_hal *hal = sc->sc_hal; 4182 struct ieee80211com *ic = &sc->sc_ic; 4183 struct ifnet *ifp = ic->ic_ifp; 4184 struct iwn_bluetooth bluetooth; 4185 uint32_t txmask; 4186 uint16_t rxchain; 4187 int error; 4188 4189 /* Configure valid TX chains for 5000 Series. */ 4190 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4191 txmask = htole32(sc->txchainmask); 4192 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4193 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4194 sizeof txmask, 0); 4195 if (error != 0) { 4196 aprint_error_dev(sc->sc_dev, 4197 "could not configure valid TX chains\n"); 4198 return error; 4199 } 4200 } 4201 4202 /* Configure bluetooth coexistence. */ 4203 memset(&bluetooth, 0, sizeof bluetooth); 4204 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4205 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4206 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4207 DPRINTF(("configuring bluetooth coexistence\n")); 4208 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4209 if (error != 0) { 4210 aprint_error_dev(sc->sc_dev, 4211 "could not configure bluetooth coexistence\n"); 4212 return error; 4213 } 4214 4215 /* Set mode, channel, RX filter and enable RX. */ 4216 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4217 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4218 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4219 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4220 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4221 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4222 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4223 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4224 switch (ic->ic_opmode) { 4225 case IEEE80211_M_STA: 4226 sc->rxon.mode = IWN_MODE_STA; 4227 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4228 break; 4229 case IEEE80211_M_MONITOR: 4230 sc->rxon.mode = IWN_MODE_MONITOR; 4231 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4232 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4233 break; 4234 default: 4235 /* Should not get there. */ 4236 break; 4237 } 4238 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4239 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4240 sc->rxon.ht_single_mask = 0xff; 4241 sc->rxon.ht_dual_mask = 0xff; 4242 sc->rxon.ht_triple_mask = 0xff; 4243 rxchain = 4244 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4245 IWN_RXCHAIN_MIMO_COUNT(2) | 4246 IWN_RXCHAIN_IDLE_COUNT(2); 4247 sc->rxon.rxchain = htole16(rxchain); 4248 DPRINTF(("setting configuration\n")); 4249 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4250 if (error != 0) { 4251 aprint_error_dev(sc->sc_dev, 4252 "RXON command failed\n"); 4253 return error; 4254 } 4255 4256 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4257 aprint_error_dev(sc->sc_dev, 4258 "could not add broadcast node\n"); 4259 return error; 4260 } 4261 4262 /* Configuration has changed, set TX power accordingly. */ 4263 if ((error = hal->set_txpower(sc, 0)) != 0) { 4264 aprint_error_dev(sc->sc_dev, 4265 "could not set TX power\n"); 4266 return error; 4267 } 4268 4269 if ((error = iwn_set_critical_temp(sc)) != 0) { 4270 aprint_error_dev(sc->sc_dev, 4271 "could not set critical temperature\n"); 4272 return error; 4273 } 4274 4275 /* Set power saving level to CAM during initialization. */ 4276 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4277 aprint_error_dev(sc->sc_dev, 4278 "could not set power saving level\n"); 4279 return error; 4280 } 4281 return 0; 4282 } 4283 4284 static int 4285 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4286 { 4287 struct ieee80211com *ic = &sc->sc_ic; 4288 struct iwn_scan_hdr *hdr; 4289 struct iwn_cmd_data *tx; 4290 struct iwn_scan_essid *essid; 4291 struct iwn_scan_chan *chan; 4292 struct ieee80211_frame *wh; 4293 struct ieee80211_rateset *rs; 4294 struct ieee80211_channel *c; 4295 uint8_t *buf, *frm; 4296 uint16_t rxchain; 4297 uint8_t txant; 4298 int buflen, error; 4299 4300 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4301 if (buf == NULL) { 4302 aprint_error_dev(sc->sc_dev, 4303 "could not allocate buffer for scan command\n"); 4304 return ENOMEM; 4305 } 4306 hdr = (struct iwn_scan_hdr *)buf; 4307 /* 4308 * Move to the next channel if no frames are received within 10ms 4309 * after sending the probe request. 4310 */ 4311 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4312 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4313 4314 /* Select antennas for scanning. */ 4315 rxchain = 4316 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4317 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4318 IWN_RXCHAIN_DRIVER_FORCE; 4319 if ((flags & IEEE80211_CHAN_5GHZ) && 4320 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4321 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4322 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4323 } else /* Use all available RX antennas. */ 4324 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4325 hdr->rxchain = htole16(rxchain); 4326 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4327 4328 tx = (struct iwn_cmd_data *)(hdr + 1); 4329 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4330 tx->id = sc->sc_hal->broadcast_id; 4331 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4332 4333 if (flags & IEEE80211_CHAN_5GHZ) { 4334 hdr->crc_threshold = 0xffff; 4335 /* Send probe requests at 6Mbps. */ 4336 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4337 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4338 } else { 4339 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4340 /* Send probe requests at 1Mbps. */ 4341 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4342 tx->rflags = IWN_RFLAG_CCK; 4343 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4344 } 4345 /* Use the first valid TX antenna. */ 4346 txant = IWN_LSB(sc->txchainmask); 4347 tx->rflags |= IWN_RFLAG_ANT(txant); 4348 4349 essid = (struct iwn_scan_essid *)(tx + 1); 4350 if (ic->ic_des_esslen != 0) { 4351 essid[0].id = IEEE80211_ELEMID_SSID; 4352 essid[0].len = ic->ic_des_esslen; 4353 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4354 } 4355 /* 4356 * Build a probe request frame. Most of the following code is a 4357 * copy & paste of what is done in net80211. 4358 */ 4359 wh = (struct ieee80211_frame *)(essid + 20); 4360 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4361 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4362 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4363 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4364 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4365 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4366 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4367 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4368 4369 frm = (uint8_t *)(wh + 1); 4370 frm = ieee80211_add_ssid(frm, NULL, 0); 4371 frm = ieee80211_add_rates(frm, rs); 4372 #ifndef IEEE80211_NO_HT 4373 if (ic->ic_flags & IEEE80211_F_HTON) 4374 frm = ieee80211_add_htcaps(frm, ic); 4375 #endif 4376 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4377 frm = ieee80211_add_xrates(frm, rs); 4378 4379 /* Set length of probe request. */ 4380 tx->len = htole16(frm - (uint8_t *)wh); 4381 4382 chan = (struct iwn_scan_chan *)frm; 4383 for (c = &ic->ic_channels[1]; 4384 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4385 if ((c->ic_flags & flags) != flags) 4386 continue; 4387 4388 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4389 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4390 chan->flags = 0; 4391 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4392 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4393 if (ic->ic_des_esslen != 0) 4394 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4395 chan->dsp_gain = 0x6e; 4396 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4397 chan->rf_gain = 0x3b; 4398 chan->active = htole16(24); 4399 chan->passive = htole16(110); 4400 } else { 4401 chan->rf_gain = 0x28; 4402 chan->active = htole16(36); 4403 chan->passive = htole16(120); 4404 } 4405 hdr->nchan++; 4406 chan++; 4407 } 4408 4409 buflen = (uint8_t *)chan - buf; 4410 hdr->len = htole16(buflen); 4411 4412 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4413 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4414 free(buf, M_DEVBUF); 4415 return error; 4416 } 4417 4418 static int 4419 iwn_auth(struct iwn_softc *sc) 4420 { 4421 const struct iwn_hal *hal = sc->sc_hal; 4422 struct ieee80211com *ic = &sc->sc_ic; 4423 struct ieee80211_node *ni = ic->ic_bss; 4424 int error; 4425 4426 /* Update adapter configuration. */ 4427 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4428 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4429 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4430 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4431 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4432 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4433 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4434 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4435 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4436 switch (ic->ic_curmode) { 4437 case IEEE80211_MODE_11A: 4438 sc->rxon.cck_mask = 0; 4439 sc->rxon.ofdm_mask = 0x15; 4440 break; 4441 case IEEE80211_MODE_11B: 4442 sc->rxon.cck_mask = 0x03; 4443 sc->rxon.ofdm_mask = 0; 4444 break; 4445 default: /* Assume 802.11b/g. */ 4446 sc->rxon.cck_mask = 0x0f; 4447 sc->rxon.ofdm_mask = 0x15; 4448 } 4449 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4450 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4451 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4452 if (error != 0) { 4453 aprint_error_dev(sc->sc_dev, 4454 "RXON command failed\n"); 4455 return error; 4456 } 4457 4458 /* Configuration has changed, set TX power accordingly. */ 4459 if ((error = hal->set_txpower(sc, 1)) != 0) { 4460 aprint_error_dev(sc->sc_dev, 4461 "could not set TX power\n"); 4462 return error; 4463 } 4464 /* 4465 * Reconfiguring RXON clears the firmware nodes table so we must 4466 * add the broadcast node again. 4467 */ 4468 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4469 aprint_error_dev(sc->sc_dev, 4470 "could not add broadcast node\n"); 4471 return error; 4472 } 4473 return 0; 4474 } 4475 4476 static int 4477 iwn_run(struct iwn_softc *sc) 4478 { 4479 const struct iwn_hal *hal = sc->sc_hal; 4480 struct ieee80211com *ic = &sc->sc_ic; 4481 struct ieee80211_node *ni = ic->ic_bss; 4482 struct iwn_node_info node; 4483 int error; 4484 4485 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4486 /* Link LED blinks while monitoring. */ 4487 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4488 return 0; 4489 } 4490 if ((error = iwn_set_timing(sc, ni)) != 0) { 4491 aprint_error_dev(sc->sc_dev, 4492 "could not set timing\n"); 4493 return error; 4494 } 4495 4496 /* Update adapter configuration. */ 4497 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4498 /* Short preamble and slot time are negotiated when associating. */ 4499 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4500 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4501 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4502 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4503 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4504 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4505 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4506 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4507 if (error != 0) { 4508 aprint_error_dev(sc->sc_dev, 4509 "could not update configuration\n"); 4510 return error; 4511 } 4512 4513 /* Configuration has changed, set TX power accordingly. */ 4514 if ((error = hal->set_txpower(sc, 1)) != 0) { 4515 aprint_error_dev(sc->sc_dev, 4516 "could not set TX power\n"); 4517 return error; 4518 } 4519 4520 /* Fake a join to initialize the TX rate. */ 4521 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4522 iwn_newassoc(ni, 1); 4523 4524 /* Add BSS node. */ 4525 memset(&node, 0, sizeof node); 4526 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4527 node.id = IWN_ID_BSS; 4528 #ifdef notyet 4529 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4530 IWN_AMDPU_DENSITY(5)); /* 2us */ 4531 #endif 4532 DPRINTF(("adding BSS node\n")); 4533 error = hal->add_node(sc, &node, 1); 4534 if (error != 0) { 4535 aprint_error_dev(sc->sc_dev, 4536 "could not add BSS node\n"); 4537 return error; 4538 } 4539 DPRINTF(("setting link quality for node %d\n", node.id)); 4540 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4541 aprint_error_dev(sc->sc_dev, 4542 "could not setup link quality for node %d\n", node.id); 4543 return error; 4544 } 4545 4546 if ((error = iwn_init_sensitivity(sc)) != 0) { 4547 aprint_error_dev(sc->sc_dev, 4548 "could not set sensitivity\n"); 4549 return error; 4550 } 4551 /* Start periodic calibration timer. */ 4552 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4553 sc->calib_cnt = 0; 4554 callout_schedule(&sc->calib_to, hz/2); 4555 4556 /* Link LED always on while associated. */ 4557 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4558 return 0; 4559 } 4560 4561 #ifdef IWN_HWCRYPTO 4562 /* 4563 * We support CCMP hardware encryption/decryption of unicast frames only. 4564 * HW support for TKIP really sucks. We should let TKIP die anyway. 4565 */ 4566 static int 4567 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4568 struct ieee80211_key *k) 4569 { 4570 struct iwn_softc *sc = ic->ic_softc; 4571 const struct iwn_hal *hal = sc->sc_hal; 4572 struct iwn_node *wn = (void *)ni; 4573 struct iwn_node_info node; 4574 uint16_t kflags; 4575 4576 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4577 k->k_cipher != IEEE80211_CIPHER_CCMP) 4578 return ieee80211_set_key(ic, ni, k); 4579 4580 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4581 if (k->k_flags & IEEE80211_KEY_GROUP) 4582 kflags |= IWN_KFLAG_GROUP; 4583 4584 memset(&node, 0, sizeof node); 4585 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4586 hal->broadcast_id : wn->id; 4587 node.control = IWN_NODE_UPDATE; 4588 node.flags = IWN_FLAG_SET_KEY; 4589 node.kflags = htole16(kflags); 4590 node.kid = k->k_id; 4591 memcpy(node.key, k->k_key, k->k_len); 4592 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4593 return hal->add_node(sc, &node, 1); 4594 } 4595 4596 static void 4597 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4598 struct ieee80211_key *k) 4599 { 4600 struct iwn_softc *sc = ic->ic_softc; 4601 const struct iwn_hal *hal = sc->sc_hal; 4602 struct iwn_node *wn = (void *)ni; 4603 struct iwn_node_info node; 4604 4605 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4606 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4607 /* See comment about other ciphers above. */ 4608 ieee80211_delete_key(ic, ni, k); 4609 return; 4610 } 4611 if (ic->ic_state != IEEE80211_S_RUN) 4612 return; /* Nothing to do. */ 4613 memset(&node, 0, sizeof node); 4614 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4615 hal->broadcast_id : wn->id; 4616 node.control = IWN_NODE_UPDATE; 4617 node.flags = IWN_FLAG_SET_KEY; 4618 node.kflags = htole16(IWN_KFLAG_INVALID); 4619 node.kid = 0xff; 4620 DPRINTF(("delete keys for node %d\n", node.id)); 4621 (void)hal->add_node(sc, &node, 1); 4622 } 4623 #endif 4624 4625 /* XXX Added for NetBSD (copied from rev 1.39). */ 4626 4627 static int 4628 iwn_wme_update(struct ieee80211com *ic) 4629 { 4630 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4631 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4632 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4633 const struct wmeParams *wmep; 4634 struct iwn_edca_params cmd; 4635 int ac; 4636 4637 /* don't override default WME values if WME is not actually enabled */ 4638 if (!(ic->ic_flags & IEEE80211_F_WME)) 4639 return 0; 4640 cmd.flags = 0; 4641 for (ac = 0; ac < WME_NUM_AC; ac++) { 4642 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4643 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4644 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4645 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4646 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4647 4648 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4649 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4650 cmd.ac[ac].cwmin, 4651 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4652 } 4653 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4654 #undef IWN_USEC 4655 #undef IWN_EXP2 4656 } 4657 4658 #ifndef IEEE80211_NO_HT 4659 /* 4660 * This function is called by upper layer when an ADDBA request is received 4661 * from another STA and before the ADDBA response is sent. 4662 */ 4663 static int 4664 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4665 uint8_t tid) 4666 { 4667 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4668 struct iwn_softc *sc = ic->ic_softc; 4669 struct iwn_node *wn = (void *)ni; 4670 struct iwn_node_info node; 4671 4672 memset(&node, 0, sizeof node); 4673 node.id = wn->id; 4674 node.control = IWN_NODE_UPDATE; 4675 node.flags = IWN_FLAG_SET_ADDBA; 4676 node.addba_tid = tid; 4677 node.addba_ssn = htole16(ba->ba_winstart); 4678 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4679 ba->ba_winstart)); 4680 return sc->sc_hal->add_node(sc, &node, 1); 4681 } 4682 4683 /* 4684 * This function is called by upper layer on teardown of an HT-immediate 4685 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 4686 */ 4687 static void 4688 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4689 uint8_t tid) 4690 { 4691 struct iwn_softc *sc = ic->ic_softc; 4692 struct iwn_node *wn = (void *)ni; 4693 struct iwn_node_info node; 4694 4695 memset(&node, 0, sizeof node); 4696 node.id = wn->id; 4697 node.control = IWN_NODE_UPDATE; 4698 node.flags = IWN_FLAG_SET_DELBA; 4699 node.delba_tid = tid; 4700 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4701 (void)sc->sc_hal->add_node(sc, &node, 1); 4702 } 4703 4704 /* 4705 * This function is called by upper layer when an ADDBA response is received 4706 * from another STA. 4707 */ 4708 static int 4709 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4710 uint8_t tid) 4711 { 4712 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4713 struct iwn_softc *sc = ic->ic_softc; 4714 const struct iwn_hal *hal = sc->sc_hal; 4715 struct iwn_node *wn = (void *)ni; 4716 struct iwn_node_info node; 4717 int error; 4718 4719 /* Enable TX for the specified RA/TID. */ 4720 wn->disable_tid &= ~(1 << tid); 4721 memset(&node, 0, sizeof node); 4722 node.id = wn->id; 4723 node.control = IWN_NODE_UPDATE; 4724 node.flags = IWN_FLAG_SET_DISABLE_TID; 4725 node.disable_tid = htole16(wn->disable_tid); 4726 error = hal->add_node(sc, &node, 1); 4727 if (error != 0) 4728 return error; 4729 4730 if ((error = iwn_nic_lock(sc)) != 0) 4731 return error; 4732 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4733 iwn_nic_unlock(sc); 4734 return 0; 4735 } 4736 4737 static void 4738 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4739 uint8_t tid) 4740 { 4741 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4742 struct iwn_softc *sc = ic->ic_softc; 4743 4744 if (iwn_nic_lock(sc) != 0) 4745 return; 4746 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4747 iwn_nic_unlock(sc); 4748 } 4749 4750 static void 4751 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4752 uint8_t tid, uint16_t ssn) 4753 { 4754 struct iwn_node *wn = (void *)ni; 4755 int qid = 7 + tid; 4756 4757 /* Stop TX scheduler while we're changing its configuration. */ 4758 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4759 IWN4965_TXQ_STATUS_CHGACT); 4760 4761 /* Assign RA/TID translation to the queue. */ 4762 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4763 wn->id << 4 | tid); 4764 4765 /* Enable chain-building mode for the queue. */ 4766 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4767 4768 /* Set starting sequence number from the ADDBA request. */ 4769 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4770 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4771 4772 /* Set scheduler window size. */ 4773 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4774 IWN_SCHED_WINSZ); 4775 /* Set scheduler frame limit. */ 4776 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4777 IWN_SCHED_LIMIT << 16); 4778 4779 /* Enable interrupts for the queue. */ 4780 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4781 4782 /* Mark the queue as active. */ 4783 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4784 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4785 iwn_tid2fifo[tid] << 1); 4786 } 4787 4788 static void 4789 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4790 { 4791 int qid = 7 + tid; 4792 4793 /* Stop TX scheduler while we're changing its configuration. */ 4794 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4795 IWN4965_TXQ_STATUS_CHGACT); 4796 4797 /* Set starting sequence number from the ADDBA request. */ 4798 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4799 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4800 4801 /* Disable interrupts for the queue. */ 4802 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4803 4804 /* Mark the queue as inactive. */ 4805 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4806 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4807 } 4808 4809 static void 4810 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4811 uint8_t tid, uint16_t ssn) 4812 { 4813 struct iwn_node *wn = (void *)ni; 4814 int qid = 10 + tid; 4815 4816 /* Stop TX scheduler while we're changing its configuration. */ 4817 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4818 IWN5000_TXQ_STATUS_CHGACT); 4819 4820 /* Assign RA/TID translation to the queue. */ 4821 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4822 wn->id << 4 | tid); 4823 4824 /* Enable chain-building mode for the queue. */ 4825 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4826 4827 /* Enable aggregation for the queue. */ 4828 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4829 4830 /* Set starting sequence number from the ADDBA request. */ 4831 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4832 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4833 4834 /* Set scheduler window size and frame limit. */ 4835 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4836 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4837 4838 /* Enable interrupts for the queue. */ 4839 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4840 4841 /* Mark the queue as active. */ 4842 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4843 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4844 } 4845 4846 static void 4847 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4848 { 4849 int qid = 10 + tid; 4850 4851 /* Stop TX scheduler while we're changing its configuration. */ 4852 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4853 IWN5000_TXQ_STATUS_CHGACT); 4854 4855 /* Disable aggregation for the queue. */ 4856 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4857 4858 /* Set starting sequence number from the ADDBA request. */ 4859 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4860 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4861 4862 /* Disable interrupts for the queue. */ 4863 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4864 4865 /* Mark the queue as inactive. */ 4866 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4867 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4868 } 4869 #endif /* !IEEE80211_NO_HT */ 4870 4871 /* 4872 * Query calibration tables from the initialization firmware. We do this 4873 * only once at first boot. Called from a process context. 4874 */ 4875 static int 4876 iwn5000_query_calibration(struct iwn_softc *sc) 4877 { 4878 struct iwn5000_calib_config cmd; 4879 int error; 4880 4881 memset(&cmd, 0, sizeof cmd); 4882 cmd.ucode.once.enable = 0xffffffff; 4883 cmd.ucode.once.start = 0xffffffff; 4884 cmd.ucode.once.send = 0xffffffff; 4885 cmd.ucode.flags = 0xffffffff; 4886 DPRINTF(("sending calibration query\n")); 4887 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4888 if (error != 0) 4889 return error; 4890 4891 /* Wait at most two seconds for calibration to complete. */ 4892 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4893 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4894 return error; 4895 } 4896 4897 /* 4898 * Send calibration results to the runtime firmware. These results were 4899 * obtained on first boot from the initialization firmware. 4900 */ 4901 static int 4902 iwn5000_send_calibration(struct iwn_softc *sc) 4903 { 4904 int idx, error; 4905 4906 for (idx = 0; idx < 5; idx++) { 4907 if (sc->calibcmd[idx].buf == NULL) 4908 continue; /* No results available. */ 4909 DPRINTF(("send calibration result idx=%d len=%d\n", 4910 idx, sc->calibcmd[idx].len)); 4911 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4912 sc->calibcmd[idx].len, 0); 4913 if (error != 0) { 4914 aprint_error_dev(sc->sc_dev, 4915 "could not send calibration result\n"); 4916 return error; 4917 } 4918 } 4919 return 0; 4920 } 4921 4922 static int 4923 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4924 { 4925 struct iwn5000_wimax_coex wimax; 4926 4927 #ifdef notyet 4928 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4929 /* Enable WiMAX coexistence for combo adapters. */ 4930 wimax.flags = 4931 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4932 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4933 IWN_WIMAX_COEX_STA_TABLE_VALID | 4934 IWN_WIMAX_COEX_ENABLE; 4935 memcpy(wimax.events, iwn6050_wimax_events, 4936 sizeof iwn6050_wimax_events); 4937 } else 4938 #endif 4939 { 4940 /* Disable WiMAX coexistence. */ 4941 wimax.flags = 0; 4942 memset(wimax.events, 0, sizeof wimax.events); 4943 } 4944 DPRINTF(("Configuring WiMAX coexistence\n")); 4945 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4946 } 4947 4948 /* 4949 * This function is called after the runtime firmware notifies us of its 4950 * readiness (called in a process context.) 4951 */ 4952 static int 4953 iwn4965_post_alive(struct iwn_softc *sc) 4954 { 4955 int error, qid; 4956 4957 if ((error = iwn_nic_lock(sc)) != 0) 4958 return error; 4959 4960 /* Clear TX scheduler state in SRAM. */ 4961 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4962 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4963 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 4964 4965 /* Set physical address of TX scheduler rings (1KB aligned.) */ 4966 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4967 4968 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4969 4970 /* Disable chain mode for all our 16 queues. */ 4971 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4972 4973 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4974 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4975 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4976 4977 /* Set scheduler window size. */ 4978 iwn_mem_write(sc, sc->sched_base + 4979 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4980 /* Set scheduler frame limit. */ 4981 iwn_mem_write(sc, sc->sched_base + 4982 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4983 IWN_SCHED_LIMIT << 16); 4984 } 4985 4986 /* Enable interrupts for all our 16 queues. */ 4987 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4988 /* Identify TX FIFO rings (0-7). */ 4989 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4990 4991 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4992 for (qid = 0; qid < 7; qid++) { 4993 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4994 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4995 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4996 } 4997 iwn_nic_unlock(sc); 4998 return 0; 4999 } 5000 5001 /* 5002 * This function is called after the initialization or runtime firmware 5003 * notifies us of its readiness (called in a process context.) 5004 */ 5005 static int 5006 iwn5000_post_alive(struct iwn_softc *sc) 5007 { 5008 int error, qid; 5009 5010 /* Switch to using ICT interrupt mode. */ 5011 iwn5000_ict_reset(sc); 5012 5013 if ((error = iwn_nic_lock(sc)) != 0) 5014 return error; 5015 5016 /* Clear TX scheduler state in SRAM. */ 5017 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5018 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5019 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5020 5021 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5022 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5023 5024 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5025 5026 /* Enable chain mode for all queues, except command queue. */ 5027 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5028 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5029 5030 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5031 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5032 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5033 5034 iwn_mem_write(sc, sc->sched_base + 5035 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5036 /* Set scheduler window size and frame limit. */ 5037 iwn_mem_write(sc, sc->sched_base + 5038 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5039 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5040 } 5041 5042 /* Enable interrupts for all our 20 queues. */ 5043 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5044 /* Identify TX FIFO rings (0-7). */ 5045 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5046 5047 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5048 for (qid = 0; qid < 7; qid++) { 5049 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5050 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5051 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5052 } 5053 iwn_nic_unlock(sc); 5054 5055 /* Configure WiMAX coexistence for combo adapters. */ 5056 error = iwn5000_send_wimax_coex(sc); 5057 if (error != 0) { 5058 aprint_error_dev(sc->sc_dev, 5059 "could not configure WiMAX coexistence\n"); 5060 return error; 5061 } 5062 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5063 struct iwn5000_phy_calib_crystal cmd; 5064 5065 /* Perform crystal calibration. */ 5066 memset(&cmd, 0, sizeof cmd); 5067 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5068 cmd.ngroups = 1; 5069 cmd.isvalid = 1; 5070 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5071 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5072 DPRINTF(("sending crystal calibration %d, %d\n", 5073 cmd.cap_pin[0], cmd.cap_pin[1])); 5074 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5075 if (error != 0) { 5076 aprint_error_dev(sc->sc_dev, 5077 "crystal calibration failed\n"); 5078 return error; 5079 } 5080 } 5081 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5082 /* Query calibration from the initialization firmware. */ 5083 if ((error = iwn5000_query_calibration(sc)) != 0) { 5084 aprint_error_dev(sc->sc_dev, 5085 "could not query calibration\n"); 5086 return error; 5087 } 5088 /* 5089 * We have the calibration results now, reboot with the 5090 * runtime firmware (call ourselves recursively!) 5091 */ 5092 iwn_hw_stop(sc); 5093 error = iwn_hw_init(sc); 5094 } else { 5095 /* Send calibration results to runtime firmware. */ 5096 error = iwn5000_send_calibration(sc); 5097 } 5098 return error; 5099 } 5100 5101 /* 5102 * The firmware boot code is small and is intended to be copied directly into 5103 * the NIC internal memory (no DMA transfer.) 5104 */ 5105 static int 5106 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5107 { 5108 int error, ntries; 5109 5110 size /= sizeof (uint32_t); 5111 5112 if ((error = iwn_nic_lock(sc)) != 0) 5113 return error; 5114 5115 /* Copy microcode image into NIC memory. */ 5116 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5117 (const uint32_t *)ucode, size); 5118 5119 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5120 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5121 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5122 5123 /* Start boot load now. */ 5124 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5125 5126 /* Wait for transfer to complete. */ 5127 for (ntries = 0; ntries < 1000; ntries++) { 5128 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5129 IWN_BSM_WR_CTRL_START)) 5130 break; 5131 DELAY(10); 5132 } 5133 if (ntries == 1000) { 5134 aprint_error_dev(sc->sc_dev, 5135 "could not load boot firmware\n"); 5136 iwn_nic_unlock(sc); 5137 return ETIMEDOUT; 5138 } 5139 5140 /* Enable boot after power up. */ 5141 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5142 5143 iwn_nic_unlock(sc); 5144 return 0; 5145 } 5146 5147 static int 5148 iwn4965_load_firmware(struct iwn_softc *sc) 5149 { 5150 struct iwn_fw_info *fw = &sc->fw; 5151 struct iwn_dma_info *dma = &sc->fw_dma; 5152 int error; 5153 5154 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5155 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5156 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5157 BUS_DMASYNC_PREWRITE); 5158 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5159 fw->init.text, fw->init.textsz); 5160 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5161 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5162 5163 /* Tell adapter where to find initialization sections. */ 5164 if ((error = iwn_nic_lock(sc)) != 0) 5165 return error; 5166 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5167 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5168 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5169 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5170 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5171 iwn_nic_unlock(sc); 5172 5173 /* Load firmware boot code. */ 5174 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5175 if (error != 0) { 5176 aprint_error_dev(sc->sc_dev, 5177 "could not load boot firmware\n"); 5178 return error; 5179 } 5180 /* Now press "execute". */ 5181 IWN_WRITE(sc, IWN_RESET, 0); 5182 5183 /* Wait at most one second for first alive notification. */ 5184 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5185 aprint_error_dev(sc->sc_dev, 5186 "timeout waiting for adapter to initialize\n"); 5187 return error; 5188 } 5189 5190 /* Retrieve current temperature for initial TX power calibration. */ 5191 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5192 sc->temp = iwn4965_get_temperature(sc); 5193 5194 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5195 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5196 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5197 BUS_DMASYNC_PREWRITE); 5198 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5199 fw->main.text, fw->main.textsz); 5200 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5201 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5202 5203 /* Tell adapter where to find runtime sections. */ 5204 if ((error = iwn_nic_lock(sc)) != 0) 5205 return error; 5206 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5207 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5208 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5209 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5210 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5211 IWN_FW_UPDATED | fw->main.textsz); 5212 iwn_nic_unlock(sc); 5213 5214 return 0; 5215 } 5216 5217 static int 5218 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5219 const uint8_t *section, int size) 5220 { 5221 struct iwn_dma_info *dma = &sc->fw_dma; 5222 int error; 5223 5224 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5225 memcpy(dma->vaddr, section, size); 5226 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5227 5228 if ((error = iwn_nic_lock(sc)) != 0) 5229 return error; 5230 5231 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5232 IWN_FH_TX_CONFIG_DMA_PAUSE); 5233 5234 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5235 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5236 IWN_LOADDR(dma->paddr)); 5237 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5238 IWN_HIADDR(dma->paddr) << 28 | size); 5239 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5240 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5241 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5242 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5243 5244 /* Kick Flow Handler to start DMA transfer. */ 5245 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5246 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5247 5248 iwn_nic_unlock(sc); 5249 5250 /* Wait at most five seconds for FH DMA transfer to complete. */ 5251 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5252 } 5253 5254 static int 5255 iwn5000_load_firmware(struct iwn_softc *sc) 5256 { 5257 struct iwn_fw_part *fw; 5258 int error; 5259 5260 /* Load the initialization firmware on first boot only. */ 5261 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5262 &sc->fw.main : &sc->fw.init; 5263 5264 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5265 fw->text, fw->textsz); 5266 if (error != 0) { 5267 aprint_error_dev(sc->sc_dev, 5268 "could not load firmware %s section\n", ".text"); 5269 return error; 5270 } 5271 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5272 fw->data, fw->datasz); 5273 if (error != 0) { 5274 aprint_error_dev(sc->sc_dev, 5275 "could not load firmware %s section\n", ".data"); 5276 return error; 5277 } 5278 5279 /* Now press "execute". */ 5280 IWN_WRITE(sc, IWN_RESET, 0); 5281 return 0; 5282 } 5283 5284 /* 5285 * Extract text and data sections from a legacy firmware image. 5286 */ 5287 static int 5288 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5289 { 5290 const uint32_t *ptr; 5291 size_t hdrlen = 24; 5292 uint32_t rev; 5293 5294 ptr = (const uint32_t *)fw->data; 5295 rev = le32toh(*ptr++); 5296 5297 /* Check firmware API version. */ 5298 if (IWN_FW_API(rev) <= 1) { 5299 aprint_error_dev(sc->sc_dev, 5300 "bad firmware, need API version >=2\n"); 5301 return EINVAL; 5302 } 5303 if (IWN_FW_API(rev) >= 3) { 5304 /* Skip build number (version 2 header). */ 5305 hdrlen += 4; 5306 ptr++; 5307 } 5308 if (fw->size < hdrlen) { 5309 aprint_error_dev(sc->sc_dev, 5310 "firmware too short: %zd bytes\n", fw->size); 5311 return EINVAL; 5312 } 5313 fw->main.textsz = le32toh(*ptr++); 5314 fw->main.datasz = le32toh(*ptr++); 5315 fw->init.textsz = le32toh(*ptr++); 5316 fw->init.datasz = le32toh(*ptr++); 5317 fw->boot.textsz = le32toh(*ptr++); 5318 5319 /* Check that all firmware sections fit. */ 5320 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5321 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5322 aprint_error_dev(sc->sc_dev, 5323 "firmware too short: %zd bytes\n", fw->size); 5324 return EINVAL; 5325 } 5326 5327 /* Get pointers to firmware sections. */ 5328 fw->main.text = (const uint8_t *)ptr; 5329 fw->main.data = fw->main.text + fw->main.textsz; 5330 fw->init.text = fw->main.data + fw->main.datasz; 5331 fw->init.data = fw->init.text + fw->init.textsz; 5332 fw->boot.text = fw->init.data + fw->init.datasz; 5333 return 0; 5334 } 5335 5336 /* 5337 * Extract text and data sections from a TLV firmware image. 5338 */ 5339 static int 5340 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5341 uint16_t alt) 5342 { 5343 const struct iwn_fw_tlv_hdr *hdr; 5344 const struct iwn_fw_tlv *tlv; 5345 const uint8_t *ptr, *end; 5346 uint64_t altmask; 5347 uint32_t len; 5348 5349 if (fw->size < sizeof (*hdr)) { 5350 aprint_error_dev(sc->sc_dev, 5351 "firmware too short: %zd bytes\n", fw->size); 5352 return EINVAL; 5353 } 5354 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5355 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5356 aprint_error_dev(sc->sc_dev, 5357 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5358 return EINVAL; 5359 } 5360 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5361 le32toh(hdr->build))); 5362 5363 /* 5364 * Select the closest supported alternative that is less than 5365 * or equal to the specified one. 5366 */ 5367 altmask = le64toh(hdr->altmask); 5368 while (alt > 0 && !(altmask & (1ULL << alt))) 5369 alt--; /* Downgrade. */ 5370 DPRINTF(("using alternative %d\n", alt)); 5371 5372 ptr = (const uint8_t *)(hdr + 1); 5373 end = (const uint8_t *)(fw->data + fw->size); 5374 5375 /* Parse type-length-value fields. */ 5376 while (ptr + sizeof (*tlv) <= end) { 5377 tlv = (const struct iwn_fw_tlv *)ptr; 5378 len = le32toh(tlv->len); 5379 5380 ptr += sizeof (*tlv); 5381 if (ptr + len > end) { 5382 aprint_error_dev(sc->sc_dev, 5383 "firmware too short: %zd bytes\n", fw->size); 5384 return EINVAL; 5385 } 5386 /* Skip other alternatives. */ 5387 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5388 goto next; 5389 5390 switch (le16toh(tlv->type)) { 5391 case IWN_FW_TLV_MAIN_TEXT: 5392 fw->main.text = ptr; 5393 fw->main.textsz = len; 5394 break; 5395 case IWN_FW_TLV_MAIN_DATA: 5396 fw->main.data = ptr; 5397 fw->main.datasz = len; 5398 break; 5399 case IWN_FW_TLV_INIT_TEXT: 5400 fw->init.text = ptr; 5401 fw->init.textsz = len; 5402 break; 5403 case IWN_FW_TLV_INIT_DATA: 5404 fw->init.data = ptr; 5405 fw->init.datasz = len; 5406 break; 5407 case IWN_FW_TLV_BOOT_TEXT: 5408 fw->boot.text = ptr; 5409 fw->boot.textsz = len; 5410 break; 5411 default: 5412 DPRINTF(("TLV type %d not handled\n", 5413 le16toh(tlv->type))); 5414 break; 5415 } 5416 next: /* TLV fields are 32-bit aligned. */ 5417 ptr += (len + 3) & ~3; 5418 } 5419 return 0; 5420 } 5421 5422 static int 5423 iwn_read_firmware(struct iwn_softc *sc) 5424 { 5425 const struct iwn_hal *hal = sc->sc_hal; 5426 struct iwn_fw_info *fw = &sc->fw; 5427 firmware_handle_t fwh; 5428 int error; 5429 5430 /* Initialize for error returns */ 5431 fw->data = NULL; 5432 fw->size = 0; 5433 5434 /* Open firmware image. */ 5435 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5436 aprint_error_dev(sc->sc_dev, 5437 "could not get firmware handle %s\n", sc->fwname); 5438 return error; 5439 } 5440 fw->size = firmware_get_size(fwh); 5441 if (fw->size < sizeof (uint32_t)) { 5442 aprint_error_dev(sc->sc_dev, 5443 "firmware too short: %zd bytes\n", fw->size); 5444 firmware_close(fwh); 5445 return EINVAL; 5446 } 5447 5448 /* Read the firmware. */ 5449 fw->data = firmware_malloc(fw->size); 5450 if (fw->data == NULL) { 5451 aprint_error_dev(sc->sc_dev, 5452 "not enough memory to stock firmware %s\n", sc->fwname); 5453 firmware_close(fwh); 5454 return ENOMEM; 5455 } 5456 error = firmware_read(fwh, 0, fw->data, fw->size); 5457 firmware_close(fwh); 5458 if (error != 0) { 5459 aprint_error_dev(sc->sc_dev, 5460 "could not read firmware %s\n", sc->fwname); 5461 goto out; 5462 } 5463 5464 /* Retrieve text and data sections. */ 5465 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5466 error = iwn_read_firmware_leg(sc, fw); 5467 else 5468 error = iwn_read_firmware_tlv(sc, fw, 1); 5469 if (error != 0) { 5470 aprint_error_dev(sc->sc_dev, 5471 "could not read firmware sections\n"); 5472 goto out; 5473 } 5474 5475 /* Make sure text and data sections fit in hardware memory. */ 5476 if (fw->main.textsz > hal->fw_text_maxsz || 5477 fw->main.datasz > hal->fw_data_maxsz || 5478 fw->init.textsz > hal->fw_text_maxsz || 5479 fw->init.datasz > hal->fw_data_maxsz || 5480 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5481 (fw->boot.textsz & 3) != 0) { 5482 aprint_error_dev(sc->sc_dev, 5483 "firmware sections too large\n"); 5484 goto out; 5485 } 5486 5487 /* We can proceed with loading the firmware. */ 5488 return 0; 5489 out: 5490 firmware_free(fw->data, fw->size); 5491 fw->data = NULL; 5492 fw->size = 0; 5493 return error ? error : EINVAL; 5494 } 5495 5496 static int 5497 iwn_clock_wait(struct iwn_softc *sc) 5498 { 5499 int ntries; 5500 5501 /* Set "initialization complete" bit. */ 5502 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5503 5504 /* Wait for clock stabilization. */ 5505 for (ntries = 0; ntries < 2500; ntries++) { 5506 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5507 return 0; 5508 DELAY(10); 5509 } 5510 aprint_error_dev(sc->sc_dev, 5511 "timeout waiting for clock stabilization\n"); 5512 return ETIMEDOUT; 5513 } 5514 5515 static int 5516 iwn_apm_init(struct iwn_softc *sc) 5517 { 5518 pcireg_t reg; 5519 int error; 5520 5521 /* Disable L0s exit timer (NMI bug workaround.) */ 5522 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5523 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5524 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5525 5526 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5527 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5528 5529 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5530 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5531 5532 /* Retrieve PCIe Active State Power Management (ASPM). */ 5533 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5534 sc->sc_cap_off + PCI_PCIE_LCSR); 5535 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5536 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5537 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5538 else 5539 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5540 5541 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5542 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5543 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5544 5545 /* Wait for clock stabilization before accessing prph. */ 5546 if ((error = iwn_clock_wait(sc)) != 0) 5547 return error; 5548 5549 if ((error = iwn_nic_lock(sc)) != 0) 5550 return error; 5551 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5552 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5553 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5554 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5555 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5556 } else { 5557 /* Enable DMA. */ 5558 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5559 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5560 } 5561 DELAY(20); 5562 /* Disable L1-Active. */ 5563 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5564 iwn_nic_unlock(sc); 5565 5566 return 0; 5567 } 5568 5569 static void 5570 iwn_apm_stop_master(struct iwn_softc *sc) 5571 { 5572 int ntries; 5573 5574 /* Stop busmaster DMA activity. */ 5575 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5576 for (ntries = 0; ntries < 100; ntries++) { 5577 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5578 return; 5579 DELAY(10); 5580 } 5581 aprint_error_dev(sc->sc_dev, 5582 "timeout waiting for master\n"); 5583 } 5584 5585 static void 5586 iwn_apm_stop(struct iwn_softc *sc) 5587 { 5588 iwn_apm_stop_master(sc); 5589 5590 /* Reset the entire device. */ 5591 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5592 DELAY(10); 5593 /* Clear "initialization complete" bit. */ 5594 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5595 } 5596 5597 static int 5598 iwn4965_nic_config(struct iwn_softc *sc) 5599 { 5600 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5601 /* 5602 * I don't believe this to be correct but this is what the 5603 * vendor driver is doing. Probably the bits should not be 5604 * shifted in IWN_RFCFG_*. 5605 */ 5606 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5607 IWN_RFCFG_TYPE(sc->rfcfg) | 5608 IWN_RFCFG_STEP(sc->rfcfg) | 5609 IWN_RFCFG_DASH(sc->rfcfg)); 5610 } 5611 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5612 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5613 return 0; 5614 } 5615 5616 static int 5617 iwn5000_nic_config(struct iwn_softc *sc) 5618 { 5619 uint32_t tmp; 5620 int error; 5621 5622 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5623 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5624 IWN_RFCFG_TYPE(sc->rfcfg) | 5625 IWN_RFCFG_STEP(sc->rfcfg) | 5626 IWN_RFCFG_DASH(sc->rfcfg)); 5627 } 5628 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5629 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5630 5631 if ((error = iwn_nic_lock(sc)) != 0) 5632 return error; 5633 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5634 5635 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5636 /* 5637 * Select first Switching Voltage Regulator (1.32V) to 5638 * solve a stability issue related to noisy DC2DC line 5639 * in the silicon of 1000 Series. 5640 */ 5641 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5642 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5643 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5644 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5645 } 5646 iwn_nic_unlock(sc); 5647 5648 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5649 /* Use internal power amplifier only. */ 5650 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5651 } 5652 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) { 5653 /* Indicate that ROM calibration version is >=6. */ 5654 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5655 } 5656 return 0; 5657 } 5658 5659 /* 5660 * Take NIC ownership over Intel Active Management Technology (AMT). 5661 */ 5662 static int 5663 iwn_hw_prepare(struct iwn_softc *sc) 5664 { 5665 int ntries; 5666 5667 /* Check if hardware is ready. */ 5668 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5669 for (ntries = 0; ntries < 5; ntries++) { 5670 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5671 IWN_HW_IF_CONFIG_NIC_READY) 5672 return 0; 5673 DELAY(10); 5674 } 5675 5676 /* Hardware not ready, force into ready state. */ 5677 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5678 for (ntries = 0; ntries < 15000; ntries++) { 5679 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5680 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5681 break; 5682 DELAY(10); 5683 } 5684 if (ntries == 15000) 5685 return ETIMEDOUT; 5686 5687 /* Hardware should be ready now. */ 5688 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5689 for (ntries = 0; ntries < 5; ntries++) { 5690 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5691 IWN_HW_IF_CONFIG_NIC_READY) 5692 return 0; 5693 DELAY(10); 5694 } 5695 return ETIMEDOUT; 5696 } 5697 5698 static int 5699 iwn_hw_init(struct iwn_softc *sc) 5700 { 5701 const struct iwn_hal *hal = sc->sc_hal; 5702 int error, chnl, qid; 5703 5704 /* Clear pending interrupts. */ 5705 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5706 5707 if ((error = iwn_apm_init(sc)) != 0) { 5708 aprint_error_dev(sc->sc_dev, 5709 "could not power ON adapter\n"); 5710 return error; 5711 } 5712 5713 /* Select VMAIN power source. */ 5714 if ((error = iwn_nic_lock(sc)) != 0) 5715 return error; 5716 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5717 iwn_nic_unlock(sc); 5718 5719 /* Perform adapter-specific initialization. */ 5720 if ((error = hal->nic_config(sc)) != 0) 5721 return error; 5722 5723 /* Initialize RX ring. */ 5724 if ((error = iwn_nic_lock(sc)) != 0) 5725 return error; 5726 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5727 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5728 /* Set physical address of RX ring (256-byte aligned.) */ 5729 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5730 /* Set physical address of RX status (16-byte aligned.) */ 5731 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5732 /* Enable RX. */ 5733 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5734 IWN_FH_RX_CONFIG_ENA | 5735 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5736 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5737 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5738 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5739 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5740 iwn_nic_unlock(sc); 5741 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5742 5743 if ((error = iwn_nic_lock(sc)) != 0) 5744 return error; 5745 5746 /* Initialize TX scheduler. */ 5747 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5748 5749 /* Set physical address of "keep warm" page (16-byte aligned.) */ 5750 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5751 5752 /* Initialize TX rings. */ 5753 for (qid = 0; qid < hal->ntxqs; qid++) { 5754 struct iwn_tx_ring *txq = &sc->txq[qid]; 5755 5756 /* Set physical address of TX ring (256-byte aligned.) */ 5757 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5758 txq->desc_dma.paddr >> 8); 5759 } 5760 iwn_nic_unlock(sc); 5761 5762 /* Enable DMA channels. */ 5763 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5764 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5765 IWN_FH_TX_CONFIG_DMA_ENA | 5766 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5767 } 5768 5769 /* Clear "radio off" and "commands blocked" bits. */ 5770 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5771 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5772 5773 /* Clear pending interrupts. */ 5774 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5775 /* Enable interrupt coalescing. */ 5776 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5777 /* Enable interrupts. */ 5778 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5779 5780 /* _Really_ make sure "radio off" bit is cleared! */ 5781 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5782 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5783 5784 if ((error = hal->load_firmware(sc)) != 0) { 5785 aprint_error_dev(sc->sc_dev, 5786 "could not load firmware\n"); 5787 return error; 5788 } 5789 /* Wait at most one second for firmware alive notification. */ 5790 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5791 aprint_error_dev(sc->sc_dev, 5792 "timeout waiting for adapter to initialize\n"); 5793 return error; 5794 } 5795 /* Do post-firmware initialization. */ 5796 return hal->post_alive(sc); 5797 } 5798 5799 static void 5800 iwn_hw_stop(struct iwn_softc *sc) 5801 { 5802 const struct iwn_hal *hal = sc->sc_hal; 5803 int chnl, qid, ntries; 5804 uint32_t tmp; 5805 5806 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5807 5808 /* Disable interrupts. */ 5809 IWN_WRITE(sc, IWN_INT_MASK, 0); 5810 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5811 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5812 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5813 5814 /* Make sure we no longer hold the NIC lock. */ 5815 iwn_nic_unlock(sc); 5816 5817 /* Stop TX scheduler. */ 5818 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5819 5820 /* Stop all DMA channels. */ 5821 if (iwn_nic_lock(sc) == 0) { 5822 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5823 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5824 for (ntries = 0; ntries < 200; ntries++) { 5825 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 5826 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 5827 IWN_FH_TX_STATUS_IDLE(chnl)) 5828 break; 5829 DELAY(10); 5830 } 5831 } 5832 iwn_nic_unlock(sc); 5833 } 5834 5835 /* Stop RX ring. */ 5836 iwn_reset_rx_ring(sc, &sc->rxq); 5837 5838 /* Reset all TX rings. */ 5839 for (qid = 0; qid < hal->ntxqs; qid++) 5840 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5841 5842 if (iwn_nic_lock(sc) == 0) { 5843 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5844 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5845 iwn_nic_unlock(sc); 5846 } 5847 DELAY(5); 5848 /* Power OFF adapter. */ 5849 iwn_apm_stop(sc); 5850 } 5851 5852 static int 5853 iwn_init(struct ifnet *ifp) 5854 { 5855 struct iwn_softc *sc = ifp->if_softc; 5856 struct ieee80211com *ic = &sc->sc_ic; 5857 int error; 5858 5859 if ((error = iwn_hw_prepare(sc)) != 0) { 5860 aprint_error_dev(sc->sc_dev, 5861 "hardware not ready\n"); 5862 goto fail; 5863 } 5864 5865 /* Check that the radio is not disabled by hardware switch. */ 5866 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5867 aprint_error_dev(sc->sc_dev, 5868 "radio is disabled by hardware switch\n"); 5869 error = EPERM; /* :-) */ 5870 goto fail; 5871 } 5872 5873 /* Read firmware images from the filesystem. */ 5874 if ((error = iwn_read_firmware(sc)) != 0) { 5875 aprint_error_dev(sc->sc_dev, 5876 "could not read firmware\n"); 5877 goto fail; 5878 } 5879 5880 /* Initialize interrupt mask to default value. */ 5881 sc->int_mask = IWN_INT_MASK_DEF; 5882 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5883 5884 /* Initialize hardware and upload firmware. */ 5885 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 5886 error = iwn_hw_init(sc); 5887 firmware_free(sc->fw.data, sc->fw.size); 5888 sc->fw.data = NULL; 5889 sc->fw.size = 0; 5890 if (error != 0) { 5891 aprint_error_dev(sc->sc_dev, 5892 "could not initialize hardware\n"); 5893 goto fail; 5894 } 5895 5896 /* Configure adapter now that it is ready. */ 5897 if ((error = iwn_config(sc)) != 0) { 5898 aprint_error_dev(sc->sc_dev, 5899 "could not configure device\n"); 5900 goto fail; 5901 } 5902 5903 ifp->if_flags &= ~IFF_OACTIVE; 5904 ifp->if_flags |= IFF_RUNNING; 5905 5906 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5907 ieee80211_begin_scan(ic, 0); 5908 else 5909 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5910 5911 return 0; 5912 5913 fail: iwn_stop(ifp, 1); 5914 return error; 5915 } 5916 5917 static void 5918 iwn_stop(struct ifnet *ifp, int disable) 5919 { 5920 struct iwn_softc *sc = ifp->if_softc; 5921 struct ieee80211com *ic = &sc->sc_ic; 5922 5923 ifp->if_timer = sc->sc_tx_timer = 0; 5924 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5925 5926 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5927 5928 /* Power OFF hardware. */ 5929 iwn_hw_stop(sc); 5930 5931 #ifndef SMALL_KERNEL 5932 /* Temperature sensor is no longer valid. */ 5933 sc->sc_sensor.value_cur = 0; 5934 sc->sc_sensor.state = ENVSYS_SINVALID; 5935 #endif 5936 } 5937 5938 /* 5939 * XXX MCLGETI alternative 5940 * 5941 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5942 * as long as there are available free buffers then it uses MEXTMALLOC., 5943 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5944 * The MCLGET4K code is used for testing an alternative mbuf cache. 5945 */ 5946 5947 static struct mbuf * 5948 MCLGETIalt(struct iwn_softc *sc, int how, 5949 struct ifnet *ifp __unused, u_int size) 5950 { 5951 struct mbuf *m; 5952 #ifdef IWN_USE_RBUF 5953 struct iwn_rbuf *rbuf; 5954 #endif 5955 5956 MGETHDR(m, how, MT_DATA); 5957 if (m == NULL) 5958 return NULL; 5959 5960 #ifdef IWN_USE_RBUF 5961 if (sc->rxq.nb_free_entries > 0 && 5962 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 5963 /* Attach buffer to mbuf header. */ 5964 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 5965 m->m_flags |= M_EXT_RW; 5966 } 5967 else { 5968 MEXTMALLOC(m, size, how); 5969 if ((m->m_flags & M_EXT) == 0) { 5970 m_freem(m); 5971 return NULL; 5972 } 5973 } 5974 5975 #else 5976 #ifdef MCLGET4K 5977 if (size == 4096) 5978 MCLGET4K(m, how); 5979 else 5980 panic("size must be 4k"); 5981 #else 5982 MEXTMALLOC(m, size, how); 5983 #endif 5984 if ((m->m_flags & M_EXT) == 0) { 5985 m_freem(m); 5986 return NULL; 5987 } 5988 #endif 5989 5990 return m; 5991 } 5992 5993 #ifdef IWN_USE_RBUF 5994 static struct iwn_rbuf * 5995 iwn_alloc_rbuf(struct iwn_softc *sc) 5996 { 5997 struct iwn_rbuf *rbuf; 5998 mutex_enter(&sc->rxq.freelist_mtx); 5999 6000 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6001 if (rbuf != NULL) { 6002 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6003 sc->rxq.nb_free_entries --; 6004 } 6005 mutex_exit(&sc->rxq.freelist_mtx); 6006 return rbuf; 6007 } 6008 6009 /* 6010 * This is called automatically by the network stack when the mbuf to which 6011 * our RX buffer is attached is freed. 6012 */ 6013 static void 6014 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6015 { 6016 struct iwn_rbuf *rbuf = arg; 6017 struct iwn_softc *sc = rbuf->sc; 6018 6019 /* Put the RX buffer back in the free list. */ 6020 mutex_enter(&sc->rxq.freelist_mtx); 6021 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6022 mutex_exit(&sc->rxq.freelist_mtx); 6023 6024 sc->rxq.nb_free_entries ++; 6025 if (__predict_true(m != NULL)) 6026 pool_cache_put(mb_cache, m); 6027 } 6028 6029 static int 6030 iwn_alloc_rpool(struct iwn_softc *sc) 6031 { 6032 struct iwn_rx_ring *ring = &sc->rxq; 6033 struct iwn_rbuf *rbuf; 6034 int i, error; 6035 6036 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6037 6038 /* Allocate a big chunk of DMA'able memory... */ 6039 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6040 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6041 if (error != 0) { 6042 aprint_error_dev(sc->sc_dev, 6043 "could not allocate RX buffers DMA memory\n"); 6044 return error; 6045 } 6046 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6047 SLIST_INIT(&ring->freelist); 6048 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6049 rbuf = &ring->rbuf[i]; 6050 6051 rbuf->sc = sc; /* Backpointer for callbacks. */ 6052 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6053 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6054 6055 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6056 } 6057 ring->nb_free_entries = IWN_RBUF_COUNT; 6058 return 0; 6059 } 6060 6061 static void 6062 iwn_free_rpool(struct iwn_softc *sc) 6063 { 6064 iwn_dma_contig_free(&sc->rxq.buf_dma); 6065 } 6066 #endif 6067 6068 /* 6069 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6070 * Copyright (c) 2001 Atsushi Onoe 6071 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6072 * Copyright (c) 2007-2009 Damien Bergamini 6073 * All rights reserved. 6074 */ 6075 6076 /* 6077 * Add an SSID element to a frame (see 7.3.2.1). 6078 */ 6079 static u_int8_t * 6080 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6081 { 6082 *frm++ = IEEE80211_ELEMID_SSID; 6083 *frm++ = len; 6084 memcpy(frm, ssid, len); 6085 return frm + len; 6086 } 6087 6088 /* 6089 * Add a supported rates element to a frame (see 7.3.2.2). 6090 */ 6091 static u_int8_t * 6092 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6093 { 6094 int nrates; 6095 6096 *frm++ = IEEE80211_ELEMID_RATES; 6097 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6098 *frm++ = nrates; 6099 memcpy(frm, rs->rs_rates, nrates); 6100 return frm + nrates; 6101 } 6102 6103 /* 6104 * Add an extended supported rates element to a frame (see 7.3.2.14). 6105 */ 6106 static u_int8_t * 6107 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6108 { 6109 int nrates; 6110 6111 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6112 6113 *frm++ = IEEE80211_ELEMID_XRATES; 6114 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6115 *frm++ = nrates; 6116 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6117 return frm + nrates; 6118 } 6119 6120 /* 6121 * XXX: Hack to set the current channel to the value advertised in beacons or 6122 * probe responses. Only used during AP detection. 6123 * XXX: Duplicated from if_iwi.c 6124 */ 6125 static void 6126 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6127 { 6128 struct ieee80211_frame *wh; 6129 uint8_t subtype; 6130 uint8_t *frm, *efrm; 6131 6132 wh = mtod(m, struct ieee80211_frame *); 6133 6134 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6135 return; 6136 6137 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6138 6139 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6140 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6141 return; 6142 6143 frm = (uint8_t *)(wh + 1); 6144 efrm = mtod(m, uint8_t *) + m->m_len; 6145 6146 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6147 while (frm < efrm) { 6148 if (*frm == IEEE80211_ELEMID_DSPARMS) 6149 #if IEEE80211_CHAN_MAX < 255 6150 if (frm[2] <= IEEE80211_CHAN_MAX) 6151 #endif 6152 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6153 6154 frm += frm[1] + 2; 6155 } 6156 } 6157 6158
Indexes created Mon Sep 29 21:09:56 GMT 2025