if_iwn.c revision 1.51
1 /* $NetBSD: if_iwn.c,v 1.51 2010/12/30 18:27:01 jruoho Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.96 2010/05/13 09:25:03 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.51 2010/12/30 18:27:01 jruoho Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 /* XXX Avoid sensor code (correct option for NetBSD too?) */ 31 #undef SMALL_KERNEL 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/proc.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <machine/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 84 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 99 #ifdef notyet 100 /* 101 * XXX NetBSD: the 6005A replaces the two 6005, above 102 * (see OpenBSD rev 1.96). 103 */ 104 PCI_PRODUCT_INTEL_WIFI_LINK_6005A_2X2_1, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6005A_2X2_2, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_1X1_1, 107 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_1X1_2, 108 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_1, 109 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_2, 110 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_3 111 #endif 112 }; 113 114 /* 115 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 116 */ 117 static const struct ieee80211_rateset iwn_rateset_11a = 118 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 119 120 static const struct ieee80211_rateset iwn_rateset_11b = 121 { 4, { 2, 4, 11, 22 } }; 122 123 static const struct ieee80211_rateset iwn_rateset_11g = 124 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 125 126 static int iwn_match(device_t , struct cfdata *, void *); 127 static void iwn_attach(device_t , device_t , void *); 128 const struct iwn_hal *iwn_hal_attach(struct iwn_softc *, pci_product_id_t pid); 129 #ifndef SMALL_KERNEL 130 static void iwn_sensor_attach(struct iwn_softc *); 131 #endif 132 static void iwn_radiotap_attach(struct iwn_softc *); 133 static int iwn_detach(device_t , int); 134 #if 0 135 static void iwn_power(int, void *); 136 #endif 137 static bool iwn_resume(device_t, const pmf_qual_t *); 138 static int iwn_nic_lock(struct iwn_softc *); 139 static int iwn_eeprom_lock(struct iwn_softc *); 140 static int iwn_init_otprom(struct iwn_softc *); 141 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 142 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 143 void **, bus_size_t, bus_size_t); 144 static void iwn_dma_contig_free(struct iwn_dma_info *); 145 static int iwn_alloc_sched(struct iwn_softc *); 146 static void iwn_free_sched(struct iwn_softc *); 147 static int iwn_alloc_kw(struct iwn_softc *); 148 static void iwn_free_kw(struct iwn_softc *); 149 static int iwn_alloc_ict(struct iwn_softc *); 150 static void iwn_free_ict(struct iwn_softc *); 151 static int iwn_alloc_fwmem(struct iwn_softc *); 152 static void iwn_free_fwmem(struct iwn_softc *); 153 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 154 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 155 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 156 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 157 int); 158 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 159 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 160 static void iwn5000_ict_reset(struct iwn_softc *); 161 static int iwn_read_eeprom(struct iwn_softc *); 162 static void iwn4965_read_eeprom(struct iwn_softc *); 163 #ifdef IWN_DEBUG 164 static void iwn4965_print_power_group(struct iwn_softc *, int); 165 #endif 166 static void iwn5000_read_eeprom(struct iwn_softc *); 167 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 168 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 169 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 170 static void iwn_newassoc(struct ieee80211_node *, int); 171 static int iwn_media_change(struct ifnet *); 172 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 173 static void iwn_iter_func(void *, struct ieee80211_node *); 174 static void iwn_calib_timeout(void *); 175 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 176 struct iwn_rx_data *); 177 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 178 struct iwn_rx_data *); 179 #ifndef IEEE80211_NO_HT 180 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 181 struct iwn_rx_data *); 182 #endif 183 static void iwn5000_rx_calib_results(struct iwn_softc *, 184 struct iwn_rx_desc *, struct iwn_rx_data *); 185 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 186 struct iwn_rx_data *); 187 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 188 struct iwn_rx_data *); 189 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 190 struct iwn_rx_data *); 191 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 192 uint8_t); 193 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 194 static void iwn_notif_intr(struct iwn_softc *); 195 static void iwn_wakeup_intr(struct iwn_softc *); 196 static void iwn_fatal_intr(struct iwn_softc *); 197 static int iwn_intr(void *); 198 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 199 uint16_t); 200 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 201 uint16_t); 202 #ifdef notyet 203 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 204 #endif 205 static int iwn_tx(struct iwn_softc *, struct mbuf *, 206 struct ieee80211_node *, int); 207 static void iwn_start(struct ifnet *); 208 static void iwn_watchdog(struct ifnet *); 209 static int iwn_ioctl(struct ifnet *, u_long, void *); 210 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 211 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 212 int); 213 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 214 int); 215 static int iwn_set_link_quality(struct iwn_softc *, 216 struct ieee80211_node *); 217 static int iwn_add_broadcast_node(struct iwn_softc *, int); 218 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 219 static int iwn_set_critical_temp(struct iwn_softc *); 220 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 221 static void iwn4965_power_calibration(struct iwn_softc *, int); 222 static int iwn4965_set_txpower(struct iwn_softc *, int); 223 static int iwn5000_set_txpower(struct iwn_softc *, int); 224 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 225 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 226 static int iwn_get_noise(const struct iwn_rx_general_stats *); 227 static int iwn4965_get_temperature(struct iwn_softc *); 228 static int iwn5000_get_temperature(struct iwn_softc *); 229 static int iwn_init_sensitivity(struct iwn_softc *); 230 static void iwn_collect_noise(struct iwn_softc *, 231 const struct iwn_rx_general_stats *); 232 static int iwn4965_init_gains(struct iwn_softc *); 233 static int iwn5000_init_gains(struct iwn_softc *); 234 static int iwn4965_set_gains(struct iwn_softc *); 235 static int iwn5000_set_gains(struct iwn_softc *); 236 static void iwn_tune_sensitivity(struct iwn_softc *, 237 const struct iwn_rx_stats *); 238 static int iwn_send_sensitivity(struct iwn_softc *); 239 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 240 static int iwn_config(struct iwn_softc *); 241 static int iwn_scan(struct iwn_softc *, uint16_t); 242 static int iwn_auth(struct iwn_softc *); 243 static int iwn_run(struct iwn_softc *); 244 #ifdef IWN_HWCRYPTO 245 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 246 struct ieee80211_key *); 247 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 248 struct ieee80211_key *); 249 #endif 250 static int iwn_wme_update(struct ieee80211com *); 251 #ifndef IEEE80211_NO_HT 252 static int iwn_ampdu_rx_start(struct ieee80211com *, 253 struct ieee80211_node *, uint8_t); 254 static void iwn_ampdu_rx_stop(struct ieee80211com *, 255 struct ieee80211_node *, uint8_t); 256 static int iwn_ampdu_tx_start(struct ieee80211com *, 257 struct ieee80211_node *, uint8_t); 258 static void iwn_ampdu_tx_stop(struct ieee80211com *, 259 struct ieee80211_node *, uint8_t); 260 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 261 struct ieee80211_node *, uint8_t, uint16_t); 262 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 263 uint8_t, uint16_t); 264 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 265 struct ieee80211_node *, uint8_t, uint16_t); 266 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 267 uint8_t, uint16_t); 268 #endif 269 static int iwn5000_query_calibration(struct iwn_softc *); 270 static int iwn5000_send_calibration(struct iwn_softc *); 271 static int iwn5000_send_wimax_coex(struct iwn_softc *); 272 static int iwn4965_post_alive(struct iwn_softc *); 273 static int iwn5000_post_alive(struct iwn_softc *); 274 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 275 int); 276 static int iwn4965_load_firmware(struct iwn_softc *); 277 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 278 const uint8_t *, int); 279 static int iwn_read_firmware_leg(struct iwn_softc *, 280 struct iwn_fw_info *); 281 static int iwn_read_firmware_tlv(struct iwn_softc *, 282 struct iwn_fw_info *, uint16_t); 283 static int iwn5000_load_firmware(struct iwn_softc *); 284 static int iwn_read_firmware(struct iwn_softc *); 285 static int iwn_clock_wait(struct iwn_softc *); 286 static int iwn_apm_init(struct iwn_softc *); 287 static void iwn_apm_stop_master(struct iwn_softc *); 288 static void iwn_apm_stop(struct iwn_softc *); 289 static int iwn4965_nic_config(struct iwn_softc *); 290 static int iwn5000_nic_config(struct iwn_softc *); 291 static int iwn_hw_prepare(struct iwn_softc *); 292 static int iwn_hw_init(struct iwn_softc *); 293 static void iwn_hw_stop(struct iwn_softc *); 294 static int iwn_init(struct ifnet *); 295 static void iwn_stop(struct ifnet *, int); 296 297 /* XXX MCLGETI alternative */ 298 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 299 struct ifnet *, u_int); 300 #ifdef IWN_USE_RBUF 301 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 302 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 303 static int iwn_alloc_rpool(struct iwn_softc *); 304 static void iwn_free_rpool(struct iwn_softc *); 305 #endif 306 307 /* XXX needed by iwn_scan */ 308 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 309 static u_int8_t *ieee80211_add_rates(u_int8_t *, 310 const struct ieee80211_rateset *); 311 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 312 const struct ieee80211_rateset *); 313 314 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 315 316 #ifdef IWN_DEBUG 317 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 318 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 319 int iwn_debug = 0; 320 #else 321 #define DPRINTF(x) 322 #define DPRINTFN(n, x) 323 #endif 324 325 static const struct iwn_hal iwn4965_hal = { 326 iwn4965_load_firmware, 327 iwn4965_read_eeprom, 328 iwn4965_post_alive, 329 iwn4965_nic_config, 330 iwn4965_update_sched, 331 iwn4965_get_temperature, 332 iwn4965_get_rssi, 333 iwn4965_set_txpower, 334 iwn4965_init_gains, 335 iwn4965_set_gains, 336 iwn4965_add_node, 337 iwn4965_tx_done, 338 #ifndef IEEE80211_NO_HT 339 iwn4965_ampdu_tx_start, 340 iwn4965_ampdu_tx_stop, 341 #endif 342 IWN4965_NTXQUEUES, 343 IWN4965_NDMACHNLS, 344 IWN4965_ID_BROADCAST, 345 IWN4965_RXONSZ, 346 IWN4965_SCHEDSZ, 347 IWN4965_FW_TEXT_MAXSZ, 348 IWN4965_FW_DATA_MAXSZ, 349 IWN4965_FWSZ, 350 IWN4965_SCHED_TXFACT 351 }; 352 353 static const struct iwn_hal iwn5000_hal = { 354 iwn5000_load_firmware, 355 iwn5000_read_eeprom, 356 iwn5000_post_alive, 357 iwn5000_nic_config, 358 iwn5000_update_sched, 359 iwn5000_get_temperature, 360 iwn5000_get_rssi, 361 iwn5000_set_txpower, 362 iwn5000_init_gains, 363 iwn5000_set_gains, 364 iwn5000_add_node, 365 iwn5000_tx_done, 366 #ifndef IEEE80211_NO_HT 367 iwn5000_ampdu_tx_start, 368 iwn5000_ampdu_tx_stop, 369 #endif 370 IWN5000_NTXQUEUES, 371 IWN5000_NDMACHNLS, 372 IWN5000_ID_BROADCAST, 373 IWN5000_RXONSZ, 374 IWN5000_SCHEDSZ, 375 IWN5000_FW_TEXT_MAXSZ, 376 IWN5000_FW_DATA_MAXSZ, 377 IWN5000_FWSZ, 378 IWN5000_SCHED_TXFACT 379 }; 380 381 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 382 iwn_detach, NULL); 383 384 static int 385 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 386 { 387 struct pci_attach_args *pa = aux; 388 size_t i; 389 390 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 391 return 0; 392 393 for (i = 0; i < __arraycount(iwn_devices); i++) 394 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 395 return 1; 396 397 return 0; 398 } 399 400 static void 401 iwn_attach(device_t parent __unused, device_t self, void *aux) 402 { 403 struct iwn_softc *sc = device_private(self); 404 struct ieee80211com *ic = &sc->sc_ic; 405 struct ifnet *ifp = &sc->sc_ec.ec_if; 406 struct pci_attach_args *pa = aux; 407 const struct iwn_hal *hal; 408 const char *intrstr; 409 char devinfo[256]; 410 pci_intr_handle_t ih; 411 pcireg_t memtype, reg; 412 int i, error; 413 int revision; 414 415 sc->sc_dev = self; 416 sc->sc_pct = pa->pa_pc; 417 sc->sc_pcitag = pa->pa_tag; 418 sc->sc_dmat = pa->pa_dmat; 419 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 420 421 callout_init(&sc->calib_to, 0); 422 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 423 424 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 425 revision = PCI_REVISION(pa->pa_class); 426 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 427 428 /* 429 * Get the offset of the PCI Express Capability Structure in PCI 430 * Configuration Space. 431 */ 432 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 433 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 434 if (error == 0) { 435 aprint_error(": PCIe capability structure not found!\n"); 436 return; 437 } 438 439 /* Clear device-specific "PCI retry timeout" register (41h). */ 440 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 441 reg &= ~0xff00; 442 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 443 444 /* Enable bus-mastering and hardware bug workaround. */ 445 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 446 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 447 reg |= PCI_COMMAND_MASTER_ENABLE; 448 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 449 DPRINTF(("PCIe INTx Disable set\n")); 450 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 451 } 452 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 453 454 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 455 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 456 &sc->sc_sh, NULL, &sc->sc_sz); 457 if (error != 0) { 458 aprint_error(": can't map mem space\n"); 459 return; 460 } 461 462 /* Install interrupt handler. */ 463 if (pci_intr_map(pa, &ih) != 0) { 464 aprint_error(": can't map interrupt\n"); 465 return; 466 } 467 intrstr = pci_intr_string(sc->sc_pct, ih); 468 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 469 if (sc->sc_ih == NULL) { 470 aprint_error(": can't establish interrupt"); 471 if (intrstr != NULL) 472 aprint_error(" at %s", intrstr); 473 aprint_error("\n"); 474 return; 475 } 476 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 477 478 /* Attach Hardware Abstraction Layer. */ 479 hal = iwn_hal_attach(sc, PCI_PRODUCT(pa->pa_id)); 480 if (hal == NULL) 481 return; 482 483 if ((error = iwn_hw_prepare(sc)) != 0) { 484 aprint_error(": hardware not ready\n"); 485 return; 486 } 487 488 /* Read MAC address, channels, etc from EEPROM. */ 489 if ((error = iwn_read_eeprom(sc)) != 0) { 490 aprint_error(": could not read EEPROM\n"); 491 return; 492 } 493 494 /* Allocate DMA memory for firmware transfers. */ 495 if ((error = iwn_alloc_fwmem(sc)) != 0) { 496 aprint_error(": could not allocate memory for firmware\n"); 497 return; 498 } 499 500 /* Allocate "Keep Warm" page. */ 501 if ((error = iwn_alloc_kw(sc)) != 0) { 502 aprint_error(": could not allocate keep warm page\n"); 503 goto fail1; 504 } 505 506 /* Allocate ICT table for 5000 Series. */ 507 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 508 (error = iwn_alloc_ict(sc)) != 0) { 509 aprint_error(": could not allocate ICT table\n"); 510 goto fail2; 511 } 512 513 /* Allocate TX scheduler "rings". */ 514 if ((error = iwn_alloc_sched(sc)) != 0) { 515 aprint_error(": could not allocate TX scheduler rings\n"); 516 goto fail3; 517 } 518 519 #ifdef IWN_USE_RBUF 520 /* Allocate RX buffers. */ 521 if ((error = iwn_alloc_rpool(sc)) != 0) { 522 aprint_error_dev(self, "could not allocate RX buffers\n"); 523 goto fail3; 524 } 525 #endif 526 527 /* Allocate TX rings (16 on 4965AGN, 20 on 5000.) */ 528 for (i = 0; i < hal->ntxqs; i++) { 529 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 530 aprint_error(": could not allocate TX ring %d\n", i); 531 goto fail4; 532 } 533 } 534 535 /* Allocate RX ring. */ 536 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 537 aprint_error(": could not allocate RX ring\n"); 538 goto fail4; 539 } 540 541 /* Clear pending interrupts. */ 542 IWN_WRITE(sc, IWN_INT, 0xffffffff); 543 544 /* Count the number of available chains. */ 545 sc->ntxchains = 546 ((sc->txchainmask >> 2) & 1) + 547 ((sc->txchainmask >> 1) & 1) + 548 ((sc->txchainmask >> 0) & 1); 549 sc->nrxchains = 550 ((sc->rxchainmask >> 2) & 1) + 551 ((sc->rxchainmask >> 1) & 1) + 552 ((sc->rxchainmask >> 0) & 1); 553 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 554 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 555 ether_sprintf(ic->ic_myaddr)); 556 557 ic->ic_ifp = ifp; 558 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 559 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 560 ic->ic_state = IEEE80211_S_INIT; 561 562 /* Set device capabilities. */ 563 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 564 * and IEEE80211_C_PMGT too. */ 565 ic->ic_caps = 566 IEEE80211_C_IBSS | /* IBSS mode support */ 567 IEEE80211_C_WPA | /* 802.11i */ 568 IEEE80211_C_MONITOR | /* monitor mode supported */ 569 IEEE80211_C_TXPMGT | /* tx power management */ 570 IEEE80211_C_SHSLOT | /* short slot time supported */ 571 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 572 IEEE80211_C_WME; /* 802.11e */ 573 574 #ifndef IEEE80211_NO_HT 575 /* Set HT capabilities. */ 576 ic->ic_htcaps = 577 #if IWN_RBUF_SIZE == 8192 578 IEEE80211_HTCAP_AMSDU7935 | 579 #endif 580 IEEE80211_HTCAP_CBW20_40 | 581 IEEE80211_HTCAP_SGI20 | 582 IEEE80211_HTCAP_SGI40; 583 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 584 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 585 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 586 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 587 else 588 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 589 #endif /* !IEEE80211_NO_HT */ 590 591 /* Set supported legacy rates. */ 592 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 593 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 594 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 595 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 596 } 597 #ifndef IEEE80211_NO_HT 598 /* Set supported HT rates. */ 599 ic->ic_sup_mcs[0] = 0xff; 600 if (sc->nrxchains > 1) /* MCS 0-7 */ 601 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 602 if (sc->nrxchains > 2) 603 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 604 #endif 605 606 /* IBSS channel undefined for now. */ 607 ic->ic_ibss_chan = &ic->ic_channels[0]; 608 609 ifp->if_softc = sc; 610 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 611 ifp->if_init = iwn_init; 612 ifp->if_ioctl = iwn_ioctl; 613 ifp->if_start = iwn_start; 614 ifp->if_stop = iwn_stop; 615 ifp->if_watchdog = iwn_watchdog; 616 IFQ_SET_READY(&ifp->if_snd); 617 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 618 619 if_attach(ifp); 620 ieee80211_ifattach(ic); 621 ic->ic_node_alloc = iwn_node_alloc; 622 ic->ic_newassoc = iwn_newassoc; 623 #ifdef IWN_HWCRYPTO 624 ic->ic_crypto.cs_key_set = iwn_set_key; 625 ic->ic_crypto.cs_key_delete = iwn_delete_key; 626 #endif 627 ic->ic_wme.wme_update = iwn_wme_update; 628 #ifndef IEEE80211_NO_HT 629 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 630 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 631 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 632 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 633 #endif 634 635 /* Override 802.11 state transition machine. */ 636 sc->sc_newstate = ic->ic_newstate; 637 ic->ic_newstate = iwn_newstate; 638 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 639 640 sc->amrr.amrr_min_success_threshold = 1; 641 sc->amrr.amrr_max_success_threshold = 15; 642 643 #ifndef SMALL_KERNEL 644 iwn_sensor_attach(sc); 645 #endif 646 iwn_radiotap_attach(sc); 647 648 /* 649 * XXX for NetBSD, OpenBSD timeout_set replaced by 650 * callout_init and callout_setfunc, above. 651 */ 652 653 if (pmf_device_register(self, NULL, iwn_resume)) 654 pmf_class_network_register(self, ifp); 655 else 656 aprint_error_dev(self, "couldn't establish power handler\n"); 657 658 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 659 ieee80211_announce(ic); 660 661 return; 662 663 /* Free allocated memory if something failed during attachment. */ 664 fail4: while (--i >= 0) 665 iwn_free_tx_ring(sc, &sc->txq[i]); 666 #ifdef IWN_USE_RBUF 667 iwn_free_rpool(sc); 668 #endif 669 iwn_free_sched(sc); 670 fail3: if (sc->ict != NULL) 671 iwn_free_ict(sc); 672 fail2: iwn_free_kw(sc); 673 fail1: iwn_free_fwmem(sc); 674 } 675 676 const struct iwn_hal * 677 iwn_hal_attach(struct iwn_softc *sc, pci_product_id_t pid) 678 { 679 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 680 681 switch (sc->hw_type) { 682 case IWN_HW_REV_TYPE_4965: 683 sc->sc_hal = &iwn4965_hal; 684 sc->limits = &iwn4965_sensitivity_limits; 685 sc->fwname = "iwlwifi-4965-2.ucode"; 686 sc->txchainmask = IWN_ANT_AB; 687 sc->rxchainmask = IWN_ANT_ABC; 688 break; 689 case IWN_HW_REV_TYPE_5100: 690 sc->sc_hal = &iwn5000_hal; 691 sc->limits = &iwn5000_sensitivity_limits; 692 sc->fwname = "iwlwifi-5000-2.ucode"; 693 sc->txchainmask = IWN_ANT_B; 694 sc->rxchainmask = IWN_ANT_AB; 695 break; 696 case IWN_HW_REV_TYPE_5150: 697 sc->sc_hal = &iwn5000_hal; 698 sc->limits = &iwn5150_sensitivity_limits; 699 sc->fwname = "iwlwifi-5150-2.ucode"; 700 sc->txchainmask = IWN_ANT_A; 701 sc->rxchainmask = IWN_ANT_AB; 702 break; 703 case IWN_HW_REV_TYPE_5300: 704 case IWN_HW_REV_TYPE_5350: 705 sc->sc_hal = &iwn5000_hal; 706 sc->limits = &iwn5000_sensitivity_limits; 707 sc->fwname = "iwlwifi-5000-2.ucode"; 708 sc->txchainmask = IWN_ANT_ABC; 709 sc->rxchainmask = IWN_ANT_ABC; 710 break; 711 case IWN_HW_REV_TYPE_1000: 712 sc->sc_hal = &iwn5000_hal; 713 sc->limits = &iwn1000_sensitivity_limits; 714 sc->fwname = "iwlwifi-1000-3.ucode"; 715 sc->txchainmask = IWN_ANT_A; 716 sc->rxchainmask = IWN_ANT_AB; 717 break; 718 case IWN_HW_REV_TYPE_6000: 719 sc->sc_hal = &iwn5000_hal; 720 sc->limits = &iwn6000_sensitivity_limits; 721 sc->fwname = "iwlwifi-6000-4.ucode"; 722 switch (pid) { 723 case PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1: 724 case PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2: 725 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 726 sc->txchainmask = IWN_ANT_BC; 727 sc->rxchainmask = IWN_ANT_BC; 728 break; 729 default: 730 sc->txchainmask = IWN_ANT_ABC; 731 sc->rxchainmask = IWN_ANT_ABC; 732 break; 733 } 734 break; 735 case IWN_HW_REV_TYPE_6050: 736 sc->sc_hal = &iwn5000_hal; 737 sc->limits = &iwn6000_sensitivity_limits; 738 sc->fwname = "iwlwifi-6050-2.ucode"; 739 sc->txchainmask = IWN_ANT_AB; 740 sc->rxchainmask = IWN_ANT_AB; 741 break; 742 case IWN_HW_REV_TYPE_6005: 743 sc->sc_hal = &iwn5000_hal; 744 sc->limits = &iwn6000_sensitivity_limits; 745 sc->fwname = "iwlwifi-6005-2.ucode"; 746 sc->txchainmask = IWN_ANT_AB; 747 sc->rxchainmask = IWN_ANT_AB; 748 break; 749 default: 750 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 751 return NULL; 752 } 753 return sc->sc_hal; 754 } 755 756 #ifndef SMALL_KERNEL 757 /* 758 * Attach the adapter on-board thermal sensor to the sensors framework. 759 */ 760 static void 761 iwn_sensor_attach(struct iwn_softc *sc) 762 { 763 int error; 764 765 sc->sc_sensor.units = ENVSYS_STEMP; 766 #if 0 767 /* XXX something like this ought to work */ 768 sc->sc_sensor.flags = ENVSYS_FMONLIMITS | ENVSYS_FMONNOTSUPP; 769 sc->sc_sensor.limits.sel_critmax = IWN_CTOK(110); 770 #endif 771 strlcpy((sc->sc_sensor.desc), "TEMP", sizeof(sc->sc_sensor.desc)); 772 773 /* Temperature is not valid unless interface is up. */ 774 sc->sc_sensor.value_cur = 0; 775 sc->sc_sensor.state = ENVSYS_SINVALID; 776 777 sc->sc_sme = sysmon_envsys_create(); 778 779 /* Initialize sensor */ 780 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 781 sysmon_envsys_destroy(sc->sc_sme); 782 return; 783 } 784 785 /* 786 * Hook into the System Monitor. 787 */ 788 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 789 sc->sc_sme->sme_flags = SME_DISABLE_REFRESH; 790 791 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 792 aprint_error_dev(sc->sc_dev, 793 "unable to register with sysmon (%d)\n", error); 794 sysmon_envsys_destroy(sc->sc_sme); 795 return; 796 } 797 } 798 #endif 799 800 /* 801 * Attach the interface to 802.11 radiotap. 802 */ 803 static void 804 iwn_radiotap_attach(struct iwn_softc *sc) 805 { 806 struct ifnet *ifp = sc->sc_ic.ic_ifp; 807 808 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 809 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 810 &sc->sc_drvbpf); 811 812 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 813 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 814 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 815 816 sc->sc_txtap_len = sizeof sc->sc_txtapu; 817 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 818 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 819 } 820 821 static int 822 iwn_detach(device_t self, int flags __unused) 823 { 824 struct iwn_softc *sc = device_private(self); 825 struct ifnet *ifp = sc->sc_ic.ic_ifp; 826 int qid; 827 828 callout_stop(&sc->calib_to); 829 830 /* Uninstall interrupt handler. */ 831 if (sc->sc_ih != NULL) 832 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 833 834 /* Free DMA resources. */ 835 iwn_free_rx_ring(sc, &sc->rxq); 836 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) 837 iwn_free_tx_ring(sc, &sc->txq[qid]); 838 #ifdef IWN_USE_RBUF 839 iwn_free_rpool(sc); 840 #endif 841 iwn_free_sched(sc); 842 iwn_free_kw(sc); 843 if (sc->ict != NULL) 844 iwn_free_ict(sc); 845 iwn_free_fwmem(sc); 846 847 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 848 849 #ifndef SMALL_KERNEL 850 /* Detach the thermal sensor. */ 851 sysmon_envsys_sensor_detach(sc->sc_sme, &sc->sc_sensor); 852 sysmon_envsys_destroy(sc->sc_sme); 853 #endif 854 855 ieee80211_ifdetach(&sc->sc_ic); 856 if_detach(ifp); 857 858 return 0; 859 } 860 861 #if 0 862 /* 863 * XXX Investigate if clearing the PCI retry timeout could eliminate 864 * the repeated scan calls. Also the calls to if_init and if_start 865 * are similar to the effect of adding the call to ifioctl_common . 866 */ 867 static void 868 iwn_power(int why, void *arg) 869 { 870 struct iwn_softc *sc = arg; 871 struct ifnet *ifp; 872 pcireg_t reg; 873 int s; 874 875 if (why != PWR_RESUME) 876 return; 877 878 /* Clear device-specific "PCI retry timeout" register (41h). */ 879 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 880 reg &= ~0xff00; 881 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg); 882 883 s = splnet(); 884 ifp = &sc->sc_ic.ic_if; 885 if (ifp->if_flags & IFF_UP) { 886 ifp->if_init(ifp); 887 if (ifp->if_flags & IFF_RUNNING) 888 ifp->if_start(ifp); 889 } 890 splx(s); 891 } 892 #endif 893 894 static bool 895 iwn_resume(device_t dv, const pmf_qual_t *qual) 896 { 897 return true; 898 } 899 900 static int 901 iwn_nic_lock(struct iwn_softc *sc) 902 { 903 int ntries; 904 905 /* Request exclusive access to NIC. */ 906 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 907 908 /* Spin until we actually get the lock. */ 909 for (ntries = 0; ntries < 1000; ntries++) { 910 if ((IWN_READ(sc, IWN_GP_CNTRL) & 911 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 912 IWN_GP_CNTRL_MAC_ACCESS_ENA) 913 return 0; 914 DELAY(10); 915 } 916 return ETIMEDOUT; 917 } 918 919 static __inline void 920 iwn_nic_unlock(struct iwn_softc *sc) 921 { 922 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 923 } 924 925 static __inline uint32_t 926 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 927 { 928 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 929 IWN_BARRIER_READ_WRITE(sc); 930 return IWN_READ(sc, IWN_PRPH_RDATA); 931 } 932 933 static __inline void 934 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 935 { 936 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 937 IWN_BARRIER_WRITE(sc); 938 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 939 } 940 941 static __inline void 942 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 943 { 944 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 945 } 946 947 static __inline void 948 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 949 { 950 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 951 } 952 953 static __inline void 954 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 955 const uint32_t *data, int count) 956 { 957 for (; count > 0; count--, data++, addr += 4) 958 iwn_prph_write(sc, addr, *data); 959 } 960 961 static __inline uint32_t 962 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 963 { 964 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 965 IWN_BARRIER_READ_WRITE(sc); 966 return IWN_READ(sc, IWN_MEM_RDATA); 967 } 968 969 static __inline void 970 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 971 { 972 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 973 IWN_BARRIER_WRITE(sc); 974 IWN_WRITE(sc, IWN_MEM_WDATA, data); 975 } 976 977 static __inline void 978 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 979 { 980 uint32_t tmp; 981 982 tmp = iwn_mem_read(sc, addr & ~3); 983 if (addr & 3) 984 tmp = (tmp & 0x0000ffff) | data << 16; 985 else 986 tmp = (tmp & 0xffff0000) | data; 987 iwn_mem_write(sc, addr & ~3, tmp); 988 } 989 990 static __inline void 991 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 992 int count) 993 { 994 for (; count > 0; count--, addr += 4) 995 *data++ = iwn_mem_read(sc, addr); 996 } 997 998 static __inline void 999 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1000 int count) 1001 { 1002 for (; count > 0; count--, addr += 4) 1003 iwn_mem_write(sc, addr, val); 1004 } 1005 1006 static int 1007 iwn_eeprom_lock(struct iwn_softc *sc) 1008 { 1009 int i, ntries; 1010 1011 for (i = 0; i < 100; i++) { 1012 /* Request exclusive access to EEPROM. */ 1013 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1014 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1015 1016 /* Spin until we actually get the lock. */ 1017 for (ntries = 0; ntries < 100; ntries++) { 1018 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1019 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1020 return 0; 1021 DELAY(10); 1022 } 1023 } 1024 return ETIMEDOUT; 1025 } 1026 1027 static __inline void 1028 iwn_eeprom_unlock(struct iwn_softc *sc) 1029 { 1030 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1031 } 1032 1033 /* 1034 * Initialize access by host to One Time Programmable ROM. 1035 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1036 */ 1037 static int 1038 iwn_init_otprom(struct iwn_softc *sc) 1039 { 1040 uint16_t prev = 0, base, next; 1041 int count, error; 1042 1043 /* Wait for clock stabilization before accessing prph. */ 1044 if ((error = iwn_clock_wait(sc)) != 0) 1045 return error; 1046 1047 if ((error = iwn_nic_lock(sc)) != 0) 1048 return error; 1049 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1050 DELAY(5); 1051 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1052 iwn_nic_unlock(sc); 1053 1054 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1055 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1056 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1057 IWN_RESET_LINK_PWR_MGMT_DIS); 1058 } 1059 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1060 /* Clear ECC status. */ 1061 IWN_SETBITS(sc, IWN_OTP_GP, 1062 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1063 1064 /* 1065 * Find the block before last block (contains the EEPROM image) 1066 * for HW without OTP shadow RAM. 1067 */ 1068 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1069 /* Switch to absolute addressing mode. */ 1070 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1071 base = 0; 1072 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1073 error = iwn_read_prom_data(sc, base, &next, 2); 1074 if (error != 0) 1075 return error; 1076 if (next == 0) /* End of linked-list. */ 1077 break; 1078 prev = base; 1079 base = le16toh(next); 1080 } 1081 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1082 return EIO; 1083 /* Skip "next" word. */ 1084 sc->prom_base = prev + 1; 1085 } 1086 return 0; 1087 } 1088 1089 static int 1090 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1091 { 1092 uint8_t *out = data; 1093 uint32_t val, tmp; 1094 int ntries; 1095 1096 addr += sc->prom_base; 1097 for (; count > 0; count -= 2, addr++) { 1098 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1099 for (ntries = 0; ntries < 10; ntries++) { 1100 val = IWN_READ(sc, IWN_EEPROM); 1101 if (val & IWN_EEPROM_READ_VALID) 1102 break; 1103 DELAY(5); 1104 } 1105 if (ntries == 10) { 1106 aprint_error_dev(sc->sc_dev, 1107 "timeout reading ROM at 0x%x\n", addr); 1108 return ETIMEDOUT; 1109 } 1110 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1111 /* OTPROM, check for ECC errors. */ 1112 tmp = IWN_READ(sc, IWN_OTP_GP); 1113 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1114 aprint_error_dev(sc->sc_dev, 1115 "OTPROM ECC error at 0x%x\n", addr); 1116 return EIO; 1117 } 1118 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1119 /* Correctable ECC error, clear bit. */ 1120 IWN_SETBITS(sc, IWN_OTP_GP, 1121 IWN_OTP_GP_ECC_CORR_STTS); 1122 } 1123 } 1124 *out++ = val >> 16; 1125 if (count > 1) 1126 *out++ = val >> 24; 1127 } 1128 return 0; 1129 } 1130 1131 static int 1132 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1133 bus_size_t size, bus_size_t alignment) 1134 { 1135 int nsegs, error; 1136 1137 dma->tag = tag; 1138 dma->size = size; 1139 1140 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1141 &dma->map); 1142 if (error != 0) 1143 goto fail; 1144 1145 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1146 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1147 if (error != 0) 1148 goto fail; 1149 1150 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1151 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1152 if (error != 0) 1153 goto fail; 1154 1155 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1156 BUS_DMA_NOWAIT); 1157 if (error != 0) 1158 goto fail; 1159 1160 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1161 memset(dma->vaddr, 0, size); 1162 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1163 1164 dma->paddr = dma->map->dm_segs[0].ds_addr; 1165 if (kvap != NULL) 1166 *kvap = dma->vaddr; 1167 1168 return 0; 1169 1170 fail: iwn_dma_contig_free(dma); 1171 return error; 1172 } 1173 1174 static void 1175 iwn_dma_contig_free(struct iwn_dma_info *dma) 1176 { 1177 if (dma->map != NULL) { 1178 if (dma->vaddr != NULL) { 1179 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1180 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1181 bus_dmamap_unload(dma->tag, dma->map); 1182 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1183 bus_dmamem_free(dma->tag, &dma->seg, 1); 1184 dma->vaddr = NULL; 1185 } 1186 bus_dmamap_destroy(dma->tag, dma->map); 1187 dma->map = NULL; 1188 } 1189 } 1190 1191 static int 1192 iwn_alloc_sched(struct iwn_softc *sc) 1193 { 1194 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1195 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1196 (void **)&sc->sched, sc->sc_hal->schedsz, 1024); 1197 } 1198 1199 static void 1200 iwn_free_sched(struct iwn_softc *sc) 1201 { 1202 iwn_dma_contig_free(&sc->sched_dma); 1203 } 1204 1205 static int 1206 iwn_alloc_kw(struct iwn_softc *sc) 1207 { 1208 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1209 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1210 4096); 1211 } 1212 1213 static void 1214 iwn_free_kw(struct iwn_softc *sc) 1215 { 1216 iwn_dma_contig_free(&sc->kw_dma); 1217 } 1218 1219 static int 1220 iwn_alloc_ict(struct iwn_softc *sc) 1221 { 1222 /* ICT table must be aligned on a 4KB boundary. */ 1223 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1224 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1225 } 1226 1227 static void 1228 iwn_free_ict(struct iwn_softc *sc) 1229 { 1230 iwn_dma_contig_free(&sc->ict_dma); 1231 } 1232 1233 static int 1234 iwn_alloc_fwmem(struct iwn_softc *sc) 1235 { 1236 /* Must be aligned on a 16-byte boundary. */ 1237 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1238 sc->sc_hal->fwsz, 16); 1239 } 1240 1241 static void 1242 iwn_free_fwmem(struct iwn_softc *sc) 1243 { 1244 iwn_dma_contig_free(&sc->fw_dma); 1245 } 1246 1247 static int 1248 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1249 { 1250 bus_size_t size; 1251 int i, error; 1252 1253 ring->cur = 0; 1254 1255 /* Allocate RX descriptors (256-byte aligned.) */ 1256 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1257 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1258 (void **)&ring->desc, size, 256); 1259 if (error != 0) { 1260 aprint_error_dev(sc->sc_dev, 1261 "could not allocate RX ring DMA memory\n"); 1262 goto fail; 1263 } 1264 1265 /* Allocate RX status area (16-byte aligned.) */ 1266 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1267 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1268 if (error != 0) { 1269 aprint_error_dev(sc->sc_dev, 1270 "could not allocate RX status DMA memory\n"); 1271 goto fail; 1272 } 1273 1274 /* 1275 * Allocate and map RX buffers. 1276 */ 1277 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1278 struct iwn_rx_data *data = &ring->data[i]; 1279 1280 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1281 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1282 &data->map); 1283 if (error != 0) { 1284 aprint_error_dev(sc->sc_dev, 1285 "could not create RX buf DMA map\n"); 1286 goto fail; 1287 } 1288 1289 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1290 if (data->m == NULL) { 1291 aprint_error_dev(sc->sc_dev, 1292 "could not allocate RX mbuf\n"); 1293 error = ENOBUFS; 1294 goto fail; 1295 } 1296 1297 error = bus_dmamap_load(sc->sc_dmat, data->map, 1298 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1299 BUS_DMA_NOWAIT | BUS_DMA_READ); 1300 if (error != 0) { 1301 aprint_error_dev(sc->sc_dev, 1302 "can't not map mbuf (error %d)\n", error); 1303 goto fail; 1304 } 1305 1306 /* Set physical address of RX buffer (256-byte aligned.) */ 1307 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1308 } 1309 1310 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1311 BUS_DMASYNC_PREWRITE); 1312 1313 return 0; 1314 1315 fail: iwn_free_rx_ring(sc, ring); 1316 return error; 1317 } 1318 1319 static void 1320 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1321 { 1322 int ntries; 1323 1324 if (iwn_nic_lock(sc) == 0) { 1325 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1326 for (ntries = 0; ntries < 1000; ntries++) { 1327 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1328 IWN_FH_RX_STATUS_IDLE) 1329 break; 1330 DELAY(10); 1331 } 1332 iwn_nic_unlock(sc); 1333 } 1334 ring->cur = 0; 1335 sc->last_rx_valid = 0; 1336 } 1337 1338 static void 1339 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1340 { 1341 int i; 1342 1343 iwn_dma_contig_free(&ring->desc_dma); 1344 iwn_dma_contig_free(&ring->stat_dma); 1345 1346 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1347 struct iwn_rx_data *data = &ring->data[i]; 1348 1349 if (data->m != NULL) { 1350 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1351 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1352 bus_dmamap_unload(sc->sc_dmat, data->map); 1353 m_freem(data->m); 1354 } 1355 if (data->map != NULL) 1356 bus_dmamap_destroy(sc->sc_dmat, data->map); 1357 } 1358 } 1359 1360 static int 1361 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1362 { 1363 bus_addr_t paddr; 1364 bus_size_t size; 1365 int i, error; 1366 1367 ring->qid = qid; 1368 ring->queued = 0; 1369 ring->cur = 0; 1370 1371 /* Allocate TX descriptors (256-byte aligned.) */ 1372 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1373 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1374 (void **)&ring->desc, size, 256); 1375 if (error != 0) { 1376 aprint_error_dev(sc->sc_dev, 1377 "could not allocate TX ring DMA memory\n"); 1378 goto fail; 1379 } 1380 /* 1381 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1382 * to allocate commands space for other rings. 1383 * XXX Do we really need to allocate descriptors for other rings? 1384 */ 1385 if (qid > 4) 1386 return 0; 1387 1388 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1389 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1390 (void **)&ring->cmd, size, 4); 1391 if (error != 0) { 1392 aprint_error_dev(sc->sc_dev, 1393 "could not allocate TX cmd DMA memory\n"); 1394 goto fail; 1395 } 1396 1397 paddr = ring->cmd_dma.paddr; 1398 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1399 struct iwn_tx_data *data = &ring->data[i]; 1400 1401 data->cmd_paddr = paddr; 1402 data->scratch_paddr = paddr + 12; 1403 paddr += sizeof (struct iwn_tx_cmd); 1404 1405 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1406 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1407 &data->map); 1408 if (error != 0) { 1409 aprint_error_dev(sc->sc_dev, 1410 "could not create TX buf DMA map\n"); 1411 goto fail; 1412 } 1413 } 1414 return 0; 1415 1416 fail: iwn_free_tx_ring(sc, ring); 1417 return error; 1418 } 1419 1420 static void 1421 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1422 { 1423 int i; 1424 1425 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1426 struct iwn_tx_data *data = &ring->data[i]; 1427 1428 if (data->m != NULL) { 1429 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1430 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1431 bus_dmamap_unload(sc->sc_dmat, data->map); 1432 m_freem(data->m); 1433 data->m = NULL; 1434 } 1435 } 1436 /* Clear TX descriptors. */ 1437 memset(ring->desc, 0, ring->desc_dma.size); 1438 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1439 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1440 sc->qfullmsk &= ~(1 << ring->qid); 1441 ring->queued = 0; 1442 ring->cur = 0; 1443 } 1444 1445 static void 1446 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1447 { 1448 int i; 1449 1450 iwn_dma_contig_free(&ring->desc_dma); 1451 iwn_dma_contig_free(&ring->cmd_dma); 1452 1453 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1454 struct iwn_tx_data *data = &ring->data[i]; 1455 1456 if (data->m != NULL) { 1457 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1458 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1459 bus_dmamap_unload(sc->sc_dmat, data->map); 1460 m_freem(data->m); 1461 } 1462 if (data->map != NULL) 1463 bus_dmamap_destroy(sc->sc_dmat, data->map); 1464 } 1465 } 1466 1467 static void 1468 iwn5000_ict_reset(struct iwn_softc *sc) 1469 { 1470 /* Disable interrupts. */ 1471 IWN_WRITE(sc, IWN_INT_MASK, 0); 1472 1473 /* Reset ICT table. */ 1474 memset(sc->ict, 0, IWN_ICT_SIZE); 1475 sc->ict_cur = 0; 1476 1477 /* Set physical address of ICT table (4KB aligned.) */ 1478 DPRINTF(("enabling ICT\n")); 1479 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1480 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1481 1482 /* Enable periodic RX interrupt. */ 1483 sc->int_mask |= IWN_INT_RX_PERIODIC; 1484 /* Switch to ICT interrupt mode in driver. */ 1485 sc->sc_flags |= IWN_FLAG_USE_ICT; 1486 1487 /* Re-enable interrupts. */ 1488 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1489 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1490 } 1491 1492 static int 1493 iwn_read_eeprom(struct iwn_softc *sc) 1494 { 1495 const struct iwn_hal *hal = sc->sc_hal; 1496 struct ieee80211com *ic = &sc->sc_ic; 1497 uint16_t val; 1498 int error; 1499 1500 /* Check whether adapter has an EEPROM or an OTPROM. */ 1501 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1502 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1503 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1504 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1505 "OTPROM" : "EEPROM")); 1506 1507 /* Adapter has to be powered on for EEPROM access to work. */ 1508 if ((error = iwn_apm_init(sc)) != 0) { 1509 aprint_error_dev(sc->sc_dev, 1510 "could not power ON adapter\n"); 1511 return error; 1512 } 1513 1514 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1515 aprint_error_dev(sc->sc_dev, 1516 "bad ROM signature\n"); 1517 return EIO; 1518 } 1519 if ((error = iwn_eeprom_lock(sc)) != 0) { 1520 aprint_error_dev(sc->sc_dev, 1521 "could not lock ROM (error=%d)\n", error); 1522 return error; 1523 } 1524 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1525 if ((error = iwn_init_otprom(sc)) != 0) { 1526 aprint_error_dev(sc->sc_dev, 1527 "could not initialize OTPROM\n"); 1528 return error; 1529 } 1530 } 1531 1532 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1533 sc->rfcfg = le16toh(val); 1534 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1535 1536 /* Read MAC address. */ 1537 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1538 1539 /* Read adapter-specific information from EEPROM. */ 1540 hal->read_eeprom(sc); 1541 1542 iwn_apm_stop(sc); /* Power OFF adapter. */ 1543 1544 iwn_eeprom_unlock(sc); 1545 return 0; 1546 } 1547 1548 static void 1549 iwn4965_read_eeprom(struct iwn_softc *sc) 1550 { 1551 uint32_t addr; 1552 uint16_t val; 1553 int i; 1554 1555 /* Read regulatory domain (4 ASCII characters.) */ 1556 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1557 1558 /* Read the list of authorized channels (20MHz ones only.) */ 1559 for (i = 0; i < 5; i++) { 1560 addr = iwn4965_regulatory_bands[i]; 1561 iwn_read_eeprom_channels(sc, i, addr); 1562 } 1563 1564 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1565 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1566 sc->maxpwr2GHz = val & 0xff; 1567 sc->maxpwr5GHz = val >> 8; 1568 /* Check that EEPROM values are within valid range. */ 1569 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1570 sc->maxpwr5GHz = 38; 1571 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1572 sc->maxpwr2GHz = 38; 1573 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1574 1575 /* Read samples for each TX power group. */ 1576 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1577 sizeof sc->bands); 1578 1579 /* Read voltage at which samples were taken. */ 1580 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1581 sc->eeprom_voltage = (int16_t)le16toh(val); 1582 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1583 1584 #ifdef IWN_DEBUG 1585 /* Print samples. */ 1586 if (iwn_debug > 0) { 1587 for (i = 0; i < IWN_NBANDS; i++) 1588 iwn4965_print_power_group(sc, i); 1589 } 1590 #endif 1591 } 1592 1593 #ifdef IWN_DEBUG 1594 static void 1595 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1596 { 1597 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1598 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1599 int j, c; 1600 1601 aprint_normal("===band %d===\n", i); 1602 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1603 aprint_normal("chan1 num=%d\n", chans[0].num); 1604 for (c = 0; c < 2; c++) { 1605 for (j = 0; j < IWN_NSAMPLES; j++) { 1606 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1607 "power=%d pa_det=%d\n", c, j, 1608 chans[0].samples[c][j].temp, 1609 chans[0].samples[c][j].gain, 1610 chans[0].samples[c][j].power, 1611 chans[0].samples[c][j].pa_det); 1612 } 1613 } 1614 aprint_normal("chan2 num=%d\n", chans[1].num); 1615 for (c = 0; c < 2; c++) { 1616 for (j = 0; j < IWN_NSAMPLES; j++) { 1617 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1618 "power=%d pa_det=%d\n", c, j, 1619 chans[1].samples[c][j].temp, 1620 chans[1].samples[c][j].gain, 1621 chans[1].samples[c][j].power, 1622 chans[1].samples[c][j].pa_det); 1623 } 1624 } 1625 } 1626 #endif 1627 1628 static void 1629 iwn5000_read_eeprom(struct iwn_softc *sc) 1630 { 1631 struct iwn5000_eeprom_calib_hdr hdr; 1632 int32_t temp, volt; 1633 uint32_t base, addr; 1634 uint16_t val; 1635 int i; 1636 1637 /* Read regulatory domain (4 ASCII characters.) */ 1638 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1639 base = le16toh(val); 1640 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1641 sc->eeprom_domain, 4); 1642 1643 /* Read the list of authorized channels (20MHz ones only.) */ 1644 for (i = 0; i < 5; i++) { 1645 addr = base + iwn5000_regulatory_bands[i]; 1646 iwn_read_eeprom_channels(sc, i, addr); 1647 } 1648 1649 /* Read enhanced TX power information for 6000 Series. */ 1650 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1651 iwn_read_eeprom_enhinfo(sc); 1652 1653 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1654 base = le16toh(val); 1655 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1656 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1657 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1658 sc->calib_ver = hdr.version; 1659 1660 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1661 /* Compute temperature offset. */ 1662 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1663 temp = le16toh(val); 1664 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1665 volt = le16toh(val); 1666 sc->temp_off = temp - (volt / -5); 1667 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1668 temp, volt, sc->temp_off)); 1669 } else { 1670 /* Read crystal calibration. */ 1671 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1672 &sc->eeprom_crystal, sizeof (uint32_t)); 1673 DPRINTF(("crystal calibration 0x%08x\n", 1674 le32toh(sc->eeprom_crystal))); 1675 } 1676 } 1677 1678 static void 1679 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1680 { 1681 struct ieee80211com *ic = &sc->sc_ic; 1682 const struct iwn_chan_band *band = &iwn_bands[n]; 1683 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1684 uint8_t chan; 1685 int i; 1686 1687 iwn_read_prom_data(sc, addr, channels, 1688 band->nchan * sizeof (struct iwn_eeprom_chan)); 1689 1690 for (i = 0; i < band->nchan; i++) { 1691 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1692 continue; 1693 1694 chan = band->chan[i]; 1695 1696 if (n == 0) { /* 2GHz band */ 1697 ic->ic_channels[chan].ic_freq = 1698 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1699 ic->ic_channels[chan].ic_flags = 1700 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1701 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1702 1703 } else { /* 5GHz band */ 1704 /* 1705 * Some adapters support channels 7, 8, 11 and 12 1706 * both in the 2GHz and 4.9GHz bands. 1707 * Because of limitations in our net80211 layer, 1708 * we don't support them in the 4.9GHz band. 1709 */ 1710 if (chan <= 14) 1711 continue; 1712 1713 ic->ic_channels[chan].ic_freq = 1714 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1715 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1716 /* We have at least one valid 5GHz channel. */ 1717 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1718 } 1719 1720 /* Is active scan allowed on this channel? */ 1721 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1722 ic->ic_channels[chan].ic_flags |= 1723 IEEE80211_CHAN_PASSIVE; 1724 } 1725 1726 /* Save maximum allowed TX power for this channel. */ 1727 sc->maxpwr[chan] = channels[i].maxpwr; 1728 1729 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1730 chan, channels[i].flags, sc->maxpwr[chan])); 1731 } 1732 } 1733 1734 static void 1735 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1736 { 1737 struct iwn_eeprom_enhinfo enhinfo[35]; 1738 uint16_t val, base; 1739 int8_t maxpwr; 1740 int i; 1741 1742 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1743 base = le16toh(val); 1744 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1745 enhinfo, sizeof enhinfo); 1746 1747 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1748 for (i = 0; i < __arraycount(enhinfo); i++) { 1749 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1750 continue; /* Skip invalid entries. */ 1751 1752 maxpwr = 0; 1753 if (sc->txchainmask & IWN_ANT_A) 1754 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1755 if (sc->txchainmask & IWN_ANT_B) 1756 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1757 if (sc->txchainmask & IWN_ANT_C) 1758 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1759 if (sc->ntxchains == 2) 1760 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1761 else if (sc->ntxchains == 3) 1762 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1763 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1764 1765 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1766 sc->enh_maxpwr[i] = maxpwr; 1767 } 1768 } 1769 1770 static struct ieee80211_node * 1771 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1772 { 1773 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1774 } 1775 1776 static void 1777 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1778 { 1779 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1780 struct iwn_node *wn = (void *)ni; 1781 uint8_t rate; 1782 int ridx, i; 1783 1784 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1785 /* Start at lowest available bit-rate, AMRR will raise. */ 1786 ni->ni_txrate = 0; 1787 1788 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1789 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1790 /* Map 802.11 rate to HW rate index. */ 1791 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1792 if (iwn_rates[ridx].rate == rate) 1793 break; 1794 wn->ridx[i] = ridx; 1795 } 1796 } 1797 1798 static int 1799 iwn_media_change(struct ifnet *ifp) 1800 { 1801 struct iwn_softc *sc = ifp->if_softc; 1802 struct ieee80211com *ic = &sc->sc_ic; 1803 uint8_t rate, ridx; 1804 int error; 1805 1806 error = ieee80211_media_change(ifp); 1807 if (error != ENETRESET) 1808 return error; 1809 1810 if (ic->ic_fixed_rate != -1) { 1811 rate = ic->ic_sup_rates[ic->ic_curmode]. 1812 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1813 /* Map 802.11 rate to HW rate index. */ 1814 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1815 if (iwn_rates[ridx].rate == rate) 1816 break; 1817 sc->fixed_ridx = ridx; 1818 } 1819 1820 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1821 (IFF_UP | IFF_RUNNING)) { 1822 iwn_stop(ifp, 0); 1823 error = iwn_init(ifp); 1824 } 1825 return error; 1826 } 1827 1828 static int 1829 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1830 { 1831 struct ifnet *ifp = ic->ic_ifp; 1832 struct iwn_softc *sc = ifp->if_softc; 1833 int error; 1834 1835 callout_stop(&sc->calib_to); 1836 1837 switch (nstate) { 1838 case IEEE80211_S_SCAN: 1839 /* XXX Do not abort a running scan. */ 1840 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1841 if (ic->ic_state != nstate) 1842 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1843 "while scanning(%d) ignored\n", nstate, 1844 ic->ic_state); 1845 break; 1846 } 1847 1848 /* XXX Not sure if call and flags are needed. */ 1849 ieee80211_node_table_reset(&ic->ic_scan); 1850 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1851 sc->sc_flags |= IWN_FLAG_SCANNING; 1852 1853 /* Make the link LED blink while we're scanning. */ 1854 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1855 1856 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1857 aprint_error_dev(sc->sc_dev, 1858 "could not initiate scan\n"); 1859 return error; 1860 } 1861 ic->ic_state = nstate; 1862 return 0; 1863 1864 case IEEE80211_S_ASSOC: 1865 if (ic->ic_state != IEEE80211_S_RUN) 1866 break; 1867 /* FALLTHROUGH */ 1868 case IEEE80211_S_AUTH: 1869 /* Reset state to handle reassociations correctly. */ 1870 sc->rxon.associd = 0; 1871 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1872 sc->calib.state = IWN_CALIB_STATE_INIT; 1873 1874 if ((error = iwn_auth(sc)) != 0) { 1875 aprint_error_dev(sc->sc_dev, 1876 "could not move to auth state\n"); 1877 return error; 1878 } 1879 break; 1880 1881 case IEEE80211_S_RUN: 1882 if ((error = iwn_run(sc)) != 0) { 1883 aprint_error_dev(sc->sc_dev, 1884 "could not move to run state\n"); 1885 return error; 1886 } 1887 break; 1888 1889 case IEEE80211_S_INIT: 1890 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1891 sc->calib.state = IWN_CALIB_STATE_INIT; 1892 break; 1893 } 1894 1895 return sc->sc_newstate(ic, nstate, arg); 1896 } 1897 1898 static void 1899 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1900 { 1901 struct iwn_softc *sc = arg; 1902 struct iwn_node *wn = (struct iwn_node *)ni; 1903 1904 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1905 } 1906 1907 static void 1908 iwn_calib_timeout(void *arg) 1909 { 1910 struct iwn_softc *sc = arg; 1911 struct ieee80211com *ic = &sc->sc_ic; 1912 int s; 1913 1914 s = splnet(); 1915 if (ic->ic_fixed_rate == -1) { 1916 if (ic->ic_opmode == IEEE80211_M_STA) 1917 iwn_iter_func(sc, ic->ic_bss); 1918 else 1919 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1920 } 1921 /* Force automatic TX power calibration every 60 secs. */ 1922 if (++sc->calib_cnt >= 120) { 1923 uint32_t flags = 0; 1924 1925 DPRINTF(("sending request for statistics\n")); 1926 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1927 sizeof flags, 1); 1928 sc->calib_cnt = 0; 1929 } 1930 splx(s); 1931 1932 /* Automatic rate control triggered every 500ms. */ 1933 callout_schedule(&sc->calib_to, hz/2); 1934 } 1935 1936 /* 1937 * Process an RX_PHY firmware notification. This is usually immediately 1938 * followed by an MPDU_RX_DONE notification. 1939 */ 1940 static void 1941 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1942 struct iwn_rx_data *data) 1943 { 1944 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1945 1946 DPRINTFN(2, ("received PHY stats\n")); 1947 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1948 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1949 1950 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1951 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1952 sc->last_rx_valid = 1; 1953 } 1954 1955 /* 1956 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1957 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1958 */ 1959 static void 1960 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1961 struct iwn_rx_data *data) 1962 { 1963 const struct iwn_hal *hal = sc->sc_hal; 1964 struct ieee80211com *ic = &sc->sc_ic; 1965 struct ifnet *ifp = ic->ic_ifp; 1966 struct iwn_rx_ring *ring = &sc->rxq; 1967 struct ieee80211_frame *wh; 1968 struct ieee80211_node *ni; 1969 struct mbuf *m, *m1; 1970 struct iwn_rx_stat *stat; 1971 char *head; 1972 uint32_t flags; 1973 int error, len, rssi; 1974 1975 if (desc->type == IWN_MPDU_RX_DONE) { 1976 /* Check for prior RX_PHY notification. */ 1977 if (!sc->last_rx_valid) { 1978 DPRINTF(("missing RX_PHY\n")); 1979 ifp->if_ierrors++; 1980 return; 1981 } 1982 sc->last_rx_valid = 0; 1983 stat = &sc->last_rx_stat; 1984 } else 1985 stat = (struct iwn_rx_stat *)(desc + 1); 1986 1987 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1988 BUS_DMASYNC_POSTREAD); 1989 1990 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1991 aprint_error_dev(sc->sc_dev, 1992 "invalid RX statistic header\n"); 1993 ifp->if_ierrors++; 1994 return; 1995 } 1996 if (desc->type == IWN_MPDU_RX_DONE) { 1997 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1998 head = (char *)(mpdu + 1); 1999 len = le16toh(mpdu->len); 2000 } else { 2001 head = (char *)(stat + 1) + stat->cfg_phy_len; 2002 len = le16toh(stat->len); 2003 } 2004 2005 flags = le32toh(*(uint32_t *)(head + len)); 2006 2007 /* Discard frames with a bad FCS early. */ 2008 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2009 DPRINTFN(2, ("RX flags error %x\n", flags)); 2010 ifp->if_ierrors++; 2011 return; 2012 } 2013 /* Discard frames that are too short. */ 2014 if (len < sizeof (*wh)) { 2015 DPRINTF(("frame too short: %d\n", len)); 2016 ic->ic_stats.is_rx_tooshort++; 2017 ifp->if_ierrors++; 2018 return; 2019 } 2020 2021 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2022 if (m1 == NULL) { 2023 ic->ic_stats.is_rx_nobuf++; 2024 ifp->if_ierrors++; 2025 return; 2026 } 2027 bus_dmamap_unload(sc->sc_dmat, data->map); 2028 2029 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2030 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2031 if (error != 0) { 2032 m_freem(m1); 2033 2034 /* Try to reload the old mbuf. */ 2035 error = bus_dmamap_load(sc->sc_dmat, data->map, 2036 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2037 BUS_DMA_NOWAIT | BUS_DMA_READ); 2038 if (error != 0) { 2039 panic("%s: could not load old RX mbuf", 2040 device_xname(sc->sc_dev)); 2041 } 2042 /* Physical address may have changed. */ 2043 ring->desc[ring->cur] = 2044 htole32(data->map->dm_segs[0].ds_addr >> 8); 2045 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2046 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2047 BUS_DMASYNC_PREWRITE); 2048 ifp->if_ierrors++; 2049 return; 2050 } 2051 2052 m = data->m; 2053 data->m = m1; 2054 /* Update RX descriptor. */ 2055 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2056 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2057 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2058 BUS_DMASYNC_PREWRITE); 2059 2060 /* Finalize mbuf. */ 2061 m->m_pkthdr.rcvif = ifp; 2062 m->m_data = head; 2063 m->m_pkthdr.len = m->m_len = len; 2064 2065 /* Grab a reference to the source node. */ 2066 wh = mtod(m, struct ieee80211_frame *); 2067 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2068 2069 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2070 /* NetBSD does decryption in ieee80211_input. */ 2071 2072 rssi = hal->get_rssi(stat); 2073 2074 /* XXX Added for NetBSD: scans never stop without it */ 2075 if (ic->ic_state == IEEE80211_S_SCAN) 2076 iwn_fix_channel(ic, m); 2077 2078 if (sc->sc_drvbpf != NULL) { 2079 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2080 2081 tap->wr_flags = 0; 2082 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2083 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2084 tap->wr_chan_freq = 2085 htole16(ic->ic_channels[stat->chan].ic_freq); 2086 tap->wr_chan_flags = 2087 htole16(ic->ic_channels[stat->chan].ic_flags); 2088 tap->wr_dbm_antsignal = (int8_t)rssi; 2089 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2090 tap->wr_tsft = stat->tstamp; 2091 switch (stat->rate) { 2092 /* CCK rates. */ 2093 case 10: tap->wr_rate = 2; break; 2094 case 20: tap->wr_rate = 4; break; 2095 case 55: tap->wr_rate = 11; break; 2096 case 110: tap->wr_rate = 22; break; 2097 /* OFDM rates. */ 2098 case 0xd: tap->wr_rate = 12; break; 2099 case 0xf: tap->wr_rate = 18; break; 2100 case 0x5: tap->wr_rate = 24; break; 2101 case 0x7: tap->wr_rate = 36; break; 2102 case 0x9: tap->wr_rate = 48; break; 2103 case 0xb: tap->wr_rate = 72; break; 2104 case 0x1: tap->wr_rate = 96; break; 2105 case 0x3: tap->wr_rate = 108; break; 2106 /* Unknown rate: should not happen. */ 2107 default: tap->wr_rate = 0; 2108 } 2109 2110 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2111 } 2112 2113 /* Send the frame to the 802.11 layer. */ 2114 ieee80211_input(ic, m, ni, rssi, 0); 2115 2116 /* Node is no longer needed. */ 2117 ieee80211_free_node(ni); 2118 } 2119 2120 #ifndef IEEE80211_NO_HT 2121 /* Process an incoming Compressed BlockAck. */ 2122 static void 2123 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2124 struct iwn_rx_data *data) 2125 { 2126 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2127 struct iwn_tx_ring *txq; 2128 2129 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2130 BUS_DMASYNC_POSTREAD); 2131 2132 txq = &sc->txq[le16toh(ba->qid)]; 2133 /* XXX TBD */ 2134 } 2135 #endif 2136 2137 /* 2138 * Process a CALIBRATION_RESULT notification sent by the initialization 2139 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.) 2140 */ 2141 static void 2142 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2143 struct iwn_rx_data *data) 2144 { 2145 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2146 int len, idx = -1; 2147 2148 /* Runtime firmware should not send such a notification. */ 2149 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2150 return; 2151 2152 len = (le32toh(desc->len) & 0x3fff) - 4; 2153 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2154 BUS_DMASYNC_POSTREAD); 2155 2156 switch (calib->code) { 2157 case IWN5000_PHY_CALIB_DC: 2158 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2159 sc->hw_type == IWN_HW_REV_TYPE_6050) 2160 idx = 0; 2161 break; 2162 case IWN5000_PHY_CALIB_LO: 2163 idx = 1; 2164 break; 2165 case IWN5000_PHY_CALIB_TX_IQ: 2166 idx = 2; 2167 break; 2168 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2169 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2170 sc->hw_type != IWN_HW_REV_TYPE_5150) 2171 idx = 3; 2172 break; 2173 case IWN5000_PHY_CALIB_BASE_BAND: 2174 idx = 4; 2175 break; 2176 } 2177 if (idx == -1) /* Ignore other results. */ 2178 return; 2179 2180 /* Save calibration result. */ 2181 if (sc->calibcmd[idx].buf != NULL) 2182 free(sc->calibcmd[idx].buf, M_DEVBUF); 2183 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2184 if (sc->calibcmd[idx].buf == NULL) { 2185 DPRINTF(("not enough memory for calibration result %d\n", 2186 calib->code)); 2187 return; 2188 } 2189 DPRINTF(("saving calibration result code=%d len=%d\n", 2190 calib->code, len)); 2191 sc->calibcmd[idx].len = len; 2192 memcpy(sc->calibcmd[idx].buf, calib, len); 2193 } 2194 2195 /* 2196 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2197 * The latter is sent by the firmware after each received beacon. 2198 */ 2199 static void 2200 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2201 struct iwn_rx_data *data) 2202 { 2203 const struct iwn_hal *hal = sc->sc_hal; 2204 struct ieee80211com *ic = &sc->sc_ic; 2205 struct iwn_calib_state *calib = &sc->calib; 2206 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2207 int temp; 2208 2209 /* Ignore statistics received during a scan. */ 2210 if (ic->ic_state != IEEE80211_S_RUN) 2211 return; 2212 2213 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2214 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2215 2216 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2217 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2218 2219 /* Test if temperature has changed. */ 2220 if (stats->general.temp != sc->rawtemp) { 2221 /* Convert "raw" temperature to degC. */ 2222 sc->rawtemp = stats->general.temp; 2223 temp = hal->get_temperature(sc); 2224 DPRINTFN(2, ("temperature=%dC\n", temp)); 2225 2226 #ifndef SMALL_KERNEL 2227 /* Update temperature sensor. */ 2228 sc->sc_sensor.value_cur = IWN_CTOMUK(temp); 2229 sc->sc_sensor.state = ENVSYS_SVALID; 2230 #endif 2231 2232 /* Update TX power if need be (4965AGN only.) */ 2233 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2234 iwn4965_power_calibration(sc, temp); 2235 } 2236 2237 if (desc->type != IWN_BEACON_STATISTICS) 2238 return; /* Reply to a statistics request. */ 2239 2240 sc->noise = iwn_get_noise(&stats->rx.general); 2241 2242 /* Test that RSSI and noise are present in stats report. */ 2243 if (le32toh(stats->rx.general.flags) != 1) { 2244 DPRINTF(("received statistics without RSSI\n")); 2245 return; 2246 } 2247 2248 if (calib->state == IWN_CALIB_STATE_ASSOC) 2249 iwn_collect_noise(sc, &stats->rx.general); 2250 else if (calib->state == IWN_CALIB_STATE_RUN) 2251 iwn_tune_sensitivity(sc, &stats->rx); 2252 } 2253 2254 /* 2255 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2256 * and 5000 adapters have different incompatible TX status formats. 2257 */ 2258 static void 2259 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2260 struct iwn_rx_data *data) 2261 { 2262 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2263 2264 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2265 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2266 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2267 } 2268 2269 static void 2270 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2271 struct iwn_rx_data *data) 2272 { 2273 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2274 2275 #ifdef notyet 2276 /* Reset TX scheduler slot. */ 2277 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2278 #endif 2279 2280 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2281 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2282 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2283 } 2284 2285 /* 2286 * Adapter-independent backend for TX_DONE firmware notifications. 2287 */ 2288 static void 2289 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2290 uint8_t status) 2291 { 2292 struct ieee80211com *ic = &sc->sc_ic; 2293 struct ifnet *ifp = ic->ic_ifp; 2294 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2295 struct iwn_tx_data *data = &ring->data[desc->idx]; 2296 struct iwn_node *wn = (struct iwn_node *)data->ni; 2297 2298 /* Update rate control statistics. */ 2299 wn->amn.amn_txcnt++; 2300 if (ackfailcnt > 0) 2301 wn->amn.amn_retrycnt++; 2302 2303 if (status != 1 && status != 2) 2304 ifp->if_oerrors++; 2305 else 2306 ifp->if_opackets++; 2307 2308 /* Unmap and free mbuf. */ 2309 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2310 BUS_DMASYNC_POSTWRITE); 2311 bus_dmamap_unload(sc->sc_dmat, data->map); 2312 m_freem(data->m); 2313 data->m = NULL; 2314 ieee80211_free_node(data->ni); 2315 data->ni = NULL; 2316 2317 sc->sc_tx_timer = 0; 2318 if (--ring->queued < IWN_TX_RING_LOMARK) { 2319 sc->qfullmsk &= ~(1 << ring->qid); 2320 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2321 ifp->if_flags &= ~IFF_OACTIVE; 2322 (*ifp->if_start)(ifp); 2323 } 2324 } 2325 } 2326 2327 /* 2328 * Process a "command done" firmware notification. This is where we wakeup 2329 * processes waiting for a synchronous command completion. 2330 */ 2331 static void 2332 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2333 { 2334 struct iwn_tx_ring *ring = &sc->txq[4]; 2335 struct iwn_tx_data *data; 2336 2337 if ((desc->qid & 0xf) != 4) 2338 return; /* Not a command ack. */ 2339 2340 data = &ring->data[desc->idx]; 2341 2342 /* If the command was mapped in an mbuf, free it. */ 2343 if (data->m != NULL) { 2344 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2345 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2346 bus_dmamap_unload(sc->sc_dmat, data->map); 2347 m_freem(data->m); 2348 data->m = NULL; 2349 } 2350 wakeup(&ring->desc[desc->idx]); 2351 } 2352 2353 /* 2354 * Process an INT_FH_RX or INT_SW_RX interrupt. 2355 */ 2356 static void 2357 iwn_notif_intr(struct iwn_softc *sc) 2358 { 2359 struct ieee80211com *ic = &sc->sc_ic; 2360 struct ifnet *ifp = ic->ic_ifp; 2361 uint16_t hw; 2362 2363 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2364 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2365 2366 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2367 while (sc->rxq.cur != hw) { 2368 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2369 struct iwn_rx_desc *desc; 2370 2371 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2372 BUS_DMASYNC_POSTREAD); 2373 desc = mtod(data->m, struct iwn_rx_desc *); 2374 2375 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2376 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2377 2378 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2379 iwn_cmd_done(sc, desc); 2380 2381 switch (desc->type) { 2382 case IWN_RX_PHY: 2383 iwn_rx_phy(sc, desc, data); 2384 break; 2385 2386 case IWN_RX_DONE: /* 4965AGN only. */ 2387 case IWN_MPDU_RX_DONE: 2388 /* An 802.11 frame has been received. */ 2389 iwn_rx_done(sc, desc, data); 2390 break; 2391 #ifndef IEEE80211_NO_HT 2392 case IWN_RX_COMPRESSED_BA: 2393 /* A Compressed BlockAck has been received. */ 2394 iwn_rx_compressed_ba(sc, desc, data); 2395 break; 2396 #endif 2397 case IWN_TX_DONE: 2398 /* An 802.11 frame has been transmitted. */ 2399 sc->sc_hal->tx_done(sc, desc, data); 2400 break; 2401 2402 case IWN_RX_STATISTICS: 2403 case IWN_BEACON_STATISTICS: 2404 iwn_rx_statistics(sc, desc, data); 2405 break; 2406 2407 case IWN_BEACON_MISSED: 2408 { 2409 struct iwn_beacon_missed *miss = 2410 (struct iwn_beacon_missed *)(desc + 1); 2411 2412 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2413 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2414 /* 2415 * If more than 5 consecutive beacons are missed, 2416 * reinitialize the sensitivity state machine. 2417 */ 2418 DPRINTF(("beacons missed %d/%d\n", 2419 le32toh(miss->consecutive), le32toh(miss->total))); 2420 if (ic->ic_state == IEEE80211_S_RUN && 2421 le32toh(miss->consecutive) > 5) 2422 (void)iwn_init_sensitivity(sc); 2423 break; 2424 } 2425 case IWN_UC_READY: 2426 { 2427 struct iwn_ucode_info *uc = 2428 (struct iwn_ucode_info *)(desc + 1); 2429 2430 /* The microcontroller is ready. */ 2431 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2432 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2433 DPRINTF(("microcode alive notification version=%d.%d " 2434 "subtype=%x alive=%x\n", uc->major, uc->minor, 2435 uc->subtype, le32toh(uc->valid))); 2436 2437 if (le32toh(uc->valid) != 1) { 2438 aprint_error_dev(sc->sc_dev, 2439 "microcontroller initialization " 2440 "failed\n"); 2441 break; 2442 } 2443 if (uc->subtype == IWN_UCODE_INIT) { 2444 /* Save microcontroller report. */ 2445 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2446 } 2447 /* Save the address of the error log in SRAM. */ 2448 sc->errptr = le32toh(uc->errptr); 2449 break; 2450 } 2451 case IWN_STATE_CHANGED: 2452 { 2453 uint32_t *status = (uint32_t *)(desc + 1); 2454 2455 /* Enabled/disabled notification. */ 2456 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2457 sizeof (*status), BUS_DMASYNC_POSTREAD); 2458 DPRINTF(("state changed to %x\n", le32toh(*status))); 2459 2460 if (le32toh(*status) & 1) { 2461 /* The radio button has to be pushed. */ 2462 aprint_error_dev(sc->sc_dev, 2463 "Radio transmitter is off\n"); 2464 /* Turn the interface down. */ 2465 ifp->if_flags &= ~IFF_UP; 2466 iwn_stop(ifp, 1); 2467 return; /* No further processing. */ 2468 } 2469 break; 2470 } 2471 case IWN_START_SCAN: 2472 { 2473 struct iwn_start_scan *scan = 2474 (struct iwn_start_scan *)(desc + 1); 2475 2476 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2477 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2478 DPRINTFN(2, ("scanning channel %d status %x\n", 2479 scan->chan, le32toh(scan->status))); 2480 2481 /* Fix current channel. */ 2482 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2483 break; 2484 } 2485 case IWN_STOP_SCAN: 2486 { 2487 struct iwn_stop_scan *scan = 2488 (struct iwn_stop_scan *)(desc + 1); 2489 2490 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2491 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2492 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2493 scan->nchan, scan->status, scan->chan)); 2494 2495 if (scan->status == 1 && scan->chan <= 14 && 2496 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2497 /* 2498 * We just finished scanning 2GHz channels, 2499 * start scanning 5GHz ones. 2500 */ 2501 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2502 break; 2503 } 2504 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2505 ieee80211_end_scan(ic); 2506 break; 2507 } 2508 case IWN5000_CALIBRATION_RESULT: 2509 iwn5000_rx_calib_results(sc, desc, data); 2510 break; 2511 2512 case IWN5000_CALIBRATION_DONE: 2513 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2514 wakeup(sc); 2515 break; 2516 } 2517 2518 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2519 } 2520 2521 /* Tell the firmware what we have processed. */ 2522 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2523 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2524 } 2525 2526 /* 2527 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2528 * from power-down sleep mode. 2529 */ 2530 static void 2531 iwn_wakeup_intr(struct iwn_softc *sc) 2532 { 2533 int qid; 2534 2535 DPRINTF(("ucode wakeup from power-down sleep\n")); 2536 2537 /* Wakeup RX and TX rings. */ 2538 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2539 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) { 2540 struct iwn_tx_ring *ring = &sc->txq[qid]; 2541 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2542 } 2543 } 2544 2545 /* 2546 * Dump the error log of the firmware when a firmware panic occurs. Although 2547 * we can't debug the firmware because it is neither open source nor free, it 2548 * can help us to identify certain classes of problems. 2549 */ 2550 static void 2551 iwn_fatal_intr(struct iwn_softc *sc) 2552 { 2553 const struct iwn_hal *hal = sc->sc_hal; 2554 struct iwn_fw_dump dump; 2555 int i; 2556 2557 /* Force a complete recalibration on next init. */ 2558 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2559 2560 /* Check that the error log address is valid. */ 2561 if (sc->errptr < IWN_FW_DATA_BASE || 2562 sc->errptr + sizeof (dump) > 2563 IWN_FW_DATA_BASE + hal->fw_data_maxsz) { 2564 aprint_error_dev(sc->sc_dev, 2565 "bad firmware error log address 0x%08x\n", sc->errptr); 2566 return; 2567 } 2568 if (iwn_nic_lock(sc) != 0) { 2569 aprint_error_dev(sc->sc_dev, 2570 "could not read firmware error log\n"); 2571 return; 2572 } 2573 /* Read firmware error log from SRAM. */ 2574 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2575 sizeof (dump) / sizeof (uint32_t)); 2576 iwn_nic_unlock(sc); 2577 2578 if (dump.valid == 0) { 2579 aprint_error_dev(sc->sc_dev, 2580 "firmware error log is empty\n"); 2581 return; 2582 } 2583 aprint_error("firmware error log:\n"); 2584 aprint_error(" error type = \"%s\" (0x%08X)\n", 2585 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2586 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2587 dump.id); 2588 aprint_error(" program counter = 0x%08X\n", dump.pc); 2589 aprint_error(" source line = 0x%08X\n", dump.src_line); 2590 aprint_error(" error data = 0x%08X%08X\n", 2591 dump.error_data[0], dump.error_data[1]); 2592 aprint_error(" branch link = 0x%08X%08X\n", 2593 dump.branch_link[0], dump.branch_link[1]); 2594 aprint_error(" interrupt link = 0x%08X%08X\n", 2595 dump.interrupt_link[0], dump.interrupt_link[1]); 2596 aprint_error(" time = %u\n", dump.time[0]); 2597 2598 /* Dump driver status (TX and RX rings) while we're here. */ 2599 aprint_error("driver status:\n"); 2600 for (i = 0; i < hal->ntxqs; i++) { 2601 struct iwn_tx_ring *ring = &sc->txq[i]; 2602 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2603 i, ring->qid, ring->cur, ring->queued); 2604 } 2605 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2606 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2607 } 2608 2609 static int 2610 iwn_intr(void *arg) 2611 { 2612 struct iwn_softc *sc = arg; 2613 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2614 uint32_t r1, r2, tmp; 2615 2616 /* Disable interrupts. */ 2617 IWN_WRITE(sc, IWN_INT_MASK, 0); 2618 2619 /* Read interrupts from ICT (fast) or from registers (slow). */ 2620 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2621 tmp = 0; 2622 while (sc->ict[sc->ict_cur] != 0) { 2623 tmp |= sc->ict[sc->ict_cur]; 2624 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2625 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2626 } 2627 tmp = le32toh(tmp); 2628 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2629 tmp = 0; 2630 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2631 tmp |= 0x8000; 2632 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2633 r2 = 0; /* Unused. */ 2634 } else { 2635 r1 = IWN_READ(sc, IWN_INT); 2636 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2637 return 0; /* Hardware gone! */ 2638 r2 = IWN_READ(sc, IWN_FH_INT); 2639 } 2640 if (r1 == 0 && r2 == 0) { 2641 if (ifp->if_flags & IFF_UP) 2642 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2643 return 0; /* Interrupt not for us. */ 2644 } 2645 2646 /* Acknowledge interrupts. */ 2647 IWN_WRITE(sc, IWN_INT, r1); 2648 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2649 IWN_WRITE(sc, IWN_FH_INT, r2); 2650 2651 if (r1 & IWN_INT_RF_TOGGLED) { 2652 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2653 aprint_error_dev(sc->sc_dev, 2654 "RF switch: radio %s\n", 2655 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2656 } 2657 if (r1 & IWN_INT_CT_REACHED) { 2658 aprint_error_dev(sc->sc_dev, 2659 "critical temperature reached!\n"); 2660 } 2661 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2662 aprint_error_dev(sc->sc_dev, 2663 "fatal firmware error\n"); 2664 /* Dump firmware error log and stop. */ 2665 iwn_fatal_intr(sc); 2666 ifp->if_flags &= ~IFF_UP; 2667 iwn_stop(ifp, 1); 2668 return 1; 2669 } 2670 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2671 (r2 & IWN_FH_INT_RX)) { 2672 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2673 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2674 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2675 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2676 IWN_INT_PERIODIC_DIS); 2677 iwn_notif_intr(sc); 2678 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2679 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2680 IWN_INT_PERIODIC_ENA); 2681 } 2682 } else 2683 iwn_notif_intr(sc); 2684 } 2685 2686 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2687 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2688 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2689 wakeup(sc); /* FH DMA transfer completed. */ 2690 } 2691 2692 if (r1 & IWN_INT_ALIVE) 2693 wakeup(sc); /* Firmware is alive. */ 2694 2695 if (r1 & IWN_INT_WAKEUP) 2696 iwn_wakeup_intr(sc); 2697 2698 /* Re-enable interrupts. */ 2699 if (ifp->if_flags & IFF_UP) 2700 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2701 2702 return 1; 2703 } 2704 2705 /* 2706 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2707 * 5000 adapters use a slightly different format.) 2708 */ 2709 static void 2710 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2711 uint16_t len) 2712 { 2713 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2714 2715 *w = htole16(len + 8); 2716 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2717 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2718 sizeof (uint16_t), 2719 BUS_DMASYNC_PREWRITE); 2720 if (idx < IWN_SCHED_WINSZ) { 2721 *(w + IWN_TX_RING_COUNT) = *w; 2722 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2723 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2724 (char *)(void *)sc->sched_dma.vaddr, 2725 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2726 } 2727 } 2728 2729 static void 2730 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2731 uint16_t len) 2732 { 2733 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2734 2735 *w = htole16(id << 12 | (len + 8)); 2736 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2737 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2738 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2739 if (idx < IWN_SCHED_WINSZ) { 2740 *(w + IWN_TX_RING_COUNT) = *w; 2741 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2742 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2743 (char *)(void *)sc->sched_dma.vaddr, 2744 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2745 } 2746 } 2747 2748 #ifdef notyet 2749 static void 2750 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2751 { 2752 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2753 2754 *w = (*w & htole16(0xf000)) | htole16(1); 2755 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2756 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2757 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2758 if (idx < IWN_SCHED_WINSZ) { 2759 *(w + IWN_TX_RING_COUNT) = *w; 2760 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2761 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2762 (char *)(void *)sc->sched_dma.vaddr, 2763 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2764 } 2765 } 2766 #endif 2767 2768 static int 2769 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2770 { 2771 const struct iwn_hal *hal = sc->sc_hal; 2772 struct ieee80211com *ic = &sc->sc_ic; 2773 struct iwn_node *wn = (void *)ni; 2774 struct iwn_tx_ring *ring; 2775 struct iwn_tx_desc *desc; 2776 struct iwn_tx_data *data; 2777 struct iwn_tx_cmd *cmd; 2778 struct iwn_cmd_data *tx; 2779 const struct iwn_rate *rinfo; 2780 struct ieee80211_frame *wh; 2781 struct ieee80211_key *k = NULL; 2782 struct mbuf *m1; 2783 uint32_t flags; 2784 u_int hdrlen; 2785 bus_dma_segment_t *seg; 2786 uint8_t tid, ridx, txant, type; 2787 int i, totlen, error, pad; 2788 2789 const struct chanAccParams *cap; 2790 int noack; 2791 int hdrlen2; 2792 2793 wh = mtod(m, struct ieee80211_frame *); 2794 hdrlen = ieee80211_anyhdrsize(wh); 2795 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2796 2797 hdrlen2 = (IEEE80211_QOS_HAS_SEQ(wh)) ? 2798 sizeof (struct ieee80211_qosframe) : 2799 sizeof (struct ieee80211_frame); 2800 2801 if (hdrlen != hdrlen2) 2802 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2803 hdrlen, hdrlen2); 2804 2805 /* XXX OpenBSD sets a different tid when using QOS */ 2806 tid = 0; 2807 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2808 cap = &ic->ic_wme.wme_chanParams; 2809 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2810 } 2811 else 2812 noack = 0; 2813 2814 ring = &sc->txq[ac]; 2815 desc = &ring->desc[ring->cur]; 2816 data = &ring->data[ring->cur]; 2817 2818 /* Choose a TX rate index. */ 2819 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2820 type != IEEE80211_FC0_TYPE_DATA) { 2821 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2822 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2823 } else if (ic->ic_fixed_rate != -1) { 2824 ridx = sc->fixed_ridx; 2825 } else 2826 ridx = wn->ridx[ni->ni_txrate]; 2827 rinfo = &iwn_rates[ridx]; 2828 2829 /* Encrypt the frame if need be. */ 2830 /* 2831 * XXX For now, NetBSD swaps the encryption and bpf sections 2832 * in order to match old code and other drivers. Tests with 2833 * tcpdump indicates that the order is irrelevant, however, 2834 * as bpf produces unencrypted data for both ordering choices. 2835 */ 2836 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2837 k = ieee80211_crypto_encap(ic, ni, m); 2838 if (k == NULL) { 2839 m_freem(m); 2840 return ENOBUFS; 2841 } 2842 /* Packet header may have moved, reset our local pointer. */ 2843 wh = mtod(m, struct ieee80211_frame *); 2844 } 2845 totlen = m->m_pkthdr.len; 2846 2847 if (sc->sc_drvbpf != NULL) { 2848 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2849 2850 tap->wt_flags = 0; 2851 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2852 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2853 tap->wt_rate = rinfo->rate; 2854 tap->wt_hwqueue = ac; 2855 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2856 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2857 2858 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2859 } 2860 2861 /* Prepare TX firmware command. */ 2862 cmd = &ring->cmd[ring->cur]; 2863 cmd->code = IWN_CMD_TX_DATA; 2864 cmd->flags = 0; 2865 cmd->qid = ring->qid; 2866 cmd->idx = ring->cur; 2867 2868 tx = (struct iwn_cmd_data *)cmd->data; 2869 /* NB: No need to clear tx, all fields are reinitialized here. */ 2870 tx->scratch = 0; /* clear "scratch" area */ 2871 2872 flags = 0; 2873 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2874 /* Unicast frame, check if an ACK is expected. */ 2875 if (!noack) 2876 flags |= IWN_TX_NEED_ACK; 2877 } 2878 2879 #ifdef notyet 2880 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2881 if ((wh->i_fc[0] & 2882 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2883 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2884 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2885 #endif 2886 2887 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2888 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2889 2890 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2891 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2892 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2893 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2894 flags |= IWN_TX_NEED_RTS; 2895 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2896 ridx >= IWN_RIDX_OFDM6) { 2897 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2898 flags |= IWN_TX_NEED_CTS; 2899 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2900 flags |= IWN_TX_NEED_RTS; 2901 } 2902 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2903 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2904 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2905 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2906 flags |= IWN_TX_NEED_PROTECTION; 2907 } else 2908 flags |= IWN_TX_FULL_TXOP; 2909 } 2910 } 2911 2912 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2913 type != IEEE80211_FC0_TYPE_DATA) 2914 tx->id = hal->broadcast_id; 2915 else 2916 tx->id = wn->id; 2917 2918 if (type == IEEE80211_FC0_TYPE_MGT) { 2919 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2920 2921 #ifndef IEEE80211_STA_ONLY 2922 /* Tell HW to set timestamp in probe responses. */ 2923 /* XXX NetBSD rev 1.11 added probe requests here but */ 2924 /* probe requests do not take timestamps (from Bergamini). */ 2925 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2926 flags |= IWN_TX_INSERT_TSTAMP; 2927 #endif 2928 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2929 /* changes here. These are not needed (from Bergamini). */ 2930 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2931 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2932 tx->timeout = htole16(3); 2933 else 2934 tx->timeout = htole16(2); 2935 } else 2936 tx->timeout = htole16(0); 2937 2938 if (hdrlen & 3) { 2939 /* First segment's length must be a multiple of 4. */ 2940 flags |= IWN_TX_NEED_PADDING; 2941 pad = 4 - (hdrlen & 3); 2942 } else 2943 pad = 0; 2944 2945 tx->len = htole16(totlen); 2946 tx->tid = tid; 2947 tx->rts_ntries = 60; 2948 tx->data_ntries = 15; 2949 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2950 tx->plcp = rinfo->plcp; 2951 tx->rflags = rinfo->flags; 2952 if (tx->id == hal->broadcast_id) { 2953 /* Group or management frame. */ 2954 tx->linkq = 0; 2955 /* XXX Alternate between antenna A and B? */ 2956 txant = IWN_LSB(sc->txchainmask); 2957 tx->rflags |= IWN_RFLAG_ANT(txant); 2958 } else { 2959 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2960 flags |= IWN_TX_LINKQ; /* enable MRR */ 2961 } 2962 /* Set physical address of "scratch area". */ 2963 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2964 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2965 2966 /* Copy 802.11 header in TX command. */ 2967 /* XXX NetBSD changed this in rev 1.20 */ 2968 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2969 2970 /* Trim 802.11 header. */ 2971 m_adj(m, hdrlen); 2972 tx->security = 0; 2973 tx->flags = htole32(flags); 2974 2975 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2976 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2977 if (error != 0) { 2978 if (error != EFBIG) { 2979 aprint_error_dev(sc->sc_dev, 2980 "can't map mbuf (error %d)\n", error); 2981 m_freem(m); 2982 return error; 2983 } 2984 /* Too many DMA segments, linearize mbuf. */ 2985 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2986 if (m1 == NULL) { 2987 m_freem(m); 2988 return ENOBUFS; 2989 } 2990 if (m->m_pkthdr.len > MHLEN) { 2991 MCLGET(m1, M_DONTWAIT); 2992 if (!(m1->m_flags & M_EXT)) { 2993 m_freem(m); 2994 m_freem(m1); 2995 return ENOBUFS; 2996 } 2997 } 2998 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2999 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3000 m_freem(m); 3001 m = m1; 3002 3003 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3004 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3005 if (error != 0) { 3006 aprint_error_dev(sc->sc_dev, 3007 "can't map mbuf (error %d)\n", error); 3008 m_freem(m); 3009 return error; 3010 } 3011 } 3012 3013 data->m = m; 3014 data->ni = ni; 3015 3016 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3017 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3018 3019 /* Fill TX descriptor. */ 3020 desc->nsegs = 1 + data->map->dm_nsegs; 3021 /* First DMA segment is used by the TX command. */ 3022 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3023 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3024 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3025 /* Other DMA segments are for data payload. */ 3026 seg = data->map->dm_segs; 3027 for (i = 1; i <= data->map->dm_nsegs; i++) { 3028 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3029 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3030 seg->ds_len << 4); 3031 seg++; 3032 } 3033 3034 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3035 BUS_DMASYNC_PREWRITE); 3036 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3037 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3038 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3039 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3040 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3041 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3042 3043 #ifdef notyet 3044 /* Update TX scheduler. */ 3045 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3046 #endif 3047 3048 /* Kick TX ring. */ 3049 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3050 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3051 3052 /* Mark TX ring as full if we reach a certain threshold. */ 3053 if (++ring->queued > IWN_TX_RING_HIMARK) 3054 sc->qfullmsk |= 1 << ring->qid; 3055 3056 return 0; 3057 } 3058 3059 static void 3060 iwn_start(struct ifnet *ifp) 3061 { 3062 struct iwn_softc *sc = ifp->if_softc; 3063 struct ieee80211com *ic = &sc->sc_ic; 3064 struct ieee80211_node *ni; 3065 struct ether_header *eh; 3066 struct mbuf *m; 3067 int ac; 3068 3069 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3070 return; 3071 3072 for (;;) { 3073 if (sc->qfullmsk != 0) { 3074 ifp->if_flags |= IFF_OACTIVE; 3075 break; 3076 } 3077 /* Send pending management frames first. */ 3078 IF_DEQUEUE(&ic->ic_mgtq, m); 3079 if (m != NULL) { 3080 ni = (void *)m->m_pkthdr.rcvif; 3081 ac = 0; 3082 goto sendit; 3083 } 3084 if (ic->ic_state != IEEE80211_S_RUN) 3085 break; 3086 3087 /* Encapsulate and send data frames. */ 3088 IFQ_DEQUEUE(&ifp->if_snd, m); 3089 if (m == NULL) 3090 break; 3091 if (m->m_len < sizeof (*eh) && 3092 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3093 ifp->if_oerrors++; 3094 continue; 3095 } 3096 eh = mtod(m, struct ether_header *); 3097 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3098 if (ni == NULL) { 3099 m_freem(m); 3100 ifp->if_oerrors++; 3101 continue; 3102 } 3103 /* classify mbuf so we can find which tx ring to use */ 3104 if (ieee80211_classify(ic, m, ni) != 0) { 3105 m_freem(m); 3106 ieee80211_free_node(ni); 3107 ifp->if_oerrors++; 3108 continue; 3109 } 3110 3111 /* No QoS encapsulation for EAPOL frames. */ 3112 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3113 M_WME_GETAC(m) : WME_AC_BE; 3114 3115 bpf_mtap(ifp, m); 3116 3117 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3118 ieee80211_free_node(ni); 3119 ifp->if_oerrors++; 3120 continue; 3121 } 3122 sendit: 3123 bpf_mtap3(ic->ic_rawbpf, m); 3124 3125 if (iwn_tx(sc, m, ni, ac) != 0) { 3126 ieee80211_free_node(ni); 3127 ifp->if_oerrors++; 3128 continue; 3129 } 3130 3131 sc->sc_tx_timer = 5; 3132 ifp->if_timer = 1; 3133 } 3134 } 3135 3136 static void 3137 iwn_watchdog(struct ifnet *ifp) 3138 { 3139 struct iwn_softc *sc = ifp->if_softc; 3140 3141 ifp->if_timer = 0; 3142 3143 if (sc->sc_tx_timer > 0) { 3144 if (--sc->sc_tx_timer == 0) { 3145 aprint_error_dev(sc->sc_dev, 3146 "device timeout\n"); 3147 ifp->if_flags &= ~IFF_UP; 3148 iwn_stop(ifp, 1); 3149 ifp->if_oerrors++; 3150 return; 3151 } 3152 ifp->if_timer = 1; 3153 } 3154 3155 ieee80211_watchdog(&sc->sc_ic); 3156 } 3157 3158 static int 3159 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3160 { 3161 struct iwn_softc *sc = ifp->if_softc; 3162 struct ieee80211com *ic = &sc->sc_ic; 3163 struct ifaddr *ifa; 3164 const struct sockaddr *sa; 3165 int s, error = 0; 3166 3167 s = splnet(); 3168 3169 switch (cmd) { 3170 case SIOCSIFADDR: 3171 ifa = (struct ifaddr *)data; 3172 ifp->if_flags |= IFF_UP; 3173 #ifdef INET 3174 if (ifa->ifa_addr->sa_family == AF_INET) 3175 arp_ifinit(&ic->ic_ac, ifa); 3176 #endif 3177 /* FALLTHROUGH */ 3178 case SIOCSIFFLAGS: 3179 /* XXX Added as it is in every NetBSD driver */ 3180 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3181 break; 3182 if (ifp->if_flags & IFF_UP) { 3183 if (!(ifp->if_flags & IFF_RUNNING)) 3184 error = iwn_init(ifp); 3185 } else { 3186 if (ifp->if_flags & IFF_RUNNING) 3187 iwn_stop(ifp, 1); 3188 } 3189 break; 3190 3191 case SIOCADDMULTI: 3192 case SIOCDELMULTI: 3193 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3194 error = (cmd == SIOCADDMULTI) ? 3195 ether_addmulti(sa, &sc->sc_ec) : 3196 ether_delmulti(sa, &sc->sc_ec); 3197 3198 if (error == ENETRESET) 3199 error = 0; 3200 break; 3201 3202 default: 3203 error = ieee80211_ioctl(ic, cmd, data); 3204 } 3205 3206 if (error == ENETRESET) { 3207 error = 0; 3208 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3209 (IFF_UP | IFF_RUNNING)) { 3210 iwn_stop(ifp, 0); 3211 error = iwn_init(ifp); 3212 } 3213 } 3214 3215 splx(s); 3216 return error; 3217 } 3218 3219 /* 3220 * Send a command to the firmware. 3221 */ 3222 static int 3223 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3224 { 3225 struct iwn_tx_ring *ring = &sc->txq[4]; 3226 struct iwn_tx_desc *desc; 3227 struct iwn_tx_data *data; 3228 struct iwn_tx_cmd *cmd; 3229 struct mbuf *m; 3230 bus_addr_t paddr; 3231 int totlen, error; 3232 3233 desc = &ring->desc[ring->cur]; 3234 data = &ring->data[ring->cur]; 3235 totlen = 4 + size; 3236 3237 if (size > sizeof cmd->data) { 3238 /* Command is too large to fit in a descriptor. */ 3239 if (totlen > MCLBYTES) 3240 return EINVAL; 3241 MGETHDR(m, M_DONTWAIT, MT_DATA); 3242 if (m == NULL) 3243 return ENOMEM; 3244 if (totlen > MHLEN) { 3245 MCLGET(m, M_DONTWAIT); 3246 if (!(m->m_flags & M_EXT)) { 3247 m_freem(m); 3248 return ENOMEM; 3249 } 3250 } 3251 cmd = mtod(m, struct iwn_tx_cmd *); 3252 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3253 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3254 if (error != 0) { 3255 m_freem(m); 3256 return error; 3257 } 3258 data->m = m; 3259 paddr = data->map->dm_segs[0].ds_addr; 3260 } else { 3261 cmd = &ring->cmd[ring->cur]; 3262 paddr = data->cmd_paddr; 3263 } 3264 3265 cmd->code = code; 3266 cmd->flags = 0; 3267 cmd->qid = ring->qid; 3268 cmd->idx = ring->cur; 3269 memcpy(cmd->data, buf, size); 3270 3271 desc->nsegs = 1; 3272 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3273 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3274 3275 if (size > sizeof cmd->data) { 3276 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3277 BUS_DMASYNC_PREWRITE); 3278 } else { 3279 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3280 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3281 totlen, BUS_DMASYNC_PREWRITE); 3282 } 3283 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3284 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3285 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3286 3287 #ifdef notyet 3288 /* Update TX scheduler. */ 3289 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0); 3290 #endif 3291 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3292 3293 /* Kick command ring. */ 3294 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3295 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3296 3297 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3298 } 3299 3300 static int 3301 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3302 { 3303 struct iwn4965_node_info hnode; 3304 char *src, *dst; 3305 3306 /* 3307 * We use the node structure for 5000 Series internally (it is 3308 * a superset of the one for 4965AGN). We thus copy the common 3309 * fields before sending the command. 3310 */ 3311 src = (char *)node; 3312 dst = (char *)&hnode; 3313 memcpy(dst, src, 48); 3314 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3315 memcpy(dst + 48, src + 72, 20); 3316 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3317 } 3318 3319 static int 3320 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3321 { 3322 /* Direct mapping. */ 3323 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3324 } 3325 3326 static int 3327 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3328 { 3329 struct iwn_node *wn = (void *)ni; 3330 struct ieee80211_rateset *rs = &ni->ni_rates; 3331 struct iwn_cmd_link_quality linkq; 3332 const struct iwn_rate *rinfo; 3333 uint8_t txant; 3334 int i, txrate; 3335 3336 /* Use the first valid TX antenna. */ 3337 txant = IWN_LSB(sc->txchainmask); 3338 3339 memset(&linkq, 0, sizeof linkq); 3340 linkq.id = wn->id; 3341 linkq.antmsk_1stream = txant; 3342 linkq.antmsk_2stream = IWN_ANT_AB; 3343 linkq.ampdu_max = 31; 3344 linkq.ampdu_threshold = 3; 3345 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3346 3347 /* Start at highest available bit-rate. */ 3348 txrate = rs->rs_nrates - 1; 3349 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3350 rinfo = &iwn_rates[wn->ridx[txrate]]; 3351 linkq.retry[i].plcp = rinfo->plcp; 3352 linkq.retry[i].rflags = rinfo->flags; 3353 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3354 /* Next retry at immediate lower bit-rate. */ 3355 if (txrate > 0) 3356 txrate--; 3357 } 3358 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3359 } 3360 3361 /* 3362 * Broadcast node is used to send group-addressed and management frames. 3363 */ 3364 static int 3365 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3366 { 3367 const struct iwn_hal *hal = sc->sc_hal; 3368 struct iwn_node_info node; 3369 struct iwn_cmd_link_quality linkq; 3370 const struct iwn_rate *rinfo; 3371 uint8_t txant; 3372 int i, error; 3373 3374 memset(&node, 0, sizeof node); 3375 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3376 node.id = hal->broadcast_id; 3377 DPRINTF(("adding broadcast node\n")); 3378 if ((error = hal->add_node(sc, &node, async)) != 0) 3379 return error; 3380 3381 /* Use the first valid TX antenna. */ 3382 txant = IWN_LSB(sc->txchainmask); 3383 3384 memset(&linkq, 0, sizeof linkq); 3385 linkq.id = hal->broadcast_id; 3386 linkq.antmsk_1stream = txant; 3387 linkq.antmsk_2stream = IWN_ANT_AB; 3388 linkq.ampdu_max = 64; 3389 linkq.ampdu_threshold = 3; 3390 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3391 3392 /* Use lowest mandatory bit-rate. */ 3393 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3394 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3395 linkq.retry[0].plcp = rinfo->plcp; 3396 linkq.retry[0].rflags = rinfo->flags; 3397 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3398 /* Use same bit-rate for all TX retries. */ 3399 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3400 linkq.retry[i].plcp = linkq.retry[0].plcp; 3401 linkq.retry[i].rflags = linkq.retry[0].rflags; 3402 } 3403 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3404 } 3405 3406 static void 3407 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3408 { 3409 struct iwn_cmd_led led; 3410 3411 /* Clear microcode LED ownership. */ 3412 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3413 3414 led.which = which; 3415 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3416 led.off = off; 3417 led.on = on; 3418 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3419 } 3420 3421 /* 3422 * Set the critical temperature at which the firmware will stop the radio 3423 * and notify us. 3424 */ 3425 static int 3426 iwn_set_critical_temp(struct iwn_softc *sc) 3427 { 3428 struct iwn_critical_temp crit; 3429 int32_t temp; 3430 3431 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3432 3433 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3434 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3435 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3436 temp = IWN_CTOK(110); 3437 else 3438 temp = 110; 3439 memset(&crit, 0, sizeof crit); 3440 crit.tempR = htole32(temp); 3441 DPRINTF(("setting critical temperature to %d\n", temp)); 3442 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3443 } 3444 3445 static int 3446 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3447 { 3448 struct iwn_cmd_timing cmd; 3449 uint64_t val, mod; 3450 3451 memset(&cmd, 0, sizeof cmd); 3452 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3453 cmd.bintval = htole16(ni->ni_intval); 3454 cmd.lintval = htole16(10); 3455 3456 /* Compute remaining time until next beacon. */ 3457 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3458 mod = le64toh(cmd.tstamp) % val; 3459 cmd.binitval = htole32((uint32_t)(val - mod)); 3460 3461 DPRINTF(("timing bintval=%u, tstamp=%zu, init=%u\n", 3462 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3463 3464 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3465 } 3466 3467 static void 3468 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3469 { 3470 /* Adjust TX power if need be (delta >= 3 degC.) */ 3471 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3472 if (abs(temp - sc->temp) >= 3) { 3473 /* Record temperature of last calibration. */ 3474 sc->temp = temp; 3475 (void)iwn4965_set_txpower(sc, 1); 3476 } 3477 } 3478 3479 /* 3480 * Set TX power for current channel (each rate has its own power settings). 3481 * This function takes into account the regulatory information from EEPROM, 3482 * the current temperature and the current voltage. 3483 */ 3484 static int 3485 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3486 { 3487 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3488 #define fdivround(a, b, n) \ 3489 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3490 /* Linear interpolation. */ 3491 #define interpolate(x, x1, y1, x2, y2, n) \ 3492 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3493 3494 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3495 struct ieee80211com *ic = &sc->sc_ic; 3496 struct iwn_ucode_info *uc = &sc->ucode_info; 3497 struct ieee80211_channel *ch; 3498 struct iwn4965_cmd_txpower cmd; 3499 struct iwn4965_eeprom_chan_samples *chans; 3500 const uint8_t *rf_gain, *dsp_gain; 3501 int32_t vdiff, tdiff; 3502 int i, c, grp, maxpwr; 3503 uint8_t chan; 3504 3505 /* Retrieve current channel from last RXON. */ 3506 chan = sc->rxon.chan; 3507 DPRINTF(("setting TX power for channel %d\n", chan)); 3508 ch = &ic->ic_channels[chan]; 3509 3510 memset(&cmd, 0, sizeof cmd); 3511 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3512 cmd.chan = chan; 3513 3514 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3515 maxpwr = sc->maxpwr5GHz; 3516 rf_gain = iwn4965_rf_gain_5ghz; 3517 dsp_gain = iwn4965_dsp_gain_5ghz; 3518 } else { 3519 maxpwr = sc->maxpwr2GHz; 3520 rf_gain = iwn4965_rf_gain_2ghz; 3521 dsp_gain = iwn4965_dsp_gain_2ghz; 3522 } 3523 3524 /* Compute voltage compensation. */ 3525 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3526 if (vdiff > 0) 3527 vdiff *= 2; 3528 if (abs(vdiff) > 2) 3529 vdiff = 0; 3530 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3531 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3532 3533 /* Get channel attenuation group. */ 3534 if (chan <= 20) /* 1-20 */ 3535 grp = 4; 3536 else if (chan <= 43) /* 34-43 */ 3537 grp = 0; 3538 else if (chan <= 70) /* 44-70 */ 3539 grp = 1; 3540 else if (chan <= 124) /* 71-124 */ 3541 grp = 2; 3542 else /* 125-200 */ 3543 grp = 3; 3544 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3545 3546 /* Get channel sub-band. */ 3547 for (i = 0; i < IWN_NBANDS; i++) 3548 if (sc->bands[i].lo != 0 && 3549 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3550 break; 3551 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3552 return EINVAL; 3553 chans = sc->bands[i].chans; 3554 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3555 3556 for (c = 0; c < 2; c++) { 3557 uint8_t power, gain, temp; 3558 int maxchpwr, pwr, ridx, idx; 3559 3560 power = interpolate(chan, 3561 chans[0].num, chans[0].samples[c][1].power, 3562 chans[1].num, chans[1].samples[c][1].power, 1); 3563 gain = interpolate(chan, 3564 chans[0].num, chans[0].samples[c][1].gain, 3565 chans[1].num, chans[1].samples[c][1].gain, 1); 3566 temp = interpolate(chan, 3567 chans[0].num, chans[0].samples[c][1].temp, 3568 chans[1].num, chans[1].samples[c][1].temp, 1); 3569 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3570 c, power, gain, temp)); 3571 3572 /* Compute temperature compensation. */ 3573 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3574 DPRINTF(("temperature compensation=%d (current=%d, " 3575 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3576 3577 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3578 /* Convert dBm to half-dBm. */ 3579 maxchpwr = sc->maxpwr[chan] * 2; 3580 if ((ridx / 8) & 1) 3581 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3582 3583 pwr = maxpwr; 3584 3585 /* Adjust TX power based on rate. */ 3586 if ((ridx % 8) == 5) 3587 pwr -= 15; /* OFDM48: -7.5dB */ 3588 else if ((ridx % 8) == 6) 3589 pwr -= 17; /* OFDM54: -8.5dB */ 3590 else if ((ridx % 8) == 7) 3591 pwr -= 20; /* OFDM60: -10dB */ 3592 else 3593 pwr -= 10; /* Others: -5dB */ 3594 3595 /* Do not exceed channel max TX power. */ 3596 if (pwr > maxchpwr) 3597 pwr = maxchpwr; 3598 3599 idx = gain - (pwr - power) - tdiff - vdiff; 3600 if ((ridx / 8) & 1) /* MIMO */ 3601 idx += (int32_t)le32toh(uc->atten[grp][c]); 3602 3603 if (cmd.band == 0) 3604 idx += 9; /* 5GHz */ 3605 if (ridx == IWN_RIDX_MAX) 3606 idx += 5; /* CCK */ 3607 3608 /* Make sure idx stays in a valid range. */ 3609 if (idx < 0) 3610 idx = 0; 3611 else if (idx > IWN4965_MAX_PWR_INDEX) 3612 idx = IWN4965_MAX_PWR_INDEX; 3613 3614 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3615 c, ridx, idx)); 3616 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3617 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3618 } 3619 } 3620 3621 DPRINTF(("setting TX power for chan %d\n", chan)); 3622 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3623 3624 #undef interpolate 3625 #undef fdivround 3626 } 3627 3628 static int 3629 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3630 { 3631 struct iwn5000_cmd_txpower cmd; 3632 3633 /* 3634 * TX power calibration is handled automatically by the firmware 3635 * for 5000 Series. 3636 */ 3637 memset(&cmd, 0, sizeof cmd); 3638 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3639 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3640 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3641 DPRINTF(("setting TX power\n")); 3642 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3643 } 3644 3645 /* 3646 * Retrieve the maximum RSSI (in dBm) among receivers. 3647 */ 3648 static int 3649 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3650 { 3651 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3652 uint8_t mask, agc; 3653 int rssi; 3654 3655 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3656 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3657 3658 rssi = 0; 3659 if (mask & IWN_ANT_A) 3660 rssi = MAX(rssi, phy->rssi[0]); 3661 if (mask & IWN_ANT_B) 3662 rssi = MAX(rssi, phy->rssi[2]); 3663 if (mask & IWN_ANT_C) 3664 rssi = MAX(rssi, phy->rssi[4]); 3665 3666 return rssi - agc - IWN_RSSI_TO_DBM; 3667 } 3668 3669 static int 3670 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3671 { 3672 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3673 uint8_t agc; 3674 int rssi; 3675 3676 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3677 3678 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3679 le16toh(phy->rssi[1]) & 0xff); 3680 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3681 3682 return rssi - agc - IWN_RSSI_TO_DBM; 3683 } 3684 3685 /* 3686 * Retrieve the average noise (in dBm) among receivers. 3687 */ 3688 static int 3689 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3690 { 3691 int i, total, nbant, noise; 3692 3693 total = nbant = 0; 3694 for (i = 0; i < 3; i++) { 3695 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3696 continue; 3697 total += noise; 3698 nbant++; 3699 } 3700 /* There should be at least one antenna but check anyway. */ 3701 return (nbant == 0) ? -127 : (total / nbant) - 107; 3702 } 3703 3704 /* 3705 * Compute temperature (in degC) from last received statistics. 3706 */ 3707 static int 3708 iwn4965_get_temperature(struct iwn_softc *sc) 3709 { 3710 struct iwn_ucode_info *uc = &sc->ucode_info; 3711 int32_t r1, r2, r3, r4, temp; 3712 3713 r1 = le32toh(uc->temp[0].chan20MHz); 3714 r2 = le32toh(uc->temp[1].chan20MHz); 3715 r3 = le32toh(uc->temp[2].chan20MHz); 3716 r4 = le32toh(sc->rawtemp); 3717 3718 if (r1 == r3) /* Prevents division by 0 (should not happen.) */ 3719 return 0; 3720 3721 /* Sign-extend 23-bit R4 value to 32-bit. */ 3722 r4 = (r4 << 8) >> 8; 3723 /* Compute temperature in Kelvin. */ 3724 temp = (259 * (r4 - r2)) / (r3 - r1); 3725 temp = (temp * 97) / 100 + 8; 3726 3727 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3728 return IWN_KTOC(temp); 3729 } 3730 3731 static int 3732 iwn5000_get_temperature(struct iwn_softc *sc) 3733 { 3734 int32_t temp; 3735 3736 /* 3737 * Temperature is not used by the driver for 5000 Series because 3738 * TX power calibration is handled by firmware. We export it to 3739 * users through the sensor framework though. 3740 */ 3741 temp = le32toh(sc->rawtemp); 3742 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3743 temp = (temp / -5) + sc->temp_off; 3744 temp = IWN_KTOC(temp); 3745 } 3746 return temp; 3747 } 3748 3749 /* 3750 * Initialize sensitivity calibration state machine. 3751 */ 3752 static int 3753 iwn_init_sensitivity(struct iwn_softc *sc) 3754 { 3755 const struct iwn_hal *hal = sc->sc_hal; 3756 struct iwn_calib_state *calib = &sc->calib; 3757 uint32_t flags; 3758 int error; 3759 3760 /* Reset calibration state machine. */ 3761 memset(calib, 0, sizeof (*calib)); 3762 calib->state = IWN_CALIB_STATE_INIT; 3763 calib->cck_state = IWN_CCK_STATE_HIFA; 3764 /* Set initial correlation values. */ 3765 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3766 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3767 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3768 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3769 calib->cck_x4 = 125; 3770 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3771 calib->energy_cck = sc->limits->energy_cck; 3772 3773 /* Write initial sensitivity. */ 3774 if ((error = iwn_send_sensitivity(sc)) != 0) 3775 return error; 3776 3777 /* Write initial gains. */ 3778 if ((error = hal->init_gains(sc)) != 0) 3779 return error; 3780 3781 /* Request statistics at each beacon interval. */ 3782 flags = 0; 3783 DPRINTF(("sending request for statistics\n")); 3784 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3785 } 3786 3787 /* 3788 * Collect noise and RSSI statistics for the first 20 beacons received 3789 * after association and use them to determine connected antennas and 3790 * to set differential gains. 3791 */ 3792 static void 3793 iwn_collect_noise(struct iwn_softc *sc, 3794 const struct iwn_rx_general_stats *stats) 3795 { 3796 const struct iwn_hal *hal = sc->sc_hal; 3797 struct iwn_calib_state *calib = &sc->calib; 3798 uint32_t val; 3799 int i; 3800 3801 /* Accumulate RSSI and noise for all 3 antennas. */ 3802 for (i = 0; i < 3; i++) { 3803 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3804 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3805 } 3806 /* NB: We update differential gains only once after 20 beacons. */ 3807 if (++calib->nbeacons < 20) 3808 return; 3809 3810 /* Determine highest average RSSI. */ 3811 val = MAX(calib->rssi[0], calib->rssi[1]); 3812 val = MAX(calib->rssi[2], val); 3813 3814 /* Determine which antennas are connected. */ 3815 sc->chainmask = sc->rxchainmask; 3816 for (i = 0; i < 3; i++) 3817 if (val - calib->rssi[i] > 15 * 20) 3818 sc->chainmask &= ~(1 << i); 3819 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3820 sc->rxchainmask, sc->chainmask)); 3821 3822 /* If none of the TX antennas are connected, keep at least one. */ 3823 if ((sc->chainmask & sc->txchainmask) == 0) 3824 sc->chainmask |= IWN_LSB(sc->txchainmask); 3825 3826 (void)hal->set_gains(sc); 3827 calib->state = IWN_CALIB_STATE_RUN; 3828 3829 #ifdef notyet 3830 /* XXX Disable RX chains with no antennas connected. */ 3831 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3832 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 3833 #endif 3834 3835 /* Enable power-saving mode if requested by user. */ 3836 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3837 (void)iwn_set_pslevel(sc, 0, 3, 1); 3838 } 3839 3840 static int 3841 iwn4965_init_gains(struct iwn_softc *sc) 3842 { 3843 struct iwn_phy_calib_gain cmd; 3844 3845 memset(&cmd, 0, sizeof cmd); 3846 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3847 /* Differential gains initially set to 0 for all 3 antennas. */ 3848 DPRINTF(("setting initial differential gains\n")); 3849 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3850 } 3851 3852 static int 3853 iwn5000_init_gains(struct iwn_softc *sc) 3854 { 3855 struct iwn_phy_calib cmd; 3856 3857 memset(&cmd, 0, sizeof cmd); 3858 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3859 cmd.ngroups = 1; 3860 cmd.isvalid = 1; 3861 DPRINTF(("setting initial differential gains\n")); 3862 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3863 } 3864 3865 static int 3866 iwn4965_set_gains(struct iwn_softc *sc) 3867 { 3868 struct iwn_calib_state *calib = &sc->calib; 3869 struct iwn_phy_calib_gain cmd; 3870 int i, delta, noise; 3871 3872 /* Get minimal noise among connected antennas. */ 3873 noise = INT_MAX; /* NB: There's at least one antenna. */ 3874 for (i = 0; i < 3; i++) 3875 if (sc->chainmask & (1 << i)) 3876 noise = MIN(calib->noise[i], noise); 3877 3878 memset(&cmd, 0, sizeof cmd); 3879 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3880 /* Set differential gains for connected antennas. */ 3881 for (i = 0; i < 3; i++) { 3882 if (sc->chainmask & (1 << i)) { 3883 /* Compute attenuation (in unit of 1.5dB). */ 3884 delta = (noise - (int32_t)calib->noise[i]) / 30; 3885 /* NB: delta <= 0 */ 3886 /* Limit to [-4.5dB,0]. */ 3887 cmd.gain[i] = MIN(abs(delta), 3); 3888 if (delta < 0) 3889 cmd.gain[i] |= 1 << 2; /* sign bit */ 3890 } 3891 } 3892 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3893 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3894 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3895 } 3896 3897 static int 3898 iwn5000_set_gains(struct iwn_softc *sc) 3899 { 3900 struct iwn_calib_state *calib = &sc->calib; 3901 struct iwn_phy_calib_gain cmd; 3902 int i, ant, div, delta; 3903 3904 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3905 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3906 3907 memset(&cmd, 0, sizeof cmd); 3908 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3909 cmd.ngroups = 1; 3910 cmd.isvalid = 1; 3911 /* Get first available RX antenna as referential. */ 3912 ant = IWN_LSB(sc->rxchainmask); 3913 /* Set differential gains for other antennas. */ 3914 for (i = ant + 1; i < 3; i++) { 3915 if (sc->chainmask & (1 << i)) { 3916 /* The delta is relative to antenna "ant". */ 3917 delta = ((int32_t)calib->noise[ant] - 3918 (int32_t)calib->noise[i]) / div; 3919 /* Limit to [-4.5dB,+4.5dB]. */ 3920 cmd.gain[i - 1] = MIN(abs(delta), 3); 3921 if (delta < 0) 3922 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3923 } 3924 } 3925 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3926 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3927 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3928 } 3929 3930 /* 3931 * Tune RF RX sensitivity based on the number of false alarms detected 3932 * during the last beacon period. 3933 */ 3934 static void 3935 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3936 { 3937 #define inc(val, inc, max) \ 3938 if ((val) < (max)) { \ 3939 if ((val) < (max) - (inc)) \ 3940 (val) += (inc); \ 3941 else \ 3942 (val) = (max); \ 3943 needs_update = 1; \ 3944 } 3945 #define dec(val, dec, min) \ 3946 if ((val) > (min)) { \ 3947 if ((val) > (min) + (dec)) \ 3948 (val) -= (dec); \ 3949 else \ 3950 (val) = (min); \ 3951 needs_update = 1; \ 3952 } 3953 3954 const struct iwn_sensitivity_limits *limits = sc->limits; 3955 struct iwn_calib_state *calib = &sc->calib; 3956 uint32_t val, rxena, fa; 3957 uint32_t energy[3], energy_min; 3958 uint8_t noise[3], noise_ref; 3959 int i, needs_update = 0; 3960 3961 /* Check that we've been enabled long enough. */ 3962 if ((rxena = le32toh(stats->general.load)) == 0) 3963 return; 3964 3965 /* Compute number of false alarms since last call for OFDM. */ 3966 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3967 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3968 fa *= 200 * 1024; /* 200TU */ 3969 3970 /* Save counters values for next call. */ 3971 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3972 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3973 3974 if (fa > 50 * rxena) { 3975 /* High false alarm count, decrease sensitivity. */ 3976 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3977 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3978 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3979 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3980 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3981 3982 } else if (fa < 5 * rxena) { 3983 /* Low false alarm count, increase sensitivity. */ 3984 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3985 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3986 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3987 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3988 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3989 } 3990 3991 /* Compute maximum noise among 3 receivers. */ 3992 for (i = 0; i < 3; i++) 3993 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 3994 val = MAX(noise[0], noise[1]); 3995 val = MAX(noise[2], val); 3996 /* Insert it into our samples table. */ 3997 calib->noise_samples[calib->cur_noise_sample] = val; 3998 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3999 4000 /* Compute maximum noise among last 20 samples. */ 4001 noise_ref = calib->noise_samples[0]; 4002 for (i = 1; i < 20; i++) 4003 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4004 4005 /* Compute maximum energy among 3 receivers. */ 4006 for (i = 0; i < 3; i++) 4007 energy[i] = le32toh(stats->general.energy[i]); 4008 val = MIN(energy[0], energy[1]); 4009 val = MIN(energy[2], val); 4010 /* Insert it into our samples table. */ 4011 calib->energy_samples[calib->cur_energy_sample] = val; 4012 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4013 4014 /* Compute minimum energy among last 10 samples. */ 4015 energy_min = calib->energy_samples[0]; 4016 for (i = 1; i < 10; i++) 4017 energy_min = MAX(energy_min, calib->energy_samples[i]); 4018 energy_min += 6; 4019 4020 /* Compute number of false alarms since last call for CCK. */ 4021 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4022 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4023 fa *= 200 * 1024; /* 200TU */ 4024 4025 /* Save counters values for next call. */ 4026 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4027 calib->fa_cck = le32toh(stats->cck.fa); 4028 4029 if (fa > 50 * rxena) { 4030 /* High false alarm count, decrease sensitivity. */ 4031 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4032 calib->cck_state = IWN_CCK_STATE_HIFA; 4033 calib->low_fa = 0; 4034 4035 if (calib->cck_x4 > 160) { 4036 calib->noise_ref = noise_ref; 4037 if (calib->energy_cck > 2) 4038 dec(calib->energy_cck, 2, energy_min); 4039 } 4040 if (calib->cck_x4 < 160) { 4041 calib->cck_x4 = 161; 4042 needs_update = 1; 4043 } else 4044 inc(calib->cck_x4, 3, limits->max_cck_x4); 4045 4046 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4047 4048 } else if (fa < 5 * rxena) { 4049 /* Low false alarm count, increase sensitivity. */ 4050 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4051 calib->cck_state = IWN_CCK_STATE_LOFA; 4052 calib->low_fa++; 4053 4054 if (calib->cck_state != IWN_CCK_STATE_INIT && 4055 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4056 calib->low_fa > 100)) { 4057 inc(calib->energy_cck, 2, limits->min_energy_cck); 4058 dec(calib->cck_x4, 3, limits->min_cck_x4); 4059 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4060 } 4061 } else { 4062 /* Not worth to increase or decrease sensitivity. */ 4063 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4064 calib->low_fa = 0; 4065 calib->noise_ref = noise_ref; 4066 4067 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4068 /* Previous interval had many false alarms. */ 4069 dec(calib->energy_cck, 8, energy_min); 4070 } 4071 calib->cck_state = IWN_CCK_STATE_INIT; 4072 } 4073 4074 if (needs_update) 4075 (void)iwn_send_sensitivity(sc); 4076 #undef dec 4077 #undef inc 4078 } 4079 4080 static int 4081 iwn_send_sensitivity(struct iwn_softc *sc) 4082 { 4083 struct iwn_calib_state *calib = &sc->calib; 4084 struct iwn_sensitivity_cmd cmd; 4085 4086 memset(&cmd, 0, sizeof cmd); 4087 cmd.which = IWN_SENSITIVITY_WORKTBL; 4088 /* OFDM modulation. */ 4089 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4090 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4091 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4092 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4093 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4094 cmd.energy_ofdm_th = htole16(62); 4095 /* CCK modulation. */ 4096 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4097 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4098 cmd.energy_cck = htole16(calib->energy_cck); 4099 /* Barker modulation: use default values. */ 4100 cmd.corr_barker = htole16(190); 4101 cmd.corr_barker_mrc = htole16(390); 4102 4103 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4104 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4105 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4106 calib->energy_cck)); 4107 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4108 } 4109 4110 /* 4111 * Set STA mode power saving level (between 0 and 5). 4112 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4113 */ 4114 static int 4115 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4116 { 4117 struct iwn_pmgt_cmd cmd; 4118 const struct iwn_pmgt *pmgt; 4119 uint32_t maxp, skip_dtim; 4120 pcireg_t reg; 4121 int i; 4122 4123 /* Select which PS parameters to use. */ 4124 if (dtim <= 2) 4125 pmgt = &iwn_pmgt[0][level]; 4126 else if (dtim <= 10) 4127 pmgt = &iwn_pmgt[1][level]; 4128 else 4129 pmgt = &iwn_pmgt[2][level]; 4130 4131 memset(&cmd, 0, sizeof cmd); 4132 if (level != 0) /* not CAM */ 4133 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4134 if (level == 5) 4135 cmd.flags |= htole16(IWN_PS_FAST_PD); 4136 /* Retrieve PCIe Active State Power Management (ASPM). */ 4137 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4138 sc->sc_cap_off + PCI_PCIE_LCSR); 4139 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4140 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4141 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4142 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4143 4144 if (dtim == 0) { 4145 dtim = 1; 4146 skip_dtim = 0; 4147 } else 4148 skip_dtim = pmgt->skip_dtim; 4149 if (skip_dtim != 0) { 4150 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4151 maxp = pmgt->intval[4]; 4152 if (maxp == (uint32_t)-1) 4153 maxp = dtim * (skip_dtim + 1); 4154 else if (maxp > dtim) 4155 maxp = (maxp / dtim) * dtim; 4156 } else 4157 maxp = dtim; 4158 for (i = 0; i < 5; i++) 4159 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4160 4161 DPRINTF(("setting power saving level to %d\n", level)); 4162 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4163 } 4164 4165 static int 4166 iwn_config(struct iwn_softc *sc) 4167 { 4168 const struct iwn_hal *hal = sc->sc_hal; 4169 struct ieee80211com *ic = &sc->sc_ic; 4170 struct ifnet *ifp = ic->ic_ifp; 4171 struct iwn_bluetooth bluetooth; 4172 uint32_t txmask; 4173 uint16_t rxchain; 4174 int error; 4175 4176 /* Configure valid TX chains for 5000 Series. */ 4177 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4178 txmask = htole32(sc->txchainmask); 4179 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4180 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4181 sizeof txmask, 0); 4182 if (error != 0) { 4183 aprint_error_dev(sc->sc_dev, 4184 "could not configure valid TX chains\n"); 4185 return error; 4186 } 4187 } 4188 4189 /* Configure bluetooth coexistence. */ 4190 memset(&bluetooth, 0, sizeof bluetooth); 4191 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4192 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4193 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4194 DPRINTF(("configuring bluetooth coexistence\n")); 4195 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4196 if (error != 0) { 4197 aprint_error_dev(sc->sc_dev, 4198 "could not configure bluetooth coexistence\n"); 4199 return error; 4200 } 4201 4202 /* Set mode, channel, RX filter and enable RX. */ 4203 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4204 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4205 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4206 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4207 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4208 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4209 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4210 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4211 switch (ic->ic_opmode) { 4212 case IEEE80211_M_STA: 4213 sc->rxon.mode = IWN_MODE_STA; 4214 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4215 break; 4216 case IEEE80211_M_MONITOR: 4217 sc->rxon.mode = IWN_MODE_MONITOR; 4218 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4219 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4220 break; 4221 default: 4222 /* Should not get there. */ 4223 break; 4224 } 4225 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4226 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4227 sc->rxon.ht_single_mask = 0xff; 4228 sc->rxon.ht_dual_mask = 0xff; 4229 sc->rxon.ht_triple_mask = 0xff; 4230 rxchain = 4231 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4232 IWN_RXCHAIN_MIMO_COUNT(2) | 4233 IWN_RXCHAIN_IDLE_COUNT(2); 4234 sc->rxon.rxchain = htole16(rxchain); 4235 DPRINTF(("setting configuration\n")); 4236 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0); 4237 if (error != 0) { 4238 aprint_error_dev(sc->sc_dev, 4239 "RXON command failed\n"); 4240 return error; 4241 } 4242 4243 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4244 aprint_error_dev(sc->sc_dev, 4245 "could not add broadcast node\n"); 4246 return error; 4247 } 4248 4249 /* Configuration has changed, set TX power accordingly. */ 4250 if ((error = hal->set_txpower(sc, 0)) != 0) { 4251 aprint_error_dev(sc->sc_dev, 4252 "could not set TX power\n"); 4253 return error; 4254 } 4255 4256 if ((error = iwn_set_critical_temp(sc)) != 0) { 4257 aprint_error_dev(sc->sc_dev, 4258 "could not set critical temperature\n"); 4259 return error; 4260 } 4261 4262 /* Set power saving level to CAM during initialization. */ 4263 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4264 aprint_error_dev(sc->sc_dev, 4265 "could not set power saving level\n"); 4266 return error; 4267 } 4268 return 0; 4269 } 4270 4271 static int 4272 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4273 { 4274 struct ieee80211com *ic = &sc->sc_ic; 4275 struct iwn_scan_hdr *hdr; 4276 struct iwn_cmd_data *tx; 4277 struct iwn_scan_essid *essid; 4278 struct iwn_scan_chan *chan; 4279 struct ieee80211_frame *wh; 4280 struct ieee80211_rateset *rs; 4281 struct ieee80211_channel *c; 4282 uint8_t *buf, *frm; 4283 uint16_t rxchain; 4284 uint8_t txant; 4285 int buflen, error; 4286 4287 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4288 if (buf == NULL) { 4289 aprint_error_dev(sc->sc_dev, 4290 "could not allocate buffer for scan command\n"); 4291 return ENOMEM; 4292 } 4293 hdr = (struct iwn_scan_hdr *)buf; 4294 /* 4295 * Move to the next channel if no frames are received within 10ms 4296 * after sending the probe request. 4297 */ 4298 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4299 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4300 4301 /* Select antennas for scanning. */ 4302 rxchain = 4303 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4304 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4305 IWN_RXCHAIN_DRIVER_FORCE; 4306 if ((flags & IEEE80211_CHAN_5GHZ) && 4307 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4308 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4309 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4310 } else /* Use all available RX antennas. */ 4311 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4312 hdr->rxchain = htole16(rxchain); 4313 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4314 4315 tx = (struct iwn_cmd_data *)(hdr + 1); 4316 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4317 tx->id = sc->sc_hal->broadcast_id; 4318 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4319 4320 if (flags & IEEE80211_CHAN_5GHZ) { 4321 hdr->crc_threshold = 0xffff; 4322 /* Send probe requests at 6Mbps. */ 4323 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4324 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4325 } else { 4326 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4327 /* Send probe requests at 1Mbps. */ 4328 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4329 tx->rflags = IWN_RFLAG_CCK; 4330 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4331 } 4332 /* Use the first valid TX antenna. */ 4333 txant = IWN_LSB(sc->txchainmask); 4334 tx->rflags |= IWN_RFLAG_ANT(txant); 4335 4336 essid = (struct iwn_scan_essid *)(tx + 1); 4337 if (ic->ic_des_esslen != 0) { 4338 essid[0].id = IEEE80211_ELEMID_SSID; 4339 essid[0].len = ic->ic_des_esslen; 4340 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4341 } 4342 /* 4343 * Build a probe request frame. Most of the following code is a 4344 * copy & paste of what is done in net80211. 4345 */ 4346 wh = (struct ieee80211_frame *)(essid + 20); 4347 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4348 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4349 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4350 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4351 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4352 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4353 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4354 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4355 4356 frm = (uint8_t *)(wh + 1); 4357 frm = ieee80211_add_ssid(frm, NULL, 0); 4358 frm = ieee80211_add_rates(frm, rs); 4359 #ifndef IEEE80211_NO_HT 4360 if (ic->ic_flags & IEEE80211_F_HTON) 4361 frm = ieee80211_add_htcaps(frm, ic); 4362 #endif 4363 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4364 frm = ieee80211_add_xrates(frm, rs); 4365 4366 /* Set length of probe request. */ 4367 tx->len = htole16(frm - (uint8_t *)wh); 4368 4369 chan = (struct iwn_scan_chan *)frm; 4370 for (c = &ic->ic_channels[1]; 4371 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4372 if ((c->ic_flags & flags) != flags) 4373 continue; 4374 4375 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4376 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4377 chan->flags = 0; 4378 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4379 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4380 if (ic->ic_des_esslen != 0) 4381 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4382 chan->dsp_gain = 0x6e; 4383 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4384 chan->rf_gain = 0x3b; 4385 chan->active = htole16(24); 4386 chan->passive = htole16(110); 4387 } else { 4388 chan->rf_gain = 0x28; 4389 chan->active = htole16(36); 4390 chan->passive = htole16(120); 4391 } 4392 hdr->nchan++; 4393 chan++; 4394 } 4395 4396 buflen = (uint8_t *)chan - buf; 4397 hdr->len = htole16(buflen); 4398 4399 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4400 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4401 free(buf, M_DEVBUF); 4402 return error; 4403 } 4404 4405 static int 4406 iwn_auth(struct iwn_softc *sc) 4407 { 4408 const struct iwn_hal *hal = sc->sc_hal; 4409 struct ieee80211com *ic = &sc->sc_ic; 4410 struct ieee80211_node *ni = ic->ic_bss; 4411 int error; 4412 4413 /* Update adapter configuration. */ 4414 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4415 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4416 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4417 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4418 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4419 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4420 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4421 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4422 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4423 switch (ic->ic_curmode) { 4424 case IEEE80211_MODE_11A: 4425 sc->rxon.cck_mask = 0; 4426 sc->rxon.ofdm_mask = 0x15; 4427 break; 4428 case IEEE80211_MODE_11B: 4429 sc->rxon.cck_mask = 0x03; 4430 sc->rxon.ofdm_mask = 0; 4431 break; 4432 default: /* Assume 802.11b/g. */ 4433 sc->rxon.cck_mask = 0x0f; 4434 sc->rxon.ofdm_mask = 0x15; 4435 } 4436 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4437 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4438 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4439 if (error != 0) { 4440 aprint_error_dev(sc->sc_dev, 4441 "RXON command failed\n"); 4442 return error; 4443 } 4444 4445 /* Configuration has changed, set TX power accordingly. */ 4446 if ((error = hal->set_txpower(sc, 1)) != 0) { 4447 aprint_error_dev(sc->sc_dev, 4448 "could not set TX power\n"); 4449 return error; 4450 } 4451 /* 4452 * Reconfiguring RXON clears the firmware nodes table so we must 4453 * add the broadcast node again. 4454 */ 4455 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4456 aprint_error_dev(sc->sc_dev, 4457 "could not add broadcast node\n"); 4458 return error; 4459 } 4460 return 0; 4461 } 4462 4463 static int 4464 iwn_run(struct iwn_softc *sc) 4465 { 4466 const struct iwn_hal *hal = sc->sc_hal; 4467 struct ieee80211com *ic = &sc->sc_ic; 4468 struct ieee80211_node *ni = ic->ic_bss; 4469 struct iwn_node_info node; 4470 int error; 4471 4472 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4473 /* Link LED blinks while monitoring. */ 4474 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4475 return 0; 4476 } 4477 if ((error = iwn_set_timing(sc, ni)) != 0) { 4478 aprint_error_dev(sc->sc_dev, 4479 "could not set timing\n"); 4480 return error; 4481 } 4482 4483 /* Update adapter configuration. */ 4484 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4485 /* Short preamble and slot time are negotiated when associating. */ 4486 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4487 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4488 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4489 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4490 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4491 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4492 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4493 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1); 4494 if (error != 0) { 4495 aprint_error_dev(sc->sc_dev, 4496 "could not update configuration\n"); 4497 return error; 4498 } 4499 4500 /* Configuration has changed, set TX power accordingly. */ 4501 if ((error = hal->set_txpower(sc, 1)) != 0) { 4502 aprint_error_dev(sc->sc_dev, 4503 "could not set TX power\n"); 4504 return error; 4505 } 4506 4507 /* Fake a join to initialize the TX rate. */ 4508 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4509 iwn_newassoc(ni, 1); 4510 4511 /* Add BSS node. */ 4512 memset(&node, 0, sizeof node); 4513 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4514 node.id = IWN_ID_BSS; 4515 #ifdef notyet 4516 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4517 IWN_AMDPU_DENSITY(5)); /* 2us */ 4518 #endif 4519 DPRINTF(("adding BSS node\n")); 4520 error = hal->add_node(sc, &node, 1); 4521 if (error != 0) { 4522 aprint_error_dev(sc->sc_dev, 4523 "could not add BSS node\n"); 4524 return error; 4525 } 4526 DPRINTF(("setting link quality for node %d\n", node.id)); 4527 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4528 aprint_error_dev(sc->sc_dev, 4529 "could not setup link quality for node %d\n", node.id); 4530 return error; 4531 } 4532 4533 if ((error = iwn_init_sensitivity(sc)) != 0) { 4534 aprint_error_dev(sc->sc_dev, 4535 "could not set sensitivity\n"); 4536 return error; 4537 } 4538 /* Start periodic calibration timer. */ 4539 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4540 sc->calib_cnt = 0; 4541 callout_schedule(&sc->calib_to, hz/2); 4542 4543 /* Link LED always on while associated. */ 4544 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4545 return 0; 4546 } 4547 4548 #ifdef IWN_HWCRYPTO 4549 /* 4550 * We support CCMP hardware encryption/decryption of unicast frames only. 4551 * HW support for TKIP really sucks. We should let TKIP die anyway. 4552 */ 4553 static int 4554 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4555 struct ieee80211_key *k) 4556 { 4557 struct iwn_softc *sc = ic->ic_softc; 4558 const struct iwn_hal *hal = sc->sc_hal; 4559 struct iwn_node *wn = (void *)ni; 4560 struct iwn_node_info node; 4561 uint16_t kflags; 4562 4563 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4564 k->k_cipher != IEEE80211_CIPHER_CCMP) 4565 return ieee80211_set_key(ic, ni, k); 4566 4567 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4568 if (k->k_flags & IEEE80211_KEY_GROUP) 4569 kflags |= IWN_KFLAG_GROUP; 4570 4571 memset(&node, 0, sizeof node); 4572 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4573 hal->broadcast_id : wn->id; 4574 node.control = IWN_NODE_UPDATE; 4575 node.flags = IWN_FLAG_SET_KEY; 4576 node.kflags = htole16(kflags); 4577 node.kid = k->k_id; 4578 memcpy(node.key, k->k_key, k->k_len); 4579 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4580 return hal->add_node(sc, &node, 1); 4581 } 4582 4583 static void 4584 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4585 struct ieee80211_key *k) 4586 { 4587 struct iwn_softc *sc = ic->ic_softc; 4588 const struct iwn_hal *hal = sc->sc_hal; 4589 struct iwn_node *wn = (void *)ni; 4590 struct iwn_node_info node; 4591 4592 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4593 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4594 /* See comment about other ciphers above. */ 4595 ieee80211_delete_key(ic, ni, k); 4596 return; 4597 } 4598 if (ic->ic_state != IEEE80211_S_RUN) 4599 return; /* Nothing to do. */ 4600 memset(&node, 0, sizeof node); 4601 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4602 hal->broadcast_id : wn->id; 4603 node.control = IWN_NODE_UPDATE; 4604 node.flags = IWN_FLAG_SET_KEY; 4605 node.kflags = htole16(IWN_KFLAG_INVALID); 4606 node.kid = 0xff; 4607 DPRINTF(("delete keys for node %d\n", node.id)); 4608 (void)hal->add_node(sc, &node, 1); 4609 } 4610 #endif 4611 4612 /* XXX Added for NetBSD (copied from rev 1.39). */ 4613 4614 static int 4615 iwn_wme_update(struct ieee80211com *ic) 4616 { 4617 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4618 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4619 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4620 const struct wmeParams *wmep; 4621 struct iwn_edca_params cmd; 4622 int ac; 4623 4624 /* don't override default WME values if WME is not actually enabled */ 4625 if (!(ic->ic_flags & IEEE80211_F_WME)) 4626 return 0; 4627 cmd.flags = 0; 4628 for (ac = 0; ac < WME_NUM_AC; ac++) { 4629 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4630 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4631 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4632 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4633 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4634 4635 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4636 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4637 cmd.ac[ac].cwmin, 4638 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4639 } 4640 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4641 #undef IWN_USEC 4642 #undef IWN_EXP2 4643 } 4644 4645 #ifndef IEEE80211_NO_HT 4646 /* 4647 * This function is called by upper layer when an ADDBA request is received 4648 * from another STA and before the ADDBA response is sent. 4649 */ 4650 static int 4651 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4652 uint8_t tid) 4653 { 4654 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4655 struct iwn_softc *sc = ic->ic_softc; 4656 struct iwn_node *wn = (void *)ni; 4657 struct iwn_node_info node; 4658 4659 memset(&node, 0, sizeof node); 4660 node.id = wn->id; 4661 node.control = IWN_NODE_UPDATE; 4662 node.flags = IWN_FLAG_SET_ADDBA; 4663 node.addba_tid = tid; 4664 node.addba_ssn = htole16(ba->ba_winstart); 4665 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4666 ba->ba_winstart)); 4667 return sc->sc_hal->add_node(sc, &node, 1); 4668 } 4669 4670 /* 4671 * This function is called by upper layer on teardown of an HT-immediate 4672 * Block Ack agreement (eg. uppon receipt of a DELBA frame.) 4673 */ 4674 static void 4675 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4676 uint8_t tid) 4677 { 4678 struct iwn_softc *sc = ic->ic_softc; 4679 struct iwn_node *wn = (void *)ni; 4680 struct iwn_node_info node; 4681 4682 memset(&node, 0, sizeof node); 4683 node.id = wn->id; 4684 node.control = IWN_NODE_UPDATE; 4685 node.flags = IWN_FLAG_SET_DELBA; 4686 node.delba_tid = tid; 4687 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4688 (void)sc->sc_hal->add_node(sc, &node, 1); 4689 } 4690 4691 /* 4692 * This function is called by upper layer when an ADDBA response is received 4693 * from another STA. 4694 */ 4695 static int 4696 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4697 uint8_t tid) 4698 { 4699 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4700 struct iwn_softc *sc = ic->ic_softc; 4701 const struct iwn_hal *hal = sc->sc_hal; 4702 struct iwn_node *wn = (void *)ni; 4703 struct iwn_node_info node; 4704 int error; 4705 4706 /* Enable TX for the specified RA/TID. */ 4707 wn->disable_tid &= ~(1 << tid); 4708 memset(&node, 0, sizeof node); 4709 node.id = wn->id; 4710 node.control = IWN_NODE_UPDATE; 4711 node.flags = IWN_FLAG_SET_DISABLE_TID; 4712 node.disable_tid = htole16(wn->disable_tid); 4713 error = hal->add_node(sc, &node, 1); 4714 if (error != 0) 4715 return error; 4716 4717 if ((error = iwn_nic_lock(sc)) != 0) 4718 return error; 4719 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4720 iwn_nic_unlock(sc); 4721 return 0; 4722 } 4723 4724 static void 4725 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4726 uint8_t tid) 4727 { 4728 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4729 struct iwn_softc *sc = ic->ic_softc; 4730 4731 if (iwn_nic_lock(sc) != 0) 4732 return; 4733 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4734 iwn_nic_unlock(sc); 4735 } 4736 4737 static void 4738 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4739 uint8_t tid, uint16_t ssn) 4740 { 4741 struct iwn_node *wn = (void *)ni; 4742 int qid = 7 + tid; 4743 4744 /* Stop TX scheduler while we're changing its configuration. */ 4745 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4746 IWN4965_TXQ_STATUS_CHGACT); 4747 4748 /* Assign RA/TID translation to the queue. */ 4749 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4750 wn->id << 4 | tid); 4751 4752 /* Enable chain-building mode for the queue. */ 4753 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4754 4755 /* Set starting sequence number from the ADDBA request. */ 4756 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4757 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4758 4759 /* Set scheduler window size. */ 4760 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4761 IWN_SCHED_WINSZ); 4762 /* Set scheduler frame limit. */ 4763 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4764 IWN_SCHED_LIMIT << 16); 4765 4766 /* Enable interrupts for the queue. */ 4767 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4768 4769 /* Mark the queue as active. */ 4770 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4771 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4772 iwn_tid2fifo[tid] << 1); 4773 } 4774 4775 static void 4776 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4777 { 4778 int qid = 7 + tid; 4779 4780 /* Stop TX scheduler while we're changing its configuration. */ 4781 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4782 IWN4965_TXQ_STATUS_CHGACT); 4783 4784 /* Set starting sequence number from the ADDBA request. */ 4785 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4786 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4787 4788 /* Disable interrupts for the queue. */ 4789 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4790 4791 /* Mark the queue as inactive. */ 4792 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4793 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4794 } 4795 4796 static void 4797 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4798 uint8_t tid, uint16_t ssn) 4799 { 4800 struct iwn_node *wn = (void *)ni; 4801 int qid = 10 + tid; 4802 4803 /* Stop TX scheduler while we're changing its configuration. */ 4804 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4805 IWN5000_TXQ_STATUS_CHGACT); 4806 4807 /* Assign RA/TID translation to the queue. */ 4808 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4809 wn->id << 4 | tid); 4810 4811 /* Enable chain-building mode for the queue. */ 4812 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4813 4814 /* Enable aggregation for the queue. */ 4815 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4816 4817 /* Set starting sequence number from the ADDBA request. */ 4818 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4819 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4820 4821 /* Set scheduler window size and frame limit. */ 4822 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4823 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4824 4825 /* Enable interrupts for the queue. */ 4826 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4827 4828 /* Mark the queue as active. */ 4829 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4830 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4831 } 4832 4833 static void 4834 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4835 { 4836 int qid = 10 + tid; 4837 4838 /* Stop TX scheduler while we're changing its configuration. */ 4839 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4840 IWN5000_TXQ_STATUS_CHGACT); 4841 4842 /* Disable aggregation for the queue. */ 4843 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4844 4845 /* Set starting sequence number from the ADDBA request. */ 4846 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4847 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4848 4849 /* Disable interrupts for the queue. */ 4850 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4851 4852 /* Mark the queue as inactive. */ 4853 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4854 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4855 } 4856 #endif /* !IEEE80211_NO_HT */ 4857 4858 /* 4859 * Query calibration tables from the initialization firmware. We do this 4860 * only once at first boot. Called from a process context. 4861 */ 4862 static int 4863 iwn5000_query_calibration(struct iwn_softc *sc) 4864 { 4865 struct iwn5000_calib_config cmd; 4866 int error; 4867 4868 memset(&cmd, 0, sizeof cmd); 4869 cmd.ucode.once.enable = 0xffffffff; 4870 cmd.ucode.once.start = 0xffffffff; 4871 cmd.ucode.once.send = 0xffffffff; 4872 cmd.ucode.flags = 0xffffffff; 4873 DPRINTF(("sending calibration query\n")); 4874 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4875 if (error != 0) 4876 return error; 4877 4878 /* Wait at most two seconds for calibration to complete. */ 4879 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4880 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4881 return error; 4882 } 4883 4884 /* 4885 * Send calibration results to the runtime firmware. These results were 4886 * obtained on first boot from the initialization firmware. 4887 */ 4888 static int 4889 iwn5000_send_calibration(struct iwn_softc *sc) 4890 { 4891 int idx, error; 4892 4893 for (idx = 0; idx < 5; idx++) { 4894 if (sc->calibcmd[idx].buf == NULL) 4895 continue; /* No results available. */ 4896 DPRINTF(("send calibration result idx=%d len=%d\n", 4897 idx, sc->calibcmd[idx].len)); 4898 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4899 sc->calibcmd[idx].len, 0); 4900 if (error != 0) { 4901 aprint_error_dev(sc->sc_dev, 4902 "could not send calibration result\n"); 4903 return error; 4904 } 4905 } 4906 return 0; 4907 } 4908 4909 static int 4910 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4911 { 4912 struct iwn5000_wimax_coex wimax; 4913 4914 #ifdef notyet 4915 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4916 /* Enable WiMAX coexistence for combo adapters. */ 4917 wimax.flags = 4918 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4919 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4920 IWN_WIMAX_COEX_STA_TABLE_VALID | 4921 IWN_WIMAX_COEX_ENABLE; 4922 memcpy(wimax.events, iwn6050_wimax_events, 4923 sizeof iwn6050_wimax_events); 4924 } else 4925 #endif 4926 { 4927 /* Disable WiMAX coexistence. */ 4928 wimax.flags = 0; 4929 memset(wimax.events, 0, sizeof wimax.events); 4930 } 4931 DPRINTF(("Configuring WiMAX coexistence\n")); 4932 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4933 } 4934 4935 /* 4936 * This function is called after the runtime firmware notifies us of its 4937 * readiness (called in a process context.) 4938 */ 4939 static int 4940 iwn4965_post_alive(struct iwn_softc *sc) 4941 { 4942 int error, qid; 4943 4944 if ((error = iwn_nic_lock(sc)) != 0) 4945 return error; 4946 4947 /* Clear TX scheduler state in SRAM. */ 4948 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4949 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4950 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 4951 4952 /* Set physical address of TX scheduler rings (1KB aligned.) */ 4953 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4954 4955 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4956 4957 /* Disable chain mode for all our 16 queues. */ 4958 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4959 4960 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4961 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4962 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4963 4964 /* Set scheduler window size. */ 4965 iwn_mem_write(sc, sc->sched_base + 4966 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4967 /* Set scheduler frame limit. */ 4968 iwn_mem_write(sc, sc->sched_base + 4969 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4970 IWN_SCHED_LIMIT << 16); 4971 } 4972 4973 /* Enable interrupts for all our 16 queues. */ 4974 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4975 /* Identify TX FIFO rings (0-7). */ 4976 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4977 4978 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4979 for (qid = 0; qid < 7; qid++) { 4980 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4981 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4982 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4983 } 4984 iwn_nic_unlock(sc); 4985 return 0; 4986 } 4987 4988 /* 4989 * This function is called after the initialization or runtime firmware 4990 * notifies us of its readiness (called in a process context.) 4991 */ 4992 static int 4993 iwn5000_post_alive(struct iwn_softc *sc) 4994 { 4995 int error, qid; 4996 4997 /* Switch to using ICT interrupt mode. */ 4998 iwn5000_ict_reset(sc); 4999 5000 if ((error = iwn_nic_lock(sc)) != 0) 5001 return error; 5002 5003 /* Clear TX scheduler state in SRAM. */ 5004 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5005 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5006 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5007 5008 /* Set physical address of TX scheduler rings (1KB aligned.) */ 5009 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5010 5011 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5012 5013 /* Enable chain mode for all queues, except command queue. */ 5014 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5015 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5016 5017 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5018 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5019 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5020 5021 iwn_mem_write(sc, sc->sched_base + 5022 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5023 /* Set scheduler window size and frame limit. */ 5024 iwn_mem_write(sc, sc->sched_base + 5025 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5026 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5027 } 5028 5029 /* Enable interrupts for all our 20 queues. */ 5030 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5031 /* Identify TX FIFO rings (0-7). */ 5032 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5033 5034 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5035 for (qid = 0; qid < 7; qid++) { 5036 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5037 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5038 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5039 } 5040 iwn_nic_unlock(sc); 5041 5042 /* Configure WiMAX coexistence for combo adapters. */ 5043 error = iwn5000_send_wimax_coex(sc); 5044 if (error != 0) { 5045 aprint_error_dev(sc->sc_dev, 5046 "could not configure WiMAX coexistence\n"); 5047 return error; 5048 } 5049 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5050 struct iwn5000_phy_calib_crystal cmd; 5051 5052 /* Perform crystal calibration. */ 5053 memset(&cmd, 0, sizeof cmd); 5054 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5055 cmd.ngroups = 1; 5056 cmd.isvalid = 1; 5057 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5058 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5059 DPRINTF(("sending crystal calibration %d, %d\n", 5060 cmd.cap_pin[0], cmd.cap_pin[1])); 5061 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5062 if (error != 0) { 5063 aprint_error_dev(sc->sc_dev, 5064 "crystal calibration failed\n"); 5065 return error; 5066 } 5067 } 5068 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5069 /* Query calibration from the initialization firmware. */ 5070 if ((error = iwn5000_query_calibration(sc)) != 0) { 5071 aprint_error_dev(sc->sc_dev, 5072 "could not query calibration\n"); 5073 return error; 5074 } 5075 /* 5076 * We have the calibration results now, reboot with the 5077 * runtime firmware (call ourselves recursively!) 5078 */ 5079 iwn_hw_stop(sc); 5080 error = iwn_hw_init(sc); 5081 } else { 5082 /* Send calibration results to runtime firmware. */ 5083 error = iwn5000_send_calibration(sc); 5084 } 5085 return error; 5086 } 5087 5088 /* 5089 * The firmware boot code is small and is intended to be copied directly into 5090 * the NIC internal memory (no DMA transfer.) 5091 */ 5092 static int 5093 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5094 { 5095 int error, ntries; 5096 5097 size /= sizeof (uint32_t); 5098 5099 if ((error = iwn_nic_lock(sc)) != 0) 5100 return error; 5101 5102 /* Copy microcode image into NIC memory. */ 5103 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5104 (const uint32_t *)ucode, size); 5105 5106 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5107 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5108 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5109 5110 /* Start boot load now. */ 5111 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5112 5113 /* Wait for transfer to complete. */ 5114 for (ntries = 0; ntries < 1000; ntries++) { 5115 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5116 IWN_BSM_WR_CTRL_START)) 5117 break; 5118 DELAY(10); 5119 } 5120 if (ntries == 1000) { 5121 aprint_error_dev(sc->sc_dev, 5122 "could not load boot firmware\n"); 5123 iwn_nic_unlock(sc); 5124 return ETIMEDOUT; 5125 } 5126 5127 /* Enable boot after power up. */ 5128 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5129 5130 iwn_nic_unlock(sc); 5131 return 0; 5132 } 5133 5134 static int 5135 iwn4965_load_firmware(struct iwn_softc *sc) 5136 { 5137 struct iwn_fw_info *fw = &sc->fw; 5138 struct iwn_dma_info *dma = &sc->fw_dma; 5139 int error; 5140 5141 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5142 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5143 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5144 BUS_DMASYNC_PREWRITE); 5145 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5146 fw->init.text, fw->init.textsz); 5147 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5148 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5149 5150 /* Tell adapter where to find initialization sections. */ 5151 if ((error = iwn_nic_lock(sc)) != 0) 5152 return error; 5153 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5154 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5155 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5156 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5157 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5158 iwn_nic_unlock(sc); 5159 5160 /* Load firmware boot code. */ 5161 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5162 if (error != 0) { 5163 aprint_error_dev(sc->sc_dev, 5164 "could not load boot firmware\n"); 5165 return error; 5166 } 5167 /* Now press "execute". */ 5168 IWN_WRITE(sc, IWN_RESET, 0); 5169 5170 /* Wait at most one second for first alive notification. */ 5171 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5172 aprint_error_dev(sc->sc_dev, 5173 "timeout waiting for adapter to initialize\n"); 5174 return error; 5175 } 5176 5177 /* Retrieve current temperature for initial TX power calibration. */ 5178 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5179 sc->temp = iwn4965_get_temperature(sc); 5180 5181 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5182 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5183 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5184 BUS_DMASYNC_PREWRITE); 5185 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5186 fw->main.text, fw->main.textsz); 5187 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5188 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5189 5190 /* Tell adapter where to find runtime sections. */ 5191 if ((error = iwn_nic_lock(sc)) != 0) 5192 return error; 5193 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5194 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5195 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5196 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5197 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5198 IWN_FW_UPDATED | fw->main.textsz); 5199 iwn_nic_unlock(sc); 5200 5201 return 0; 5202 } 5203 5204 static int 5205 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5206 const uint8_t *section, int size) 5207 { 5208 struct iwn_dma_info *dma = &sc->fw_dma; 5209 int error; 5210 5211 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5212 memcpy(dma->vaddr, section, size); 5213 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5214 5215 if ((error = iwn_nic_lock(sc)) != 0) 5216 return error; 5217 5218 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5219 IWN_FH_TX_CONFIG_DMA_PAUSE); 5220 5221 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5222 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5223 IWN_LOADDR(dma->paddr)); 5224 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5225 IWN_HIADDR(dma->paddr) << 28 | size); 5226 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5227 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5228 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5229 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5230 5231 /* Kick Flow Handler to start DMA transfer. */ 5232 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5233 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5234 5235 iwn_nic_unlock(sc); 5236 5237 /* Wait at most five seconds for FH DMA transfer to complete. */ 5238 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5239 } 5240 5241 static int 5242 iwn5000_load_firmware(struct iwn_softc *sc) 5243 { 5244 struct iwn_fw_part *fw; 5245 int error; 5246 5247 /* Load the initialization firmware on first boot only. */ 5248 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5249 &sc->fw.main : &sc->fw.init; 5250 5251 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5252 fw->text, fw->textsz); 5253 if (error != 0) { 5254 aprint_error_dev(sc->sc_dev, 5255 "could not load firmware %s section\n", ".text"); 5256 return error; 5257 } 5258 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5259 fw->data, fw->datasz); 5260 if (error != 0) { 5261 aprint_error_dev(sc->sc_dev, 5262 "could not load firmware %s section\n", ".data"); 5263 return error; 5264 } 5265 5266 /* Now press "execute". */ 5267 IWN_WRITE(sc, IWN_RESET, 0); 5268 return 0; 5269 } 5270 5271 /* 5272 * Extract text and data sections from a legacy firmware image. 5273 */ 5274 static int 5275 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5276 { 5277 const uint32_t *ptr; 5278 size_t hdrlen = 24; 5279 uint32_t rev; 5280 5281 ptr = (const uint32_t *)fw->data; 5282 rev = le32toh(*ptr++); 5283 5284 /* Check firmware API version. */ 5285 if (IWN_FW_API(rev) <= 1) { 5286 aprint_error_dev(sc->sc_dev, 5287 "bad firmware, need API version >=2\n"); 5288 return EINVAL; 5289 } 5290 if (IWN_FW_API(rev) >= 3) { 5291 /* Skip build number (version 2 header). */ 5292 hdrlen += 4; 5293 ptr++; 5294 } 5295 if (fw->size < hdrlen) { 5296 aprint_error_dev(sc->sc_dev, 5297 "firmware too short: %zd bytes\n", fw->size); 5298 return EINVAL; 5299 } 5300 fw->main.textsz = le32toh(*ptr++); 5301 fw->main.datasz = le32toh(*ptr++); 5302 fw->init.textsz = le32toh(*ptr++); 5303 fw->init.datasz = le32toh(*ptr++); 5304 fw->boot.textsz = le32toh(*ptr++); 5305 5306 /* Check that all firmware sections fit. */ 5307 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5308 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5309 aprint_error_dev(sc->sc_dev, 5310 "firmware too short: %zd bytes\n", fw->size); 5311 return EINVAL; 5312 } 5313 5314 /* Get pointers to firmware sections. */ 5315 fw->main.text = (const uint8_t *)ptr; 5316 fw->main.data = fw->main.text + fw->main.textsz; 5317 fw->init.text = fw->main.data + fw->main.datasz; 5318 fw->init.data = fw->init.text + fw->init.textsz; 5319 fw->boot.text = fw->init.data + fw->init.datasz; 5320 return 0; 5321 } 5322 5323 /* 5324 * Extract text and data sections from a TLV firmware image. 5325 */ 5326 static int 5327 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5328 uint16_t alt) 5329 { 5330 const struct iwn_fw_tlv_hdr *hdr; 5331 const struct iwn_fw_tlv *tlv; 5332 const uint8_t *ptr, *end; 5333 uint64_t altmask; 5334 uint32_t len; 5335 5336 if (fw->size < sizeof (*hdr)) { 5337 aprint_error_dev(sc->sc_dev, 5338 "firmware too short: %zd bytes\n", fw->size); 5339 return EINVAL; 5340 } 5341 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5342 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5343 aprint_error_dev(sc->sc_dev, 5344 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5345 return EINVAL; 5346 } 5347 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5348 le32toh(hdr->build))); 5349 5350 /* 5351 * Select the closest supported alternative that is less than 5352 * or equal to the specified one. 5353 */ 5354 altmask = le64toh(hdr->altmask); 5355 while (alt > 0 && !(altmask & (1ULL << alt))) 5356 alt--; /* Downgrade. */ 5357 DPRINTF(("using alternative %d\n", alt)); 5358 5359 ptr = (const uint8_t *)(hdr + 1); 5360 end = (const uint8_t *)(fw->data + fw->size); 5361 5362 /* Parse type-length-value fields. */ 5363 while (ptr + sizeof (*tlv) <= end) { 5364 tlv = (const struct iwn_fw_tlv *)ptr; 5365 len = le32toh(tlv->len); 5366 5367 ptr += sizeof (*tlv); 5368 if (ptr + len > end) { 5369 aprint_error_dev(sc->sc_dev, 5370 "firmware too short: %zd bytes\n", fw->size); 5371 return EINVAL; 5372 } 5373 /* Skip other alternatives. */ 5374 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5375 goto next; 5376 5377 switch (le16toh(tlv->type)) { 5378 case IWN_FW_TLV_MAIN_TEXT: 5379 fw->main.text = ptr; 5380 fw->main.textsz = len; 5381 break; 5382 case IWN_FW_TLV_MAIN_DATA: 5383 fw->main.data = ptr; 5384 fw->main.datasz = len; 5385 break; 5386 case IWN_FW_TLV_INIT_TEXT: 5387 fw->init.text = ptr; 5388 fw->init.textsz = len; 5389 break; 5390 case IWN_FW_TLV_INIT_DATA: 5391 fw->init.data = ptr; 5392 fw->init.datasz = len; 5393 break; 5394 case IWN_FW_TLV_BOOT_TEXT: 5395 fw->boot.text = ptr; 5396 fw->boot.textsz = len; 5397 break; 5398 default: 5399 DPRINTF(("TLV type %d not handled\n", 5400 le16toh(tlv->type))); 5401 break; 5402 } 5403 next: /* TLV fields are 32-bit aligned. */ 5404 ptr += (len + 3) & ~3; 5405 } 5406 return 0; 5407 } 5408 5409 static int 5410 iwn_read_firmware(struct iwn_softc *sc) 5411 { 5412 const struct iwn_hal *hal = sc->sc_hal; 5413 struct iwn_fw_info *fw = &sc->fw; 5414 firmware_handle_t fwh; 5415 int error; 5416 5417 /* Initialize for error returns */ 5418 fw->data = NULL; 5419 fw->size = 0; 5420 5421 /* Open firmware image. */ 5422 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5423 aprint_error_dev(sc->sc_dev, 5424 "could not get firmware handle %s\n", sc->fwname); 5425 return error; 5426 } 5427 fw->size = firmware_get_size(fwh); 5428 if (fw->size < sizeof (uint32_t)) { 5429 aprint_error_dev(sc->sc_dev, 5430 "firmware too short: %zd bytes\n", fw->size); 5431 firmware_close(fwh); 5432 return EINVAL; 5433 } 5434 5435 /* Read the firmware. */ 5436 fw->data = firmware_malloc(fw->size); 5437 if (fw->data == NULL) { 5438 aprint_error_dev(sc->sc_dev, 5439 "not enough memory to stock firmware %s\n", sc->fwname); 5440 firmware_close(fwh); 5441 return ENOMEM; 5442 } 5443 error = firmware_read(fwh, 0, fw->data, fw->size); 5444 firmware_close(fwh); 5445 if (error != 0) { 5446 aprint_error_dev(sc->sc_dev, 5447 "could not read firmware %s\n", sc->fwname); 5448 goto out; 5449 } 5450 5451 /* Retrieve text and data sections. */ 5452 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5453 error = iwn_read_firmware_leg(sc, fw); 5454 else 5455 error = iwn_read_firmware_tlv(sc, fw, 1); 5456 if (error != 0) { 5457 aprint_error_dev(sc->sc_dev, 5458 "could not read firmware sections\n"); 5459 goto out; 5460 } 5461 5462 /* Make sure text and data sections fit in hardware memory. */ 5463 if (fw->main.textsz > hal->fw_text_maxsz || 5464 fw->main.datasz > hal->fw_data_maxsz || 5465 fw->init.textsz > hal->fw_text_maxsz || 5466 fw->init.datasz > hal->fw_data_maxsz || 5467 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5468 (fw->boot.textsz & 3) != 0) { 5469 aprint_error_dev(sc->sc_dev, 5470 "firmware sections too large\n"); 5471 goto out; 5472 } 5473 5474 /* We can proceed with loading the firmware. */ 5475 return 0; 5476 out: 5477 firmware_free(fw->data, fw->size); 5478 fw->data = NULL; 5479 fw->size = 0; 5480 return error ? error : EINVAL; 5481 } 5482 5483 static int 5484 iwn_clock_wait(struct iwn_softc *sc) 5485 { 5486 int ntries; 5487 5488 /* Set "initialization complete" bit. */ 5489 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5490 5491 /* Wait for clock stabilization. */ 5492 for (ntries = 0; ntries < 2500; ntries++) { 5493 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5494 return 0; 5495 DELAY(10); 5496 } 5497 aprint_error_dev(sc->sc_dev, 5498 "timeout waiting for clock stabilization\n"); 5499 return ETIMEDOUT; 5500 } 5501 5502 static int 5503 iwn_apm_init(struct iwn_softc *sc) 5504 { 5505 pcireg_t reg; 5506 int error; 5507 5508 /* Disable L0s exit timer (NMI bug workaround.) */ 5509 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5510 /* Don't wait for ICH L0s (ICH bug workaround.) */ 5511 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5512 5513 /* Set FH wait threshold to max (HW bug under stress workaround.) */ 5514 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5515 5516 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5517 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5518 5519 /* Retrieve PCIe Active State Power Management (ASPM). */ 5520 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5521 sc->sc_cap_off + PCI_PCIE_LCSR); 5522 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5523 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5524 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5525 else 5526 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5527 5528 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5529 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5530 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5531 5532 /* Wait for clock stabilization before accessing prph. */ 5533 if ((error = iwn_clock_wait(sc)) != 0) 5534 return error; 5535 5536 if ((error = iwn_nic_lock(sc)) != 0) 5537 return error; 5538 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5539 /* Enable DMA and BSM (Bootstrap State Machine.) */ 5540 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5541 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5542 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5543 } else { 5544 /* Enable DMA. */ 5545 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5546 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5547 } 5548 DELAY(20); 5549 /* Disable L1-Active. */ 5550 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5551 iwn_nic_unlock(sc); 5552 5553 return 0; 5554 } 5555 5556 static void 5557 iwn_apm_stop_master(struct iwn_softc *sc) 5558 { 5559 int ntries; 5560 5561 /* Stop busmaster DMA activity. */ 5562 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5563 for (ntries = 0; ntries < 100; ntries++) { 5564 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5565 return; 5566 DELAY(10); 5567 } 5568 aprint_error_dev(sc->sc_dev, 5569 "timeout waiting for master\n"); 5570 } 5571 5572 static void 5573 iwn_apm_stop(struct iwn_softc *sc) 5574 { 5575 iwn_apm_stop_master(sc); 5576 5577 /* Reset the entire device. */ 5578 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5579 DELAY(10); 5580 /* Clear "initialization complete" bit. */ 5581 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5582 } 5583 5584 static int 5585 iwn4965_nic_config(struct iwn_softc *sc) 5586 { 5587 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5588 /* 5589 * I don't believe this to be correct but this is what the 5590 * vendor driver is doing. Probably the bits should not be 5591 * shifted in IWN_RFCFG_*. 5592 */ 5593 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5594 IWN_RFCFG_TYPE(sc->rfcfg) | 5595 IWN_RFCFG_STEP(sc->rfcfg) | 5596 IWN_RFCFG_DASH(sc->rfcfg)); 5597 } 5598 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5599 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5600 return 0; 5601 } 5602 5603 static int 5604 iwn5000_nic_config(struct iwn_softc *sc) 5605 { 5606 uint32_t tmp; 5607 int error; 5608 5609 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5610 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5611 IWN_RFCFG_TYPE(sc->rfcfg) | 5612 IWN_RFCFG_STEP(sc->rfcfg) | 5613 IWN_RFCFG_DASH(sc->rfcfg)); 5614 } 5615 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5616 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5617 5618 if ((error = iwn_nic_lock(sc)) != 0) 5619 return error; 5620 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5621 5622 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5623 /* 5624 * Select first Switching Voltage Regulator (1.32V) to 5625 * solve a stability issue related to noisy DC2DC line 5626 * in the silicon of 1000 Series. 5627 */ 5628 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5629 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5630 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5631 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5632 } 5633 iwn_nic_unlock(sc); 5634 5635 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5636 /* Use internal power amplifier only. */ 5637 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5638 } 5639 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) { 5640 /* Indicate that ROM calibration version is >=6. */ 5641 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5642 } 5643 return 0; 5644 } 5645 5646 /* 5647 * Take NIC ownership over Intel Active Management Technology (AMT). 5648 */ 5649 static int 5650 iwn_hw_prepare(struct iwn_softc *sc) 5651 { 5652 int ntries; 5653 5654 /* Check if hardware is ready. */ 5655 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5656 for (ntries = 0; ntries < 5; ntries++) { 5657 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5658 IWN_HW_IF_CONFIG_NIC_READY) 5659 return 0; 5660 DELAY(10); 5661 } 5662 5663 /* Hardware not ready, force into ready state. */ 5664 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5665 for (ntries = 0; ntries < 15000; ntries++) { 5666 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5667 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5668 break; 5669 DELAY(10); 5670 } 5671 if (ntries == 15000) 5672 return ETIMEDOUT; 5673 5674 /* Hardware should be ready now. */ 5675 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5676 for (ntries = 0; ntries < 5; ntries++) { 5677 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5678 IWN_HW_IF_CONFIG_NIC_READY) 5679 return 0; 5680 DELAY(10); 5681 } 5682 return ETIMEDOUT; 5683 } 5684 5685 static int 5686 iwn_hw_init(struct iwn_softc *sc) 5687 { 5688 const struct iwn_hal *hal = sc->sc_hal; 5689 int error, chnl, qid; 5690 5691 /* Clear pending interrupts. */ 5692 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5693 5694 if ((error = iwn_apm_init(sc)) != 0) { 5695 aprint_error_dev(sc->sc_dev, 5696 "could not power ON adapter\n"); 5697 return error; 5698 } 5699 5700 /* Select VMAIN power source. */ 5701 if ((error = iwn_nic_lock(sc)) != 0) 5702 return error; 5703 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5704 iwn_nic_unlock(sc); 5705 5706 /* Perform adapter-specific initialization. */ 5707 if ((error = hal->nic_config(sc)) != 0) 5708 return error; 5709 5710 /* Initialize RX ring. */ 5711 if ((error = iwn_nic_lock(sc)) != 0) 5712 return error; 5713 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5714 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5715 /* Set physical address of RX ring (256-byte aligned.) */ 5716 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5717 /* Set physical address of RX status (16-byte aligned.) */ 5718 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5719 /* Enable RX. */ 5720 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5721 IWN_FH_RX_CONFIG_ENA | 5722 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5723 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5724 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5725 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5726 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5727 iwn_nic_unlock(sc); 5728 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5729 5730 if ((error = iwn_nic_lock(sc)) != 0) 5731 return error; 5732 5733 /* Initialize TX scheduler. */ 5734 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5735 5736 /* Set physical address of "keep warm" page (16-byte aligned.) */ 5737 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5738 5739 /* Initialize TX rings. */ 5740 for (qid = 0; qid < hal->ntxqs; qid++) { 5741 struct iwn_tx_ring *txq = &sc->txq[qid]; 5742 5743 /* Set physical address of TX ring (256-byte aligned.) */ 5744 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5745 txq->desc_dma.paddr >> 8); 5746 } 5747 iwn_nic_unlock(sc); 5748 5749 /* Enable DMA channels. */ 5750 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5751 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5752 IWN_FH_TX_CONFIG_DMA_ENA | 5753 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5754 } 5755 5756 /* Clear "radio off" and "commands blocked" bits. */ 5757 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5758 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5759 5760 /* Clear pending interrupts. */ 5761 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5762 /* Enable interrupt coalescing. */ 5763 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5764 /* Enable interrupts. */ 5765 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5766 5767 /* _Really_ make sure "radio off" bit is cleared! */ 5768 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5769 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5770 5771 if ((error = hal->load_firmware(sc)) != 0) { 5772 aprint_error_dev(sc->sc_dev, 5773 "could not load firmware\n"); 5774 return error; 5775 } 5776 /* Wait at most one second for firmware alive notification. */ 5777 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5778 aprint_error_dev(sc->sc_dev, 5779 "timeout waiting for adapter to initialize\n"); 5780 return error; 5781 } 5782 /* Do post-firmware initialization. */ 5783 return hal->post_alive(sc); 5784 } 5785 5786 static void 5787 iwn_hw_stop(struct iwn_softc *sc) 5788 { 5789 const struct iwn_hal *hal = sc->sc_hal; 5790 int chnl, qid, ntries; 5791 uint32_t tmp; 5792 5793 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5794 5795 /* Disable interrupts. */ 5796 IWN_WRITE(sc, IWN_INT_MASK, 0); 5797 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5798 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5799 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5800 5801 /* Make sure we no longer hold the NIC lock. */ 5802 iwn_nic_unlock(sc); 5803 5804 /* Stop TX scheduler. */ 5805 iwn_prph_write(sc, hal->sched_txfact_addr, 0); 5806 5807 /* Stop all DMA channels. */ 5808 if (iwn_nic_lock(sc) == 0) { 5809 for (chnl = 0; chnl < hal->ndmachnls; chnl++) { 5810 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5811 for (ntries = 0; ntries < 200; ntries++) { 5812 tmp = IWN_READ(sc, IWN_FH_TX_STATUS); 5813 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) == 5814 IWN_FH_TX_STATUS_IDLE(chnl)) 5815 break; 5816 DELAY(10); 5817 } 5818 } 5819 iwn_nic_unlock(sc); 5820 } 5821 5822 /* Stop RX ring. */ 5823 iwn_reset_rx_ring(sc, &sc->rxq); 5824 5825 /* Reset all TX rings. */ 5826 for (qid = 0; qid < hal->ntxqs; qid++) 5827 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5828 5829 if (iwn_nic_lock(sc) == 0) { 5830 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5831 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5832 iwn_nic_unlock(sc); 5833 } 5834 DELAY(5); 5835 /* Power OFF adapter. */ 5836 iwn_apm_stop(sc); 5837 } 5838 5839 static int 5840 iwn_init(struct ifnet *ifp) 5841 { 5842 struct iwn_softc *sc = ifp->if_softc; 5843 struct ieee80211com *ic = &sc->sc_ic; 5844 int error; 5845 5846 mutex_enter(&sc->sc_mtx); 5847 if (sc->sc_flags & IWN_FLAG_HW_INITED) 5848 goto out; 5849 if ((error = iwn_hw_prepare(sc)) != 0) { 5850 aprint_error_dev(sc->sc_dev, 5851 "hardware not ready\n"); 5852 goto fail; 5853 } 5854 5855 /* Check that the radio is not disabled by hardware switch. */ 5856 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5857 aprint_error_dev(sc->sc_dev, 5858 "radio is disabled by hardware switch\n"); 5859 error = EPERM; /* :-) */ 5860 goto fail; 5861 } 5862 5863 /* Read firmware images from the filesystem. */ 5864 if ((error = iwn_read_firmware(sc)) != 0) { 5865 aprint_error_dev(sc->sc_dev, 5866 "could not read firmware\n"); 5867 goto fail; 5868 } 5869 5870 /* Initialize interrupt mask to default value. */ 5871 sc->int_mask = IWN_INT_MASK_DEF; 5872 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5873 5874 /* Initialize hardware and upload firmware. */ 5875 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 5876 error = iwn_hw_init(sc); 5877 firmware_free(sc->fw.data, sc->fw.size); 5878 sc->fw.data = NULL; 5879 sc->fw.size = 0; 5880 if (error != 0) { 5881 aprint_error_dev(sc->sc_dev, 5882 "could not initialize hardware\n"); 5883 goto fail; 5884 } 5885 5886 /* Configure adapter now that it is ready. */ 5887 if ((error = iwn_config(sc)) != 0) { 5888 aprint_error_dev(sc->sc_dev, 5889 "could not configure device\n"); 5890 goto fail; 5891 } 5892 5893 ifp->if_flags &= ~IFF_OACTIVE; 5894 ifp->if_flags |= IFF_RUNNING; 5895 5896 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5897 ieee80211_begin_scan(ic, 0); 5898 else 5899 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5900 5901 sc->sc_flags |= IWN_FLAG_HW_INITED; 5902 out: 5903 mutex_exit(&sc->sc_mtx); 5904 return 0; 5905 5906 fail: mutex_exit(&sc->sc_mtx); 5907 iwn_stop(ifp, 1); 5908 return error; 5909 } 5910 5911 static void 5912 iwn_stop(struct ifnet *ifp, int disable) 5913 { 5914 struct iwn_softc *sc = ifp->if_softc; 5915 struct ieee80211com *ic = &sc->sc_ic; 5916 5917 if (!disable) 5918 mutex_enter(&sc->sc_mtx); 5919 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 5920 ifp->if_timer = sc->sc_tx_timer = 0; 5921 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5922 5923 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5924 5925 /* Power OFF hardware. */ 5926 iwn_hw_stop(sc); 5927 5928 #ifndef SMALL_KERNEL 5929 /* Temperature sensor is no longer valid. */ 5930 sc->sc_sensor.value_cur = 0; 5931 sc->sc_sensor.state = ENVSYS_SINVALID; 5932 #endif 5933 if (!disable) 5934 mutex_exit(&sc->sc_mtx); 5935 } 5936 5937 /* 5938 * XXX MCLGETI alternative 5939 * 5940 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5941 * as long as there are available free buffers then it uses MEXTMALLOC., 5942 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5943 * The MCLGET4K code is used for testing an alternative mbuf cache. 5944 */ 5945 5946 static struct mbuf * 5947 MCLGETIalt(struct iwn_softc *sc, int how, 5948 struct ifnet *ifp __unused, u_int size) 5949 { 5950 struct mbuf *m; 5951 #ifdef IWN_USE_RBUF 5952 struct iwn_rbuf *rbuf; 5953 #endif 5954 5955 MGETHDR(m, how, MT_DATA); 5956 if (m == NULL) 5957 return NULL; 5958 5959 #ifdef IWN_USE_RBUF 5960 if (sc->rxq.nb_free_entries > 0 && 5961 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 5962 /* Attach buffer to mbuf header. */ 5963 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 5964 m->m_flags |= M_EXT_RW; 5965 } 5966 else { 5967 MEXTMALLOC(m, size, how); 5968 if ((m->m_flags & M_EXT) == 0) { 5969 m_freem(m); 5970 return NULL; 5971 } 5972 } 5973 5974 #else 5975 #ifdef MCLGET4K 5976 if (size == 4096) 5977 MCLGET4K(m, how); 5978 else 5979 panic("size must be 4k"); 5980 #else 5981 MEXTMALLOC(m, size, how); 5982 #endif 5983 if ((m->m_flags & M_EXT) == 0) { 5984 m_freem(m); 5985 return NULL; 5986 } 5987 #endif 5988 5989 return m; 5990 } 5991 5992 #ifdef IWN_USE_RBUF 5993 static struct iwn_rbuf * 5994 iwn_alloc_rbuf(struct iwn_softc *sc) 5995 { 5996 struct iwn_rbuf *rbuf; 5997 mutex_enter(&sc->rxq.freelist_mtx); 5998 5999 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6000 if (rbuf != NULL) { 6001 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6002 sc->rxq.nb_free_entries --; 6003 } 6004 mutex_exit(&sc->rxq.freelist_mtx); 6005 return rbuf; 6006 } 6007 6008 /* 6009 * This is called automatically by the network stack when the mbuf to which 6010 * our RX buffer is attached is freed. 6011 */ 6012 static void 6013 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6014 { 6015 struct iwn_rbuf *rbuf = arg; 6016 struct iwn_softc *sc = rbuf->sc; 6017 6018 /* Put the RX buffer back in the free list. */ 6019 mutex_enter(&sc->rxq.freelist_mtx); 6020 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6021 mutex_exit(&sc->rxq.freelist_mtx); 6022 6023 sc->rxq.nb_free_entries ++; 6024 if (__predict_true(m != NULL)) 6025 pool_cache_put(mb_cache, m); 6026 } 6027 6028 static int 6029 iwn_alloc_rpool(struct iwn_softc *sc) 6030 { 6031 struct iwn_rx_ring *ring = &sc->rxq; 6032 struct iwn_rbuf *rbuf; 6033 int i, error; 6034 6035 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6036 6037 /* Allocate a big chunk of DMA'able memory... */ 6038 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6039 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6040 if (error != 0) { 6041 aprint_error_dev(sc->sc_dev, 6042 "could not allocate RX buffers DMA memory\n"); 6043 return error; 6044 } 6045 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6046 SLIST_INIT(&ring->freelist); 6047 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6048 rbuf = &ring->rbuf[i]; 6049 6050 rbuf->sc = sc; /* Backpointer for callbacks. */ 6051 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6052 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6053 6054 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6055 } 6056 ring->nb_free_entries = IWN_RBUF_COUNT; 6057 return 0; 6058 } 6059 6060 static void 6061 iwn_free_rpool(struct iwn_softc *sc) 6062 { 6063 iwn_dma_contig_free(&sc->rxq.buf_dma); 6064 } 6065 #endif 6066 6067 /* 6068 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6069 * Copyright (c) 2001 Atsushi Onoe 6070 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6071 * Copyright (c) 2007-2009 Damien Bergamini 6072 * All rights reserved. 6073 */ 6074 6075 /* 6076 * Add an SSID element to a frame (see 7.3.2.1). 6077 */ 6078 static u_int8_t * 6079 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6080 { 6081 *frm++ = IEEE80211_ELEMID_SSID; 6082 *frm++ = len; 6083 memcpy(frm, ssid, len); 6084 return frm + len; 6085 } 6086 6087 /* 6088 * Add a supported rates element to a frame (see 7.3.2.2). 6089 */ 6090 static u_int8_t * 6091 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6092 { 6093 int nrates; 6094 6095 *frm++ = IEEE80211_ELEMID_RATES; 6096 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6097 *frm++ = nrates; 6098 memcpy(frm, rs->rs_rates, nrates); 6099 return frm + nrates; 6100 } 6101 6102 /* 6103 * Add an extended supported rates element to a frame (see 7.3.2.14). 6104 */ 6105 static u_int8_t * 6106 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6107 { 6108 int nrates; 6109 6110 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6111 6112 *frm++ = IEEE80211_ELEMID_XRATES; 6113 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6114 *frm++ = nrates; 6115 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6116 return frm + nrates; 6117 } 6118 6119 /* 6120 * XXX: Hack to set the current channel to the value advertised in beacons or 6121 * probe responses. Only used during AP detection. 6122 * XXX: Duplicated from if_iwi.c 6123 */ 6124 static void 6125 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6126 { 6127 struct ieee80211_frame *wh; 6128 uint8_t subtype; 6129 uint8_t *frm, *efrm; 6130 6131 wh = mtod(m, struct ieee80211_frame *); 6132 6133 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6134 return; 6135 6136 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6137 6138 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6139 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6140 return; 6141 6142 frm = (uint8_t *)(wh + 1); 6143 efrm = mtod(m, uint8_t *) + m->m_len; 6144 6145 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6146 while (frm < efrm) { 6147 if (*frm == IEEE80211_ELEMID_DSPARMS) 6148 #if IEEE80211_CHAN_MAX < 255 6149 if (frm[2] <= IEEE80211_CHAN_MAX) 6150 #endif 6151 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6152 6153 frm += frm[1] + 2; 6154 } 6155 } 6156 6157
Indexes created Mon Sep 29 03:10:08 GMT 2025