if_iwn.c revision 1.53
1 /* $NetBSD: if_iwn.c,v 1.53 2011/05/15 13:56:20 christos Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.96 2010/05/13 09:25:03 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.53 2011/05/15 13:56:20 christos Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/conf.h> 40 #include <sys/kauth.h> 41 #include <sys/callout.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 45 #include <machine/bus.h> 46 #include <machine/endian.h> 47 #include <machine/intr.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <net/if_ether.h> 64 #include <netinet/ip.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_amrr.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <dev/firmload.h> 71 72 #include <dev/pci/if_iwnreg.h> 73 #include <dev/pci/if_iwnvar.h> 74 75 static const pci_product_id_t iwn_devices[] = { 76 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 77 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 78 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 79 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 80 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 81 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 82 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 83 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 84 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 86 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 87 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 88 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 89 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 90 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 91 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 92 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 93 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 94 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 96 #ifdef notyet 97 /* 98 * XXX NetBSD: the 6005A replaces the two 6005, above 99 * (see OpenBSD rev 1.96). 100 */ 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005A_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005A_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_1X1_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_1X1_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_1, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_2, 107 PCI_PRODUCT_INTEL_WIFI_LINK_6005B_2X2_3 108 #endif 109 }; 110 111 /* 112 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 113 */ 114 static const struct ieee80211_rateset iwn_rateset_11a = 115 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 116 117 static const struct ieee80211_rateset iwn_rateset_11b = 118 { 4, { 2, 4, 11, 22 } }; 119 120 static const struct ieee80211_rateset iwn_rateset_11g = 121 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 122 123 static int iwn_match(device_t , struct cfdata *, void *); 124 static void iwn_attach(device_t , device_t , void *); 125 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 126 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 127 static void iwn_radiotap_attach(struct iwn_softc *); 128 static int iwn_detach(device_t , int); 129 #if 0 130 static void iwn_power(int, void *); 131 #endif 132 static bool iwn_resume(device_t, const pmf_qual_t *); 133 static int iwn_nic_lock(struct iwn_softc *); 134 static int iwn_eeprom_lock(struct iwn_softc *); 135 static int iwn_init_otprom(struct iwn_softc *); 136 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 137 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 138 void **, bus_size_t, bus_size_t); 139 static void iwn_dma_contig_free(struct iwn_dma_info *); 140 static int iwn_alloc_sched(struct iwn_softc *); 141 static void iwn_free_sched(struct iwn_softc *); 142 static int iwn_alloc_kw(struct iwn_softc *); 143 static void iwn_free_kw(struct iwn_softc *); 144 static int iwn_alloc_ict(struct iwn_softc *); 145 static void iwn_free_ict(struct iwn_softc *); 146 static int iwn_alloc_fwmem(struct iwn_softc *); 147 static void iwn_free_fwmem(struct iwn_softc *); 148 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 149 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 150 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 151 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 152 int); 153 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 154 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 155 static void iwn5000_ict_reset(struct iwn_softc *); 156 static int iwn_read_eeprom(struct iwn_softc *); 157 static void iwn4965_read_eeprom(struct iwn_softc *); 158 159 #define IWN_DEBUG 1 160 #ifdef IWN_DEBUG 161 static void iwn4965_print_power_group(struct iwn_softc *, int); 162 #endif 163 static void iwn5000_read_eeprom(struct iwn_softc *); 164 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 165 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 166 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 167 static void iwn_newassoc(struct ieee80211_node *, int); 168 static int iwn_media_change(struct ifnet *); 169 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 170 static void iwn_iter_func(void *, struct ieee80211_node *); 171 static void iwn_calib_timeout(void *); 172 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 173 struct iwn_rx_data *); 174 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 #ifndef IEEE80211_NO_HT 177 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 178 struct iwn_rx_data *); 179 #endif 180 static void iwn5000_rx_calib_results(struct iwn_softc *, 181 struct iwn_rx_desc *, struct iwn_rx_data *); 182 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 183 struct iwn_rx_data *); 184 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 185 struct iwn_rx_data *); 186 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 187 struct iwn_rx_data *); 188 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 189 uint8_t); 190 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 191 static void iwn_notif_intr(struct iwn_softc *); 192 static void iwn_wakeup_intr(struct iwn_softc *); 193 static void iwn_fatal_intr(struct iwn_softc *); 194 static int iwn_intr(void *); 195 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 196 uint16_t); 197 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 198 uint16_t); 199 #ifdef notyet 200 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 201 #endif 202 static int iwn_tx(struct iwn_softc *, struct mbuf *, 203 struct ieee80211_node *, int); 204 static void iwn_start(struct ifnet *); 205 static void iwn_watchdog(struct ifnet *); 206 static int iwn_ioctl(struct ifnet *, u_long, void *); 207 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 208 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 209 int); 210 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 211 int); 212 static int iwn_set_link_quality(struct iwn_softc *, 213 struct ieee80211_node *); 214 static int iwn_add_broadcast_node(struct iwn_softc *, int); 215 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 216 static int iwn_set_critical_temp(struct iwn_softc *); 217 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 218 static void iwn4965_power_calibration(struct iwn_softc *, int); 219 static int iwn4965_set_txpower(struct iwn_softc *, int); 220 static int iwn5000_set_txpower(struct iwn_softc *, int); 221 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 222 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 223 static int iwn_get_noise(const struct iwn_rx_general_stats *); 224 static int iwn4965_get_temperature(struct iwn_softc *); 225 static int iwn5000_get_temperature(struct iwn_softc *); 226 static int iwn_init_sensitivity(struct iwn_softc *); 227 static void iwn_collect_noise(struct iwn_softc *, 228 const struct iwn_rx_general_stats *); 229 static int iwn4965_init_gains(struct iwn_softc *); 230 static int iwn5000_init_gains(struct iwn_softc *); 231 static int iwn4965_set_gains(struct iwn_softc *); 232 static int iwn5000_set_gains(struct iwn_softc *); 233 static void iwn_tune_sensitivity(struct iwn_softc *, 234 const struct iwn_rx_stats *); 235 static int iwn_send_sensitivity(struct iwn_softc *); 236 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 237 static int iwn_config(struct iwn_softc *); 238 static int iwn_scan(struct iwn_softc *, uint16_t); 239 static int iwn_auth(struct iwn_softc *); 240 static int iwn_run(struct iwn_softc *); 241 #ifdef IWN_HWCRYPTO 242 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 243 struct ieee80211_key *); 244 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 245 struct ieee80211_key *); 246 #endif 247 static int iwn_wme_update(struct ieee80211com *); 248 #ifndef IEEE80211_NO_HT 249 static int iwn_ampdu_rx_start(struct ieee80211com *, 250 struct ieee80211_node *, uint8_t); 251 static void iwn_ampdu_rx_stop(struct ieee80211com *, 252 struct ieee80211_node *, uint8_t); 253 static int iwn_ampdu_tx_start(struct ieee80211com *, 254 struct ieee80211_node *, uint8_t); 255 static void iwn_ampdu_tx_stop(struct ieee80211com *, 256 struct ieee80211_node *, uint8_t); 257 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 258 struct ieee80211_node *, uint8_t, uint16_t); 259 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 260 uint8_t, uint16_t); 261 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 262 struct ieee80211_node *, uint8_t, uint16_t); 263 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 264 uint8_t, uint16_t); 265 #endif 266 static int iwn5000_query_calibration(struct iwn_softc *); 267 static int iwn5000_send_calibration(struct iwn_softc *); 268 static int iwn5000_send_wimax_coex(struct iwn_softc *); 269 static int iwn4965_post_alive(struct iwn_softc *); 270 static int iwn5000_post_alive(struct iwn_softc *); 271 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 272 int); 273 static int iwn4965_load_firmware(struct iwn_softc *); 274 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 275 const uint8_t *, int); 276 static int iwn5000_load_firmware(struct iwn_softc *); 277 static int iwn_read_firmware_leg(struct iwn_softc *, 278 struct iwn_fw_info *); 279 static int iwn_read_firmware_tlv(struct iwn_softc *, 280 struct iwn_fw_info *, uint16_t); 281 static int iwn_read_firmware(struct iwn_softc *); 282 static int iwn_clock_wait(struct iwn_softc *); 283 static int iwn_apm_init(struct iwn_softc *); 284 static void iwn_apm_stop_master(struct iwn_softc *); 285 static void iwn_apm_stop(struct iwn_softc *); 286 static int iwn4965_nic_config(struct iwn_softc *); 287 static int iwn5000_nic_config(struct iwn_softc *); 288 static int iwn_hw_prepare(struct iwn_softc *); 289 static int iwn_hw_init(struct iwn_softc *); 290 static void iwn_hw_stop(struct iwn_softc *); 291 static int iwn_init(struct ifnet *); 292 static void iwn_stop(struct ifnet *, int); 293 294 /* XXX MCLGETI alternative */ 295 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 296 struct ifnet *, u_int); 297 #ifdef IWN_USE_RBUF 298 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 299 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 300 static int iwn_alloc_rpool(struct iwn_softc *); 301 static void iwn_free_rpool(struct iwn_softc *); 302 #endif 303 304 /* XXX needed by iwn_scan */ 305 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 306 static u_int8_t *ieee80211_add_rates(u_int8_t *, 307 const struct ieee80211_rateset *); 308 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 309 const struct ieee80211_rateset *); 310 311 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 312 313 #ifdef IWN_DEBUG 314 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 315 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 316 int iwn_debug = 0; 317 #else 318 #define DPRINTF(x) 319 #define DPRINTFN(n, x) 320 #endif 321 322 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 323 iwn_detach, NULL); 324 325 static int 326 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 327 { 328 struct pci_attach_args *pa = aux; 329 size_t i; 330 331 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 332 return 0; 333 334 for (i = 0; i < __arraycount(iwn_devices); i++) 335 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 336 return 1; 337 338 return 0; 339 } 340 341 static void 342 iwn_attach(device_t parent __unused, device_t self, void *aux) 343 { 344 struct iwn_softc *sc = device_private(self); 345 struct ieee80211com *ic = &sc->sc_ic; 346 struct ifnet *ifp = &sc->sc_ec.ec_if; 347 struct pci_attach_args *pa = aux; 348 const char *intrstr; 349 char devinfo[256]; 350 pci_intr_handle_t ih; 351 pcireg_t memtype, reg; 352 int i, error; 353 int revision; 354 355 sc->sc_dev = self; 356 sc->sc_pct = pa->pa_pc; 357 sc->sc_pcitag = pa->pa_tag; 358 sc->sc_dmat = pa->pa_dmat; 359 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 360 361 callout_init(&sc->calib_to, 0); 362 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 363 364 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 365 revision = PCI_REVISION(pa->pa_class); 366 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 367 368 /* 369 * Get the offset of the PCI Express Capability Structure in PCI 370 * Configuration Space. 371 */ 372 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 373 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 374 if (error == 0) { 375 aprint_error(": PCIe capability structure not found!\n"); 376 return; 377 } 378 379 /* Clear device-specific "PCI retry timeout" register (41h). */ 380 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 381 if (reg & 0xff00) 382 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 383 384 /* Enable bus-mastering and hardware bug workaround. */ 385 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 386 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 387 reg |= PCI_COMMAND_MASTER_ENABLE; 388 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 389 DPRINTF(("PCIe INTx Disable set\n")); 390 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 391 } 392 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 393 394 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 395 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 396 &sc->sc_sh, NULL, &sc->sc_sz); 397 if (error != 0) { 398 aprint_error(": can't map mem space\n"); 399 return; 400 } 401 402 /* Install interrupt handler. */ 403 if (pci_intr_map(pa, &ih) != 0) { 404 aprint_error(": can't map interrupt\n"); 405 return; 406 } 407 intrstr = pci_intr_string(sc->sc_pct, ih); 408 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 409 if (sc->sc_ih == NULL) { 410 aprint_error(": can't establish interrupt"); 411 if (intrstr != NULL) 412 aprint_error(" at %s", intrstr); 413 aprint_error("\n"); 414 return; 415 } 416 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 417 418 /* Read hardware revision and attach. */ 419 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 420 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 421 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 422 else 423 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 424 if (error != 0) { 425 aprint_error(": could not attach device\n"); 426 return; 427 } 428 429 if ((error = iwn_hw_prepare(sc)) != 0) { 430 aprint_error(": hardware not ready\n"); 431 return; 432 } 433 434 /* Read MAC address, channels, etc from EEPROM. */ 435 if ((error = iwn_read_eeprom(sc)) != 0) { 436 aprint_error(": could not read EEPROM\n"); 437 return; 438 } 439 440 /* Allocate DMA memory for firmware transfers. */ 441 if ((error = iwn_alloc_fwmem(sc)) != 0) { 442 aprint_error(": could not allocate memory for firmware\n"); 443 return; 444 } 445 446 /* Allocate "Keep Warm" page. */ 447 if ((error = iwn_alloc_kw(sc)) != 0) { 448 aprint_error(": could not allocate keep warm page\n"); 449 goto fail1; 450 } 451 452 /* Allocate ICT table for 5000 Series. */ 453 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 454 (error = iwn_alloc_ict(sc)) != 0) { 455 aprint_error(": could not allocate ICT table\n"); 456 goto fail2; 457 } 458 459 /* Allocate TX scheduler "rings". */ 460 if ((error = iwn_alloc_sched(sc)) != 0) { 461 aprint_error(": could not allocate TX scheduler rings\n"); 462 goto fail3; 463 } 464 465 #ifdef IWN_USE_RBUF 466 /* Allocate RX buffers. */ 467 if ((error = iwn_alloc_rpool(sc)) != 0) { 468 aprint_error_dev(self, "could not allocate RX buffers\n"); 469 goto fail3; 470 } 471 #endif 472 473 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 474 for (i = 0; i < sc->ntxqs; i++) { 475 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 476 aprint_error(": could not allocate TX ring %d\n", i); 477 goto fail4; 478 } 479 } 480 481 /* Allocate RX ring. */ 482 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 483 aprint_error(": could not allocate RX ring\n"); 484 goto fail4; 485 } 486 487 /* Clear pending interrupts. */ 488 IWN_WRITE(sc, IWN_INT, 0xffffffff); 489 490 /* Count the number of available chains. */ 491 sc->ntxchains = 492 ((sc->txchainmask >> 2) & 1) + 493 ((sc->txchainmask >> 1) & 1) + 494 ((sc->txchainmask >> 0) & 1); 495 sc->nrxchains = 496 ((sc->rxchainmask >> 2) & 1) + 497 ((sc->rxchainmask >> 1) & 1) + 498 ((sc->rxchainmask >> 0) & 1); 499 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 500 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 501 ether_sprintf(ic->ic_myaddr)); 502 503 ic->ic_ifp = ifp; 504 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 505 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 506 ic->ic_state = IEEE80211_S_INIT; 507 508 /* Set device capabilities. */ 509 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 510 * and IEEE80211_C_PMGT too. */ 511 ic->ic_caps = 512 IEEE80211_C_IBSS | /* IBSS mode support */ 513 IEEE80211_C_WPA | /* 802.11i */ 514 IEEE80211_C_MONITOR | /* monitor mode supported */ 515 IEEE80211_C_TXPMGT | /* tx power management */ 516 IEEE80211_C_SHSLOT | /* short slot time supported */ 517 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 518 IEEE80211_C_WME; /* 802.11e */ 519 520 #ifndef IEEE80211_NO_HT 521 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 522 /* Set HT capabilities. */ 523 ic->ic_htcaps = 524 #if IWN_RBUF_SIZE == 8192 525 IEEE80211_HTCAP_AMSDU7935 | 526 #endif 527 IEEE80211_HTCAP_CBW20_40 | 528 IEEE80211_HTCAP_SGI20 | 529 IEEE80211_HTCAP_SGI40; 530 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 531 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 532 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 533 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 534 else 535 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 536 } 537 #endif /* !IEEE80211_NO_HT */ 538 539 /* Set supported legacy rates. */ 540 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 541 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 542 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 543 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 544 } 545 #ifndef IEEE80211_NO_HT 546 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 547 /* Set supported HT rates. */ 548 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 549 if (sc->nrxchains > 1) 550 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 551 if (sc->nrxchains > 2) 552 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 553 } 554 #endif 555 556 /* IBSS channel undefined for now. */ 557 ic->ic_ibss_chan = &ic->ic_channels[0]; 558 559 ifp->if_softc = sc; 560 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 561 ifp->if_init = iwn_init; 562 ifp->if_ioctl = iwn_ioctl; 563 ifp->if_start = iwn_start; 564 ifp->if_stop = iwn_stop; 565 ifp->if_watchdog = iwn_watchdog; 566 IFQ_SET_READY(&ifp->if_snd); 567 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 568 569 if_attach(ifp); 570 ieee80211_ifattach(ic); 571 ic->ic_node_alloc = iwn_node_alloc; 572 ic->ic_newassoc = iwn_newassoc; 573 #ifdef IWN_HWCRYPTO 574 ic->ic_crypto.cs_key_set = iwn_set_key; 575 ic->ic_crypto.cs_key_delete = iwn_delete_key; 576 #endif 577 ic->ic_wme.wme_update = iwn_wme_update; 578 #ifndef IEEE80211_NO_HT 579 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 580 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 581 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 582 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 583 #endif 584 585 /* Override 802.11 state transition machine. */ 586 sc->sc_newstate = ic->ic_newstate; 587 ic->ic_newstate = iwn_newstate; 588 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 589 590 sc->amrr.amrr_min_success_threshold = 1; 591 sc->amrr.amrr_max_success_threshold = 15; 592 593 iwn_radiotap_attach(sc); 594 595 /* 596 * XXX for NetBSD, OpenBSD timeout_set replaced by 597 * callout_init and callout_setfunc, above. 598 */ 599 600 if (pmf_device_register(self, NULL, iwn_resume)) 601 pmf_class_network_register(self, ifp); 602 else 603 aprint_error_dev(self, "couldn't establish power handler\n"); 604 605 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 606 ieee80211_announce(ic); 607 608 return; 609 610 /* Free allocated memory if something failed during attachment. */ 611 fail4: while (--i >= 0) 612 iwn_free_tx_ring(sc, &sc->txq[i]); 613 #ifdef IWN_USE_RBUF 614 iwn_free_rpool(sc); 615 #endif 616 iwn_free_sched(sc); 617 fail3: if (sc->ict != NULL) 618 iwn_free_ict(sc); 619 fail2: iwn_free_kw(sc); 620 fail1: iwn_free_fwmem(sc); 621 } 622 623 int 624 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 625 { 626 struct iwn_ops *ops = &sc->ops; 627 628 ops->load_firmware = iwn4965_load_firmware; 629 ops->read_eeprom = iwn4965_read_eeprom; 630 ops->post_alive = iwn4965_post_alive; 631 ops->nic_config = iwn4965_nic_config; 632 ops->update_sched = iwn4965_update_sched; 633 ops->get_temperature = iwn4965_get_temperature; 634 ops->get_rssi = iwn4965_get_rssi; 635 ops->set_txpower = iwn4965_set_txpower; 636 ops->init_gains = iwn4965_init_gains; 637 ops->set_gains = iwn4965_set_gains; 638 ops->add_node = iwn4965_add_node; 639 ops->tx_done = iwn4965_tx_done; 640 #ifndef IEEE80211_NO_HT 641 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 642 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 643 #endif 644 sc->ntxqs = IWN4965_NTXQUEUES; 645 sc->ndmachnls = IWN4965_NDMACHNLS; 646 sc->broadcast_id = IWN4965_ID_BROADCAST; 647 sc->rxonsz = IWN4965_RXONSZ; 648 sc->schedsz = IWN4965_SCHEDSZ; 649 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 650 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 651 sc->fwsz = IWN4965_FWSZ; 652 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 653 sc->limits = &iwn4965_sensitivity_limits; 654 sc->fwname = "iwlwifi-4965-2.ucode"; 655 /* Override chains masks, ROM is known to be broken. */ 656 sc->txchainmask = IWN_ANT_AB; 657 sc->rxchainmask = IWN_ANT_ABC; 658 659 return 0; 660 } 661 662 int 663 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 664 { 665 struct iwn_ops *ops = &sc->ops; 666 667 ops->load_firmware = iwn5000_load_firmware; 668 ops->read_eeprom = iwn5000_read_eeprom; 669 ops->post_alive = iwn5000_post_alive; 670 ops->nic_config = iwn5000_nic_config; 671 ops->update_sched = iwn5000_update_sched; 672 ops->get_temperature = iwn5000_get_temperature; 673 ops->get_rssi = iwn5000_get_rssi; 674 ops->set_txpower = iwn5000_set_txpower; 675 ops->init_gains = iwn5000_init_gains; 676 ops->set_gains = iwn5000_set_gains; 677 ops->add_node = iwn5000_add_node; 678 ops->tx_done = iwn5000_tx_done; 679 #ifndef IEEE80211_NO_HT 680 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 681 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 682 #endif 683 sc->ntxqs = IWN5000_NTXQUEUES; 684 sc->ndmachnls = IWN5000_NDMACHNLS; 685 sc->broadcast_id = IWN5000_ID_BROADCAST; 686 sc->rxonsz = IWN5000_RXONSZ; 687 sc->schedsz = IWN5000_SCHEDSZ; 688 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 689 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 690 sc->fwsz = IWN5000_FWSZ; 691 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 692 693 switch (sc->hw_type) { 694 case IWN_HW_REV_TYPE_5100: 695 sc->limits = &iwn5000_sensitivity_limits; 696 sc->fwname = "iwlwifi-5000-2.ucode"; 697 /* Override chains masks, ROM is known to be broken. */ 698 sc->txchainmask = IWN_ANT_B; 699 sc->rxchainmask = IWN_ANT_AB; 700 break; 701 case IWN_HW_REV_TYPE_5150: 702 sc->limits = &iwn5150_sensitivity_limits; 703 sc->fwname = "iwlwifi-5150-2.ucode"; 704 break; 705 case IWN_HW_REV_TYPE_5300: 706 case IWN_HW_REV_TYPE_5350: 707 sc->limits = &iwn5000_sensitivity_limits; 708 sc->fwname = "iwlwifi-5000-2.ucode"; 709 break; 710 case IWN_HW_REV_TYPE_1000: 711 sc->limits = &iwn1000_sensitivity_limits; 712 sc->fwname = "iwlwifi-1000-3.ucode"; 713 break; 714 case IWN_HW_REV_TYPE_6000: 715 sc->limits = &iwn6000_sensitivity_limits; 716 sc->fwname = "iwlwifi-6000-4.ucode"; 717 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 718 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 719 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 720 /* Override chains masks, ROM is known to be broken. */ 721 sc->txchainmask = IWN_ANT_BC; 722 sc->rxchainmask = IWN_ANT_BC; 723 } 724 break; 725 case IWN_HW_REV_TYPE_6050: 726 sc->limits = &iwn6000_sensitivity_limits; 727 sc->fwname = "iwlwifi-6050-2.ucode"; 728 break; 729 case IWN_HW_REV_TYPE_6005: 730 sc->limits = &iwn6000_sensitivity_limits; 731 sc->fwname = "iwlwifi-6005-2.ucode"; 732 break; 733 default: 734 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 735 return ENOTSUP; 736 } 737 return 0; 738 } 739 740 /* 741 * Attach the interface to 802.11 radiotap. 742 */ 743 static void 744 iwn_radiotap_attach(struct iwn_softc *sc) 745 { 746 struct ifnet *ifp = sc->sc_ic.ic_ifp; 747 748 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 749 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 750 &sc->sc_drvbpf); 751 752 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 753 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 754 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 755 756 sc->sc_txtap_len = sizeof sc->sc_txtapu; 757 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 758 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 759 } 760 761 static int 762 iwn_detach(device_t self, int flags __unused) 763 { 764 struct iwn_softc *sc = device_private(self); 765 struct ifnet *ifp = sc->sc_ic.ic_ifp; 766 int qid; 767 768 callout_stop(&sc->calib_to); 769 770 /* Uninstall interrupt handler. */ 771 if (sc->sc_ih != NULL) 772 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 773 774 /* Free DMA resources. */ 775 iwn_free_rx_ring(sc, &sc->rxq); 776 for (qid = 0; qid < sc->ntxqs; qid++) 777 iwn_free_tx_ring(sc, &sc->txq[qid]); 778 #ifdef IWN_USE_RBUF 779 iwn_free_rpool(sc); 780 #endif 781 iwn_free_sched(sc); 782 iwn_free_kw(sc); 783 if (sc->ict != NULL) 784 iwn_free_ict(sc); 785 iwn_free_fwmem(sc); 786 787 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 788 789 ieee80211_ifdetach(&sc->sc_ic); 790 if_detach(ifp); 791 792 return 0; 793 } 794 795 #if 0 796 /* 797 * XXX Investigate if clearing the PCI retry timeout could eliminate 798 * the repeated scan calls. Also the calls to if_init and if_start 799 * are similar to the effect of adding the call to ifioctl_common . 800 */ 801 static void 802 iwn_power(int why, void *arg) 803 { 804 struct iwn_softc *sc = arg; 805 struct ifnet *ifp; 806 pcireg_t reg; 807 int s; 808 809 if (why != PWR_RESUME) 810 return; 811 812 /* Clear device-specific "PCI retry timeout" register (41h). */ 813 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 814 if (reg & 0xff00) 815 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 816 817 s = splnet(); 818 ifp = &sc->sc_ic.ic_if; 819 if (ifp->if_flags & IFF_UP) { 820 ifp->if_init(ifp); 821 if (ifp->if_flags & IFF_RUNNING) 822 ifp->if_start(ifp); 823 } 824 splx(s); 825 } 826 #endif 827 828 static bool 829 iwn_resume(device_t dv, const pmf_qual_t *qual) 830 { 831 return true; 832 } 833 834 static int 835 iwn_nic_lock(struct iwn_softc *sc) 836 { 837 int ntries; 838 839 /* Request exclusive access to NIC. */ 840 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 841 842 /* Spin until we actually get the lock. */ 843 for (ntries = 0; ntries < 1000; ntries++) { 844 if ((IWN_READ(sc, IWN_GP_CNTRL) & 845 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 846 IWN_GP_CNTRL_MAC_ACCESS_ENA) 847 return 0; 848 DELAY(10); 849 } 850 return ETIMEDOUT; 851 } 852 853 static __inline void 854 iwn_nic_unlock(struct iwn_softc *sc) 855 { 856 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 857 } 858 859 static __inline uint32_t 860 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 861 { 862 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 863 IWN_BARRIER_READ_WRITE(sc); 864 return IWN_READ(sc, IWN_PRPH_RDATA); 865 } 866 867 static __inline void 868 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 869 { 870 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 871 IWN_BARRIER_WRITE(sc); 872 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 873 } 874 875 static __inline void 876 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 877 { 878 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 879 } 880 881 static __inline void 882 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 883 { 884 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 885 } 886 887 static __inline void 888 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 889 const uint32_t *data, int count) 890 { 891 for (; count > 0; count--, data++, addr += 4) 892 iwn_prph_write(sc, addr, *data); 893 } 894 895 static __inline uint32_t 896 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 897 { 898 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 899 IWN_BARRIER_READ_WRITE(sc); 900 return IWN_READ(sc, IWN_MEM_RDATA); 901 } 902 903 static __inline void 904 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 905 { 906 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 907 IWN_BARRIER_WRITE(sc); 908 IWN_WRITE(sc, IWN_MEM_WDATA, data); 909 } 910 911 static __inline void 912 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 913 { 914 uint32_t tmp; 915 916 tmp = iwn_mem_read(sc, addr & ~3); 917 if (addr & 3) 918 tmp = (tmp & 0x0000ffff) | data << 16; 919 else 920 tmp = (tmp & 0xffff0000) | data; 921 iwn_mem_write(sc, addr & ~3, tmp); 922 } 923 924 static __inline void 925 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 926 int count) 927 { 928 for (; count > 0; count--, addr += 4) 929 *data++ = iwn_mem_read(sc, addr); 930 } 931 932 static __inline void 933 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 934 int count) 935 { 936 for (; count > 0; count--, addr += 4) 937 iwn_mem_write(sc, addr, val); 938 } 939 940 static int 941 iwn_eeprom_lock(struct iwn_softc *sc) 942 { 943 int i, ntries; 944 945 for (i = 0; i < 100; i++) { 946 /* Request exclusive access to EEPROM. */ 947 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 948 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 949 950 /* Spin until we actually get the lock. */ 951 for (ntries = 0; ntries < 100; ntries++) { 952 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 953 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 954 return 0; 955 DELAY(10); 956 } 957 } 958 return ETIMEDOUT; 959 } 960 961 static __inline void 962 iwn_eeprom_unlock(struct iwn_softc *sc) 963 { 964 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 965 } 966 967 /* 968 * Initialize access by host to One Time Programmable ROM. 969 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 970 */ 971 static int 972 iwn_init_otprom(struct iwn_softc *sc) 973 { 974 uint16_t prev = 0, base, next; 975 int count, error; 976 977 /* Wait for clock stabilization before accessing prph. */ 978 if ((error = iwn_clock_wait(sc)) != 0) 979 return error; 980 981 if ((error = iwn_nic_lock(sc)) != 0) 982 return error; 983 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 984 DELAY(5); 985 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 986 iwn_nic_unlock(sc); 987 988 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 989 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 990 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 991 IWN_RESET_LINK_PWR_MGMT_DIS); 992 } 993 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 994 /* Clear ECC status. */ 995 IWN_SETBITS(sc, IWN_OTP_GP, 996 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 997 998 /* 999 * Find the block before last block (contains the EEPROM image) 1000 * for HW without OTP shadow RAM. 1001 */ 1002 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1003 /* Switch to absolute addressing mode. */ 1004 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1005 base = 0; 1006 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1007 error = iwn_read_prom_data(sc, base, &next, 2); 1008 if (error != 0) 1009 return error; 1010 if (next == 0) /* End of linked-list. */ 1011 break; 1012 prev = base; 1013 base = le16toh(next); 1014 } 1015 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1016 return EIO; 1017 /* Skip "next" word. */ 1018 sc->prom_base = prev + 1; 1019 } 1020 return 0; 1021 } 1022 1023 static int 1024 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1025 { 1026 uint8_t *out = data; 1027 uint32_t val, tmp; 1028 int ntries; 1029 1030 addr += sc->prom_base; 1031 for (; count > 0; count -= 2, addr++) { 1032 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1033 for (ntries = 0; ntries < 10; ntries++) { 1034 val = IWN_READ(sc, IWN_EEPROM); 1035 if (val & IWN_EEPROM_READ_VALID) 1036 break; 1037 DELAY(5); 1038 } 1039 if (ntries == 10) { 1040 aprint_error_dev(sc->sc_dev, 1041 "timeout reading ROM at 0x%x\n", addr); 1042 return ETIMEDOUT; 1043 } 1044 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1045 /* OTPROM, check for ECC errors. */ 1046 tmp = IWN_READ(sc, IWN_OTP_GP); 1047 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1048 aprint_error_dev(sc->sc_dev, 1049 "OTPROM ECC error at 0x%x\n", addr); 1050 return EIO; 1051 } 1052 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1053 /* Correctable ECC error, clear bit. */ 1054 IWN_SETBITS(sc, IWN_OTP_GP, 1055 IWN_OTP_GP_ECC_CORR_STTS); 1056 } 1057 } 1058 *out++ = val >> 16; 1059 if (count > 1) 1060 *out++ = val >> 24; 1061 } 1062 return 0; 1063 } 1064 1065 static int 1066 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1067 bus_size_t size, bus_size_t alignment) 1068 { 1069 int nsegs, error; 1070 1071 dma->tag = tag; 1072 dma->size = size; 1073 1074 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1075 &dma->map); 1076 if (error != 0) 1077 goto fail; 1078 1079 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1080 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1081 if (error != 0) 1082 goto fail; 1083 1084 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1085 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1086 if (error != 0) 1087 goto fail; 1088 1089 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1090 BUS_DMA_NOWAIT); 1091 if (error != 0) 1092 goto fail; 1093 1094 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1095 memset(dma->vaddr, 0, size); 1096 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1097 1098 dma->paddr = dma->map->dm_segs[0].ds_addr; 1099 if (kvap != NULL) 1100 *kvap = dma->vaddr; 1101 1102 return 0; 1103 1104 fail: iwn_dma_contig_free(dma); 1105 return error; 1106 } 1107 1108 static void 1109 iwn_dma_contig_free(struct iwn_dma_info *dma) 1110 { 1111 if (dma->map != NULL) { 1112 if (dma->vaddr != NULL) { 1113 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1114 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1115 bus_dmamap_unload(dma->tag, dma->map); 1116 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1117 bus_dmamem_free(dma->tag, &dma->seg, 1); 1118 dma->vaddr = NULL; 1119 } 1120 bus_dmamap_destroy(dma->tag, dma->map); 1121 dma->map = NULL; 1122 } 1123 } 1124 1125 static int 1126 iwn_alloc_sched(struct iwn_softc *sc) 1127 { 1128 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1129 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1130 (void **)&sc->sched, sc->schedsz, 1024); 1131 } 1132 1133 static void 1134 iwn_free_sched(struct iwn_softc *sc) 1135 { 1136 iwn_dma_contig_free(&sc->sched_dma); 1137 } 1138 1139 static int 1140 iwn_alloc_kw(struct iwn_softc *sc) 1141 { 1142 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1143 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1144 4096); 1145 } 1146 1147 static void 1148 iwn_free_kw(struct iwn_softc *sc) 1149 { 1150 iwn_dma_contig_free(&sc->kw_dma); 1151 } 1152 1153 static int 1154 iwn_alloc_ict(struct iwn_softc *sc) 1155 { 1156 /* ICT table must be aligned on a 4KB boundary. */ 1157 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1158 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1159 } 1160 1161 static void 1162 iwn_free_ict(struct iwn_softc *sc) 1163 { 1164 iwn_dma_contig_free(&sc->ict_dma); 1165 } 1166 1167 static int 1168 iwn_alloc_fwmem(struct iwn_softc *sc) 1169 { 1170 /* Must be aligned on a 16-byte boundary. */ 1171 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1172 sc->fwsz, 16); 1173 } 1174 1175 static void 1176 iwn_free_fwmem(struct iwn_softc *sc) 1177 { 1178 iwn_dma_contig_free(&sc->fw_dma); 1179 } 1180 1181 static int 1182 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1183 { 1184 bus_size_t size; 1185 int i, error; 1186 1187 ring->cur = 0; 1188 1189 /* Allocate RX descriptors (256-byte aligned). */ 1190 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1191 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1192 (void **)&ring->desc, size, 256); 1193 if (error != 0) { 1194 aprint_error_dev(sc->sc_dev, 1195 "could not allocate RX ring DMA memory\n"); 1196 goto fail; 1197 } 1198 1199 /* Allocate RX status area (16-byte aligned). */ 1200 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1201 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1202 if (error != 0) { 1203 aprint_error_dev(sc->sc_dev, 1204 "could not allocate RX status DMA memory\n"); 1205 goto fail; 1206 } 1207 1208 /* 1209 * Allocate and map RX buffers. 1210 */ 1211 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1212 struct iwn_rx_data *data = &ring->data[i]; 1213 1214 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1215 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1216 &data->map); 1217 if (error != 0) { 1218 aprint_error_dev(sc->sc_dev, 1219 "could not create RX buf DMA map\n"); 1220 goto fail; 1221 } 1222 1223 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1224 if (data->m == NULL) { 1225 aprint_error_dev(sc->sc_dev, 1226 "could not allocate RX mbuf\n"); 1227 error = ENOBUFS; 1228 goto fail; 1229 } 1230 1231 error = bus_dmamap_load(sc->sc_dmat, data->map, 1232 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1233 BUS_DMA_NOWAIT | BUS_DMA_READ); 1234 if (error != 0) { 1235 aprint_error_dev(sc->sc_dev, 1236 "can't not map mbuf (error %d)\n", error); 1237 goto fail; 1238 } 1239 1240 /* Set physical address of RX buffer (256-byte aligned). */ 1241 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1242 } 1243 1244 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1245 BUS_DMASYNC_PREWRITE); 1246 1247 return 0; 1248 1249 fail: iwn_free_rx_ring(sc, ring); 1250 return error; 1251 } 1252 1253 static void 1254 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1255 { 1256 int ntries; 1257 1258 if (iwn_nic_lock(sc) == 0) { 1259 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1260 for (ntries = 0; ntries < 1000; ntries++) { 1261 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1262 IWN_FH_RX_STATUS_IDLE) 1263 break; 1264 DELAY(10); 1265 } 1266 iwn_nic_unlock(sc); 1267 } 1268 ring->cur = 0; 1269 sc->last_rx_valid = 0; 1270 } 1271 1272 static void 1273 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1274 { 1275 int i; 1276 1277 iwn_dma_contig_free(&ring->desc_dma); 1278 iwn_dma_contig_free(&ring->stat_dma); 1279 1280 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1281 struct iwn_rx_data *data = &ring->data[i]; 1282 1283 if (data->m != NULL) { 1284 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1285 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1286 bus_dmamap_unload(sc->sc_dmat, data->map); 1287 m_freem(data->m); 1288 } 1289 if (data->map != NULL) 1290 bus_dmamap_destroy(sc->sc_dmat, data->map); 1291 } 1292 } 1293 1294 static int 1295 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1296 { 1297 bus_addr_t paddr; 1298 bus_size_t size; 1299 int i, error; 1300 1301 ring->qid = qid; 1302 ring->queued = 0; 1303 ring->cur = 0; 1304 1305 /* Allocate TX descriptors (256-byte aligned). */ 1306 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1307 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1308 (void **)&ring->desc, size, 256); 1309 if (error != 0) { 1310 aprint_error_dev(sc->sc_dev, 1311 "could not allocate TX ring DMA memory\n"); 1312 goto fail; 1313 } 1314 /* 1315 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1316 * to allocate commands space for other rings. 1317 * XXX Do we really need to allocate descriptors for other rings? 1318 */ 1319 if (qid > 4) 1320 return 0; 1321 1322 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1323 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1324 (void **)&ring->cmd, size, 4); 1325 if (error != 0) { 1326 aprint_error_dev(sc->sc_dev, 1327 "could not allocate TX cmd DMA memory\n"); 1328 goto fail; 1329 } 1330 1331 paddr = ring->cmd_dma.paddr; 1332 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1333 struct iwn_tx_data *data = &ring->data[i]; 1334 1335 data->cmd_paddr = paddr; 1336 data->scratch_paddr = paddr + 12; 1337 paddr += sizeof (struct iwn_tx_cmd); 1338 1339 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1340 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1341 &data->map); 1342 if (error != 0) { 1343 aprint_error_dev(sc->sc_dev, 1344 "could not create TX buf DMA map\n"); 1345 goto fail; 1346 } 1347 } 1348 return 0; 1349 1350 fail: iwn_free_tx_ring(sc, ring); 1351 return error; 1352 } 1353 1354 static void 1355 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1356 { 1357 int i; 1358 1359 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1360 struct iwn_tx_data *data = &ring->data[i]; 1361 1362 if (data->m != NULL) { 1363 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1364 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1365 bus_dmamap_unload(sc->sc_dmat, data->map); 1366 m_freem(data->m); 1367 data->m = NULL; 1368 } 1369 } 1370 /* Clear TX descriptors. */ 1371 memset(ring->desc, 0, ring->desc_dma.size); 1372 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1373 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1374 sc->qfullmsk &= ~(1 << ring->qid); 1375 ring->queued = 0; 1376 ring->cur = 0; 1377 } 1378 1379 static void 1380 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1381 { 1382 int i; 1383 1384 iwn_dma_contig_free(&ring->desc_dma); 1385 iwn_dma_contig_free(&ring->cmd_dma); 1386 1387 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1388 struct iwn_tx_data *data = &ring->data[i]; 1389 1390 if (data->m != NULL) { 1391 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1392 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1393 bus_dmamap_unload(sc->sc_dmat, data->map); 1394 m_freem(data->m); 1395 } 1396 if (data->map != NULL) 1397 bus_dmamap_destroy(sc->sc_dmat, data->map); 1398 } 1399 } 1400 1401 static void 1402 iwn5000_ict_reset(struct iwn_softc *sc) 1403 { 1404 /* Disable interrupts. */ 1405 IWN_WRITE(sc, IWN_INT_MASK, 0); 1406 1407 /* Reset ICT table. */ 1408 memset(sc->ict, 0, IWN_ICT_SIZE); 1409 sc->ict_cur = 0; 1410 1411 /* Set physical address of ICT table (4KB aligned). */ 1412 DPRINTF(("enabling ICT\n")); 1413 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1414 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1415 1416 /* Enable periodic RX interrupt. */ 1417 sc->int_mask |= IWN_INT_RX_PERIODIC; 1418 /* Switch to ICT interrupt mode in driver. */ 1419 sc->sc_flags |= IWN_FLAG_USE_ICT; 1420 1421 /* Re-enable interrupts. */ 1422 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1423 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1424 } 1425 1426 static int 1427 iwn_read_eeprom(struct iwn_softc *sc) 1428 { 1429 struct iwn_ops *ops = &sc->ops; 1430 struct ieee80211com *ic = &sc->sc_ic; 1431 uint16_t val; 1432 int error; 1433 1434 /* Check whether adapter has an EEPROM or an OTPROM. */ 1435 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1436 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1437 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1438 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1439 "OTPROM" : "EEPROM")); 1440 1441 /* Adapter has to be powered on for EEPROM access to work. */ 1442 if ((error = iwn_apm_init(sc)) != 0) { 1443 aprint_error_dev(sc->sc_dev, 1444 "could not power ON adapter\n"); 1445 return error; 1446 } 1447 1448 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1449 aprint_error_dev(sc->sc_dev, 1450 "bad ROM signature\n"); 1451 return EIO; 1452 } 1453 if ((error = iwn_eeprom_lock(sc)) != 0) { 1454 aprint_error_dev(sc->sc_dev, 1455 "could not lock ROM (error=%d)\n", error); 1456 return error; 1457 } 1458 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1459 if ((error = iwn_init_otprom(sc)) != 0) { 1460 aprint_error_dev(sc->sc_dev, 1461 "could not initialize OTPROM\n"); 1462 return error; 1463 } 1464 } 1465 1466 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1467 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1468 /* Check if HT support is bonded out. */ 1469 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1470 sc->sc_flags |= IWN_FLAG_HAS_11N; 1471 1472 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1473 sc->rfcfg = le16toh(val); 1474 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1475 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1476 if (sc->txchainmask == 0) 1477 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1478 if (sc->rxchainmask == 0) 1479 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1480 1481 /* Read MAC address. */ 1482 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1483 1484 /* Read adapter-specific information from EEPROM. */ 1485 ops->read_eeprom(sc); 1486 1487 iwn_apm_stop(sc); /* Power OFF adapter. */ 1488 1489 iwn_eeprom_unlock(sc); 1490 return 0; 1491 } 1492 1493 static void 1494 iwn4965_read_eeprom(struct iwn_softc *sc) 1495 { 1496 uint32_t addr; 1497 uint16_t val; 1498 int i; 1499 1500 /* Read regulatory domain (4 ASCII characters). */ 1501 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1502 1503 /* Read the list of authorized channels (20MHz ones only). */ 1504 for (i = 0; i < 5; i++) { 1505 addr = iwn4965_regulatory_bands[i]; 1506 iwn_read_eeprom_channels(sc, i, addr); 1507 } 1508 1509 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1510 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1511 sc->maxpwr2GHz = val & 0xff; 1512 sc->maxpwr5GHz = val >> 8; 1513 /* Check that EEPROM values are within valid range. */ 1514 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1515 sc->maxpwr5GHz = 38; 1516 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1517 sc->maxpwr2GHz = 38; 1518 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1519 1520 /* Read samples for each TX power group. */ 1521 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1522 sizeof sc->bands); 1523 1524 /* Read voltage at which samples were taken. */ 1525 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1526 sc->eeprom_voltage = (int16_t)le16toh(val); 1527 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1528 1529 #ifdef IWN_DEBUG 1530 /* Print samples. */ 1531 if (iwn_debug > 0) { 1532 for (i = 0; i < IWN_NBANDS; i++) 1533 iwn4965_print_power_group(sc, i); 1534 } 1535 #endif 1536 } 1537 1538 #ifdef IWN_DEBUG 1539 static void 1540 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1541 { 1542 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1543 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1544 int j, c; 1545 1546 aprint_normal("===band %d===\n", i); 1547 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1548 aprint_normal("chan1 num=%d\n", chans[0].num); 1549 for (c = 0; c < 2; c++) { 1550 for (j = 0; j < IWN_NSAMPLES; j++) { 1551 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1552 "power=%d pa_det=%d\n", c, j, 1553 chans[0].samples[c][j].temp, 1554 chans[0].samples[c][j].gain, 1555 chans[0].samples[c][j].power, 1556 chans[0].samples[c][j].pa_det); 1557 } 1558 } 1559 aprint_normal("chan2 num=%d\n", chans[1].num); 1560 for (c = 0; c < 2; c++) { 1561 for (j = 0; j < IWN_NSAMPLES; j++) { 1562 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1563 "power=%d pa_det=%d\n", c, j, 1564 chans[1].samples[c][j].temp, 1565 chans[1].samples[c][j].gain, 1566 chans[1].samples[c][j].power, 1567 chans[1].samples[c][j].pa_det); 1568 } 1569 } 1570 } 1571 #endif 1572 1573 static void 1574 iwn5000_read_eeprom(struct iwn_softc *sc) 1575 { 1576 struct iwn5000_eeprom_calib_hdr hdr; 1577 int32_t volt; 1578 uint32_t base, addr; 1579 uint16_t val; 1580 int i; 1581 1582 /* Read regulatory domain (4 ASCII characters). */ 1583 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1584 base = le16toh(val); 1585 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1586 sc->eeprom_domain, 4); 1587 1588 /* Read the list of authorized channels (20MHz ones only). */ 1589 for (i = 0; i < 5; i++) { 1590 addr = base + iwn5000_regulatory_bands[i]; 1591 iwn_read_eeprom_channels(sc, i, addr); 1592 } 1593 1594 /* Read enhanced TX power information for 6000 Series. */ 1595 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1596 iwn_read_eeprom_enhinfo(sc); 1597 1598 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1599 base = le16toh(val); 1600 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1601 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1602 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1603 sc->calib_ver = hdr.version; 1604 1605 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1606 /* Compute temperature offset. */ 1607 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1608 sc->eeprom_temp = le16toh(val); 1609 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1610 volt = le16toh(val); 1611 sc->temp_off = sc->eeprom_temp - (volt / -5); 1612 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1613 sc->eeprom_temp, volt, sc->temp_off)); 1614 } else { 1615 /* Read crystal calibration. */ 1616 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1617 &sc->eeprom_crystal, sizeof (uint32_t)); 1618 DPRINTF(("crystal calibration 0x%08x\n", 1619 le32toh(sc->eeprom_crystal))); 1620 } 1621 } 1622 1623 static void 1624 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1625 { 1626 struct ieee80211com *ic = &sc->sc_ic; 1627 const struct iwn_chan_band *band = &iwn_bands[n]; 1628 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1629 uint8_t chan; 1630 int i; 1631 1632 iwn_read_prom_data(sc, addr, channels, 1633 band->nchan * sizeof (struct iwn_eeprom_chan)); 1634 1635 for (i = 0; i < band->nchan; i++) { 1636 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1637 continue; 1638 1639 chan = band->chan[i]; 1640 1641 if (n == 0) { /* 2GHz band */ 1642 ic->ic_channels[chan].ic_freq = 1643 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1644 ic->ic_channels[chan].ic_flags = 1645 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1646 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1647 1648 } else { /* 5GHz band */ 1649 /* 1650 * Some adapters support channels 7, 8, 11 and 12 1651 * both in the 2GHz and 4.9GHz bands. 1652 * Because of limitations in our net80211 layer, 1653 * we don't support them in the 4.9GHz band. 1654 */ 1655 if (chan <= 14) 1656 continue; 1657 1658 ic->ic_channels[chan].ic_freq = 1659 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1660 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1661 /* We have at least one valid 5GHz channel. */ 1662 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1663 } 1664 1665 /* Is active scan allowed on this channel? */ 1666 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1667 ic->ic_channels[chan].ic_flags |= 1668 IEEE80211_CHAN_PASSIVE; 1669 } 1670 1671 /* Save maximum allowed TX power for this channel. */ 1672 sc->maxpwr[chan] = channels[i].maxpwr; 1673 1674 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1675 chan, channels[i].flags, sc->maxpwr[chan])); 1676 } 1677 } 1678 1679 static void 1680 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1681 { 1682 struct iwn_eeprom_enhinfo enhinfo[35]; 1683 uint16_t val, base; 1684 int8_t maxpwr; 1685 int i; 1686 1687 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1688 base = le16toh(val); 1689 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1690 enhinfo, sizeof enhinfo); 1691 1692 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1693 for (i = 0; i < __arraycount(enhinfo); i++) { 1694 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1695 continue; /* Skip invalid entries. */ 1696 1697 maxpwr = 0; 1698 if (sc->txchainmask & IWN_ANT_A) 1699 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1700 if (sc->txchainmask & IWN_ANT_B) 1701 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1702 if (sc->txchainmask & IWN_ANT_C) 1703 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1704 if (sc->ntxchains == 2) 1705 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1706 else if (sc->ntxchains == 3) 1707 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1708 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1709 1710 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1711 sc->enh_maxpwr[i] = maxpwr; 1712 } 1713 } 1714 1715 static struct ieee80211_node * 1716 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1717 { 1718 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1719 } 1720 1721 static void 1722 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1723 { 1724 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1725 struct iwn_node *wn = (void *)ni; 1726 uint8_t rate; 1727 int ridx, i; 1728 1729 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1730 /* Start at lowest available bit-rate, AMRR will raise. */ 1731 ni->ni_txrate = 0; 1732 1733 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1734 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1735 /* Map 802.11 rate to HW rate index. */ 1736 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1737 if (iwn_rates[ridx].rate == rate) 1738 break; 1739 wn->ridx[i] = ridx; 1740 } 1741 } 1742 1743 static int 1744 iwn_media_change(struct ifnet *ifp) 1745 { 1746 struct iwn_softc *sc = ifp->if_softc; 1747 struct ieee80211com *ic = &sc->sc_ic; 1748 uint8_t rate, ridx; 1749 int error; 1750 1751 error = ieee80211_media_change(ifp); 1752 if (error != ENETRESET) 1753 return error; 1754 1755 if (ic->ic_fixed_rate != -1) { 1756 rate = ic->ic_sup_rates[ic->ic_curmode]. 1757 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1758 /* Map 802.11 rate to HW rate index. */ 1759 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1760 if (iwn_rates[ridx].rate == rate) 1761 break; 1762 sc->fixed_ridx = ridx; 1763 } 1764 1765 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1766 (IFF_UP | IFF_RUNNING)) { 1767 iwn_stop(ifp, 0); 1768 error = iwn_init(ifp); 1769 } 1770 return error; 1771 } 1772 1773 static int 1774 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1775 { 1776 struct ifnet *ifp = ic->ic_ifp; 1777 struct iwn_softc *sc = ifp->if_softc; 1778 int error; 1779 1780 callout_stop(&sc->calib_to); 1781 1782 switch (nstate) { 1783 case IEEE80211_S_SCAN: 1784 /* XXX Do not abort a running scan. */ 1785 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1786 if (ic->ic_state != nstate) 1787 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1788 "while scanning(%d) ignored\n", nstate, 1789 ic->ic_state); 1790 break; 1791 } 1792 1793 /* XXX Not sure if call and flags are needed. */ 1794 ieee80211_node_table_reset(&ic->ic_scan); 1795 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1796 sc->sc_flags |= IWN_FLAG_SCANNING; 1797 1798 /* Make the link LED blink while we're scanning. */ 1799 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1800 1801 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1802 aprint_error_dev(sc->sc_dev, 1803 "could not initiate scan\n"); 1804 return error; 1805 } 1806 ic->ic_state = nstate; 1807 return 0; 1808 1809 case IEEE80211_S_ASSOC: 1810 if (ic->ic_state != IEEE80211_S_RUN) 1811 break; 1812 /* FALLTHROUGH */ 1813 case IEEE80211_S_AUTH: 1814 /* Reset state to handle reassociations correctly. */ 1815 sc->rxon.associd = 0; 1816 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1817 sc->calib.state = IWN_CALIB_STATE_INIT; 1818 1819 if ((error = iwn_auth(sc)) != 0) { 1820 aprint_error_dev(sc->sc_dev, 1821 "could not move to auth state\n"); 1822 return error; 1823 } 1824 break; 1825 1826 case IEEE80211_S_RUN: 1827 if ((error = iwn_run(sc)) != 0) { 1828 aprint_error_dev(sc->sc_dev, 1829 "could not move to run state\n"); 1830 return error; 1831 } 1832 break; 1833 1834 case IEEE80211_S_INIT: 1835 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1836 sc->calib.state = IWN_CALIB_STATE_INIT; 1837 break; 1838 } 1839 1840 return sc->sc_newstate(ic, nstate, arg); 1841 } 1842 1843 static void 1844 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1845 { 1846 struct iwn_softc *sc = arg; 1847 struct iwn_node *wn = (struct iwn_node *)ni; 1848 1849 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1850 } 1851 1852 static void 1853 iwn_calib_timeout(void *arg) 1854 { 1855 struct iwn_softc *sc = arg; 1856 struct ieee80211com *ic = &sc->sc_ic; 1857 int s; 1858 1859 s = splnet(); 1860 if (ic->ic_fixed_rate == -1) { 1861 if (ic->ic_opmode == IEEE80211_M_STA) 1862 iwn_iter_func(sc, ic->ic_bss); 1863 else 1864 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1865 } 1866 /* Force automatic TX power calibration every 60 secs. */ 1867 if (++sc->calib_cnt >= 120) { 1868 uint32_t flags = 0; 1869 1870 DPRINTF(("sending request for statistics\n")); 1871 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1872 sizeof flags, 1); 1873 sc->calib_cnt = 0; 1874 } 1875 splx(s); 1876 1877 /* Automatic rate control triggered every 500ms. */ 1878 callout_schedule(&sc->calib_to, hz/2); 1879 } 1880 1881 /* 1882 * Process an RX_PHY firmware notification. This is usually immediately 1883 * followed by an MPDU_RX_DONE notification. 1884 */ 1885 static void 1886 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1887 struct iwn_rx_data *data) 1888 { 1889 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1890 1891 DPRINTFN(2, ("received PHY stats\n")); 1892 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1893 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1894 1895 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1896 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1897 sc->last_rx_valid = 1; 1898 } 1899 1900 /* 1901 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1902 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1903 */ 1904 static void 1905 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1906 struct iwn_rx_data *data) 1907 { 1908 struct iwn_ops *ops = &sc->ops; 1909 struct ieee80211com *ic = &sc->sc_ic; 1910 struct ifnet *ifp = ic->ic_ifp; 1911 struct iwn_rx_ring *ring = &sc->rxq; 1912 struct ieee80211_frame *wh; 1913 struct ieee80211_node *ni; 1914 struct mbuf *m, *m1; 1915 struct iwn_rx_stat *stat; 1916 char *head; 1917 uint32_t flags; 1918 int error, len, rssi; 1919 1920 if (desc->type == IWN_MPDU_RX_DONE) { 1921 /* Check for prior RX_PHY notification. */ 1922 if (!sc->last_rx_valid) { 1923 DPRINTF(("missing RX_PHY\n")); 1924 return; 1925 } 1926 sc->last_rx_valid = 0; 1927 stat = &sc->last_rx_stat; 1928 } else 1929 stat = (struct iwn_rx_stat *)(desc + 1); 1930 1931 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1932 BUS_DMASYNC_POSTREAD); 1933 1934 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1935 aprint_error_dev(sc->sc_dev, 1936 "invalid RX statistic header\n"); 1937 return; 1938 } 1939 if (desc->type == IWN_MPDU_RX_DONE) { 1940 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1941 head = (char *)(mpdu + 1); 1942 len = le16toh(mpdu->len); 1943 } else { 1944 head = (char *)(stat + 1) + stat->cfg_phy_len; 1945 len = le16toh(stat->len); 1946 } 1947 1948 flags = le32toh(*(uint32_t *)(head + len)); 1949 1950 /* Discard frames with a bad FCS early. */ 1951 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 1952 DPRINTFN(2, ("RX flags error %x\n", flags)); 1953 ifp->if_ierrors++; 1954 return; 1955 } 1956 /* Discard frames that are too short. */ 1957 if (len < sizeof (*wh)) { 1958 DPRINTF(("frame too short: %d\n", len)); 1959 ic->ic_stats.is_rx_tooshort++; 1960 ifp->if_ierrors++; 1961 return; 1962 } 1963 1964 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1965 if (m1 == NULL) { 1966 ic->ic_stats.is_rx_nobuf++; 1967 ifp->if_ierrors++; 1968 return; 1969 } 1970 bus_dmamap_unload(sc->sc_dmat, data->map); 1971 1972 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 1973 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1974 if (error != 0) { 1975 m_freem(m1); 1976 1977 /* Try to reload the old mbuf. */ 1978 error = bus_dmamap_load(sc->sc_dmat, data->map, 1979 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1980 BUS_DMA_NOWAIT | BUS_DMA_READ); 1981 if (error != 0) { 1982 panic("%s: could not load old RX mbuf", 1983 device_xname(sc->sc_dev)); 1984 } 1985 /* Physical address may have changed. */ 1986 ring->desc[ring->cur] = 1987 htole32(data->map->dm_segs[0].ds_addr >> 8); 1988 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1989 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1990 BUS_DMASYNC_PREWRITE); 1991 ifp->if_ierrors++; 1992 return; 1993 } 1994 1995 m = data->m; 1996 data->m = m1; 1997 /* Update RX descriptor. */ 1998 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1999 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2000 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2001 BUS_DMASYNC_PREWRITE); 2002 2003 /* Finalize mbuf. */ 2004 m->m_pkthdr.rcvif = ifp; 2005 m->m_data = head; 2006 m->m_pkthdr.len = m->m_len = len; 2007 2008 /* Grab a reference to the source node. */ 2009 wh = mtod(m, struct ieee80211_frame *); 2010 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2011 2012 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2013 /* NetBSD does decryption in ieee80211_input. */ 2014 2015 rssi = ops->get_rssi(stat); 2016 2017 /* XXX Added for NetBSD: scans never stop without it */ 2018 if (ic->ic_state == IEEE80211_S_SCAN) 2019 iwn_fix_channel(ic, m); 2020 2021 if (sc->sc_drvbpf != NULL) { 2022 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2023 2024 tap->wr_flags = 0; 2025 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2026 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2027 tap->wr_chan_freq = 2028 htole16(ic->ic_channels[stat->chan].ic_freq); 2029 tap->wr_chan_flags = 2030 htole16(ic->ic_channels[stat->chan].ic_flags); 2031 tap->wr_dbm_antsignal = (int8_t)rssi; 2032 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2033 tap->wr_tsft = stat->tstamp; 2034 switch (stat->rate) { 2035 /* CCK rates. */ 2036 case 10: tap->wr_rate = 2; break; 2037 case 20: tap->wr_rate = 4; break; 2038 case 55: tap->wr_rate = 11; break; 2039 case 110: tap->wr_rate = 22; break; 2040 /* OFDM rates. */ 2041 case 0xd: tap->wr_rate = 12; break; 2042 case 0xf: tap->wr_rate = 18; break; 2043 case 0x5: tap->wr_rate = 24; break; 2044 case 0x7: tap->wr_rate = 36; break; 2045 case 0x9: tap->wr_rate = 48; break; 2046 case 0xb: tap->wr_rate = 72; break; 2047 case 0x1: tap->wr_rate = 96; break; 2048 case 0x3: tap->wr_rate = 108; break; 2049 /* Unknown rate: should not happen. */ 2050 default: tap->wr_rate = 0; 2051 } 2052 2053 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2054 } 2055 2056 /* Send the frame to the 802.11 layer. */ 2057 ieee80211_input(ic, m, ni, rssi, 0); 2058 2059 /* Node is no longer needed. */ 2060 ieee80211_free_node(ni); 2061 } 2062 2063 #ifndef IEEE80211_NO_HT 2064 /* Process an incoming Compressed BlockAck. */ 2065 static void 2066 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2067 struct iwn_rx_data *data) 2068 { 2069 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2070 struct iwn_tx_ring *txq; 2071 2072 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2073 BUS_DMASYNC_POSTREAD); 2074 2075 txq = &sc->txq[le16toh(ba->qid)]; 2076 /* XXX TBD */ 2077 } 2078 #endif 2079 2080 /* 2081 * Process a CALIBRATION_RESULT notification sent by the initialization 2082 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2083 */ 2084 static void 2085 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2086 struct iwn_rx_data *data) 2087 { 2088 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2089 int len, idx = -1; 2090 2091 /* Runtime firmware should not send such a notification. */ 2092 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2093 return; 2094 2095 len = (le32toh(desc->len) & 0x3fff) - 4; 2096 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2097 BUS_DMASYNC_POSTREAD); 2098 2099 switch (calib->code) { 2100 case IWN5000_PHY_CALIB_DC: 2101 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 2102 idx = 0; 2103 break; 2104 case IWN5000_PHY_CALIB_LO: 2105 idx = 1; 2106 break; 2107 case IWN5000_PHY_CALIB_TX_IQ: 2108 idx = 2; 2109 break; 2110 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2111 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2112 sc->hw_type != IWN_HW_REV_TYPE_5150) 2113 idx = 3; 2114 break; 2115 case IWN5000_PHY_CALIB_BASE_BAND: 2116 idx = 4; 2117 break; 2118 } 2119 if (idx == -1) /* Ignore other results. */ 2120 return; 2121 2122 /* Save calibration result. */ 2123 if (sc->calibcmd[idx].buf != NULL) 2124 free(sc->calibcmd[idx].buf, M_DEVBUF); 2125 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2126 if (sc->calibcmd[idx].buf == NULL) { 2127 DPRINTF(("not enough memory for calibration result %d\n", 2128 calib->code)); 2129 return; 2130 } 2131 DPRINTF(("saving calibration result code=%d len=%d\n", 2132 calib->code, len)); 2133 sc->calibcmd[idx].len = len; 2134 memcpy(sc->calibcmd[idx].buf, calib, len); 2135 } 2136 2137 /* 2138 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2139 * The latter is sent by the firmware after each received beacon. 2140 */ 2141 static void 2142 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2143 struct iwn_rx_data *data) 2144 { 2145 struct iwn_ops *ops = &sc->ops; 2146 struct ieee80211com *ic = &sc->sc_ic; 2147 struct iwn_calib_state *calib = &sc->calib; 2148 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2149 int temp; 2150 2151 /* Ignore statistics received during a scan. */ 2152 if (ic->ic_state != IEEE80211_S_RUN) 2153 return; 2154 2155 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2156 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2157 2158 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2159 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2160 2161 /* Test if temperature has changed. */ 2162 if (stats->general.temp != sc->rawtemp) { 2163 /* Convert "raw" temperature to degC. */ 2164 sc->rawtemp = stats->general.temp; 2165 temp = ops->get_temperature(sc); 2166 DPRINTFN(2, ("temperature=%dC\n", temp)); 2167 2168 /* Update TX power if need be (4965AGN only). */ 2169 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2170 iwn4965_power_calibration(sc, temp); 2171 } 2172 2173 if (desc->type != IWN_BEACON_STATISTICS) 2174 return; /* Reply to a statistics request. */ 2175 2176 sc->noise = iwn_get_noise(&stats->rx.general); 2177 2178 /* Test that RSSI and noise are present in stats report. */ 2179 if (le32toh(stats->rx.general.flags) != 1) { 2180 DPRINTF(("received statistics without RSSI\n")); 2181 return; 2182 } 2183 2184 if (calib->state == IWN_CALIB_STATE_ASSOC) 2185 iwn_collect_noise(sc, &stats->rx.general); 2186 else if (calib->state == IWN_CALIB_STATE_RUN) 2187 iwn_tune_sensitivity(sc, &stats->rx); 2188 } 2189 2190 /* 2191 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2192 * and 5000 adapters have different incompatible TX status formats. 2193 */ 2194 static void 2195 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2196 struct iwn_rx_data *data) 2197 { 2198 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2199 2200 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2201 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2202 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2203 } 2204 2205 static void 2206 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2207 struct iwn_rx_data *data) 2208 { 2209 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2210 2211 #ifdef notyet 2212 /* Reset TX scheduler slot. */ 2213 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2214 #endif 2215 2216 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2217 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2218 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2219 } 2220 2221 /* 2222 * Adapter-independent backend for TX_DONE firmware notifications. 2223 */ 2224 static void 2225 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2226 uint8_t status) 2227 { 2228 struct ieee80211com *ic = &sc->sc_ic; 2229 struct ifnet *ifp = ic->ic_ifp; 2230 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2231 struct iwn_tx_data *data = &ring->data[desc->idx]; 2232 struct iwn_node *wn = (struct iwn_node *)data->ni; 2233 2234 /* Update rate control statistics. */ 2235 wn->amn.amn_txcnt++; 2236 if (ackfailcnt > 0) 2237 wn->amn.amn_retrycnt++; 2238 2239 if (status != 1 && status != 2) 2240 ifp->if_oerrors++; 2241 else 2242 ifp->if_opackets++; 2243 2244 /* Unmap and free mbuf. */ 2245 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2246 BUS_DMASYNC_POSTWRITE); 2247 bus_dmamap_unload(sc->sc_dmat, data->map); 2248 m_freem(data->m); 2249 data->m = NULL; 2250 ieee80211_free_node(data->ni); 2251 data->ni = NULL; 2252 2253 sc->sc_tx_timer = 0; 2254 if (--ring->queued < IWN_TX_RING_LOMARK) { 2255 sc->qfullmsk &= ~(1 << ring->qid); 2256 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2257 ifp->if_flags &= ~IFF_OACTIVE; 2258 (*ifp->if_start)(ifp); 2259 } 2260 } 2261 } 2262 2263 /* 2264 * Process a "command done" firmware notification. This is where we wakeup 2265 * processes waiting for a synchronous command completion. 2266 */ 2267 static void 2268 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2269 { 2270 struct iwn_tx_ring *ring = &sc->txq[4]; 2271 struct iwn_tx_data *data; 2272 2273 if ((desc->qid & 0xf) != 4) 2274 return; /* Not a command ack. */ 2275 2276 data = &ring->data[desc->idx]; 2277 2278 /* If the command was mapped in an mbuf, free it. */ 2279 if (data->m != NULL) { 2280 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2281 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2282 bus_dmamap_unload(sc->sc_dmat, data->map); 2283 m_freem(data->m); 2284 data->m = NULL; 2285 } 2286 wakeup(&ring->desc[desc->idx]); 2287 } 2288 2289 /* 2290 * Process an INT_FH_RX or INT_SW_RX interrupt. 2291 */ 2292 static void 2293 iwn_notif_intr(struct iwn_softc *sc) 2294 { 2295 struct iwn_ops *ops = &sc->ops; 2296 struct ieee80211com *ic = &sc->sc_ic; 2297 struct ifnet *ifp = ic->ic_ifp; 2298 uint16_t hw; 2299 2300 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2301 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2302 2303 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2304 while (sc->rxq.cur != hw) { 2305 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2306 struct iwn_rx_desc *desc; 2307 2308 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2309 BUS_DMASYNC_POSTREAD); 2310 desc = mtod(data->m, struct iwn_rx_desc *); 2311 2312 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2313 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2314 2315 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2316 iwn_cmd_done(sc, desc); 2317 2318 switch (desc->type) { 2319 case IWN_RX_PHY: 2320 iwn_rx_phy(sc, desc, data); 2321 break; 2322 2323 case IWN_RX_DONE: /* 4965AGN only. */ 2324 case IWN_MPDU_RX_DONE: 2325 /* An 802.11 frame has been received. */ 2326 iwn_rx_done(sc, desc, data); 2327 break; 2328 #ifndef IEEE80211_NO_HT 2329 case IWN_RX_COMPRESSED_BA: 2330 /* A Compressed BlockAck has been received. */ 2331 iwn_rx_compressed_ba(sc, desc, data); 2332 break; 2333 #endif 2334 case IWN_TX_DONE: 2335 /* An 802.11 frame has been transmitted. */ 2336 ops->tx_done(sc, desc, data); 2337 break; 2338 2339 case IWN_RX_STATISTICS: 2340 case IWN_BEACON_STATISTICS: 2341 iwn_rx_statistics(sc, desc, data); 2342 break; 2343 2344 case IWN_BEACON_MISSED: 2345 { 2346 struct iwn_beacon_missed *miss = 2347 (struct iwn_beacon_missed *)(desc + 1); 2348 2349 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2350 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2351 /* 2352 * If more than 5 consecutive beacons are missed, 2353 * reinitialize the sensitivity state machine. 2354 */ 2355 DPRINTF(("beacons missed %d/%d\n", 2356 le32toh(miss->consecutive), le32toh(miss->total))); 2357 if (ic->ic_state == IEEE80211_S_RUN && 2358 le32toh(miss->consecutive) > 5) 2359 (void)iwn_init_sensitivity(sc); 2360 break; 2361 } 2362 case IWN_UC_READY: 2363 { 2364 struct iwn_ucode_info *uc = 2365 (struct iwn_ucode_info *)(desc + 1); 2366 2367 /* The microcontroller is ready. */ 2368 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2369 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2370 DPRINTF(("microcode alive notification version=%d.%d " 2371 "subtype=%x alive=%x\n", uc->major, uc->minor, 2372 uc->subtype, le32toh(uc->valid))); 2373 2374 if (le32toh(uc->valid) != 1) { 2375 aprint_error_dev(sc->sc_dev, 2376 "microcontroller initialization " 2377 "failed\n"); 2378 break; 2379 } 2380 if (uc->subtype == IWN_UCODE_INIT) { 2381 /* Save microcontroller report. */ 2382 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2383 } 2384 /* Save the address of the error log in SRAM. */ 2385 sc->errptr = le32toh(uc->errptr); 2386 break; 2387 } 2388 case IWN_STATE_CHANGED: 2389 { 2390 uint32_t *status = (uint32_t *)(desc + 1); 2391 2392 /* Enabled/disabled notification. */ 2393 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2394 sizeof (*status), BUS_DMASYNC_POSTREAD); 2395 DPRINTF(("state changed to %x\n", le32toh(*status))); 2396 2397 if (le32toh(*status) & 1) { 2398 /* The radio button has to be pushed. */ 2399 aprint_error_dev(sc->sc_dev, 2400 "Radio transmitter is off\n"); 2401 /* Turn the interface down. */ 2402 ifp->if_flags &= ~IFF_UP; 2403 iwn_stop(ifp, 1); 2404 return; /* No further processing. */ 2405 } 2406 break; 2407 } 2408 case IWN_START_SCAN: 2409 { 2410 struct iwn_start_scan *scan = 2411 (struct iwn_start_scan *)(desc + 1); 2412 2413 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2414 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2415 DPRINTFN(2, ("scanning channel %d status %x\n", 2416 scan->chan, le32toh(scan->status))); 2417 2418 /* Fix current channel. */ 2419 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2420 break; 2421 } 2422 case IWN_STOP_SCAN: 2423 { 2424 struct iwn_stop_scan *scan = 2425 (struct iwn_stop_scan *)(desc + 1); 2426 2427 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2428 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2429 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2430 scan->nchan, scan->status, scan->chan)); 2431 2432 if (scan->status == 1 && scan->chan <= 14 && 2433 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2434 /* 2435 * We just finished scanning 2GHz channels, 2436 * start scanning 5GHz ones. 2437 */ 2438 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2439 break; 2440 } 2441 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2442 ieee80211_end_scan(ic); 2443 break; 2444 } 2445 case IWN5000_CALIBRATION_RESULT: 2446 iwn5000_rx_calib_results(sc, desc, data); 2447 break; 2448 2449 case IWN5000_CALIBRATION_DONE: 2450 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2451 wakeup(sc); 2452 break; 2453 } 2454 2455 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2456 } 2457 2458 /* Tell the firmware what we have processed. */ 2459 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2460 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2461 } 2462 2463 /* 2464 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2465 * from power-down sleep mode. 2466 */ 2467 static void 2468 iwn_wakeup_intr(struct iwn_softc *sc) 2469 { 2470 int qid; 2471 2472 DPRINTF(("ucode wakeup from power-down sleep\n")); 2473 2474 /* Wakeup RX and TX rings. */ 2475 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2476 for (qid = 0; qid < sc->ntxqs; qid++) { 2477 struct iwn_tx_ring *ring = &sc->txq[qid]; 2478 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2479 } 2480 } 2481 2482 /* 2483 * Dump the error log of the firmware when a firmware panic occurs. Although 2484 * we can't debug the firmware because it is neither open source nor free, it 2485 * can help us to identify certain classes of problems. 2486 */ 2487 static void 2488 iwn_fatal_intr(struct iwn_softc *sc) 2489 { 2490 struct iwn_fw_dump dump; 2491 int i; 2492 2493 /* Force a complete recalibration on next init. */ 2494 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2495 2496 /* Check that the error log address is valid. */ 2497 if (sc->errptr < IWN_FW_DATA_BASE || 2498 sc->errptr + sizeof (dump) > 2499 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2500 aprint_error_dev(sc->sc_dev, 2501 "bad firmware error log address 0x%08x\n", sc->errptr); 2502 return; 2503 } 2504 if (iwn_nic_lock(sc) != 0) { 2505 aprint_error_dev(sc->sc_dev, 2506 "could not read firmware error log\n"); 2507 return; 2508 } 2509 /* Read firmware error log from SRAM. */ 2510 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2511 sizeof (dump) / sizeof (uint32_t)); 2512 iwn_nic_unlock(sc); 2513 2514 if (dump.valid == 0) { 2515 aprint_error_dev(sc->sc_dev, 2516 "firmware error log is empty\n"); 2517 return; 2518 } 2519 aprint_error("firmware error log:\n"); 2520 aprint_error(" error type = \"%s\" (0x%08X)\n", 2521 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2522 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2523 dump.id); 2524 aprint_error(" program counter = 0x%08X\n", dump.pc); 2525 aprint_error(" source line = 0x%08X\n", dump.src_line); 2526 aprint_error(" error data = 0x%08X%08X\n", 2527 dump.error_data[0], dump.error_data[1]); 2528 aprint_error(" branch link = 0x%08X%08X\n", 2529 dump.branch_link[0], dump.branch_link[1]); 2530 aprint_error(" interrupt link = 0x%08X%08X\n", 2531 dump.interrupt_link[0], dump.interrupt_link[1]); 2532 aprint_error(" time = %u\n", dump.time[0]); 2533 2534 /* Dump driver status (TX and RX rings) while we're here. */ 2535 aprint_error("driver status:\n"); 2536 for (i = 0; i < sc->ntxqs; i++) { 2537 struct iwn_tx_ring *ring = &sc->txq[i]; 2538 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2539 i, ring->qid, ring->cur, ring->queued); 2540 } 2541 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2542 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2543 } 2544 2545 static int 2546 iwn_intr(void *arg) 2547 { 2548 struct iwn_softc *sc = arg; 2549 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2550 uint32_t r1, r2, tmp; 2551 2552 /* Disable interrupts. */ 2553 IWN_WRITE(sc, IWN_INT_MASK, 0); 2554 2555 /* Read interrupts from ICT (fast) or from registers (slow). */ 2556 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2557 tmp = 0; 2558 while (sc->ict[sc->ict_cur] != 0) { 2559 tmp |= sc->ict[sc->ict_cur]; 2560 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2561 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2562 } 2563 tmp = le32toh(tmp); 2564 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2565 tmp = 0; 2566 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2567 tmp |= 0x8000; 2568 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2569 r2 = 0; /* Unused. */ 2570 } else { 2571 r1 = IWN_READ(sc, IWN_INT); 2572 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2573 return 0; /* Hardware gone! */ 2574 r2 = IWN_READ(sc, IWN_FH_INT); 2575 } 2576 if (r1 == 0 && r2 == 0) { 2577 if (ifp->if_flags & IFF_UP) 2578 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2579 return 0; /* Interrupt not for us. */ 2580 } 2581 2582 /* Acknowledge interrupts. */ 2583 IWN_WRITE(sc, IWN_INT, r1); 2584 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2585 IWN_WRITE(sc, IWN_FH_INT, r2); 2586 2587 if (r1 & IWN_INT_RF_TOGGLED) { 2588 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2589 aprint_error_dev(sc->sc_dev, 2590 "RF switch: radio %s\n", 2591 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2592 } 2593 if (r1 & IWN_INT_CT_REACHED) { 2594 aprint_error_dev(sc->sc_dev, 2595 "critical temperature reached!\n"); 2596 } 2597 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2598 aprint_error_dev(sc->sc_dev, 2599 "fatal firmware error\n"); 2600 /* Dump firmware error log and stop. */ 2601 iwn_fatal_intr(sc); 2602 ifp->if_flags &= ~IFF_UP; 2603 iwn_stop(ifp, 1); 2604 return 1; 2605 } 2606 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2607 (r2 & IWN_FH_INT_RX)) { 2608 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2609 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2610 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2611 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2612 IWN_INT_PERIODIC_DIS); 2613 iwn_notif_intr(sc); 2614 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2615 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2616 IWN_INT_PERIODIC_ENA); 2617 } 2618 } else 2619 iwn_notif_intr(sc); 2620 } 2621 2622 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2623 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2624 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2625 wakeup(sc); /* FH DMA transfer completed. */ 2626 } 2627 2628 if (r1 & IWN_INT_ALIVE) 2629 wakeup(sc); /* Firmware is alive. */ 2630 2631 if (r1 & IWN_INT_WAKEUP) 2632 iwn_wakeup_intr(sc); 2633 2634 /* Re-enable interrupts. */ 2635 if (ifp->if_flags & IFF_UP) 2636 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2637 2638 return 1; 2639 } 2640 2641 /* 2642 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2643 * 5000 adapters use a slightly different format). 2644 */ 2645 static void 2646 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2647 uint16_t len) 2648 { 2649 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2650 2651 *w = htole16(len + 8); 2652 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2653 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2654 sizeof (uint16_t), 2655 BUS_DMASYNC_PREWRITE); 2656 if (idx < IWN_SCHED_WINSZ) { 2657 *(w + IWN_TX_RING_COUNT) = *w; 2658 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2659 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2660 (char *)(void *)sc->sched_dma.vaddr, 2661 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2662 } 2663 } 2664 2665 static void 2666 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2667 uint16_t len) 2668 { 2669 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2670 2671 *w = htole16(id << 12 | (len + 8)); 2672 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2673 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2674 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2675 if (idx < IWN_SCHED_WINSZ) { 2676 *(w + IWN_TX_RING_COUNT) = *w; 2677 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2678 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2679 (char *)(void *)sc->sched_dma.vaddr, 2680 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2681 } 2682 } 2683 2684 #ifdef notyet 2685 static void 2686 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2687 { 2688 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2689 2690 *w = (*w & htole16(0xf000)) | htole16(1); 2691 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2692 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2693 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2694 if (idx < IWN_SCHED_WINSZ) { 2695 *(w + IWN_TX_RING_COUNT) = *w; 2696 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2697 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2698 (char *)(void *)sc->sched_dma.vaddr, 2699 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2700 } 2701 } 2702 #endif 2703 2704 static int 2705 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2706 { 2707 struct ieee80211com *ic = &sc->sc_ic; 2708 struct iwn_node *wn = (void *)ni; 2709 struct iwn_tx_ring *ring; 2710 struct iwn_tx_desc *desc; 2711 struct iwn_tx_data *data; 2712 struct iwn_tx_cmd *cmd; 2713 struct iwn_cmd_data *tx; 2714 const struct iwn_rate *rinfo; 2715 struct ieee80211_frame *wh; 2716 struct ieee80211_key *k = NULL; 2717 struct mbuf *m1; 2718 uint32_t flags; 2719 u_int hdrlen; 2720 bus_dma_segment_t *seg; 2721 uint8_t tid, ridx, txant, type; 2722 int i, totlen, error, pad; 2723 2724 const struct chanAccParams *cap; 2725 int noack; 2726 int hdrlen2; 2727 2728 wh = mtod(m, struct ieee80211_frame *); 2729 hdrlen = ieee80211_anyhdrsize(wh); 2730 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2731 2732 hdrlen2 = (IEEE80211_QOS_HAS_SEQ(wh)) ? 2733 sizeof (struct ieee80211_qosframe) : 2734 sizeof (struct ieee80211_frame); 2735 2736 if (hdrlen != hdrlen2) 2737 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2738 hdrlen, hdrlen2); 2739 2740 /* XXX OpenBSD sets a different tid when using QOS */ 2741 tid = 0; 2742 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2743 cap = &ic->ic_wme.wme_chanParams; 2744 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2745 } 2746 else 2747 noack = 0; 2748 2749 ring = &sc->txq[ac]; 2750 desc = &ring->desc[ring->cur]; 2751 data = &ring->data[ring->cur]; 2752 2753 /* Choose a TX rate index. */ 2754 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2755 type != IEEE80211_FC0_TYPE_DATA) { 2756 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2757 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2758 } else if (ic->ic_fixed_rate != -1) { 2759 ridx = sc->fixed_ridx; 2760 } else 2761 ridx = wn->ridx[ni->ni_txrate]; 2762 rinfo = &iwn_rates[ridx]; 2763 2764 /* Encrypt the frame if need be. */ 2765 /* 2766 * XXX For now, NetBSD swaps the encryption and bpf sections 2767 * in order to match old code and other drivers. Tests with 2768 * tcpdump indicates that the order is irrelevant, however, 2769 * as bpf produces unencrypted data for both ordering choices. 2770 */ 2771 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2772 k = ieee80211_crypto_encap(ic, ni, m); 2773 if (k == NULL) { 2774 m_freem(m); 2775 return ENOBUFS; 2776 } 2777 /* Packet header may have moved, reset our local pointer. */ 2778 wh = mtod(m, struct ieee80211_frame *); 2779 } 2780 totlen = m->m_pkthdr.len; 2781 2782 if (sc->sc_drvbpf != NULL) { 2783 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2784 2785 tap->wt_flags = 0; 2786 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2787 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2788 tap->wt_rate = rinfo->rate; 2789 tap->wt_hwqueue = ac; 2790 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2791 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2792 2793 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2794 } 2795 2796 /* Prepare TX firmware command. */ 2797 cmd = &ring->cmd[ring->cur]; 2798 cmd->code = IWN_CMD_TX_DATA; 2799 cmd->flags = 0; 2800 cmd->qid = ring->qid; 2801 cmd->idx = ring->cur; 2802 2803 tx = (struct iwn_cmd_data *)cmd->data; 2804 /* NB: No need to clear tx, all fields are reinitialized here. */ 2805 tx->scratch = 0; /* clear "scratch" area */ 2806 2807 flags = 0; 2808 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2809 /* Unicast frame, check if an ACK is expected. */ 2810 if (!noack) 2811 flags |= IWN_TX_NEED_ACK; 2812 } 2813 2814 #ifdef notyet 2815 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2816 if ((wh->i_fc[0] & 2817 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2818 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2819 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2820 #endif 2821 2822 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2823 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2824 2825 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2826 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2827 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2828 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2829 flags |= IWN_TX_NEED_RTS; 2830 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2831 ridx >= IWN_RIDX_OFDM6) { 2832 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2833 flags |= IWN_TX_NEED_CTS; 2834 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2835 flags |= IWN_TX_NEED_RTS; 2836 } 2837 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2838 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2839 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2840 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2841 flags |= IWN_TX_NEED_PROTECTION; 2842 } else 2843 flags |= IWN_TX_FULL_TXOP; 2844 } 2845 } 2846 2847 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2848 type != IEEE80211_FC0_TYPE_DATA) 2849 tx->id = sc->broadcast_id; 2850 else 2851 tx->id = wn->id; 2852 2853 if (type == IEEE80211_FC0_TYPE_MGT) { 2854 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2855 2856 #ifndef IEEE80211_STA_ONLY 2857 /* Tell HW to set timestamp in probe responses. */ 2858 /* XXX NetBSD rev 1.11 added probe requests here but */ 2859 /* probe requests do not take timestamps (from Bergamini). */ 2860 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2861 flags |= IWN_TX_INSERT_TSTAMP; 2862 #endif 2863 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2864 /* changes here. These are not needed (from Bergamini). */ 2865 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2866 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2867 tx->timeout = htole16(3); 2868 else 2869 tx->timeout = htole16(2); 2870 } else 2871 tx->timeout = htole16(0); 2872 2873 if (hdrlen & 3) { 2874 /* First segment length must be a multiple of 4. */ 2875 flags |= IWN_TX_NEED_PADDING; 2876 pad = 4 - (hdrlen & 3); 2877 } else 2878 pad = 0; 2879 2880 tx->len = htole16(totlen); 2881 tx->tid = tid; 2882 tx->rts_ntries = 60; 2883 tx->data_ntries = 15; 2884 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2885 tx->plcp = rinfo->plcp; 2886 tx->rflags = rinfo->flags; 2887 if (tx->id == sc->broadcast_id) { 2888 /* Group or management frame. */ 2889 tx->linkq = 0; 2890 /* XXX Alternate between antenna A and B? */ 2891 txant = IWN_LSB(sc->txchainmask); 2892 tx->rflags |= IWN_RFLAG_ANT(txant); 2893 } else { 2894 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2895 flags |= IWN_TX_LINKQ; /* enable MRR */ 2896 } 2897 /* Set physical address of "scratch area". */ 2898 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2899 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2900 2901 /* Copy 802.11 header in TX command. */ 2902 /* XXX NetBSD changed this in rev 1.20 */ 2903 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2904 2905 /* Trim 802.11 header. */ 2906 m_adj(m, hdrlen); 2907 tx->security = 0; 2908 tx->flags = htole32(flags); 2909 2910 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2911 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2912 if (error != 0) { 2913 if (error != EFBIG) { 2914 aprint_error_dev(sc->sc_dev, 2915 "can't map mbuf (error %d)\n", error); 2916 m_freem(m); 2917 return error; 2918 } 2919 /* Too many DMA segments, linearize mbuf. */ 2920 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2921 if (m1 == NULL) { 2922 m_freem(m); 2923 return ENOBUFS; 2924 } 2925 if (m->m_pkthdr.len > MHLEN) { 2926 MCLGET(m1, M_DONTWAIT); 2927 if (!(m1->m_flags & M_EXT)) { 2928 m_freem(m); 2929 m_freem(m1); 2930 return ENOBUFS; 2931 } 2932 } 2933 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2934 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2935 m_freem(m); 2936 m = m1; 2937 2938 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2939 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2940 if (error != 0) { 2941 aprint_error_dev(sc->sc_dev, 2942 "can't map mbuf (error %d)\n", error); 2943 m_freem(m); 2944 return error; 2945 } 2946 } 2947 2948 data->m = m; 2949 data->ni = ni; 2950 2951 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 2952 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 2953 2954 /* Fill TX descriptor. */ 2955 desc->nsegs = 1 + data->map->dm_nsegs; 2956 /* First DMA segment is used by the TX command. */ 2957 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 2958 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 2959 (4 + sizeof (*tx) + hdrlen + pad) << 4); 2960 /* Other DMA segments are for data payload. */ 2961 seg = data->map->dm_segs; 2962 for (i = 1; i <= data->map->dm_nsegs; i++) { 2963 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 2964 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 2965 seg->ds_len << 4); 2966 seg++; 2967 } 2968 2969 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2970 BUS_DMASYNC_PREWRITE); 2971 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 2972 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 2973 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 2974 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2975 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 2976 sizeof (*desc), BUS_DMASYNC_PREWRITE); 2977 2978 #ifdef notyet 2979 /* Update TX scheduler. */ 2980 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 2981 #endif 2982 2983 /* Kick TX ring. */ 2984 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 2985 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 2986 2987 /* Mark TX ring as full if we reach a certain threshold. */ 2988 if (++ring->queued > IWN_TX_RING_HIMARK) 2989 sc->qfullmsk |= 1 << ring->qid; 2990 2991 return 0; 2992 } 2993 2994 static void 2995 iwn_start(struct ifnet *ifp) 2996 { 2997 struct iwn_softc *sc = ifp->if_softc; 2998 struct ieee80211com *ic = &sc->sc_ic; 2999 struct ieee80211_node *ni; 3000 struct ether_header *eh; 3001 struct mbuf *m; 3002 int ac; 3003 3004 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3005 return; 3006 3007 for (;;) { 3008 if (sc->qfullmsk != 0) { 3009 ifp->if_flags |= IFF_OACTIVE; 3010 break; 3011 } 3012 /* Send pending management frames first. */ 3013 IF_DEQUEUE(&ic->ic_mgtq, m); 3014 if (m != NULL) { 3015 ni = (void *)m->m_pkthdr.rcvif; 3016 ac = 0; 3017 goto sendit; 3018 } 3019 if (ic->ic_state != IEEE80211_S_RUN) 3020 break; 3021 3022 /* Encapsulate and send data frames. */ 3023 IFQ_DEQUEUE(&ifp->if_snd, m); 3024 if (m == NULL) 3025 break; 3026 if (m->m_len < sizeof (*eh) && 3027 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3028 ifp->if_oerrors++; 3029 continue; 3030 } 3031 eh = mtod(m, struct ether_header *); 3032 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3033 if (ni == NULL) { 3034 m_freem(m); 3035 ifp->if_oerrors++; 3036 continue; 3037 } 3038 /* classify mbuf so we can find which tx ring to use */ 3039 if (ieee80211_classify(ic, m, ni) != 0) { 3040 m_freem(m); 3041 ieee80211_free_node(ni); 3042 ifp->if_oerrors++; 3043 continue; 3044 } 3045 3046 /* No QoS encapsulation for EAPOL frames. */ 3047 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3048 M_WME_GETAC(m) : WME_AC_BE; 3049 3050 bpf_mtap(ifp, m); 3051 3052 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3053 ieee80211_free_node(ni); 3054 ifp->if_oerrors++; 3055 continue; 3056 } 3057 sendit: 3058 bpf_mtap3(ic->ic_rawbpf, m); 3059 3060 if (iwn_tx(sc, m, ni, ac) != 0) { 3061 ieee80211_free_node(ni); 3062 ifp->if_oerrors++; 3063 continue; 3064 } 3065 3066 sc->sc_tx_timer = 5; 3067 ifp->if_timer = 1; 3068 } 3069 } 3070 3071 static void 3072 iwn_watchdog(struct ifnet *ifp) 3073 { 3074 struct iwn_softc *sc = ifp->if_softc; 3075 3076 ifp->if_timer = 0; 3077 3078 if (sc->sc_tx_timer > 0) { 3079 if (--sc->sc_tx_timer == 0) { 3080 aprint_error_dev(sc->sc_dev, 3081 "device timeout\n"); 3082 ifp->if_flags &= ~IFF_UP; 3083 iwn_stop(ifp, 1); 3084 ifp->if_oerrors++; 3085 return; 3086 } 3087 ifp->if_timer = 1; 3088 } 3089 3090 ieee80211_watchdog(&sc->sc_ic); 3091 } 3092 3093 static int 3094 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3095 { 3096 struct iwn_softc *sc = ifp->if_softc; 3097 struct ieee80211com *ic = &sc->sc_ic; 3098 struct ifaddr *ifa; 3099 const struct sockaddr *sa; 3100 int s, error = 0; 3101 3102 s = splnet(); 3103 3104 switch (cmd) { 3105 case SIOCSIFADDR: 3106 ifa = (struct ifaddr *)data; 3107 ifp->if_flags |= IFF_UP; 3108 #ifdef INET 3109 if (ifa->ifa_addr->sa_family == AF_INET) 3110 arp_ifinit(&ic->ic_ac, ifa); 3111 #endif 3112 /* FALLTHROUGH */ 3113 case SIOCSIFFLAGS: 3114 /* XXX Added as it is in every NetBSD driver */ 3115 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3116 break; 3117 if (ifp->if_flags & IFF_UP) { 3118 if (!(ifp->if_flags & IFF_RUNNING)) 3119 error = iwn_init(ifp); 3120 } else { 3121 if (ifp->if_flags & IFF_RUNNING) 3122 iwn_stop(ifp, 1); 3123 } 3124 break; 3125 3126 case SIOCADDMULTI: 3127 case SIOCDELMULTI: 3128 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3129 error = (cmd == SIOCADDMULTI) ? 3130 ether_addmulti(sa, &sc->sc_ec) : 3131 ether_delmulti(sa, &sc->sc_ec); 3132 3133 if (error == ENETRESET) 3134 error = 0; 3135 break; 3136 3137 default: 3138 error = ieee80211_ioctl(ic, cmd, data); 3139 } 3140 3141 if (error == ENETRESET) { 3142 error = 0; 3143 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3144 (IFF_UP | IFF_RUNNING)) { 3145 iwn_stop(ifp, 0); 3146 error = iwn_init(ifp); 3147 } 3148 } 3149 3150 splx(s); 3151 return error; 3152 } 3153 3154 /* 3155 * Send a command to the firmware. 3156 */ 3157 static int 3158 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3159 { 3160 struct iwn_tx_ring *ring = &sc->txq[4]; 3161 struct iwn_tx_desc *desc; 3162 struct iwn_tx_data *data; 3163 struct iwn_tx_cmd *cmd; 3164 struct mbuf *m; 3165 bus_addr_t paddr; 3166 int totlen, error; 3167 3168 desc = &ring->desc[ring->cur]; 3169 data = &ring->data[ring->cur]; 3170 totlen = 4 + size; 3171 3172 if (size > sizeof cmd->data) { 3173 /* Command is too large to fit in a descriptor. */ 3174 if (totlen > MCLBYTES) 3175 return EINVAL; 3176 MGETHDR(m, M_DONTWAIT, MT_DATA); 3177 if (m == NULL) 3178 return ENOMEM; 3179 if (totlen > MHLEN) { 3180 MCLGET(m, M_DONTWAIT); 3181 if (!(m->m_flags & M_EXT)) { 3182 m_freem(m); 3183 return ENOMEM; 3184 } 3185 } 3186 cmd = mtod(m, struct iwn_tx_cmd *); 3187 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3188 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3189 if (error != 0) { 3190 m_freem(m); 3191 return error; 3192 } 3193 data->m = m; 3194 paddr = data->map->dm_segs[0].ds_addr; 3195 } else { 3196 cmd = &ring->cmd[ring->cur]; 3197 paddr = data->cmd_paddr; 3198 } 3199 3200 cmd->code = code; 3201 cmd->flags = 0; 3202 cmd->qid = ring->qid; 3203 cmd->idx = ring->cur; 3204 memcpy(cmd->data, buf, size); 3205 3206 desc->nsegs = 1; 3207 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3208 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3209 3210 if (size > sizeof cmd->data) { 3211 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3212 BUS_DMASYNC_PREWRITE); 3213 } else { 3214 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3215 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3216 totlen, BUS_DMASYNC_PREWRITE); 3217 } 3218 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3219 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3220 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3221 3222 #ifdef notyet 3223 /* Update TX scheduler. */ 3224 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3225 #endif 3226 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3227 3228 /* Kick command ring. */ 3229 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3230 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3231 3232 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3233 } 3234 3235 static int 3236 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3237 { 3238 struct iwn4965_node_info hnode; 3239 char *src, *dst; 3240 3241 /* 3242 * We use the node structure for 5000 Series internally (it is 3243 * a superset of the one for 4965AGN). We thus copy the common 3244 * fields before sending the command. 3245 */ 3246 src = (char *)node; 3247 dst = (char *)&hnode; 3248 memcpy(dst, src, 48); 3249 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3250 memcpy(dst + 48, src + 72, 20); 3251 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3252 } 3253 3254 static int 3255 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3256 { 3257 /* Direct mapping. */ 3258 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3259 } 3260 3261 static int 3262 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3263 { 3264 struct iwn_node *wn = (void *)ni; 3265 struct ieee80211_rateset *rs = &ni->ni_rates; 3266 struct iwn_cmd_link_quality linkq; 3267 const struct iwn_rate *rinfo; 3268 uint8_t txant; 3269 int i, txrate; 3270 3271 /* Use the first valid TX antenna. */ 3272 txant = IWN_LSB(sc->txchainmask); 3273 3274 memset(&linkq, 0, sizeof linkq); 3275 linkq.id = wn->id; 3276 linkq.antmsk_1stream = txant; 3277 linkq.antmsk_2stream = IWN_ANT_AB; 3278 linkq.ampdu_max = 31; 3279 linkq.ampdu_threshold = 3; 3280 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3281 3282 /* Start at highest available bit-rate. */ 3283 txrate = rs->rs_nrates - 1; 3284 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3285 rinfo = &iwn_rates[wn->ridx[txrate]]; 3286 linkq.retry[i].plcp = rinfo->plcp; 3287 linkq.retry[i].rflags = rinfo->flags; 3288 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3289 /* Next retry at immediate lower bit-rate. */ 3290 if (txrate > 0) 3291 txrate--; 3292 } 3293 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3294 } 3295 3296 /* 3297 * Broadcast node is used to send group-addressed and management frames. 3298 */ 3299 static int 3300 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3301 { 3302 struct iwn_ops *ops = &sc->ops; 3303 struct iwn_node_info node; 3304 struct iwn_cmd_link_quality linkq; 3305 const struct iwn_rate *rinfo; 3306 uint8_t txant; 3307 int i, error; 3308 3309 memset(&node, 0, sizeof node); 3310 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3311 node.id = sc->broadcast_id; 3312 DPRINTF(("adding broadcast node\n")); 3313 if ((error = ops->add_node(sc, &node, async)) != 0) 3314 return error; 3315 3316 /* Use the first valid TX antenna. */ 3317 txant = IWN_LSB(sc->txchainmask); 3318 3319 memset(&linkq, 0, sizeof linkq); 3320 linkq.id = sc->broadcast_id; 3321 linkq.antmsk_1stream = txant; 3322 linkq.antmsk_2stream = IWN_ANT_AB; 3323 linkq.ampdu_max = 64; 3324 linkq.ampdu_threshold = 3; 3325 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3326 3327 /* Use lowest mandatory bit-rate. */ 3328 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3329 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3330 linkq.retry[0].plcp = rinfo->plcp; 3331 linkq.retry[0].rflags = rinfo->flags; 3332 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3333 /* Use same bit-rate for all TX retries. */ 3334 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3335 linkq.retry[i].plcp = linkq.retry[0].plcp; 3336 linkq.retry[i].rflags = linkq.retry[0].rflags; 3337 } 3338 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3339 } 3340 3341 static void 3342 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3343 { 3344 struct iwn_cmd_led led; 3345 3346 /* Clear microcode LED ownership. */ 3347 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3348 3349 led.which = which; 3350 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3351 led.off = off; 3352 led.on = on; 3353 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3354 } 3355 3356 /* 3357 * Set the critical temperature at which the firmware will stop the radio 3358 * and notify us. 3359 */ 3360 static int 3361 iwn_set_critical_temp(struct iwn_softc *sc) 3362 { 3363 struct iwn_critical_temp crit; 3364 int32_t temp; 3365 3366 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3367 3368 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3369 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3370 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3371 temp = IWN_CTOK(110); 3372 else 3373 temp = 110; 3374 memset(&crit, 0, sizeof crit); 3375 crit.tempR = htole32(temp); 3376 DPRINTF(("setting critical temperature to %d\n", temp)); 3377 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3378 } 3379 3380 static int 3381 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3382 { 3383 struct iwn_cmd_timing cmd; 3384 uint64_t val, mod; 3385 3386 memset(&cmd, 0, sizeof cmd); 3387 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3388 cmd.bintval = htole16(ni->ni_intval); 3389 cmd.lintval = htole16(10); 3390 3391 /* Compute remaining time until next beacon. */ 3392 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3393 mod = le64toh(cmd.tstamp) % val; 3394 cmd.binitval = htole32((uint32_t)(val - mod)); 3395 3396 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3397 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3398 3399 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3400 } 3401 3402 static void 3403 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3404 { 3405 /* Adjust TX power if need be (delta >= 3 degC). */ 3406 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3407 if (abs(temp - sc->temp) >= 3) { 3408 /* Record temperature of last calibration. */ 3409 sc->temp = temp; 3410 (void)iwn4965_set_txpower(sc, 1); 3411 } 3412 } 3413 3414 /* 3415 * Set TX power for current channel (each rate has its own power settings). 3416 * This function takes into account the regulatory information from EEPROM, 3417 * the current temperature and the current voltage. 3418 */ 3419 static int 3420 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3421 { 3422 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3423 #define fdivround(a, b, n) \ 3424 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3425 /* Linear interpolation. */ 3426 #define interpolate(x, x1, y1, x2, y2, n) \ 3427 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3428 3429 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3430 struct ieee80211com *ic = &sc->sc_ic; 3431 struct iwn_ucode_info *uc = &sc->ucode_info; 3432 struct ieee80211_channel *ch; 3433 struct iwn4965_cmd_txpower cmd; 3434 struct iwn4965_eeprom_chan_samples *chans; 3435 const uint8_t *rf_gain, *dsp_gain; 3436 int32_t vdiff, tdiff; 3437 int i, c, grp, maxpwr; 3438 uint8_t chan; 3439 3440 /* Retrieve current channel from last RXON. */ 3441 chan = sc->rxon.chan; 3442 DPRINTF(("setting TX power for channel %d\n", chan)); 3443 ch = &ic->ic_channels[chan]; 3444 3445 memset(&cmd, 0, sizeof cmd); 3446 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3447 cmd.chan = chan; 3448 3449 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3450 maxpwr = sc->maxpwr5GHz; 3451 rf_gain = iwn4965_rf_gain_5ghz; 3452 dsp_gain = iwn4965_dsp_gain_5ghz; 3453 } else { 3454 maxpwr = sc->maxpwr2GHz; 3455 rf_gain = iwn4965_rf_gain_2ghz; 3456 dsp_gain = iwn4965_dsp_gain_2ghz; 3457 } 3458 3459 /* Compute voltage compensation. */ 3460 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3461 if (vdiff > 0) 3462 vdiff *= 2; 3463 if (abs(vdiff) > 2) 3464 vdiff = 0; 3465 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3466 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3467 3468 /* Get channel attenuation group. */ 3469 if (chan <= 20) /* 1-20 */ 3470 grp = 4; 3471 else if (chan <= 43) /* 34-43 */ 3472 grp = 0; 3473 else if (chan <= 70) /* 44-70 */ 3474 grp = 1; 3475 else if (chan <= 124) /* 71-124 */ 3476 grp = 2; 3477 else /* 125-200 */ 3478 grp = 3; 3479 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3480 3481 /* Get channel sub-band. */ 3482 for (i = 0; i < IWN_NBANDS; i++) 3483 if (sc->bands[i].lo != 0 && 3484 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3485 break; 3486 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3487 return EINVAL; 3488 chans = sc->bands[i].chans; 3489 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3490 3491 for (c = 0; c < 2; c++) { 3492 uint8_t power, gain, temp; 3493 int maxchpwr, pwr, ridx, idx; 3494 3495 power = interpolate(chan, 3496 chans[0].num, chans[0].samples[c][1].power, 3497 chans[1].num, chans[1].samples[c][1].power, 1); 3498 gain = interpolate(chan, 3499 chans[0].num, chans[0].samples[c][1].gain, 3500 chans[1].num, chans[1].samples[c][1].gain, 1); 3501 temp = interpolate(chan, 3502 chans[0].num, chans[0].samples[c][1].temp, 3503 chans[1].num, chans[1].samples[c][1].temp, 1); 3504 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3505 c, power, gain, temp)); 3506 3507 /* Compute temperature compensation. */ 3508 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3509 DPRINTF(("temperature compensation=%d (current=%d, " 3510 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3511 3512 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3513 /* Convert dBm to half-dBm. */ 3514 maxchpwr = sc->maxpwr[chan] * 2; 3515 if ((ridx / 8) & 1) 3516 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3517 3518 pwr = maxpwr; 3519 3520 /* Adjust TX power based on rate. */ 3521 if ((ridx % 8) == 5) 3522 pwr -= 15; /* OFDM48: -7.5dB */ 3523 else if ((ridx % 8) == 6) 3524 pwr -= 17; /* OFDM54: -8.5dB */ 3525 else if ((ridx % 8) == 7) 3526 pwr -= 20; /* OFDM60: -10dB */ 3527 else 3528 pwr -= 10; /* Others: -5dB */ 3529 3530 /* Do not exceed channel max TX power. */ 3531 if (pwr > maxchpwr) 3532 pwr = maxchpwr; 3533 3534 idx = gain - (pwr - power) - tdiff - vdiff; 3535 if ((ridx / 8) & 1) /* MIMO */ 3536 idx += (int32_t)le32toh(uc->atten[grp][c]); 3537 3538 if (cmd.band == 0) 3539 idx += 9; /* 5GHz */ 3540 if (ridx == IWN_RIDX_MAX) 3541 idx += 5; /* CCK */ 3542 3543 /* Make sure idx stays in a valid range. */ 3544 if (idx < 0) 3545 idx = 0; 3546 else if (idx > IWN4965_MAX_PWR_INDEX) 3547 idx = IWN4965_MAX_PWR_INDEX; 3548 3549 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3550 c, ridx, idx)); 3551 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3552 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3553 } 3554 } 3555 3556 DPRINTF(("setting TX power for chan %d\n", chan)); 3557 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3558 3559 #undef interpolate 3560 #undef fdivround 3561 } 3562 3563 static int 3564 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3565 { 3566 struct iwn5000_cmd_txpower cmd; 3567 3568 /* 3569 * TX power calibration is handled automatically by the firmware 3570 * for 5000 Series. 3571 */ 3572 memset(&cmd, 0, sizeof cmd); 3573 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3574 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3575 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3576 DPRINTF(("setting TX power\n")); 3577 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3578 } 3579 3580 /* 3581 * Retrieve the maximum RSSI (in dBm) among receivers. 3582 */ 3583 static int 3584 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3585 { 3586 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3587 uint8_t mask, agc; 3588 int rssi; 3589 3590 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3591 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3592 3593 rssi = 0; 3594 if (mask & IWN_ANT_A) 3595 rssi = MAX(rssi, phy->rssi[0]); 3596 if (mask & IWN_ANT_B) 3597 rssi = MAX(rssi, phy->rssi[2]); 3598 if (mask & IWN_ANT_C) 3599 rssi = MAX(rssi, phy->rssi[4]); 3600 3601 return rssi - agc - IWN_RSSI_TO_DBM; 3602 } 3603 3604 static int 3605 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3606 { 3607 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3608 uint8_t agc; 3609 int rssi; 3610 3611 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3612 3613 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3614 le16toh(phy->rssi[1]) & 0xff); 3615 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3616 3617 return rssi - agc - IWN_RSSI_TO_DBM; 3618 } 3619 3620 /* 3621 * Retrieve the average noise (in dBm) among receivers. 3622 */ 3623 static int 3624 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3625 { 3626 int i, total, nbant, noise; 3627 3628 total = nbant = 0; 3629 for (i = 0; i < 3; i++) { 3630 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3631 continue; 3632 total += noise; 3633 nbant++; 3634 } 3635 /* There should be at least one antenna but check anyway. */ 3636 return (nbant == 0) ? -127 : (total / nbant) - 107; 3637 } 3638 3639 /* 3640 * Compute temperature (in degC) from last received statistics. 3641 */ 3642 static int 3643 iwn4965_get_temperature(struct iwn_softc *sc) 3644 { 3645 struct iwn_ucode_info *uc = &sc->ucode_info; 3646 int32_t r1, r2, r3, r4, temp; 3647 3648 r1 = le32toh(uc->temp[0].chan20MHz); 3649 r2 = le32toh(uc->temp[1].chan20MHz); 3650 r3 = le32toh(uc->temp[2].chan20MHz); 3651 r4 = le32toh(sc->rawtemp); 3652 3653 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3654 return 0; 3655 3656 /* Sign-extend 23-bit R4 value to 32-bit. */ 3657 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3658 /* Compute temperature in Kelvin. */ 3659 temp = (259 * (r4 - r2)) / (r3 - r1); 3660 temp = (temp * 97) / 100 + 8; 3661 3662 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3663 return IWN_KTOC(temp); 3664 } 3665 3666 static int 3667 iwn5000_get_temperature(struct iwn_softc *sc) 3668 { 3669 int32_t temp; 3670 3671 /* 3672 * Temperature is not used by the driver for 5000 Series because 3673 * TX power calibration is handled by firmware. We export it to 3674 * users through the sensor framework though. 3675 */ 3676 temp = le32toh(sc->rawtemp); 3677 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3678 temp = (temp / -5) + sc->temp_off; 3679 temp = IWN_KTOC(temp); 3680 } 3681 return temp; 3682 } 3683 3684 /* 3685 * Initialize sensitivity calibration state machine. 3686 */ 3687 static int 3688 iwn_init_sensitivity(struct iwn_softc *sc) 3689 { 3690 struct iwn_ops *ops = &sc->ops; 3691 struct iwn_calib_state *calib = &sc->calib; 3692 uint32_t flags; 3693 int error; 3694 3695 /* Reset calibration state machine. */ 3696 memset(calib, 0, sizeof (*calib)); 3697 calib->state = IWN_CALIB_STATE_INIT; 3698 calib->cck_state = IWN_CCK_STATE_HIFA; 3699 /* Set initial correlation values. */ 3700 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3701 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3702 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3703 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3704 calib->cck_x4 = 125; 3705 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3706 calib->energy_cck = sc->limits->energy_cck; 3707 3708 /* Write initial sensitivity. */ 3709 if ((error = iwn_send_sensitivity(sc)) != 0) 3710 return error; 3711 3712 /* Write initial gains. */ 3713 if ((error = ops->init_gains(sc)) != 0) 3714 return error; 3715 3716 /* Request statistics at each beacon interval. */ 3717 flags = 0; 3718 DPRINTF(("sending request for statistics\n")); 3719 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3720 } 3721 3722 /* 3723 * Collect noise and RSSI statistics for the first 20 beacons received 3724 * after association and use them to determine connected antennas and 3725 * to set differential gains. 3726 */ 3727 static void 3728 iwn_collect_noise(struct iwn_softc *sc, 3729 const struct iwn_rx_general_stats *stats) 3730 { 3731 struct iwn_ops *ops = &sc->ops; 3732 struct iwn_calib_state *calib = &sc->calib; 3733 uint32_t val; 3734 int i; 3735 3736 /* Accumulate RSSI and noise for all 3 antennas. */ 3737 for (i = 0; i < 3; i++) { 3738 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3739 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3740 } 3741 /* NB: We update differential gains only once after 20 beacons. */ 3742 if (++calib->nbeacons < 20) 3743 return; 3744 3745 /* Determine highest average RSSI. */ 3746 val = MAX(calib->rssi[0], calib->rssi[1]); 3747 val = MAX(calib->rssi[2], val); 3748 3749 /* Determine which antennas are connected. */ 3750 sc->chainmask = sc->rxchainmask; 3751 for (i = 0; i < 3; i++) 3752 if (val - calib->rssi[i] > 15 * 20) 3753 sc->chainmask &= ~(1 << i); 3754 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3755 sc->rxchainmask, sc->chainmask)); 3756 3757 /* If none of the TX antennas are connected, keep at least one. */ 3758 if ((sc->chainmask & sc->txchainmask) == 0) 3759 sc->chainmask |= IWN_LSB(sc->txchainmask); 3760 3761 (void)ops->set_gains(sc); 3762 calib->state = IWN_CALIB_STATE_RUN; 3763 3764 #ifdef notyet 3765 /* XXX Disable RX chains with no antennas connected. */ 3766 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3767 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3768 #endif 3769 3770 /* Enable power-saving mode if requested by user. */ 3771 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3772 (void)iwn_set_pslevel(sc, 0, 3, 1); 3773 } 3774 3775 static int 3776 iwn4965_init_gains(struct iwn_softc *sc) 3777 { 3778 struct iwn_phy_calib_gain cmd; 3779 3780 memset(&cmd, 0, sizeof cmd); 3781 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3782 /* Differential gains initially set to 0 for all 3 antennas. */ 3783 DPRINTF(("setting initial differential gains\n")); 3784 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3785 } 3786 3787 static int 3788 iwn5000_init_gains(struct iwn_softc *sc) 3789 { 3790 struct iwn_phy_calib cmd; 3791 3792 memset(&cmd, 0, sizeof cmd); 3793 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3794 cmd.ngroups = 1; 3795 cmd.isvalid = 1; 3796 DPRINTF(("setting initial differential gains\n")); 3797 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3798 } 3799 3800 static int 3801 iwn4965_set_gains(struct iwn_softc *sc) 3802 { 3803 struct iwn_calib_state *calib = &sc->calib; 3804 struct iwn_phy_calib_gain cmd; 3805 int i, delta, noise; 3806 3807 /* Get minimal noise among connected antennas. */ 3808 noise = INT_MAX; /* NB: There's at least one antenna. */ 3809 for (i = 0; i < 3; i++) 3810 if (sc->chainmask & (1 << i)) 3811 noise = MIN(calib->noise[i], noise); 3812 3813 memset(&cmd, 0, sizeof cmd); 3814 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3815 /* Set differential gains for connected antennas. */ 3816 for (i = 0; i < 3; i++) { 3817 if (sc->chainmask & (1 << i)) { 3818 /* Compute attenuation (in unit of 1.5dB). */ 3819 delta = (noise - (int32_t)calib->noise[i]) / 30; 3820 /* NB: delta <= 0 */ 3821 /* Limit to [-4.5dB,0]. */ 3822 cmd.gain[i] = MIN(abs(delta), 3); 3823 if (delta < 0) 3824 cmd.gain[i] |= 1 << 2; /* sign bit */ 3825 } 3826 } 3827 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3828 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3829 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3830 } 3831 3832 static int 3833 iwn5000_set_gains(struct iwn_softc *sc) 3834 { 3835 struct iwn_calib_state *calib = &sc->calib; 3836 struct iwn_phy_calib_gain cmd; 3837 int i, ant, div, delta; 3838 3839 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3840 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3841 3842 memset(&cmd, 0, sizeof cmd); 3843 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3844 cmd.ngroups = 1; 3845 cmd.isvalid = 1; 3846 /* Get first available RX antenna as referential. */ 3847 ant = IWN_LSB(sc->rxchainmask); 3848 /* Set differential gains for other antennas. */ 3849 for (i = ant + 1; i < 3; i++) { 3850 if (sc->chainmask & (1 << i)) { 3851 /* The delta is relative to antenna "ant". */ 3852 delta = ((int32_t)calib->noise[ant] - 3853 (int32_t)calib->noise[i]) / div; 3854 /* Limit to [-4.5dB,+4.5dB]. */ 3855 cmd.gain[i - 1] = MIN(abs(delta), 3); 3856 if (delta < 0) 3857 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3858 } 3859 } 3860 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3861 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3862 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3863 } 3864 3865 /* 3866 * Tune RF RX sensitivity based on the number of false alarms detected 3867 * during the last beacon period. 3868 */ 3869 static void 3870 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3871 { 3872 #define inc(val, inc, max) \ 3873 if ((val) < (max)) { \ 3874 if ((val) < (max) - (inc)) \ 3875 (val) += (inc); \ 3876 else \ 3877 (val) = (max); \ 3878 needs_update = 1; \ 3879 } 3880 #define dec(val, dec, min) \ 3881 if ((val) > (min)) { \ 3882 if ((val) > (min) + (dec)) \ 3883 (val) -= (dec); \ 3884 else \ 3885 (val) = (min); \ 3886 needs_update = 1; \ 3887 } 3888 3889 const struct iwn_sensitivity_limits *limits = sc->limits; 3890 struct iwn_calib_state *calib = &sc->calib; 3891 uint32_t val, rxena, fa; 3892 uint32_t energy[3], energy_min; 3893 uint8_t noise[3], noise_ref; 3894 int i, needs_update = 0; 3895 3896 /* Check that we've been enabled long enough. */ 3897 if ((rxena = le32toh(stats->general.load)) == 0) 3898 return; 3899 3900 /* Compute number of false alarms since last call for OFDM. */ 3901 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3902 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3903 fa *= 200 * 1024; /* 200TU */ 3904 3905 /* Save counters values for next call. */ 3906 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3907 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3908 3909 if (fa > 50 * rxena) { 3910 /* High false alarm count, decrease sensitivity. */ 3911 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3912 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3913 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3914 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3915 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3916 3917 } else if (fa < 5 * rxena) { 3918 /* Low false alarm count, increase sensitivity. */ 3919 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3920 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3921 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3922 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3923 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3924 } 3925 3926 /* Compute maximum noise among 3 receivers. */ 3927 for (i = 0; i < 3; i++) 3928 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 3929 val = MAX(noise[0], noise[1]); 3930 val = MAX(noise[2], val); 3931 /* Insert it into our samples table. */ 3932 calib->noise_samples[calib->cur_noise_sample] = val; 3933 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3934 3935 /* Compute maximum noise among last 20 samples. */ 3936 noise_ref = calib->noise_samples[0]; 3937 for (i = 1; i < 20; i++) 3938 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 3939 3940 /* Compute maximum energy among 3 receivers. */ 3941 for (i = 0; i < 3; i++) 3942 energy[i] = le32toh(stats->general.energy[i]); 3943 val = MIN(energy[0], energy[1]); 3944 val = MIN(energy[2], val); 3945 /* Insert it into our samples table. */ 3946 calib->energy_samples[calib->cur_energy_sample] = val; 3947 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 3948 3949 /* Compute minimum energy among last 10 samples. */ 3950 energy_min = calib->energy_samples[0]; 3951 for (i = 1; i < 10; i++) 3952 energy_min = MAX(energy_min, calib->energy_samples[i]); 3953 energy_min += 6; 3954 3955 /* Compute number of false alarms since last call for CCK. */ 3956 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 3957 fa += le32toh(stats->cck.fa) - calib->fa_cck; 3958 fa *= 200 * 1024; /* 200TU */ 3959 3960 /* Save counters values for next call. */ 3961 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 3962 calib->fa_cck = le32toh(stats->cck.fa); 3963 3964 if (fa > 50 * rxena) { 3965 /* High false alarm count, decrease sensitivity. */ 3966 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 3967 calib->cck_state = IWN_CCK_STATE_HIFA; 3968 calib->low_fa = 0; 3969 3970 if (calib->cck_x4 > 160) { 3971 calib->noise_ref = noise_ref; 3972 if (calib->energy_cck > 2) 3973 dec(calib->energy_cck, 2, energy_min); 3974 } 3975 if (calib->cck_x4 < 160) { 3976 calib->cck_x4 = 161; 3977 needs_update = 1; 3978 } else 3979 inc(calib->cck_x4, 3, limits->max_cck_x4); 3980 3981 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 3982 3983 } else if (fa < 5 * rxena) { 3984 /* Low false alarm count, increase sensitivity. */ 3985 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 3986 calib->cck_state = IWN_CCK_STATE_LOFA; 3987 calib->low_fa++; 3988 3989 if (calib->cck_state != IWN_CCK_STATE_INIT && 3990 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 3991 calib->low_fa > 100)) { 3992 inc(calib->energy_cck, 2, limits->min_energy_cck); 3993 dec(calib->cck_x4, 3, limits->min_cck_x4); 3994 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 3995 } 3996 } else { 3997 /* Not worth to increase or decrease sensitivity. */ 3998 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 3999 calib->low_fa = 0; 4000 calib->noise_ref = noise_ref; 4001 4002 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4003 /* Previous interval had many false alarms. */ 4004 dec(calib->energy_cck, 8, energy_min); 4005 } 4006 calib->cck_state = IWN_CCK_STATE_INIT; 4007 } 4008 4009 if (needs_update) 4010 (void)iwn_send_sensitivity(sc); 4011 #undef dec 4012 #undef inc 4013 } 4014 4015 static int 4016 iwn_send_sensitivity(struct iwn_softc *sc) 4017 { 4018 struct iwn_calib_state *calib = &sc->calib; 4019 struct iwn_sensitivity_cmd cmd; 4020 4021 memset(&cmd, 0, sizeof cmd); 4022 cmd.which = IWN_SENSITIVITY_WORKTBL; 4023 /* OFDM modulation. */ 4024 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4025 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4026 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4027 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4028 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4029 cmd.energy_ofdm_th = htole16(62); 4030 /* CCK modulation. */ 4031 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4032 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4033 cmd.energy_cck = htole16(calib->energy_cck); 4034 /* Barker modulation: use default values. */ 4035 cmd.corr_barker = htole16(190); 4036 cmd.corr_barker_mrc = htole16(390); 4037 4038 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4039 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4040 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4041 calib->energy_cck)); 4042 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4043 } 4044 4045 /* 4046 * Set STA mode power saving level (between 0 and 5). 4047 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4048 */ 4049 static int 4050 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4051 { 4052 struct iwn_pmgt_cmd cmd; 4053 const struct iwn_pmgt *pmgt; 4054 uint32_t maxp, skip_dtim; 4055 pcireg_t reg; 4056 int i; 4057 4058 /* Select which PS parameters to use. */ 4059 if (dtim <= 2) 4060 pmgt = &iwn_pmgt[0][level]; 4061 else if (dtim <= 10) 4062 pmgt = &iwn_pmgt[1][level]; 4063 else 4064 pmgt = &iwn_pmgt[2][level]; 4065 4066 memset(&cmd, 0, sizeof cmd); 4067 if (level != 0) /* not CAM */ 4068 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4069 if (level == 5) 4070 cmd.flags |= htole16(IWN_PS_FAST_PD); 4071 /* Retrieve PCIe Active State Power Management (ASPM). */ 4072 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4073 sc->sc_cap_off + PCI_PCIE_LCSR); 4074 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4075 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4076 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4077 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4078 4079 if (dtim == 0) { 4080 dtim = 1; 4081 skip_dtim = 0; 4082 } else 4083 skip_dtim = pmgt->skip_dtim; 4084 if (skip_dtim != 0) { 4085 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4086 maxp = pmgt->intval[4]; 4087 if (maxp == (uint32_t)-1) 4088 maxp = dtim * (skip_dtim + 1); 4089 else if (maxp > dtim) 4090 maxp = (maxp / dtim) * dtim; 4091 } else 4092 maxp = dtim; 4093 for (i = 0; i < 5; i++) 4094 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4095 4096 DPRINTF(("setting power saving level to %d\n", level)); 4097 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4098 } 4099 4100 static int 4101 iwn_config(struct iwn_softc *sc) 4102 { 4103 struct iwn_ops *ops = &sc->ops; 4104 struct ieee80211com *ic = &sc->sc_ic; 4105 struct ifnet *ifp = ic->ic_ifp; 4106 struct iwn_bluetooth bluetooth; 4107 uint32_t txmask; 4108 uint16_t rxchain; 4109 int error; 4110 4111 /* Configure valid TX chains for 5000 Series. */ 4112 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4113 txmask = htole32(sc->txchainmask); 4114 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4115 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4116 sizeof txmask, 0); 4117 if (error != 0) { 4118 aprint_error_dev(sc->sc_dev, 4119 "could not configure valid TX chains\n"); 4120 return error; 4121 } 4122 } 4123 4124 /* Configure bluetooth coexistence. */ 4125 memset(&bluetooth, 0, sizeof bluetooth); 4126 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4127 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4128 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4129 DPRINTF(("configuring bluetooth coexistence\n")); 4130 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4131 if (error != 0) { 4132 aprint_error_dev(sc->sc_dev, 4133 "could not configure bluetooth coexistence\n"); 4134 return error; 4135 } 4136 4137 /* Set mode, channel, RX filter and enable RX. */ 4138 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4139 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4140 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4141 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4142 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4143 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4144 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4145 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4146 switch (ic->ic_opmode) { 4147 case IEEE80211_M_STA: 4148 sc->rxon.mode = IWN_MODE_STA; 4149 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4150 break; 4151 case IEEE80211_M_MONITOR: 4152 sc->rxon.mode = IWN_MODE_MONITOR; 4153 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4154 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4155 break; 4156 default: 4157 /* Should not get there. */ 4158 break; 4159 } 4160 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4161 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4162 sc->rxon.ht_single_mask = 0xff; 4163 sc->rxon.ht_dual_mask = 0xff; 4164 sc->rxon.ht_triple_mask = 0xff; 4165 rxchain = 4166 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4167 IWN_RXCHAIN_MIMO_COUNT(2) | 4168 IWN_RXCHAIN_IDLE_COUNT(2); 4169 sc->rxon.rxchain = htole16(rxchain); 4170 DPRINTF(("setting configuration\n")); 4171 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4172 if (error != 0) { 4173 aprint_error_dev(sc->sc_dev, 4174 "RXON command failed\n"); 4175 return error; 4176 } 4177 4178 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4179 aprint_error_dev(sc->sc_dev, 4180 "could not add broadcast node\n"); 4181 return error; 4182 } 4183 4184 /* Configuration has changed, set TX power accordingly. */ 4185 if ((error = ops->set_txpower(sc, 0)) != 0) { 4186 aprint_error_dev(sc->sc_dev, 4187 "could not set TX power\n"); 4188 return error; 4189 } 4190 4191 if ((error = iwn_set_critical_temp(sc)) != 0) { 4192 aprint_error_dev(sc->sc_dev, 4193 "could not set critical temperature\n"); 4194 return error; 4195 } 4196 4197 /* Set power saving level to CAM during initialization. */ 4198 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4199 aprint_error_dev(sc->sc_dev, 4200 "could not set power saving level\n"); 4201 return error; 4202 } 4203 return 0; 4204 } 4205 4206 static int 4207 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4208 { 4209 struct ieee80211com *ic = &sc->sc_ic; 4210 struct iwn_scan_hdr *hdr; 4211 struct iwn_cmd_data *tx; 4212 struct iwn_scan_essid *essid; 4213 struct iwn_scan_chan *chan; 4214 struct ieee80211_frame *wh; 4215 struct ieee80211_rateset *rs; 4216 struct ieee80211_channel *c; 4217 uint8_t *buf, *frm; 4218 uint16_t rxchain; 4219 uint8_t txant; 4220 int buflen, error; 4221 4222 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4223 if (buf == NULL) { 4224 aprint_error_dev(sc->sc_dev, 4225 "could not allocate buffer for scan command\n"); 4226 return ENOMEM; 4227 } 4228 hdr = (struct iwn_scan_hdr *)buf; 4229 /* 4230 * Move to the next channel if no frames are received within 10ms 4231 * after sending the probe request. 4232 */ 4233 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4234 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4235 4236 /* Select antennas for scanning. */ 4237 rxchain = 4238 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4239 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4240 IWN_RXCHAIN_DRIVER_FORCE; 4241 if ((flags & IEEE80211_CHAN_5GHZ) && 4242 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4243 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4244 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4245 } else /* Use all available RX antennas. */ 4246 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4247 hdr->rxchain = htole16(rxchain); 4248 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4249 4250 tx = (struct iwn_cmd_data *)(hdr + 1); 4251 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4252 tx->id = sc->broadcast_id; 4253 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4254 4255 if (flags & IEEE80211_CHAN_5GHZ) { 4256 hdr->crc_threshold = 0xffff; 4257 /* Send probe requests at 6Mbps. */ 4258 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4259 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4260 } else { 4261 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4262 /* Send probe requests at 1Mbps. */ 4263 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4264 tx->rflags = IWN_RFLAG_CCK; 4265 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4266 } 4267 /* Use the first valid TX antenna. */ 4268 txant = IWN_LSB(sc->txchainmask); 4269 tx->rflags |= IWN_RFLAG_ANT(txant); 4270 4271 essid = (struct iwn_scan_essid *)(tx + 1); 4272 if (ic->ic_des_esslen != 0) { 4273 essid[0].id = IEEE80211_ELEMID_SSID; 4274 essid[0].len = ic->ic_des_esslen; 4275 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4276 } 4277 /* 4278 * Build a probe request frame. Most of the following code is a 4279 * copy & paste of what is done in net80211. 4280 */ 4281 wh = (struct ieee80211_frame *)(essid + 20); 4282 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4283 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4284 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4285 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4286 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4287 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4288 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4289 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4290 4291 frm = (uint8_t *)(wh + 1); 4292 frm = ieee80211_add_ssid(frm, NULL, 0); 4293 frm = ieee80211_add_rates(frm, rs); 4294 #ifndef IEEE80211_NO_HT 4295 if (ic->ic_flags & IEEE80211_F_HTON) 4296 frm = ieee80211_add_htcaps(frm, ic); 4297 #endif 4298 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4299 frm = ieee80211_add_xrates(frm, rs); 4300 4301 /* Set length of probe request. */ 4302 tx->len = htole16(frm - (uint8_t *)wh); 4303 4304 chan = (struct iwn_scan_chan *)frm; 4305 for (c = &ic->ic_channels[1]; 4306 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4307 if ((c->ic_flags & flags) != flags) 4308 continue; 4309 4310 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4311 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4312 chan->flags = 0; 4313 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4314 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4315 if (ic->ic_des_esslen != 0) 4316 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4317 chan->dsp_gain = 0x6e; 4318 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4319 chan->rf_gain = 0x3b; 4320 chan->active = htole16(24); 4321 chan->passive = htole16(110); 4322 } else { 4323 chan->rf_gain = 0x28; 4324 chan->active = htole16(36); 4325 chan->passive = htole16(120); 4326 } 4327 hdr->nchan++; 4328 chan++; 4329 } 4330 4331 buflen = (uint8_t *)chan - buf; 4332 hdr->len = htole16(buflen); 4333 4334 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4335 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4336 free(buf, M_DEVBUF); 4337 return error; 4338 } 4339 4340 static int 4341 iwn_auth(struct iwn_softc *sc) 4342 { 4343 struct iwn_ops *ops = &sc->ops; 4344 struct ieee80211com *ic = &sc->sc_ic; 4345 struct ieee80211_node *ni = ic->ic_bss; 4346 int error; 4347 4348 /* Update adapter configuration. */ 4349 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4350 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4351 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4352 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4353 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4354 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4355 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4356 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4357 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4358 switch (ic->ic_curmode) { 4359 case IEEE80211_MODE_11A: 4360 sc->rxon.cck_mask = 0; 4361 sc->rxon.ofdm_mask = 0x15; 4362 break; 4363 case IEEE80211_MODE_11B: 4364 sc->rxon.cck_mask = 0x03; 4365 sc->rxon.ofdm_mask = 0; 4366 break; 4367 default: /* Assume 802.11b/g. */ 4368 sc->rxon.cck_mask = 0x0f; 4369 sc->rxon.ofdm_mask = 0x15; 4370 } 4371 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4372 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4373 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4374 if (error != 0) { 4375 aprint_error_dev(sc->sc_dev, 4376 "RXON command failed\n"); 4377 return error; 4378 } 4379 4380 /* Configuration has changed, set TX power accordingly. */ 4381 if ((error = ops->set_txpower(sc, 1)) != 0) { 4382 aprint_error_dev(sc->sc_dev, 4383 "could not set TX power\n"); 4384 return error; 4385 } 4386 /* 4387 * Reconfiguring RXON clears the firmware nodes table so we must 4388 * add the broadcast node again. 4389 */ 4390 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4391 aprint_error_dev(sc->sc_dev, 4392 "could not add broadcast node\n"); 4393 return error; 4394 } 4395 return 0; 4396 } 4397 4398 static int 4399 iwn_run(struct iwn_softc *sc) 4400 { 4401 struct iwn_ops *ops = &sc->ops; 4402 struct ieee80211com *ic = &sc->sc_ic; 4403 struct ieee80211_node *ni = ic->ic_bss; 4404 struct iwn_node_info node; 4405 int error; 4406 4407 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4408 /* Link LED blinks while monitoring. */ 4409 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4410 return 0; 4411 } 4412 if ((error = iwn_set_timing(sc, ni)) != 0) { 4413 aprint_error_dev(sc->sc_dev, 4414 "could not set timing\n"); 4415 return error; 4416 } 4417 4418 /* Update adapter configuration. */ 4419 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4420 /* Short preamble and slot time are negotiated when associating. */ 4421 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4422 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4423 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4424 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4425 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4426 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4427 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4428 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4429 if (error != 0) { 4430 aprint_error_dev(sc->sc_dev, 4431 "could not update configuration\n"); 4432 return error; 4433 } 4434 4435 /* Configuration has changed, set TX power accordingly. */ 4436 if ((error = ops->set_txpower(sc, 1)) != 0) { 4437 aprint_error_dev(sc->sc_dev, 4438 "could not set TX power\n"); 4439 return error; 4440 } 4441 4442 /* Fake a join to initialize the TX rate. */ 4443 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4444 iwn_newassoc(ni, 1); 4445 4446 /* Add BSS node. */ 4447 memset(&node, 0, sizeof node); 4448 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4449 node.id = IWN_ID_BSS; 4450 #ifdef notyet 4451 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4452 IWN_AMDPU_DENSITY(5)); /* 2us */ 4453 #endif 4454 DPRINTF(("adding BSS node\n")); 4455 error = ops->add_node(sc, &node, 1); 4456 if (error != 0) { 4457 aprint_error_dev(sc->sc_dev, 4458 "could not add BSS node\n"); 4459 return error; 4460 } 4461 DPRINTF(("setting link quality for node %d\n", node.id)); 4462 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4463 aprint_error_dev(sc->sc_dev, 4464 "could not setup link quality for node %d\n", node.id); 4465 return error; 4466 } 4467 4468 if ((error = iwn_init_sensitivity(sc)) != 0) { 4469 aprint_error_dev(sc->sc_dev, 4470 "could not set sensitivity\n"); 4471 return error; 4472 } 4473 /* Start periodic calibration timer. */ 4474 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4475 sc->calib_cnt = 0; 4476 callout_schedule(&sc->calib_to, hz/2); 4477 4478 /* Link LED always on while associated. */ 4479 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4480 return 0; 4481 } 4482 4483 #ifdef IWN_HWCRYPTO 4484 /* 4485 * We support CCMP hardware encryption/decryption of unicast frames only. 4486 * HW support for TKIP really sucks. We should let TKIP die anyway. 4487 */ 4488 static int 4489 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4490 struct ieee80211_key *k) 4491 { 4492 struct iwn_softc *sc = ic->ic_softc; 4493 struct iwn_ops *ops = &sc->ops; 4494 struct iwn_node *wn = (void *)ni; 4495 struct iwn_node_info node; 4496 uint16_t kflags; 4497 4498 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4499 k->k_cipher != IEEE80211_CIPHER_CCMP) 4500 return ieee80211_set_key(ic, ni, k); 4501 4502 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4503 if (k->k_flags & IEEE80211_KEY_GROUP) 4504 kflags |= IWN_KFLAG_GROUP; 4505 4506 memset(&node, 0, sizeof node); 4507 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4508 sc->broadcast_id : wn->id; 4509 node.control = IWN_NODE_UPDATE; 4510 node.flags = IWN_FLAG_SET_KEY; 4511 node.kflags = htole16(kflags); 4512 node.kid = k->k_id; 4513 memcpy(node.key, k->k_key, k->k_len); 4514 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4515 return ops->add_node(sc, &node, 1); 4516 } 4517 4518 static void 4519 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4520 struct ieee80211_key *k) 4521 { 4522 struct iwn_softc *sc = ic->ic_softc; 4523 struct iwn_ops *ops = &sc->ops; 4524 struct iwn_node *wn = (void *)ni; 4525 struct iwn_node_info node; 4526 4527 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4528 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4529 /* See comment about other ciphers above. */ 4530 ieee80211_delete_key(ic, ni, k); 4531 return; 4532 } 4533 if (ic->ic_state != IEEE80211_S_RUN) 4534 return; /* Nothing to do. */ 4535 memset(&node, 0, sizeof node); 4536 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4537 sc->broadcast_id : wn->id; 4538 node.control = IWN_NODE_UPDATE; 4539 node.flags = IWN_FLAG_SET_KEY; 4540 node.kflags = htole16(IWN_KFLAG_INVALID); 4541 node.kid = 0xff; 4542 DPRINTF(("delete keys for node %d\n", node.id)); 4543 (void)ops->add_node(sc, &node, 1); 4544 } 4545 #endif 4546 4547 /* XXX Added for NetBSD (copied from rev 1.39). */ 4548 4549 static int 4550 iwn_wme_update(struct ieee80211com *ic) 4551 { 4552 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4553 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4554 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4555 const struct wmeParams *wmep; 4556 struct iwn_edca_params cmd; 4557 int ac; 4558 4559 /* don't override default WME values if WME is not actually enabled */ 4560 if (!(ic->ic_flags & IEEE80211_F_WME)) 4561 return 0; 4562 cmd.flags = 0; 4563 for (ac = 0; ac < WME_NUM_AC; ac++) { 4564 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4565 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4566 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4567 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4568 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4569 4570 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4571 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4572 cmd.ac[ac].cwmin, 4573 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4574 } 4575 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4576 #undef IWN_USEC 4577 #undef IWN_EXP2 4578 } 4579 4580 #ifndef IEEE80211_NO_HT 4581 /* 4582 * This function is called by upper layer when an ADDBA request is received 4583 * from another STA and before the ADDBA response is sent. 4584 */ 4585 static int 4586 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4587 uint8_t tid) 4588 { 4589 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4590 struct iwn_softc *sc = ic->ic_softc; 4591 struct iwn_ops *ops = &sc->ops; 4592 struct iwn_node *wn = (void *)ni; 4593 struct iwn_node_info node; 4594 4595 memset(&node, 0, sizeof node); 4596 node.id = wn->id; 4597 node.control = IWN_NODE_UPDATE; 4598 node.flags = IWN_FLAG_SET_ADDBA; 4599 node.addba_tid = tid; 4600 node.addba_ssn = htole16(ba->ba_winstart); 4601 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4602 ba->ba_winstart)); 4603 return ops->add_node(sc, &node, 1); 4604 } 4605 4606 /* 4607 * This function is called by upper layer on teardown of an HT-immediate 4608 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4609 */ 4610 static void 4611 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4612 uint8_t tid) 4613 { 4614 struct iwn_softc *sc = ic->ic_softc; 4615 struct iwn_ops *ops = &sc->ops; 4616 struct iwn_node *wn = (void *)ni; 4617 struct iwn_node_info node; 4618 4619 memset(&node, 0, sizeof node); 4620 node.id = wn->id; 4621 node.control = IWN_NODE_UPDATE; 4622 node.flags = IWN_FLAG_SET_DELBA; 4623 node.delba_tid = tid; 4624 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4625 (void)ops->add_node(sc, &node, 1); 4626 } 4627 4628 /* 4629 * This function is called by upper layer when an ADDBA response is received 4630 * from another STA. 4631 */ 4632 static int 4633 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4634 uint8_t tid) 4635 { 4636 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4637 struct iwn_softc *sc = ic->ic_softc; 4638 struct iwn_ops *ops = &sc->ops; 4639 struct iwn_node *wn = (void *)ni; 4640 struct iwn_node_info node; 4641 int error; 4642 4643 /* Enable TX for the specified RA/TID. */ 4644 wn->disable_tid &= ~(1 << tid); 4645 memset(&node, 0, sizeof node); 4646 node.id = wn->id; 4647 node.control = IWN_NODE_UPDATE; 4648 node.flags = IWN_FLAG_SET_DISABLE_TID; 4649 node.disable_tid = htole16(wn->disable_tid); 4650 error = ops->add_node(sc, &node, 1); 4651 if (error != 0) 4652 return error; 4653 4654 if ((error = iwn_nic_lock(sc)) != 0) 4655 return error; 4656 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4657 iwn_nic_unlock(sc); 4658 return 0; 4659 } 4660 4661 static void 4662 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4663 uint8_t tid) 4664 { 4665 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4666 struct iwn_softc *sc = ic->ic_softc; 4667 struct iwn_ops *ops = &sc->ops; 4668 4669 if (iwn_nic_lock(sc) != 0) 4670 return; 4671 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4672 iwn_nic_unlock(sc); 4673 } 4674 4675 static void 4676 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4677 uint8_t tid, uint16_t ssn) 4678 { 4679 struct iwn_node *wn = (void *)ni; 4680 int qid = 7 + tid; 4681 4682 /* Stop TX scheduler while we're changing its configuration. */ 4683 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4684 IWN4965_TXQ_STATUS_CHGACT); 4685 4686 /* Assign RA/TID translation to the queue. */ 4687 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4688 wn->id << 4 | tid); 4689 4690 /* Enable chain-building mode for the queue. */ 4691 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4692 4693 /* Set starting sequence number from the ADDBA request. */ 4694 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4695 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4696 4697 /* Set scheduler window size. */ 4698 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4699 IWN_SCHED_WINSZ); 4700 /* Set scheduler frame limit. */ 4701 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4702 IWN_SCHED_LIMIT << 16); 4703 4704 /* Enable interrupts for the queue. */ 4705 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4706 4707 /* Mark the queue as active. */ 4708 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4709 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4710 iwn_tid2fifo[tid] << 1); 4711 } 4712 4713 static void 4714 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4715 { 4716 int qid = 7 + tid; 4717 4718 /* Stop TX scheduler while we're changing its configuration. */ 4719 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4720 IWN4965_TXQ_STATUS_CHGACT); 4721 4722 /* Set starting sequence number from the ADDBA request. */ 4723 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4724 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4725 4726 /* Disable interrupts for the queue. */ 4727 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4728 4729 /* Mark the queue as inactive. */ 4730 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4731 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4732 } 4733 4734 static void 4735 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4736 uint8_t tid, uint16_t ssn) 4737 { 4738 struct iwn_node *wn = (void *)ni; 4739 int qid = 10 + tid; 4740 4741 /* Stop TX scheduler while we're changing its configuration. */ 4742 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4743 IWN5000_TXQ_STATUS_CHGACT); 4744 4745 /* Assign RA/TID translation to the queue. */ 4746 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4747 wn->id << 4 | tid); 4748 4749 /* Enable chain-building mode for the queue. */ 4750 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4751 4752 /* Enable aggregation for the queue. */ 4753 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4754 4755 /* Set starting sequence number from the ADDBA request. */ 4756 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4757 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4758 4759 /* Set scheduler window size and frame limit. */ 4760 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4761 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4762 4763 /* Enable interrupts for the queue. */ 4764 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4765 4766 /* Mark the queue as active. */ 4767 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4768 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4769 } 4770 4771 static void 4772 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4773 { 4774 int qid = 10 + tid; 4775 4776 /* Stop TX scheduler while we're changing its configuration. */ 4777 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4778 IWN5000_TXQ_STATUS_CHGACT); 4779 4780 /* Disable aggregation for the queue. */ 4781 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4782 4783 /* Set starting sequence number from the ADDBA request. */ 4784 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4785 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4786 4787 /* Disable interrupts for the queue. */ 4788 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4789 4790 /* Mark the queue as inactive. */ 4791 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4792 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4793 } 4794 #endif /* !IEEE80211_NO_HT */ 4795 4796 /* 4797 * Query calibration tables from the initialization firmware. We do this 4798 * only once at first boot. Called from a process context. 4799 */ 4800 static int 4801 iwn5000_query_calibration(struct iwn_softc *sc) 4802 { 4803 struct iwn5000_calib_config cmd; 4804 int error; 4805 4806 memset(&cmd, 0, sizeof cmd); 4807 cmd.ucode.once.enable = 0xffffffff; 4808 cmd.ucode.once.start = 0xffffffff; 4809 cmd.ucode.once.send = 0xffffffff; 4810 cmd.ucode.flags = 0xffffffff; 4811 DPRINTF(("sending calibration query\n")); 4812 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4813 if (error != 0) 4814 return error; 4815 4816 /* Wait at most two seconds for calibration to complete. */ 4817 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4818 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4819 return error; 4820 } 4821 4822 /* 4823 * Send calibration results to the runtime firmware. These results were 4824 * obtained on first boot from the initialization firmware. 4825 */ 4826 static int 4827 iwn5000_send_calibration(struct iwn_softc *sc) 4828 { 4829 int idx, error; 4830 4831 for (idx = 0; idx < 5; idx++) { 4832 if (sc->calibcmd[idx].buf == NULL) 4833 continue; /* No results available. */ 4834 DPRINTF(("send calibration result idx=%d len=%d\n", 4835 idx, sc->calibcmd[idx].len)); 4836 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4837 sc->calibcmd[idx].len, 0); 4838 if (error != 0) { 4839 aprint_error_dev(sc->sc_dev, 4840 "could not send calibration result\n"); 4841 return error; 4842 } 4843 } 4844 return 0; 4845 } 4846 4847 static int 4848 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4849 { 4850 struct iwn5000_wimax_coex wimax; 4851 4852 #ifdef notyet 4853 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4854 /* Enable WiMAX coexistence for combo adapters. */ 4855 wimax.flags = 4856 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4857 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4858 IWN_WIMAX_COEX_STA_TABLE_VALID | 4859 IWN_WIMAX_COEX_ENABLE; 4860 memcpy(wimax.events, iwn6050_wimax_events, 4861 sizeof iwn6050_wimax_events); 4862 } else 4863 #endif 4864 { 4865 /* Disable WiMAX coexistence. */ 4866 wimax.flags = 0; 4867 memset(wimax.events, 0, sizeof wimax.events); 4868 } 4869 DPRINTF(("Configuring WiMAX coexistence\n")); 4870 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4871 } 4872 4873 /* 4874 * This function is called after the runtime firmware notifies us of its 4875 * readiness (called in a process context). 4876 */ 4877 static int 4878 iwn4965_post_alive(struct iwn_softc *sc) 4879 { 4880 int error, qid; 4881 4882 if ((error = iwn_nic_lock(sc)) != 0) 4883 return error; 4884 4885 /* Clear TX scheduler state in SRAM. */ 4886 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4887 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4888 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 4889 4890 /* Set physical address of TX scheduler rings (1KB aligned). */ 4891 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4892 4893 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4894 4895 /* Disable chain mode for all our 16 queues. */ 4896 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4897 4898 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4899 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4900 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4901 4902 /* Set scheduler window size. */ 4903 iwn_mem_write(sc, sc->sched_base + 4904 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4905 /* Set scheduler frame limit. */ 4906 iwn_mem_write(sc, sc->sched_base + 4907 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4908 IWN_SCHED_LIMIT << 16); 4909 } 4910 4911 /* Enable interrupts for all our 16 queues. */ 4912 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4913 /* Identify TX FIFO rings (0-7). */ 4914 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4915 4916 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4917 for (qid = 0; qid < 7; qid++) { 4918 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4919 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4920 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4921 } 4922 iwn_nic_unlock(sc); 4923 return 0; 4924 } 4925 4926 /* 4927 * This function is called after the initialization or runtime firmware 4928 * notifies us of its readiness (called in a process context). 4929 */ 4930 static int 4931 iwn5000_post_alive(struct iwn_softc *sc) 4932 { 4933 int error, qid; 4934 4935 /* Switch to using ICT interrupt mode. */ 4936 iwn5000_ict_reset(sc); 4937 4938 if ((error = iwn_nic_lock(sc)) != 0) 4939 return error; 4940 4941 /* Clear TX scheduler state in SRAM. */ 4942 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4943 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 4944 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 4945 4946 /* Set physical address of TX scheduler rings (1KB aligned). */ 4947 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4948 4949 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4950 4951 /* Enable chain mode for all queues, except command queue. */ 4952 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 4953 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 4954 4955 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 4956 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 4957 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4958 4959 iwn_mem_write(sc, sc->sched_base + 4960 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 4961 /* Set scheduler window size and frame limit. */ 4962 iwn_mem_write(sc, sc->sched_base + 4963 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4964 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4965 } 4966 4967 /* Enable interrupts for all our 20 queues. */ 4968 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 4969 /* Identify TX FIFO rings (0-7). */ 4970 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 4971 4972 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4973 for (qid = 0; qid < 7; qid++) { 4974 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 4975 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4976 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 4977 } 4978 iwn_nic_unlock(sc); 4979 4980 /* Configure WiMAX coexistence for combo adapters. */ 4981 error = iwn5000_send_wimax_coex(sc); 4982 if (error != 0) { 4983 aprint_error_dev(sc->sc_dev, 4984 "could not configure WiMAX coexistence\n"); 4985 return error; 4986 } 4987 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 4988 struct iwn5000_phy_calib_crystal cmd; 4989 4990 /* Perform crystal calibration. */ 4991 memset(&cmd, 0, sizeof cmd); 4992 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 4993 cmd.ngroups = 1; 4994 cmd.isvalid = 1; 4995 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 4996 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 4997 DPRINTF(("sending crystal calibration %d, %d\n", 4998 cmd.cap_pin[0], cmd.cap_pin[1])); 4999 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5000 if (error != 0) { 5001 aprint_error_dev(sc->sc_dev, 5002 "crystal calibration failed\n"); 5003 return error; 5004 } 5005 } 5006 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5007 /* Query calibration from the initialization firmware. */ 5008 if ((error = iwn5000_query_calibration(sc)) != 0) { 5009 aprint_error_dev(sc->sc_dev, 5010 "could not query calibration\n"); 5011 return error; 5012 } 5013 /* 5014 * We have the calibration results now, reboot with the 5015 * runtime firmware (call ourselves recursively!) 5016 */ 5017 iwn_hw_stop(sc); 5018 error = iwn_hw_init(sc); 5019 } else { 5020 /* Send calibration results to runtime firmware. */ 5021 error = iwn5000_send_calibration(sc); 5022 } 5023 return error; 5024 } 5025 5026 /* 5027 * The firmware boot code is small and is intended to be copied directly into 5028 * the NIC internal memory (no DMA transfer). 5029 */ 5030 static int 5031 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5032 { 5033 int error, ntries; 5034 5035 size /= sizeof (uint32_t); 5036 5037 if ((error = iwn_nic_lock(sc)) != 0) 5038 return error; 5039 5040 /* Copy microcode image into NIC memory. */ 5041 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5042 (const uint32_t *)ucode, size); 5043 5044 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5045 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5046 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5047 5048 /* Start boot load now. */ 5049 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5050 5051 /* Wait for transfer to complete. */ 5052 for (ntries = 0; ntries < 1000; ntries++) { 5053 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5054 IWN_BSM_WR_CTRL_START)) 5055 break; 5056 DELAY(10); 5057 } 5058 if (ntries == 1000) { 5059 aprint_error_dev(sc->sc_dev, 5060 "could not load boot firmware\n"); 5061 iwn_nic_unlock(sc); 5062 return ETIMEDOUT; 5063 } 5064 5065 /* Enable boot after power up. */ 5066 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5067 5068 iwn_nic_unlock(sc); 5069 return 0; 5070 } 5071 5072 static int 5073 iwn4965_load_firmware(struct iwn_softc *sc) 5074 { 5075 struct iwn_fw_info *fw = &sc->fw; 5076 struct iwn_dma_info *dma = &sc->fw_dma; 5077 int error; 5078 5079 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5080 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5081 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5082 BUS_DMASYNC_PREWRITE); 5083 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5084 fw->init.text, fw->init.textsz); 5085 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5086 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5087 5088 /* Tell adapter where to find initialization sections. */ 5089 if ((error = iwn_nic_lock(sc)) != 0) 5090 return error; 5091 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5092 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5093 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5094 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5095 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5096 iwn_nic_unlock(sc); 5097 5098 /* Load firmware boot code. */ 5099 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5100 if (error != 0) { 5101 aprint_error_dev(sc->sc_dev, 5102 "could not load boot firmware\n"); 5103 return error; 5104 } 5105 /* Now press "execute". */ 5106 IWN_WRITE(sc, IWN_RESET, 0); 5107 5108 /* Wait at most one second for first alive notification. */ 5109 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5110 aprint_error_dev(sc->sc_dev, 5111 "timeout waiting for adapter to initialize\n"); 5112 return error; 5113 } 5114 5115 /* Retrieve current temperature for initial TX power calibration. */ 5116 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5117 sc->temp = iwn4965_get_temperature(sc); 5118 5119 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5120 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5121 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5122 BUS_DMASYNC_PREWRITE); 5123 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5124 fw->main.text, fw->main.textsz); 5125 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5126 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5127 5128 /* Tell adapter where to find runtime sections. */ 5129 if ((error = iwn_nic_lock(sc)) != 0) 5130 return error; 5131 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5132 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5133 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5134 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5135 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5136 IWN_FW_UPDATED | fw->main.textsz); 5137 iwn_nic_unlock(sc); 5138 5139 return 0; 5140 } 5141 5142 static int 5143 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5144 const uint8_t *section, int size) 5145 { 5146 struct iwn_dma_info *dma = &sc->fw_dma; 5147 int error; 5148 5149 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5150 memcpy(dma->vaddr, section, size); 5151 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5152 5153 if ((error = iwn_nic_lock(sc)) != 0) 5154 return error; 5155 5156 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5157 IWN_FH_TX_CONFIG_DMA_PAUSE); 5158 5159 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5160 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5161 IWN_LOADDR(dma->paddr)); 5162 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5163 IWN_HIADDR(dma->paddr) << 28 | size); 5164 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5165 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5166 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5167 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5168 5169 /* Kick Flow Handler to start DMA transfer. */ 5170 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5171 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5172 5173 iwn_nic_unlock(sc); 5174 5175 /* Wait at most five seconds for FH DMA transfer to complete. */ 5176 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5177 } 5178 5179 static int 5180 iwn5000_load_firmware(struct iwn_softc *sc) 5181 { 5182 struct iwn_fw_part *fw; 5183 int error; 5184 5185 /* Load the initialization firmware on first boot only. */ 5186 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5187 &sc->fw.main : &sc->fw.init; 5188 5189 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5190 fw->text, fw->textsz); 5191 if (error != 0) { 5192 aprint_error_dev(sc->sc_dev, 5193 "could not load firmware %s section\n", ".text"); 5194 return error; 5195 } 5196 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5197 fw->data, fw->datasz); 5198 if (error != 0) { 5199 aprint_error_dev(sc->sc_dev, 5200 "could not load firmware %s section\n", ".data"); 5201 return error; 5202 } 5203 5204 /* Now press "execute". */ 5205 IWN_WRITE(sc, IWN_RESET, 0); 5206 return 0; 5207 } 5208 5209 /* 5210 * Extract text and data sections from a legacy firmware image. 5211 */ 5212 static int 5213 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5214 { 5215 const uint32_t *ptr; 5216 size_t hdrlen = 24; 5217 uint32_t rev; 5218 5219 ptr = (const uint32_t *)fw->data; 5220 rev = le32toh(*ptr++); 5221 5222 /* Check firmware API version. */ 5223 if (IWN_FW_API(rev) <= 1) { 5224 aprint_error_dev(sc->sc_dev, 5225 "bad firmware, need API version >=2\n"); 5226 return EINVAL; 5227 } 5228 if (IWN_FW_API(rev) >= 3) { 5229 /* Skip build number (version 2 header). */ 5230 hdrlen += 4; 5231 ptr++; 5232 } 5233 if (fw->size < hdrlen) { 5234 aprint_error_dev(sc->sc_dev, 5235 "firmware too short: %zd bytes\n", fw->size); 5236 return EINVAL; 5237 } 5238 fw->main.textsz = le32toh(*ptr++); 5239 fw->main.datasz = le32toh(*ptr++); 5240 fw->init.textsz = le32toh(*ptr++); 5241 fw->init.datasz = le32toh(*ptr++); 5242 fw->boot.textsz = le32toh(*ptr++); 5243 5244 /* Check that all firmware sections fit. */ 5245 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5246 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5247 aprint_error_dev(sc->sc_dev, 5248 "firmware too short: %zd bytes\n", fw->size); 5249 return EINVAL; 5250 } 5251 5252 /* Get pointers to firmware sections. */ 5253 fw->main.text = (const uint8_t *)ptr; 5254 fw->main.data = fw->main.text + fw->main.textsz; 5255 fw->init.text = fw->main.data + fw->main.datasz; 5256 fw->init.data = fw->init.text + fw->init.textsz; 5257 fw->boot.text = fw->init.data + fw->init.datasz; 5258 return 0; 5259 } 5260 5261 /* 5262 * Extract text and data sections from a TLV firmware image. 5263 */ 5264 static int 5265 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5266 uint16_t alt) 5267 { 5268 const struct iwn_fw_tlv_hdr *hdr; 5269 const struct iwn_fw_tlv *tlv; 5270 const uint8_t *ptr, *end; 5271 uint64_t altmask; 5272 uint32_t len; 5273 5274 if (fw->size < sizeof (*hdr)) { 5275 aprint_error_dev(sc->sc_dev, 5276 "firmware too short: %zd bytes\n", fw->size); 5277 return EINVAL; 5278 } 5279 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5280 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5281 aprint_error_dev(sc->sc_dev, 5282 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5283 return EINVAL; 5284 } 5285 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5286 le32toh(hdr->build))); 5287 5288 /* 5289 * Select the closest supported alternative that is less than 5290 * or equal to the specified one. 5291 */ 5292 altmask = le64toh(hdr->altmask); 5293 while (alt > 0 && !(altmask & (1ULL << alt))) 5294 alt--; /* Downgrade. */ 5295 DPRINTF(("using alternative %d\n", alt)); 5296 5297 ptr = (const uint8_t *)(hdr + 1); 5298 end = (const uint8_t *)(fw->data + fw->size); 5299 5300 /* Parse type-length-value fields. */ 5301 while (ptr + sizeof (*tlv) <= end) { 5302 tlv = (const struct iwn_fw_tlv *)ptr; 5303 len = le32toh(tlv->len); 5304 5305 ptr += sizeof (*tlv); 5306 if (ptr + len > end) { 5307 aprint_error_dev(sc->sc_dev, 5308 "firmware too short: %zd bytes\n", fw->size); 5309 return EINVAL; 5310 } 5311 /* Skip other alternatives. */ 5312 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5313 goto next; 5314 5315 switch (le16toh(tlv->type)) { 5316 case IWN_FW_TLV_MAIN_TEXT: 5317 fw->main.text = ptr; 5318 fw->main.textsz = len; 5319 break; 5320 case IWN_FW_TLV_MAIN_DATA: 5321 fw->main.data = ptr; 5322 fw->main.datasz = len; 5323 break; 5324 case IWN_FW_TLV_INIT_TEXT: 5325 fw->init.text = ptr; 5326 fw->init.textsz = len; 5327 break; 5328 case IWN_FW_TLV_INIT_DATA: 5329 fw->init.data = ptr; 5330 fw->init.datasz = len; 5331 break; 5332 case IWN_FW_TLV_BOOT_TEXT: 5333 fw->boot.text = ptr; 5334 fw->boot.textsz = len; 5335 break; 5336 default: 5337 DPRINTF(("TLV type %d not handled\n", 5338 le16toh(tlv->type))); 5339 break; 5340 } 5341 next: /* TLV fields are 32-bit aligned. */ 5342 ptr += (len + 3) & ~3; 5343 } 5344 return 0; 5345 } 5346 5347 static int 5348 iwn_read_firmware(struct iwn_softc *sc) 5349 { 5350 struct iwn_fw_info *fw = &sc->fw; 5351 firmware_handle_t fwh; 5352 int error; 5353 5354 /* Initialize for error returns */ 5355 fw->data = NULL; 5356 fw->size = 0; 5357 5358 /* Open firmware image. */ 5359 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5360 aprint_error_dev(sc->sc_dev, 5361 "could not get firmware handle %s\n", sc->fwname); 5362 return error; 5363 } 5364 fw->size = firmware_get_size(fwh); 5365 if (fw->size < sizeof (uint32_t)) { 5366 aprint_error_dev(sc->sc_dev, 5367 "firmware too short: %zd bytes\n", fw->size); 5368 firmware_close(fwh); 5369 return EINVAL; 5370 } 5371 5372 /* Read the firmware. */ 5373 fw->data = firmware_malloc(fw->size); 5374 if (fw->data == NULL) { 5375 aprint_error_dev(sc->sc_dev, 5376 "not enough memory to stock firmware %s\n", sc->fwname); 5377 firmware_close(fwh); 5378 return ENOMEM; 5379 } 5380 error = firmware_read(fwh, 0, fw->data, fw->size); 5381 firmware_close(fwh); 5382 if (error != 0) { 5383 aprint_error_dev(sc->sc_dev, 5384 "could not read firmware %s\n", sc->fwname); 5385 goto out; 5386 } 5387 5388 /* Retrieve text and data sections. */ 5389 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5390 error = iwn_read_firmware_leg(sc, fw); 5391 else 5392 error = iwn_read_firmware_tlv(sc, fw, 1); 5393 if (error != 0) { 5394 aprint_error_dev(sc->sc_dev, 5395 "could not read firmware sections\n"); 5396 goto out; 5397 } 5398 5399 /* Make sure text and data sections fit in hardware memory. */ 5400 if (fw->main.textsz > sc->fw_text_maxsz || 5401 fw->main.datasz > sc->fw_data_maxsz || 5402 fw->init.textsz > sc->fw_text_maxsz || 5403 fw->init.datasz > sc->fw_data_maxsz || 5404 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5405 (fw->boot.textsz & 3) != 0) { 5406 aprint_error_dev(sc->sc_dev, 5407 "firmware sections too large\n"); 5408 goto out; 5409 } 5410 5411 /* We can proceed with loading the firmware. */ 5412 return 0; 5413 out: 5414 firmware_free(fw->data, fw->size); 5415 fw->data = NULL; 5416 fw->size = 0; 5417 return error ? error : EINVAL; 5418 } 5419 5420 static int 5421 iwn_clock_wait(struct iwn_softc *sc) 5422 { 5423 int ntries; 5424 5425 /* Set "initialization complete" bit. */ 5426 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5427 5428 /* Wait for clock stabilization. */ 5429 for (ntries = 0; ntries < 2500; ntries++) { 5430 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5431 return 0; 5432 DELAY(10); 5433 } 5434 aprint_error_dev(sc->sc_dev, 5435 "timeout waiting for clock stabilization\n"); 5436 return ETIMEDOUT; 5437 } 5438 5439 static int 5440 iwn_apm_init(struct iwn_softc *sc) 5441 { 5442 pcireg_t reg; 5443 int error; 5444 5445 /* Disable L0s exit timer (NMI bug workaround). */ 5446 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5447 /* Don't wait for ICH L0s (ICH bug workaround). */ 5448 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5449 5450 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5451 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5452 5453 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5454 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5455 5456 /* Retrieve PCIe Active State Power Management (ASPM). */ 5457 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5458 sc->sc_cap_off + PCI_PCIE_LCSR); 5459 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5460 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5461 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5462 else 5463 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5464 5465 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5466 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5467 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5468 5469 /* Wait for clock stabilization before accessing prph. */ 5470 if ((error = iwn_clock_wait(sc)) != 0) 5471 return error; 5472 5473 if ((error = iwn_nic_lock(sc)) != 0) 5474 return error; 5475 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5476 /* Enable DMA and BSM (Bootstrap State Machine). */ 5477 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5478 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5479 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5480 } else { 5481 /* Enable DMA. */ 5482 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5483 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5484 } 5485 DELAY(20); 5486 /* Disable L1-Active. */ 5487 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5488 iwn_nic_unlock(sc); 5489 5490 return 0; 5491 } 5492 5493 static void 5494 iwn_apm_stop_master(struct iwn_softc *sc) 5495 { 5496 int ntries; 5497 5498 /* Stop busmaster DMA activity. */ 5499 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5500 for (ntries = 0; ntries < 100; ntries++) { 5501 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5502 return; 5503 DELAY(10); 5504 } 5505 aprint_error_dev(sc->sc_dev, 5506 "timeout waiting for master\n"); 5507 } 5508 5509 static void 5510 iwn_apm_stop(struct iwn_softc *sc) 5511 { 5512 iwn_apm_stop_master(sc); 5513 5514 /* Reset the entire device. */ 5515 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5516 DELAY(10); 5517 /* Clear "initialization complete" bit. */ 5518 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5519 } 5520 5521 static int 5522 iwn4965_nic_config(struct iwn_softc *sc) 5523 { 5524 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5525 /* 5526 * I don't believe this to be correct but this is what the 5527 * vendor driver is doing. Probably the bits should not be 5528 * shifted in IWN_RFCFG_*. 5529 */ 5530 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5531 IWN_RFCFG_TYPE(sc->rfcfg) | 5532 IWN_RFCFG_STEP(sc->rfcfg) | 5533 IWN_RFCFG_DASH(sc->rfcfg)); 5534 } 5535 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5536 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5537 return 0; 5538 } 5539 5540 static int 5541 iwn5000_nic_config(struct iwn_softc *sc) 5542 { 5543 uint32_t tmp; 5544 int error; 5545 5546 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5547 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5548 IWN_RFCFG_TYPE(sc->rfcfg) | 5549 IWN_RFCFG_STEP(sc->rfcfg) | 5550 IWN_RFCFG_DASH(sc->rfcfg)); 5551 } 5552 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5553 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5554 5555 if ((error = iwn_nic_lock(sc)) != 0) 5556 return error; 5557 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5558 5559 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5560 /* 5561 * Select first Switching Voltage Regulator (1.32V) to 5562 * solve a stability issue related to noisy DC2DC line 5563 * in the silicon of 1000 Series. 5564 */ 5565 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5566 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5567 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5568 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5569 } 5570 iwn_nic_unlock(sc); 5571 5572 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5573 /* Use internal power amplifier only. */ 5574 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5575 } 5576 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 5577 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 5578 /* Indicate that ROM calibration version is >=6. */ 5579 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5580 } 5581 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 5582 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 5583 return 0; 5584 } 5585 5586 /* 5587 * Take NIC ownership over Intel Active Management Technology (AMT). 5588 */ 5589 static int 5590 iwn_hw_prepare(struct iwn_softc *sc) 5591 { 5592 int ntries; 5593 5594 /* Check if hardware is ready. */ 5595 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5596 for (ntries = 0; ntries < 5; ntries++) { 5597 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5598 IWN_HW_IF_CONFIG_NIC_READY) 5599 return 0; 5600 DELAY(10); 5601 } 5602 5603 /* Hardware not ready, force into ready state. */ 5604 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5605 for (ntries = 0; ntries < 15000; ntries++) { 5606 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5607 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5608 break; 5609 DELAY(10); 5610 } 5611 if (ntries == 15000) 5612 return ETIMEDOUT; 5613 5614 /* Hardware should be ready now. */ 5615 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5616 for (ntries = 0; ntries < 5; ntries++) { 5617 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5618 IWN_HW_IF_CONFIG_NIC_READY) 5619 return 0; 5620 DELAY(10); 5621 } 5622 return ETIMEDOUT; 5623 } 5624 5625 static int 5626 iwn_hw_init(struct iwn_softc *sc) 5627 { 5628 struct iwn_ops *ops = &sc->ops; 5629 int error, chnl, qid; 5630 5631 /* Clear pending interrupts. */ 5632 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5633 5634 if ((error = iwn_apm_init(sc)) != 0) { 5635 aprint_error_dev(sc->sc_dev, 5636 "could not power ON adapter\n"); 5637 return error; 5638 } 5639 5640 /* Select VMAIN power source. */ 5641 if ((error = iwn_nic_lock(sc)) != 0) 5642 return error; 5643 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5644 iwn_nic_unlock(sc); 5645 5646 /* Perform adapter-specific initialization. */ 5647 if ((error = ops->nic_config(sc)) != 0) 5648 return error; 5649 5650 /* Initialize RX ring. */ 5651 if ((error = iwn_nic_lock(sc)) != 0) 5652 return error; 5653 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5654 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5655 /* Set physical address of RX ring (256-byte aligned). */ 5656 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5657 /* Set physical address of RX status (16-byte aligned). */ 5658 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5659 /* Enable RX. */ 5660 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5661 IWN_FH_RX_CONFIG_ENA | 5662 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5663 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5664 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5665 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5666 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5667 iwn_nic_unlock(sc); 5668 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5669 5670 if ((error = iwn_nic_lock(sc)) != 0) 5671 return error; 5672 5673 /* Initialize TX scheduler. */ 5674 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5675 5676 /* Set physical address of "keep warm" page (16-byte aligned). */ 5677 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5678 5679 /* Initialize TX rings. */ 5680 for (qid = 0; qid < sc->ntxqs; qid++) { 5681 struct iwn_tx_ring *txq = &sc->txq[qid]; 5682 5683 /* Set physical address of TX ring (256-byte aligned). */ 5684 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5685 txq->desc_dma.paddr >> 8); 5686 } 5687 iwn_nic_unlock(sc); 5688 5689 /* Enable DMA channels. */ 5690 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5691 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5692 IWN_FH_TX_CONFIG_DMA_ENA | 5693 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5694 } 5695 5696 /* Clear "radio off" and "commands blocked" bits. */ 5697 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5698 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5699 5700 /* Clear pending interrupts. */ 5701 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5702 /* Enable interrupt coalescing. */ 5703 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5704 /* Enable interrupts. */ 5705 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5706 5707 /* _Really_ make sure "radio off" bit is cleared! */ 5708 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5709 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5710 5711 /* Enable shadow registers. */ 5712 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 5713 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 5714 5715 if ((error = ops->load_firmware(sc)) != 0) { 5716 aprint_error_dev(sc->sc_dev, 5717 "could not load firmware\n"); 5718 return error; 5719 } 5720 /* Wait at most one second for firmware alive notification. */ 5721 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5722 aprint_error_dev(sc->sc_dev, 5723 "timeout waiting for adapter to initialize\n"); 5724 return error; 5725 } 5726 /* Do post-firmware initialization. */ 5727 return ops->post_alive(sc); 5728 } 5729 5730 static void 5731 iwn_hw_stop(struct iwn_softc *sc) 5732 { 5733 int chnl, qid, ntries; 5734 5735 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5736 5737 /* Disable interrupts. */ 5738 IWN_WRITE(sc, IWN_INT_MASK, 0); 5739 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5740 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5741 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5742 5743 /* Make sure we no longer hold the NIC lock. */ 5744 iwn_nic_unlock(sc); 5745 5746 /* Stop TX scheduler. */ 5747 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5748 5749 /* Stop all DMA channels. */ 5750 if (iwn_nic_lock(sc) == 0) { 5751 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5752 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5753 for (ntries = 0; ntries < 200; ntries++) { 5754 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 5755 IWN_FH_TX_STATUS_IDLE(chnl)) 5756 break; 5757 DELAY(10); 5758 } 5759 } 5760 iwn_nic_unlock(sc); 5761 } 5762 5763 /* Stop RX ring. */ 5764 iwn_reset_rx_ring(sc, &sc->rxq); 5765 5766 /* Reset all TX rings. */ 5767 for (qid = 0; qid < sc->ntxqs; qid++) 5768 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5769 5770 if (iwn_nic_lock(sc) == 0) { 5771 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5772 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5773 iwn_nic_unlock(sc); 5774 } 5775 DELAY(5); 5776 /* Power OFF adapter. */ 5777 iwn_apm_stop(sc); 5778 } 5779 5780 static int 5781 iwn_init(struct ifnet *ifp) 5782 { 5783 struct iwn_softc *sc = ifp->if_softc; 5784 struct ieee80211com *ic = &sc->sc_ic; 5785 int error; 5786 5787 mutex_enter(&sc->sc_mtx); 5788 if (sc->sc_flags & IWN_FLAG_HW_INITED) 5789 goto out; 5790 if ((error = iwn_hw_prepare(sc)) != 0) { 5791 aprint_error_dev(sc->sc_dev, 5792 "hardware not ready\n"); 5793 goto fail; 5794 } 5795 5796 /* Check that the radio is not disabled by hardware switch. */ 5797 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5798 aprint_error_dev(sc->sc_dev, 5799 "radio is disabled by hardware switch\n"); 5800 error = EPERM; /* :-) */ 5801 goto fail; 5802 } 5803 5804 /* Read firmware images from the filesystem. */ 5805 if ((error = iwn_read_firmware(sc)) != 0) { 5806 aprint_error_dev(sc->sc_dev, 5807 "could not read firmware\n"); 5808 goto fail; 5809 } 5810 5811 /* Initialize interrupt mask to default value. */ 5812 sc->int_mask = IWN_INT_MASK_DEF; 5813 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5814 5815 /* Initialize hardware and upload firmware. */ 5816 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 5817 error = iwn_hw_init(sc); 5818 firmware_free(sc->fw.data, sc->fw.size); 5819 sc->fw.data = NULL; 5820 sc->fw.size = 0; 5821 if (error != 0) { 5822 aprint_error_dev(sc->sc_dev, 5823 "could not initialize hardware\n"); 5824 goto fail; 5825 } 5826 5827 /* Configure adapter now that it is ready. */ 5828 if ((error = iwn_config(sc)) != 0) { 5829 aprint_error_dev(sc->sc_dev, 5830 "could not configure device\n"); 5831 goto fail; 5832 } 5833 5834 ifp->if_flags &= ~IFF_OACTIVE; 5835 ifp->if_flags |= IFF_RUNNING; 5836 5837 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5838 ieee80211_begin_scan(ic, 0); 5839 else 5840 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5841 5842 sc->sc_flags |= IWN_FLAG_HW_INITED; 5843 out: 5844 mutex_exit(&sc->sc_mtx); 5845 return 0; 5846 5847 fail: mutex_exit(&sc->sc_mtx); 5848 iwn_stop(ifp, 1); 5849 return error; 5850 } 5851 5852 static void 5853 iwn_stop(struct ifnet *ifp, int disable) 5854 { 5855 struct iwn_softc *sc = ifp->if_softc; 5856 struct ieee80211com *ic = &sc->sc_ic; 5857 5858 if (!disable) 5859 mutex_enter(&sc->sc_mtx); 5860 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 5861 ifp->if_timer = sc->sc_tx_timer = 0; 5862 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5863 5864 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5865 5866 /* Power OFF hardware. */ 5867 iwn_hw_stop(sc); 5868 5869 if (!disable) 5870 mutex_exit(&sc->sc_mtx); 5871 } 5872 5873 /* 5874 * XXX MCLGETI alternative 5875 * 5876 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5877 * as long as there are available free buffers then it uses MEXTMALLOC., 5878 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5879 * The MCLGET4K code is used for testing an alternative mbuf cache. 5880 */ 5881 5882 static struct mbuf * 5883 MCLGETIalt(struct iwn_softc *sc, int how, 5884 struct ifnet *ifp __unused, u_int size) 5885 { 5886 struct mbuf *m; 5887 #ifdef IWN_USE_RBUF 5888 struct iwn_rbuf *rbuf; 5889 #endif 5890 5891 MGETHDR(m, how, MT_DATA); 5892 if (m == NULL) 5893 return NULL; 5894 5895 #ifdef IWN_USE_RBUF 5896 if (sc->rxq.nb_free_entries > 0 && 5897 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 5898 /* Attach buffer to mbuf header. */ 5899 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 5900 m->m_flags |= M_EXT_RW; 5901 } 5902 else { 5903 MEXTMALLOC(m, size, how); 5904 if ((m->m_flags & M_EXT) == 0) { 5905 m_freem(m); 5906 return NULL; 5907 } 5908 } 5909 5910 #else 5911 #ifdef MCLGET4K 5912 if (size == 4096) 5913 MCLGET4K(m, how); 5914 else 5915 panic("size must be 4k"); 5916 #else 5917 MEXTMALLOC(m, size, how); 5918 #endif 5919 if ((m->m_flags & M_EXT) == 0) { 5920 m_freem(m); 5921 return NULL; 5922 } 5923 #endif 5924 5925 return m; 5926 } 5927 5928 #ifdef IWN_USE_RBUF 5929 static struct iwn_rbuf * 5930 iwn_alloc_rbuf(struct iwn_softc *sc) 5931 { 5932 struct iwn_rbuf *rbuf; 5933 mutex_enter(&sc->rxq.freelist_mtx); 5934 5935 rbuf = SLIST_FIRST(&sc->rxq.freelist); 5936 if (rbuf != NULL) { 5937 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 5938 sc->rxq.nb_free_entries --; 5939 } 5940 mutex_exit(&sc->rxq.freelist_mtx); 5941 return rbuf; 5942 } 5943 5944 /* 5945 * This is called automatically by the network stack when the mbuf to which 5946 * our RX buffer is attached is freed. 5947 */ 5948 static void 5949 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 5950 { 5951 struct iwn_rbuf *rbuf = arg; 5952 struct iwn_softc *sc = rbuf->sc; 5953 5954 /* Put the RX buffer back in the free list. */ 5955 mutex_enter(&sc->rxq.freelist_mtx); 5956 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 5957 mutex_exit(&sc->rxq.freelist_mtx); 5958 5959 sc->rxq.nb_free_entries ++; 5960 if (__predict_true(m != NULL)) 5961 pool_cache_put(mb_cache, m); 5962 } 5963 5964 static int 5965 iwn_alloc_rpool(struct iwn_softc *sc) 5966 { 5967 struct iwn_rx_ring *ring = &sc->rxq; 5968 struct iwn_rbuf *rbuf; 5969 int i, error; 5970 5971 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 5972 5973 /* Allocate a big chunk of DMA'able memory... */ 5974 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 5975 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 5976 if (error != 0) { 5977 aprint_error_dev(sc->sc_dev, 5978 "could not allocate RX buffers DMA memory\n"); 5979 return error; 5980 } 5981 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 5982 SLIST_INIT(&ring->freelist); 5983 for (i = 0; i < IWN_RBUF_COUNT; i++) { 5984 rbuf = &ring->rbuf[i]; 5985 5986 rbuf->sc = sc; /* Backpointer for callbacks. */ 5987 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 5988 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 5989 5990 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 5991 } 5992 ring->nb_free_entries = IWN_RBUF_COUNT; 5993 return 0; 5994 } 5995 5996 static void 5997 iwn_free_rpool(struct iwn_softc *sc) 5998 { 5999 iwn_dma_contig_free(&sc->rxq.buf_dma); 6000 } 6001 #endif 6002 6003 /* 6004 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6005 * Copyright (c) 2001 Atsushi Onoe 6006 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6007 * Copyright (c) 2007-2009 Damien Bergamini 6008 * All rights reserved. 6009 */ 6010 6011 /* 6012 * Add an SSID element to a frame (see 7.3.2.1). 6013 */ 6014 static u_int8_t * 6015 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6016 { 6017 *frm++ = IEEE80211_ELEMID_SSID; 6018 *frm++ = len; 6019 memcpy(frm, ssid, len); 6020 return frm + len; 6021 } 6022 6023 /* 6024 * Add a supported rates element to a frame (see 7.3.2.2). 6025 */ 6026 static u_int8_t * 6027 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6028 { 6029 int nrates; 6030 6031 *frm++ = IEEE80211_ELEMID_RATES; 6032 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6033 *frm++ = nrates; 6034 memcpy(frm, rs->rs_rates, nrates); 6035 return frm + nrates; 6036 } 6037 6038 /* 6039 * Add an extended supported rates element to a frame (see 7.3.2.14). 6040 */ 6041 static u_int8_t * 6042 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6043 { 6044 int nrates; 6045 6046 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6047 6048 *frm++ = IEEE80211_ELEMID_XRATES; 6049 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6050 *frm++ = nrates; 6051 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6052 return frm + nrates; 6053 } 6054 6055 /* 6056 * XXX: Hack to set the current channel to the value advertised in beacons or 6057 * probe responses. Only used during AP detection. 6058 * XXX: Duplicated from if_iwi.c 6059 */ 6060 static void 6061 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6062 { 6063 struct ieee80211_frame *wh; 6064 uint8_t subtype; 6065 uint8_t *frm, *efrm; 6066 6067 wh = mtod(m, struct ieee80211_frame *); 6068 6069 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6070 return; 6071 6072 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6073 6074 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6075 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6076 return; 6077 6078 frm = (uint8_t *)(wh + 1); 6079 efrm = mtod(m, uint8_t *) + m->m_len; 6080 6081 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6082 while (frm < efrm) { 6083 if (*frm == IEEE80211_ELEMID_DSPARMS) 6084 #if IEEE80211_CHAN_MAX < 255 6085 if (frm[2] <= IEEE80211_CHAN_MAX) 6086 #endif 6087 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6088 6089 frm += frm[1] + 2; 6090 } 6091 } 6092 6093
Indexes created Mon Sep 29 13:09:55 GMT 2025