if_iwn.c revision 1.58
1 /* $NetBSD: if_iwn.c,v 1.58 2011/08/28 16:33:51 elric Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.96 2010/05/13 09:25:03 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.58 2011/08/28 16:33:51 elric Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/conf.h> 40 #include <sys/kauth.h> 41 #include <sys/callout.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <machine/intr.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <net/if_ether.h> 64 #include <netinet/ip.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_amrr.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <dev/firmload.h> 71 72 #include <dev/pci/if_iwnreg.h> 73 #include <dev/pci/if_iwnvar.h> 74 75 static const pci_product_id_t iwn_devices[] = { 76 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 77 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 78 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 79 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 80 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 82 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 83 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 84 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 90 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 91 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 92 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 93 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 94 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 102 }; 103 104 /* 105 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 106 */ 107 static const struct ieee80211_rateset iwn_rateset_11a = 108 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 109 110 static const struct ieee80211_rateset iwn_rateset_11b = 111 { 4, { 2, 4, 11, 22 } }; 112 113 static const struct ieee80211_rateset iwn_rateset_11g = 114 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 115 116 static int iwn_match(device_t , struct cfdata *, void *); 117 static void iwn_attach(device_t , device_t , void *); 118 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 119 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 120 static void iwn_radiotap_attach(struct iwn_softc *); 121 static int iwn_detach(device_t , int); 122 #if 0 123 static void iwn_power(int, void *); 124 #endif 125 static bool iwn_resume(device_t, const pmf_qual_t *); 126 static int iwn_nic_lock(struct iwn_softc *); 127 static int iwn_eeprom_lock(struct iwn_softc *); 128 static int iwn_init_otprom(struct iwn_softc *); 129 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 130 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 131 void **, bus_size_t, bus_size_t); 132 static void iwn_dma_contig_free(struct iwn_dma_info *); 133 static int iwn_alloc_sched(struct iwn_softc *); 134 static void iwn_free_sched(struct iwn_softc *); 135 static int iwn_alloc_kw(struct iwn_softc *); 136 static void iwn_free_kw(struct iwn_softc *); 137 static int iwn_alloc_ict(struct iwn_softc *); 138 static void iwn_free_ict(struct iwn_softc *); 139 static int iwn_alloc_fwmem(struct iwn_softc *); 140 static void iwn_free_fwmem(struct iwn_softc *); 141 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 142 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 143 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 144 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 145 int); 146 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 147 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 148 static void iwn5000_ict_reset(struct iwn_softc *); 149 static int iwn_read_eeprom(struct iwn_softc *); 150 static void iwn4965_read_eeprom(struct iwn_softc *); 151 152 #ifdef IWN_DEBUG 153 static void iwn4965_print_power_group(struct iwn_softc *, int); 154 #endif 155 static void iwn5000_read_eeprom(struct iwn_softc *); 156 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 157 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 158 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 159 static void iwn_newassoc(struct ieee80211_node *, int); 160 static int iwn_media_change(struct ifnet *); 161 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 162 static void iwn_iter_func(void *, struct ieee80211_node *); 163 static void iwn_calib_timeout(void *); 164 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 165 struct iwn_rx_data *); 166 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 167 struct iwn_rx_data *); 168 #ifndef IEEE80211_NO_HT 169 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 170 struct iwn_rx_data *); 171 #endif 172 static void iwn5000_rx_calib_results(struct iwn_softc *, 173 struct iwn_rx_desc *, struct iwn_rx_data *); 174 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 179 struct iwn_rx_data *); 180 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 181 uint8_t); 182 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 183 static void iwn_notif_intr(struct iwn_softc *); 184 static void iwn_wakeup_intr(struct iwn_softc *); 185 static void iwn_fatal_intr(struct iwn_softc *); 186 static int iwn_intr(void *); 187 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 188 uint16_t); 189 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 190 uint16_t); 191 #ifdef notyet 192 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 193 #endif 194 static int iwn_tx(struct iwn_softc *, struct mbuf *, 195 struct ieee80211_node *, int); 196 static void iwn_start(struct ifnet *); 197 static void iwn_watchdog(struct ifnet *); 198 static int iwn_ioctl(struct ifnet *, u_long, void *); 199 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 200 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 201 int); 202 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 203 int); 204 static int iwn_set_link_quality(struct iwn_softc *, 205 struct ieee80211_node *); 206 static int iwn_add_broadcast_node(struct iwn_softc *, int); 207 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 208 static int iwn_set_critical_temp(struct iwn_softc *); 209 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 210 static void iwn4965_power_calibration(struct iwn_softc *, int); 211 static int iwn4965_set_txpower(struct iwn_softc *, int); 212 static int iwn5000_set_txpower(struct iwn_softc *, int); 213 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 214 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 215 static int iwn_get_noise(const struct iwn_rx_general_stats *); 216 static int iwn4965_get_temperature(struct iwn_softc *); 217 static int iwn5000_get_temperature(struct iwn_softc *); 218 static int iwn_init_sensitivity(struct iwn_softc *); 219 static void iwn_collect_noise(struct iwn_softc *, 220 const struct iwn_rx_general_stats *); 221 static int iwn4965_init_gains(struct iwn_softc *); 222 static int iwn5000_init_gains(struct iwn_softc *); 223 static int iwn4965_set_gains(struct iwn_softc *); 224 static int iwn5000_set_gains(struct iwn_softc *); 225 static void iwn_tune_sensitivity(struct iwn_softc *, 226 const struct iwn_rx_stats *); 227 static int iwn_send_sensitivity(struct iwn_softc *); 228 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 229 static int iwn_config(struct iwn_softc *); 230 static int iwn_scan(struct iwn_softc *, uint16_t); 231 static int iwn_auth(struct iwn_softc *); 232 static int iwn_run(struct iwn_softc *); 233 #ifdef IWN_HWCRYPTO 234 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 235 struct ieee80211_key *); 236 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 237 struct ieee80211_key *); 238 #endif 239 static int iwn_wme_update(struct ieee80211com *); 240 #ifndef IEEE80211_NO_HT 241 static int iwn_ampdu_rx_start(struct ieee80211com *, 242 struct ieee80211_node *, uint8_t); 243 static void iwn_ampdu_rx_stop(struct ieee80211com *, 244 struct ieee80211_node *, uint8_t); 245 static int iwn_ampdu_tx_start(struct ieee80211com *, 246 struct ieee80211_node *, uint8_t); 247 static void iwn_ampdu_tx_stop(struct ieee80211com *, 248 struct ieee80211_node *, uint8_t); 249 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 250 struct ieee80211_node *, uint8_t, uint16_t); 251 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 252 uint8_t, uint16_t); 253 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 254 struct ieee80211_node *, uint8_t, uint16_t); 255 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 256 uint8_t, uint16_t); 257 #endif 258 static int iwn5000_query_calibration(struct iwn_softc *); 259 static int iwn5000_send_calibration(struct iwn_softc *); 260 static int iwn5000_send_wimax_coex(struct iwn_softc *); 261 static int iwn4965_post_alive(struct iwn_softc *); 262 static int iwn5000_post_alive(struct iwn_softc *); 263 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 264 int); 265 static int iwn4965_load_firmware(struct iwn_softc *); 266 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 267 const uint8_t *, int); 268 static int iwn5000_load_firmware(struct iwn_softc *); 269 static int iwn_read_firmware_leg(struct iwn_softc *, 270 struct iwn_fw_info *); 271 static int iwn_read_firmware_tlv(struct iwn_softc *, 272 struct iwn_fw_info *, uint16_t); 273 static int iwn_read_firmware(struct iwn_softc *); 274 static int iwn_clock_wait(struct iwn_softc *); 275 static int iwn_apm_init(struct iwn_softc *); 276 static void iwn_apm_stop_master(struct iwn_softc *); 277 static void iwn_apm_stop(struct iwn_softc *); 278 static int iwn4965_nic_config(struct iwn_softc *); 279 static int iwn5000_nic_config(struct iwn_softc *); 280 static int iwn_hw_prepare(struct iwn_softc *); 281 static int iwn_hw_init(struct iwn_softc *); 282 static void iwn_hw_stop(struct iwn_softc *); 283 static int iwn_init(struct ifnet *); 284 static void iwn_stop(struct ifnet *, int); 285 286 /* XXX MCLGETI alternative */ 287 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 288 struct ifnet *, u_int); 289 #ifdef IWN_USE_RBUF 290 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 291 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 292 static int iwn_alloc_rpool(struct iwn_softc *); 293 static void iwn_free_rpool(struct iwn_softc *); 294 #endif 295 296 /* XXX needed by iwn_scan */ 297 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 298 static u_int8_t *ieee80211_add_rates(u_int8_t *, 299 const struct ieee80211_rateset *); 300 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 301 const struct ieee80211_rateset *); 302 303 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 304 305 #ifdef IWN_DEBUG 306 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 307 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 308 int iwn_debug = 0; 309 #else 310 #define DPRINTF(x) 311 #define DPRINTFN(n, x) 312 #endif 313 314 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 315 iwn_detach, NULL); 316 317 static int 318 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 319 { 320 struct pci_attach_args *pa = aux; 321 size_t i; 322 323 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 324 return 0; 325 326 for (i = 0; i < __arraycount(iwn_devices); i++) 327 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 328 return 1; 329 330 return 0; 331 } 332 333 static void 334 iwn_attach(device_t parent __unused, device_t self, void *aux) 335 { 336 struct iwn_softc *sc = device_private(self); 337 struct ieee80211com *ic = &sc->sc_ic; 338 struct ifnet *ifp = &sc->sc_ec.ec_if; 339 struct pci_attach_args *pa = aux; 340 const char *intrstr; 341 char devinfo[256]; 342 pci_intr_handle_t ih; 343 pcireg_t memtype, reg; 344 int i, error; 345 int revision; 346 347 sc->sc_dev = self; 348 sc->sc_pct = pa->pa_pc; 349 sc->sc_pcitag = pa->pa_tag; 350 sc->sc_dmat = pa->pa_dmat; 351 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 352 353 callout_init(&sc->calib_to, 0); 354 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 355 356 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 357 revision = PCI_REVISION(pa->pa_class); 358 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 359 360 /* 361 * Get the offset of the PCI Express Capability Structure in PCI 362 * Configuration Space. 363 */ 364 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 365 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 366 if (error == 0) { 367 aprint_error(": PCIe capability structure not found!\n"); 368 return; 369 } 370 371 /* Clear device-specific "PCI retry timeout" register (41h). */ 372 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 373 if (reg & 0xff00) 374 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 375 376 /* Enable bus-mastering and hardware bug workaround. */ 377 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 378 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 379 reg |= PCI_COMMAND_MASTER_ENABLE; 380 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 381 DPRINTF(("PCIe INTx Disable set\n")); 382 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 383 } 384 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 385 386 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 387 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 388 &sc->sc_sh, NULL, &sc->sc_sz); 389 if (error != 0) { 390 aprint_error(": can't map mem space\n"); 391 return; 392 } 393 394 /* Install interrupt handler. */ 395 if (pci_intr_map(pa, &ih) != 0) { 396 aprint_error(": can't map interrupt\n"); 397 return; 398 } 399 intrstr = pci_intr_string(sc->sc_pct, ih); 400 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 401 if (sc->sc_ih == NULL) { 402 aprint_error(": can't establish interrupt"); 403 if (intrstr != NULL) 404 aprint_error(" at %s", intrstr); 405 aprint_error("\n"); 406 return; 407 } 408 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 409 410 /* Read hardware revision and attach. */ 411 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 412 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 413 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 414 else 415 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 416 if (error != 0) { 417 aprint_error(": could not attach device\n"); 418 return; 419 } 420 421 if ((error = iwn_hw_prepare(sc)) != 0) { 422 aprint_error(": hardware not ready\n"); 423 return; 424 } 425 426 /* Read MAC address, channels, etc from EEPROM. */ 427 if ((error = iwn_read_eeprom(sc)) != 0) { 428 aprint_error(": could not read EEPROM\n"); 429 return; 430 } 431 432 /* Allocate DMA memory for firmware transfers. */ 433 if ((error = iwn_alloc_fwmem(sc)) != 0) { 434 aprint_error(": could not allocate memory for firmware\n"); 435 return; 436 } 437 438 /* Allocate "Keep Warm" page. */ 439 if ((error = iwn_alloc_kw(sc)) != 0) { 440 aprint_error(": could not allocate keep warm page\n"); 441 goto fail1; 442 } 443 444 /* Allocate ICT table for 5000 Series. */ 445 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 446 (error = iwn_alloc_ict(sc)) != 0) { 447 aprint_error(": could not allocate ICT table\n"); 448 goto fail2; 449 } 450 451 /* Allocate TX scheduler "rings". */ 452 if ((error = iwn_alloc_sched(sc)) != 0) { 453 aprint_error(": could not allocate TX scheduler rings\n"); 454 goto fail3; 455 } 456 457 #ifdef IWN_USE_RBUF 458 /* Allocate RX buffers. */ 459 if ((error = iwn_alloc_rpool(sc)) != 0) { 460 aprint_error_dev(self, "could not allocate RX buffers\n"); 461 goto fail3; 462 } 463 #endif 464 465 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 466 for (i = 0; i < sc->ntxqs; i++) { 467 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 468 aprint_error(": could not allocate TX ring %d\n", i); 469 goto fail4; 470 } 471 } 472 473 /* Allocate RX ring. */ 474 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 475 aprint_error(": could not allocate RX ring\n"); 476 goto fail4; 477 } 478 479 /* Clear pending interrupts. */ 480 IWN_WRITE(sc, IWN_INT, 0xffffffff); 481 482 /* Count the number of available chains. */ 483 sc->ntxchains = 484 ((sc->txchainmask >> 2) & 1) + 485 ((sc->txchainmask >> 1) & 1) + 486 ((sc->txchainmask >> 0) & 1); 487 sc->nrxchains = 488 ((sc->rxchainmask >> 2) & 1) + 489 ((sc->rxchainmask >> 1) & 1) + 490 ((sc->rxchainmask >> 0) & 1); 491 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 492 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 493 ether_sprintf(ic->ic_myaddr)); 494 495 ic->ic_ifp = ifp; 496 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 497 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 498 ic->ic_state = IEEE80211_S_INIT; 499 500 /* Set device capabilities. */ 501 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 502 * and IEEE80211_C_PMGT too. */ 503 ic->ic_caps = 504 IEEE80211_C_IBSS | /* IBSS mode support */ 505 IEEE80211_C_WPA | /* 802.11i */ 506 IEEE80211_C_MONITOR | /* monitor mode supported */ 507 IEEE80211_C_TXPMGT | /* tx power management */ 508 IEEE80211_C_SHSLOT | /* short slot time supported */ 509 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 510 IEEE80211_C_WME; /* 802.11e */ 511 512 #ifndef IEEE80211_NO_HT 513 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 514 /* Set HT capabilities. */ 515 ic->ic_htcaps = 516 #if IWN_RBUF_SIZE == 8192 517 IEEE80211_HTCAP_AMSDU7935 | 518 #endif 519 IEEE80211_HTCAP_CBW20_40 | 520 IEEE80211_HTCAP_SGI20 | 521 IEEE80211_HTCAP_SGI40; 522 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 523 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 524 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 525 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 526 else 527 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 528 } 529 #endif /* !IEEE80211_NO_HT */ 530 531 /* Set supported legacy rates. */ 532 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 533 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 534 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 535 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 536 } 537 #ifndef IEEE80211_NO_HT 538 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 539 /* Set supported HT rates. */ 540 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 541 if (sc->nrxchains > 1) 542 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 543 if (sc->nrxchains > 2) 544 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 545 } 546 #endif 547 548 /* IBSS channel undefined for now. */ 549 ic->ic_ibss_chan = &ic->ic_channels[0]; 550 551 ifp->if_softc = sc; 552 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 553 ifp->if_init = iwn_init; 554 ifp->if_ioctl = iwn_ioctl; 555 ifp->if_start = iwn_start; 556 ifp->if_stop = iwn_stop; 557 ifp->if_watchdog = iwn_watchdog; 558 IFQ_SET_READY(&ifp->if_snd); 559 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 560 561 if_attach(ifp); 562 ieee80211_ifattach(ic); 563 ic->ic_node_alloc = iwn_node_alloc; 564 ic->ic_newassoc = iwn_newassoc; 565 #ifdef IWN_HWCRYPTO 566 ic->ic_crypto.cs_key_set = iwn_set_key; 567 ic->ic_crypto.cs_key_delete = iwn_delete_key; 568 #endif 569 ic->ic_wme.wme_update = iwn_wme_update; 570 #ifndef IEEE80211_NO_HT 571 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 572 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 573 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 574 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 575 #endif 576 577 /* Override 802.11 state transition machine. */ 578 sc->sc_newstate = ic->ic_newstate; 579 ic->ic_newstate = iwn_newstate; 580 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 581 582 sc->amrr.amrr_min_success_threshold = 1; 583 sc->amrr.amrr_max_success_threshold = 15; 584 585 iwn_radiotap_attach(sc); 586 587 /* 588 * XXX for NetBSD, OpenBSD timeout_set replaced by 589 * callout_init and callout_setfunc, above. 590 */ 591 592 if (pmf_device_register(self, NULL, iwn_resume)) 593 pmf_class_network_register(self, ifp); 594 else 595 aprint_error_dev(self, "couldn't establish power handler\n"); 596 597 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 598 ieee80211_announce(ic); 599 600 return; 601 602 /* Free allocated memory if something failed during attachment. */ 603 fail4: while (--i >= 0) 604 iwn_free_tx_ring(sc, &sc->txq[i]); 605 #ifdef IWN_USE_RBUF 606 iwn_free_rpool(sc); 607 #endif 608 iwn_free_sched(sc); 609 fail3: if (sc->ict != NULL) 610 iwn_free_ict(sc); 611 fail2: iwn_free_kw(sc); 612 fail1: iwn_free_fwmem(sc); 613 } 614 615 int 616 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 617 { 618 struct iwn_ops *ops = &sc->ops; 619 620 ops->load_firmware = iwn4965_load_firmware; 621 ops->read_eeprom = iwn4965_read_eeprom; 622 ops->post_alive = iwn4965_post_alive; 623 ops->nic_config = iwn4965_nic_config; 624 ops->update_sched = iwn4965_update_sched; 625 ops->get_temperature = iwn4965_get_temperature; 626 ops->get_rssi = iwn4965_get_rssi; 627 ops->set_txpower = iwn4965_set_txpower; 628 ops->init_gains = iwn4965_init_gains; 629 ops->set_gains = iwn4965_set_gains; 630 ops->add_node = iwn4965_add_node; 631 ops->tx_done = iwn4965_tx_done; 632 #ifndef IEEE80211_NO_HT 633 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 634 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 635 #endif 636 sc->ntxqs = IWN4965_NTXQUEUES; 637 sc->ndmachnls = IWN4965_NDMACHNLS; 638 sc->broadcast_id = IWN4965_ID_BROADCAST; 639 sc->rxonsz = IWN4965_RXONSZ; 640 sc->schedsz = IWN4965_SCHEDSZ; 641 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 642 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 643 sc->fwsz = IWN4965_FWSZ; 644 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 645 sc->limits = &iwn4965_sensitivity_limits; 646 sc->fwname = "iwlwifi-4965-2.ucode"; 647 /* Override chains masks, ROM is known to be broken. */ 648 sc->txchainmask = IWN_ANT_AB; 649 sc->rxchainmask = IWN_ANT_ABC; 650 651 return 0; 652 } 653 654 int 655 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 656 { 657 struct iwn_ops *ops = &sc->ops; 658 659 ops->load_firmware = iwn5000_load_firmware; 660 ops->read_eeprom = iwn5000_read_eeprom; 661 ops->post_alive = iwn5000_post_alive; 662 ops->nic_config = iwn5000_nic_config; 663 ops->update_sched = iwn5000_update_sched; 664 ops->get_temperature = iwn5000_get_temperature; 665 ops->get_rssi = iwn5000_get_rssi; 666 ops->set_txpower = iwn5000_set_txpower; 667 ops->init_gains = iwn5000_init_gains; 668 ops->set_gains = iwn5000_set_gains; 669 ops->add_node = iwn5000_add_node; 670 ops->tx_done = iwn5000_tx_done; 671 #ifndef IEEE80211_NO_HT 672 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 673 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 674 #endif 675 sc->ntxqs = IWN5000_NTXQUEUES; 676 sc->ndmachnls = IWN5000_NDMACHNLS; 677 sc->broadcast_id = IWN5000_ID_BROADCAST; 678 sc->rxonsz = IWN5000_RXONSZ; 679 sc->schedsz = IWN5000_SCHEDSZ; 680 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 681 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 682 sc->fwsz = IWN5000_FWSZ; 683 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 684 685 switch (sc->hw_type) { 686 case IWN_HW_REV_TYPE_5100: 687 sc->limits = &iwn5000_sensitivity_limits; 688 sc->fwname = "iwlwifi-5000-2.ucode"; 689 /* Override chains masks, ROM is known to be broken. */ 690 sc->txchainmask = IWN_ANT_B; 691 sc->rxchainmask = IWN_ANT_AB; 692 break; 693 case IWN_HW_REV_TYPE_5150: 694 sc->limits = &iwn5150_sensitivity_limits; 695 sc->fwname = "iwlwifi-5150-2.ucode"; 696 break; 697 case IWN_HW_REV_TYPE_5300: 698 case IWN_HW_REV_TYPE_5350: 699 sc->limits = &iwn5000_sensitivity_limits; 700 sc->fwname = "iwlwifi-5000-2.ucode"; 701 break; 702 case IWN_HW_REV_TYPE_1000: 703 sc->limits = &iwn1000_sensitivity_limits; 704 sc->fwname = "iwlwifi-1000-3.ucode"; 705 break; 706 case IWN_HW_REV_TYPE_6000: 707 sc->limits = &iwn6000_sensitivity_limits; 708 sc->fwname = "iwlwifi-6000-4.ucode"; 709 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 710 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 711 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 712 /* Override chains masks, ROM is known to be broken. */ 713 sc->txchainmask = IWN_ANT_BC; 714 sc->rxchainmask = IWN_ANT_BC; 715 } 716 break; 717 case IWN_HW_REV_TYPE_6050: 718 sc->limits = &iwn6000_sensitivity_limits; 719 sc->fwname = "iwlwifi-6050-5.ucode"; 720 break; 721 case IWN_HW_REV_TYPE_6005: 722 sc->limits = &iwn6000_sensitivity_limits; 723 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 724 break; 725 default: 726 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 727 return ENOTSUP; 728 } 729 return 0; 730 } 731 732 /* 733 * Attach the interface to 802.11 radiotap. 734 */ 735 static void 736 iwn_radiotap_attach(struct iwn_softc *sc) 737 { 738 struct ifnet *ifp = sc->sc_ic.ic_ifp; 739 740 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 741 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 742 &sc->sc_drvbpf); 743 744 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 745 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 746 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 747 748 sc->sc_txtap_len = sizeof sc->sc_txtapu; 749 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 750 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 751 } 752 753 static int 754 iwn_detach(device_t self, int flags __unused) 755 { 756 struct iwn_softc *sc = device_private(self); 757 struct ifnet *ifp = sc->sc_ic.ic_ifp; 758 int qid; 759 760 callout_stop(&sc->calib_to); 761 762 /* Uninstall interrupt handler. */ 763 if (sc->sc_ih != NULL) 764 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 765 766 /* Free DMA resources. */ 767 iwn_free_rx_ring(sc, &sc->rxq); 768 for (qid = 0; qid < sc->ntxqs; qid++) 769 iwn_free_tx_ring(sc, &sc->txq[qid]); 770 #ifdef IWN_USE_RBUF 771 iwn_free_rpool(sc); 772 #endif 773 iwn_free_sched(sc); 774 iwn_free_kw(sc); 775 if (sc->ict != NULL) 776 iwn_free_ict(sc); 777 iwn_free_fwmem(sc); 778 779 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 780 781 ieee80211_ifdetach(&sc->sc_ic); 782 if_detach(ifp); 783 784 return 0; 785 } 786 787 #if 0 788 /* 789 * XXX Investigate if clearing the PCI retry timeout could eliminate 790 * the repeated scan calls. Also the calls to if_init and if_start 791 * are similar to the effect of adding the call to ifioctl_common . 792 */ 793 static void 794 iwn_power(int why, void *arg) 795 { 796 struct iwn_softc *sc = arg; 797 struct ifnet *ifp; 798 pcireg_t reg; 799 int s; 800 801 if (why != PWR_RESUME) 802 return; 803 804 /* Clear device-specific "PCI retry timeout" register (41h). */ 805 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 806 if (reg & 0xff00) 807 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 808 809 s = splnet(); 810 ifp = &sc->sc_ic.ic_if; 811 if (ifp->if_flags & IFF_UP) { 812 ifp->if_init(ifp); 813 if (ifp->if_flags & IFF_RUNNING) 814 ifp->if_start(ifp); 815 } 816 splx(s); 817 } 818 #endif 819 820 static bool 821 iwn_resume(device_t dv, const pmf_qual_t *qual) 822 { 823 return true; 824 } 825 826 static int 827 iwn_nic_lock(struct iwn_softc *sc) 828 { 829 int ntries; 830 831 /* Request exclusive access to NIC. */ 832 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 833 834 /* Spin until we actually get the lock. */ 835 for (ntries = 0; ntries < 1000; ntries++) { 836 if ((IWN_READ(sc, IWN_GP_CNTRL) & 837 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 838 IWN_GP_CNTRL_MAC_ACCESS_ENA) 839 return 0; 840 DELAY(10); 841 } 842 return ETIMEDOUT; 843 } 844 845 static __inline void 846 iwn_nic_unlock(struct iwn_softc *sc) 847 { 848 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 849 } 850 851 static __inline uint32_t 852 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 853 { 854 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 855 IWN_BARRIER_READ_WRITE(sc); 856 return IWN_READ(sc, IWN_PRPH_RDATA); 857 } 858 859 static __inline void 860 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 861 { 862 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 863 IWN_BARRIER_WRITE(sc); 864 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 865 } 866 867 static __inline void 868 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 869 { 870 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 871 } 872 873 static __inline void 874 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 875 { 876 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 877 } 878 879 static __inline void 880 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 881 const uint32_t *data, int count) 882 { 883 for (; count > 0; count--, data++, addr += 4) 884 iwn_prph_write(sc, addr, *data); 885 } 886 887 static __inline uint32_t 888 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 889 { 890 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 891 IWN_BARRIER_READ_WRITE(sc); 892 return IWN_READ(sc, IWN_MEM_RDATA); 893 } 894 895 static __inline void 896 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 897 { 898 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 899 IWN_BARRIER_WRITE(sc); 900 IWN_WRITE(sc, IWN_MEM_WDATA, data); 901 } 902 903 static __inline void 904 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 905 { 906 uint32_t tmp; 907 908 tmp = iwn_mem_read(sc, addr & ~3); 909 if (addr & 3) 910 tmp = (tmp & 0x0000ffff) | data << 16; 911 else 912 tmp = (tmp & 0xffff0000) | data; 913 iwn_mem_write(sc, addr & ~3, tmp); 914 } 915 916 static __inline void 917 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 918 int count) 919 { 920 for (; count > 0; count--, addr += 4) 921 *data++ = iwn_mem_read(sc, addr); 922 } 923 924 static __inline void 925 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 926 int count) 927 { 928 for (; count > 0; count--, addr += 4) 929 iwn_mem_write(sc, addr, val); 930 } 931 932 static int 933 iwn_eeprom_lock(struct iwn_softc *sc) 934 { 935 int i, ntries; 936 937 for (i = 0; i < 100; i++) { 938 /* Request exclusive access to EEPROM. */ 939 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 940 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 941 942 /* Spin until we actually get the lock. */ 943 for (ntries = 0; ntries < 100; ntries++) { 944 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 945 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 946 return 0; 947 DELAY(10); 948 } 949 } 950 return ETIMEDOUT; 951 } 952 953 static __inline void 954 iwn_eeprom_unlock(struct iwn_softc *sc) 955 { 956 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 957 } 958 959 /* 960 * Initialize access by host to One Time Programmable ROM. 961 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 962 */ 963 static int 964 iwn_init_otprom(struct iwn_softc *sc) 965 { 966 uint16_t prev = 0, base, next; 967 int count, error; 968 969 /* Wait for clock stabilization before accessing prph. */ 970 if ((error = iwn_clock_wait(sc)) != 0) 971 return error; 972 973 if ((error = iwn_nic_lock(sc)) != 0) 974 return error; 975 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 976 DELAY(5); 977 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 978 iwn_nic_unlock(sc); 979 980 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 981 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 982 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 983 IWN_RESET_LINK_PWR_MGMT_DIS); 984 } 985 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 986 /* Clear ECC status. */ 987 IWN_SETBITS(sc, IWN_OTP_GP, 988 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 989 990 /* 991 * Find the block before last block (contains the EEPROM image) 992 * for HW without OTP shadow RAM. 993 */ 994 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 995 /* Switch to absolute addressing mode. */ 996 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 997 base = 0; 998 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 999 error = iwn_read_prom_data(sc, base, &next, 2); 1000 if (error != 0) 1001 return error; 1002 if (next == 0) /* End of linked-list. */ 1003 break; 1004 prev = base; 1005 base = le16toh(next); 1006 } 1007 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1008 return EIO; 1009 /* Skip "next" word. */ 1010 sc->prom_base = prev + 1; 1011 } 1012 return 0; 1013 } 1014 1015 static int 1016 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1017 { 1018 uint8_t *out = data; 1019 uint32_t val, tmp; 1020 int ntries; 1021 1022 addr += sc->prom_base; 1023 for (; count > 0; count -= 2, addr++) { 1024 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1025 for (ntries = 0; ntries < 10; ntries++) { 1026 val = IWN_READ(sc, IWN_EEPROM); 1027 if (val & IWN_EEPROM_READ_VALID) 1028 break; 1029 DELAY(5); 1030 } 1031 if (ntries == 10) { 1032 aprint_error_dev(sc->sc_dev, 1033 "timeout reading ROM at 0x%x\n", addr); 1034 return ETIMEDOUT; 1035 } 1036 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1037 /* OTPROM, check for ECC errors. */ 1038 tmp = IWN_READ(sc, IWN_OTP_GP); 1039 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1040 aprint_error_dev(sc->sc_dev, 1041 "OTPROM ECC error at 0x%x\n", addr); 1042 return EIO; 1043 } 1044 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1045 /* Correctable ECC error, clear bit. */ 1046 IWN_SETBITS(sc, IWN_OTP_GP, 1047 IWN_OTP_GP_ECC_CORR_STTS); 1048 } 1049 } 1050 *out++ = val >> 16; 1051 if (count > 1) 1052 *out++ = val >> 24; 1053 } 1054 return 0; 1055 } 1056 1057 static int 1058 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1059 bus_size_t size, bus_size_t alignment) 1060 { 1061 int nsegs, error; 1062 1063 dma->tag = tag; 1064 dma->size = size; 1065 1066 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1067 &dma->map); 1068 if (error != 0) 1069 goto fail; 1070 1071 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1072 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1073 if (error != 0) 1074 goto fail; 1075 1076 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1077 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1078 if (error != 0) 1079 goto fail; 1080 1081 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1082 BUS_DMA_NOWAIT); 1083 if (error != 0) 1084 goto fail; 1085 1086 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1087 memset(dma->vaddr, 0, size); 1088 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1089 1090 dma->paddr = dma->map->dm_segs[0].ds_addr; 1091 if (kvap != NULL) 1092 *kvap = dma->vaddr; 1093 1094 return 0; 1095 1096 fail: iwn_dma_contig_free(dma); 1097 return error; 1098 } 1099 1100 static void 1101 iwn_dma_contig_free(struct iwn_dma_info *dma) 1102 { 1103 if (dma->map != NULL) { 1104 if (dma->vaddr != NULL) { 1105 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1106 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1107 bus_dmamap_unload(dma->tag, dma->map); 1108 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1109 bus_dmamem_free(dma->tag, &dma->seg, 1); 1110 dma->vaddr = NULL; 1111 } 1112 bus_dmamap_destroy(dma->tag, dma->map); 1113 dma->map = NULL; 1114 } 1115 } 1116 1117 static int 1118 iwn_alloc_sched(struct iwn_softc *sc) 1119 { 1120 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1121 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1122 (void **)&sc->sched, sc->schedsz, 1024); 1123 } 1124 1125 static void 1126 iwn_free_sched(struct iwn_softc *sc) 1127 { 1128 iwn_dma_contig_free(&sc->sched_dma); 1129 } 1130 1131 static int 1132 iwn_alloc_kw(struct iwn_softc *sc) 1133 { 1134 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1135 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1136 4096); 1137 } 1138 1139 static void 1140 iwn_free_kw(struct iwn_softc *sc) 1141 { 1142 iwn_dma_contig_free(&sc->kw_dma); 1143 } 1144 1145 static int 1146 iwn_alloc_ict(struct iwn_softc *sc) 1147 { 1148 /* ICT table must be aligned on a 4KB boundary. */ 1149 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1150 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1151 } 1152 1153 static void 1154 iwn_free_ict(struct iwn_softc *sc) 1155 { 1156 iwn_dma_contig_free(&sc->ict_dma); 1157 } 1158 1159 static int 1160 iwn_alloc_fwmem(struct iwn_softc *sc) 1161 { 1162 /* Must be aligned on a 16-byte boundary. */ 1163 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1164 sc->fwsz, 16); 1165 } 1166 1167 static void 1168 iwn_free_fwmem(struct iwn_softc *sc) 1169 { 1170 iwn_dma_contig_free(&sc->fw_dma); 1171 } 1172 1173 static int 1174 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1175 { 1176 bus_size_t size; 1177 int i, error; 1178 1179 ring->cur = 0; 1180 1181 /* Allocate RX descriptors (256-byte aligned). */ 1182 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1183 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1184 (void **)&ring->desc, size, 256); 1185 if (error != 0) { 1186 aprint_error_dev(sc->sc_dev, 1187 "could not allocate RX ring DMA memory\n"); 1188 goto fail; 1189 } 1190 1191 /* Allocate RX status area (16-byte aligned). */ 1192 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1193 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1194 if (error != 0) { 1195 aprint_error_dev(sc->sc_dev, 1196 "could not allocate RX status DMA memory\n"); 1197 goto fail; 1198 } 1199 1200 /* 1201 * Allocate and map RX buffers. 1202 */ 1203 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1204 struct iwn_rx_data *data = &ring->data[i]; 1205 1206 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1207 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1208 &data->map); 1209 if (error != 0) { 1210 aprint_error_dev(sc->sc_dev, 1211 "could not create RX buf DMA map\n"); 1212 goto fail; 1213 } 1214 1215 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1216 if (data->m == NULL) { 1217 aprint_error_dev(sc->sc_dev, 1218 "could not allocate RX mbuf\n"); 1219 error = ENOBUFS; 1220 goto fail; 1221 } 1222 1223 error = bus_dmamap_load(sc->sc_dmat, data->map, 1224 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1225 BUS_DMA_NOWAIT | BUS_DMA_READ); 1226 if (error != 0) { 1227 aprint_error_dev(sc->sc_dev, 1228 "can't not map mbuf (error %d)\n", error); 1229 goto fail; 1230 } 1231 1232 /* Set physical address of RX buffer (256-byte aligned). */ 1233 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1234 } 1235 1236 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1237 BUS_DMASYNC_PREWRITE); 1238 1239 return 0; 1240 1241 fail: iwn_free_rx_ring(sc, ring); 1242 return error; 1243 } 1244 1245 static void 1246 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1247 { 1248 int ntries; 1249 1250 if (iwn_nic_lock(sc) == 0) { 1251 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1252 for (ntries = 0; ntries < 1000; ntries++) { 1253 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1254 IWN_FH_RX_STATUS_IDLE) 1255 break; 1256 DELAY(10); 1257 } 1258 iwn_nic_unlock(sc); 1259 } 1260 ring->cur = 0; 1261 sc->last_rx_valid = 0; 1262 } 1263 1264 static void 1265 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1266 { 1267 int i; 1268 1269 iwn_dma_contig_free(&ring->desc_dma); 1270 iwn_dma_contig_free(&ring->stat_dma); 1271 1272 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1273 struct iwn_rx_data *data = &ring->data[i]; 1274 1275 if (data->m != NULL) { 1276 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1277 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1278 bus_dmamap_unload(sc->sc_dmat, data->map); 1279 m_freem(data->m); 1280 } 1281 if (data->map != NULL) 1282 bus_dmamap_destroy(sc->sc_dmat, data->map); 1283 } 1284 } 1285 1286 static int 1287 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1288 { 1289 bus_addr_t paddr; 1290 bus_size_t size; 1291 int i, error; 1292 1293 ring->qid = qid; 1294 ring->queued = 0; 1295 ring->cur = 0; 1296 1297 /* Allocate TX descriptors (256-byte aligned). */ 1298 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1299 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1300 (void **)&ring->desc, size, 256); 1301 if (error != 0) { 1302 aprint_error_dev(sc->sc_dev, 1303 "could not allocate TX ring DMA memory\n"); 1304 goto fail; 1305 } 1306 /* 1307 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1308 * to allocate commands space for other rings. 1309 * XXX Do we really need to allocate descriptors for other rings? 1310 */ 1311 if (qid > 4) 1312 return 0; 1313 1314 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1315 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1316 (void **)&ring->cmd, size, 4); 1317 if (error != 0) { 1318 aprint_error_dev(sc->sc_dev, 1319 "could not allocate TX cmd DMA memory\n"); 1320 goto fail; 1321 } 1322 1323 paddr = ring->cmd_dma.paddr; 1324 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1325 struct iwn_tx_data *data = &ring->data[i]; 1326 1327 data->cmd_paddr = paddr; 1328 data->scratch_paddr = paddr + 12; 1329 paddr += sizeof (struct iwn_tx_cmd); 1330 1331 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1332 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1333 &data->map); 1334 if (error != 0) { 1335 aprint_error_dev(sc->sc_dev, 1336 "could not create TX buf DMA map\n"); 1337 goto fail; 1338 } 1339 } 1340 return 0; 1341 1342 fail: iwn_free_tx_ring(sc, ring); 1343 return error; 1344 } 1345 1346 static void 1347 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1348 { 1349 int i; 1350 1351 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1352 struct iwn_tx_data *data = &ring->data[i]; 1353 1354 if (data->m != NULL) { 1355 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1356 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1357 bus_dmamap_unload(sc->sc_dmat, data->map); 1358 m_freem(data->m); 1359 data->m = NULL; 1360 } 1361 } 1362 /* Clear TX descriptors. */ 1363 memset(ring->desc, 0, ring->desc_dma.size); 1364 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1365 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1366 sc->qfullmsk &= ~(1 << ring->qid); 1367 ring->queued = 0; 1368 ring->cur = 0; 1369 } 1370 1371 static void 1372 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1373 { 1374 int i; 1375 1376 iwn_dma_contig_free(&ring->desc_dma); 1377 iwn_dma_contig_free(&ring->cmd_dma); 1378 1379 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1380 struct iwn_tx_data *data = &ring->data[i]; 1381 1382 if (data->m != NULL) { 1383 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1384 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1385 bus_dmamap_unload(sc->sc_dmat, data->map); 1386 m_freem(data->m); 1387 } 1388 if (data->map != NULL) 1389 bus_dmamap_destroy(sc->sc_dmat, data->map); 1390 } 1391 } 1392 1393 static void 1394 iwn5000_ict_reset(struct iwn_softc *sc) 1395 { 1396 /* Disable interrupts. */ 1397 IWN_WRITE(sc, IWN_INT_MASK, 0); 1398 1399 /* Reset ICT table. */ 1400 memset(sc->ict, 0, IWN_ICT_SIZE); 1401 sc->ict_cur = 0; 1402 1403 /* Set physical address of ICT table (4KB aligned). */ 1404 DPRINTF(("enabling ICT\n")); 1405 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1406 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1407 1408 /* Enable periodic RX interrupt. */ 1409 sc->int_mask |= IWN_INT_RX_PERIODIC; 1410 /* Switch to ICT interrupt mode in driver. */ 1411 sc->sc_flags |= IWN_FLAG_USE_ICT; 1412 1413 /* Re-enable interrupts. */ 1414 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1415 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1416 } 1417 1418 static int 1419 iwn_read_eeprom(struct iwn_softc *sc) 1420 { 1421 struct iwn_ops *ops = &sc->ops; 1422 struct ieee80211com *ic = &sc->sc_ic; 1423 uint16_t val; 1424 int error; 1425 1426 /* Check whether adapter has an EEPROM or an OTPROM. */ 1427 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1428 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1429 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1430 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1431 "OTPROM" : "EEPROM")); 1432 1433 /* Adapter has to be powered on for EEPROM access to work. */ 1434 if ((error = iwn_apm_init(sc)) != 0) { 1435 aprint_error_dev(sc->sc_dev, 1436 "could not power ON adapter\n"); 1437 return error; 1438 } 1439 1440 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1441 aprint_error_dev(sc->sc_dev, 1442 "bad ROM signature\n"); 1443 return EIO; 1444 } 1445 if ((error = iwn_eeprom_lock(sc)) != 0) { 1446 aprint_error_dev(sc->sc_dev, 1447 "could not lock ROM (error=%d)\n", error); 1448 return error; 1449 } 1450 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1451 if ((error = iwn_init_otprom(sc)) != 0) { 1452 aprint_error_dev(sc->sc_dev, 1453 "could not initialize OTPROM\n"); 1454 return error; 1455 } 1456 } 1457 1458 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1459 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1460 /* Check if HT support is bonded out. */ 1461 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1462 sc->sc_flags |= IWN_FLAG_HAS_11N; 1463 1464 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1465 sc->rfcfg = le16toh(val); 1466 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1467 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1468 if (sc->txchainmask == 0) 1469 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1470 if (sc->rxchainmask == 0) 1471 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1472 1473 /* Read MAC address. */ 1474 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1475 1476 /* Read adapter-specific information from EEPROM. */ 1477 ops->read_eeprom(sc); 1478 1479 iwn_apm_stop(sc); /* Power OFF adapter. */ 1480 1481 iwn_eeprom_unlock(sc); 1482 return 0; 1483 } 1484 1485 static void 1486 iwn4965_read_eeprom(struct iwn_softc *sc) 1487 { 1488 uint32_t addr; 1489 uint16_t val; 1490 int i; 1491 1492 /* Read regulatory domain (4 ASCII characters). */ 1493 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1494 1495 /* Read the list of authorized channels (20MHz ones only). */ 1496 for (i = 0; i < 5; i++) { 1497 addr = iwn4965_regulatory_bands[i]; 1498 iwn_read_eeprom_channels(sc, i, addr); 1499 } 1500 1501 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1502 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1503 sc->maxpwr2GHz = val & 0xff; 1504 sc->maxpwr5GHz = val >> 8; 1505 /* Check that EEPROM values are within valid range. */ 1506 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1507 sc->maxpwr5GHz = 38; 1508 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1509 sc->maxpwr2GHz = 38; 1510 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1511 1512 /* Read samples for each TX power group. */ 1513 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1514 sizeof sc->bands); 1515 1516 /* Read voltage at which samples were taken. */ 1517 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1518 sc->eeprom_voltage = (int16_t)le16toh(val); 1519 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1520 1521 #ifdef IWN_DEBUG 1522 /* Print samples. */ 1523 if (iwn_debug > 0) { 1524 for (i = 0; i < IWN_NBANDS; i++) 1525 iwn4965_print_power_group(sc, i); 1526 } 1527 #endif 1528 } 1529 1530 #ifdef IWN_DEBUG 1531 static void 1532 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1533 { 1534 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1535 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1536 int j, c; 1537 1538 aprint_normal("===band %d===\n", i); 1539 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1540 aprint_normal("chan1 num=%d\n", chans[0].num); 1541 for (c = 0; c < 2; c++) { 1542 for (j = 0; j < IWN_NSAMPLES; j++) { 1543 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1544 "power=%d pa_det=%d\n", c, j, 1545 chans[0].samples[c][j].temp, 1546 chans[0].samples[c][j].gain, 1547 chans[0].samples[c][j].power, 1548 chans[0].samples[c][j].pa_det); 1549 } 1550 } 1551 aprint_normal("chan2 num=%d\n", chans[1].num); 1552 for (c = 0; c < 2; c++) { 1553 for (j = 0; j < IWN_NSAMPLES; j++) { 1554 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1555 "power=%d pa_det=%d\n", c, j, 1556 chans[1].samples[c][j].temp, 1557 chans[1].samples[c][j].gain, 1558 chans[1].samples[c][j].power, 1559 chans[1].samples[c][j].pa_det); 1560 } 1561 } 1562 } 1563 #endif 1564 1565 static void 1566 iwn5000_read_eeprom(struct iwn_softc *sc) 1567 { 1568 struct iwn5000_eeprom_calib_hdr hdr; 1569 int32_t volt; 1570 uint32_t base, addr; 1571 uint16_t val; 1572 int i; 1573 1574 /* Read regulatory domain (4 ASCII characters). */ 1575 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1576 base = le16toh(val); 1577 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1578 sc->eeprom_domain, 4); 1579 1580 /* Read the list of authorized channels (20MHz ones only). */ 1581 for (i = 0; i < 5; i++) { 1582 addr = base + iwn5000_regulatory_bands[i]; 1583 iwn_read_eeprom_channels(sc, i, addr); 1584 } 1585 1586 /* Read enhanced TX power information for 6000 Series. */ 1587 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1588 iwn_read_eeprom_enhinfo(sc); 1589 1590 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1591 base = le16toh(val); 1592 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1593 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1594 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1595 sc->calib_ver = hdr.version; 1596 1597 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1598 /* Compute temperature offset. */ 1599 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1600 sc->eeprom_temp = le16toh(val); 1601 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1602 volt = le16toh(val); 1603 sc->temp_off = sc->eeprom_temp - (volt / -5); 1604 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1605 sc->eeprom_temp, volt, sc->temp_off)); 1606 } else { 1607 /* Read crystal calibration. */ 1608 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1609 &sc->eeprom_crystal, sizeof (uint32_t)); 1610 DPRINTF(("crystal calibration 0x%08x\n", 1611 le32toh(sc->eeprom_crystal))); 1612 } 1613 } 1614 1615 static void 1616 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1617 { 1618 struct ieee80211com *ic = &sc->sc_ic; 1619 const struct iwn_chan_band *band = &iwn_bands[n]; 1620 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1621 uint8_t chan; 1622 int i; 1623 1624 iwn_read_prom_data(sc, addr, channels, 1625 band->nchan * sizeof (struct iwn_eeprom_chan)); 1626 1627 for (i = 0; i < band->nchan; i++) { 1628 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1629 continue; 1630 1631 chan = band->chan[i]; 1632 1633 if (n == 0) { /* 2GHz band */ 1634 ic->ic_channels[chan].ic_freq = 1635 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1636 ic->ic_channels[chan].ic_flags = 1637 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1638 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1639 1640 } else { /* 5GHz band */ 1641 /* 1642 * Some adapters support channels 7, 8, 11 and 12 1643 * both in the 2GHz and 4.9GHz bands. 1644 * Because of limitations in our net80211 layer, 1645 * we don't support them in the 4.9GHz band. 1646 */ 1647 if (chan <= 14) 1648 continue; 1649 1650 ic->ic_channels[chan].ic_freq = 1651 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1652 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1653 /* We have at least one valid 5GHz channel. */ 1654 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1655 } 1656 1657 /* Is active scan allowed on this channel? */ 1658 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1659 ic->ic_channels[chan].ic_flags |= 1660 IEEE80211_CHAN_PASSIVE; 1661 } 1662 1663 /* Save maximum allowed TX power for this channel. */ 1664 sc->maxpwr[chan] = channels[i].maxpwr; 1665 1666 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1667 chan, channels[i].flags, sc->maxpwr[chan])); 1668 } 1669 } 1670 1671 static void 1672 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1673 { 1674 struct iwn_eeprom_enhinfo enhinfo[35]; 1675 uint16_t val, base; 1676 int8_t maxpwr; 1677 int i; 1678 1679 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1680 base = le16toh(val); 1681 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1682 enhinfo, sizeof enhinfo); 1683 1684 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1685 for (i = 0; i < __arraycount(enhinfo); i++) { 1686 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1687 continue; /* Skip invalid entries. */ 1688 1689 maxpwr = 0; 1690 if (sc->txchainmask & IWN_ANT_A) 1691 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1692 if (sc->txchainmask & IWN_ANT_B) 1693 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1694 if (sc->txchainmask & IWN_ANT_C) 1695 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1696 if (sc->ntxchains == 2) 1697 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1698 else if (sc->ntxchains == 3) 1699 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1700 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1701 1702 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1703 sc->enh_maxpwr[i] = maxpwr; 1704 } 1705 } 1706 1707 static struct ieee80211_node * 1708 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1709 { 1710 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1711 } 1712 1713 static void 1714 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1715 { 1716 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1717 struct iwn_node *wn = (void *)ni; 1718 uint8_t rate; 1719 int ridx, i; 1720 1721 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1722 /* Start at lowest available bit-rate, AMRR will raise. */ 1723 ni->ni_txrate = 0; 1724 1725 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1726 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1727 /* Map 802.11 rate to HW rate index. */ 1728 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1729 if (iwn_rates[ridx].rate == rate) 1730 break; 1731 wn->ridx[i] = ridx; 1732 } 1733 } 1734 1735 static int 1736 iwn_media_change(struct ifnet *ifp) 1737 { 1738 struct iwn_softc *sc = ifp->if_softc; 1739 struct ieee80211com *ic = &sc->sc_ic; 1740 uint8_t rate, ridx; 1741 int error; 1742 1743 error = ieee80211_media_change(ifp); 1744 if (error != ENETRESET) 1745 return error; 1746 1747 if (ic->ic_fixed_rate != -1) { 1748 rate = ic->ic_sup_rates[ic->ic_curmode]. 1749 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1750 /* Map 802.11 rate to HW rate index. */ 1751 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1752 if (iwn_rates[ridx].rate == rate) 1753 break; 1754 sc->fixed_ridx = ridx; 1755 } 1756 1757 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1758 (IFF_UP | IFF_RUNNING)) { 1759 iwn_stop(ifp, 0); 1760 error = iwn_init(ifp); 1761 } 1762 return error; 1763 } 1764 1765 static int 1766 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1767 { 1768 struct ifnet *ifp = ic->ic_ifp; 1769 struct iwn_softc *sc = ifp->if_softc; 1770 int error; 1771 1772 callout_stop(&sc->calib_to); 1773 1774 switch (nstate) { 1775 case IEEE80211_S_SCAN: 1776 /* XXX Do not abort a running scan. */ 1777 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1778 if (ic->ic_state != nstate) 1779 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1780 "while scanning(%d) ignored\n", nstate, 1781 ic->ic_state); 1782 break; 1783 } 1784 1785 /* XXX Not sure if call and flags are needed. */ 1786 ieee80211_node_table_reset(&ic->ic_scan); 1787 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1788 sc->sc_flags |= IWN_FLAG_SCANNING; 1789 1790 /* Make the link LED blink while we're scanning. */ 1791 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1792 1793 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1794 aprint_error_dev(sc->sc_dev, 1795 "could not initiate scan\n"); 1796 return error; 1797 } 1798 ic->ic_state = nstate; 1799 return 0; 1800 1801 case IEEE80211_S_ASSOC: 1802 if (ic->ic_state != IEEE80211_S_RUN) 1803 break; 1804 /* FALLTHROUGH */ 1805 case IEEE80211_S_AUTH: 1806 /* Reset state to handle reassociations correctly. */ 1807 sc->rxon.associd = 0; 1808 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1809 sc->calib.state = IWN_CALIB_STATE_INIT; 1810 1811 if ((error = iwn_auth(sc)) != 0) { 1812 aprint_error_dev(sc->sc_dev, 1813 "could not move to auth state\n"); 1814 return error; 1815 } 1816 break; 1817 1818 case IEEE80211_S_RUN: 1819 if ((error = iwn_run(sc)) != 0) { 1820 aprint_error_dev(sc->sc_dev, 1821 "could not move to run state\n"); 1822 return error; 1823 } 1824 break; 1825 1826 case IEEE80211_S_INIT: 1827 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1828 sc->calib.state = IWN_CALIB_STATE_INIT; 1829 break; 1830 } 1831 1832 return sc->sc_newstate(ic, nstate, arg); 1833 } 1834 1835 static void 1836 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1837 { 1838 struct iwn_softc *sc = arg; 1839 struct iwn_node *wn = (struct iwn_node *)ni; 1840 1841 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1842 } 1843 1844 static void 1845 iwn_calib_timeout(void *arg) 1846 { 1847 struct iwn_softc *sc = arg; 1848 struct ieee80211com *ic = &sc->sc_ic; 1849 int s; 1850 1851 s = splnet(); 1852 if (ic->ic_fixed_rate == -1) { 1853 if (ic->ic_opmode == IEEE80211_M_STA) 1854 iwn_iter_func(sc, ic->ic_bss); 1855 else 1856 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1857 } 1858 /* Force automatic TX power calibration every 60 secs. */ 1859 if (++sc->calib_cnt >= 120) { 1860 uint32_t flags = 0; 1861 1862 DPRINTF(("sending request for statistics\n")); 1863 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1864 sizeof flags, 1); 1865 sc->calib_cnt = 0; 1866 } 1867 splx(s); 1868 1869 /* Automatic rate control triggered every 500ms. */ 1870 callout_schedule(&sc->calib_to, hz/2); 1871 } 1872 1873 /* 1874 * Process an RX_PHY firmware notification. This is usually immediately 1875 * followed by an MPDU_RX_DONE notification. 1876 */ 1877 static void 1878 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1879 struct iwn_rx_data *data) 1880 { 1881 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1882 1883 DPRINTFN(2, ("received PHY stats\n")); 1884 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1885 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1886 1887 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1888 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1889 sc->last_rx_valid = 1; 1890 } 1891 1892 /* 1893 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1894 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1895 */ 1896 static void 1897 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1898 struct iwn_rx_data *data) 1899 { 1900 struct iwn_ops *ops = &sc->ops; 1901 struct ieee80211com *ic = &sc->sc_ic; 1902 struct ifnet *ifp = ic->ic_ifp; 1903 struct iwn_rx_ring *ring = &sc->rxq; 1904 struct ieee80211_frame *wh; 1905 struct ieee80211_node *ni; 1906 struct mbuf *m, *m1; 1907 struct iwn_rx_stat *stat; 1908 char *head; 1909 uint32_t flags; 1910 int error, len, rssi; 1911 1912 if (desc->type == IWN_MPDU_RX_DONE) { 1913 /* Check for prior RX_PHY notification. */ 1914 if (!sc->last_rx_valid) { 1915 DPRINTF(("missing RX_PHY\n")); 1916 return; 1917 } 1918 sc->last_rx_valid = 0; 1919 stat = &sc->last_rx_stat; 1920 } else 1921 stat = (struct iwn_rx_stat *)(desc + 1); 1922 1923 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1924 BUS_DMASYNC_POSTREAD); 1925 1926 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1927 aprint_error_dev(sc->sc_dev, 1928 "invalid RX statistic header\n"); 1929 return; 1930 } 1931 if (desc->type == IWN_MPDU_RX_DONE) { 1932 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1933 head = (char *)(mpdu + 1); 1934 len = le16toh(mpdu->len); 1935 } else { 1936 head = (char *)(stat + 1) + stat->cfg_phy_len; 1937 len = le16toh(stat->len); 1938 } 1939 1940 flags = le32toh(*(uint32_t *)(head + len)); 1941 1942 /* Discard frames with a bad FCS early. */ 1943 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 1944 DPRINTFN(2, ("RX flags error %x\n", flags)); 1945 ifp->if_ierrors++; 1946 return; 1947 } 1948 /* Discard frames that are too short. */ 1949 if (len < sizeof (*wh)) { 1950 DPRINTF(("frame too short: %d\n", len)); 1951 ic->ic_stats.is_rx_tooshort++; 1952 ifp->if_ierrors++; 1953 return; 1954 } 1955 1956 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1957 if (m1 == NULL) { 1958 ic->ic_stats.is_rx_nobuf++; 1959 ifp->if_ierrors++; 1960 return; 1961 } 1962 bus_dmamap_unload(sc->sc_dmat, data->map); 1963 1964 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 1965 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1966 if (error != 0) { 1967 m_freem(m1); 1968 1969 /* Try to reload the old mbuf. */ 1970 error = bus_dmamap_load(sc->sc_dmat, data->map, 1971 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1972 BUS_DMA_NOWAIT | BUS_DMA_READ); 1973 if (error != 0) { 1974 panic("%s: could not load old RX mbuf", 1975 device_xname(sc->sc_dev)); 1976 } 1977 /* Physical address may have changed. */ 1978 ring->desc[ring->cur] = 1979 htole32(data->map->dm_segs[0].ds_addr >> 8); 1980 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1981 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1982 BUS_DMASYNC_PREWRITE); 1983 ifp->if_ierrors++; 1984 return; 1985 } 1986 1987 m = data->m; 1988 data->m = m1; 1989 /* Update RX descriptor. */ 1990 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1991 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1992 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1993 BUS_DMASYNC_PREWRITE); 1994 1995 /* Finalize mbuf. */ 1996 m->m_pkthdr.rcvif = ifp; 1997 m->m_data = head; 1998 m->m_pkthdr.len = m->m_len = len; 1999 2000 /* Grab a reference to the source node. */ 2001 wh = mtod(m, struct ieee80211_frame *); 2002 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2003 2004 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2005 /* NetBSD does decryption in ieee80211_input. */ 2006 2007 rssi = ops->get_rssi(stat); 2008 2009 /* XXX Added for NetBSD: scans never stop without it */ 2010 if (ic->ic_state == IEEE80211_S_SCAN) 2011 iwn_fix_channel(ic, m); 2012 2013 if (sc->sc_drvbpf != NULL) { 2014 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2015 2016 tap->wr_flags = 0; 2017 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2018 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2019 tap->wr_chan_freq = 2020 htole16(ic->ic_channels[stat->chan].ic_freq); 2021 tap->wr_chan_flags = 2022 htole16(ic->ic_channels[stat->chan].ic_flags); 2023 tap->wr_dbm_antsignal = (int8_t)rssi; 2024 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2025 tap->wr_tsft = stat->tstamp; 2026 switch (stat->rate) { 2027 /* CCK rates. */ 2028 case 10: tap->wr_rate = 2; break; 2029 case 20: tap->wr_rate = 4; break; 2030 case 55: tap->wr_rate = 11; break; 2031 case 110: tap->wr_rate = 22; break; 2032 /* OFDM rates. */ 2033 case 0xd: tap->wr_rate = 12; break; 2034 case 0xf: tap->wr_rate = 18; break; 2035 case 0x5: tap->wr_rate = 24; break; 2036 case 0x7: tap->wr_rate = 36; break; 2037 case 0x9: tap->wr_rate = 48; break; 2038 case 0xb: tap->wr_rate = 72; break; 2039 case 0x1: tap->wr_rate = 96; break; 2040 case 0x3: tap->wr_rate = 108; break; 2041 /* Unknown rate: should not happen. */ 2042 default: tap->wr_rate = 0; 2043 } 2044 2045 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2046 } 2047 2048 /* Send the frame to the 802.11 layer. */ 2049 ieee80211_input(ic, m, ni, rssi, 0); 2050 2051 /* Node is no longer needed. */ 2052 ieee80211_free_node(ni); 2053 } 2054 2055 #ifndef IEEE80211_NO_HT 2056 /* Process an incoming Compressed BlockAck. */ 2057 static void 2058 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2059 struct iwn_rx_data *data) 2060 { 2061 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2062 struct iwn_tx_ring *txq; 2063 2064 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2065 BUS_DMASYNC_POSTREAD); 2066 2067 txq = &sc->txq[le16toh(ba->qid)]; 2068 /* XXX TBD */ 2069 } 2070 #endif 2071 2072 /* 2073 * Process a CALIBRATION_RESULT notification sent by the initialization 2074 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2075 */ 2076 static void 2077 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2078 struct iwn_rx_data *data) 2079 { 2080 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2081 int len, idx = -1; 2082 2083 /* Runtime firmware should not send such a notification. */ 2084 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2085 return; 2086 2087 len = (le32toh(desc->len) & 0x3fff) - 4; 2088 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2089 BUS_DMASYNC_POSTREAD); 2090 2091 switch (calib->code) { 2092 case IWN5000_PHY_CALIB_DC: 2093 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 2094 idx = 0; 2095 break; 2096 case IWN5000_PHY_CALIB_LO: 2097 idx = 1; 2098 break; 2099 case IWN5000_PHY_CALIB_TX_IQ: 2100 idx = 2; 2101 break; 2102 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2103 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2104 sc->hw_type != IWN_HW_REV_TYPE_5150) 2105 idx = 3; 2106 break; 2107 case IWN5000_PHY_CALIB_BASE_BAND: 2108 idx = 4; 2109 break; 2110 } 2111 if (idx == -1) /* Ignore other results. */ 2112 return; 2113 2114 /* Save calibration result. */ 2115 if (sc->calibcmd[idx].buf != NULL) 2116 free(sc->calibcmd[idx].buf, M_DEVBUF); 2117 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2118 if (sc->calibcmd[idx].buf == NULL) { 2119 DPRINTF(("not enough memory for calibration result %d\n", 2120 calib->code)); 2121 return; 2122 } 2123 DPRINTF(("saving calibration result code=%d len=%d\n", 2124 calib->code, len)); 2125 sc->calibcmd[idx].len = len; 2126 memcpy(sc->calibcmd[idx].buf, calib, len); 2127 } 2128 2129 /* 2130 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2131 * The latter is sent by the firmware after each received beacon. 2132 */ 2133 static void 2134 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2135 struct iwn_rx_data *data) 2136 { 2137 struct iwn_ops *ops = &sc->ops; 2138 struct ieee80211com *ic = &sc->sc_ic; 2139 struct iwn_calib_state *calib = &sc->calib; 2140 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2141 int temp; 2142 2143 /* Ignore statistics received during a scan. */ 2144 if (ic->ic_state != IEEE80211_S_RUN) 2145 return; 2146 2147 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2148 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2149 2150 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2151 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2152 2153 /* Test if temperature has changed. */ 2154 if (stats->general.temp != sc->rawtemp) { 2155 /* Convert "raw" temperature to degC. */ 2156 sc->rawtemp = stats->general.temp; 2157 temp = ops->get_temperature(sc); 2158 DPRINTFN(2, ("temperature=%dC\n", temp)); 2159 2160 /* Update TX power if need be (4965AGN only). */ 2161 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2162 iwn4965_power_calibration(sc, temp); 2163 } 2164 2165 if (desc->type != IWN_BEACON_STATISTICS) 2166 return; /* Reply to a statistics request. */ 2167 2168 sc->noise = iwn_get_noise(&stats->rx.general); 2169 2170 /* Test that RSSI and noise are present in stats report. */ 2171 if (le32toh(stats->rx.general.flags) != 1) { 2172 DPRINTF(("received statistics without RSSI\n")); 2173 return; 2174 } 2175 2176 if (calib->state == IWN_CALIB_STATE_ASSOC) 2177 iwn_collect_noise(sc, &stats->rx.general); 2178 else if (calib->state == IWN_CALIB_STATE_RUN) 2179 iwn_tune_sensitivity(sc, &stats->rx); 2180 } 2181 2182 /* 2183 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2184 * and 5000 adapters have different incompatible TX status formats. 2185 */ 2186 static void 2187 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2188 struct iwn_rx_data *data) 2189 { 2190 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2191 2192 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2193 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2194 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2195 } 2196 2197 static void 2198 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2199 struct iwn_rx_data *data) 2200 { 2201 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2202 2203 #ifdef notyet 2204 /* Reset TX scheduler slot. */ 2205 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2206 #endif 2207 2208 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2209 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2210 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2211 } 2212 2213 /* 2214 * Adapter-independent backend for TX_DONE firmware notifications. 2215 */ 2216 static void 2217 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2218 uint8_t status) 2219 { 2220 struct ieee80211com *ic = &sc->sc_ic; 2221 struct ifnet *ifp = ic->ic_ifp; 2222 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2223 struct iwn_tx_data *data = &ring->data[desc->idx]; 2224 struct iwn_node *wn = (struct iwn_node *)data->ni; 2225 2226 /* Update rate control statistics. */ 2227 wn->amn.amn_txcnt++; 2228 if (ackfailcnt > 0) 2229 wn->amn.amn_retrycnt++; 2230 2231 if (status != 1 && status != 2) 2232 ifp->if_oerrors++; 2233 else 2234 ifp->if_opackets++; 2235 2236 /* Unmap and free mbuf. */ 2237 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2238 BUS_DMASYNC_POSTWRITE); 2239 bus_dmamap_unload(sc->sc_dmat, data->map); 2240 m_freem(data->m); 2241 data->m = NULL; 2242 ieee80211_free_node(data->ni); 2243 data->ni = NULL; 2244 2245 sc->sc_tx_timer = 0; 2246 if (--ring->queued < IWN_TX_RING_LOMARK) { 2247 sc->qfullmsk &= ~(1 << ring->qid); 2248 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2249 ifp->if_flags &= ~IFF_OACTIVE; 2250 (*ifp->if_start)(ifp); 2251 } 2252 } 2253 } 2254 2255 /* 2256 * Process a "command done" firmware notification. This is where we wakeup 2257 * processes waiting for a synchronous command completion. 2258 */ 2259 static void 2260 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2261 { 2262 struct iwn_tx_ring *ring = &sc->txq[4]; 2263 struct iwn_tx_data *data; 2264 2265 if ((desc->qid & 0xf) != 4) 2266 return; /* Not a command ack. */ 2267 2268 data = &ring->data[desc->idx]; 2269 2270 /* If the command was mapped in an mbuf, free it. */ 2271 if (data->m != NULL) { 2272 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2273 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2274 bus_dmamap_unload(sc->sc_dmat, data->map); 2275 m_freem(data->m); 2276 data->m = NULL; 2277 } 2278 wakeup(&ring->desc[desc->idx]); 2279 } 2280 2281 /* 2282 * Process an INT_FH_RX or INT_SW_RX interrupt. 2283 */ 2284 static void 2285 iwn_notif_intr(struct iwn_softc *sc) 2286 { 2287 struct iwn_ops *ops = &sc->ops; 2288 struct ieee80211com *ic = &sc->sc_ic; 2289 struct ifnet *ifp = ic->ic_ifp; 2290 uint16_t hw; 2291 2292 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2293 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2294 2295 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2296 while (sc->rxq.cur != hw) { 2297 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2298 struct iwn_rx_desc *desc; 2299 2300 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2301 BUS_DMASYNC_POSTREAD); 2302 desc = mtod(data->m, struct iwn_rx_desc *); 2303 2304 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2305 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2306 2307 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2308 iwn_cmd_done(sc, desc); 2309 2310 switch (desc->type) { 2311 case IWN_RX_PHY: 2312 iwn_rx_phy(sc, desc, data); 2313 break; 2314 2315 case IWN_RX_DONE: /* 4965AGN only. */ 2316 case IWN_MPDU_RX_DONE: 2317 /* An 802.11 frame has been received. */ 2318 iwn_rx_done(sc, desc, data); 2319 break; 2320 #ifndef IEEE80211_NO_HT 2321 case IWN_RX_COMPRESSED_BA: 2322 /* A Compressed BlockAck has been received. */ 2323 iwn_rx_compressed_ba(sc, desc, data); 2324 break; 2325 #endif 2326 case IWN_TX_DONE: 2327 /* An 802.11 frame has been transmitted. */ 2328 ops->tx_done(sc, desc, data); 2329 break; 2330 2331 case IWN_RX_STATISTICS: 2332 case IWN_BEACON_STATISTICS: 2333 iwn_rx_statistics(sc, desc, data); 2334 break; 2335 2336 case IWN_BEACON_MISSED: 2337 { 2338 struct iwn_beacon_missed *miss = 2339 (struct iwn_beacon_missed *)(desc + 1); 2340 2341 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2342 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2343 /* 2344 * If more than 5 consecutive beacons are missed, 2345 * reinitialize the sensitivity state machine. 2346 */ 2347 DPRINTF(("beacons missed %d/%d\n", 2348 le32toh(miss->consecutive), le32toh(miss->total))); 2349 if (ic->ic_state == IEEE80211_S_RUN && 2350 le32toh(miss->consecutive) > 5) 2351 (void)iwn_init_sensitivity(sc); 2352 break; 2353 } 2354 case IWN_UC_READY: 2355 { 2356 struct iwn_ucode_info *uc = 2357 (struct iwn_ucode_info *)(desc + 1); 2358 2359 /* The microcontroller is ready. */ 2360 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2361 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2362 DPRINTF(("microcode alive notification version=%d.%d " 2363 "subtype=%x alive=%x\n", uc->major, uc->minor, 2364 uc->subtype, le32toh(uc->valid))); 2365 2366 if (le32toh(uc->valid) != 1) { 2367 aprint_error_dev(sc->sc_dev, 2368 "microcontroller initialization " 2369 "failed\n"); 2370 break; 2371 } 2372 if (uc->subtype == IWN_UCODE_INIT) { 2373 /* Save microcontroller report. */ 2374 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2375 } 2376 /* Save the address of the error log in SRAM. */ 2377 sc->errptr = le32toh(uc->errptr); 2378 break; 2379 } 2380 case IWN_STATE_CHANGED: 2381 { 2382 uint32_t *status = (uint32_t *)(desc + 1); 2383 2384 /* Enabled/disabled notification. */ 2385 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2386 sizeof (*status), BUS_DMASYNC_POSTREAD); 2387 DPRINTF(("state changed to %x\n", le32toh(*status))); 2388 2389 if (le32toh(*status) & 1) { 2390 /* The radio button has to be pushed. */ 2391 aprint_error_dev(sc->sc_dev, 2392 "Radio transmitter is off\n"); 2393 /* Turn the interface down. */ 2394 ifp->if_flags &= ~IFF_UP; 2395 iwn_stop(ifp, 1); 2396 return; /* No further processing. */ 2397 } 2398 break; 2399 } 2400 case IWN_START_SCAN: 2401 { 2402 struct iwn_start_scan *scan = 2403 (struct iwn_start_scan *)(desc + 1); 2404 2405 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2406 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2407 DPRINTFN(2, ("scanning channel %d status %x\n", 2408 scan->chan, le32toh(scan->status))); 2409 2410 /* Fix current channel. */ 2411 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2412 break; 2413 } 2414 case IWN_STOP_SCAN: 2415 { 2416 struct iwn_stop_scan *scan = 2417 (struct iwn_stop_scan *)(desc + 1); 2418 2419 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2420 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2421 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2422 scan->nchan, scan->status, scan->chan)); 2423 2424 if (scan->status == 1 && scan->chan <= 14 && 2425 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2426 /* 2427 * We just finished scanning 2GHz channels, 2428 * start scanning 5GHz ones. 2429 */ 2430 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2431 break; 2432 } 2433 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2434 ieee80211_end_scan(ic); 2435 break; 2436 } 2437 case IWN5000_CALIBRATION_RESULT: 2438 iwn5000_rx_calib_results(sc, desc, data); 2439 break; 2440 2441 case IWN5000_CALIBRATION_DONE: 2442 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2443 wakeup(sc); 2444 break; 2445 } 2446 2447 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2448 } 2449 2450 /* Tell the firmware what we have processed. */ 2451 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2452 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2453 } 2454 2455 /* 2456 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2457 * from power-down sleep mode. 2458 */ 2459 static void 2460 iwn_wakeup_intr(struct iwn_softc *sc) 2461 { 2462 int qid; 2463 2464 DPRINTF(("ucode wakeup from power-down sleep\n")); 2465 2466 /* Wakeup RX and TX rings. */ 2467 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2468 for (qid = 0; qid < sc->ntxqs; qid++) { 2469 struct iwn_tx_ring *ring = &sc->txq[qid]; 2470 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2471 } 2472 } 2473 2474 /* 2475 * Dump the error log of the firmware when a firmware panic occurs. Although 2476 * we can't debug the firmware because it is neither open source nor free, it 2477 * can help us to identify certain classes of problems. 2478 */ 2479 static void 2480 iwn_fatal_intr(struct iwn_softc *sc) 2481 { 2482 struct iwn_fw_dump dump; 2483 int i; 2484 2485 /* Force a complete recalibration on next init. */ 2486 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2487 2488 /* Check that the error log address is valid. */ 2489 if (sc->errptr < IWN_FW_DATA_BASE || 2490 sc->errptr + sizeof (dump) > 2491 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2492 aprint_error_dev(sc->sc_dev, 2493 "bad firmware error log address 0x%08x\n", sc->errptr); 2494 return; 2495 } 2496 if (iwn_nic_lock(sc) != 0) { 2497 aprint_error_dev(sc->sc_dev, 2498 "could not read firmware error log\n"); 2499 return; 2500 } 2501 /* Read firmware error log from SRAM. */ 2502 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2503 sizeof (dump) / sizeof (uint32_t)); 2504 iwn_nic_unlock(sc); 2505 2506 if (dump.valid == 0) { 2507 aprint_error_dev(sc->sc_dev, 2508 "firmware error log is empty\n"); 2509 return; 2510 } 2511 aprint_error("firmware error log:\n"); 2512 aprint_error(" error type = \"%s\" (0x%08X)\n", 2513 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2514 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2515 dump.id); 2516 aprint_error(" program counter = 0x%08X\n", dump.pc); 2517 aprint_error(" source line = 0x%08X\n", dump.src_line); 2518 aprint_error(" error data = 0x%08X%08X\n", 2519 dump.error_data[0], dump.error_data[1]); 2520 aprint_error(" branch link = 0x%08X%08X\n", 2521 dump.branch_link[0], dump.branch_link[1]); 2522 aprint_error(" interrupt link = 0x%08X%08X\n", 2523 dump.interrupt_link[0], dump.interrupt_link[1]); 2524 aprint_error(" time = %u\n", dump.time[0]); 2525 2526 /* Dump driver status (TX and RX rings) while we're here. */ 2527 aprint_error("driver status:\n"); 2528 for (i = 0; i < sc->ntxqs; i++) { 2529 struct iwn_tx_ring *ring = &sc->txq[i]; 2530 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2531 i, ring->qid, ring->cur, ring->queued); 2532 } 2533 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2534 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2535 } 2536 2537 static int 2538 iwn_intr(void *arg) 2539 { 2540 struct iwn_softc *sc = arg; 2541 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2542 uint32_t r1, r2, tmp; 2543 2544 /* Disable interrupts. */ 2545 IWN_WRITE(sc, IWN_INT_MASK, 0); 2546 2547 /* Read interrupts from ICT (fast) or from registers (slow). */ 2548 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2549 tmp = 0; 2550 while (sc->ict[sc->ict_cur] != 0) { 2551 tmp |= sc->ict[sc->ict_cur]; 2552 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2553 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2554 } 2555 tmp = le32toh(tmp); 2556 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2557 tmp = 0; 2558 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2559 tmp |= 0x8000; 2560 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2561 r2 = 0; /* Unused. */ 2562 } else { 2563 r1 = IWN_READ(sc, IWN_INT); 2564 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2565 return 0; /* Hardware gone! */ 2566 r2 = IWN_READ(sc, IWN_FH_INT); 2567 } 2568 if (r1 == 0 && r2 == 0) { 2569 if (ifp->if_flags & IFF_UP) 2570 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2571 return 0; /* Interrupt not for us. */ 2572 } 2573 2574 /* Acknowledge interrupts. */ 2575 IWN_WRITE(sc, IWN_INT, r1); 2576 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2577 IWN_WRITE(sc, IWN_FH_INT, r2); 2578 2579 if (r1 & IWN_INT_RF_TOGGLED) { 2580 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2581 aprint_error_dev(sc->sc_dev, 2582 "RF switch: radio %s\n", 2583 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2584 } 2585 if (r1 & IWN_INT_CT_REACHED) { 2586 aprint_error_dev(sc->sc_dev, 2587 "critical temperature reached!\n"); 2588 } 2589 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2590 aprint_error_dev(sc->sc_dev, 2591 "fatal firmware error\n"); 2592 /* Dump firmware error log and stop. */ 2593 iwn_fatal_intr(sc); 2594 ifp->if_flags &= ~IFF_UP; 2595 iwn_stop(ifp, 1); 2596 return 1; 2597 } 2598 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2599 (r2 & IWN_FH_INT_RX)) { 2600 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2601 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2602 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2603 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2604 IWN_INT_PERIODIC_DIS); 2605 iwn_notif_intr(sc); 2606 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2607 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2608 IWN_INT_PERIODIC_ENA); 2609 } 2610 } else 2611 iwn_notif_intr(sc); 2612 } 2613 2614 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2615 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2616 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2617 wakeup(sc); /* FH DMA transfer completed. */ 2618 } 2619 2620 if (r1 & IWN_INT_ALIVE) 2621 wakeup(sc); /* Firmware is alive. */ 2622 2623 if (r1 & IWN_INT_WAKEUP) 2624 iwn_wakeup_intr(sc); 2625 2626 /* Re-enable interrupts. */ 2627 if (ifp->if_flags & IFF_UP) 2628 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2629 2630 return 1; 2631 } 2632 2633 /* 2634 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2635 * 5000 adapters use a slightly different format). 2636 */ 2637 static void 2638 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2639 uint16_t len) 2640 { 2641 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2642 2643 *w = htole16(len + 8); 2644 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2645 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2646 sizeof (uint16_t), 2647 BUS_DMASYNC_PREWRITE); 2648 if (idx < IWN_SCHED_WINSZ) { 2649 *(w + IWN_TX_RING_COUNT) = *w; 2650 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2651 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2652 (char *)(void *)sc->sched_dma.vaddr, 2653 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2654 } 2655 } 2656 2657 static void 2658 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2659 uint16_t len) 2660 { 2661 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2662 2663 *w = htole16(id << 12 | (len + 8)); 2664 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2665 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2666 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2667 if (idx < IWN_SCHED_WINSZ) { 2668 *(w + IWN_TX_RING_COUNT) = *w; 2669 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2670 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2671 (char *)(void *)sc->sched_dma.vaddr, 2672 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2673 } 2674 } 2675 2676 #ifdef notyet 2677 static void 2678 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2679 { 2680 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2681 2682 *w = (*w & htole16(0xf000)) | htole16(1); 2683 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2684 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2685 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2686 if (idx < IWN_SCHED_WINSZ) { 2687 *(w + IWN_TX_RING_COUNT) = *w; 2688 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2689 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2690 (char *)(void *)sc->sched_dma.vaddr, 2691 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2692 } 2693 } 2694 #endif 2695 2696 static int 2697 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2698 { 2699 struct ieee80211com *ic = &sc->sc_ic; 2700 struct iwn_node *wn = (void *)ni; 2701 struct iwn_tx_ring *ring; 2702 struct iwn_tx_desc *desc; 2703 struct iwn_tx_data *data; 2704 struct iwn_tx_cmd *cmd; 2705 struct iwn_cmd_data *tx; 2706 const struct iwn_rate *rinfo; 2707 struct ieee80211_frame *wh; 2708 struct ieee80211_key *k = NULL; 2709 struct mbuf *m1; 2710 uint32_t flags; 2711 u_int hdrlen; 2712 bus_dma_segment_t *seg; 2713 uint8_t tid, ridx, txant, type; 2714 int i, totlen, error, pad; 2715 2716 const struct chanAccParams *cap; 2717 int noack; 2718 int hdrlen2; 2719 2720 wh = mtod(m, struct ieee80211_frame *); 2721 hdrlen = ieee80211_anyhdrsize(wh); 2722 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2723 2724 hdrlen2 = (IEEE80211_QOS_HAS_SEQ(wh)) ? 2725 sizeof (struct ieee80211_qosframe) : 2726 sizeof (struct ieee80211_frame); 2727 2728 if (hdrlen != hdrlen2) 2729 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2730 hdrlen, hdrlen2); 2731 2732 /* XXX OpenBSD sets a different tid when using QOS */ 2733 tid = 0; 2734 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2735 cap = &ic->ic_wme.wme_chanParams; 2736 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2737 } 2738 else 2739 noack = 0; 2740 2741 ring = &sc->txq[ac]; 2742 desc = &ring->desc[ring->cur]; 2743 data = &ring->data[ring->cur]; 2744 2745 /* Choose a TX rate index. */ 2746 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2747 type != IEEE80211_FC0_TYPE_DATA) { 2748 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2749 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2750 } else if (ic->ic_fixed_rate != -1) { 2751 ridx = sc->fixed_ridx; 2752 } else 2753 ridx = wn->ridx[ni->ni_txrate]; 2754 rinfo = &iwn_rates[ridx]; 2755 2756 /* Encrypt the frame if need be. */ 2757 /* 2758 * XXX For now, NetBSD swaps the encryption and bpf sections 2759 * in order to match old code and other drivers. Tests with 2760 * tcpdump indicates that the order is irrelevant, however, 2761 * as bpf produces unencrypted data for both ordering choices. 2762 */ 2763 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2764 k = ieee80211_crypto_encap(ic, ni, m); 2765 if (k == NULL) { 2766 m_freem(m); 2767 return ENOBUFS; 2768 } 2769 /* Packet header may have moved, reset our local pointer. */ 2770 wh = mtod(m, struct ieee80211_frame *); 2771 } 2772 totlen = m->m_pkthdr.len; 2773 2774 if (sc->sc_drvbpf != NULL) { 2775 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2776 2777 tap->wt_flags = 0; 2778 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2779 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2780 tap->wt_rate = rinfo->rate; 2781 tap->wt_hwqueue = ac; 2782 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2783 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2784 2785 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2786 } 2787 2788 /* Prepare TX firmware command. */ 2789 cmd = &ring->cmd[ring->cur]; 2790 cmd->code = IWN_CMD_TX_DATA; 2791 cmd->flags = 0; 2792 cmd->qid = ring->qid; 2793 cmd->idx = ring->cur; 2794 2795 tx = (struct iwn_cmd_data *)cmd->data; 2796 /* NB: No need to clear tx, all fields are reinitialized here. */ 2797 tx->scratch = 0; /* clear "scratch" area */ 2798 2799 flags = 0; 2800 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2801 /* Unicast frame, check if an ACK is expected. */ 2802 if (!noack) 2803 flags |= IWN_TX_NEED_ACK; 2804 } 2805 2806 #ifdef notyet 2807 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2808 if ((wh->i_fc[0] & 2809 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2810 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2811 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2812 #endif 2813 2814 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2815 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2816 2817 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2818 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2819 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2820 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2821 flags |= IWN_TX_NEED_RTS; 2822 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2823 ridx >= IWN_RIDX_OFDM6) { 2824 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2825 flags |= IWN_TX_NEED_CTS; 2826 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2827 flags |= IWN_TX_NEED_RTS; 2828 } 2829 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2830 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2831 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2832 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2833 flags |= IWN_TX_NEED_PROTECTION; 2834 } else 2835 flags |= IWN_TX_FULL_TXOP; 2836 } 2837 } 2838 2839 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2840 type != IEEE80211_FC0_TYPE_DATA) 2841 tx->id = sc->broadcast_id; 2842 else 2843 tx->id = wn->id; 2844 2845 if (type == IEEE80211_FC0_TYPE_MGT) { 2846 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2847 2848 #ifndef IEEE80211_STA_ONLY 2849 /* Tell HW to set timestamp in probe responses. */ 2850 /* XXX NetBSD rev 1.11 added probe requests here but */ 2851 /* probe requests do not take timestamps (from Bergamini). */ 2852 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2853 flags |= IWN_TX_INSERT_TSTAMP; 2854 #endif 2855 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2856 /* changes here. These are not needed (from Bergamini). */ 2857 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2858 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2859 tx->timeout = htole16(3); 2860 else 2861 tx->timeout = htole16(2); 2862 } else 2863 tx->timeout = htole16(0); 2864 2865 if (hdrlen & 3) { 2866 /* First segment length must be a multiple of 4. */ 2867 flags |= IWN_TX_NEED_PADDING; 2868 pad = 4 - (hdrlen & 3); 2869 } else 2870 pad = 0; 2871 2872 tx->len = htole16(totlen); 2873 tx->tid = tid; 2874 tx->rts_ntries = 60; 2875 tx->data_ntries = 15; 2876 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2877 tx->plcp = rinfo->plcp; 2878 tx->rflags = rinfo->flags; 2879 if (tx->id == sc->broadcast_id) { 2880 /* Group or management frame. */ 2881 tx->linkq = 0; 2882 /* XXX Alternate between antenna A and B? */ 2883 txant = IWN_LSB(sc->txchainmask); 2884 tx->rflags |= IWN_RFLAG_ANT(txant); 2885 } else { 2886 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2887 flags |= IWN_TX_LINKQ; /* enable MRR */ 2888 } 2889 /* Set physical address of "scratch area". */ 2890 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2891 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2892 2893 /* Copy 802.11 header in TX command. */ 2894 /* XXX NetBSD changed this in rev 1.20 */ 2895 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2896 2897 /* Trim 802.11 header. */ 2898 m_adj(m, hdrlen); 2899 tx->security = 0; 2900 tx->flags = htole32(flags); 2901 2902 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2903 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2904 if (error != 0) { 2905 if (error != EFBIG) { 2906 aprint_error_dev(sc->sc_dev, 2907 "can't map mbuf (error %d)\n", error); 2908 m_freem(m); 2909 return error; 2910 } 2911 /* Too many DMA segments, linearize mbuf. */ 2912 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2913 if (m1 == NULL) { 2914 m_freem(m); 2915 return ENOBUFS; 2916 } 2917 if (m->m_pkthdr.len > MHLEN) { 2918 MCLGET(m1, M_DONTWAIT); 2919 if (!(m1->m_flags & M_EXT)) { 2920 m_freem(m); 2921 m_freem(m1); 2922 return ENOBUFS; 2923 } 2924 } 2925 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2926 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2927 m_freem(m); 2928 m = m1; 2929 2930 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2931 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2932 if (error != 0) { 2933 aprint_error_dev(sc->sc_dev, 2934 "can't map mbuf (error %d)\n", error); 2935 m_freem(m); 2936 return error; 2937 } 2938 } 2939 2940 data->m = m; 2941 data->ni = ni; 2942 2943 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 2944 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 2945 2946 /* Fill TX descriptor. */ 2947 desc->nsegs = 1 + data->map->dm_nsegs; 2948 /* First DMA segment is used by the TX command. */ 2949 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 2950 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 2951 (4 + sizeof (*tx) + hdrlen + pad) << 4); 2952 /* Other DMA segments are for data payload. */ 2953 seg = data->map->dm_segs; 2954 for (i = 1; i <= data->map->dm_nsegs; i++) { 2955 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 2956 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 2957 seg->ds_len << 4); 2958 seg++; 2959 } 2960 2961 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2962 BUS_DMASYNC_PREWRITE); 2963 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 2964 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 2965 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 2966 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2967 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 2968 sizeof (*desc), BUS_DMASYNC_PREWRITE); 2969 2970 #ifdef notyet 2971 /* Update TX scheduler. */ 2972 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 2973 #endif 2974 2975 /* Kick TX ring. */ 2976 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 2977 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 2978 2979 /* Mark TX ring as full if we reach a certain threshold. */ 2980 if (++ring->queued > IWN_TX_RING_HIMARK) 2981 sc->qfullmsk |= 1 << ring->qid; 2982 2983 return 0; 2984 } 2985 2986 static void 2987 iwn_start(struct ifnet *ifp) 2988 { 2989 struct iwn_softc *sc = ifp->if_softc; 2990 struct ieee80211com *ic = &sc->sc_ic; 2991 struct ieee80211_node *ni; 2992 struct ether_header *eh; 2993 struct mbuf *m; 2994 int ac; 2995 2996 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2997 return; 2998 2999 for (;;) { 3000 if (sc->qfullmsk != 0) { 3001 ifp->if_flags |= IFF_OACTIVE; 3002 break; 3003 } 3004 /* Send pending management frames first. */ 3005 IF_DEQUEUE(&ic->ic_mgtq, m); 3006 if (m != NULL) { 3007 ni = (void *)m->m_pkthdr.rcvif; 3008 ac = 0; 3009 goto sendit; 3010 } 3011 if (ic->ic_state != IEEE80211_S_RUN) 3012 break; 3013 3014 /* Encapsulate and send data frames. */ 3015 IFQ_DEQUEUE(&ifp->if_snd, m); 3016 if (m == NULL) 3017 break; 3018 if (m->m_len < sizeof (*eh) && 3019 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3020 ifp->if_oerrors++; 3021 continue; 3022 } 3023 eh = mtod(m, struct ether_header *); 3024 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3025 if (ni == NULL) { 3026 m_freem(m); 3027 ifp->if_oerrors++; 3028 continue; 3029 } 3030 /* classify mbuf so we can find which tx ring to use */ 3031 if (ieee80211_classify(ic, m, ni) != 0) { 3032 m_freem(m); 3033 ieee80211_free_node(ni); 3034 ifp->if_oerrors++; 3035 continue; 3036 } 3037 3038 /* No QoS encapsulation for EAPOL frames. */ 3039 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3040 M_WME_GETAC(m) : WME_AC_BE; 3041 3042 bpf_mtap(ifp, m); 3043 3044 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3045 ieee80211_free_node(ni); 3046 ifp->if_oerrors++; 3047 continue; 3048 } 3049 sendit: 3050 bpf_mtap3(ic->ic_rawbpf, m); 3051 3052 if (iwn_tx(sc, m, ni, ac) != 0) { 3053 ieee80211_free_node(ni); 3054 ifp->if_oerrors++; 3055 continue; 3056 } 3057 3058 sc->sc_tx_timer = 5; 3059 ifp->if_timer = 1; 3060 } 3061 } 3062 3063 static void 3064 iwn_watchdog(struct ifnet *ifp) 3065 { 3066 struct iwn_softc *sc = ifp->if_softc; 3067 3068 ifp->if_timer = 0; 3069 3070 if (sc->sc_tx_timer > 0) { 3071 if (--sc->sc_tx_timer == 0) { 3072 aprint_error_dev(sc->sc_dev, 3073 "device timeout\n"); 3074 ifp->if_flags &= ~IFF_UP; 3075 iwn_stop(ifp, 1); 3076 ifp->if_oerrors++; 3077 return; 3078 } 3079 ifp->if_timer = 1; 3080 } 3081 3082 ieee80211_watchdog(&sc->sc_ic); 3083 } 3084 3085 static int 3086 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3087 { 3088 struct iwn_softc *sc = ifp->if_softc; 3089 struct ieee80211com *ic = &sc->sc_ic; 3090 struct ifaddr *ifa; 3091 const struct sockaddr *sa; 3092 int s, error = 0; 3093 3094 s = splnet(); 3095 3096 switch (cmd) { 3097 case SIOCSIFADDR: 3098 ifa = (struct ifaddr *)data; 3099 ifp->if_flags |= IFF_UP; 3100 #ifdef INET 3101 if (ifa->ifa_addr->sa_family == AF_INET) 3102 arp_ifinit(&ic->ic_ac, ifa); 3103 #endif 3104 /* FALLTHROUGH */ 3105 case SIOCSIFFLAGS: 3106 /* XXX Added as it is in every NetBSD driver */ 3107 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3108 break; 3109 if (ifp->if_flags & IFF_UP) { 3110 if (!(ifp->if_flags & IFF_RUNNING)) 3111 error = iwn_init(ifp); 3112 } else { 3113 if (ifp->if_flags & IFF_RUNNING) 3114 iwn_stop(ifp, 1); 3115 } 3116 break; 3117 3118 case SIOCADDMULTI: 3119 case SIOCDELMULTI: 3120 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3121 error = (cmd == SIOCADDMULTI) ? 3122 ether_addmulti(sa, &sc->sc_ec) : 3123 ether_delmulti(sa, &sc->sc_ec); 3124 3125 if (error == ENETRESET) 3126 error = 0; 3127 break; 3128 3129 default: 3130 error = ieee80211_ioctl(ic, cmd, data); 3131 } 3132 3133 if (error == ENETRESET) { 3134 error = 0; 3135 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3136 (IFF_UP | IFF_RUNNING)) { 3137 iwn_stop(ifp, 0); 3138 error = iwn_init(ifp); 3139 } 3140 } 3141 3142 splx(s); 3143 return error; 3144 } 3145 3146 /* 3147 * Send a command to the firmware. 3148 */ 3149 static int 3150 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3151 { 3152 struct iwn_tx_ring *ring = &sc->txq[4]; 3153 struct iwn_tx_desc *desc; 3154 struct iwn_tx_data *data; 3155 struct iwn_tx_cmd *cmd; 3156 struct mbuf *m; 3157 bus_addr_t paddr; 3158 int totlen, error; 3159 3160 desc = &ring->desc[ring->cur]; 3161 data = &ring->data[ring->cur]; 3162 totlen = 4 + size; 3163 3164 if (size > sizeof cmd->data) { 3165 /* Command is too large to fit in a descriptor. */ 3166 if (totlen > MCLBYTES) 3167 return EINVAL; 3168 MGETHDR(m, M_DONTWAIT, MT_DATA); 3169 if (m == NULL) 3170 return ENOMEM; 3171 if (totlen > MHLEN) { 3172 MCLGET(m, M_DONTWAIT); 3173 if (!(m->m_flags & M_EXT)) { 3174 m_freem(m); 3175 return ENOMEM; 3176 } 3177 } 3178 cmd = mtod(m, struct iwn_tx_cmd *); 3179 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3180 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3181 if (error != 0) { 3182 m_freem(m); 3183 return error; 3184 } 3185 data->m = m; 3186 paddr = data->map->dm_segs[0].ds_addr; 3187 } else { 3188 cmd = &ring->cmd[ring->cur]; 3189 paddr = data->cmd_paddr; 3190 } 3191 3192 cmd->code = code; 3193 cmd->flags = 0; 3194 cmd->qid = ring->qid; 3195 cmd->idx = ring->cur; 3196 memcpy(cmd->data, buf, size); 3197 3198 desc->nsegs = 1; 3199 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3200 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3201 3202 if (size > sizeof cmd->data) { 3203 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3204 BUS_DMASYNC_PREWRITE); 3205 } else { 3206 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3207 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3208 totlen, BUS_DMASYNC_PREWRITE); 3209 } 3210 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3211 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3212 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3213 3214 #ifdef notyet 3215 /* Update TX scheduler. */ 3216 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3217 #endif 3218 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3219 3220 /* Kick command ring. */ 3221 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3222 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3223 3224 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3225 } 3226 3227 static int 3228 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3229 { 3230 struct iwn4965_node_info hnode; 3231 char *src, *dst; 3232 3233 /* 3234 * We use the node structure for 5000 Series internally (it is 3235 * a superset of the one for 4965AGN). We thus copy the common 3236 * fields before sending the command. 3237 */ 3238 src = (char *)node; 3239 dst = (char *)&hnode; 3240 memcpy(dst, src, 48); 3241 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3242 memcpy(dst + 48, src + 72, 20); 3243 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3244 } 3245 3246 static int 3247 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3248 { 3249 /* Direct mapping. */ 3250 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3251 } 3252 3253 static int 3254 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3255 { 3256 struct iwn_node *wn = (void *)ni; 3257 struct ieee80211_rateset *rs = &ni->ni_rates; 3258 struct iwn_cmd_link_quality linkq; 3259 const struct iwn_rate *rinfo; 3260 uint8_t txant; 3261 int i, txrate; 3262 3263 /* Use the first valid TX antenna. */ 3264 txant = IWN_LSB(sc->txchainmask); 3265 3266 memset(&linkq, 0, sizeof linkq); 3267 linkq.id = wn->id; 3268 linkq.antmsk_1stream = txant; 3269 linkq.antmsk_2stream = IWN_ANT_AB; 3270 linkq.ampdu_max = 31; 3271 linkq.ampdu_threshold = 3; 3272 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3273 3274 /* Start at highest available bit-rate. */ 3275 txrate = rs->rs_nrates - 1; 3276 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3277 rinfo = &iwn_rates[wn->ridx[txrate]]; 3278 linkq.retry[i].plcp = rinfo->plcp; 3279 linkq.retry[i].rflags = rinfo->flags; 3280 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3281 /* Next retry at immediate lower bit-rate. */ 3282 if (txrate > 0) 3283 txrate--; 3284 } 3285 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3286 } 3287 3288 /* 3289 * Broadcast node is used to send group-addressed and management frames. 3290 */ 3291 static int 3292 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3293 { 3294 struct iwn_ops *ops = &sc->ops; 3295 struct iwn_node_info node; 3296 struct iwn_cmd_link_quality linkq; 3297 const struct iwn_rate *rinfo; 3298 uint8_t txant; 3299 int i, error; 3300 3301 memset(&node, 0, sizeof node); 3302 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3303 node.id = sc->broadcast_id; 3304 DPRINTF(("adding broadcast node\n")); 3305 if ((error = ops->add_node(sc, &node, async)) != 0) 3306 return error; 3307 3308 /* Use the first valid TX antenna. */ 3309 txant = IWN_LSB(sc->txchainmask); 3310 3311 memset(&linkq, 0, sizeof linkq); 3312 linkq.id = sc->broadcast_id; 3313 linkq.antmsk_1stream = txant; 3314 linkq.antmsk_2stream = IWN_ANT_AB; 3315 linkq.ampdu_max = 64; 3316 linkq.ampdu_threshold = 3; 3317 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3318 3319 /* Use lowest mandatory bit-rate. */ 3320 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3321 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3322 linkq.retry[0].plcp = rinfo->plcp; 3323 linkq.retry[0].rflags = rinfo->flags; 3324 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3325 /* Use same bit-rate for all TX retries. */ 3326 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3327 linkq.retry[i].plcp = linkq.retry[0].plcp; 3328 linkq.retry[i].rflags = linkq.retry[0].rflags; 3329 } 3330 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3331 } 3332 3333 static void 3334 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3335 { 3336 struct iwn_cmd_led led; 3337 3338 /* Clear microcode LED ownership. */ 3339 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3340 3341 led.which = which; 3342 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3343 led.off = off; 3344 led.on = on; 3345 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3346 } 3347 3348 /* 3349 * Set the critical temperature at which the firmware will stop the radio 3350 * and notify us. 3351 */ 3352 static int 3353 iwn_set_critical_temp(struct iwn_softc *sc) 3354 { 3355 struct iwn_critical_temp crit; 3356 int32_t temp; 3357 3358 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3359 3360 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3361 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3362 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3363 temp = IWN_CTOK(110); 3364 else 3365 temp = 110; 3366 memset(&crit, 0, sizeof crit); 3367 crit.tempR = htole32(temp); 3368 DPRINTF(("setting critical temperature to %d\n", temp)); 3369 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3370 } 3371 3372 static int 3373 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3374 { 3375 struct iwn_cmd_timing cmd; 3376 uint64_t val, mod; 3377 3378 memset(&cmd, 0, sizeof cmd); 3379 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3380 cmd.bintval = htole16(ni->ni_intval); 3381 cmd.lintval = htole16(10); 3382 3383 /* Compute remaining time until next beacon. */ 3384 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3385 mod = le64toh(cmd.tstamp) % val; 3386 cmd.binitval = htole32((uint32_t)(val - mod)); 3387 3388 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3389 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3390 3391 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3392 } 3393 3394 static void 3395 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3396 { 3397 /* Adjust TX power if need be (delta >= 3 degC). */ 3398 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3399 if (abs(temp - sc->temp) >= 3) { 3400 /* Record temperature of last calibration. */ 3401 sc->temp = temp; 3402 (void)iwn4965_set_txpower(sc, 1); 3403 } 3404 } 3405 3406 /* 3407 * Set TX power for current channel (each rate has its own power settings). 3408 * This function takes into account the regulatory information from EEPROM, 3409 * the current temperature and the current voltage. 3410 */ 3411 static int 3412 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3413 { 3414 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3415 #define fdivround(a, b, n) \ 3416 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3417 /* Linear interpolation. */ 3418 #define interpolate(x, x1, y1, x2, y2, n) \ 3419 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3420 3421 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3422 struct ieee80211com *ic = &sc->sc_ic; 3423 struct iwn_ucode_info *uc = &sc->ucode_info; 3424 struct ieee80211_channel *ch; 3425 struct iwn4965_cmd_txpower cmd; 3426 struct iwn4965_eeprom_chan_samples *chans; 3427 const uint8_t *rf_gain, *dsp_gain; 3428 int32_t vdiff, tdiff; 3429 int i, c, grp, maxpwr; 3430 uint8_t chan; 3431 3432 /* Retrieve current channel from last RXON. */ 3433 chan = sc->rxon.chan; 3434 DPRINTF(("setting TX power for channel %d\n", chan)); 3435 ch = &ic->ic_channels[chan]; 3436 3437 memset(&cmd, 0, sizeof cmd); 3438 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3439 cmd.chan = chan; 3440 3441 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3442 maxpwr = sc->maxpwr5GHz; 3443 rf_gain = iwn4965_rf_gain_5ghz; 3444 dsp_gain = iwn4965_dsp_gain_5ghz; 3445 } else { 3446 maxpwr = sc->maxpwr2GHz; 3447 rf_gain = iwn4965_rf_gain_2ghz; 3448 dsp_gain = iwn4965_dsp_gain_2ghz; 3449 } 3450 3451 /* Compute voltage compensation. */ 3452 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3453 if (vdiff > 0) 3454 vdiff *= 2; 3455 if (abs(vdiff) > 2) 3456 vdiff = 0; 3457 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3458 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3459 3460 /* Get channel attenuation group. */ 3461 if (chan <= 20) /* 1-20 */ 3462 grp = 4; 3463 else if (chan <= 43) /* 34-43 */ 3464 grp = 0; 3465 else if (chan <= 70) /* 44-70 */ 3466 grp = 1; 3467 else if (chan <= 124) /* 71-124 */ 3468 grp = 2; 3469 else /* 125-200 */ 3470 grp = 3; 3471 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3472 3473 /* Get channel sub-band. */ 3474 for (i = 0; i < IWN_NBANDS; i++) 3475 if (sc->bands[i].lo != 0 && 3476 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3477 break; 3478 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3479 return EINVAL; 3480 chans = sc->bands[i].chans; 3481 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3482 3483 for (c = 0; c < 2; c++) { 3484 uint8_t power, gain, temp; 3485 int maxchpwr, pwr, ridx, idx; 3486 3487 power = interpolate(chan, 3488 chans[0].num, chans[0].samples[c][1].power, 3489 chans[1].num, chans[1].samples[c][1].power, 1); 3490 gain = interpolate(chan, 3491 chans[0].num, chans[0].samples[c][1].gain, 3492 chans[1].num, chans[1].samples[c][1].gain, 1); 3493 temp = interpolate(chan, 3494 chans[0].num, chans[0].samples[c][1].temp, 3495 chans[1].num, chans[1].samples[c][1].temp, 1); 3496 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3497 c, power, gain, temp)); 3498 3499 /* Compute temperature compensation. */ 3500 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3501 DPRINTF(("temperature compensation=%d (current=%d, " 3502 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3503 3504 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3505 /* Convert dBm to half-dBm. */ 3506 maxchpwr = sc->maxpwr[chan] * 2; 3507 if ((ridx / 8) & 1) 3508 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3509 3510 pwr = maxpwr; 3511 3512 /* Adjust TX power based on rate. */ 3513 if ((ridx % 8) == 5) 3514 pwr -= 15; /* OFDM48: -7.5dB */ 3515 else if ((ridx % 8) == 6) 3516 pwr -= 17; /* OFDM54: -8.5dB */ 3517 else if ((ridx % 8) == 7) 3518 pwr -= 20; /* OFDM60: -10dB */ 3519 else 3520 pwr -= 10; /* Others: -5dB */ 3521 3522 /* Do not exceed channel max TX power. */ 3523 if (pwr > maxchpwr) 3524 pwr = maxchpwr; 3525 3526 idx = gain - (pwr - power) - tdiff - vdiff; 3527 if ((ridx / 8) & 1) /* MIMO */ 3528 idx += (int32_t)le32toh(uc->atten[grp][c]); 3529 3530 if (cmd.band == 0) 3531 idx += 9; /* 5GHz */ 3532 if (ridx == IWN_RIDX_MAX) 3533 idx += 5; /* CCK */ 3534 3535 /* Make sure idx stays in a valid range. */ 3536 if (idx < 0) 3537 idx = 0; 3538 else if (idx > IWN4965_MAX_PWR_INDEX) 3539 idx = IWN4965_MAX_PWR_INDEX; 3540 3541 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3542 c, ridx, idx)); 3543 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3544 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3545 } 3546 } 3547 3548 DPRINTF(("setting TX power for chan %d\n", chan)); 3549 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3550 3551 #undef interpolate 3552 #undef fdivround 3553 } 3554 3555 static int 3556 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3557 { 3558 struct iwn5000_cmd_txpower cmd; 3559 3560 /* 3561 * TX power calibration is handled automatically by the firmware 3562 * for 5000 Series. 3563 */ 3564 memset(&cmd, 0, sizeof cmd); 3565 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3566 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3567 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3568 DPRINTF(("setting TX power\n")); 3569 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3570 } 3571 3572 /* 3573 * Retrieve the maximum RSSI (in dBm) among receivers. 3574 */ 3575 static int 3576 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3577 { 3578 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3579 uint8_t mask, agc; 3580 int rssi; 3581 3582 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3583 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3584 3585 rssi = 0; 3586 if (mask & IWN_ANT_A) 3587 rssi = MAX(rssi, phy->rssi[0]); 3588 if (mask & IWN_ANT_B) 3589 rssi = MAX(rssi, phy->rssi[2]); 3590 if (mask & IWN_ANT_C) 3591 rssi = MAX(rssi, phy->rssi[4]); 3592 3593 return rssi - agc - IWN_RSSI_TO_DBM; 3594 } 3595 3596 static int 3597 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3598 { 3599 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3600 uint8_t agc; 3601 int rssi; 3602 3603 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3604 3605 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3606 le16toh(phy->rssi[1]) & 0xff); 3607 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3608 3609 return rssi - agc - IWN_RSSI_TO_DBM; 3610 } 3611 3612 /* 3613 * Retrieve the average noise (in dBm) among receivers. 3614 */ 3615 static int 3616 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3617 { 3618 int i, total, nbant, noise; 3619 3620 total = nbant = 0; 3621 for (i = 0; i < 3; i++) { 3622 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3623 continue; 3624 total += noise; 3625 nbant++; 3626 } 3627 /* There should be at least one antenna but check anyway. */ 3628 return (nbant == 0) ? -127 : (total / nbant) - 107; 3629 } 3630 3631 /* 3632 * Compute temperature (in degC) from last received statistics. 3633 */ 3634 static int 3635 iwn4965_get_temperature(struct iwn_softc *sc) 3636 { 3637 struct iwn_ucode_info *uc = &sc->ucode_info; 3638 int32_t r1, r2, r3, r4, temp; 3639 3640 r1 = le32toh(uc->temp[0].chan20MHz); 3641 r2 = le32toh(uc->temp[1].chan20MHz); 3642 r3 = le32toh(uc->temp[2].chan20MHz); 3643 r4 = le32toh(sc->rawtemp); 3644 3645 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3646 return 0; 3647 3648 /* Sign-extend 23-bit R4 value to 32-bit. */ 3649 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3650 /* Compute temperature in Kelvin. */ 3651 temp = (259 * (r4 - r2)) / (r3 - r1); 3652 temp = (temp * 97) / 100 + 8; 3653 3654 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3655 return IWN_KTOC(temp); 3656 } 3657 3658 static int 3659 iwn5000_get_temperature(struct iwn_softc *sc) 3660 { 3661 int32_t temp; 3662 3663 /* 3664 * Temperature is not used by the driver for 5000 Series because 3665 * TX power calibration is handled by firmware. We export it to 3666 * users through the sensor framework though. 3667 */ 3668 temp = le32toh(sc->rawtemp); 3669 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3670 temp = (temp / -5) + sc->temp_off; 3671 temp = IWN_KTOC(temp); 3672 } 3673 return temp; 3674 } 3675 3676 /* 3677 * Initialize sensitivity calibration state machine. 3678 */ 3679 static int 3680 iwn_init_sensitivity(struct iwn_softc *sc) 3681 { 3682 struct iwn_ops *ops = &sc->ops; 3683 struct iwn_calib_state *calib = &sc->calib; 3684 uint32_t flags; 3685 int error; 3686 3687 /* Reset calibration state machine. */ 3688 memset(calib, 0, sizeof (*calib)); 3689 calib->state = IWN_CALIB_STATE_INIT; 3690 calib->cck_state = IWN_CCK_STATE_HIFA; 3691 /* Set initial correlation values. */ 3692 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3693 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3694 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3695 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3696 calib->cck_x4 = 125; 3697 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3698 calib->energy_cck = sc->limits->energy_cck; 3699 3700 /* Write initial sensitivity. */ 3701 if ((error = iwn_send_sensitivity(sc)) != 0) 3702 return error; 3703 3704 /* Write initial gains. */ 3705 if ((error = ops->init_gains(sc)) != 0) 3706 return error; 3707 3708 /* Request statistics at each beacon interval. */ 3709 flags = 0; 3710 DPRINTF(("sending request for statistics\n")); 3711 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3712 } 3713 3714 /* 3715 * Collect noise and RSSI statistics for the first 20 beacons received 3716 * after association and use them to determine connected antennas and 3717 * to set differential gains. 3718 */ 3719 static void 3720 iwn_collect_noise(struct iwn_softc *sc, 3721 const struct iwn_rx_general_stats *stats) 3722 { 3723 struct iwn_ops *ops = &sc->ops; 3724 struct iwn_calib_state *calib = &sc->calib; 3725 uint32_t val; 3726 int i; 3727 3728 /* Accumulate RSSI and noise for all 3 antennas. */ 3729 for (i = 0; i < 3; i++) { 3730 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3731 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3732 } 3733 /* NB: We update differential gains only once after 20 beacons. */ 3734 if (++calib->nbeacons < 20) 3735 return; 3736 3737 /* Determine highest average RSSI. */ 3738 val = MAX(calib->rssi[0], calib->rssi[1]); 3739 val = MAX(calib->rssi[2], val); 3740 3741 /* Determine which antennas are connected. */ 3742 sc->chainmask = sc->rxchainmask; 3743 for (i = 0; i < 3; i++) 3744 if (val - calib->rssi[i] > 15 * 20) 3745 sc->chainmask &= ~(1 << i); 3746 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3747 sc->rxchainmask, sc->chainmask)); 3748 3749 /* If none of the TX antennas are connected, keep at least one. */ 3750 if ((sc->chainmask & sc->txchainmask) == 0) 3751 sc->chainmask |= IWN_LSB(sc->txchainmask); 3752 3753 (void)ops->set_gains(sc); 3754 calib->state = IWN_CALIB_STATE_RUN; 3755 3756 #ifdef notyet 3757 /* XXX Disable RX chains with no antennas connected. */ 3758 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3759 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3760 #endif 3761 3762 /* Enable power-saving mode if requested by user. */ 3763 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3764 (void)iwn_set_pslevel(sc, 0, 3, 1); 3765 } 3766 3767 static int 3768 iwn4965_init_gains(struct iwn_softc *sc) 3769 { 3770 struct iwn_phy_calib_gain cmd; 3771 3772 memset(&cmd, 0, sizeof cmd); 3773 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3774 /* Differential gains initially set to 0 for all 3 antennas. */ 3775 DPRINTF(("setting initial differential gains\n")); 3776 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3777 } 3778 3779 static int 3780 iwn5000_init_gains(struct iwn_softc *sc) 3781 { 3782 struct iwn_phy_calib cmd; 3783 3784 memset(&cmd, 0, sizeof cmd); 3785 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3786 cmd.ngroups = 1; 3787 cmd.isvalid = 1; 3788 DPRINTF(("setting initial differential gains\n")); 3789 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3790 } 3791 3792 static int 3793 iwn4965_set_gains(struct iwn_softc *sc) 3794 { 3795 struct iwn_calib_state *calib = &sc->calib; 3796 struct iwn_phy_calib_gain cmd; 3797 int i, delta, noise; 3798 3799 /* Get minimal noise among connected antennas. */ 3800 noise = INT_MAX; /* NB: There's at least one antenna. */ 3801 for (i = 0; i < 3; i++) 3802 if (sc->chainmask & (1 << i)) 3803 noise = MIN(calib->noise[i], noise); 3804 3805 memset(&cmd, 0, sizeof cmd); 3806 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3807 /* Set differential gains for connected antennas. */ 3808 for (i = 0; i < 3; i++) { 3809 if (sc->chainmask & (1 << i)) { 3810 /* Compute attenuation (in unit of 1.5dB). */ 3811 delta = (noise - (int32_t)calib->noise[i]) / 30; 3812 /* NB: delta <= 0 */ 3813 /* Limit to [-4.5dB,0]. */ 3814 cmd.gain[i] = MIN(abs(delta), 3); 3815 if (delta < 0) 3816 cmd.gain[i] |= 1 << 2; /* sign bit */ 3817 } 3818 } 3819 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3820 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3821 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3822 } 3823 3824 static int 3825 iwn5000_set_gains(struct iwn_softc *sc) 3826 { 3827 struct iwn_calib_state *calib = &sc->calib; 3828 struct iwn_phy_calib_gain cmd; 3829 int i, ant, div, delta; 3830 3831 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3832 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3833 3834 memset(&cmd, 0, sizeof cmd); 3835 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3836 cmd.ngroups = 1; 3837 cmd.isvalid = 1; 3838 /* Get first available RX antenna as referential. */ 3839 ant = IWN_LSB(sc->rxchainmask); 3840 /* Set differential gains for other antennas. */ 3841 for (i = ant + 1; i < 3; i++) { 3842 if (sc->chainmask & (1 << i)) { 3843 /* The delta is relative to antenna "ant". */ 3844 delta = ((int32_t)calib->noise[ant] - 3845 (int32_t)calib->noise[i]) / div; 3846 /* Limit to [-4.5dB,+4.5dB]. */ 3847 cmd.gain[i - 1] = MIN(abs(delta), 3); 3848 if (delta < 0) 3849 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3850 } 3851 } 3852 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3853 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3854 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3855 } 3856 3857 /* 3858 * Tune RF RX sensitivity based on the number of false alarms detected 3859 * during the last beacon period. 3860 */ 3861 static void 3862 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3863 { 3864 #define inc(val, inc, max) \ 3865 if ((val) < (max)) { \ 3866 if ((val) < (max) - (inc)) \ 3867 (val) += (inc); \ 3868 else \ 3869 (val) = (max); \ 3870 needs_update = 1; \ 3871 } 3872 #define dec(val, dec, min) \ 3873 if ((val) > (min)) { \ 3874 if ((val) > (min) + (dec)) \ 3875 (val) -= (dec); \ 3876 else \ 3877 (val) = (min); \ 3878 needs_update = 1; \ 3879 } 3880 3881 const struct iwn_sensitivity_limits *limits = sc->limits; 3882 struct iwn_calib_state *calib = &sc->calib; 3883 uint32_t val, rxena, fa; 3884 uint32_t energy[3], energy_min; 3885 uint8_t noise[3], noise_ref; 3886 int i, needs_update = 0; 3887 3888 /* Check that we've been enabled long enough. */ 3889 if ((rxena = le32toh(stats->general.load)) == 0) 3890 return; 3891 3892 /* Compute number of false alarms since last call for OFDM. */ 3893 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3894 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3895 fa *= 200 * 1024; /* 200TU */ 3896 3897 /* Save counters values for next call. */ 3898 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3899 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3900 3901 if (fa > 50 * rxena) { 3902 /* High false alarm count, decrease sensitivity. */ 3903 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3904 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3905 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3906 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3907 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3908 3909 } else if (fa < 5 * rxena) { 3910 /* Low false alarm count, increase sensitivity. */ 3911 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3912 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3913 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3914 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3915 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3916 } 3917 3918 /* Compute maximum noise among 3 receivers. */ 3919 for (i = 0; i < 3; i++) 3920 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 3921 val = MAX(noise[0], noise[1]); 3922 val = MAX(noise[2], val); 3923 /* Insert it into our samples table. */ 3924 calib->noise_samples[calib->cur_noise_sample] = val; 3925 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3926 3927 /* Compute maximum noise among last 20 samples. */ 3928 noise_ref = calib->noise_samples[0]; 3929 for (i = 1; i < 20; i++) 3930 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 3931 3932 /* Compute maximum energy among 3 receivers. */ 3933 for (i = 0; i < 3; i++) 3934 energy[i] = le32toh(stats->general.energy[i]); 3935 val = MIN(energy[0], energy[1]); 3936 val = MIN(energy[2], val); 3937 /* Insert it into our samples table. */ 3938 calib->energy_samples[calib->cur_energy_sample] = val; 3939 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 3940 3941 /* Compute minimum energy among last 10 samples. */ 3942 energy_min = calib->energy_samples[0]; 3943 for (i = 1; i < 10; i++) 3944 energy_min = MAX(energy_min, calib->energy_samples[i]); 3945 energy_min += 6; 3946 3947 /* Compute number of false alarms since last call for CCK. */ 3948 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 3949 fa += le32toh(stats->cck.fa) - calib->fa_cck; 3950 fa *= 200 * 1024; /* 200TU */ 3951 3952 /* Save counters values for next call. */ 3953 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 3954 calib->fa_cck = le32toh(stats->cck.fa); 3955 3956 if (fa > 50 * rxena) { 3957 /* High false alarm count, decrease sensitivity. */ 3958 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 3959 calib->cck_state = IWN_CCK_STATE_HIFA; 3960 calib->low_fa = 0; 3961 3962 if (calib->cck_x4 > 160) { 3963 calib->noise_ref = noise_ref; 3964 if (calib->energy_cck > 2) 3965 dec(calib->energy_cck, 2, energy_min); 3966 } 3967 if (calib->cck_x4 < 160) { 3968 calib->cck_x4 = 161; 3969 needs_update = 1; 3970 } else 3971 inc(calib->cck_x4, 3, limits->max_cck_x4); 3972 3973 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 3974 3975 } else if (fa < 5 * rxena) { 3976 /* Low false alarm count, increase sensitivity. */ 3977 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 3978 calib->cck_state = IWN_CCK_STATE_LOFA; 3979 calib->low_fa++; 3980 3981 if (calib->cck_state != IWN_CCK_STATE_INIT && 3982 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 3983 calib->low_fa > 100)) { 3984 inc(calib->energy_cck, 2, limits->min_energy_cck); 3985 dec(calib->cck_x4, 3, limits->min_cck_x4); 3986 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 3987 } 3988 } else { 3989 /* Not worth to increase or decrease sensitivity. */ 3990 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 3991 calib->low_fa = 0; 3992 calib->noise_ref = noise_ref; 3993 3994 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 3995 /* Previous interval had many false alarms. */ 3996 dec(calib->energy_cck, 8, energy_min); 3997 } 3998 calib->cck_state = IWN_CCK_STATE_INIT; 3999 } 4000 4001 if (needs_update) 4002 (void)iwn_send_sensitivity(sc); 4003 #undef dec 4004 #undef inc 4005 } 4006 4007 static int 4008 iwn_send_sensitivity(struct iwn_softc *sc) 4009 { 4010 struct iwn_calib_state *calib = &sc->calib; 4011 struct iwn_sensitivity_cmd cmd; 4012 4013 memset(&cmd, 0, sizeof cmd); 4014 cmd.which = IWN_SENSITIVITY_WORKTBL; 4015 /* OFDM modulation. */ 4016 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4017 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4018 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4019 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4020 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4021 cmd.energy_ofdm_th = htole16(62); 4022 /* CCK modulation. */ 4023 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4024 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4025 cmd.energy_cck = htole16(calib->energy_cck); 4026 /* Barker modulation: use default values. */ 4027 cmd.corr_barker = htole16(190); 4028 cmd.corr_barker_mrc = htole16(390); 4029 4030 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4031 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4032 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4033 calib->energy_cck)); 4034 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4035 } 4036 4037 /* 4038 * Set STA mode power saving level (between 0 and 5). 4039 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4040 */ 4041 static int 4042 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4043 { 4044 struct iwn_pmgt_cmd cmd; 4045 const struct iwn_pmgt *pmgt; 4046 uint32_t maxp, skip_dtim; 4047 pcireg_t reg; 4048 int i; 4049 4050 /* Select which PS parameters to use. */ 4051 if (dtim <= 2) 4052 pmgt = &iwn_pmgt[0][level]; 4053 else if (dtim <= 10) 4054 pmgt = &iwn_pmgt[1][level]; 4055 else 4056 pmgt = &iwn_pmgt[2][level]; 4057 4058 memset(&cmd, 0, sizeof cmd); 4059 if (level != 0) /* not CAM */ 4060 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4061 if (level == 5) 4062 cmd.flags |= htole16(IWN_PS_FAST_PD); 4063 /* Retrieve PCIe Active State Power Management (ASPM). */ 4064 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4065 sc->sc_cap_off + PCI_PCIE_LCSR); 4066 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4067 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4068 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4069 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4070 4071 if (dtim == 0) { 4072 dtim = 1; 4073 skip_dtim = 0; 4074 } else 4075 skip_dtim = pmgt->skip_dtim; 4076 if (skip_dtim != 0) { 4077 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4078 maxp = pmgt->intval[4]; 4079 if (maxp == (uint32_t)-1) 4080 maxp = dtim * (skip_dtim + 1); 4081 else if (maxp > dtim) 4082 maxp = (maxp / dtim) * dtim; 4083 } else 4084 maxp = dtim; 4085 for (i = 0; i < 5; i++) 4086 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4087 4088 DPRINTF(("setting power saving level to %d\n", level)); 4089 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4090 } 4091 4092 static int 4093 iwn_config(struct iwn_softc *sc) 4094 { 4095 struct iwn_ops *ops = &sc->ops; 4096 struct ieee80211com *ic = &sc->sc_ic; 4097 struct ifnet *ifp = ic->ic_ifp; 4098 struct iwn_bluetooth bluetooth; 4099 uint32_t txmask; 4100 uint16_t rxchain; 4101 int error; 4102 4103 /* Configure valid TX chains for 5000 Series. */ 4104 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4105 txmask = htole32(sc->txchainmask); 4106 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4107 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4108 sizeof txmask, 0); 4109 if (error != 0) { 4110 aprint_error_dev(sc->sc_dev, 4111 "could not configure valid TX chains\n"); 4112 return error; 4113 } 4114 } 4115 4116 /* Configure bluetooth coexistence. */ 4117 memset(&bluetooth, 0, sizeof bluetooth); 4118 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4119 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4120 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4121 DPRINTF(("configuring bluetooth coexistence\n")); 4122 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4123 if (error != 0) { 4124 aprint_error_dev(sc->sc_dev, 4125 "could not configure bluetooth coexistence\n"); 4126 return error; 4127 } 4128 4129 /* Set mode, channel, RX filter and enable RX. */ 4130 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4131 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4132 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4133 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4134 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4135 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4136 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4137 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4138 switch (ic->ic_opmode) { 4139 case IEEE80211_M_STA: 4140 sc->rxon.mode = IWN_MODE_STA; 4141 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4142 break; 4143 case IEEE80211_M_MONITOR: 4144 sc->rxon.mode = IWN_MODE_MONITOR; 4145 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4146 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4147 break; 4148 default: 4149 /* Should not get there. */ 4150 break; 4151 } 4152 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4153 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4154 sc->rxon.ht_single_mask = 0xff; 4155 sc->rxon.ht_dual_mask = 0xff; 4156 sc->rxon.ht_triple_mask = 0xff; 4157 rxchain = 4158 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4159 IWN_RXCHAIN_MIMO_COUNT(2) | 4160 IWN_RXCHAIN_IDLE_COUNT(2); 4161 sc->rxon.rxchain = htole16(rxchain); 4162 DPRINTF(("setting configuration\n")); 4163 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4164 if (error != 0) { 4165 aprint_error_dev(sc->sc_dev, 4166 "RXON command failed\n"); 4167 return error; 4168 } 4169 4170 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4171 aprint_error_dev(sc->sc_dev, 4172 "could not add broadcast node\n"); 4173 return error; 4174 } 4175 4176 /* Configuration has changed, set TX power accordingly. */ 4177 if ((error = ops->set_txpower(sc, 0)) != 0) { 4178 aprint_error_dev(sc->sc_dev, 4179 "could not set TX power\n"); 4180 return error; 4181 } 4182 4183 if ((error = iwn_set_critical_temp(sc)) != 0) { 4184 aprint_error_dev(sc->sc_dev, 4185 "could not set critical temperature\n"); 4186 return error; 4187 } 4188 4189 /* Set power saving level to CAM during initialization. */ 4190 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4191 aprint_error_dev(sc->sc_dev, 4192 "could not set power saving level\n"); 4193 return error; 4194 } 4195 return 0; 4196 } 4197 4198 static int 4199 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4200 { 4201 struct ieee80211com *ic = &sc->sc_ic; 4202 struct iwn_scan_hdr *hdr; 4203 struct iwn_cmd_data *tx; 4204 struct iwn_scan_essid *essid; 4205 struct iwn_scan_chan *chan; 4206 struct ieee80211_frame *wh; 4207 struct ieee80211_rateset *rs; 4208 struct ieee80211_channel *c; 4209 uint8_t *buf, *frm; 4210 uint16_t rxchain; 4211 uint8_t txant; 4212 int buflen, error; 4213 4214 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4215 if (buf == NULL) { 4216 aprint_error_dev(sc->sc_dev, 4217 "could not allocate buffer for scan command\n"); 4218 return ENOMEM; 4219 } 4220 hdr = (struct iwn_scan_hdr *)buf; 4221 /* 4222 * Move to the next channel if no frames are received within 10ms 4223 * after sending the probe request. 4224 */ 4225 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4226 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4227 4228 /* Select antennas for scanning. */ 4229 rxchain = 4230 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4231 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4232 IWN_RXCHAIN_DRIVER_FORCE; 4233 if ((flags & IEEE80211_CHAN_5GHZ) && 4234 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4235 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4236 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4237 } else /* Use all available RX antennas. */ 4238 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4239 hdr->rxchain = htole16(rxchain); 4240 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4241 4242 tx = (struct iwn_cmd_data *)(hdr + 1); 4243 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4244 tx->id = sc->broadcast_id; 4245 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4246 4247 if (flags & IEEE80211_CHAN_5GHZ) { 4248 hdr->crc_threshold = 0xffff; 4249 /* Send probe requests at 6Mbps. */ 4250 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4251 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4252 } else { 4253 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4254 /* Send probe requests at 1Mbps. */ 4255 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4256 tx->rflags = IWN_RFLAG_CCK; 4257 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4258 } 4259 /* Use the first valid TX antenna. */ 4260 txant = IWN_LSB(sc->txchainmask); 4261 tx->rflags |= IWN_RFLAG_ANT(txant); 4262 4263 essid = (struct iwn_scan_essid *)(tx + 1); 4264 if (ic->ic_des_esslen != 0) { 4265 essid[0].id = IEEE80211_ELEMID_SSID; 4266 essid[0].len = ic->ic_des_esslen; 4267 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4268 } 4269 /* 4270 * Build a probe request frame. Most of the following code is a 4271 * copy & paste of what is done in net80211. 4272 */ 4273 wh = (struct ieee80211_frame *)(essid + 20); 4274 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4275 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4276 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4277 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4278 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4279 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4280 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4281 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4282 4283 frm = (uint8_t *)(wh + 1); 4284 frm = ieee80211_add_ssid(frm, NULL, 0); 4285 frm = ieee80211_add_rates(frm, rs); 4286 #ifndef IEEE80211_NO_HT 4287 if (ic->ic_flags & IEEE80211_F_HTON) 4288 frm = ieee80211_add_htcaps(frm, ic); 4289 #endif 4290 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4291 frm = ieee80211_add_xrates(frm, rs); 4292 4293 /* Set length of probe request. */ 4294 tx->len = htole16(frm - (uint8_t *)wh); 4295 4296 chan = (struct iwn_scan_chan *)frm; 4297 for (c = &ic->ic_channels[1]; 4298 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4299 if ((c->ic_flags & flags) != flags) 4300 continue; 4301 4302 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4303 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4304 chan->flags = 0; 4305 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4306 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4307 if (ic->ic_des_esslen != 0) 4308 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4309 chan->dsp_gain = 0x6e; 4310 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4311 chan->rf_gain = 0x3b; 4312 chan->active = htole16(24); 4313 chan->passive = htole16(110); 4314 } else { 4315 chan->rf_gain = 0x28; 4316 chan->active = htole16(36); 4317 chan->passive = htole16(120); 4318 } 4319 hdr->nchan++; 4320 chan++; 4321 } 4322 4323 buflen = (uint8_t *)chan - buf; 4324 hdr->len = htole16(buflen); 4325 4326 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4327 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4328 free(buf, M_DEVBUF); 4329 return error; 4330 } 4331 4332 static int 4333 iwn_auth(struct iwn_softc *sc) 4334 { 4335 struct iwn_ops *ops = &sc->ops; 4336 struct ieee80211com *ic = &sc->sc_ic; 4337 struct ieee80211_node *ni = ic->ic_bss; 4338 int error; 4339 4340 /* Update adapter configuration. */ 4341 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4342 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4343 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4344 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4345 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4346 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4347 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4348 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4349 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4350 switch (ic->ic_curmode) { 4351 case IEEE80211_MODE_11A: 4352 sc->rxon.cck_mask = 0; 4353 sc->rxon.ofdm_mask = 0x15; 4354 break; 4355 case IEEE80211_MODE_11B: 4356 sc->rxon.cck_mask = 0x03; 4357 sc->rxon.ofdm_mask = 0; 4358 break; 4359 default: /* Assume 802.11b/g. */ 4360 sc->rxon.cck_mask = 0x0f; 4361 sc->rxon.ofdm_mask = 0x15; 4362 } 4363 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4364 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4365 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4366 if (error != 0) { 4367 aprint_error_dev(sc->sc_dev, 4368 "RXON command failed\n"); 4369 return error; 4370 } 4371 4372 /* Configuration has changed, set TX power accordingly. */ 4373 if ((error = ops->set_txpower(sc, 1)) != 0) { 4374 aprint_error_dev(sc->sc_dev, 4375 "could not set TX power\n"); 4376 return error; 4377 } 4378 /* 4379 * Reconfiguring RXON clears the firmware nodes table so we must 4380 * add the broadcast node again. 4381 */ 4382 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4383 aprint_error_dev(sc->sc_dev, 4384 "could not add broadcast node\n"); 4385 return error; 4386 } 4387 return 0; 4388 } 4389 4390 static int 4391 iwn_run(struct iwn_softc *sc) 4392 { 4393 struct iwn_ops *ops = &sc->ops; 4394 struct ieee80211com *ic = &sc->sc_ic; 4395 struct ieee80211_node *ni = ic->ic_bss; 4396 struct iwn_node_info node; 4397 int error; 4398 4399 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4400 /* Link LED blinks while monitoring. */ 4401 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4402 return 0; 4403 } 4404 if ((error = iwn_set_timing(sc, ni)) != 0) { 4405 aprint_error_dev(sc->sc_dev, 4406 "could not set timing\n"); 4407 return error; 4408 } 4409 4410 /* Update adapter configuration. */ 4411 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4412 /* Short preamble and slot time are negotiated when associating. */ 4413 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4414 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4415 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4416 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4417 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4418 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4419 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4420 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4421 if (error != 0) { 4422 aprint_error_dev(sc->sc_dev, 4423 "could not update configuration\n"); 4424 return error; 4425 } 4426 4427 /* Configuration has changed, set TX power accordingly. */ 4428 if ((error = ops->set_txpower(sc, 1)) != 0) { 4429 aprint_error_dev(sc->sc_dev, 4430 "could not set TX power\n"); 4431 return error; 4432 } 4433 4434 /* Fake a join to initialize the TX rate. */ 4435 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4436 iwn_newassoc(ni, 1); 4437 4438 /* Add BSS node. */ 4439 memset(&node, 0, sizeof node); 4440 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4441 node.id = IWN_ID_BSS; 4442 #ifdef notyet 4443 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4444 IWN_AMDPU_DENSITY(5)); /* 2us */ 4445 #endif 4446 DPRINTF(("adding BSS node\n")); 4447 error = ops->add_node(sc, &node, 1); 4448 if (error != 0) { 4449 aprint_error_dev(sc->sc_dev, 4450 "could not add BSS node\n"); 4451 return error; 4452 } 4453 DPRINTF(("setting link quality for node %d\n", node.id)); 4454 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4455 aprint_error_dev(sc->sc_dev, 4456 "could not setup link quality for node %d\n", node.id); 4457 return error; 4458 } 4459 4460 if ((error = iwn_init_sensitivity(sc)) != 0) { 4461 aprint_error_dev(sc->sc_dev, 4462 "could not set sensitivity\n"); 4463 return error; 4464 } 4465 /* Start periodic calibration timer. */ 4466 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4467 sc->calib_cnt = 0; 4468 callout_schedule(&sc->calib_to, hz/2); 4469 4470 /* Link LED always on while associated. */ 4471 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4472 return 0; 4473 } 4474 4475 #ifdef IWN_HWCRYPTO 4476 /* 4477 * We support CCMP hardware encryption/decryption of unicast frames only. 4478 * HW support for TKIP really sucks. We should let TKIP die anyway. 4479 */ 4480 static int 4481 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4482 struct ieee80211_key *k) 4483 { 4484 struct iwn_softc *sc = ic->ic_softc; 4485 struct iwn_ops *ops = &sc->ops; 4486 struct iwn_node *wn = (void *)ni; 4487 struct iwn_node_info node; 4488 uint16_t kflags; 4489 4490 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4491 k->k_cipher != IEEE80211_CIPHER_CCMP) 4492 return ieee80211_set_key(ic, ni, k); 4493 4494 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4495 if (k->k_flags & IEEE80211_KEY_GROUP) 4496 kflags |= IWN_KFLAG_GROUP; 4497 4498 memset(&node, 0, sizeof node); 4499 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4500 sc->broadcast_id : wn->id; 4501 node.control = IWN_NODE_UPDATE; 4502 node.flags = IWN_FLAG_SET_KEY; 4503 node.kflags = htole16(kflags); 4504 node.kid = k->k_id; 4505 memcpy(node.key, k->k_key, k->k_len); 4506 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4507 return ops->add_node(sc, &node, 1); 4508 } 4509 4510 static void 4511 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4512 struct ieee80211_key *k) 4513 { 4514 struct iwn_softc *sc = ic->ic_softc; 4515 struct iwn_ops *ops = &sc->ops; 4516 struct iwn_node *wn = (void *)ni; 4517 struct iwn_node_info node; 4518 4519 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4520 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4521 /* See comment about other ciphers above. */ 4522 ieee80211_delete_key(ic, ni, k); 4523 return; 4524 } 4525 if (ic->ic_state != IEEE80211_S_RUN) 4526 return; /* Nothing to do. */ 4527 memset(&node, 0, sizeof node); 4528 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4529 sc->broadcast_id : wn->id; 4530 node.control = IWN_NODE_UPDATE; 4531 node.flags = IWN_FLAG_SET_KEY; 4532 node.kflags = htole16(IWN_KFLAG_INVALID); 4533 node.kid = 0xff; 4534 DPRINTF(("delete keys for node %d\n", node.id)); 4535 (void)ops->add_node(sc, &node, 1); 4536 } 4537 #endif 4538 4539 /* XXX Added for NetBSD (copied from rev 1.39). */ 4540 4541 static int 4542 iwn_wme_update(struct ieee80211com *ic) 4543 { 4544 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4545 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4546 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4547 const struct wmeParams *wmep; 4548 struct iwn_edca_params cmd; 4549 int ac; 4550 4551 /* don't override default WME values if WME is not actually enabled */ 4552 if (!(ic->ic_flags & IEEE80211_F_WME)) 4553 return 0; 4554 cmd.flags = 0; 4555 for (ac = 0; ac < WME_NUM_AC; ac++) { 4556 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4557 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4558 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4559 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4560 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4561 4562 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4563 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4564 cmd.ac[ac].cwmin, 4565 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4566 } 4567 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4568 #undef IWN_USEC 4569 #undef IWN_EXP2 4570 } 4571 4572 #ifndef IEEE80211_NO_HT 4573 /* 4574 * This function is called by upper layer when an ADDBA request is received 4575 * from another STA and before the ADDBA response is sent. 4576 */ 4577 static int 4578 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4579 uint8_t tid) 4580 { 4581 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4582 struct iwn_softc *sc = ic->ic_softc; 4583 struct iwn_ops *ops = &sc->ops; 4584 struct iwn_node *wn = (void *)ni; 4585 struct iwn_node_info node; 4586 4587 memset(&node, 0, sizeof node); 4588 node.id = wn->id; 4589 node.control = IWN_NODE_UPDATE; 4590 node.flags = IWN_FLAG_SET_ADDBA; 4591 node.addba_tid = tid; 4592 node.addba_ssn = htole16(ba->ba_winstart); 4593 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4594 ba->ba_winstart)); 4595 return ops->add_node(sc, &node, 1); 4596 } 4597 4598 /* 4599 * This function is called by upper layer on teardown of an HT-immediate 4600 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4601 */ 4602 static void 4603 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4604 uint8_t tid) 4605 { 4606 struct iwn_softc *sc = ic->ic_softc; 4607 struct iwn_ops *ops = &sc->ops; 4608 struct iwn_node *wn = (void *)ni; 4609 struct iwn_node_info node; 4610 4611 memset(&node, 0, sizeof node); 4612 node.id = wn->id; 4613 node.control = IWN_NODE_UPDATE; 4614 node.flags = IWN_FLAG_SET_DELBA; 4615 node.delba_tid = tid; 4616 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4617 (void)ops->add_node(sc, &node, 1); 4618 } 4619 4620 /* 4621 * This function is called by upper layer when an ADDBA response is received 4622 * from another STA. 4623 */ 4624 static int 4625 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4626 uint8_t tid) 4627 { 4628 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4629 struct iwn_softc *sc = ic->ic_softc; 4630 struct iwn_ops *ops = &sc->ops; 4631 struct iwn_node *wn = (void *)ni; 4632 struct iwn_node_info node; 4633 int error; 4634 4635 /* Enable TX for the specified RA/TID. */ 4636 wn->disable_tid &= ~(1 << tid); 4637 memset(&node, 0, sizeof node); 4638 node.id = wn->id; 4639 node.control = IWN_NODE_UPDATE; 4640 node.flags = IWN_FLAG_SET_DISABLE_TID; 4641 node.disable_tid = htole16(wn->disable_tid); 4642 error = ops->add_node(sc, &node, 1); 4643 if (error != 0) 4644 return error; 4645 4646 if ((error = iwn_nic_lock(sc)) != 0) 4647 return error; 4648 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4649 iwn_nic_unlock(sc); 4650 return 0; 4651 } 4652 4653 static void 4654 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4655 uint8_t tid) 4656 { 4657 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4658 struct iwn_softc *sc = ic->ic_softc; 4659 struct iwn_ops *ops = &sc->ops; 4660 4661 if (iwn_nic_lock(sc) != 0) 4662 return; 4663 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4664 iwn_nic_unlock(sc); 4665 } 4666 4667 static void 4668 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4669 uint8_t tid, uint16_t ssn) 4670 { 4671 struct iwn_node *wn = (void *)ni; 4672 int qid = 7 + tid; 4673 4674 /* Stop TX scheduler while we're changing its configuration. */ 4675 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4676 IWN4965_TXQ_STATUS_CHGACT); 4677 4678 /* Assign RA/TID translation to the queue. */ 4679 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4680 wn->id << 4 | tid); 4681 4682 /* Enable chain-building mode for the queue. */ 4683 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4684 4685 /* Set starting sequence number from the ADDBA request. */ 4686 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4687 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4688 4689 /* Set scheduler window size. */ 4690 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4691 IWN_SCHED_WINSZ); 4692 /* Set scheduler frame limit. */ 4693 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4694 IWN_SCHED_LIMIT << 16); 4695 4696 /* Enable interrupts for the queue. */ 4697 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4698 4699 /* Mark the queue as active. */ 4700 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4701 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4702 iwn_tid2fifo[tid] << 1); 4703 } 4704 4705 static void 4706 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4707 { 4708 int qid = 7 + tid; 4709 4710 /* Stop TX scheduler while we're changing its configuration. */ 4711 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4712 IWN4965_TXQ_STATUS_CHGACT); 4713 4714 /* Set starting sequence number from the ADDBA request. */ 4715 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4716 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4717 4718 /* Disable interrupts for the queue. */ 4719 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4720 4721 /* Mark the queue as inactive. */ 4722 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4723 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4724 } 4725 4726 static void 4727 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4728 uint8_t tid, uint16_t ssn) 4729 { 4730 struct iwn_node *wn = (void *)ni; 4731 int qid = 10 + tid; 4732 4733 /* Stop TX scheduler while we're changing its configuration. */ 4734 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4735 IWN5000_TXQ_STATUS_CHGACT); 4736 4737 /* Assign RA/TID translation to the queue. */ 4738 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4739 wn->id << 4 | tid); 4740 4741 /* Enable chain-building mode for the queue. */ 4742 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4743 4744 /* Enable aggregation for the queue. */ 4745 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4746 4747 /* Set starting sequence number from the ADDBA request. */ 4748 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4749 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4750 4751 /* Set scheduler window size and frame limit. */ 4752 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4753 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4754 4755 /* Enable interrupts for the queue. */ 4756 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4757 4758 /* Mark the queue as active. */ 4759 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4760 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4761 } 4762 4763 static void 4764 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4765 { 4766 int qid = 10 + tid; 4767 4768 /* Stop TX scheduler while we're changing its configuration. */ 4769 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4770 IWN5000_TXQ_STATUS_CHGACT); 4771 4772 /* Disable aggregation for the queue. */ 4773 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4774 4775 /* Set starting sequence number from the ADDBA request. */ 4776 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4777 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4778 4779 /* Disable interrupts for the queue. */ 4780 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4781 4782 /* Mark the queue as inactive. */ 4783 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4784 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4785 } 4786 #endif /* !IEEE80211_NO_HT */ 4787 4788 /* 4789 * Query calibration tables from the initialization firmware. We do this 4790 * only once at first boot. Called from a process context. 4791 */ 4792 static int 4793 iwn5000_query_calibration(struct iwn_softc *sc) 4794 { 4795 struct iwn5000_calib_config cmd; 4796 int error; 4797 4798 memset(&cmd, 0, sizeof cmd); 4799 cmd.ucode.once.enable = 0xffffffff; 4800 cmd.ucode.once.start = 0xffffffff; 4801 cmd.ucode.once.send = 0xffffffff; 4802 cmd.ucode.flags = 0xffffffff; 4803 DPRINTF(("sending calibration query\n")); 4804 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4805 if (error != 0) 4806 return error; 4807 4808 /* Wait at most two seconds for calibration to complete. */ 4809 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4810 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4811 return error; 4812 } 4813 4814 /* 4815 * Send calibration results to the runtime firmware. These results were 4816 * obtained on first boot from the initialization firmware. 4817 */ 4818 static int 4819 iwn5000_send_calibration(struct iwn_softc *sc) 4820 { 4821 int idx, error; 4822 4823 for (idx = 0; idx < 5; idx++) { 4824 if (sc->calibcmd[idx].buf == NULL) 4825 continue; /* No results available. */ 4826 DPRINTF(("send calibration result idx=%d len=%d\n", 4827 idx, sc->calibcmd[idx].len)); 4828 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4829 sc->calibcmd[idx].len, 0); 4830 if (error != 0) { 4831 aprint_error_dev(sc->sc_dev, 4832 "could not send calibration result\n"); 4833 return error; 4834 } 4835 } 4836 return 0; 4837 } 4838 4839 static int 4840 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4841 { 4842 struct iwn5000_wimax_coex wimax; 4843 4844 #ifdef notyet 4845 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4846 /* Enable WiMAX coexistence for combo adapters. */ 4847 wimax.flags = 4848 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4849 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4850 IWN_WIMAX_COEX_STA_TABLE_VALID | 4851 IWN_WIMAX_COEX_ENABLE; 4852 memcpy(wimax.events, iwn6050_wimax_events, 4853 sizeof iwn6050_wimax_events); 4854 } else 4855 #endif 4856 { 4857 /* Disable WiMAX coexistence. */ 4858 wimax.flags = 0; 4859 memset(wimax.events, 0, sizeof wimax.events); 4860 } 4861 DPRINTF(("Configuring WiMAX coexistence\n")); 4862 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4863 } 4864 4865 /* 4866 * This function is called after the runtime firmware notifies us of its 4867 * readiness (called in a process context). 4868 */ 4869 static int 4870 iwn4965_post_alive(struct iwn_softc *sc) 4871 { 4872 int error, qid; 4873 4874 if ((error = iwn_nic_lock(sc)) != 0) 4875 return error; 4876 4877 /* Clear TX scheduler state in SRAM. */ 4878 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4879 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4880 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 4881 4882 /* Set physical address of TX scheduler rings (1KB aligned). */ 4883 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4884 4885 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4886 4887 /* Disable chain mode for all our 16 queues. */ 4888 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4889 4890 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4891 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4892 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4893 4894 /* Set scheduler window size. */ 4895 iwn_mem_write(sc, sc->sched_base + 4896 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4897 /* Set scheduler frame limit. */ 4898 iwn_mem_write(sc, sc->sched_base + 4899 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4900 IWN_SCHED_LIMIT << 16); 4901 } 4902 4903 /* Enable interrupts for all our 16 queues. */ 4904 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4905 /* Identify TX FIFO rings (0-7). */ 4906 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4907 4908 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4909 for (qid = 0; qid < 7; qid++) { 4910 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4911 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4912 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4913 } 4914 iwn_nic_unlock(sc); 4915 return 0; 4916 } 4917 4918 /* 4919 * This function is called after the initialization or runtime firmware 4920 * notifies us of its readiness (called in a process context). 4921 */ 4922 static int 4923 iwn5000_post_alive(struct iwn_softc *sc) 4924 { 4925 int error, qid; 4926 4927 /* Switch to using ICT interrupt mode. */ 4928 iwn5000_ict_reset(sc); 4929 4930 if ((error = iwn_nic_lock(sc)) != 0) 4931 return error; 4932 4933 /* Clear TX scheduler state in SRAM. */ 4934 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4935 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 4936 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 4937 4938 /* Set physical address of TX scheduler rings (1KB aligned). */ 4939 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4940 4941 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4942 4943 /* Enable chain mode for all queues, except command queue. */ 4944 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 4945 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 4946 4947 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 4948 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 4949 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4950 4951 iwn_mem_write(sc, sc->sched_base + 4952 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 4953 /* Set scheduler window size and frame limit. */ 4954 iwn_mem_write(sc, sc->sched_base + 4955 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4956 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4957 } 4958 4959 /* Enable interrupts for all our 20 queues. */ 4960 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 4961 /* Identify TX FIFO rings (0-7). */ 4962 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 4963 4964 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4965 for (qid = 0; qid < 7; qid++) { 4966 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 4967 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4968 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 4969 } 4970 iwn_nic_unlock(sc); 4971 4972 /* Configure WiMAX coexistence for combo adapters. */ 4973 error = iwn5000_send_wimax_coex(sc); 4974 if (error != 0) { 4975 aprint_error_dev(sc->sc_dev, 4976 "could not configure WiMAX coexistence\n"); 4977 return error; 4978 } 4979 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 4980 struct iwn5000_phy_calib_crystal cmd; 4981 4982 /* Perform crystal calibration. */ 4983 memset(&cmd, 0, sizeof cmd); 4984 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 4985 cmd.ngroups = 1; 4986 cmd.isvalid = 1; 4987 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 4988 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 4989 DPRINTF(("sending crystal calibration %d, %d\n", 4990 cmd.cap_pin[0], cmd.cap_pin[1])); 4991 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 4992 if (error != 0) { 4993 aprint_error_dev(sc->sc_dev, 4994 "crystal calibration failed\n"); 4995 return error; 4996 } 4997 } 4998 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 4999 /* Query calibration from the initialization firmware. */ 5000 if ((error = iwn5000_query_calibration(sc)) != 0) { 5001 aprint_error_dev(sc->sc_dev, 5002 "could not query calibration\n"); 5003 return error; 5004 } 5005 /* 5006 * We have the calibration results now, reboot with the 5007 * runtime firmware (call ourselves recursively!) 5008 */ 5009 iwn_hw_stop(sc); 5010 error = iwn_hw_init(sc); 5011 } else { 5012 /* Send calibration results to runtime firmware. */ 5013 error = iwn5000_send_calibration(sc); 5014 } 5015 return error; 5016 } 5017 5018 /* 5019 * The firmware boot code is small and is intended to be copied directly into 5020 * the NIC internal memory (no DMA transfer). 5021 */ 5022 static int 5023 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5024 { 5025 int error, ntries; 5026 5027 size /= sizeof (uint32_t); 5028 5029 if ((error = iwn_nic_lock(sc)) != 0) 5030 return error; 5031 5032 /* Copy microcode image into NIC memory. */ 5033 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5034 (const uint32_t *)ucode, size); 5035 5036 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5037 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5038 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5039 5040 /* Start boot load now. */ 5041 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5042 5043 /* Wait for transfer to complete. */ 5044 for (ntries = 0; ntries < 1000; ntries++) { 5045 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5046 IWN_BSM_WR_CTRL_START)) 5047 break; 5048 DELAY(10); 5049 } 5050 if (ntries == 1000) { 5051 aprint_error_dev(sc->sc_dev, 5052 "could not load boot firmware\n"); 5053 iwn_nic_unlock(sc); 5054 return ETIMEDOUT; 5055 } 5056 5057 /* Enable boot after power up. */ 5058 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5059 5060 iwn_nic_unlock(sc); 5061 return 0; 5062 } 5063 5064 static int 5065 iwn4965_load_firmware(struct iwn_softc *sc) 5066 { 5067 struct iwn_fw_info *fw = &sc->fw; 5068 struct iwn_dma_info *dma = &sc->fw_dma; 5069 int error; 5070 5071 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5072 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5073 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5074 BUS_DMASYNC_PREWRITE); 5075 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5076 fw->init.text, fw->init.textsz); 5077 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5078 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5079 5080 /* Tell adapter where to find initialization sections. */ 5081 if ((error = iwn_nic_lock(sc)) != 0) 5082 return error; 5083 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5084 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5085 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5086 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5087 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5088 iwn_nic_unlock(sc); 5089 5090 /* Load firmware boot code. */ 5091 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5092 if (error != 0) { 5093 aprint_error_dev(sc->sc_dev, 5094 "could not load boot firmware\n"); 5095 return error; 5096 } 5097 /* Now press "execute". */ 5098 IWN_WRITE(sc, IWN_RESET, 0); 5099 5100 /* Wait at most one second for first alive notification. */ 5101 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5102 aprint_error_dev(sc->sc_dev, 5103 "timeout waiting for adapter to initialize\n"); 5104 return error; 5105 } 5106 5107 /* Retrieve current temperature for initial TX power calibration. */ 5108 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5109 sc->temp = iwn4965_get_temperature(sc); 5110 5111 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5112 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5113 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5114 BUS_DMASYNC_PREWRITE); 5115 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5116 fw->main.text, fw->main.textsz); 5117 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5118 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5119 5120 /* Tell adapter where to find runtime sections. */ 5121 if ((error = iwn_nic_lock(sc)) != 0) 5122 return error; 5123 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5124 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5125 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5126 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5127 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5128 IWN_FW_UPDATED | fw->main.textsz); 5129 iwn_nic_unlock(sc); 5130 5131 return 0; 5132 } 5133 5134 static int 5135 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5136 const uint8_t *section, int size) 5137 { 5138 struct iwn_dma_info *dma = &sc->fw_dma; 5139 int error; 5140 5141 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5142 memcpy(dma->vaddr, section, size); 5143 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5144 5145 if ((error = iwn_nic_lock(sc)) != 0) 5146 return error; 5147 5148 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5149 IWN_FH_TX_CONFIG_DMA_PAUSE); 5150 5151 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5152 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5153 IWN_LOADDR(dma->paddr)); 5154 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5155 IWN_HIADDR(dma->paddr) << 28 | size); 5156 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5157 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5158 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5159 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5160 5161 /* Kick Flow Handler to start DMA transfer. */ 5162 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5163 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5164 5165 iwn_nic_unlock(sc); 5166 5167 /* Wait at most five seconds for FH DMA transfer to complete. */ 5168 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5169 } 5170 5171 static int 5172 iwn5000_load_firmware(struct iwn_softc *sc) 5173 { 5174 struct iwn_fw_part *fw; 5175 int error; 5176 5177 /* Load the initialization firmware on first boot only. */ 5178 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5179 &sc->fw.main : &sc->fw.init; 5180 5181 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5182 fw->text, fw->textsz); 5183 if (error != 0) { 5184 aprint_error_dev(sc->sc_dev, 5185 "could not load firmware %s section\n", ".text"); 5186 return error; 5187 } 5188 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5189 fw->data, fw->datasz); 5190 if (error != 0) { 5191 aprint_error_dev(sc->sc_dev, 5192 "could not load firmware %s section\n", ".data"); 5193 return error; 5194 } 5195 5196 /* Now press "execute". */ 5197 IWN_WRITE(sc, IWN_RESET, 0); 5198 return 0; 5199 } 5200 5201 /* 5202 * Extract text and data sections from a legacy firmware image. 5203 */ 5204 static int 5205 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5206 { 5207 const uint32_t *ptr; 5208 size_t hdrlen = 24; 5209 uint32_t rev; 5210 5211 ptr = (const uint32_t *)fw->data; 5212 rev = le32toh(*ptr++); 5213 5214 /* Check firmware API version. */ 5215 if (IWN_FW_API(rev) <= 1) { 5216 aprint_error_dev(sc->sc_dev, 5217 "bad firmware, need API version >=2\n"); 5218 return EINVAL; 5219 } 5220 if (IWN_FW_API(rev) >= 3) { 5221 /* Skip build number (version 2 header). */ 5222 hdrlen += 4; 5223 ptr++; 5224 } 5225 if (fw->size < hdrlen) { 5226 aprint_error_dev(sc->sc_dev, 5227 "firmware too short: %zd bytes\n", fw->size); 5228 return EINVAL; 5229 } 5230 fw->main.textsz = le32toh(*ptr++); 5231 fw->main.datasz = le32toh(*ptr++); 5232 fw->init.textsz = le32toh(*ptr++); 5233 fw->init.datasz = le32toh(*ptr++); 5234 fw->boot.textsz = le32toh(*ptr++); 5235 5236 /* Check that all firmware sections fit. */ 5237 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5238 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5239 aprint_error_dev(sc->sc_dev, 5240 "firmware too short: %zd bytes\n", fw->size); 5241 return EINVAL; 5242 } 5243 5244 /* Get pointers to firmware sections. */ 5245 fw->main.text = (const uint8_t *)ptr; 5246 fw->main.data = fw->main.text + fw->main.textsz; 5247 fw->init.text = fw->main.data + fw->main.datasz; 5248 fw->init.data = fw->init.text + fw->init.textsz; 5249 fw->boot.text = fw->init.data + fw->init.datasz; 5250 return 0; 5251 } 5252 5253 /* 5254 * Extract text and data sections from a TLV firmware image. 5255 */ 5256 static int 5257 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5258 uint16_t alt) 5259 { 5260 const struct iwn_fw_tlv_hdr *hdr; 5261 const struct iwn_fw_tlv *tlv; 5262 const uint8_t *ptr, *end; 5263 uint64_t altmask; 5264 uint32_t len; 5265 5266 if (fw->size < sizeof (*hdr)) { 5267 aprint_error_dev(sc->sc_dev, 5268 "firmware too short: %zd bytes\n", fw->size); 5269 return EINVAL; 5270 } 5271 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5272 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5273 aprint_error_dev(sc->sc_dev, 5274 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5275 return EINVAL; 5276 } 5277 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5278 le32toh(hdr->build))); 5279 5280 /* 5281 * Select the closest supported alternative that is less than 5282 * or equal to the specified one. 5283 */ 5284 altmask = le64toh(hdr->altmask); 5285 while (alt > 0 && !(altmask & (1ULL << alt))) 5286 alt--; /* Downgrade. */ 5287 DPRINTF(("using alternative %d\n", alt)); 5288 5289 ptr = (const uint8_t *)(hdr + 1); 5290 end = (const uint8_t *)(fw->data + fw->size); 5291 5292 /* Parse type-length-value fields. */ 5293 while (ptr + sizeof (*tlv) <= end) { 5294 tlv = (const struct iwn_fw_tlv *)ptr; 5295 len = le32toh(tlv->len); 5296 5297 ptr += sizeof (*tlv); 5298 if (ptr + len > end) { 5299 aprint_error_dev(sc->sc_dev, 5300 "firmware too short: %zd bytes\n", fw->size); 5301 return EINVAL; 5302 } 5303 /* Skip other alternatives. */ 5304 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5305 goto next; 5306 5307 switch (le16toh(tlv->type)) { 5308 case IWN_FW_TLV_MAIN_TEXT: 5309 fw->main.text = ptr; 5310 fw->main.textsz = len; 5311 break; 5312 case IWN_FW_TLV_MAIN_DATA: 5313 fw->main.data = ptr; 5314 fw->main.datasz = len; 5315 break; 5316 case IWN_FW_TLV_INIT_TEXT: 5317 fw->init.text = ptr; 5318 fw->init.textsz = len; 5319 break; 5320 case IWN_FW_TLV_INIT_DATA: 5321 fw->init.data = ptr; 5322 fw->init.datasz = len; 5323 break; 5324 case IWN_FW_TLV_BOOT_TEXT: 5325 fw->boot.text = ptr; 5326 fw->boot.textsz = len; 5327 break; 5328 default: 5329 DPRINTF(("TLV type %d not handled\n", 5330 le16toh(tlv->type))); 5331 break; 5332 } 5333 next: /* TLV fields are 32-bit aligned. */ 5334 ptr += (len + 3) & ~3; 5335 } 5336 return 0; 5337 } 5338 5339 static int 5340 iwn_read_firmware(struct iwn_softc *sc) 5341 { 5342 struct iwn_fw_info *fw = &sc->fw; 5343 firmware_handle_t fwh; 5344 int error; 5345 5346 /* Initialize for error returns */ 5347 fw->data = NULL; 5348 fw->size = 0; 5349 5350 /* Open firmware image. */ 5351 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5352 aprint_error_dev(sc->sc_dev, 5353 "could not get firmware handle %s\n", sc->fwname); 5354 return error; 5355 } 5356 fw->size = firmware_get_size(fwh); 5357 if (fw->size < sizeof (uint32_t)) { 5358 aprint_error_dev(sc->sc_dev, 5359 "firmware too short: %zd bytes\n", fw->size); 5360 firmware_close(fwh); 5361 return EINVAL; 5362 } 5363 5364 /* Read the firmware. */ 5365 fw->data = firmware_malloc(fw->size); 5366 if (fw->data == NULL) { 5367 aprint_error_dev(sc->sc_dev, 5368 "not enough memory to stock firmware %s\n", sc->fwname); 5369 firmware_close(fwh); 5370 return ENOMEM; 5371 } 5372 error = firmware_read(fwh, 0, fw->data, fw->size); 5373 firmware_close(fwh); 5374 if (error != 0) { 5375 aprint_error_dev(sc->sc_dev, 5376 "could not read firmware %s\n", sc->fwname); 5377 goto out; 5378 } 5379 5380 /* Retrieve text and data sections. */ 5381 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5382 error = iwn_read_firmware_leg(sc, fw); 5383 else 5384 error = iwn_read_firmware_tlv(sc, fw, 1); 5385 if (error != 0) { 5386 aprint_error_dev(sc->sc_dev, 5387 "could not read firmware sections\n"); 5388 goto out; 5389 } 5390 5391 /* Make sure text and data sections fit in hardware memory. */ 5392 if (fw->main.textsz > sc->fw_text_maxsz || 5393 fw->main.datasz > sc->fw_data_maxsz || 5394 fw->init.textsz > sc->fw_text_maxsz || 5395 fw->init.datasz > sc->fw_data_maxsz || 5396 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5397 (fw->boot.textsz & 3) != 0) { 5398 aprint_error_dev(sc->sc_dev, 5399 "firmware sections too large\n"); 5400 goto out; 5401 } 5402 5403 /* We can proceed with loading the firmware. */ 5404 return 0; 5405 out: 5406 firmware_free(fw->data, fw->size); 5407 fw->data = NULL; 5408 fw->size = 0; 5409 return error ? error : EINVAL; 5410 } 5411 5412 static int 5413 iwn_clock_wait(struct iwn_softc *sc) 5414 { 5415 int ntries; 5416 5417 /* Set "initialization complete" bit. */ 5418 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5419 5420 /* Wait for clock stabilization. */ 5421 for (ntries = 0; ntries < 2500; ntries++) { 5422 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5423 return 0; 5424 DELAY(10); 5425 } 5426 aprint_error_dev(sc->sc_dev, 5427 "timeout waiting for clock stabilization\n"); 5428 return ETIMEDOUT; 5429 } 5430 5431 static int 5432 iwn_apm_init(struct iwn_softc *sc) 5433 { 5434 pcireg_t reg; 5435 int error; 5436 5437 /* Disable L0s exit timer (NMI bug workaround). */ 5438 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5439 /* Don't wait for ICH L0s (ICH bug workaround). */ 5440 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5441 5442 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5443 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5444 5445 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5446 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5447 5448 /* Retrieve PCIe Active State Power Management (ASPM). */ 5449 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5450 sc->sc_cap_off + PCI_PCIE_LCSR); 5451 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5452 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5453 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5454 else 5455 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5456 5457 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5458 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5459 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5460 5461 /* Wait for clock stabilization before accessing prph. */ 5462 if ((error = iwn_clock_wait(sc)) != 0) 5463 return error; 5464 5465 if ((error = iwn_nic_lock(sc)) != 0) 5466 return error; 5467 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5468 /* Enable DMA and BSM (Bootstrap State Machine). */ 5469 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5470 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5471 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5472 } else { 5473 /* Enable DMA. */ 5474 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5475 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5476 } 5477 DELAY(20); 5478 /* Disable L1-Active. */ 5479 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5480 iwn_nic_unlock(sc); 5481 5482 return 0; 5483 } 5484 5485 static void 5486 iwn_apm_stop_master(struct iwn_softc *sc) 5487 { 5488 int ntries; 5489 5490 /* Stop busmaster DMA activity. */ 5491 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5492 for (ntries = 0; ntries < 100; ntries++) { 5493 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5494 return; 5495 DELAY(10); 5496 } 5497 aprint_error_dev(sc->sc_dev, 5498 "timeout waiting for master\n"); 5499 } 5500 5501 static void 5502 iwn_apm_stop(struct iwn_softc *sc) 5503 { 5504 iwn_apm_stop_master(sc); 5505 5506 /* Reset the entire device. */ 5507 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5508 DELAY(10); 5509 /* Clear "initialization complete" bit. */ 5510 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5511 } 5512 5513 static int 5514 iwn4965_nic_config(struct iwn_softc *sc) 5515 { 5516 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5517 /* 5518 * I don't believe this to be correct but this is what the 5519 * vendor driver is doing. Probably the bits should not be 5520 * shifted in IWN_RFCFG_*. 5521 */ 5522 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5523 IWN_RFCFG_TYPE(sc->rfcfg) | 5524 IWN_RFCFG_STEP(sc->rfcfg) | 5525 IWN_RFCFG_DASH(sc->rfcfg)); 5526 } 5527 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5528 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5529 return 0; 5530 } 5531 5532 static int 5533 iwn5000_nic_config(struct iwn_softc *sc) 5534 { 5535 uint32_t tmp; 5536 int error; 5537 5538 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5539 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5540 IWN_RFCFG_TYPE(sc->rfcfg) | 5541 IWN_RFCFG_STEP(sc->rfcfg) | 5542 IWN_RFCFG_DASH(sc->rfcfg)); 5543 } 5544 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5545 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5546 5547 if ((error = iwn_nic_lock(sc)) != 0) 5548 return error; 5549 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5550 5551 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5552 /* 5553 * Select first Switching Voltage Regulator (1.32V) to 5554 * solve a stability issue related to noisy DC2DC line 5555 * in the silicon of 1000 Series. 5556 */ 5557 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5558 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5559 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5560 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5561 } 5562 iwn_nic_unlock(sc); 5563 5564 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5565 /* Use internal power amplifier only. */ 5566 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5567 } 5568 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 5569 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 5570 /* Indicate that ROM calibration version is >=6. */ 5571 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5572 } 5573 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 5574 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 5575 return 0; 5576 } 5577 5578 /* 5579 * Take NIC ownership over Intel Active Management Technology (AMT). 5580 */ 5581 static int 5582 iwn_hw_prepare(struct iwn_softc *sc) 5583 { 5584 int ntries; 5585 5586 /* Check if hardware is ready. */ 5587 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5588 for (ntries = 0; ntries < 5; ntries++) { 5589 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5590 IWN_HW_IF_CONFIG_NIC_READY) 5591 return 0; 5592 DELAY(10); 5593 } 5594 5595 /* Hardware not ready, force into ready state. */ 5596 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5597 for (ntries = 0; ntries < 15000; ntries++) { 5598 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5599 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5600 break; 5601 DELAY(10); 5602 } 5603 if (ntries == 15000) 5604 return ETIMEDOUT; 5605 5606 /* Hardware should be ready now. */ 5607 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5608 for (ntries = 0; ntries < 5; ntries++) { 5609 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5610 IWN_HW_IF_CONFIG_NIC_READY) 5611 return 0; 5612 DELAY(10); 5613 } 5614 return ETIMEDOUT; 5615 } 5616 5617 static int 5618 iwn_hw_init(struct iwn_softc *sc) 5619 { 5620 struct iwn_ops *ops = &sc->ops; 5621 int error, chnl, qid; 5622 5623 /* Clear pending interrupts. */ 5624 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5625 5626 if ((error = iwn_apm_init(sc)) != 0) { 5627 aprint_error_dev(sc->sc_dev, 5628 "could not power ON adapter\n"); 5629 return error; 5630 } 5631 5632 /* Select VMAIN power source. */ 5633 if ((error = iwn_nic_lock(sc)) != 0) 5634 return error; 5635 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5636 iwn_nic_unlock(sc); 5637 5638 /* Perform adapter-specific initialization. */ 5639 if ((error = ops->nic_config(sc)) != 0) 5640 return error; 5641 5642 /* Initialize RX ring. */ 5643 if ((error = iwn_nic_lock(sc)) != 0) 5644 return error; 5645 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5646 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5647 /* Set physical address of RX ring (256-byte aligned). */ 5648 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5649 /* Set physical address of RX status (16-byte aligned). */ 5650 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5651 /* Enable RX. */ 5652 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5653 IWN_FH_RX_CONFIG_ENA | 5654 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5655 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5656 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5657 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5658 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5659 iwn_nic_unlock(sc); 5660 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5661 5662 if ((error = iwn_nic_lock(sc)) != 0) 5663 return error; 5664 5665 /* Initialize TX scheduler. */ 5666 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5667 5668 /* Set physical address of "keep warm" page (16-byte aligned). */ 5669 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5670 5671 /* Initialize TX rings. */ 5672 for (qid = 0; qid < sc->ntxqs; qid++) { 5673 struct iwn_tx_ring *txq = &sc->txq[qid]; 5674 5675 /* Set physical address of TX ring (256-byte aligned). */ 5676 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5677 txq->desc_dma.paddr >> 8); 5678 } 5679 iwn_nic_unlock(sc); 5680 5681 /* Enable DMA channels. */ 5682 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5683 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5684 IWN_FH_TX_CONFIG_DMA_ENA | 5685 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5686 } 5687 5688 /* Clear "radio off" and "commands blocked" bits. */ 5689 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5690 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5691 5692 /* Clear pending interrupts. */ 5693 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5694 /* Enable interrupt coalescing. */ 5695 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5696 /* Enable interrupts. */ 5697 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5698 5699 /* _Really_ make sure "radio off" bit is cleared! */ 5700 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5701 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5702 5703 /* Enable shadow registers. */ 5704 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 5705 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 5706 5707 if ((error = ops->load_firmware(sc)) != 0) { 5708 aprint_error_dev(sc->sc_dev, 5709 "could not load firmware\n"); 5710 return error; 5711 } 5712 /* Wait at most one second for firmware alive notification. */ 5713 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5714 aprint_error_dev(sc->sc_dev, 5715 "timeout waiting for adapter to initialize\n"); 5716 return error; 5717 } 5718 /* Do post-firmware initialization. */ 5719 return ops->post_alive(sc); 5720 } 5721 5722 static void 5723 iwn_hw_stop(struct iwn_softc *sc) 5724 { 5725 int chnl, qid, ntries; 5726 5727 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5728 5729 /* Disable interrupts. */ 5730 IWN_WRITE(sc, IWN_INT_MASK, 0); 5731 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5732 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5733 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5734 5735 /* Make sure we no longer hold the NIC lock. */ 5736 iwn_nic_unlock(sc); 5737 5738 /* Stop TX scheduler. */ 5739 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5740 5741 /* Stop all DMA channels. */ 5742 if (iwn_nic_lock(sc) == 0) { 5743 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5744 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5745 for (ntries = 0; ntries < 200; ntries++) { 5746 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 5747 IWN_FH_TX_STATUS_IDLE(chnl)) 5748 break; 5749 DELAY(10); 5750 } 5751 } 5752 iwn_nic_unlock(sc); 5753 } 5754 5755 /* Stop RX ring. */ 5756 iwn_reset_rx_ring(sc, &sc->rxq); 5757 5758 /* Reset all TX rings. */ 5759 for (qid = 0; qid < sc->ntxqs; qid++) 5760 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5761 5762 if (iwn_nic_lock(sc) == 0) { 5763 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5764 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5765 iwn_nic_unlock(sc); 5766 } 5767 DELAY(5); 5768 /* Power OFF adapter. */ 5769 iwn_apm_stop(sc); 5770 } 5771 5772 static int 5773 iwn_init(struct ifnet *ifp) 5774 { 5775 struct iwn_softc *sc = ifp->if_softc; 5776 struct ieee80211com *ic = &sc->sc_ic; 5777 int error; 5778 5779 mutex_enter(&sc->sc_mtx); 5780 if (sc->sc_flags & IWN_FLAG_HW_INITED) 5781 goto out; 5782 if ((error = iwn_hw_prepare(sc)) != 0) { 5783 aprint_error_dev(sc->sc_dev, 5784 "hardware not ready\n"); 5785 goto fail; 5786 } 5787 5788 /* Check that the radio is not disabled by hardware switch. */ 5789 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5790 aprint_error_dev(sc->sc_dev, 5791 "radio is disabled by hardware switch\n"); 5792 error = EPERM; /* :-) */ 5793 goto fail; 5794 } 5795 5796 /* Read firmware images from the filesystem. */ 5797 if ((error = iwn_read_firmware(sc)) != 0) { 5798 aprint_error_dev(sc->sc_dev, 5799 "could not read firmware\n"); 5800 goto fail; 5801 } 5802 5803 /* Initialize interrupt mask to default value. */ 5804 sc->int_mask = IWN_INT_MASK_DEF; 5805 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5806 5807 /* Initialize hardware and upload firmware. */ 5808 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 5809 error = iwn_hw_init(sc); 5810 firmware_free(sc->fw.data, sc->fw.size); 5811 sc->fw.data = NULL; 5812 sc->fw.size = 0; 5813 if (error != 0) { 5814 aprint_error_dev(sc->sc_dev, 5815 "could not initialize hardware\n"); 5816 goto fail; 5817 } 5818 5819 /* Configure adapter now that it is ready. */ 5820 if ((error = iwn_config(sc)) != 0) { 5821 aprint_error_dev(sc->sc_dev, 5822 "could not configure device\n"); 5823 goto fail; 5824 } 5825 5826 ifp->if_flags &= ~IFF_OACTIVE; 5827 ifp->if_flags |= IFF_RUNNING; 5828 5829 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5830 ieee80211_begin_scan(ic, 0); 5831 else 5832 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5833 5834 sc->sc_flags |= IWN_FLAG_HW_INITED; 5835 out: 5836 mutex_exit(&sc->sc_mtx); 5837 return 0; 5838 5839 fail: mutex_exit(&sc->sc_mtx); 5840 iwn_stop(ifp, 1); 5841 return error; 5842 } 5843 5844 static void 5845 iwn_stop(struct ifnet *ifp, int disable) 5846 { 5847 struct iwn_softc *sc = ifp->if_softc; 5848 struct ieee80211com *ic = &sc->sc_ic; 5849 5850 if (!disable) 5851 mutex_enter(&sc->sc_mtx); 5852 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 5853 ifp->if_timer = sc->sc_tx_timer = 0; 5854 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5855 5856 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5857 5858 /* Power OFF hardware. */ 5859 iwn_hw_stop(sc); 5860 5861 if (!disable) 5862 mutex_exit(&sc->sc_mtx); 5863 } 5864 5865 /* 5866 * XXX MCLGETI alternative 5867 * 5868 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5869 * as long as there are available free buffers then it uses MEXTMALLOC., 5870 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5871 * The MCLGET4K code is used for testing an alternative mbuf cache. 5872 */ 5873 5874 static struct mbuf * 5875 MCLGETIalt(struct iwn_softc *sc, int how, 5876 struct ifnet *ifp __unused, u_int size) 5877 { 5878 struct mbuf *m; 5879 #ifdef IWN_USE_RBUF 5880 struct iwn_rbuf *rbuf; 5881 #endif 5882 5883 MGETHDR(m, how, MT_DATA); 5884 if (m == NULL) 5885 return NULL; 5886 5887 #ifdef IWN_USE_RBUF 5888 if (sc->rxq.nb_free_entries > 0 && 5889 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 5890 /* Attach buffer to mbuf header. */ 5891 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 5892 m->m_flags |= M_EXT_RW; 5893 } 5894 else { 5895 MEXTMALLOC(m, size, how); 5896 if ((m->m_flags & M_EXT) == 0) { 5897 m_freem(m); 5898 return NULL; 5899 } 5900 } 5901 5902 #else 5903 #ifdef MCLGET4K 5904 if (size == 4096) 5905 MCLGET4K(m, how); 5906 else 5907 panic("size must be 4k"); 5908 #else 5909 MEXTMALLOC(m, size, how); 5910 #endif 5911 if ((m->m_flags & M_EXT) == 0) { 5912 m_freem(m); 5913 return NULL; 5914 } 5915 #endif 5916 5917 return m; 5918 } 5919 5920 #ifdef IWN_USE_RBUF 5921 static struct iwn_rbuf * 5922 iwn_alloc_rbuf(struct iwn_softc *sc) 5923 { 5924 struct iwn_rbuf *rbuf; 5925 mutex_enter(&sc->rxq.freelist_mtx); 5926 5927 rbuf = SLIST_FIRST(&sc->rxq.freelist); 5928 if (rbuf != NULL) { 5929 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 5930 sc->rxq.nb_free_entries --; 5931 } 5932 mutex_exit(&sc->rxq.freelist_mtx); 5933 return rbuf; 5934 } 5935 5936 /* 5937 * This is called automatically by the network stack when the mbuf to which 5938 * our RX buffer is attached is freed. 5939 */ 5940 static void 5941 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 5942 { 5943 struct iwn_rbuf *rbuf = arg; 5944 struct iwn_softc *sc = rbuf->sc; 5945 5946 /* Put the RX buffer back in the free list. */ 5947 mutex_enter(&sc->rxq.freelist_mtx); 5948 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 5949 mutex_exit(&sc->rxq.freelist_mtx); 5950 5951 sc->rxq.nb_free_entries ++; 5952 if (__predict_true(m != NULL)) 5953 pool_cache_put(mb_cache, m); 5954 } 5955 5956 static int 5957 iwn_alloc_rpool(struct iwn_softc *sc) 5958 { 5959 struct iwn_rx_ring *ring = &sc->rxq; 5960 struct iwn_rbuf *rbuf; 5961 int i, error; 5962 5963 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 5964 5965 /* Allocate a big chunk of DMA'able memory... */ 5966 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 5967 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 5968 if (error != 0) { 5969 aprint_error_dev(sc->sc_dev, 5970 "could not allocate RX buffers DMA memory\n"); 5971 return error; 5972 } 5973 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 5974 SLIST_INIT(&ring->freelist); 5975 for (i = 0; i < IWN_RBUF_COUNT; i++) { 5976 rbuf = &ring->rbuf[i]; 5977 5978 rbuf->sc = sc; /* Backpointer for callbacks. */ 5979 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 5980 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 5981 5982 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 5983 } 5984 ring->nb_free_entries = IWN_RBUF_COUNT; 5985 return 0; 5986 } 5987 5988 static void 5989 iwn_free_rpool(struct iwn_softc *sc) 5990 { 5991 iwn_dma_contig_free(&sc->rxq.buf_dma); 5992 } 5993 #endif 5994 5995 /* 5996 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 5997 * Copyright (c) 2001 Atsushi Onoe 5998 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 5999 * Copyright (c) 2007-2009 Damien Bergamini 6000 * All rights reserved. 6001 */ 6002 6003 /* 6004 * Add an SSID element to a frame (see 7.3.2.1). 6005 */ 6006 static u_int8_t * 6007 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6008 { 6009 *frm++ = IEEE80211_ELEMID_SSID; 6010 *frm++ = len; 6011 memcpy(frm, ssid, len); 6012 return frm + len; 6013 } 6014 6015 /* 6016 * Add a supported rates element to a frame (see 7.3.2.2). 6017 */ 6018 static u_int8_t * 6019 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6020 { 6021 int nrates; 6022 6023 *frm++ = IEEE80211_ELEMID_RATES; 6024 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6025 *frm++ = nrates; 6026 memcpy(frm, rs->rs_rates, nrates); 6027 return frm + nrates; 6028 } 6029 6030 /* 6031 * Add an extended supported rates element to a frame (see 7.3.2.14). 6032 */ 6033 static u_int8_t * 6034 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6035 { 6036 int nrates; 6037 6038 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6039 6040 *frm++ = IEEE80211_ELEMID_XRATES; 6041 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6042 *frm++ = nrates; 6043 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6044 return frm + nrates; 6045 } 6046 6047 /* 6048 * XXX: Hack to set the current channel to the value advertised in beacons or 6049 * probe responses. Only used during AP detection. 6050 * XXX: Duplicated from if_iwi.c 6051 */ 6052 static void 6053 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6054 { 6055 struct ieee80211_frame *wh; 6056 uint8_t subtype; 6057 uint8_t *frm, *efrm; 6058 6059 wh = mtod(m, struct ieee80211_frame *); 6060 6061 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6062 return; 6063 6064 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6065 6066 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6067 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6068 return; 6069 6070 frm = (uint8_t *)(wh + 1); 6071 efrm = mtod(m, uint8_t *) + m->m_len; 6072 6073 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6074 while (frm < efrm) { 6075 if (*frm == IEEE80211_ELEMID_DSPARMS) 6076 #if IEEE80211_CHAN_MAX < 255 6077 if (frm[2] <= IEEE80211_CHAN_MAX) 6078 #endif 6079 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6080 6081 frm += frm[1] + 2; 6082 } 6083 } 6084 6085
Indexes created Mon Sep 29 18:09:42 GMT 2025