if_iwn.c revision 1.62.2.1
1 /* $NetBSD: if_iwn.c,v 1.62.2.1 2015/11/15 20:27:34 bouyer Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.96 2010/05/13 09:25:03 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.62.2.1 2015/11/15 20:27:34 bouyer Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/conf.h> 40 #include <sys/kauth.h> 41 #include <sys/callout.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <machine/intr.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcidevs.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_arp.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <net/if_ether.h> 64 #include <netinet/ip.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_amrr.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <dev/firmload.h> 71 72 #include <dev/pci/if_iwnreg.h> 73 #include <dev/pci/if_iwnvar.h> 74 75 static const pci_product_id_t iwn_devices[] = { 76 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 77 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 78 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 79 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 80 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 82 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 83 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 84 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 90 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 91 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 92 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 93 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 94 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 102 }; 103 104 /* 105 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 106 */ 107 static const struct ieee80211_rateset iwn_rateset_11a = 108 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 109 110 static const struct ieee80211_rateset iwn_rateset_11b = 111 { 4, { 2, 4, 11, 22 } }; 112 113 static const struct ieee80211_rateset iwn_rateset_11g = 114 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 115 116 static int iwn_match(device_t , struct cfdata *, void *); 117 static void iwn_attach(device_t , device_t , void *); 118 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 119 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 120 static void iwn_radiotap_attach(struct iwn_softc *); 121 static int iwn_detach(device_t , int); 122 #if 0 123 static void iwn_power(int, void *); 124 #endif 125 static bool iwn_resume(device_t, const pmf_qual_t *); 126 static int iwn_nic_lock(struct iwn_softc *); 127 static int iwn_eeprom_lock(struct iwn_softc *); 128 static int iwn_init_otprom(struct iwn_softc *); 129 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 130 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 131 void **, bus_size_t, bus_size_t); 132 static void iwn_dma_contig_free(struct iwn_dma_info *); 133 static int iwn_alloc_sched(struct iwn_softc *); 134 static void iwn_free_sched(struct iwn_softc *); 135 static int iwn_alloc_kw(struct iwn_softc *); 136 static void iwn_free_kw(struct iwn_softc *); 137 static int iwn_alloc_ict(struct iwn_softc *); 138 static void iwn_free_ict(struct iwn_softc *); 139 static int iwn_alloc_fwmem(struct iwn_softc *); 140 static void iwn_free_fwmem(struct iwn_softc *); 141 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 142 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 143 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 144 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 145 int); 146 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 147 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 148 static void iwn5000_ict_reset(struct iwn_softc *); 149 static int iwn_read_eeprom(struct iwn_softc *); 150 static void iwn4965_read_eeprom(struct iwn_softc *); 151 152 #ifdef IWN_DEBUG 153 static void iwn4965_print_power_group(struct iwn_softc *, int); 154 #endif 155 static void iwn5000_read_eeprom(struct iwn_softc *); 156 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 157 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 158 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 159 static void iwn_newassoc(struct ieee80211_node *, int); 160 static int iwn_media_change(struct ifnet *); 161 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 162 static void iwn_iter_func(void *, struct ieee80211_node *); 163 static void iwn_calib_timeout(void *); 164 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 165 struct iwn_rx_data *); 166 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 167 struct iwn_rx_data *); 168 #ifndef IEEE80211_NO_HT 169 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 170 struct iwn_rx_data *); 171 #endif 172 static void iwn5000_rx_calib_results(struct iwn_softc *, 173 struct iwn_rx_desc *, struct iwn_rx_data *); 174 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 179 struct iwn_rx_data *); 180 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 181 uint8_t); 182 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 183 static void iwn_notif_intr(struct iwn_softc *); 184 static void iwn_wakeup_intr(struct iwn_softc *); 185 static void iwn_fatal_intr(struct iwn_softc *); 186 static int iwn_intr(void *); 187 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 188 uint16_t); 189 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 190 uint16_t); 191 #ifdef notyet 192 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 193 #endif 194 static int iwn_tx(struct iwn_softc *, struct mbuf *, 195 struct ieee80211_node *, int); 196 static void iwn_start(struct ifnet *); 197 static void iwn_watchdog(struct ifnet *); 198 static int iwn_ioctl(struct ifnet *, u_long, void *); 199 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 200 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 201 int); 202 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 203 int); 204 static int iwn_set_link_quality(struct iwn_softc *, 205 struct ieee80211_node *); 206 static int iwn_add_broadcast_node(struct iwn_softc *, int); 207 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 208 static int iwn_set_critical_temp(struct iwn_softc *); 209 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 210 static void iwn4965_power_calibration(struct iwn_softc *, int); 211 static int iwn4965_set_txpower(struct iwn_softc *, int); 212 static int iwn5000_set_txpower(struct iwn_softc *, int); 213 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 214 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 215 static int iwn_get_noise(const struct iwn_rx_general_stats *); 216 static int iwn4965_get_temperature(struct iwn_softc *); 217 static int iwn5000_get_temperature(struct iwn_softc *); 218 static int iwn_init_sensitivity(struct iwn_softc *); 219 static void iwn_collect_noise(struct iwn_softc *, 220 const struct iwn_rx_general_stats *); 221 static int iwn4965_init_gains(struct iwn_softc *); 222 static int iwn5000_init_gains(struct iwn_softc *); 223 static int iwn4965_set_gains(struct iwn_softc *); 224 static int iwn5000_set_gains(struct iwn_softc *); 225 static void iwn_tune_sensitivity(struct iwn_softc *, 226 const struct iwn_rx_stats *); 227 static int iwn_send_sensitivity(struct iwn_softc *); 228 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 229 static int iwn5000_runtime_calib(struct iwn_softc *); 230 static int iwn_config(struct iwn_softc *); 231 static int iwn_scan(struct iwn_softc *, uint16_t); 232 static int iwn_auth(struct iwn_softc *); 233 static int iwn_run(struct iwn_softc *); 234 #ifdef IWN_HWCRYPTO 235 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 236 struct ieee80211_key *); 237 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 238 struct ieee80211_key *); 239 #endif 240 static int iwn_wme_update(struct ieee80211com *); 241 #ifndef IEEE80211_NO_HT 242 static int iwn_ampdu_rx_start(struct ieee80211com *, 243 struct ieee80211_node *, uint8_t); 244 static void iwn_ampdu_rx_stop(struct ieee80211com *, 245 struct ieee80211_node *, uint8_t); 246 static int iwn_ampdu_tx_start(struct ieee80211com *, 247 struct ieee80211_node *, uint8_t); 248 static void iwn_ampdu_tx_stop(struct ieee80211com *, 249 struct ieee80211_node *, uint8_t); 250 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 251 struct ieee80211_node *, uint8_t, uint16_t); 252 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 253 uint8_t, uint16_t); 254 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 255 struct ieee80211_node *, uint8_t, uint16_t); 256 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 257 uint8_t, uint16_t); 258 #endif 259 static int iwn5000_query_calibration(struct iwn_softc *); 260 static int iwn5000_send_calibration(struct iwn_softc *); 261 static int iwn5000_send_wimax_coex(struct iwn_softc *); 262 static int iwn4965_post_alive(struct iwn_softc *); 263 static int iwn5000_post_alive(struct iwn_softc *); 264 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 265 int); 266 static int iwn4965_load_firmware(struct iwn_softc *); 267 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 268 const uint8_t *, int); 269 static int iwn5000_load_firmware(struct iwn_softc *); 270 static int iwn_read_firmware_leg(struct iwn_softc *, 271 struct iwn_fw_info *); 272 static int iwn_read_firmware_tlv(struct iwn_softc *, 273 struct iwn_fw_info *, uint16_t); 274 static int iwn_read_firmware(struct iwn_softc *); 275 static int iwn_clock_wait(struct iwn_softc *); 276 static int iwn_apm_init(struct iwn_softc *); 277 static void iwn_apm_stop_master(struct iwn_softc *); 278 static void iwn_apm_stop(struct iwn_softc *); 279 static int iwn4965_nic_config(struct iwn_softc *); 280 static int iwn5000_nic_config(struct iwn_softc *); 281 static int iwn_hw_prepare(struct iwn_softc *); 282 static int iwn_hw_init(struct iwn_softc *); 283 static void iwn_hw_stop(struct iwn_softc *); 284 static int iwn_init(struct ifnet *); 285 static void iwn_stop(struct ifnet *, int); 286 287 /* XXX MCLGETI alternative */ 288 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 289 struct ifnet *, u_int); 290 #ifdef IWN_USE_RBUF 291 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 292 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 293 static int iwn_alloc_rpool(struct iwn_softc *); 294 static void iwn_free_rpool(struct iwn_softc *); 295 #endif 296 297 /* XXX needed by iwn_scan */ 298 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 299 static u_int8_t *ieee80211_add_rates(u_int8_t *, 300 const struct ieee80211_rateset *); 301 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 302 const struct ieee80211_rateset *); 303 304 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *, 305 struct iwn_rx_stat *); 306 307 #ifdef IWN_DEBUG 308 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 309 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 310 int iwn_debug = 0; 311 #else 312 #define DPRINTF(x) 313 #define DPRINTFN(n, x) 314 #endif 315 316 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 317 iwn_detach, NULL); 318 319 static int 320 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 321 { 322 struct pci_attach_args *pa = aux; 323 size_t i; 324 325 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 326 return 0; 327 328 for (i = 0; i < __arraycount(iwn_devices); i++) 329 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 330 return 1; 331 332 return 0; 333 } 334 335 static void 336 iwn_attach(device_t parent __unused, device_t self, void *aux) 337 { 338 struct iwn_softc *sc = device_private(self); 339 struct ieee80211com *ic = &sc->sc_ic; 340 struct ifnet *ifp = &sc->sc_ec.ec_if; 341 struct pci_attach_args *pa = aux; 342 const char *intrstr; 343 pci_intr_handle_t ih; 344 pcireg_t memtype, reg; 345 int i, error; 346 347 sc->sc_dev = self; 348 sc->sc_pct = pa->pa_pc; 349 sc->sc_pcitag = pa->pa_tag; 350 sc->sc_dmat = pa->pa_dmat; 351 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 352 353 callout_init(&sc->calib_to, 0); 354 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 355 356 pci_aprint_devinfo(pa, NULL); 357 358 /* 359 * Get the offset of the PCI Express Capability Structure in PCI 360 * Configuration Space. 361 */ 362 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 363 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 364 if (error == 0) { 365 aprint_error(": PCIe capability structure not found!\n"); 366 return; 367 } 368 369 /* Clear device-specific "PCI retry timeout" register (41h). */ 370 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 371 if (reg & 0xff00) 372 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 373 374 /* Enable bus-mastering and hardware bug workaround. */ 375 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 376 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 377 reg |= PCI_COMMAND_MASTER_ENABLE; 378 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 379 DPRINTF(("PCIe INTx Disable set\n")); 380 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 381 } 382 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 383 384 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 385 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 386 &sc->sc_sh, NULL, &sc->sc_sz); 387 if (error != 0) { 388 aprint_error(": can't map mem space\n"); 389 return; 390 } 391 392 /* Install interrupt handler. */ 393 if (pci_intr_map(pa, &ih) != 0) { 394 aprint_error(": can't map interrupt\n"); 395 return; 396 } 397 intrstr = pci_intr_string(sc->sc_pct, ih); 398 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 399 if (sc->sc_ih == NULL) { 400 aprint_error(": can't establish interrupt"); 401 if (intrstr != NULL) 402 aprint_error(" at %s", intrstr); 403 aprint_error("\n"); 404 return; 405 } 406 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 407 408 /* Read hardware revision and attach. */ 409 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 410 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 411 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 412 else 413 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 414 if (error != 0) { 415 aprint_error(": could not attach device\n"); 416 return; 417 } 418 419 if ((error = iwn_hw_prepare(sc)) != 0) { 420 aprint_error(": hardware not ready\n"); 421 return; 422 } 423 424 /* Read MAC address, channels, etc from EEPROM. */ 425 if ((error = iwn_read_eeprom(sc)) != 0) { 426 aprint_error(": could not read EEPROM\n"); 427 return; 428 } 429 430 /* Allocate DMA memory for firmware transfers. */ 431 if ((error = iwn_alloc_fwmem(sc)) != 0) { 432 aprint_error(": could not allocate memory for firmware\n"); 433 return; 434 } 435 436 /* Allocate "Keep Warm" page. */ 437 if ((error = iwn_alloc_kw(sc)) != 0) { 438 aprint_error(": could not allocate keep warm page\n"); 439 goto fail1; 440 } 441 442 /* Allocate ICT table for 5000 Series. */ 443 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 444 (error = iwn_alloc_ict(sc)) != 0) { 445 aprint_error(": could not allocate ICT table\n"); 446 goto fail2; 447 } 448 449 /* Allocate TX scheduler "rings". */ 450 if ((error = iwn_alloc_sched(sc)) != 0) { 451 aprint_error(": could not allocate TX scheduler rings\n"); 452 goto fail3; 453 } 454 455 #ifdef IWN_USE_RBUF 456 /* Allocate RX buffers. */ 457 if ((error = iwn_alloc_rpool(sc)) != 0) { 458 aprint_error_dev(self, "could not allocate RX buffers\n"); 459 goto fail3; 460 } 461 #endif 462 463 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 464 for (i = 0; i < sc->ntxqs; i++) { 465 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 466 aprint_error(": could not allocate TX ring %d\n", i); 467 goto fail4; 468 } 469 } 470 471 /* Allocate RX ring. */ 472 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 473 aprint_error(": could not allocate RX ring\n"); 474 goto fail4; 475 } 476 477 /* Clear pending interrupts. */ 478 IWN_WRITE(sc, IWN_INT, 0xffffffff); 479 480 /* Count the number of available chains. */ 481 sc->ntxchains = 482 ((sc->txchainmask >> 2) & 1) + 483 ((sc->txchainmask >> 1) & 1) + 484 ((sc->txchainmask >> 0) & 1); 485 sc->nrxchains = 486 ((sc->rxchainmask >> 2) & 1) + 487 ((sc->rxchainmask >> 1) & 1) + 488 ((sc->rxchainmask >> 0) & 1); 489 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 490 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 491 ether_sprintf(ic->ic_myaddr)); 492 493 ic->ic_ifp = ifp; 494 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 495 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 496 ic->ic_state = IEEE80211_S_INIT; 497 498 /* Set device capabilities. */ 499 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 500 * and IEEE80211_C_PMGT too. */ 501 ic->ic_caps = 502 IEEE80211_C_IBSS | /* IBSS mode support */ 503 IEEE80211_C_WPA | /* 802.11i */ 504 IEEE80211_C_MONITOR | /* monitor mode supported */ 505 IEEE80211_C_TXPMGT | /* tx power management */ 506 IEEE80211_C_SHSLOT | /* short slot time supported */ 507 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 508 IEEE80211_C_WME; /* 802.11e */ 509 510 #ifndef IEEE80211_NO_HT 511 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 512 /* Set HT capabilities. */ 513 ic->ic_htcaps = 514 #if IWN_RBUF_SIZE == 8192 515 IEEE80211_HTCAP_AMSDU7935 | 516 #endif 517 IEEE80211_HTCAP_CBW20_40 | 518 IEEE80211_HTCAP_SGI20 | 519 IEEE80211_HTCAP_SGI40; 520 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 521 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 522 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 523 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 524 else 525 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 526 } 527 #endif /* !IEEE80211_NO_HT */ 528 529 /* Set supported legacy rates. */ 530 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 531 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 532 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 533 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 534 } 535 #ifndef IEEE80211_NO_HT 536 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 537 /* Set supported HT rates. */ 538 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 539 if (sc->nrxchains > 1) 540 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 541 if (sc->nrxchains > 2) 542 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 543 } 544 #endif 545 546 /* IBSS channel undefined for now. */ 547 ic->ic_ibss_chan = &ic->ic_channels[0]; 548 549 ifp->if_softc = sc; 550 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 551 ifp->if_init = iwn_init; 552 ifp->if_ioctl = iwn_ioctl; 553 ifp->if_start = iwn_start; 554 ifp->if_stop = iwn_stop; 555 ifp->if_watchdog = iwn_watchdog; 556 IFQ_SET_READY(&ifp->if_snd); 557 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 558 559 if_attach(ifp); 560 ieee80211_ifattach(ic); 561 ic->ic_node_alloc = iwn_node_alloc; 562 ic->ic_newassoc = iwn_newassoc; 563 #ifdef IWN_HWCRYPTO 564 ic->ic_crypto.cs_key_set = iwn_set_key; 565 ic->ic_crypto.cs_key_delete = iwn_delete_key; 566 #endif 567 ic->ic_wme.wme_update = iwn_wme_update; 568 #ifndef IEEE80211_NO_HT 569 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 570 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 571 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 572 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 573 #endif 574 575 /* Override 802.11 state transition machine. */ 576 sc->sc_newstate = ic->ic_newstate; 577 ic->ic_newstate = iwn_newstate; 578 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 579 580 sc->amrr.amrr_min_success_threshold = 1; 581 sc->amrr.amrr_max_success_threshold = 15; 582 583 iwn_radiotap_attach(sc); 584 585 /* 586 * XXX for NetBSD, OpenBSD timeout_set replaced by 587 * callout_init and callout_setfunc, above. 588 */ 589 590 if (pmf_device_register(self, NULL, iwn_resume)) 591 pmf_class_network_register(self, ifp); 592 else 593 aprint_error_dev(self, "couldn't establish power handler\n"); 594 595 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 596 ieee80211_announce(ic); 597 598 return; 599 600 /* Free allocated memory if something failed during attachment. */ 601 fail4: while (--i >= 0) 602 iwn_free_tx_ring(sc, &sc->txq[i]); 603 #ifdef IWN_USE_RBUF 604 iwn_free_rpool(sc); 605 #endif 606 iwn_free_sched(sc); 607 fail3: if (sc->ict != NULL) 608 iwn_free_ict(sc); 609 fail2: iwn_free_kw(sc); 610 fail1: iwn_free_fwmem(sc); 611 } 612 613 int 614 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 615 { 616 struct iwn_ops *ops = &sc->ops; 617 618 ops->load_firmware = iwn4965_load_firmware; 619 ops->read_eeprom = iwn4965_read_eeprom; 620 ops->post_alive = iwn4965_post_alive; 621 ops->nic_config = iwn4965_nic_config; 622 ops->update_sched = iwn4965_update_sched; 623 ops->get_temperature = iwn4965_get_temperature; 624 ops->get_rssi = iwn4965_get_rssi; 625 ops->set_txpower = iwn4965_set_txpower; 626 ops->init_gains = iwn4965_init_gains; 627 ops->set_gains = iwn4965_set_gains; 628 ops->add_node = iwn4965_add_node; 629 ops->tx_done = iwn4965_tx_done; 630 #ifndef IEEE80211_NO_HT 631 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 632 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 633 #endif 634 sc->ntxqs = IWN4965_NTXQUEUES; 635 sc->ndmachnls = IWN4965_NDMACHNLS; 636 sc->broadcast_id = IWN4965_ID_BROADCAST; 637 sc->rxonsz = IWN4965_RXONSZ; 638 sc->schedsz = IWN4965_SCHEDSZ; 639 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 640 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 641 sc->fwsz = IWN4965_FWSZ; 642 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 643 sc->limits = &iwn4965_sensitivity_limits; 644 sc->fwname = "iwlwifi-4965-2.ucode"; 645 /* Override chains masks, ROM is known to be broken. */ 646 sc->txchainmask = IWN_ANT_AB; 647 sc->rxchainmask = IWN_ANT_ABC; 648 649 return 0; 650 } 651 652 int 653 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 654 { 655 struct iwn_ops *ops = &sc->ops; 656 657 ops->load_firmware = iwn5000_load_firmware; 658 ops->read_eeprom = iwn5000_read_eeprom; 659 ops->post_alive = iwn5000_post_alive; 660 ops->nic_config = iwn5000_nic_config; 661 ops->update_sched = iwn5000_update_sched; 662 ops->get_temperature = iwn5000_get_temperature; 663 ops->get_rssi = iwn5000_get_rssi; 664 ops->set_txpower = iwn5000_set_txpower; 665 ops->init_gains = iwn5000_init_gains; 666 ops->set_gains = iwn5000_set_gains; 667 ops->add_node = iwn5000_add_node; 668 ops->tx_done = iwn5000_tx_done; 669 #ifndef IEEE80211_NO_HT 670 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 671 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 672 #endif 673 sc->ntxqs = IWN5000_NTXQUEUES; 674 sc->ndmachnls = IWN5000_NDMACHNLS; 675 sc->broadcast_id = IWN5000_ID_BROADCAST; 676 sc->rxonsz = IWN5000_RXONSZ; 677 sc->schedsz = IWN5000_SCHEDSZ; 678 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 679 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 680 sc->fwsz = IWN5000_FWSZ; 681 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 682 683 switch (sc->hw_type) { 684 case IWN_HW_REV_TYPE_5100: 685 sc->limits = &iwn5000_sensitivity_limits; 686 sc->fwname = "iwlwifi-5000-2.ucode"; 687 /* Override chains masks, ROM is known to be broken. */ 688 sc->txchainmask = IWN_ANT_B; 689 sc->rxchainmask = IWN_ANT_AB; 690 break; 691 case IWN_HW_REV_TYPE_5150: 692 sc->limits = &iwn5150_sensitivity_limits; 693 sc->fwname = "iwlwifi-5150-2.ucode"; 694 break; 695 case IWN_HW_REV_TYPE_5300: 696 case IWN_HW_REV_TYPE_5350: 697 sc->limits = &iwn5000_sensitivity_limits; 698 sc->fwname = "iwlwifi-5000-2.ucode"; 699 break; 700 case IWN_HW_REV_TYPE_1000: 701 sc->limits = &iwn1000_sensitivity_limits; 702 sc->fwname = "iwlwifi-1000-3.ucode"; 703 break; 704 case IWN_HW_REV_TYPE_6000: 705 sc->limits = &iwn6000_sensitivity_limits; 706 sc->fwname = "iwlwifi-6000-4.ucode"; 707 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 708 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 709 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 710 /* Override chains masks, ROM is known to be broken. */ 711 sc->txchainmask = IWN_ANT_BC; 712 sc->rxchainmask = IWN_ANT_BC; 713 } 714 break; 715 case IWN_HW_REV_TYPE_6050: 716 sc->limits = &iwn6000_sensitivity_limits; 717 sc->fwname = "iwlwifi-6050-5.ucode"; 718 break; 719 case IWN_HW_REV_TYPE_6005: 720 sc->limits = &iwn6000_sensitivity_limits; 721 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 722 break; 723 default: 724 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 725 return ENOTSUP; 726 } 727 return 0; 728 } 729 730 /* 731 * Attach the interface to 802.11 radiotap. 732 */ 733 static void 734 iwn_radiotap_attach(struct iwn_softc *sc) 735 { 736 struct ifnet *ifp = sc->sc_ic.ic_ifp; 737 738 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 739 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 740 &sc->sc_drvbpf); 741 742 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 743 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 744 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 745 746 sc->sc_txtap_len = sizeof sc->sc_txtapu; 747 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 748 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 749 } 750 751 static int 752 iwn_detach(device_t self, int flags __unused) 753 { 754 struct iwn_softc *sc = device_private(self); 755 struct ifnet *ifp = sc->sc_ic.ic_ifp; 756 int qid; 757 758 callout_stop(&sc->calib_to); 759 760 /* Uninstall interrupt handler. */ 761 if (sc->sc_ih != NULL) 762 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 763 764 /* Free DMA resources. */ 765 iwn_free_rx_ring(sc, &sc->rxq); 766 for (qid = 0; qid < sc->ntxqs; qid++) 767 iwn_free_tx_ring(sc, &sc->txq[qid]); 768 #ifdef IWN_USE_RBUF 769 iwn_free_rpool(sc); 770 #endif 771 iwn_free_sched(sc); 772 iwn_free_kw(sc); 773 if (sc->ict != NULL) 774 iwn_free_ict(sc); 775 iwn_free_fwmem(sc); 776 777 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 778 779 ieee80211_ifdetach(&sc->sc_ic); 780 if_detach(ifp); 781 782 return 0; 783 } 784 785 #if 0 786 /* 787 * XXX Investigate if clearing the PCI retry timeout could eliminate 788 * the repeated scan calls. Also the calls to if_init and if_start 789 * are similar to the effect of adding the call to ifioctl_common . 790 */ 791 static void 792 iwn_power(int why, void *arg) 793 { 794 struct iwn_softc *sc = arg; 795 struct ifnet *ifp; 796 pcireg_t reg; 797 int s; 798 799 if (why != PWR_RESUME) 800 return; 801 802 /* Clear device-specific "PCI retry timeout" register (41h). */ 803 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 804 if (reg & 0xff00) 805 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 806 807 s = splnet(); 808 ifp = &sc->sc_ic.ic_if; 809 if (ifp->if_flags & IFF_UP) { 810 ifp->if_init(ifp); 811 if (ifp->if_flags & IFF_RUNNING) 812 ifp->if_start(ifp); 813 } 814 splx(s); 815 } 816 #endif 817 818 static bool 819 iwn_resume(device_t dv, const pmf_qual_t *qual) 820 { 821 return true; 822 } 823 824 static int 825 iwn_nic_lock(struct iwn_softc *sc) 826 { 827 int ntries; 828 829 /* Request exclusive access to NIC. */ 830 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 831 832 /* Spin until we actually get the lock. */ 833 for (ntries = 0; ntries < 1000; ntries++) { 834 if ((IWN_READ(sc, IWN_GP_CNTRL) & 835 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 836 IWN_GP_CNTRL_MAC_ACCESS_ENA) 837 return 0; 838 DELAY(10); 839 } 840 return ETIMEDOUT; 841 } 842 843 static __inline void 844 iwn_nic_unlock(struct iwn_softc *sc) 845 { 846 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 847 } 848 849 static __inline uint32_t 850 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 851 { 852 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 853 IWN_BARRIER_READ_WRITE(sc); 854 return IWN_READ(sc, IWN_PRPH_RDATA); 855 } 856 857 static __inline void 858 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 859 { 860 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 861 IWN_BARRIER_WRITE(sc); 862 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 863 } 864 865 static __inline void 866 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 867 { 868 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 869 } 870 871 static __inline void 872 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 873 { 874 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 875 } 876 877 static __inline void 878 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 879 const uint32_t *data, int count) 880 { 881 for (; count > 0; count--, data++, addr += 4) 882 iwn_prph_write(sc, addr, *data); 883 } 884 885 static __inline uint32_t 886 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 887 { 888 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 889 IWN_BARRIER_READ_WRITE(sc); 890 return IWN_READ(sc, IWN_MEM_RDATA); 891 } 892 893 static __inline void 894 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 895 { 896 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 897 IWN_BARRIER_WRITE(sc); 898 IWN_WRITE(sc, IWN_MEM_WDATA, data); 899 } 900 901 static __inline void 902 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 903 { 904 uint32_t tmp; 905 906 tmp = iwn_mem_read(sc, addr & ~3); 907 if (addr & 3) 908 tmp = (tmp & 0x0000ffff) | data << 16; 909 else 910 tmp = (tmp & 0xffff0000) | data; 911 iwn_mem_write(sc, addr & ~3, tmp); 912 } 913 914 static __inline void 915 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 916 int count) 917 { 918 for (; count > 0; count--, addr += 4) 919 *data++ = iwn_mem_read(sc, addr); 920 } 921 922 static __inline void 923 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 924 int count) 925 { 926 for (; count > 0; count--, addr += 4) 927 iwn_mem_write(sc, addr, val); 928 } 929 930 static int 931 iwn_eeprom_lock(struct iwn_softc *sc) 932 { 933 int i, ntries; 934 935 for (i = 0; i < 100; i++) { 936 /* Request exclusive access to EEPROM. */ 937 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 938 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 939 940 /* Spin until we actually get the lock. */ 941 for (ntries = 0; ntries < 100; ntries++) { 942 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 943 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 944 return 0; 945 DELAY(10); 946 } 947 } 948 return ETIMEDOUT; 949 } 950 951 static __inline void 952 iwn_eeprom_unlock(struct iwn_softc *sc) 953 { 954 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 955 } 956 957 /* 958 * Initialize access by host to One Time Programmable ROM. 959 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 960 */ 961 static int 962 iwn_init_otprom(struct iwn_softc *sc) 963 { 964 uint16_t prev = 0, base, next; 965 int count, error; 966 967 /* Wait for clock stabilization before accessing prph. */ 968 if ((error = iwn_clock_wait(sc)) != 0) 969 return error; 970 971 if ((error = iwn_nic_lock(sc)) != 0) 972 return error; 973 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 974 DELAY(5); 975 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 976 iwn_nic_unlock(sc); 977 978 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 979 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 980 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 981 IWN_RESET_LINK_PWR_MGMT_DIS); 982 } 983 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 984 /* Clear ECC status. */ 985 IWN_SETBITS(sc, IWN_OTP_GP, 986 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 987 988 /* 989 * Find the block before last block (contains the EEPROM image) 990 * for HW without OTP shadow RAM. 991 */ 992 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 993 /* Switch to absolute addressing mode. */ 994 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 995 base = 0; 996 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 997 error = iwn_read_prom_data(sc, base, &next, 2); 998 if (error != 0) 999 return error; 1000 if (next == 0) /* End of linked-list. */ 1001 break; 1002 prev = base; 1003 base = le16toh(next); 1004 } 1005 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1006 return EIO; 1007 /* Skip "next" word. */ 1008 sc->prom_base = prev + 1; 1009 } 1010 return 0; 1011 } 1012 1013 static int 1014 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1015 { 1016 uint8_t *out = data; 1017 uint32_t val, tmp; 1018 int ntries; 1019 1020 addr += sc->prom_base; 1021 for (; count > 0; count -= 2, addr++) { 1022 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1023 for (ntries = 0; ntries < 10; ntries++) { 1024 val = IWN_READ(sc, IWN_EEPROM); 1025 if (val & IWN_EEPROM_READ_VALID) 1026 break; 1027 DELAY(5); 1028 } 1029 if (ntries == 10) { 1030 aprint_error_dev(sc->sc_dev, 1031 "timeout reading ROM at 0x%x\n", addr); 1032 return ETIMEDOUT; 1033 } 1034 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1035 /* OTPROM, check for ECC errors. */ 1036 tmp = IWN_READ(sc, IWN_OTP_GP); 1037 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1038 aprint_error_dev(sc->sc_dev, 1039 "OTPROM ECC error at 0x%x\n", addr); 1040 return EIO; 1041 } 1042 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1043 /* Correctable ECC error, clear bit. */ 1044 IWN_SETBITS(sc, IWN_OTP_GP, 1045 IWN_OTP_GP_ECC_CORR_STTS); 1046 } 1047 } 1048 *out++ = val >> 16; 1049 if (count > 1) 1050 *out++ = val >> 24; 1051 } 1052 return 0; 1053 } 1054 1055 static int 1056 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1057 bus_size_t size, bus_size_t alignment) 1058 { 1059 int nsegs, error; 1060 1061 dma->tag = tag; 1062 dma->size = size; 1063 1064 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1065 &dma->map); 1066 if (error != 0) 1067 goto fail; 1068 1069 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1070 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1071 if (error != 0) 1072 goto fail; 1073 1074 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1075 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1076 if (error != 0) 1077 goto fail; 1078 1079 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1080 BUS_DMA_NOWAIT); 1081 if (error != 0) 1082 goto fail; 1083 1084 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1085 memset(dma->vaddr, 0, size); 1086 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1087 1088 dma->paddr = dma->map->dm_segs[0].ds_addr; 1089 if (kvap != NULL) 1090 *kvap = dma->vaddr; 1091 1092 return 0; 1093 1094 fail: iwn_dma_contig_free(dma); 1095 return error; 1096 } 1097 1098 static void 1099 iwn_dma_contig_free(struct iwn_dma_info *dma) 1100 { 1101 if (dma->map != NULL) { 1102 if (dma->vaddr != NULL) { 1103 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1104 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1105 bus_dmamap_unload(dma->tag, dma->map); 1106 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1107 bus_dmamem_free(dma->tag, &dma->seg, 1); 1108 dma->vaddr = NULL; 1109 } 1110 bus_dmamap_destroy(dma->tag, dma->map); 1111 dma->map = NULL; 1112 } 1113 } 1114 1115 static int 1116 iwn_alloc_sched(struct iwn_softc *sc) 1117 { 1118 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1119 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1120 (void **)&sc->sched, sc->schedsz, 1024); 1121 } 1122 1123 static void 1124 iwn_free_sched(struct iwn_softc *sc) 1125 { 1126 iwn_dma_contig_free(&sc->sched_dma); 1127 } 1128 1129 static int 1130 iwn_alloc_kw(struct iwn_softc *sc) 1131 { 1132 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1133 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1134 4096); 1135 } 1136 1137 static void 1138 iwn_free_kw(struct iwn_softc *sc) 1139 { 1140 iwn_dma_contig_free(&sc->kw_dma); 1141 } 1142 1143 static int 1144 iwn_alloc_ict(struct iwn_softc *sc) 1145 { 1146 /* ICT table must be aligned on a 4KB boundary. */ 1147 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1148 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1149 } 1150 1151 static void 1152 iwn_free_ict(struct iwn_softc *sc) 1153 { 1154 iwn_dma_contig_free(&sc->ict_dma); 1155 } 1156 1157 static int 1158 iwn_alloc_fwmem(struct iwn_softc *sc) 1159 { 1160 /* Must be aligned on a 16-byte boundary. */ 1161 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1162 sc->fwsz, 16); 1163 } 1164 1165 static void 1166 iwn_free_fwmem(struct iwn_softc *sc) 1167 { 1168 iwn_dma_contig_free(&sc->fw_dma); 1169 } 1170 1171 static int 1172 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1173 { 1174 bus_size_t size; 1175 int i, error; 1176 1177 ring->cur = 0; 1178 1179 /* Allocate RX descriptors (256-byte aligned). */ 1180 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1181 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1182 (void **)&ring->desc, size, 256); 1183 if (error != 0) { 1184 aprint_error_dev(sc->sc_dev, 1185 "could not allocate RX ring DMA memory\n"); 1186 goto fail; 1187 } 1188 1189 /* Allocate RX status area (16-byte aligned). */ 1190 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1191 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1192 if (error != 0) { 1193 aprint_error_dev(sc->sc_dev, 1194 "could not allocate RX status DMA memory\n"); 1195 goto fail; 1196 } 1197 1198 /* 1199 * Allocate and map RX buffers. 1200 */ 1201 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1202 struct iwn_rx_data *data = &ring->data[i]; 1203 1204 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1205 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1206 &data->map); 1207 if (error != 0) { 1208 aprint_error_dev(sc->sc_dev, 1209 "could not create RX buf DMA map\n"); 1210 goto fail; 1211 } 1212 1213 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1214 if (data->m == NULL) { 1215 aprint_error_dev(sc->sc_dev, 1216 "could not allocate RX mbuf\n"); 1217 error = ENOBUFS; 1218 goto fail; 1219 } 1220 1221 error = bus_dmamap_load(sc->sc_dmat, data->map, 1222 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1223 BUS_DMA_NOWAIT | BUS_DMA_READ); 1224 if (error != 0) { 1225 aprint_error_dev(sc->sc_dev, 1226 "can't not map mbuf (error %d)\n", error); 1227 goto fail; 1228 } 1229 1230 /* Set physical address of RX buffer (256-byte aligned). */ 1231 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1232 } 1233 1234 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1235 BUS_DMASYNC_PREWRITE); 1236 1237 return 0; 1238 1239 fail: iwn_free_rx_ring(sc, ring); 1240 return error; 1241 } 1242 1243 static void 1244 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1245 { 1246 int ntries; 1247 1248 if (iwn_nic_lock(sc) == 0) { 1249 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1250 for (ntries = 0; ntries < 1000; ntries++) { 1251 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1252 IWN_FH_RX_STATUS_IDLE) 1253 break; 1254 DELAY(10); 1255 } 1256 iwn_nic_unlock(sc); 1257 } 1258 ring->cur = 0; 1259 sc->last_rx_valid = 0; 1260 } 1261 1262 static void 1263 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1264 { 1265 int i; 1266 1267 iwn_dma_contig_free(&ring->desc_dma); 1268 iwn_dma_contig_free(&ring->stat_dma); 1269 1270 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1271 struct iwn_rx_data *data = &ring->data[i]; 1272 1273 if (data->m != NULL) { 1274 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1275 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1276 bus_dmamap_unload(sc->sc_dmat, data->map); 1277 m_freem(data->m); 1278 } 1279 if (data->map != NULL) 1280 bus_dmamap_destroy(sc->sc_dmat, data->map); 1281 } 1282 } 1283 1284 static int 1285 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1286 { 1287 bus_addr_t paddr; 1288 bus_size_t size; 1289 int i, error; 1290 1291 ring->qid = qid; 1292 ring->queued = 0; 1293 ring->cur = 0; 1294 1295 /* Allocate TX descriptors (256-byte aligned). */ 1296 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1297 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1298 (void **)&ring->desc, size, 256); 1299 if (error != 0) { 1300 aprint_error_dev(sc->sc_dev, 1301 "could not allocate TX ring DMA memory\n"); 1302 goto fail; 1303 } 1304 /* 1305 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1306 * to allocate commands space for other rings. 1307 * XXX Do we really need to allocate descriptors for other rings? 1308 */ 1309 if (qid > 4) 1310 return 0; 1311 1312 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1313 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1314 (void **)&ring->cmd, size, 4); 1315 if (error != 0) { 1316 aprint_error_dev(sc->sc_dev, 1317 "could not allocate TX cmd DMA memory\n"); 1318 goto fail; 1319 } 1320 1321 paddr = ring->cmd_dma.paddr; 1322 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1323 struct iwn_tx_data *data = &ring->data[i]; 1324 1325 data->cmd_paddr = paddr; 1326 data->scratch_paddr = paddr + 12; 1327 paddr += sizeof (struct iwn_tx_cmd); 1328 1329 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1330 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1331 &data->map); 1332 if (error != 0) { 1333 aprint_error_dev(sc->sc_dev, 1334 "could not create TX buf DMA map\n"); 1335 goto fail; 1336 } 1337 } 1338 return 0; 1339 1340 fail: iwn_free_tx_ring(sc, ring); 1341 return error; 1342 } 1343 1344 static void 1345 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1346 { 1347 int i; 1348 1349 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1350 struct iwn_tx_data *data = &ring->data[i]; 1351 1352 if (data->m != NULL) { 1353 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1354 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1355 bus_dmamap_unload(sc->sc_dmat, data->map); 1356 m_freem(data->m); 1357 data->m = NULL; 1358 } 1359 } 1360 /* Clear TX descriptors. */ 1361 memset(ring->desc, 0, ring->desc_dma.size); 1362 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1363 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1364 sc->qfullmsk &= ~(1 << ring->qid); 1365 ring->queued = 0; 1366 ring->cur = 0; 1367 } 1368 1369 static void 1370 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1371 { 1372 int i; 1373 1374 iwn_dma_contig_free(&ring->desc_dma); 1375 iwn_dma_contig_free(&ring->cmd_dma); 1376 1377 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1378 struct iwn_tx_data *data = &ring->data[i]; 1379 1380 if (data->m != NULL) { 1381 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1382 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1383 bus_dmamap_unload(sc->sc_dmat, data->map); 1384 m_freem(data->m); 1385 } 1386 if (data->map != NULL) 1387 bus_dmamap_destroy(sc->sc_dmat, data->map); 1388 } 1389 } 1390 1391 static void 1392 iwn5000_ict_reset(struct iwn_softc *sc) 1393 { 1394 /* Disable interrupts. */ 1395 IWN_WRITE(sc, IWN_INT_MASK, 0); 1396 1397 /* Reset ICT table. */ 1398 memset(sc->ict, 0, IWN_ICT_SIZE); 1399 sc->ict_cur = 0; 1400 1401 /* Set physical address of ICT table (4KB aligned). */ 1402 DPRINTF(("enabling ICT\n")); 1403 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1404 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1405 1406 /* Enable periodic RX interrupt. */ 1407 sc->int_mask |= IWN_INT_RX_PERIODIC; 1408 /* Switch to ICT interrupt mode in driver. */ 1409 sc->sc_flags |= IWN_FLAG_USE_ICT; 1410 1411 /* Re-enable interrupts. */ 1412 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1413 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1414 } 1415 1416 static int 1417 iwn_read_eeprom(struct iwn_softc *sc) 1418 { 1419 struct iwn_ops *ops = &sc->ops; 1420 struct ieee80211com *ic = &sc->sc_ic; 1421 uint16_t val; 1422 int error; 1423 1424 /* Check whether adapter has an EEPROM or an OTPROM. */ 1425 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1426 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1427 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1428 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1429 "OTPROM" : "EEPROM")); 1430 1431 /* Adapter has to be powered on for EEPROM access to work. */ 1432 if ((error = iwn_apm_init(sc)) != 0) { 1433 aprint_error_dev(sc->sc_dev, 1434 "could not power ON adapter\n"); 1435 return error; 1436 } 1437 1438 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1439 aprint_error_dev(sc->sc_dev, 1440 "bad ROM signature\n"); 1441 return EIO; 1442 } 1443 if ((error = iwn_eeprom_lock(sc)) != 0) { 1444 aprint_error_dev(sc->sc_dev, 1445 "could not lock ROM (error=%d)\n", error); 1446 return error; 1447 } 1448 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1449 if ((error = iwn_init_otprom(sc)) != 0) { 1450 aprint_error_dev(sc->sc_dev, 1451 "could not initialize OTPROM\n"); 1452 return error; 1453 } 1454 } 1455 1456 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1457 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1458 /* Check if HT support is bonded out. */ 1459 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1460 sc->sc_flags |= IWN_FLAG_HAS_11N; 1461 1462 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1463 sc->rfcfg = le16toh(val); 1464 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1465 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1466 if (sc->txchainmask == 0) 1467 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1468 if (sc->rxchainmask == 0) 1469 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1470 1471 /* Read MAC address. */ 1472 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1473 1474 /* Read adapter-specific information from EEPROM. */ 1475 ops->read_eeprom(sc); 1476 1477 iwn_apm_stop(sc); /* Power OFF adapter. */ 1478 1479 iwn_eeprom_unlock(sc); 1480 return 0; 1481 } 1482 1483 static void 1484 iwn4965_read_eeprom(struct iwn_softc *sc) 1485 { 1486 uint32_t addr; 1487 uint16_t val; 1488 int i; 1489 1490 /* Read regulatory domain (4 ASCII characters). */ 1491 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1492 1493 /* Read the list of authorized channels (20MHz ones only). */ 1494 for (i = 0; i < 5; i++) { 1495 addr = iwn4965_regulatory_bands[i]; 1496 iwn_read_eeprom_channels(sc, i, addr); 1497 } 1498 1499 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1500 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1501 sc->maxpwr2GHz = val & 0xff; 1502 sc->maxpwr5GHz = val >> 8; 1503 /* Check that EEPROM values are within valid range. */ 1504 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1505 sc->maxpwr5GHz = 38; 1506 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1507 sc->maxpwr2GHz = 38; 1508 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1509 1510 /* Read samples for each TX power group. */ 1511 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1512 sizeof sc->bands); 1513 1514 /* Read voltage at which samples were taken. */ 1515 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1516 sc->eeprom_voltage = (int16_t)le16toh(val); 1517 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1518 1519 #ifdef IWN_DEBUG 1520 /* Print samples. */ 1521 if (iwn_debug > 0) { 1522 for (i = 0; i < IWN_NBANDS; i++) 1523 iwn4965_print_power_group(sc, i); 1524 } 1525 #endif 1526 } 1527 1528 #ifdef IWN_DEBUG 1529 static void 1530 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1531 { 1532 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1533 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1534 int j, c; 1535 1536 aprint_normal("===band %d===\n", i); 1537 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1538 aprint_normal("chan1 num=%d\n", chans[0].num); 1539 for (c = 0; c < 2; c++) { 1540 for (j = 0; j < IWN_NSAMPLES; j++) { 1541 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1542 "power=%d pa_det=%d\n", c, j, 1543 chans[0].samples[c][j].temp, 1544 chans[0].samples[c][j].gain, 1545 chans[0].samples[c][j].power, 1546 chans[0].samples[c][j].pa_det); 1547 } 1548 } 1549 aprint_normal("chan2 num=%d\n", chans[1].num); 1550 for (c = 0; c < 2; c++) { 1551 for (j = 0; j < IWN_NSAMPLES; j++) { 1552 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1553 "power=%d pa_det=%d\n", c, j, 1554 chans[1].samples[c][j].temp, 1555 chans[1].samples[c][j].gain, 1556 chans[1].samples[c][j].power, 1557 chans[1].samples[c][j].pa_det); 1558 } 1559 } 1560 } 1561 #endif 1562 1563 static void 1564 iwn5000_read_eeprom(struct iwn_softc *sc) 1565 { 1566 struct iwn5000_eeprom_calib_hdr hdr; 1567 int32_t volt; 1568 uint32_t base, addr; 1569 uint16_t val; 1570 int i; 1571 1572 /* Read regulatory domain (4 ASCII characters). */ 1573 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1574 base = le16toh(val); 1575 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1576 sc->eeprom_domain, 4); 1577 1578 /* Read the list of authorized channels (20MHz ones only). */ 1579 for (i = 0; i < 5; i++) { 1580 addr = base + iwn5000_regulatory_bands[i]; 1581 iwn_read_eeprom_channels(sc, i, addr); 1582 } 1583 1584 /* Read enhanced TX power information for 6000 Series. */ 1585 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1586 iwn_read_eeprom_enhinfo(sc); 1587 1588 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1589 base = le16toh(val); 1590 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1591 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1592 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1593 sc->calib_ver = hdr.version; 1594 1595 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1596 /* Compute temperature offset. */ 1597 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1598 sc->eeprom_temp = le16toh(val); 1599 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1600 volt = le16toh(val); 1601 sc->temp_off = sc->eeprom_temp - (volt / -5); 1602 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1603 sc->eeprom_temp, volt, sc->temp_off)); 1604 } else { 1605 /* Read crystal calibration. */ 1606 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1607 &sc->eeprom_crystal, sizeof (uint32_t)); 1608 DPRINTF(("crystal calibration 0x%08x\n", 1609 le32toh(sc->eeprom_crystal))); 1610 } 1611 } 1612 1613 static void 1614 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1615 { 1616 struct ieee80211com *ic = &sc->sc_ic; 1617 const struct iwn_chan_band *band = &iwn_bands[n]; 1618 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1619 uint8_t chan; 1620 int i; 1621 1622 iwn_read_prom_data(sc, addr, channels, 1623 band->nchan * sizeof (struct iwn_eeprom_chan)); 1624 1625 for (i = 0; i < band->nchan; i++) { 1626 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1627 continue; 1628 1629 chan = band->chan[i]; 1630 1631 if (n == 0) { /* 2GHz band */ 1632 ic->ic_channels[chan].ic_freq = 1633 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1634 ic->ic_channels[chan].ic_flags = 1635 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1636 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1637 1638 } else { /* 5GHz band */ 1639 /* 1640 * Some adapters support channels 7, 8, 11 and 12 1641 * both in the 2GHz and 4.9GHz bands. 1642 * Because of limitations in our net80211 layer, 1643 * we don't support them in the 4.9GHz band. 1644 */ 1645 if (chan <= 14) 1646 continue; 1647 1648 ic->ic_channels[chan].ic_freq = 1649 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1650 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1651 /* We have at least one valid 5GHz channel. */ 1652 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1653 } 1654 1655 /* Is active scan allowed on this channel? */ 1656 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1657 ic->ic_channels[chan].ic_flags |= 1658 IEEE80211_CHAN_PASSIVE; 1659 } 1660 1661 /* Save maximum allowed TX power for this channel. */ 1662 sc->maxpwr[chan] = channels[i].maxpwr; 1663 1664 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1665 chan, channels[i].flags, sc->maxpwr[chan])); 1666 } 1667 } 1668 1669 static void 1670 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1671 { 1672 struct iwn_eeprom_enhinfo enhinfo[35]; 1673 uint16_t val, base; 1674 int8_t maxpwr; 1675 int i; 1676 1677 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1678 base = le16toh(val); 1679 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1680 enhinfo, sizeof enhinfo); 1681 1682 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1683 for (i = 0; i < __arraycount(enhinfo); i++) { 1684 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1685 continue; /* Skip invalid entries. */ 1686 1687 maxpwr = 0; 1688 if (sc->txchainmask & IWN_ANT_A) 1689 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1690 if (sc->txchainmask & IWN_ANT_B) 1691 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1692 if (sc->txchainmask & IWN_ANT_C) 1693 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1694 if (sc->ntxchains == 2) 1695 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1696 else if (sc->ntxchains == 3) 1697 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1698 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1699 1700 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1701 sc->enh_maxpwr[i] = maxpwr; 1702 } 1703 } 1704 1705 static struct ieee80211_node * 1706 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1707 { 1708 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1709 } 1710 1711 static void 1712 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1713 { 1714 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1715 struct iwn_node *wn = (void *)ni; 1716 uint8_t rate; 1717 int ridx, i; 1718 1719 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1720 /* Start at lowest available bit-rate, AMRR will raise. */ 1721 ni->ni_txrate = 0; 1722 1723 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1724 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1725 /* Map 802.11 rate to HW rate index. */ 1726 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1727 if (iwn_rates[ridx].rate == rate) 1728 break; 1729 wn->ridx[i] = ridx; 1730 } 1731 } 1732 1733 static int 1734 iwn_media_change(struct ifnet *ifp) 1735 { 1736 struct iwn_softc *sc = ifp->if_softc; 1737 struct ieee80211com *ic = &sc->sc_ic; 1738 uint8_t rate, ridx; 1739 int error; 1740 1741 error = ieee80211_media_change(ifp); 1742 if (error != ENETRESET) 1743 return error; 1744 1745 if (ic->ic_fixed_rate != -1) { 1746 rate = ic->ic_sup_rates[ic->ic_curmode]. 1747 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1748 /* Map 802.11 rate to HW rate index. */ 1749 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1750 if (iwn_rates[ridx].rate == rate) 1751 break; 1752 sc->fixed_ridx = ridx; 1753 } 1754 1755 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1756 (IFF_UP | IFF_RUNNING)) { 1757 iwn_stop(ifp, 0); 1758 error = iwn_init(ifp); 1759 } 1760 return error; 1761 } 1762 1763 static int 1764 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1765 { 1766 struct ifnet *ifp = ic->ic_ifp; 1767 struct iwn_softc *sc = ifp->if_softc; 1768 int error; 1769 1770 callout_stop(&sc->calib_to); 1771 1772 switch (nstate) { 1773 case IEEE80211_S_SCAN: 1774 /* XXX Do not abort a running scan. */ 1775 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1776 if (ic->ic_state != nstate) 1777 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1778 "while scanning(%d) ignored\n", nstate, 1779 ic->ic_state); 1780 break; 1781 } 1782 1783 /* XXX Not sure if call and flags are needed. */ 1784 ieee80211_node_table_reset(&ic->ic_scan); 1785 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1786 sc->sc_flags |= IWN_FLAG_SCANNING_2GHZ; 1787 1788 /* Make the link LED blink while we're scanning. */ 1789 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1790 1791 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1792 aprint_error_dev(sc->sc_dev, 1793 "could not initiate scan\n"); 1794 return error; 1795 } 1796 ic->ic_state = nstate; 1797 return 0; 1798 1799 case IEEE80211_S_ASSOC: 1800 if (ic->ic_state != IEEE80211_S_RUN) 1801 break; 1802 /* FALLTHROUGH */ 1803 case IEEE80211_S_AUTH: 1804 /* Reset state to handle reassociations correctly. */ 1805 sc->rxon.associd = 0; 1806 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1807 sc->calib.state = IWN_CALIB_STATE_INIT; 1808 1809 if ((error = iwn_auth(sc)) != 0) { 1810 aprint_error_dev(sc->sc_dev, 1811 "could not move to auth state\n"); 1812 return error; 1813 } 1814 break; 1815 1816 case IEEE80211_S_RUN: 1817 if ((error = iwn_run(sc)) != 0) { 1818 aprint_error_dev(sc->sc_dev, 1819 "could not move to run state\n"); 1820 return error; 1821 } 1822 break; 1823 1824 case IEEE80211_S_INIT: 1825 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1826 sc->calib.state = IWN_CALIB_STATE_INIT; 1827 break; 1828 } 1829 1830 return sc->sc_newstate(ic, nstate, arg); 1831 } 1832 1833 static void 1834 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1835 { 1836 struct iwn_softc *sc = arg; 1837 struct iwn_node *wn = (struct iwn_node *)ni; 1838 1839 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1840 } 1841 1842 static void 1843 iwn_calib_timeout(void *arg) 1844 { 1845 struct iwn_softc *sc = arg; 1846 struct ieee80211com *ic = &sc->sc_ic; 1847 int s; 1848 1849 s = splnet(); 1850 if (ic->ic_fixed_rate == -1) { 1851 if (ic->ic_opmode == IEEE80211_M_STA) 1852 iwn_iter_func(sc, ic->ic_bss); 1853 else 1854 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1855 } 1856 /* Force automatic TX power calibration every 60 secs. */ 1857 if (++sc->calib_cnt >= 120) { 1858 uint32_t flags = 0; 1859 1860 DPRINTF(("sending request for statistics\n")); 1861 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1862 sizeof flags, 1); 1863 sc->calib_cnt = 0; 1864 } 1865 splx(s); 1866 1867 /* Automatic rate control triggered every 500ms. */ 1868 callout_schedule(&sc->calib_to, hz/2); 1869 } 1870 1871 /* 1872 * Process an RX_PHY firmware notification. This is usually immediately 1873 * followed by an MPDU_RX_DONE notification. 1874 */ 1875 static void 1876 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1877 struct iwn_rx_data *data) 1878 { 1879 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1880 1881 DPRINTFN(2, ("received PHY stats\n")); 1882 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1883 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1884 1885 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1886 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1887 sc->last_rx_valid = 1; 1888 } 1889 1890 /* 1891 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1892 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1893 */ 1894 static void 1895 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1896 struct iwn_rx_data *data) 1897 { 1898 struct iwn_ops *ops = &sc->ops; 1899 struct ieee80211com *ic = &sc->sc_ic; 1900 struct ifnet *ifp = ic->ic_ifp; 1901 struct iwn_rx_ring *ring = &sc->rxq; 1902 struct ieee80211_frame *wh; 1903 struct ieee80211_node *ni; 1904 struct mbuf *m, *m1; 1905 struct iwn_rx_stat *stat; 1906 char *head; 1907 uint32_t flags; 1908 int error, len, rssi; 1909 1910 if (desc->type == IWN_MPDU_RX_DONE) { 1911 /* Check for prior RX_PHY notification. */ 1912 if (!sc->last_rx_valid) { 1913 DPRINTF(("missing RX_PHY\n")); 1914 return; 1915 } 1916 sc->last_rx_valid = 0; 1917 stat = &sc->last_rx_stat; 1918 } else 1919 stat = (struct iwn_rx_stat *)(desc + 1); 1920 1921 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1922 BUS_DMASYNC_POSTREAD); 1923 1924 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1925 aprint_error_dev(sc->sc_dev, 1926 "invalid RX statistic header\n"); 1927 return; 1928 } 1929 if (desc->type == IWN_MPDU_RX_DONE) { 1930 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1931 head = (char *)(mpdu + 1); 1932 len = le16toh(mpdu->len); 1933 } else { 1934 head = (char *)(stat + 1) + stat->cfg_phy_len; 1935 len = le16toh(stat->len); 1936 } 1937 1938 flags = le32toh(*(uint32_t *)(head + len)); 1939 1940 /* Discard frames with a bad FCS early. */ 1941 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 1942 DPRINTFN(2, ("RX flags error %x\n", flags)); 1943 ifp->if_ierrors++; 1944 return; 1945 } 1946 /* Discard frames that are too short. */ 1947 if (len < sizeof (*wh)) { 1948 DPRINTF(("frame too short: %d\n", len)); 1949 ic->ic_stats.is_rx_tooshort++; 1950 ifp->if_ierrors++; 1951 return; 1952 } 1953 1954 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1955 if (m1 == NULL) { 1956 ic->ic_stats.is_rx_nobuf++; 1957 ifp->if_ierrors++; 1958 return; 1959 } 1960 bus_dmamap_unload(sc->sc_dmat, data->map); 1961 1962 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 1963 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1964 if (error != 0) { 1965 m_freem(m1); 1966 1967 /* Try to reload the old mbuf. */ 1968 error = bus_dmamap_load(sc->sc_dmat, data->map, 1969 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1970 BUS_DMA_NOWAIT | BUS_DMA_READ); 1971 if (error != 0) { 1972 panic("%s: could not load old RX mbuf", 1973 device_xname(sc->sc_dev)); 1974 } 1975 /* Physical address may have changed. */ 1976 ring->desc[ring->cur] = 1977 htole32(data->map->dm_segs[0].ds_addr >> 8); 1978 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1979 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1980 BUS_DMASYNC_PREWRITE); 1981 ifp->if_ierrors++; 1982 return; 1983 } 1984 1985 m = data->m; 1986 data->m = m1; 1987 /* Update RX descriptor. */ 1988 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1989 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1990 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 1991 BUS_DMASYNC_PREWRITE); 1992 1993 /* Finalize mbuf. */ 1994 m->m_pkthdr.rcvif = ifp; 1995 m->m_data = head; 1996 m->m_pkthdr.len = m->m_len = len; 1997 1998 /* Grab a reference to the source node. */ 1999 wh = mtod(m, struct ieee80211_frame *); 2000 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2001 2002 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2003 /* NetBSD does decryption in ieee80211_input. */ 2004 2005 rssi = ops->get_rssi(stat); 2006 2007 /* XXX Added for NetBSD: scans never stop without it */ 2008 if (ic->ic_state == IEEE80211_S_SCAN) 2009 iwn_fix_channel(ic, m, stat); 2010 2011 if (sc->sc_drvbpf != NULL) { 2012 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2013 2014 tap->wr_flags = 0; 2015 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2016 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2017 tap->wr_chan_freq = 2018 htole16(ic->ic_channels[stat->chan].ic_freq); 2019 tap->wr_chan_flags = 2020 htole16(ic->ic_channels[stat->chan].ic_flags); 2021 tap->wr_dbm_antsignal = (int8_t)rssi; 2022 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2023 tap->wr_tsft = stat->tstamp; 2024 switch (stat->rate) { 2025 /* CCK rates. */ 2026 case 10: tap->wr_rate = 2; break; 2027 case 20: tap->wr_rate = 4; break; 2028 case 55: tap->wr_rate = 11; break; 2029 case 110: tap->wr_rate = 22; break; 2030 /* OFDM rates. */ 2031 case 0xd: tap->wr_rate = 12; break; 2032 case 0xf: tap->wr_rate = 18; break; 2033 case 0x5: tap->wr_rate = 24; break; 2034 case 0x7: tap->wr_rate = 36; break; 2035 case 0x9: tap->wr_rate = 48; break; 2036 case 0xb: tap->wr_rate = 72; break; 2037 case 0x1: tap->wr_rate = 96; break; 2038 case 0x3: tap->wr_rate = 108; break; 2039 /* Unknown rate: should not happen. */ 2040 default: tap->wr_rate = 0; 2041 } 2042 2043 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2044 } 2045 2046 /* Send the frame to the 802.11 layer. */ 2047 ieee80211_input(ic, m, ni, rssi, 0); 2048 2049 /* Node is no longer needed. */ 2050 ieee80211_free_node(ni); 2051 } 2052 2053 #ifndef IEEE80211_NO_HT 2054 /* Process an incoming Compressed BlockAck. */ 2055 static void 2056 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2057 struct iwn_rx_data *data) 2058 { 2059 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2060 struct iwn_tx_ring *txq; 2061 2062 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2063 BUS_DMASYNC_POSTREAD); 2064 2065 txq = &sc->txq[le16toh(ba->qid)]; 2066 /* XXX TBD */ 2067 } 2068 #endif 2069 2070 /* 2071 * Process a CALIBRATION_RESULT notification sent by the initialization 2072 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2073 */ 2074 static void 2075 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2076 struct iwn_rx_data *data) 2077 { 2078 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2079 int len, idx = -1; 2080 2081 /* Runtime firmware should not send such a notification. */ 2082 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2083 return; 2084 2085 len = (le32toh(desc->len) & 0x3fff) - 4; 2086 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2087 BUS_DMASYNC_POSTREAD); 2088 2089 switch (calib->code) { 2090 case IWN5000_PHY_CALIB_DC: 2091 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 2092 idx = 0; 2093 break; 2094 case IWN5000_PHY_CALIB_LO: 2095 idx = 1; 2096 break; 2097 case IWN5000_PHY_CALIB_TX_IQ: 2098 idx = 2; 2099 break; 2100 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2101 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2102 sc->hw_type != IWN_HW_REV_TYPE_5150) 2103 idx = 3; 2104 break; 2105 case IWN5000_PHY_CALIB_BASE_BAND: 2106 idx = 4; 2107 break; 2108 } 2109 if (idx == -1) /* Ignore other results. */ 2110 return; 2111 2112 /* Save calibration result. */ 2113 if (sc->calibcmd[idx].buf != NULL) 2114 free(sc->calibcmd[idx].buf, M_DEVBUF); 2115 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2116 if (sc->calibcmd[idx].buf == NULL) { 2117 DPRINTF(("not enough memory for calibration result %d\n", 2118 calib->code)); 2119 return; 2120 } 2121 DPRINTF(("saving calibration result code=%d len=%d\n", 2122 calib->code, len)); 2123 sc->calibcmd[idx].len = len; 2124 memcpy(sc->calibcmd[idx].buf, calib, len); 2125 } 2126 2127 /* 2128 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2129 * The latter is sent by the firmware after each received beacon. 2130 */ 2131 static void 2132 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2133 struct iwn_rx_data *data) 2134 { 2135 struct iwn_ops *ops = &sc->ops; 2136 struct ieee80211com *ic = &sc->sc_ic; 2137 struct iwn_calib_state *calib = &sc->calib; 2138 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2139 int temp; 2140 2141 /* Ignore statistics received during a scan. */ 2142 if (ic->ic_state != IEEE80211_S_RUN) 2143 return; 2144 2145 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2146 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2147 2148 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2149 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2150 2151 /* Test if temperature has changed. */ 2152 if (stats->general.temp != sc->rawtemp) { 2153 /* Convert "raw" temperature to degC. */ 2154 sc->rawtemp = stats->general.temp; 2155 temp = ops->get_temperature(sc); 2156 DPRINTFN(2, ("temperature=%dC\n", temp)); 2157 2158 /* Update TX power if need be (4965AGN only). */ 2159 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2160 iwn4965_power_calibration(sc, temp); 2161 } 2162 2163 if (desc->type != IWN_BEACON_STATISTICS) 2164 return; /* Reply to a statistics request. */ 2165 2166 sc->noise = iwn_get_noise(&stats->rx.general); 2167 2168 /* Test that RSSI and noise are present in stats report. */ 2169 if (le32toh(stats->rx.general.flags) != 1) { 2170 DPRINTF(("received statistics without RSSI\n")); 2171 return; 2172 } 2173 2174 /* 2175 * XXX Differential gain calibration makes the 6005 firmware 2176 * crap out, so skip it for now. This effectively disables 2177 * sensitivity tuning as well. 2178 */ 2179 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2180 return; 2181 2182 if (calib->state == IWN_CALIB_STATE_ASSOC) 2183 iwn_collect_noise(sc, &stats->rx.general); 2184 else if (calib->state == IWN_CALIB_STATE_RUN) 2185 iwn_tune_sensitivity(sc, &stats->rx); 2186 } 2187 2188 /* 2189 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2190 * and 5000 adapters have different incompatible TX status formats. 2191 */ 2192 static void 2193 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2194 struct iwn_rx_data *data) 2195 { 2196 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2197 2198 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2199 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2200 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2201 } 2202 2203 static void 2204 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2205 struct iwn_rx_data *data) 2206 { 2207 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2208 2209 #ifdef notyet 2210 /* Reset TX scheduler slot. */ 2211 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2212 #endif 2213 2214 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2215 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2216 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2217 } 2218 2219 /* 2220 * Adapter-independent backend for TX_DONE firmware notifications. 2221 */ 2222 static void 2223 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2224 uint8_t status) 2225 { 2226 struct ieee80211com *ic = &sc->sc_ic; 2227 struct ifnet *ifp = ic->ic_ifp; 2228 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2229 struct iwn_tx_data *data = &ring->data[desc->idx]; 2230 struct iwn_node *wn = (struct iwn_node *)data->ni; 2231 2232 /* Update rate control statistics. */ 2233 wn->amn.amn_txcnt++; 2234 if (ackfailcnt > 0) 2235 wn->amn.amn_retrycnt++; 2236 2237 if (status != 1 && status != 2) 2238 ifp->if_oerrors++; 2239 else 2240 ifp->if_opackets++; 2241 2242 /* Unmap and free mbuf. */ 2243 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2244 BUS_DMASYNC_POSTWRITE); 2245 bus_dmamap_unload(sc->sc_dmat, data->map); 2246 m_freem(data->m); 2247 data->m = NULL; 2248 ieee80211_free_node(data->ni); 2249 data->ni = NULL; 2250 2251 sc->sc_tx_timer = 0; 2252 if (--ring->queued < IWN_TX_RING_LOMARK) { 2253 sc->qfullmsk &= ~(1 << ring->qid); 2254 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2255 ifp->if_flags &= ~IFF_OACTIVE; 2256 (*ifp->if_start)(ifp); 2257 } 2258 } 2259 } 2260 2261 /* 2262 * Process a "command done" firmware notification. This is where we wakeup 2263 * processes waiting for a synchronous command completion. 2264 */ 2265 static void 2266 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2267 { 2268 struct iwn_tx_ring *ring = &sc->txq[4]; 2269 struct iwn_tx_data *data; 2270 2271 if ((desc->qid & 0xf) != 4) 2272 return; /* Not a command ack. */ 2273 2274 data = &ring->data[desc->idx]; 2275 2276 /* If the command was mapped in an mbuf, free it. */ 2277 if (data->m != NULL) { 2278 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2279 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2280 bus_dmamap_unload(sc->sc_dmat, data->map); 2281 m_freem(data->m); 2282 data->m = NULL; 2283 } 2284 wakeup(&ring->desc[desc->idx]); 2285 } 2286 2287 /* 2288 * Process an INT_FH_RX or INT_SW_RX interrupt. 2289 */ 2290 static void 2291 iwn_notif_intr(struct iwn_softc *sc) 2292 { 2293 struct iwn_ops *ops = &sc->ops; 2294 struct ieee80211com *ic = &sc->sc_ic; 2295 struct ifnet *ifp = ic->ic_ifp; 2296 uint16_t hw; 2297 2298 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2299 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2300 2301 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2302 while (sc->rxq.cur != hw) { 2303 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2304 struct iwn_rx_desc *desc; 2305 2306 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2307 BUS_DMASYNC_POSTREAD); 2308 desc = mtod(data->m, struct iwn_rx_desc *); 2309 2310 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2311 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2312 2313 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2314 iwn_cmd_done(sc, desc); 2315 2316 switch (desc->type) { 2317 case IWN_RX_PHY: 2318 iwn_rx_phy(sc, desc, data); 2319 break; 2320 2321 case IWN_RX_DONE: /* 4965AGN only. */ 2322 case IWN_MPDU_RX_DONE: 2323 /* An 802.11 frame has been received. */ 2324 iwn_rx_done(sc, desc, data); 2325 break; 2326 #ifndef IEEE80211_NO_HT 2327 case IWN_RX_COMPRESSED_BA: 2328 /* A Compressed BlockAck has been received. */ 2329 iwn_rx_compressed_ba(sc, desc, data); 2330 break; 2331 #endif 2332 case IWN_TX_DONE: 2333 /* An 802.11 frame has been transmitted. */ 2334 ops->tx_done(sc, desc, data); 2335 break; 2336 2337 case IWN_RX_STATISTICS: 2338 case IWN_BEACON_STATISTICS: 2339 iwn_rx_statistics(sc, desc, data); 2340 break; 2341 2342 case IWN_BEACON_MISSED: 2343 { 2344 struct iwn_beacon_missed *miss = 2345 (struct iwn_beacon_missed *)(desc + 1); 2346 2347 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2348 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2349 /* 2350 * If more than 5 consecutive beacons are missed, 2351 * reinitialize the sensitivity state machine. 2352 */ 2353 DPRINTF(("beacons missed %d/%d\n", 2354 le32toh(miss->consecutive), le32toh(miss->total))); 2355 if (ic->ic_state == IEEE80211_S_RUN && 2356 le32toh(miss->consecutive) > 5) 2357 (void)iwn_init_sensitivity(sc); 2358 break; 2359 } 2360 case IWN_UC_READY: 2361 { 2362 struct iwn_ucode_info *uc = 2363 (struct iwn_ucode_info *)(desc + 1); 2364 2365 /* The microcontroller is ready. */ 2366 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2367 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2368 DPRINTF(("microcode alive notification version=%d.%d " 2369 "subtype=%x alive=%x\n", uc->major, uc->minor, 2370 uc->subtype, le32toh(uc->valid))); 2371 2372 if (le32toh(uc->valid) != 1) { 2373 aprint_error_dev(sc->sc_dev, 2374 "microcontroller initialization " 2375 "failed\n"); 2376 break; 2377 } 2378 if (uc->subtype == IWN_UCODE_INIT) { 2379 /* Save microcontroller report. */ 2380 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2381 } 2382 /* Save the address of the error log in SRAM. */ 2383 sc->errptr = le32toh(uc->errptr); 2384 break; 2385 } 2386 case IWN_STATE_CHANGED: 2387 { 2388 uint32_t *status = (uint32_t *)(desc + 1); 2389 2390 /* Enabled/disabled notification. */ 2391 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2392 sizeof (*status), BUS_DMASYNC_POSTREAD); 2393 DPRINTF(("state changed to %x\n", le32toh(*status))); 2394 2395 if (le32toh(*status) & 1) { 2396 /* The radio button has to be pushed. */ 2397 aprint_error_dev(sc->sc_dev, 2398 "Radio transmitter is off\n"); 2399 /* Turn the interface down. */ 2400 ifp->if_flags &= ~IFF_UP; 2401 iwn_stop(ifp, 1); 2402 return; /* No further processing. */ 2403 } 2404 break; 2405 } 2406 case IWN_START_SCAN: 2407 { 2408 struct iwn_start_scan *scan = 2409 (struct iwn_start_scan *)(desc + 1); 2410 2411 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2412 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2413 DPRINTFN(2, ("scanning channel %d status %x\n", 2414 scan->chan, le32toh(scan->status))); 2415 2416 /* Fix current channel. */ 2417 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2418 break; 2419 } 2420 case IWN_STOP_SCAN: 2421 { 2422 struct iwn_stop_scan *scan = 2423 (struct iwn_stop_scan *)(desc + 1); 2424 2425 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2426 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2427 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2428 scan->nchan, scan->status, scan->chan)); 2429 2430 if (scan->status == 1 && scan->chan <= 14 && 2431 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2432 /* 2433 * We just finished scanning 2GHz channels, 2434 * start scanning 5GHz ones. 2435 */ 2436 sc->sc_flags &= ~IWN_FLAG_SCANNING_2GHZ; 2437 sc->sc_flags |= IWN_FLAG_SCANNING_5GHZ; 2438 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2439 break; 2440 } 2441 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2442 ieee80211_end_scan(ic); 2443 break; 2444 } 2445 case IWN5000_CALIBRATION_RESULT: 2446 iwn5000_rx_calib_results(sc, desc, data); 2447 break; 2448 2449 case IWN5000_CALIBRATION_DONE: 2450 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2451 wakeup(sc); 2452 break; 2453 } 2454 2455 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2456 } 2457 2458 /* Tell the firmware what we have processed. */ 2459 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2460 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2461 } 2462 2463 /* 2464 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2465 * from power-down sleep mode. 2466 */ 2467 static void 2468 iwn_wakeup_intr(struct iwn_softc *sc) 2469 { 2470 int qid; 2471 2472 DPRINTF(("ucode wakeup from power-down sleep\n")); 2473 2474 /* Wakeup RX and TX rings. */ 2475 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2476 for (qid = 0; qid < sc->ntxqs; qid++) { 2477 struct iwn_tx_ring *ring = &sc->txq[qid]; 2478 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2479 } 2480 } 2481 2482 /* 2483 * Dump the error log of the firmware when a firmware panic occurs. Although 2484 * we can't debug the firmware because it is neither open source nor free, it 2485 * can help us to identify certain classes of problems. 2486 */ 2487 static void 2488 iwn_fatal_intr(struct iwn_softc *sc) 2489 { 2490 struct iwn_fw_dump dump; 2491 int i; 2492 2493 /* Force a complete recalibration on next init. */ 2494 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2495 2496 /* Check that the error log address is valid. */ 2497 if (sc->errptr < IWN_FW_DATA_BASE || 2498 sc->errptr + sizeof (dump) > 2499 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2500 aprint_error_dev(sc->sc_dev, 2501 "bad firmware error log address 0x%08x\n", sc->errptr); 2502 return; 2503 } 2504 if (iwn_nic_lock(sc) != 0) { 2505 aprint_error_dev(sc->sc_dev, 2506 "could not read firmware error log\n"); 2507 return; 2508 } 2509 /* Read firmware error log from SRAM. */ 2510 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2511 sizeof (dump) / sizeof (uint32_t)); 2512 iwn_nic_unlock(sc); 2513 2514 if (dump.valid == 0) { 2515 aprint_error_dev(sc->sc_dev, 2516 "firmware error log is empty\n"); 2517 return; 2518 } 2519 aprint_error("firmware error log:\n"); 2520 aprint_error(" error type = \"%s\" (0x%08X)\n", 2521 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2522 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2523 dump.id); 2524 aprint_error(" program counter = 0x%08X\n", dump.pc); 2525 aprint_error(" source line = 0x%08X\n", dump.src_line); 2526 aprint_error(" error data = 0x%08X%08X\n", 2527 dump.error_data[0], dump.error_data[1]); 2528 aprint_error(" branch link = 0x%08X%08X\n", 2529 dump.branch_link[0], dump.branch_link[1]); 2530 aprint_error(" interrupt link = 0x%08X%08X\n", 2531 dump.interrupt_link[0], dump.interrupt_link[1]); 2532 aprint_error(" time = %u\n", dump.time[0]); 2533 2534 /* Dump driver status (TX and RX rings) while we're here. */ 2535 aprint_error("driver status:\n"); 2536 for (i = 0; i < sc->ntxqs; i++) { 2537 struct iwn_tx_ring *ring = &sc->txq[i]; 2538 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2539 i, ring->qid, ring->cur, ring->queued); 2540 } 2541 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2542 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2543 } 2544 2545 static int 2546 iwn_intr(void *arg) 2547 { 2548 struct iwn_softc *sc = arg; 2549 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2550 uint32_t r1, r2, tmp; 2551 2552 /* Disable interrupts. */ 2553 IWN_WRITE(sc, IWN_INT_MASK, 0); 2554 2555 /* Read interrupts from ICT (fast) or from registers (slow). */ 2556 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2557 tmp = 0; 2558 while (sc->ict[sc->ict_cur] != 0) { 2559 tmp |= sc->ict[sc->ict_cur]; 2560 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2561 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2562 } 2563 tmp = le32toh(tmp); 2564 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2565 tmp = 0; 2566 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2567 tmp |= 0x8000; 2568 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2569 r2 = 0; /* Unused. */ 2570 } else { 2571 r1 = IWN_READ(sc, IWN_INT); 2572 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2573 return 0; /* Hardware gone! */ 2574 r2 = IWN_READ(sc, IWN_FH_INT); 2575 } 2576 if (r1 == 0 && r2 == 0) { 2577 if (ifp->if_flags & IFF_UP) 2578 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2579 return 0; /* Interrupt not for us. */ 2580 } 2581 2582 /* Acknowledge interrupts. */ 2583 IWN_WRITE(sc, IWN_INT, r1); 2584 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2585 IWN_WRITE(sc, IWN_FH_INT, r2); 2586 2587 if (r1 & IWN_INT_RF_TOGGLED) { 2588 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2589 aprint_error_dev(sc->sc_dev, 2590 "RF switch: radio %s\n", 2591 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2592 } 2593 if (r1 & IWN_INT_CT_REACHED) { 2594 aprint_error_dev(sc->sc_dev, 2595 "critical temperature reached!\n"); 2596 } 2597 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2598 aprint_error_dev(sc->sc_dev, 2599 "fatal firmware error\n"); 2600 /* Dump firmware error log and stop. */ 2601 iwn_fatal_intr(sc); 2602 ifp->if_flags &= ~IFF_UP; 2603 iwn_stop(ifp, 1); 2604 return 1; 2605 } 2606 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2607 (r2 & IWN_FH_INT_RX)) { 2608 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2609 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2610 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2611 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2612 IWN_INT_PERIODIC_DIS); 2613 iwn_notif_intr(sc); 2614 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2615 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2616 IWN_INT_PERIODIC_ENA); 2617 } 2618 } else 2619 iwn_notif_intr(sc); 2620 } 2621 2622 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2623 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2624 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2625 wakeup(sc); /* FH DMA transfer completed. */ 2626 } 2627 2628 if (r1 & IWN_INT_ALIVE) 2629 wakeup(sc); /* Firmware is alive. */ 2630 2631 if (r1 & IWN_INT_WAKEUP) 2632 iwn_wakeup_intr(sc); 2633 2634 /* Re-enable interrupts. */ 2635 if (ifp->if_flags & IFF_UP) 2636 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2637 2638 return 1; 2639 } 2640 2641 /* 2642 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2643 * 5000 adapters use a slightly different format). 2644 */ 2645 static void 2646 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2647 uint16_t len) 2648 { 2649 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2650 2651 *w = htole16(len + 8); 2652 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2653 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2654 sizeof (uint16_t), 2655 BUS_DMASYNC_PREWRITE); 2656 if (idx < IWN_SCHED_WINSZ) { 2657 *(w + IWN_TX_RING_COUNT) = *w; 2658 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2659 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2660 (char *)(void *)sc->sched_dma.vaddr, 2661 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2662 } 2663 } 2664 2665 static void 2666 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2667 uint16_t len) 2668 { 2669 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2670 2671 *w = htole16(id << 12 | (len + 8)); 2672 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2673 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2674 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2675 if (idx < IWN_SCHED_WINSZ) { 2676 *(w + IWN_TX_RING_COUNT) = *w; 2677 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2678 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2679 (char *)(void *)sc->sched_dma.vaddr, 2680 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2681 } 2682 } 2683 2684 #ifdef notyet 2685 static void 2686 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2687 { 2688 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2689 2690 *w = (*w & htole16(0xf000)) | htole16(1); 2691 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2692 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2693 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2694 if (idx < IWN_SCHED_WINSZ) { 2695 *(w + IWN_TX_RING_COUNT) = *w; 2696 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2697 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2698 (char *)(void *)sc->sched_dma.vaddr, 2699 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2700 } 2701 } 2702 #endif 2703 2704 static int 2705 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2706 { 2707 struct ieee80211com *ic = &sc->sc_ic; 2708 struct iwn_node *wn = (void *)ni; 2709 struct iwn_tx_ring *ring; 2710 struct iwn_tx_desc *desc; 2711 struct iwn_tx_data *data; 2712 struct iwn_tx_cmd *cmd; 2713 struct iwn_cmd_data *tx; 2714 const struct iwn_rate *rinfo; 2715 struct ieee80211_frame *wh; 2716 struct ieee80211_key *k = NULL; 2717 struct mbuf *m1; 2718 uint32_t flags; 2719 u_int hdrlen; 2720 bus_dma_segment_t *seg; 2721 uint8_t tid, ridx, txant, type; 2722 int i, totlen, error, pad; 2723 2724 const struct chanAccParams *cap; 2725 int noack; 2726 int hdrlen2; 2727 2728 wh = mtod(m, struct ieee80211_frame *); 2729 hdrlen = ieee80211_anyhdrsize(wh); 2730 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2731 2732 hdrlen2 = (IEEE80211_QOS_HAS_SEQ(wh)) ? 2733 sizeof (struct ieee80211_qosframe) : 2734 sizeof (struct ieee80211_frame); 2735 2736 if (hdrlen != hdrlen2) 2737 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2738 hdrlen, hdrlen2); 2739 2740 /* XXX OpenBSD sets a different tid when using QOS */ 2741 tid = 0; 2742 if (IEEE80211_QOS_HAS_SEQ(wh)) { 2743 cap = &ic->ic_wme.wme_chanParams; 2744 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2745 } 2746 else 2747 noack = 0; 2748 2749 ring = &sc->txq[ac]; 2750 desc = &ring->desc[ring->cur]; 2751 data = &ring->data[ring->cur]; 2752 2753 /* Choose a TX rate index. */ 2754 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2755 type != IEEE80211_FC0_TYPE_DATA) { 2756 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2757 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2758 } else if (ic->ic_fixed_rate != -1) { 2759 ridx = sc->fixed_ridx; 2760 } else 2761 ridx = wn->ridx[ni->ni_txrate]; 2762 rinfo = &iwn_rates[ridx]; 2763 2764 /* Encrypt the frame if need be. */ 2765 /* 2766 * XXX For now, NetBSD swaps the encryption and bpf sections 2767 * in order to match old code and other drivers. Tests with 2768 * tcpdump indicates that the order is irrelevant, however, 2769 * as bpf produces unencrypted data for both ordering choices. 2770 */ 2771 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2772 k = ieee80211_crypto_encap(ic, ni, m); 2773 if (k == NULL) { 2774 m_freem(m); 2775 return ENOBUFS; 2776 } 2777 /* Packet header may have moved, reset our local pointer. */ 2778 wh = mtod(m, struct ieee80211_frame *); 2779 } 2780 totlen = m->m_pkthdr.len; 2781 2782 if (sc->sc_drvbpf != NULL) { 2783 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2784 2785 tap->wt_flags = 0; 2786 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2787 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2788 tap->wt_rate = rinfo->rate; 2789 tap->wt_hwqueue = ac; 2790 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2791 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2792 2793 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2794 } 2795 2796 /* Prepare TX firmware command. */ 2797 cmd = &ring->cmd[ring->cur]; 2798 cmd->code = IWN_CMD_TX_DATA; 2799 cmd->flags = 0; 2800 cmd->qid = ring->qid; 2801 cmd->idx = ring->cur; 2802 2803 tx = (struct iwn_cmd_data *)cmd->data; 2804 /* NB: No need to clear tx, all fields are reinitialized here. */ 2805 tx->scratch = 0; /* clear "scratch" area */ 2806 2807 flags = 0; 2808 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2809 /* Unicast frame, check if an ACK is expected. */ 2810 if (!noack) 2811 flags |= IWN_TX_NEED_ACK; 2812 } 2813 2814 #ifdef notyet 2815 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2816 if ((wh->i_fc[0] & 2817 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2818 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2819 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2820 #endif 2821 2822 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2823 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2824 2825 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2826 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2827 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2828 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2829 flags |= IWN_TX_NEED_RTS; 2830 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2831 ridx >= IWN_RIDX_OFDM6) { 2832 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2833 flags |= IWN_TX_NEED_CTS; 2834 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2835 flags |= IWN_TX_NEED_RTS; 2836 } 2837 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2838 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2839 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2840 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2841 flags |= IWN_TX_NEED_PROTECTION; 2842 } else 2843 flags |= IWN_TX_FULL_TXOP; 2844 } 2845 } 2846 2847 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2848 type != IEEE80211_FC0_TYPE_DATA) 2849 tx->id = sc->broadcast_id; 2850 else 2851 tx->id = wn->id; 2852 2853 if (type == IEEE80211_FC0_TYPE_MGT) { 2854 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2855 2856 #ifndef IEEE80211_STA_ONLY 2857 /* Tell HW to set timestamp in probe responses. */ 2858 /* XXX NetBSD rev 1.11 added probe requests here but */ 2859 /* probe requests do not take timestamps (from Bergamini). */ 2860 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2861 flags |= IWN_TX_INSERT_TSTAMP; 2862 #endif 2863 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2864 /* changes here. These are not needed (from Bergamini). */ 2865 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2866 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2867 tx->timeout = htole16(3); 2868 else 2869 tx->timeout = htole16(2); 2870 } else 2871 tx->timeout = htole16(0); 2872 2873 if (hdrlen & 3) { 2874 /* First segment length must be a multiple of 4. */ 2875 flags |= IWN_TX_NEED_PADDING; 2876 pad = 4 - (hdrlen & 3); 2877 } else 2878 pad = 0; 2879 2880 tx->len = htole16(totlen); 2881 tx->tid = tid; 2882 tx->rts_ntries = 60; 2883 tx->data_ntries = 15; 2884 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2885 tx->plcp = rinfo->plcp; 2886 tx->rflags = rinfo->flags; 2887 if (tx->id == sc->broadcast_id) { 2888 /* Group or management frame. */ 2889 tx->linkq = 0; 2890 /* XXX Alternate between antenna A and B? */ 2891 txant = IWN_LSB(sc->txchainmask); 2892 tx->rflags |= IWN_RFLAG_ANT(txant); 2893 } else { 2894 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2895 flags |= IWN_TX_LINKQ; /* enable MRR */ 2896 } 2897 /* Set physical address of "scratch area". */ 2898 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2899 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2900 2901 /* Copy 802.11 header in TX command. */ 2902 /* XXX NetBSD changed this in rev 1.20 */ 2903 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2904 2905 /* Trim 802.11 header. */ 2906 m_adj(m, hdrlen); 2907 tx->security = 0; 2908 tx->flags = htole32(flags); 2909 2910 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2911 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2912 if (error != 0) { 2913 if (error != EFBIG) { 2914 aprint_error_dev(sc->sc_dev, 2915 "can't map mbuf (error %d)\n", error); 2916 m_freem(m); 2917 return error; 2918 } 2919 /* Too many DMA segments, linearize mbuf. */ 2920 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2921 if (m1 == NULL) { 2922 m_freem(m); 2923 return ENOBUFS; 2924 } 2925 if (m->m_pkthdr.len > MHLEN) { 2926 MCLGET(m1, M_DONTWAIT); 2927 if (!(m1->m_flags & M_EXT)) { 2928 m_freem(m); 2929 m_freem(m1); 2930 return ENOBUFS; 2931 } 2932 } 2933 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2934 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2935 m_freem(m); 2936 m = m1; 2937 2938 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2939 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2940 if (error != 0) { 2941 aprint_error_dev(sc->sc_dev, 2942 "can't map mbuf (error %d)\n", error); 2943 m_freem(m); 2944 return error; 2945 } 2946 } 2947 2948 data->m = m; 2949 data->ni = ni; 2950 2951 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 2952 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 2953 2954 /* Fill TX descriptor. */ 2955 desc->nsegs = 1 + data->map->dm_nsegs; 2956 /* First DMA segment is used by the TX command. */ 2957 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 2958 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 2959 (4 + sizeof (*tx) + hdrlen + pad) << 4); 2960 /* Other DMA segments are for data payload. */ 2961 seg = data->map->dm_segs; 2962 for (i = 1; i <= data->map->dm_nsegs; i++) { 2963 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 2964 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 2965 seg->ds_len << 4); 2966 seg++; 2967 } 2968 2969 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2970 BUS_DMASYNC_PREWRITE); 2971 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 2972 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 2973 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 2974 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2975 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 2976 sizeof (*desc), BUS_DMASYNC_PREWRITE); 2977 2978 #ifdef notyet 2979 /* Update TX scheduler. */ 2980 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 2981 #endif 2982 2983 /* Kick TX ring. */ 2984 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 2985 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 2986 2987 /* Mark TX ring as full if we reach a certain threshold. */ 2988 if (++ring->queued > IWN_TX_RING_HIMARK) 2989 sc->qfullmsk |= 1 << ring->qid; 2990 2991 return 0; 2992 } 2993 2994 static void 2995 iwn_start(struct ifnet *ifp) 2996 { 2997 struct iwn_softc *sc = ifp->if_softc; 2998 struct ieee80211com *ic = &sc->sc_ic; 2999 struct ieee80211_node *ni; 3000 struct ether_header *eh; 3001 struct mbuf *m; 3002 int ac; 3003 3004 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3005 return; 3006 3007 for (;;) { 3008 if (sc->qfullmsk != 0) { 3009 ifp->if_flags |= IFF_OACTIVE; 3010 break; 3011 } 3012 /* Send pending management frames first. */ 3013 IF_DEQUEUE(&ic->ic_mgtq, m); 3014 if (m != NULL) { 3015 ni = (void *)m->m_pkthdr.rcvif; 3016 ac = 0; 3017 goto sendit; 3018 } 3019 if (ic->ic_state != IEEE80211_S_RUN) 3020 break; 3021 3022 /* Encapsulate and send data frames. */ 3023 IFQ_DEQUEUE(&ifp->if_snd, m); 3024 if (m == NULL) 3025 break; 3026 if (m->m_len < sizeof (*eh) && 3027 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3028 ifp->if_oerrors++; 3029 continue; 3030 } 3031 eh = mtod(m, struct ether_header *); 3032 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3033 if (ni == NULL) { 3034 m_freem(m); 3035 ifp->if_oerrors++; 3036 continue; 3037 } 3038 /* classify mbuf so we can find which tx ring to use */ 3039 if (ieee80211_classify(ic, m, ni) != 0) { 3040 m_freem(m); 3041 ieee80211_free_node(ni); 3042 ifp->if_oerrors++; 3043 continue; 3044 } 3045 3046 /* No QoS encapsulation for EAPOL frames. */ 3047 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3048 M_WME_GETAC(m) : WME_AC_BE; 3049 3050 bpf_mtap(ifp, m); 3051 3052 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3053 ieee80211_free_node(ni); 3054 ifp->if_oerrors++; 3055 continue; 3056 } 3057 sendit: 3058 bpf_mtap3(ic->ic_rawbpf, m); 3059 3060 if (iwn_tx(sc, m, ni, ac) != 0) { 3061 ieee80211_free_node(ni); 3062 ifp->if_oerrors++; 3063 continue; 3064 } 3065 3066 sc->sc_tx_timer = 5; 3067 ifp->if_timer = 1; 3068 } 3069 } 3070 3071 static void 3072 iwn_watchdog(struct ifnet *ifp) 3073 { 3074 struct iwn_softc *sc = ifp->if_softc; 3075 3076 ifp->if_timer = 0; 3077 3078 if (sc->sc_tx_timer > 0) { 3079 if (--sc->sc_tx_timer == 0) { 3080 aprint_error_dev(sc->sc_dev, 3081 "device timeout\n"); 3082 ifp->if_flags &= ~IFF_UP; 3083 iwn_stop(ifp, 1); 3084 ifp->if_oerrors++; 3085 return; 3086 } 3087 ifp->if_timer = 1; 3088 } 3089 3090 ieee80211_watchdog(&sc->sc_ic); 3091 } 3092 3093 static int 3094 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3095 { 3096 struct iwn_softc *sc = ifp->if_softc; 3097 struct ieee80211com *ic = &sc->sc_ic; 3098 struct ifaddr *ifa; 3099 const struct sockaddr *sa; 3100 int s, error = 0; 3101 3102 s = splnet(); 3103 3104 switch (cmd) { 3105 case SIOCSIFADDR: 3106 ifa = (struct ifaddr *)data; 3107 ifp->if_flags |= IFF_UP; 3108 #ifdef INET 3109 if (ifa->ifa_addr->sa_family == AF_INET) 3110 arp_ifinit(&ic->ic_ac, ifa); 3111 #endif 3112 /* FALLTHROUGH */ 3113 case SIOCSIFFLAGS: 3114 /* XXX Added as it is in every NetBSD driver */ 3115 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3116 break; 3117 if (ifp->if_flags & IFF_UP) { 3118 if (!(ifp->if_flags & IFF_RUNNING)) 3119 error = iwn_init(ifp); 3120 } else { 3121 if (ifp->if_flags & IFF_RUNNING) 3122 iwn_stop(ifp, 1); 3123 } 3124 break; 3125 3126 case SIOCADDMULTI: 3127 case SIOCDELMULTI: 3128 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3129 error = (cmd == SIOCADDMULTI) ? 3130 ether_addmulti(sa, &sc->sc_ec) : 3131 ether_delmulti(sa, &sc->sc_ec); 3132 3133 if (error == ENETRESET) 3134 error = 0; 3135 break; 3136 3137 default: 3138 error = ieee80211_ioctl(ic, cmd, data); 3139 } 3140 3141 if (error == ENETRESET) { 3142 error = 0; 3143 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3144 (IFF_UP | IFF_RUNNING)) { 3145 iwn_stop(ifp, 0); 3146 error = iwn_init(ifp); 3147 } 3148 } 3149 3150 splx(s); 3151 return error; 3152 } 3153 3154 /* 3155 * Send a command to the firmware. 3156 */ 3157 static int 3158 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3159 { 3160 struct iwn_tx_ring *ring = &sc->txq[4]; 3161 struct iwn_tx_desc *desc; 3162 struct iwn_tx_data *data; 3163 struct iwn_tx_cmd *cmd; 3164 struct mbuf *m; 3165 bus_addr_t paddr; 3166 int totlen, error; 3167 3168 desc = &ring->desc[ring->cur]; 3169 data = &ring->data[ring->cur]; 3170 totlen = 4 + size; 3171 3172 if (size > sizeof cmd->data) { 3173 /* Command is too large to fit in a descriptor. */ 3174 if (totlen > MCLBYTES) 3175 return EINVAL; 3176 MGETHDR(m, M_DONTWAIT, MT_DATA); 3177 if (m == NULL) 3178 return ENOMEM; 3179 if (totlen > MHLEN) { 3180 MCLGET(m, M_DONTWAIT); 3181 if (!(m->m_flags & M_EXT)) { 3182 m_freem(m); 3183 return ENOMEM; 3184 } 3185 } 3186 cmd = mtod(m, struct iwn_tx_cmd *); 3187 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3188 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3189 if (error != 0) { 3190 m_freem(m); 3191 return error; 3192 } 3193 data->m = m; 3194 paddr = data->map->dm_segs[0].ds_addr; 3195 } else { 3196 cmd = &ring->cmd[ring->cur]; 3197 paddr = data->cmd_paddr; 3198 } 3199 3200 cmd->code = code; 3201 cmd->flags = 0; 3202 cmd->qid = ring->qid; 3203 cmd->idx = ring->cur; 3204 memcpy(cmd->data, buf, size); 3205 3206 desc->nsegs = 1; 3207 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3208 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3209 3210 if (size > sizeof cmd->data) { 3211 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3212 BUS_DMASYNC_PREWRITE); 3213 } else { 3214 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3215 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3216 totlen, BUS_DMASYNC_PREWRITE); 3217 } 3218 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3219 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3220 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3221 3222 #ifdef notyet 3223 /* Update TX scheduler. */ 3224 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3225 #endif 3226 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3227 3228 /* Kick command ring. */ 3229 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3230 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3231 3232 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3233 } 3234 3235 static int 3236 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3237 { 3238 struct iwn4965_node_info hnode; 3239 char *src, *dst; 3240 3241 /* 3242 * We use the node structure for 5000 Series internally (it is 3243 * a superset of the one for 4965AGN). We thus copy the common 3244 * fields before sending the command. 3245 */ 3246 src = (char *)node; 3247 dst = (char *)&hnode; 3248 memcpy(dst, src, 48); 3249 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3250 memcpy(dst + 48, src + 72, 20); 3251 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3252 } 3253 3254 static int 3255 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3256 { 3257 /* Direct mapping. */ 3258 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3259 } 3260 3261 static int 3262 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3263 { 3264 struct iwn_node *wn = (void *)ni; 3265 struct ieee80211_rateset *rs = &ni->ni_rates; 3266 struct iwn_cmd_link_quality linkq; 3267 const struct iwn_rate *rinfo; 3268 uint8_t txant; 3269 int i, txrate; 3270 3271 /* Use the first valid TX antenna. */ 3272 txant = IWN_LSB(sc->txchainmask); 3273 3274 memset(&linkq, 0, sizeof linkq); 3275 linkq.id = wn->id; 3276 linkq.antmsk_1stream = txant; 3277 linkq.antmsk_2stream = IWN_ANT_AB; 3278 linkq.ampdu_max = 31; 3279 linkq.ampdu_threshold = 3; 3280 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3281 3282 /* Start at highest available bit-rate. */ 3283 txrate = rs->rs_nrates - 1; 3284 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3285 rinfo = &iwn_rates[wn->ridx[txrate]]; 3286 linkq.retry[i].plcp = rinfo->plcp; 3287 linkq.retry[i].rflags = rinfo->flags; 3288 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3289 /* Next retry at immediate lower bit-rate. */ 3290 if (txrate > 0) 3291 txrate--; 3292 } 3293 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3294 } 3295 3296 /* 3297 * Broadcast node is used to send group-addressed and management frames. 3298 */ 3299 static int 3300 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3301 { 3302 struct iwn_ops *ops = &sc->ops; 3303 struct iwn_node_info node; 3304 struct iwn_cmd_link_quality linkq; 3305 const struct iwn_rate *rinfo; 3306 uint8_t txant; 3307 int i, error; 3308 3309 memset(&node, 0, sizeof node); 3310 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3311 node.id = sc->broadcast_id; 3312 DPRINTF(("adding broadcast node\n")); 3313 if ((error = ops->add_node(sc, &node, async)) != 0) 3314 return error; 3315 3316 /* Use the first valid TX antenna. */ 3317 txant = IWN_LSB(sc->txchainmask); 3318 3319 memset(&linkq, 0, sizeof linkq); 3320 linkq.id = sc->broadcast_id; 3321 linkq.antmsk_1stream = txant; 3322 linkq.antmsk_2stream = IWN_ANT_AB; 3323 linkq.ampdu_max = 64; 3324 linkq.ampdu_threshold = 3; 3325 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3326 3327 /* Use lowest mandatory bit-rate. */ 3328 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3329 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3330 linkq.retry[0].plcp = rinfo->plcp; 3331 linkq.retry[0].rflags = rinfo->flags; 3332 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3333 /* Use same bit-rate for all TX retries. */ 3334 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3335 linkq.retry[i].plcp = linkq.retry[0].plcp; 3336 linkq.retry[i].rflags = linkq.retry[0].rflags; 3337 } 3338 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3339 } 3340 3341 static void 3342 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3343 { 3344 struct iwn_cmd_led led; 3345 3346 /* Clear microcode LED ownership. */ 3347 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3348 3349 led.which = which; 3350 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3351 led.off = off; 3352 led.on = on; 3353 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3354 } 3355 3356 /* 3357 * Set the critical temperature at which the firmware will stop the radio 3358 * and notify us. 3359 */ 3360 static int 3361 iwn_set_critical_temp(struct iwn_softc *sc) 3362 { 3363 struct iwn_critical_temp crit; 3364 int32_t temp; 3365 3366 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3367 3368 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3369 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3370 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3371 temp = IWN_CTOK(110); 3372 else 3373 temp = 110; 3374 memset(&crit, 0, sizeof crit); 3375 crit.tempR = htole32(temp); 3376 DPRINTF(("setting critical temperature to %d\n", temp)); 3377 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3378 } 3379 3380 static int 3381 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3382 { 3383 struct iwn_cmd_timing cmd; 3384 uint64_t val, mod; 3385 3386 memset(&cmd, 0, sizeof cmd); 3387 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3388 cmd.bintval = htole16(ni->ni_intval); 3389 cmd.lintval = htole16(10); 3390 3391 /* Compute remaining time until next beacon. */ 3392 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3393 mod = le64toh(cmd.tstamp) % val; 3394 cmd.binitval = htole32((uint32_t)(val - mod)); 3395 3396 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3397 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3398 3399 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3400 } 3401 3402 static void 3403 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3404 { 3405 /* Adjust TX power if need be (delta >= 3 degC). */ 3406 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3407 if (abs(temp - sc->temp) >= 3) { 3408 /* Record temperature of last calibration. */ 3409 sc->temp = temp; 3410 (void)iwn4965_set_txpower(sc, 1); 3411 } 3412 } 3413 3414 /* 3415 * Set TX power for current channel (each rate has its own power settings). 3416 * This function takes into account the regulatory information from EEPROM, 3417 * the current temperature and the current voltage. 3418 */ 3419 static int 3420 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3421 { 3422 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3423 #define fdivround(a, b, n) \ 3424 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3425 /* Linear interpolation. */ 3426 #define interpolate(x, x1, y1, x2, y2, n) \ 3427 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3428 3429 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3430 struct ieee80211com *ic = &sc->sc_ic; 3431 struct iwn_ucode_info *uc = &sc->ucode_info; 3432 struct ieee80211_channel *ch; 3433 struct iwn4965_cmd_txpower cmd; 3434 struct iwn4965_eeprom_chan_samples *chans; 3435 const uint8_t *rf_gain, *dsp_gain; 3436 int32_t vdiff, tdiff; 3437 int i, c, grp, maxpwr; 3438 uint8_t chan; 3439 3440 /* Retrieve current channel from last RXON. */ 3441 chan = sc->rxon.chan; 3442 DPRINTF(("setting TX power for channel %d\n", chan)); 3443 ch = &ic->ic_channels[chan]; 3444 3445 memset(&cmd, 0, sizeof cmd); 3446 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3447 cmd.chan = chan; 3448 3449 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3450 maxpwr = sc->maxpwr5GHz; 3451 rf_gain = iwn4965_rf_gain_5ghz; 3452 dsp_gain = iwn4965_dsp_gain_5ghz; 3453 } else { 3454 maxpwr = sc->maxpwr2GHz; 3455 rf_gain = iwn4965_rf_gain_2ghz; 3456 dsp_gain = iwn4965_dsp_gain_2ghz; 3457 } 3458 3459 /* Compute voltage compensation. */ 3460 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3461 if (vdiff > 0) 3462 vdiff *= 2; 3463 if (abs(vdiff) > 2) 3464 vdiff = 0; 3465 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3466 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3467 3468 /* Get channel attenuation group. */ 3469 if (chan <= 20) /* 1-20 */ 3470 grp = 4; 3471 else if (chan <= 43) /* 34-43 */ 3472 grp = 0; 3473 else if (chan <= 70) /* 44-70 */ 3474 grp = 1; 3475 else if (chan <= 124) /* 71-124 */ 3476 grp = 2; 3477 else /* 125-200 */ 3478 grp = 3; 3479 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3480 3481 /* Get channel sub-band. */ 3482 for (i = 0; i < IWN_NBANDS; i++) 3483 if (sc->bands[i].lo != 0 && 3484 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3485 break; 3486 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3487 return EINVAL; 3488 chans = sc->bands[i].chans; 3489 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3490 3491 for (c = 0; c < 2; c++) { 3492 uint8_t power, gain, temp; 3493 int maxchpwr, pwr, ridx, idx; 3494 3495 power = interpolate(chan, 3496 chans[0].num, chans[0].samples[c][1].power, 3497 chans[1].num, chans[1].samples[c][1].power, 1); 3498 gain = interpolate(chan, 3499 chans[0].num, chans[0].samples[c][1].gain, 3500 chans[1].num, chans[1].samples[c][1].gain, 1); 3501 temp = interpolate(chan, 3502 chans[0].num, chans[0].samples[c][1].temp, 3503 chans[1].num, chans[1].samples[c][1].temp, 1); 3504 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3505 c, power, gain, temp)); 3506 3507 /* Compute temperature compensation. */ 3508 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3509 DPRINTF(("temperature compensation=%d (current=%d, " 3510 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3511 3512 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3513 /* Convert dBm to half-dBm. */ 3514 maxchpwr = sc->maxpwr[chan] * 2; 3515 if ((ridx / 8) & 1) 3516 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3517 3518 pwr = maxpwr; 3519 3520 /* Adjust TX power based on rate. */ 3521 if ((ridx % 8) == 5) 3522 pwr -= 15; /* OFDM48: -7.5dB */ 3523 else if ((ridx % 8) == 6) 3524 pwr -= 17; /* OFDM54: -8.5dB */ 3525 else if ((ridx % 8) == 7) 3526 pwr -= 20; /* OFDM60: -10dB */ 3527 else 3528 pwr -= 10; /* Others: -5dB */ 3529 3530 /* Do not exceed channel max TX power. */ 3531 if (pwr > maxchpwr) 3532 pwr = maxchpwr; 3533 3534 idx = gain - (pwr - power) - tdiff - vdiff; 3535 if ((ridx / 8) & 1) /* MIMO */ 3536 idx += (int32_t)le32toh(uc->atten[grp][c]); 3537 3538 if (cmd.band == 0) 3539 idx += 9; /* 5GHz */ 3540 if (ridx == IWN_RIDX_MAX) 3541 idx += 5; /* CCK */ 3542 3543 /* Make sure idx stays in a valid range. */ 3544 if (idx < 0) 3545 idx = 0; 3546 else if (idx > IWN4965_MAX_PWR_INDEX) 3547 idx = IWN4965_MAX_PWR_INDEX; 3548 3549 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3550 c, ridx, idx)); 3551 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3552 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3553 } 3554 } 3555 3556 DPRINTF(("setting TX power for chan %d\n", chan)); 3557 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3558 3559 #undef interpolate 3560 #undef fdivround 3561 } 3562 3563 static int 3564 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3565 { 3566 struct iwn5000_cmd_txpower cmd; 3567 3568 /* 3569 * TX power calibration is handled automatically by the firmware 3570 * for 5000 Series. 3571 */ 3572 memset(&cmd, 0, sizeof cmd); 3573 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3574 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3575 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3576 DPRINTF(("setting TX power\n")); 3577 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3578 } 3579 3580 /* 3581 * Retrieve the maximum RSSI (in dBm) among receivers. 3582 */ 3583 static int 3584 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3585 { 3586 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3587 uint8_t mask, agc; 3588 int rssi; 3589 3590 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3591 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3592 3593 rssi = 0; 3594 if (mask & IWN_ANT_A) 3595 rssi = MAX(rssi, phy->rssi[0]); 3596 if (mask & IWN_ANT_B) 3597 rssi = MAX(rssi, phy->rssi[2]); 3598 if (mask & IWN_ANT_C) 3599 rssi = MAX(rssi, phy->rssi[4]); 3600 3601 return rssi - agc - IWN_RSSI_TO_DBM; 3602 } 3603 3604 static int 3605 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3606 { 3607 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3608 uint8_t agc; 3609 int rssi; 3610 3611 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3612 3613 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3614 le16toh(phy->rssi[1]) & 0xff); 3615 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3616 3617 return rssi - agc - IWN_RSSI_TO_DBM; 3618 } 3619 3620 /* 3621 * Retrieve the average noise (in dBm) among receivers. 3622 */ 3623 static int 3624 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3625 { 3626 int i, total, nbant, noise; 3627 3628 total = nbant = 0; 3629 for (i = 0; i < 3; i++) { 3630 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3631 continue; 3632 total += noise; 3633 nbant++; 3634 } 3635 /* There should be at least one antenna but check anyway. */ 3636 return (nbant == 0) ? -127 : (total / nbant) - 107; 3637 } 3638 3639 /* 3640 * Compute temperature (in degC) from last received statistics. 3641 */ 3642 static int 3643 iwn4965_get_temperature(struct iwn_softc *sc) 3644 { 3645 struct iwn_ucode_info *uc = &sc->ucode_info; 3646 int32_t r1, r2, r3, r4, temp; 3647 3648 r1 = le32toh(uc->temp[0].chan20MHz); 3649 r2 = le32toh(uc->temp[1].chan20MHz); 3650 r3 = le32toh(uc->temp[2].chan20MHz); 3651 r4 = le32toh(sc->rawtemp); 3652 3653 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3654 return 0; 3655 3656 /* Sign-extend 23-bit R4 value to 32-bit. */ 3657 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3658 /* Compute temperature in Kelvin. */ 3659 temp = (259 * (r4 - r2)) / (r3 - r1); 3660 temp = (temp * 97) / 100 + 8; 3661 3662 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3663 return IWN_KTOC(temp); 3664 } 3665 3666 static int 3667 iwn5000_get_temperature(struct iwn_softc *sc) 3668 { 3669 int32_t temp; 3670 3671 /* 3672 * Temperature is not used by the driver for 5000 Series because 3673 * TX power calibration is handled by firmware. We export it to 3674 * users through the sensor framework though. 3675 */ 3676 temp = le32toh(sc->rawtemp); 3677 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3678 temp = (temp / -5) + sc->temp_off; 3679 temp = IWN_KTOC(temp); 3680 } 3681 return temp; 3682 } 3683 3684 /* 3685 * Initialize sensitivity calibration state machine. 3686 */ 3687 static int 3688 iwn_init_sensitivity(struct iwn_softc *sc) 3689 { 3690 struct iwn_ops *ops = &sc->ops; 3691 struct iwn_calib_state *calib = &sc->calib; 3692 uint32_t flags; 3693 int error; 3694 3695 /* Reset calibration state machine. */ 3696 memset(calib, 0, sizeof (*calib)); 3697 calib->state = IWN_CALIB_STATE_INIT; 3698 calib->cck_state = IWN_CCK_STATE_HIFA; 3699 /* Set initial correlation values. */ 3700 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3701 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3702 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3703 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3704 calib->cck_x4 = 125; 3705 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3706 calib->energy_cck = sc->limits->energy_cck; 3707 3708 /* Write initial sensitivity. */ 3709 if ((error = iwn_send_sensitivity(sc)) != 0) 3710 return error; 3711 3712 /* Write initial gains. */ 3713 if ((error = ops->init_gains(sc)) != 0) 3714 return error; 3715 3716 /* Request statistics at each beacon interval. */ 3717 flags = 0; 3718 DPRINTF(("sending request for statistics\n")); 3719 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3720 } 3721 3722 /* 3723 * Collect noise and RSSI statistics for the first 20 beacons received 3724 * after association and use them to determine connected antennas and 3725 * to set differential gains. 3726 */ 3727 static void 3728 iwn_collect_noise(struct iwn_softc *sc, 3729 const struct iwn_rx_general_stats *stats) 3730 { 3731 struct iwn_ops *ops = &sc->ops; 3732 struct iwn_calib_state *calib = &sc->calib; 3733 uint32_t val; 3734 int i; 3735 3736 /* Accumulate RSSI and noise for all 3 antennas. */ 3737 for (i = 0; i < 3; i++) { 3738 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3739 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3740 } 3741 /* NB: We update differential gains only once after 20 beacons. */ 3742 if (++calib->nbeacons < 20) 3743 return; 3744 3745 /* Determine highest average RSSI. */ 3746 val = MAX(calib->rssi[0], calib->rssi[1]); 3747 val = MAX(calib->rssi[2], val); 3748 3749 /* Determine which antennas are connected. */ 3750 sc->chainmask = sc->rxchainmask; 3751 for (i = 0; i < 3; i++) 3752 if (val - calib->rssi[i] > 15 * 20) 3753 sc->chainmask &= ~(1 << i); 3754 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3755 sc->rxchainmask, sc->chainmask)); 3756 3757 /* If none of the TX antennas are connected, keep at least one. */ 3758 if ((sc->chainmask & sc->txchainmask) == 0) 3759 sc->chainmask |= IWN_LSB(sc->txchainmask); 3760 3761 (void)ops->set_gains(sc); 3762 calib->state = IWN_CALIB_STATE_RUN; 3763 3764 #ifdef notyet 3765 /* XXX Disable RX chains with no antennas connected. */ 3766 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3767 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3768 #endif 3769 3770 /* Enable power-saving mode if requested by user. */ 3771 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3772 (void)iwn_set_pslevel(sc, 0, 3, 1); 3773 } 3774 3775 static int 3776 iwn4965_init_gains(struct iwn_softc *sc) 3777 { 3778 struct iwn_phy_calib_gain cmd; 3779 3780 memset(&cmd, 0, sizeof cmd); 3781 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3782 /* Differential gains initially set to 0 for all 3 antennas. */ 3783 DPRINTF(("setting initial differential gains\n")); 3784 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3785 } 3786 3787 static int 3788 iwn5000_init_gains(struct iwn_softc *sc) 3789 { 3790 struct iwn_phy_calib cmd; 3791 3792 memset(&cmd, 0, sizeof cmd); 3793 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3794 cmd.ngroups = 1; 3795 cmd.isvalid = 1; 3796 DPRINTF(("setting initial differential gains\n")); 3797 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3798 } 3799 3800 static int 3801 iwn4965_set_gains(struct iwn_softc *sc) 3802 { 3803 struct iwn_calib_state *calib = &sc->calib; 3804 struct iwn_phy_calib_gain cmd; 3805 int i, delta, noise; 3806 3807 /* Get minimal noise among connected antennas. */ 3808 noise = INT_MAX; /* NB: There's at least one antenna. */ 3809 for (i = 0; i < 3; i++) 3810 if (sc->chainmask & (1 << i)) 3811 noise = MIN(calib->noise[i], noise); 3812 3813 memset(&cmd, 0, sizeof cmd); 3814 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3815 /* Set differential gains for connected antennas. */ 3816 for (i = 0; i < 3; i++) { 3817 if (sc->chainmask & (1 << i)) { 3818 /* Compute attenuation (in unit of 1.5dB). */ 3819 delta = (noise - (int32_t)calib->noise[i]) / 30; 3820 /* NB: delta <= 0 */ 3821 /* Limit to [-4.5dB,0]. */ 3822 cmd.gain[i] = MIN(abs(delta), 3); 3823 if (delta < 0) 3824 cmd.gain[i] |= 1 << 2; /* sign bit */ 3825 } 3826 } 3827 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3828 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3829 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3830 } 3831 3832 static int 3833 iwn5000_set_gains(struct iwn_softc *sc) 3834 { 3835 struct iwn_calib_state *calib = &sc->calib; 3836 struct iwn_phy_calib_gain cmd; 3837 int i, ant, div, delta; 3838 3839 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3840 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3841 3842 memset(&cmd, 0, sizeof cmd); 3843 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3844 cmd.ngroups = 1; 3845 cmd.isvalid = 1; 3846 /* Get first available RX antenna as referential. */ 3847 ant = IWN_LSB(sc->rxchainmask); 3848 /* Set differential gains for other antennas. */ 3849 for (i = ant + 1; i < 3; i++) { 3850 if (sc->chainmask & (1 << i)) { 3851 /* The delta is relative to antenna "ant". */ 3852 delta = ((int32_t)calib->noise[ant] - 3853 (int32_t)calib->noise[i]) / div; 3854 /* Limit to [-4.5dB,+4.5dB]. */ 3855 cmd.gain[i - 1] = MIN(abs(delta), 3); 3856 if (delta < 0) 3857 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3858 } 3859 } 3860 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3861 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3862 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3863 } 3864 3865 /* 3866 * Tune RF RX sensitivity based on the number of false alarms detected 3867 * during the last beacon period. 3868 */ 3869 static void 3870 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3871 { 3872 #define inc(val, inc, max) \ 3873 if ((val) < (max)) { \ 3874 if ((val) < (max) - (inc)) \ 3875 (val) += (inc); \ 3876 else \ 3877 (val) = (max); \ 3878 needs_update = 1; \ 3879 } 3880 #define dec(val, dec, min) \ 3881 if ((val) > (min)) { \ 3882 if ((val) > (min) + (dec)) \ 3883 (val) -= (dec); \ 3884 else \ 3885 (val) = (min); \ 3886 needs_update = 1; \ 3887 } 3888 3889 const struct iwn_sensitivity_limits *limits = sc->limits; 3890 struct iwn_calib_state *calib = &sc->calib; 3891 uint32_t val, rxena, fa; 3892 uint32_t energy[3], energy_min; 3893 uint8_t noise[3], noise_ref; 3894 int i, needs_update = 0; 3895 3896 /* Check that we've been enabled long enough. */ 3897 if ((rxena = le32toh(stats->general.load)) == 0) 3898 return; 3899 3900 /* Compute number of false alarms since last call for OFDM. */ 3901 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3902 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3903 fa *= 200 * 1024; /* 200TU */ 3904 3905 /* Save counters values for next call. */ 3906 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3907 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3908 3909 if (fa > 50 * rxena) { 3910 /* High false alarm count, decrease sensitivity. */ 3911 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3912 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3913 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3914 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3915 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3916 3917 } else if (fa < 5 * rxena) { 3918 /* Low false alarm count, increase sensitivity. */ 3919 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3920 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3921 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3922 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3923 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3924 } 3925 3926 /* Compute maximum noise among 3 receivers. */ 3927 for (i = 0; i < 3; i++) 3928 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 3929 val = MAX(noise[0], noise[1]); 3930 val = MAX(noise[2], val); 3931 /* Insert it into our samples table. */ 3932 calib->noise_samples[calib->cur_noise_sample] = val; 3933 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3934 3935 /* Compute maximum noise among last 20 samples. */ 3936 noise_ref = calib->noise_samples[0]; 3937 for (i = 1; i < 20; i++) 3938 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 3939 3940 /* Compute maximum energy among 3 receivers. */ 3941 for (i = 0; i < 3; i++) 3942 energy[i] = le32toh(stats->general.energy[i]); 3943 val = MIN(energy[0], energy[1]); 3944 val = MIN(energy[2], val); 3945 /* Insert it into our samples table. */ 3946 calib->energy_samples[calib->cur_energy_sample] = val; 3947 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 3948 3949 /* Compute minimum energy among last 10 samples. */ 3950 energy_min = calib->energy_samples[0]; 3951 for (i = 1; i < 10; i++) 3952 energy_min = MAX(energy_min, calib->energy_samples[i]); 3953 energy_min += 6; 3954 3955 /* Compute number of false alarms since last call for CCK. */ 3956 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 3957 fa += le32toh(stats->cck.fa) - calib->fa_cck; 3958 fa *= 200 * 1024; /* 200TU */ 3959 3960 /* Save counters values for next call. */ 3961 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 3962 calib->fa_cck = le32toh(stats->cck.fa); 3963 3964 if (fa > 50 * rxena) { 3965 /* High false alarm count, decrease sensitivity. */ 3966 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 3967 calib->cck_state = IWN_CCK_STATE_HIFA; 3968 calib->low_fa = 0; 3969 3970 if (calib->cck_x4 > 160) { 3971 calib->noise_ref = noise_ref; 3972 if (calib->energy_cck > 2) 3973 dec(calib->energy_cck, 2, energy_min); 3974 } 3975 if (calib->cck_x4 < 160) { 3976 calib->cck_x4 = 161; 3977 needs_update = 1; 3978 } else 3979 inc(calib->cck_x4, 3, limits->max_cck_x4); 3980 3981 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 3982 3983 } else if (fa < 5 * rxena) { 3984 /* Low false alarm count, increase sensitivity. */ 3985 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 3986 calib->cck_state = IWN_CCK_STATE_LOFA; 3987 calib->low_fa++; 3988 3989 if (calib->cck_state != IWN_CCK_STATE_INIT && 3990 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 3991 calib->low_fa > 100)) { 3992 inc(calib->energy_cck, 2, limits->min_energy_cck); 3993 dec(calib->cck_x4, 3, limits->min_cck_x4); 3994 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 3995 } 3996 } else { 3997 /* Not worth to increase or decrease sensitivity. */ 3998 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 3999 calib->low_fa = 0; 4000 calib->noise_ref = noise_ref; 4001 4002 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4003 /* Previous interval had many false alarms. */ 4004 dec(calib->energy_cck, 8, energy_min); 4005 } 4006 calib->cck_state = IWN_CCK_STATE_INIT; 4007 } 4008 4009 if (needs_update) 4010 (void)iwn_send_sensitivity(sc); 4011 #undef dec 4012 #undef inc 4013 } 4014 4015 static int 4016 iwn_send_sensitivity(struct iwn_softc *sc) 4017 { 4018 struct iwn_calib_state *calib = &sc->calib; 4019 struct iwn_sensitivity_cmd cmd; 4020 4021 memset(&cmd, 0, sizeof cmd); 4022 cmd.which = IWN_SENSITIVITY_WORKTBL; 4023 /* OFDM modulation. */ 4024 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4025 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4026 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4027 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4028 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4029 cmd.energy_ofdm_th = htole16(62); 4030 /* CCK modulation. */ 4031 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4032 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4033 cmd.energy_cck = htole16(calib->energy_cck); 4034 /* Barker modulation: use default values. */ 4035 cmd.corr_barker = htole16(190); 4036 cmd.corr_barker_mrc = htole16(390); 4037 4038 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4039 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4040 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4041 calib->energy_cck)); 4042 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4043 } 4044 4045 /* 4046 * Set STA mode power saving level (between 0 and 5). 4047 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4048 */ 4049 static int 4050 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4051 { 4052 struct iwn_pmgt_cmd cmd; 4053 const struct iwn_pmgt *pmgt; 4054 uint32_t maxp, skip_dtim; 4055 pcireg_t reg; 4056 int i; 4057 4058 /* Select which PS parameters to use. */ 4059 if (dtim <= 2) 4060 pmgt = &iwn_pmgt[0][level]; 4061 else if (dtim <= 10) 4062 pmgt = &iwn_pmgt[1][level]; 4063 else 4064 pmgt = &iwn_pmgt[2][level]; 4065 4066 memset(&cmd, 0, sizeof cmd); 4067 if (level != 0) /* not CAM */ 4068 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4069 if (level == 5) 4070 cmd.flags |= htole16(IWN_PS_FAST_PD); 4071 /* Retrieve PCIe Active State Power Management (ASPM). */ 4072 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4073 sc->sc_cap_off + PCI_PCIE_LCSR); 4074 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4075 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4076 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4077 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4078 4079 if (dtim == 0) { 4080 dtim = 1; 4081 skip_dtim = 0; 4082 } else 4083 skip_dtim = pmgt->skip_dtim; 4084 if (skip_dtim != 0) { 4085 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4086 maxp = pmgt->intval[4]; 4087 if (maxp == (uint32_t)-1) 4088 maxp = dtim * (skip_dtim + 1); 4089 else if (maxp > dtim) 4090 maxp = (maxp / dtim) * dtim; 4091 } else 4092 maxp = dtim; 4093 for (i = 0; i < 5; i++) 4094 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4095 4096 DPRINTF(("setting power saving level to %d\n", level)); 4097 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4098 } 4099 4100 int 4101 iwn5000_runtime_calib(struct iwn_softc *sc) 4102 { 4103 struct iwn5000_calib_config cmd; 4104 4105 memset(&cmd, 0, sizeof cmd); 4106 cmd.ucode.once.enable = 0xffffffff; 4107 cmd.ucode.once.start = IWN5000_CALIB_DC; 4108 DPRINTF(("configuring runtime calibration\n")); 4109 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4110 } 4111 4112 static int 4113 iwn_config(struct iwn_softc *sc) 4114 { 4115 struct iwn_ops *ops = &sc->ops; 4116 struct ieee80211com *ic = &sc->sc_ic; 4117 struct ifnet *ifp = ic->ic_ifp; 4118 struct iwn_bluetooth bluetooth; 4119 uint32_t txmask; 4120 uint16_t rxchain; 4121 int error; 4122 4123 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4124 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4125 /* Configure runtime DC calibration. */ 4126 error = iwn5000_runtime_calib(sc); 4127 if (error != 0) { 4128 aprint_error_dev(sc->sc_dev, 4129 "could not configure runtime calibration\n"); 4130 return error; 4131 } 4132 } 4133 4134 /* Configure valid TX chains for 5000 Series. */ 4135 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4136 txmask = htole32(sc->txchainmask); 4137 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4138 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4139 sizeof txmask, 0); 4140 if (error != 0) { 4141 aprint_error_dev(sc->sc_dev, 4142 "could not configure valid TX chains\n"); 4143 return error; 4144 } 4145 } 4146 4147 /* Configure bluetooth coexistence. */ 4148 memset(&bluetooth, 0, sizeof bluetooth); 4149 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4150 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4151 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4152 DPRINTF(("configuring bluetooth coexistence\n")); 4153 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4154 if (error != 0) { 4155 aprint_error_dev(sc->sc_dev, 4156 "could not configure bluetooth coexistence\n"); 4157 return error; 4158 } 4159 4160 /* Set mode, channel, RX filter and enable RX. */ 4161 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4162 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4163 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4164 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4165 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4166 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4167 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4168 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4169 switch (ic->ic_opmode) { 4170 case IEEE80211_M_STA: 4171 sc->rxon.mode = IWN_MODE_STA; 4172 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4173 break; 4174 case IEEE80211_M_MONITOR: 4175 sc->rxon.mode = IWN_MODE_MONITOR; 4176 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4177 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4178 break; 4179 default: 4180 /* Should not get there. */ 4181 break; 4182 } 4183 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4184 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4185 sc->rxon.ht_single_mask = 0xff; 4186 sc->rxon.ht_dual_mask = 0xff; 4187 sc->rxon.ht_triple_mask = 0xff; 4188 rxchain = 4189 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4190 IWN_RXCHAIN_MIMO_COUNT(2) | 4191 IWN_RXCHAIN_IDLE_COUNT(2); 4192 sc->rxon.rxchain = htole16(rxchain); 4193 DPRINTF(("setting configuration\n")); 4194 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4195 if (error != 0) { 4196 aprint_error_dev(sc->sc_dev, 4197 "RXON command failed\n"); 4198 return error; 4199 } 4200 4201 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4202 aprint_error_dev(sc->sc_dev, 4203 "could not add broadcast node\n"); 4204 return error; 4205 } 4206 4207 /* Configuration has changed, set TX power accordingly. */ 4208 if ((error = ops->set_txpower(sc, 0)) != 0) { 4209 aprint_error_dev(sc->sc_dev, 4210 "could not set TX power\n"); 4211 return error; 4212 } 4213 4214 if ((error = iwn_set_critical_temp(sc)) != 0) { 4215 aprint_error_dev(sc->sc_dev, 4216 "could not set critical temperature\n"); 4217 return error; 4218 } 4219 4220 /* Set power saving level to CAM during initialization. */ 4221 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4222 aprint_error_dev(sc->sc_dev, 4223 "could not set power saving level\n"); 4224 return error; 4225 } 4226 return 0; 4227 } 4228 4229 static int 4230 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4231 { 4232 struct ieee80211com *ic = &sc->sc_ic; 4233 struct iwn_scan_hdr *hdr; 4234 struct iwn_cmd_data *tx; 4235 struct iwn_scan_essid *essid; 4236 struct iwn_scan_chan *chan; 4237 struct ieee80211_frame *wh; 4238 struct ieee80211_rateset *rs; 4239 struct ieee80211_channel *c; 4240 uint8_t *buf, *frm; 4241 uint16_t rxchain; 4242 uint8_t txant; 4243 int buflen, error; 4244 4245 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4246 if (buf == NULL) { 4247 aprint_error_dev(sc->sc_dev, 4248 "could not allocate buffer for scan command\n"); 4249 return ENOMEM; 4250 } 4251 hdr = (struct iwn_scan_hdr *)buf; 4252 /* 4253 * Move to the next channel if no frames are received within 10ms 4254 * after sending the probe request. 4255 */ 4256 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4257 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4258 4259 /* Select antennas for scanning. */ 4260 rxchain = 4261 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4262 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4263 IWN_RXCHAIN_DRIVER_FORCE; 4264 if ((flags & IEEE80211_CHAN_5GHZ) && 4265 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4266 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4267 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4268 } else /* Use all available RX antennas. */ 4269 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4270 hdr->rxchain = htole16(rxchain); 4271 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4272 4273 tx = (struct iwn_cmd_data *)(hdr + 1); 4274 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4275 tx->id = sc->broadcast_id; 4276 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4277 4278 if (flags & IEEE80211_CHAN_5GHZ) { 4279 hdr->crc_threshold = 0xffff; 4280 /* Send probe requests at 6Mbps. */ 4281 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4282 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4283 } else { 4284 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4285 /* Send probe requests at 1Mbps. */ 4286 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4287 tx->rflags = IWN_RFLAG_CCK; 4288 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4289 } 4290 /* Use the first valid TX antenna. */ 4291 txant = IWN_LSB(sc->txchainmask); 4292 tx->rflags |= IWN_RFLAG_ANT(txant); 4293 4294 essid = (struct iwn_scan_essid *)(tx + 1); 4295 if (ic->ic_des_esslen != 0) { 4296 essid[0].id = IEEE80211_ELEMID_SSID; 4297 essid[0].len = ic->ic_des_esslen; 4298 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4299 } 4300 /* 4301 * Build a probe request frame. Most of the following code is a 4302 * copy & paste of what is done in net80211. 4303 */ 4304 wh = (struct ieee80211_frame *)(essid + 20); 4305 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4306 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4307 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4308 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4309 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4310 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4311 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4312 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4313 4314 frm = (uint8_t *)(wh + 1); 4315 frm = ieee80211_add_ssid(frm, NULL, 0); 4316 frm = ieee80211_add_rates(frm, rs); 4317 #ifndef IEEE80211_NO_HT 4318 if (ic->ic_flags & IEEE80211_F_HTON) 4319 frm = ieee80211_add_htcaps(frm, ic); 4320 #endif 4321 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4322 frm = ieee80211_add_xrates(frm, rs); 4323 4324 /* Set length of probe request. */ 4325 tx->len = htole16(frm - (uint8_t *)wh); 4326 4327 chan = (struct iwn_scan_chan *)frm; 4328 for (c = &ic->ic_channels[1]; 4329 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4330 if ((c->ic_flags & flags) != flags) 4331 continue; 4332 4333 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4334 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4335 chan->flags = 0; 4336 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4337 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4338 if (ic->ic_des_esslen != 0) 4339 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4340 chan->dsp_gain = 0x6e; 4341 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4342 chan->rf_gain = 0x3b; 4343 chan->active = htole16(24); 4344 chan->passive = htole16(110); 4345 } else { 4346 chan->rf_gain = 0x28; 4347 chan->active = htole16(36); 4348 chan->passive = htole16(120); 4349 } 4350 hdr->nchan++; 4351 chan++; 4352 } 4353 4354 buflen = (uint8_t *)chan - buf; 4355 hdr->len = htole16(buflen); 4356 4357 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4358 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4359 free(buf, M_DEVBUF); 4360 return error; 4361 } 4362 4363 static int 4364 iwn_auth(struct iwn_softc *sc) 4365 { 4366 struct iwn_ops *ops = &sc->ops; 4367 struct ieee80211com *ic = &sc->sc_ic; 4368 struct ieee80211_node *ni = ic->ic_bss; 4369 int error; 4370 4371 /* Update adapter configuration. */ 4372 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4373 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4374 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4375 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4376 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4377 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4378 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4379 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4380 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4381 switch (ic->ic_curmode) { 4382 case IEEE80211_MODE_11A: 4383 sc->rxon.cck_mask = 0; 4384 sc->rxon.ofdm_mask = 0x15; 4385 break; 4386 case IEEE80211_MODE_11B: 4387 sc->rxon.cck_mask = 0x03; 4388 sc->rxon.ofdm_mask = 0; 4389 break; 4390 default: /* Assume 802.11b/g. */ 4391 sc->rxon.cck_mask = 0x0f; 4392 sc->rxon.ofdm_mask = 0x15; 4393 } 4394 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4395 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4396 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4397 if (error != 0) { 4398 aprint_error_dev(sc->sc_dev, 4399 "RXON command failed\n"); 4400 return error; 4401 } 4402 4403 /* Configuration has changed, set TX power accordingly. */ 4404 if ((error = ops->set_txpower(sc, 1)) != 0) { 4405 aprint_error_dev(sc->sc_dev, 4406 "could not set TX power\n"); 4407 return error; 4408 } 4409 /* 4410 * Reconfiguring RXON clears the firmware nodes table so we must 4411 * add the broadcast node again. 4412 */ 4413 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4414 aprint_error_dev(sc->sc_dev, 4415 "could not add broadcast node\n"); 4416 return error; 4417 } 4418 return 0; 4419 } 4420 4421 static int 4422 iwn_run(struct iwn_softc *sc) 4423 { 4424 struct iwn_ops *ops = &sc->ops; 4425 struct ieee80211com *ic = &sc->sc_ic; 4426 struct ieee80211_node *ni = ic->ic_bss; 4427 struct iwn_node_info node; 4428 int error; 4429 4430 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4431 /* Link LED blinks while monitoring. */ 4432 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4433 return 0; 4434 } 4435 if ((error = iwn_set_timing(sc, ni)) != 0) { 4436 aprint_error_dev(sc->sc_dev, 4437 "could not set timing\n"); 4438 return error; 4439 } 4440 4441 /* Update adapter configuration. */ 4442 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4443 /* Short preamble and slot time are negotiated when associating. */ 4444 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4445 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4446 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4447 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4448 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4449 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4450 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4451 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4452 if (error != 0) { 4453 aprint_error_dev(sc->sc_dev, 4454 "could not update configuration\n"); 4455 return error; 4456 } 4457 4458 /* Configuration has changed, set TX power accordingly. */ 4459 if ((error = ops->set_txpower(sc, 1)) != 0) { 4460 aprint_error_dev(sc->sc_dev, 4461 "could not set TX power\n"); 4462 return error; 4463 } 4464 4465 /* Fake a join to initialize the TX rate. */ 4466 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4467 iwn_newassoc(ni, 1); 4468 4469 /* Add BSS node. */ 4470 memset(&node, 0, sizeof node); 4471 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4472 node.id = IWN_ID_BSS; 4473 #ifdef notyet 4474 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4475 IWN_AMDPU_DENSITY(5)); /* 2us */ 4476 #endif 4477 DPRINTF(("adding BSS node\n")); 4478 error = ops->add_node(sc, &node, 1); 4479 if (error != 0) { 4480 aprint_error_dev(sc->sc_dev, 4481 "could not add BSS node\n"); 4482 return error; 4483 } 4484 DPRINTF(("setting link quality for node %d\n", node.id)); 4485 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4486 aprint_error_dev(sc->sc_dev, 4487 "could not setup link quality for node %d\n", node.id); 4488 return error; 4489 } 4490 4491 if ((error = iwn_init_sensitivity(sc)) != 0) { 4492 aprint_error_dev(sc->sc_dev, 4493 "could not set sensitivity\n"); 4494 return error; 4495 } 4496 /* Start periodic calibration timer. */ 4497 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4498 sc->calib_cnt = 0; 4499 callout_schedule(&sc->calib_to, hz/2); 4500 4501 /* Link LED always on while associated. */ 4502 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4503 return 0; 4504 } 4505 4506 #ifdef IWN_HWCRYPTO 4507 /* 4508 * We support CCMP hardware encryption/decryption of unicast frames only. 4509 * HW support for TKIP really sucks. We should let TKIP die anyway. 4510 */ 4511 static int 4512 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4513 struct ieee80211_key *k) 4514 { 4515 struct iwn_softc *sc = ic->ic_softc; 4516 struct iwn_ops *ops = &sc->ops; 4517 struct iwn_node *wn = (void *)ni; 4518 struct iwn_node_info node; 4519 uint16_t kflags; 4520 4521 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4522 k->k_cipher != IEEE80211_CIPHER_CCMP) 4523 return ieee80211_set_key(ic, ni, k); 4524 4525 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4526 if (k->k_flags & IEEE80211_KEY_GROUP) 4527 kflags |= IWN_KFLAG_GROUP; 4528 4529 memset(&node, 0, sizeof node); 4530 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4531 sc->broadcast_id : wn->id; 4532 node.control = IWN_NODE_UPDATE; 4533 node.flags = IWN_FLAG_SET_KEY; 4534 node.kflags = htole16(kflags); 4535 node.kid = k->k_id; 4536 memcpy(node.key, k->k_key, k->k_len); 4537 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4538 return ops->add_node(sc, &node, 1); 4539 } 4540 4541 static void 4542 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4543 struct ieee80211_key *k) 4544 { 4545 struct iwn_softc *sc = ic->ic_softc; 4546 struct iwn_ops *ops = &sc->ops; 4547 struct iwn_node *wn = (void *)ni; 4548 struct iwn_node_info node; 4549 4550 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4551 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4552 /* See comment about other ciphers above. */ 4553 ieee80211_delete_key(ic, ni, k); 4554 return; 4555 } 4556 if (ic->ic_state != IEEE80211_S_RUN) 4557 return; /* Nothing to do. */ 4558 memset(&node, 0, sizeof node); 4559 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4560 sc->broadcast_id : wn->id; 4561 node.control = IWN_NODE_UPDATE; 4562 node.flags = IWN_FLAG_SET_KEY; 4563 node.kflags = htole16(IWN_KFLAG_INVALID); 4564 node.kid = 0xff; 4565 DPRINTF(("delete keys for node %d\n", node.id)); 4566 (void)ops->add_node(sc, &node, 1); 4567 } 4568 #endif 4569 4570 /* XXX Added for NetBSD (copied from rev 1.39). */ 4571 4572 static int 4573 iwn_wme_update(struct ieee80211com *ic) 4574 { 4575 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4576 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4577 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4578 const struct wmeParams *wmep; 4579 struct iwn_edca_params cmd; 4580 int ac; 4581 4582 /* don't override default WME values if WME is not actually enabled */ 4583 if (!(ic->ic_flags & IEEE80211_F_WME)) 4584 return 0; 4585 cmd.flags = 0; 4586 for (ac = 0; ac < WME_NUM_AC; ac++) { 4587 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4588 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4589 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4590 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4591 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4592 4593 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4594 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4595 cmd.ac[ac].cwmin, 4596 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4597 } 4598 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4599 #undef IWN_USEC 4600 #undef IWN_EXP2 4601 } 4602 4603 #ifndef IEEE80211_NO_HT 4604 /* 4605 * This function is called by upper layer when an ADDBA request is received 4606 * from another STA and before the ADDBA response is sent. 4607 */ 4608 static int 4609 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4610 uint8_t tid) 4611 { 4612 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4613 struct iwn_softc *sc = ic->ic_softc; 4614 struct iwn_ops *ops = &sc->ops; 4615 struct iwn_node *wn = (void *)ni; 4616 struct iwn_node_info node; 4617 4618 memset(&node, 0, sizeof node); 4619 node.id = wn->id; 4620 node.control = IWN_NODE_UPDATE; 4621 node.flags = IWN_FLAG_SET_ADDBA; 4622 node.addba_tid = tid; 4623 node.addba_ssn = htole16(ba->ba_winstart); 4624 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4625 ba->ba_winstart)); 4626 return ops->add_node(sc, &node, 1); 4627 } 4628 4629 /* 4630 * This function is called by upper layer on teardown of an HT-immediate 4631 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4632 */ 4633 static void 4634 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4635 uint8_t tid) 4636 { 4637 struct iwn_softc *sc = ic->ic_softc; 4638 struct iwn_ops *ops = &sc->ops; 4639 struct iwn_node *wn = (void *)ni; 4640 struct iwn_node_info node; 4641 4642 memset(&node, 0, sizeof node); 4643 node.id = wn->id; 4644 node.control = IWN_NODE_UPDATE; 4645 node.flags = IWN_FLAG_SET_DELBA; 4646 node.delba_tid = tid; 4647 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4648 (void)ops->add_node(sc, &node, 1); 4649 } 4650 4651 /* 4652 * This function is called by upper layer when an ADDBA response is received 4653 * from another STA. 4654 */ 4655 static int 4656 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4657 uint8_t tid) 4658 { 4659 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4660 struct iwn_softc *sc = ic->ic_softc; 4661 struct iwn_ops *ops = &sc->ops; 4662 struct iwn_node *wn = (void *)ni; 4663 struct iwn_node_info node; 4664 int error; 4665 4666 /* Enable TX for the specified RA/TID. */ 4667 wn->disable_tid &= ~(1 << tid); 4668 memset(&node, 0, sizeof node); 4669 node.id = wn->id; 4670 node.control = IWN_NODE_UPDATE; 4671 node.flags = IWN_FLAG_SET_DISABLE_TID; 4672 node.disable_tid = htole16(wn->disable_tid); 4673 error = ops->add_node(sc, &node, 1); 4674 if (error != 0) 4675 return error; 4676 4677 if ((error = iwn_nic_lock(sc)) != 0) 4678 return error; 4679 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4680 iwn_nic_unlock(sc); 4681 return 0; 4682 } 4683 4684 static void 4685 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4686 uint8_t tid) 4687 { 4688 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4689 struct iwn_softc *sc = ic->ic_softc; 4690 struct iwn_ops *ops = &sc->ops; 4691 4692 if (iwn_nic_lock(sc) != 0) 4693 return; 4694 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4695 iwn_nic_unlock(sc); 4696 } 4697 4698 static void 4699 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4700 uint8_t tid, uint16_t ssn) 4701 { 4702 struct iwn_node *wn = (void *)ni; 4703 int qid = 7 + tid; 4704 4705 /* Stop TX scheduler while we're changing its configuration. */ 4706 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4707 IWN4965_TXQ_STATUS_CHGACT); 4708 4709 /* Assign RA/TID translation to the queue. */ 4710 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4711 wn->id << 4 | tid); 4712 4713 /* Enable chain-building mode for the queue. */ 4714 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4715 4716 /* Set starting sequence number from the ADDBA request. */ 4717 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4718 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4719 4720 /* Set scheduler window size. */ 4721 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4722 IWN_SCHED_WINSZ); 4723 /* Set scheduler frame limit. */ 4724 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4725 IWN_SCHED_LIMIT << 16); 4726 4727 /* Enable interrupts for the queue. */ 4728 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4729 4730 /* Mark the queue as active. */ 4731 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4732 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4733 iwn_tid2fifo[tid] << 1); 4734 } 4735 4736 static void 4737 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4738 { 4739 int qid = 7 + tid; 4740 4741 /* Stop TX scheduler while we're changing its configuration. */ 4742 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4743 IWN4965_TXQ_STATUS_CHGACT); 4744 4745 /* Set starting sequence number from the ADDBA request. */ 4746 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4747 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4748 4749 /* Disable interrupts for the queue. */ 4750 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4751 4752 /* Mark the queue as inactive. */ 4753 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4754 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4755 } 4756 4757 static void 4758 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4759 uint8_t tid, uint16_t ssn) 4760 { 4761 struct iwn_node *wn = (void *)ni; 4762 int qid = 10 + tid; 4763 4764 /* Stop TX scheduler while we're changing its configuration. */ 4765 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4766 IWN5000_TXQ_STATUS_CHGACT); 4767 4768 /* Assign RA/TID translation to the queue. */ 4769 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4770 wn->id << 4 | tid); 4771 4772 /* Enable chain-building mode for the queue. */ 4773 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4774 4775 /* Enable aggregation for the queue. */ 4776 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4777 4778 /* Set starting sequence number from the ADDBA request. */ 4779 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4780 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4781 4782 /* Set scheduler window size and frame limit. */ 4783 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4784 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4785 4786 /* Enable interrupts for the queue. */ 4787 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4788 4789 /* Mark the queue as active. */ 4790 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4791 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4792 } 4793 4794 static void 4795 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4796 { 4797 int qid = 10 + tid; 4798 4799 /* Stop TX scheduler while we're changing its configuration. */ 4800 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4801 IWN5000_TXQ_STATUS_CHGACT); 4802 4803 /* Disable aggregation for the queue. */ 4804 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4805 4806 /* Set starting sequence number from the ADDBA request. */ 4807 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4808 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4809 4810 /* Disable interrupts for the queue. */ 4811 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4812 4813 /* Mark the queue as inactive. */ 4814 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4815 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4816 } 4817 #endif /* !IEEE80211_NO_HT */ 4818 4819 /* 4820 * Query calibration tables from the initialization firmware. We do this 4821 * only once at first boot. Called from a process context. 4822 */ 4823 static int 4824 iwn5000_query_calibration(struct iwn_softc *sc) 4825 { 4826 struct iwn5000_calib_config cmd; 4827 int error; 4828 4829 memset(&cmd, 0, sizeof cmd); 4830 cmd.ucode.once.enable = 0xffffffff; 4831 cmd.ucode.once.start = 0xffffffff; 4832 cmd.ucode.once.send = 0xffffffff; 4833 cmd.ucode.flags = 0xffffffff; 4834 DPRINTF(("sending calibration query\n")); 4835 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4836 if (error != 0) 4837 return error; 4838 4839 /* Wait at most two seconds for calibration to complete. */ 4840 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4841 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4842 return error; 4843 } 4844 4845 /* 4846 * Send calibration results to the runtime firmware. These results were 4847 * obtained on first boot from the initialization firmware. 4848 */ 4849 static int 4850 iwn5000_send_calibration(struct iwn_softc *sc) 4851 { 4852 int idx, error; 4853 4854 for (idx = 0; idx < 5; idx++) { 4855 if (sc->calibcmd[idx].buf == NULL) 4856 continue; /* No results available. */ 4857 DPRINTF(("send calibration result idx=%d len=%d\n", 4858 idx, sc->calibcmd[idx].len)); 4859 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4860 sc->calibcmd[idx].len, 0); 4861 if (error != 0) { 4862 aprint_error_dev(sc->sc_dev, 4863 "could not send calibration result\n"); 4864 return error; 4865 } 4866 } 4867 return 0; 4868 } 4869 4870 static int 4871 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4872 { 4873 struct iwn5000_wimax_coex wimax; 4874 4875 #ifdef notyet 4876 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4877 /* Enable WiMAX coexistence for combo adapters. */ 4878 wimax.flags = 4879 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4880 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4881 IWN_WIMAX_COEX_STA_TABLE_VALID | 4882 IWN_WIMAX_COEX_ENABLE; 4883 memcpy(wimax.events, iwn6050_wimax_events, 4884 sizeof iwn6050_wimax_events); 4885 } else 4886 #endif 4887 { 4888 /* Disable WiMAX coexistence. */ 4889 wimax.flags = 0; 4890 memset(wimax.events, 0, sizeof wimax.events); 4891 } 4892 DPRINTF(("Configuring WiMAX coexistence\n")); 4893 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4894 } 4895 4896 /* 4897 * This function is called after the runtime firmware notifies us of its 4898 * readiness (called in a process context). 4899 */ 4900 static int 4901 iwn4965_post_alive(struct iwn_softc *sc) 4902 { 4903 int error, qid; 4904 4905 if ((error = iwn_nic_lock(sc)) != 0) 4906 return error; 4907 4908 /* Clear TX scheduler state in SRAM. */ 4909 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4910 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 4911 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 4912 4913 /* Set physical address of TX scheduler rings (1KB aligned). */ 4914 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4915 4916 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4917 4918 /* Disable chain mode for all our 16 queues. */ 4919 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 4920 4921 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 4922 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 4923 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4924 4925 /* Set scheduler window size. */ 4926 iwn_mem_write(sc, sc->sched_base + 4927 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 4928 /* Set scheduler frame limit. */ 4929 iwn_mem_write(sc, sc->sched_base + 4930 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4931 IWN_SCHED_LIMIT << 16); 4932 } 4933 4934 /* Enable interrupts for all our 16 queues. */ 4935 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 4936 /* Identify TX FIFO rings (0-7). */ 4937 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 4938 4939 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4940 for (qid = 0; qid < 7; qid++) { 4941 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 4942 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4943 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 4944 } 4945 iwn_nic_unlock(sc); 4946 return 0; 4947 } 4948 4949 /* 4950 * This function is called after the initialization or runtime firmware 4951 * notifies us of its readiness (called in a process context). 4952 */ 4953 static int 4954 iwn5000_post_alive(struct iwn_softc *sc) 4955 { 4956 int error, qid; 4957 4958 /* Switch to using ICT interrupt mode. */ 4959 iwn5000_ict_reset(sc); 4960 4961 if ((error = iwn_nic_lock(sc)) != 0) 4962 return error; 4963 4964 /* Clear TX scheduler state in SRAM. */ 4965 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 4966 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 4967 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 4968 4969 /* Set physical address of TX scheduler rings (1KB aligned). */ 4970 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 4971 4972 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 4973 4974 /* Enable chain mode for all queues, except command queue. */ 4975 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 4976 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 4977 4978 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 4979 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 4980 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 4981 4982 iwn_mem_write(sc, sc->sched_base + 4983 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 4984 /* Set scheduler window size and frame limit. */ 4985 iwn_mem_write(sc, sc->sched_base + 4986 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4987 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4988 } 4989 4990 /* Enable interrupts for all our 20 queues. */ 4991 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 4992 /* Identify TX FIFO rings (0-7). */ 4993 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 4994 4995 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 4996 for (qid = 0; qid < 7; qid++) { 4997 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 4998 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4999 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5000 } 5001 iwn_nic_unlock(sc); 5002 5003 /* Configure WiMAX coexistence for combo adapters. */ 5004 error = iwn5000_send_wimax_coex(sc); 5005 if (error != 0) { 5006 aprint_error_dev(sc->sc_dev, 5007 "could not configure WiMAX coexistence\n"); 5008 return error; 5009 } 5010 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5011 struct iwn5000_phy_calib_crystal cmd; 5012 5013 /* Perform crystal calibration. */ 5014 memset(&cmd, 0, sizeof cmd); 5015 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5016 cmd.ngroups = 1; 5017 cmd.isvalid = 1; 5018 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5019 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5020 DPRINTF(("sending crystal calibration %d, %d\n", 5021 cmd.cap_pin[0], cmd.cap_pin[1])); 5022 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5023 if (error != 0) { 5024 aprint_error_dev(sc->sc_dev, 5025 "crystal calibration failed\n"); 5026 return error; 5027 } 5028 } 5029 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5030 /* Query calibration from the initialization firmware. */ 5031 if ((error = iwn5000_query_calibration(sc)) != 0) { 5032 aprint_error_dev(sc->sc_dev, 5033 "could not query calibration\n"); 5034 return error; 5035 } 5036 /* 5037 * We have the calibration results now, reboot with the 5038 * runtime firmware (call ourselves recursively!) 5039 */ 5040 iwn_hw_stop(sc); 5041 error = iwn_hw_init(sc); 5042 } else { 5043 /* Send calibration results to runtime firmware. */ 5044 error = iwn5000_send_calibration(sc); 5045 } 5046 return error; 5047 } 5048 5049 /* 5050 * The firmware boot code is small and is intended to be copied directly into 5051 * the NIC internal memory (no DMA transfer). 5052 */ 5053 static int 5054 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5055 { 5056 int error, ntries; 5057 5058 size /= sizeof (uint32_t); 5059 5060 if ((error = iwn_nic_lock(sc)) != 0) 5061 return error; 5062 5063 /* Copy microcode image into NIC memory. */ 5064 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5065 (const uint32_t *)ucode, size); 5066 5067 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5068 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5069 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5070 5071 /* Start boot load now. */ 5072 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5073 5074 /* Wait for transfer to complete. */ 5075 for (ntries = 0; ntries < 1000; ntries++) { 5076 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5077 IWN_BSM_WR_CTRL_START)) 5078 break; 5079 DELAY(10); 5080 } 5081 if (ntries == 1000) { 5082 aprint_error_dev(sc->sc_dev, 5083 "could not load boot firmware\n"); 5084 iwn_nic_unlock(sc); 5085 return ETIMEDOUT; 5086 } 5087 5088 /* Enable boot after power up. */ 5089 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5090 5091 iwn_nic_unlock(sc); 5092 return 0; 5093 } 5094 5095 static int 5096 iwn4965_load_firmware(struct iwn_softc *sc) 5097 { 5098 struct iwn_fw_info *fw = &sc->fw; 5099 struct iwn_dma_info *dma = &sc->fw_dma; 5100 int error; 5101 5102 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5103 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5104 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5105 BUS_DMASYNC_PREWRITE); 5106 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5107 fw->init.text, fw->init.textsz); 5108 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5109 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5110 5111 /* Tell adapter where to find initialization sections. */ 5112 if ((error = iwn_nic_lock(sc)) != 0) 5113 return error; 5114 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5115 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5116 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5117 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5118 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5119 iwn_nic_unlock(sc); 5120 5121 /* Load firmware boot code. */ 5122 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5123 if (error != 0) { 5124 aprint_error_dev(sc->sc_dev, 5125 "could not load boot firmware\n"); 5126 return error; 5127 } 5128 /* Now press "execute". */ 5129 IWN_WRITE(sc, IWN_RESET, 0); 5130 5131 /* Wait at most one second for first alive notification. */ 5132 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5133 aprint_error_dev(sc->sc_dev, 5134 "timeout waiting for adapter to initialize\n"); 5135 return error; 5136 } 5137 5138 /* Retrieve current temperature for initial TX power calibration. */ 5139 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5140 sc->temp = iwn4965_get_temperature(sc); 5141 5142 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5143 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5144 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5145 BUS_DMASYNC_PREWRITE); 5146 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5147 fw->main.text, fw->main.textsz); 5148 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5149 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5150 5151 /* Tell adapter where to find runtime sections. */ 5152 if ((error = iwn_nic_lock(sc)) != 0) 5153 return error; 5154 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5155 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5156 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5157 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5158 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5159 IWN_FW_UPDATED | fw->main.textsz); 5160 iwn_nic_unlock(sc); 5161 5162 return 0; 5163 } 5164 5165 static int 5166 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5167 const uint8_t *section, int size) 5168 { 5169 struct iwn_dma_info *dma = &sc->fw_dma; 5170 int error; 5171 5172 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5173 memcpy(dma->vaddr, section, size); 5174 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5175 5176 if ((error = iwn_nic_lock(sc)) != 0) 5177 return error; 5178 5179 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5180 IWN_FH_TX_CONFIG_DMA_PAUSE); 5181 5182 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5183 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5184 IWN_LOADDR(dma->paddr)); 5185 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5186 IWN_HIADDR(dma->paddr) << 28 | size); 5187 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5188 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5189 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5190 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5191 5192 /* Kick Flow Handler to start DMA transfer. */ 5193 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5194 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5195 5196 iwn_nic_unlock(sc); 5197 5198 /* Wait at most five seconds for FH DMA transfer to complete. */ 5199 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5200 } 5201 5202 static int 5203 iwn5000_load_firmware(struct iwn_softc *sc) 5204 { 5205 struct iwn_fw_part *fw; 5206 int error; 5207 5208 /* Load the initialization firmware on first boot only. */ 5209 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5210 &sc->fw.main : &sc->fw.init; 5211 5212 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5213 fw->text, fw->textsz); 5214 if (error != 0) { 5215 aprint_error_dev(sc->sc_dev, 5216 "could not load firmware %s section\n", ".text"); 5217 return error; 5218 } 5219 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5220 fw->data, fw->datasz); 5221 if (error != 0) { 5222 aprint_error_dev(sc->sc_dev, 5223 "could not load firmware %s section\n", ".data"); 5224 return error; 5225 } 5226 5227 /* Now press "execute". */ 5228 IWN_WRITE(sc, IWN_RESET, 0); 5229 return 0; 5230 } 5231 5232 /* 5233 * Extract text and data sections from a legacy firmware image. 5234 */ 5235 static int 5236 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5237 { 5238 const uint32_t *ptr; 5239 size_t hdrlen = 24; 5240 uint32_t rev; 5241 5242 ptr = (const uint32_t *)fw->data; 5243 rev = le32toh(*ptr++); 5244 5245 /* Check firmware API version. */ 5246 if (IWN_FW_API(rev) <= 1) { 5247 aprint_error_dev(sc->sc_dev, 5248 "bad firmware, need API version >=2\n"); 5249 return EINVAL; 5250 } 5251 if (IWN_FW_API(rev) >= 3) { 5252 /* Skip build number (version 2 header). */ 5253 hdrlen += 4; 5254 ptr++; 5255 } 5256 if (fw->size < hdrlen) { 5257 aprint_error_dev(sc->sc_dev, 5258 "firmware too short: %zd bytes\n", fw->size); 5259 return EINVAL; 5260 } 5261 fw->main.textsz = le32toh(*ptr++); 5262 fw->main.datasz = le32toh(*ptr++); 5263 fw->init.textsz = le32toh(*ptr++); 5264 fw->init.datasz = le32toh(*ptr++); 5265 fw->boot.textsz = le32toh(*ptr++); 5266 5267 /* Check that all firmware sections fit. */ 5268 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5269 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5270 aprint_error_dev(sc->sc_dev, 5271 "firmware too short: %zd bytes\n", fw->size); 5272 return EINVAL; 5273 } 5274 5275 /* Get pointers to firmware sections. */ 5276 fw->main.text = (const uint8_t *)ptr; 5277 fw->main.data = fw->main.text + fw->main.textsz; 5278 fw->init.text = fw->main.data + fw->main.datasz; 5279 fw->init.data = fw->init.text + fw->init.textsz; 5280 fw->boot.text = fw->init.data + fw->init.datasz; 5281 return 0; 5282 } 5283 5284 /* 5285 * Extract text and data sections from a TLV firmware image. 5286 */ 5287 static int 5288 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5289 uint16_t alt) 5290 { 5291 const struct iwn_fw_tlv_hdr *hdr; 5292 const struct iwn_fw_tlv *tlv; 5293 const uint8_t *ptr, *end; 5294 uint64_t altmask; 5295 uint32_t len; 5296 5297 if (fw->size < sizeof (*hdr)) { 5298 aprint_error_dev(sc->sc_dev, 5299 "firmware too short: %zd bytes\n", fw->size); 5300 return EINVAL; 5301 } 5302 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5303 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5304 aprint_error_dev(sc->sc_dev, 5305 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5306 return EINVAL; 5307 } 5308 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5309 le32toh(hdr->build))); 5310 5311 /* 5312 * Select the closest supported alternative that is less than 5313 * or equal to the specified one. 5314 */ 5315 altmask = le64toh(hdr->altmask); 5316 while (alt > 0 && !(altmask & (1ULL << alt))) 5317 alt--; /* Downgrade. */ 5318 DPRINTF(("using alternative %d\n", alt)); 5319 5320 ptr = (const uint8_t *)(hdr + 1); 5321 end = (const uint8_t *)(fw->data + fw->size); 5322 5323 /* Parse type-length-value fields. */ 5324 while (ptr + sizeof (*tlv) <= end) { 5325 tlv = (const struct iwn_fw_tlv *)ptr; 5326 len = le32toh(tlv->len); 5327 5328 ptr += sizeof (*tlv); 5329 if (ptr + len > end) { 5330 aprint_error_dev(sc->sc_dev, 5331 "firmware too short: %zd bytes\n", fw->size); 5332 return EINVAL; 5333 } 5334 /* Skip other alternatives. */ 5335 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5336 goto next; 5337 5338 switch (le16toh(tlv->type)) { 5339 case IWN_FW_TLV_MAIN_TEXT: 5340 fw->main.text = ptr; 5341 fw->main.textsz = len; 5342 break; 5343 case IWN_FW_TLV_MAIN_DATA: 5344 fw->main.data = ptr; 5345 fw->main.datasz = len; 5346 break; 5347 case IWN_FW_TLV_INIT_TEXT: 5348 fw->init.text = ptr; 5349 fw->init.textsz = len; 5350 break; 5351 case IWN_FW_TLV_INIT_DATA: 5352 fw->init.data = ptr; 5353 fw->init.datasz = len; 5354 break; 5355 case IWN_FW_TLV_BOOT_TEXT: 5356 fw->boot.text = ptr; 5357 fw->boot.textsz = len; 5358 break; 5359 default: 5360 DPRINTF(("TLV type %d not handled\n", 5361 le16toh(tlv->type))); 5362 break; 5363 } 5364 next: /* TLV fields are 32-bit aligned. */ 5365 ptr += (len + 3) & ~3; 5366 } 5367 return 0; 5368 } 5369 5370 static int 5371 iwn_read_firmware(struct iwn_softc *sc) 5372 { 5373 struct iwn_fw_info *fw = &sc->fw; 5374 firmware_handle_t fwh; 5375 int error; 5376 5377 /* Initialize for error returns */ 5378 fw->data = NULL; 5379 fw->size = 0; 5380 5381 /* Open firmware image. */ 5382 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5383 aprint_error_dev(sc->sc_dev, 5384 "could not get firmware handle %s\n", sc->fwname); 5385 return error; 5386 } 5387 fw->size = firmware_get_size(fwh); 5388 if (fw->size < sizeof (uint32_t)) { 5389 aprint_error_dev(sc->sc_dev, 5390 "firmware too short: %zd bytes\n", fw->size); 5391 firmware_close(fwh); 5392 return EINVAL; 5393 } 5394 5395 /* Read the firmware. */ 5396 fw->data = firmware_malloc(fw->size); 5397 if (fw->data == NULL) { 5398 aprint_error_dev(sc->sc_dev, 5399 "not enough memory to stock firmware %s\n", sc->fwname); 5400 firmware_close(fwh); 5401 return ENOMEM; 5402 } 5403 error = firmware_read(fwh, 0, fw->data, fw->size); 5404 firmware_close(fwh); 5405 if (error != 0) { 5406 aprint_error_dev(sc->sc_dev, 5407 "could not read firmware %s\n", sc->fwname); 5408 goto out; 5409 } 5410 5411 /* Retrieve text and data sections. */ 5412 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5413 error = iwn_read_firmware_leg(sc, fw); 5414 else 5415 error = iwn_read_firmware_tlv(sc, fw, 1); 5416 if (error != 0) { 5417 aprint_error_dev(sc->sc_dev, 5418 "could not read firmware sections\n"); 5419 goto out; 5420 } 5421 5422 /* Make sure text and data sections fit in hardware memory. */ 5423 if (fw->main.textsz > sc->fw_text_maxsz || 5424 fw->main.datasz > sc->fw_data_maxsz || 5425 fw->init.textsz > sc->fw_text_maxsz || 5426 fw->init.datasz > sc->fw_data_maxsz || 5427 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5428 (fw->boot.textsz & 3) != 0) { 5429 aprint_error_dev(sc->sc_dev, 5430 "firmware sections too large\n"); 5431 goto out; 5432 } 5433 5434 /* We can proceed with loading the firmware. */ 5435 return 0; 5436 out: 5437 firmware_free(fw->data, fw->size); 5438 fw->data = NULL; 5439 fw->size = 0; 5440 return error ? error : EINVAL; 5441 } 5442 5443 static int 5444 iwn_clock_wait(struct iwn_softc *sc) 5445 { 5446 int ntries; 5447 5448 /* Set "initialization complete" bit. */ 5449 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5450 5451 /* Wait for clock stabilization. */ 5452 for (ntries = 0; ntries < 2500; ntries++) { 5453 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5454 return 0; 5455 DELAY(10); 5456 } 5457 aprint_error_dev(sc->sc_dev, 5458 "timeout waiting for clock stabilization\n"); 5459 return ETIMEDOUT; 5460 } 5461 5462 static int 5463 iwn_apm_init(struct iwn_softc *sc) 5464 { 5465 pcireg_t reg; 5466 int error; 5467 5468 /* Disable L0s exit timer (NMI bug workaround). */ 5469 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5470 /* Don't wait for ICH L0s (ICH bug workaround). */ 5471 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5472 5473 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5474 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5475 5476 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5477 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5478 5479 /* Retrieve PCIe Active State Power Management (ASPM). */ 5480 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5481 sc->sc_cap_off + PCI_PCIE_LCSR); 5482 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5483 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5484 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5485 else 5486 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5487 5488 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5489 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5490 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5491 5492 /* Wait for clock stabilization before accessing prph. */ 5493 if ((error = iwn_clock_wait(sc)) != 0) 5494 return error; 5495 5496 if ((error = iwn_nic_lock(sc)) != 0) 5497 return error; 5498 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5499 /* Enable DMA and BSM (Bootstrap State Machine). */ 5500 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5501 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5502 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5503 } else { 5504 /* Enable DMA. */ 5505 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5506 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5507 } 5508 DELAY(20); 5509 /* Disable L1-Active. */ 5510 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5511 iwn_nic_unlock(sc); 5512 5513 return 0; 5514 } 5515 5516 static void 5517 iwn_apm_stop_master(struct iwn_softc *sc) 5518 { 5519 int ntries; 5520 5521 /* Stop busmaster DMA activity. */ 5522 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5523 for (ntries = 0; ntries < 100; ntries++) { 5524 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5525 return; 5526 DELAY(10); 5527 } 5528 aprint_error_dev(sc->sc_dev, 5529 "timeout waiting for master\n"); 5530 } 5531 5532 static void 5533 iwn_apm_stop(struct iwn_softc *sc) 5534 { 5535 iwn_apm_stop_master(sc); 5536 5537 /* Reset the entire device. */ 5538 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5539 DELAY(10); 5540 /* Clear "initialization complete" bit. */ 5541 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5542 } 5543 5544 static int 5545 iwn4965_nic_config(struct iwn_softc *sc) 5546 { 5547 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5548 /* 5549 * I don't believe this to be correct but this is what the 5550 * vendor driver is doing. Probably the bits should not be 5551 * shifted in IWN_RFCFG_*. 5552 */ 5553 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5554 IWN_RFCFG_TYPE(sc->rfcfg) | 5555 IWN_RFCFG_STEP(sc->rfcfg) | 5556 IWN_RFCFG_DASH(sc->rfcfg)); 5557 } 5558 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5559 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5560 return 0; 5561 } 5562 5563 static int 5564 iwn5000_nic_config(struct iwn_softc *sc) 5565 { 5566 uint32_t tmp; 5567 int error; 5568 5569 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5570 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5571 IWN_RFCFG_TYPE(sc->rfcfg) | 5572 IWN_RFCFG_STEP(sc->rfcfg) | 5573 IWN_RFCFG_DASH(sc->rfcfg)); 5574 } 5575 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5576 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5577 5578 if ((error = iwn_nic_lock(sc)) != 0) 5579 return error; 5580 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5581 5582 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5583 /* 5584 * Select first Switching Voltage Regulator (1.32V) to 5585 * solve a stability issue related to noisy DC2DC line 5586 * in the silicon of 1000 Series. 5587 */ 5588 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5589 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5590 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5591 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5592 } 5593 iwn_nic_unlock(sc); 5594 5595 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5596 /* Use internal power amplifier only. */ 5597 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5598 } 5599 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 5600 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 5601 /* Indicate that ROM calibration version is >=6. */ 5602 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5603 } 5604 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 5605 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 5606 return 0; 5607 } 5608 5609 /* 5610 * Take NIC ownership over Intel Active Management Technology (AMT). 5611 */ 5612 static int 5613 iwn_hw_prepare(struct iwn_softc *sc) 5614 { 5615 int ntries; 5616 5617 /* Check if hardware is ready. */ 5618 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5619 for (ntries = 0; ntries < 5; ntries++) { 5620 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5621 IWN_HW_IF_CONFIG_NIC_READY) 5622 return 0; 5623 DELAY(10); 5624 } 5625 5626 /* Hardware not ready, force into ready state. */ 5627 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5628 for (ntries = 0; ntries < 15000; ntries++) { 5629 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5630 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5631 break; 5632 DELAY(10); 5633 } 5634 if (ntries == 15000) 5635 return ETIMEDOUT; 5636 5637 /* Hardware should be ready now. */ 5638 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5639 for (ntries = 0; ntries < 5; ntries++) { 5640 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5641 IWN_HW_IF_CONFIG_NIC_READY) 5642 return 0; 5643 DELAY(10); 5644 } 5645 return ETIMEDOUT; 5646 } 5647 5648 static int 5649 iwn_hw_init(struct iwn_softc *sc) 5650 { 5651 struct iwn_ops *ops = &sc->ops; 5652 int error, chnl, qid; 5653 5654 /* Clear pending interrupts. */ 5655 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5656 5657 if ((error = iwn_apm_init(sc)) != 0) { 5658 aprint_error_dev(sc->sc_dev, 5659 "could not power ON adapter\n"); 5660 return error; 5661 } 5662 5663 /* Select VMAIN power source. */ 5664 if ((error = iwn_nic_lock(sc)) != 0) 5665 return error; 5666 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5667 iwn_nic_unlock(sc); 5668 5669 /* Perform adapter-specific initialization. */ 5670 if ((error = ops->nic_config(sc)) != 0) 5671 return error; 5672 5673 /* Initialize RX ring. */ 5674 if ((error = iwn_nic_lock(sc)) != 0) 5675 return error; 5676 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5677 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5678 /* Set physical address of RX ring (256-byte aligned). */ 5679 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5680 /* Set physical address of RX status (16-byte aligned). */ 5681 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5682 /* Enable RX. */ 5683 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5684 IWN_FH_RX_CONFIG_ENA | 5685 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5686 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5687 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5688 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5689 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5690 iwn_nic_unlock(sc); 5691 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5692 5693 if ((error = iwn_nic_lock(sc)) != 0) 5694 return error; 5695 5696 /* Initialize TX scheduler. */ 5697 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5698 5699 /* Set physical address of "keep warm" page (16-byte aligned). */ 5700 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5701 5702 /* Initialize TX rings. */ 5703 for (qid = 0; qid < sc->ntxqs; qid++) { 5704 struct iwn_tx_ring *txq = &sc->txq[qid]; 5705 5706 /* Set physical address of TX ring (256-byte aligned). */ 5707 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5708 txq->desc_dma.paddr >> 8); 5709 } 5710 iwn_nic_unlock(sc); 5711 5712 /* Enable DMA channels. */ 5713 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5714 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5715 IWN_FH_TX_CONFIG_DMA_ENA | 5716 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5717 } 5718 5719 /* Clear "radio off" and "commands blocked" bits. */ 5720 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5721 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5722 5723 /* Clear pending interrupts. */ 5724 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5725 /* Enable interrupt coalescing. */ 5726 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5727 /* Enable interrupts. */ 5728 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5729 5730 /* _Really_ make sure "radio off" bit is cleared! */ 5731 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5732 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5733 5734 /* Enable shadow registers. */ 5735 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 5736 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 5737 5738 if ((error = ops->load_firmware(sc)) != 0) { 5739 aprint_error_dev(sc->sc_dev, 5740 "could not load firmware\n"); 5741 return error; 5742 } 5743 /* Wait at most one second for firmware alive notification. */ 5744 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5745 aprint_error_dev(sc->sc_dev, 5746 "timeout waiting for adapter to initialize\n"); 5747 return error; 5748 } 5749 /* Do post-firmware initialization. */ 5750 return ops->post_alive(sc); 5751 } 5752 5753 static void 5754 iwn_hw_stop(struct iwn_softc *sc) 5755 { 5756 int chnl, qid, ntries; 5757 5758 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5759 5760 /* Disable interrupts. */ 5761 IWN_WRITE(sc, IWN_INT_MASK, 0); 5762 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5763 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5764 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5765 5766 /* Make sure we no longer hold the NIC lock. */ 5767 iwn_nic_unlock(sc); 5768 5769 /* Stop TX scheduler. */ 5770 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5771 5772 /* Stop all DMA channels. */ 5773 if (iwn_nic_lock(sc) == 0) { 5774 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5775 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5776 for (ntries = 0; ntries < 200; ntries++) { 5777 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 5778 IWN_FH_TX_STATUS_IDLE(chnl)) 5779 break; 5780 DELAY(10); 5781 } 5782 } 5783 iwn_nic_unlock(sc); 5784 } 5785 5786 /* Stop RX ring. */ 5787 iwn_reset_rx_ring(sc, &sc->rxq); 5788 5789 /* Reset all TX rings. */ 5790 for (qid = 0; qid < sc->ntxqs; qid++) 5791 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5792 5793 if (iwn_nic_lock(sc) == 0) { 5794 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5795 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5796 iwn_nic_unlock(sc); 5797 } 5798 DELAY(5); 5799 /* Power OFF adapter. */ 5800 iwn_apm_stop(sc); 5801 } 5802 5803 static int 5804 iwn_init(struct ifnet *ifp) 5805 { 5806 struct iwn_softc *sc = ifp->if_softc; 5807 struct ieee80211com *ic = &sc->sc_ic; 5808 int error; 5809 5810 mutex_enter(&sc->sc_mtx); 5811 if (sc->sc_flags & IWN_FLAG_HW_INITED) 5812 goto out; 5813 if ((error = iwn_hw_prepare(sc)) != 0) { 5814 aprint_error_dev(sc->sc_dev, 5815 "hardware not ready\n"); 5816 goto fail; 5817 } 5818 5819 /* Check that the radio is not disabled by hardware switch. */ 5820 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5821 aprint_error_dev(sc->sc_dev, 5822 "radio is disabled by hardware switch\n"); 5823 error = EPERM; /* :-) */ 5824 goto fail; 5825 } 5826 5827 /* Read firmware images from the filesystem. */ 5828 if ((error = iwn_read_firmware(sc)) != 0) { 5829 aprint_error_dev(sc->sc_dev, 5830 "could not read firmware\n"); 5831 goto fail; 5832 } 5833 5834 /* Initialize interrupt mask to default value. */ 5835 sc->int_mask = IWN_INT_MASK_DEF; 5836 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5837 5838 /* Initialize hardware and upload firmware. */ 5839 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 5840 error = iwn_hw_init(sc); 5841 firmware_free(sc->fw.data, sc->fw.size); 5842 sc->fw.data = NULL; 5843 sc->fw.size = 0; 5844 if (error != 0) { 5845 aprint_error_dev(sc->sc_dev, 5846 "could not initialize hardware\n"); 5847 goto fail; 5848 } 5849 5850 /* Configure adapter now that it is ready. */ 5851 if ((error = iwn_config(sc)) != 0) { 5852 aprint_error_dev(sc->sc_dev, 5853 "could not configure device\n"); 5854 goto fail; 5855 } 5856 5857 ifp->if_flags &= ~IFF_OACTIVE; 5858 ifp->if_flags |= IFF_RUNNING; 5859 5860 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5861 ieee80211_begin_scan(ic, 0); 5862 else 5863 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5864 5865 sc->sc_flags |= IWN_FLAG_HW_INITED; 5866 out: 5867 mutex_exit(&sc->sc_mtx); 5868 return 0; 5869 5870 fail: mutex_exit(&sc->sc_mtx); 5871 iwn_stop(ifp, 1); 5872 return error; 5873 } 5874 5875 static void 5876 iwn_stop(struct ifnet *ifp, int disable) 5877 { 5878 struct iwn_softc *sc = ifp->if_softc; 5879 struct ieee80211com *ic = &sc->sc_ic; 5880 5881 if (!disable) 5882 mutex_enter(&sc->sc_mtx); 5883 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 5884 ifp->if_timer = sc->sc_tx_timer = 0; 5885 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5886 5887 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5888 5889 /* Power OFF hardware. */ 5890 iwn_hw_stop(sc); 5891 5892 if (!disable) 5893 mutex_exit(&sc->sc_mtx); 5894 } 5895 5896 /* 5897 * XXX MCLGETI alternative 5898 * 5899 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5900 * as long as there are available free buffers then it uses MEXTMALLOC., 5901 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5902 * The MCLGET4K code is used for testing an alternative mbuf cache. 5903 */ 5904 5905 static struct mbuf * 5906 MCLGETIalt(struct iwn_softc *sc, int how, 5907 struct ifnet *ifp __unused, u_int size) 5908 { 5909 struct mbuf *m; 5910 #ifdef IWN_USE_RBUF 5911 struct iwn_rbuf *rbuf; 5912 #endif 5913 5914 MGETHDR(m, how, MT_DATA); 5915 if (m == NULL) 5916 return NULL; 5917 5918 #ifdef IWN_USE_RBUF 5919 if (sc->rxq.nb_free_entries > 0 && 5920 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 5921 /* Attach buffer to mbuf header. */ 5922 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 5923 m->m_flags |= M_EXT_RW; 5924 } 5925 else { 5926 MEXTMALLOC(m, size, how); 5927 if ((m->m_flags & M_EXT) == 0) { 5928 m_freem(m); 5929 return NULL; 5930 } 5931 } 5932 5933 #else 5934 #ifdef MCLGET4K 5935 if (size == 4096) 5936 MCLGET4K(m, how); 5937 else 5938 panic("size must be 4k"); 5939 #else 5940 MEXTMALLOC(m, size, how); 5941 #endif 5942 if ((m->m_flags & M_EXT) == 0) { 5943 m_freem(m); 5944 return NULL; 5945 } 5946 #endif 5947 5948 return m; 5949 } 5950 5951 #ifdef IWN_USE_RBUF 5952 static struct iwn_rbuf * 5953 iwn_alloc_rbuf(struct iwn_softc *sc) 5954 { 5955 struct iwn_rbuf *rbuf; 5956 mutex_enter(&sc->rxq.freelist_mtx); 5957 5958 rbuf = SLIST_FIRST(&sc->rxq.freelist); 5959 if (rbuf != NULL) { 5960 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 5961 sc->rxq.nb_free_entries --; 5962 } 5963 mutex_exit(&sc->rxq.freelist_mtx); 5964 return rbuf; 5965 } 5966 5967 /* 5968 * This is called automatically by the network stack when the mbuf to which 5969 * our RX buffer is attached is freed. 5970 */ 5971 static void 5972 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 5973 { 5974 struct iwn_rbuf *rbuf = arg; 5975 struct iwn_softc *sc = rbuf->sc; 5976 5977 /* Put the RX buffer back in the free list. */ 5978 mutex_enter(&sc->rxq.freelist_mtx); 5979 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 5980 mutex_exit(&sc->rxq.freelist_mtx); 5981 5982 sc->rxq.nb_free_entries ++; 5983 if (__predict_true(m != NULL)) 5984 pool_cache_put(mb_cache, m); 5985 } 5986 5987 static int 5988 iwn_alloc_rpool(struct iwn_softc *sc) 5989 { 5990 struct iwn_rx_ring *ring = &sc->rxq; 5991 struct iwn_rbuf *rbuf; 5992 int i, error; 5993 5994 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 5995 5996 /* Allocate a big chunk of DMA'able memory... */ 5997 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 5998 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 5999 if (error != 0) { 6000 aprint_error_dev(sc->sc_dev, 6001 "could not allocate RX buffers DMA memory\n"); 6002 return error; 6003 } 6004 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6005 SLIST_INIT(&ring->freelist); 6006 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6007 rbuf = &ring->rbuf[i]; 6008 6009 rbuf->sc = sc; /* Backpointer for callbacks. */ 6010 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6011 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6012 6013 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6014 } 6015 ring->nb_free_entries = IWN_RBUF_COUNT; 6016 return 0; 6017 } 6018 6019 static void 6020 iwn_free_rpool(struct iwn_softc *sc) 6021 { 6022 iwn_dma_contig_free(&sc->rxq.buf_dma); 6023 } 6024 #endif 6025 6026 /* 6027 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6028 * Copyright (c) 2001 Atsushi Onoe 6029 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6030 * Copyright (c) 2007-2009 Damien Bergamini 6031 * All rights reserved. 6032 */ 6033 6034 /* 6035 * Add an SSID element to a frame (see 7.3.2.1). 6036 */ 6037 static u_int8_t * 6038 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6039 { 6040 *frm++ = IEEE80211_ELEMID_SSID; 6041 *frm++ = len; 6042 memcpy(frm, ssid, len); 6043 return frm + len; 6044 } 6045 6046 /* 6047 * Add a supported rates element to a frame (see 7.3.2.2). 6048 */ 6049 static u_int8_t * 6050 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6051 { 6052 int nrates; 6053 6054 *frm++ = IEEE80211_ELEMID_RATES; 6055 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6056 *frm++ = nrates; 6057 memcpy(frm, rs->rs_rates, nrates); 6058 return frm + nrates; 6059 } 6060 6061 /* 6062 * Add an extended supported rates element to a frame (see 7.3.2.14). 6063 */ 6064 static u_int8_t * 6065 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6066 { 6067 int nrates; 6068 6069 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6070 6071 *frm++ = IEEE80211_ELEMID_XRATES; 6072 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6073 *frm++ = nrates; 6074 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6075 return frm + nrates; 6076 } 6077 6078 /* 6079 * XXX: Hack to set the current channel to the value advertised in beacons or 6080 * probe responses. Only used during AP detection. 6081 * XXX: Duplicated from if_iwi.c 6082 */ 6083 static void 6084 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m, 6085 struct iwn_rx_stat *stat) 6086 { 6087 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6088 struct ieee80211_frame *wh; 6089 uint8_t subtype; 6090 uint8_t *frm, *efrm; 6091 6092 wh = mtod(m, struct ieee80211_frame *); 6093 6094 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6095 return; 6096 6097 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6098 6099 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6100 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6101 return; 6102 6103 if (sc->sc_flags & IWN_FLAG_SCANNING_5GHZ) { 6104 int chan = le16toh(stat->chan); 6105 if (chan < __arraycount(ic->ic_channels)) 6106 ic->ic_curchan = &ic->ic_channels[chan]; 6107 return; 6108 } 6109 6110 frm = (uint8_t *)(wh + 1); 6111 efrm = mtod(m, uint8_t *) + m->m_len; 6112 6113 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6114 while (frm < efrm) { 6115 if (*frm == IEEE80211_ELEMID_DSPARMS) 6116 #if IEEE80211_CHAN_MAX < 255 6117 if (frm[2] <= IEEE80211_CHAN_MAX) 6118 #endif 6119 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6120 6121 frm += frm[1] + 2; 6122 } 6123 } 6124 6125
Indexes created Thu Oct 02 14:10:14 GMT 2025