if_iwn.c revision 1.68
1 /* $NetBSD: if_iwn.c,v 1.68 2013/08/23 16:49:53 christos Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.119 2013/05/29 23:16:52 yuo Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.68 2013/08/23 16:49:53 christos Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #ifdef notyetMODULE 39 #include <sys/module.h> 40 #endif 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <sys/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 106 }; 107 108 /* 109 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 110 */ 111 static const struct ieee80211_rateset iwn_rateset_11a = 112 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 113 114 static const struct ieee80211_rateset iwn_rateset_11b = 115 { 4, { 2, 4, 11, 22 } }; 116 117 static const struct ieee80211_rateset iwn_rateset_11g = 118 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 119 120 static int iwn_match(device_t , struct cfdata *, void *); 121 static void iwn_attach(device_t , device_t , void *); 122 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 123 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 124 static void iwn_radiotap_attach(struct iwn_softc *); 125 static int iwn_detach(device_t , int); 126 #if 0 127 static void iwn_power(int, void *); 128 #endif 129 static bool iwn_resume(device_t, const pmf_qual_t *); 130 static int iwn_nic_lock(struct iwn_softc *); 131 static int iwn_eeprom_lock(struct iwn_softc *); 132 static int iwn_init_otprom(struct iwn_softc *); 133 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 134 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 135 void **, bus_size_t, bus_size_t); 136 static void iwn_dma_contig_free(struct iwn_dma_info *); 137 static int iwn_alloc_sched(struct iwn_softc *); 138 static void iwn_free_sched(struct iwn_softc *); 139 static int iwn_alloc_kw(struct iwn_softc *); 140 static void iwn_free_kw(struct iwn_softc *); 141 static int iwn_alloc_ict(struct iwn_softc *); 142 static void iwn_free_ict(struct iwn_softc *); 143 static int iwn_alloc_fwmem(struct iwn_softc *); 144 static void iwn_free_fwmem(struct iwn_softc *); 145 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 146 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 147 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 148 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 149 int); 150 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 151 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 152 static void iwn5000_ict_reset(struct iwn_softc *); 153 static int iwn_read_eeprom(struct iwn_softc *); 154 static void iwn4965_read_eeprom(struct iwn_softc *); 155 156 #ifdef IWN_DEBUG 157 static void iwn4965_print_power_group(struct iwn_softc *, int); 158 #endif 159 static void iwn5000_read_eeprom(struct iwn_softc *); 160 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 161 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 162 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 163 static void iwn_newassoc(struct ieee80211_node *, int); 164 static int iwn_media_change(struct ifnet *); 165 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 166 static void iwn_iter_func(void *, struct ieee80211_node *); 167 static void iwn_calib_timeout(void *); 168 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 169 struct iwn_rx_data *); 170 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 171 struct iwn_rx_data *); 172 #ifndef IEEE80211_NO_HT 173 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 174 struct iwn_rx_data *); 175 #endif 176 static void iwn5000_rx_calib_results(struct iwn_softc *, 177 struct iwn_rx_desc *, struct iwn_rx_data *); 178 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 179 struct iwn_rx_data *); 180 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 181 struct iwn_rx_data *); 182 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 183 struct iwn_rx_data *); 184 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 185 uint8_t); 186 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 187 static void iwn_notif_intr(struct iwn_softc *); 188 static void iwn_wakeup_intr(struct iwn_softc *); 189 static void iwn_fatal_intr(struct iwn_softc *); 190 static int iwn_intr(void *); 191 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 192 uint16_t); 193 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 194 uint16_t); 195 #ifdef notyet 196 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 197 #endif 198 static int iwn_tx(struct iwn_softc *, struct mbuf *, 199 struct ieee80211_node *, int); 200 static void iwn_start(struct ifnet *); 201 static void iwn_watchdog(struct ifnet *); 202 static int iwn_ioctl(struct ifnet *, u_long, void *); 203 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 204 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 205 int); 206 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 207 int); 208 static int iwn_set_link_quality(struct iwn_softc *, 209 struct ieee80211_node *); 210 static int iwn_add_broadcast_node(struct iwn_softc *, int); 211 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 212 static int iwn_set_critical_temp(struct iwn_softc *); 213 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 214 static void iwn4965_power_calibration(struct iwn_softc *, int); 215 static int iwn4965_set_txpower(struct iwn_softc *, int); 216 static int iwn5000_set_txpower(struct iwn_softc *, int); 217 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 218 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 219 static int iwn_get_noise(const struct iwn_rx_general_stats *); 220 static int iwn4965_get_temperature(struct iwn_softc *); 221 static int iwn5000_get_temperature(struct iwn_softc *); 222 static int iwn_init_sensitivity(struct iwn_softc *); 223 static void iwn_collect_noise(struct iwn_softc *, 224 const struct iwn_rx_general_stats *); 225 static int iwn4965_init_gains(struct iwn_softc *); 226 static int iwn5000_init_gains(struct iwn_softc *); 227 static int iwn4965_set_gains(struct iwn_softc *); 228 static int iwn5000_set_gains(struct iwn_softc *); 229 static void iwn_tune_sensitivity(struct iwn_softc *, 230 const struct iwn_rx_stats *); 231 static int iwn_send_sensitivity(struct iwn_softc *); 232 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 233 static int iwn5000_runtime_calib(struct iwn_softc *); 234 235 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 236 static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 237 static int iwn_config_bt_coex_adv1(struct iwn_softc *); 238 239 static int iwn_config(struct iwn_softc *); 240 static int iwn_scan(struct iwn_softc *, uint16_t); 241 static int iwn_auth(struct iwn_softc *); 242 static int iwn_run(struct iwn_softc *); 243 #ifdef IWN_HWCRYPTO 244 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 245 struct ieee80211_key *); 246 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 247 struct ieee80211_key *); 248 #endif 249 static int iwn_wme_update(struct ieee80211com *); 250 #ifndef IEEE80211_NO_HT 251 static int iwn_ampdu_rx_start(struct ieee80211com *, 252 struct ieee80211_node *, uint8_t); 253 static void iwn_ampdu_rx_stop(struct ieee80211com *, 254 struct ieee80211_node *, uint8_t); 255 static int iwn_ampdu_tx_start(struct ieee80211com *, 256 struct ieee80211_node *, uint8_t); 257 static void iwn_ampdu_tx_stop(struct ieee80211com *, 258 struct ieee80211_node *, uint8_t); 259 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 260 struct ieee80211_node *, uint8_t, uint16_t); 261 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 262 uint8_t, uint16_t); 263 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 264 struct ieee80211_node *, uint8_t, uint16_t); 265 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 266 uint8_t, uint16_t); 267 #endif 268 static int iwn5000_query_calibration(struct iwn_softc *); 269 static int iwn5000_send_calibration(struct iwn_softc *); 270 static int iwn5000_send_wimax_coex(struct iwn_softc *); 271 static int iwn4965_post_alive(struct iwn_softc *); 272 static int iwn5000_post_alive(struct iwn_softc *); 273 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 274 int); 275 static int iwn4965_load_firmware(struct iwn_softc *); 276 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 277 const uint8_t *, int); 278 static int iwn5000_load_firmware(struct iwn_softc *); 279 static int iwn_read_firmware_leg(struct iwn_softc *, 280 struct iwn_fw_info *); 281 static int iwn_read_firmware_tlv(struct iwn_softc *, 282 struct iwn_fw_info *, uint16_t); 283 static int iwn_read_firmware(struct iwn_softc *); 284 static int iwn_clock_wait(struct iwn_softc *); 285 static int iwn_apm_init(struct iwn_softc *); 286 static void iwn_apm_stop_master(struct iwn_softc *); 287 static void iwn_apm_stop(struct iwn_softc *); 288 static int iwn4965_nic_config(struct iwn_softc *); 289 static int iwn5000_nic_config(struct iwn_softc *); 290 static int iwn_hw_prepare(struct iwn_softc *); 291 static int iwn_hw_init(struct iwn_softc *); 292 static void iwn_hw_stop(struct iwn_softc *); 293 static int iwn_init(struct ifnet *); 294 static void iwn_stop(struct ifnet *, int); 295 296 /* XXX MCLGETI alternative */ 297 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 298 struct ifnet *, u_int); 299 #ifdef IWN_USE_RBUF 300 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 301 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 302 static int iwn_alloc_rpool(struct iwn_softc *); 303 static void iwn_free_rpool(struct iwn_softc *); 304 #endif 305 306 /* XXX needed by iwn_scan */ 307 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 308 static u_int8_t *ieee80211_add_rates(u_int8_t *, 309 const struct ieee80211_rateset *); 310 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 311 const struct ieee80211_rateset *); 312 313 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 314 315 #ifdef IWN_DEBUG 316 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 317 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 318 int iwn_debug = 0; 319 #else 320 #define DPRINTF(x) 321 #define DPRINTFN(n, x) 322 #endif 323 324 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 325 iwn_detach, NULL); 326 327 static int 328 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 329 { 330 struct pci_attach_args *pa = aux; 331 size_t i; 332 333 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 334 return 0; 335 336 for (i = 0; i < __arraycount(iwn_devices); i++) 337 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 338 return 1; 339 340 return 0; 341 } 342 343 static void 344 iwn_attach(device_t parent __unused, device_t self, void *aux) 345 { 346 struct iwn_softc *sc = device_private(self); 347 struct ieee80211com *ic = &sc->sc_ic; 348 struct ifnet *ifp = &sc->sc_ec.ec_if; 349 struct pci_attach_args *pa = aux; 350 const char *intrstr; 351 pci_intr_handle_t ih; 352 pcireg_t memtype, reg; 353 int i, error; 354 355 sc->sc_dev = self; 356 sc->sc_pct = pa->pa_pc; 357 sc->sc_pcitag = pa->pa_tag; 358 sc->sc_dmat = pa->pa_dmat; 359 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 360 361 callout_init(&sc->calib_to, 0); 362 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 363 364 pci_aprint_devinfo(pa, NULL); 365 366 /* 367 * Get the offset of the PCI Express Capability Structure in PCI 368 * Configuration Space. 369 */ 370 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 371 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 372 if (error == 0) { 373 aprint_error(": PCIe capability structure not found!\n"); 374 return; 375 } 376 377 /* Clear device-specific "PCI retry timeout" register (41h). */ 378 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 379 if (reg & 0xff00) 380 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 381 382 /* Enable bus-mastering and hardware bug workaround. */ 383 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 384 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 385 reg |= PCI_COMMAND_MASTER_ENABLE; 386 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 387 DPRINTF(("PCIe INTx Disable set\n")); 388 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 389 } 390 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 391 392 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 393 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 394 &sc->sc_sh, NULL, &sc->sc_sz); 395 if (error != 0) { 396 aprint_error(": can't map mem space\n"); 397 return; 398 } 399 400 /* Install interrupt handler. */ 401 if (pci_intr_map(pa, &ih) != 0) { 402 aprint_error(": can't map interrupt\n"); 403 return; 404 } 405 intrstr = pci_intr_string(sc->sc_pct, ih); 406 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 407 if (sc->sc_ih == NULL) { 408 aprint_error(": can't establish interrupt"); 409 if (intrstr != NULL) 410 aprint_error(" at %s", intrstr); 411 aprint_error("\n"); 412 return; 413 } 414 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 415 416 /* Read hardware revision and attach. */ 417 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 418 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 419 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 420 else 421 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 422 if (error != 0) { 423 aprint_error(": could not attach device\n"); 424 return; 425 } 426 427 if ((error = iwn_hw_prepare(sc)) != 0) { 428 aprint_error(": hardware not ready\n"); 429 return; 430 } 431 432 /* Read MAC address, channels, etc from EEPROM. */ 433 if ((error = iwn_read_eeprom(sc)) != 0) { 434 aprint_error(": could not read EEPROM\n"); 435 return; 436 } 437 438 /* Allocate DMA memory for firmware transfers. */ 439 if ((error = iwn_alloc_fwmem(sc)) != 0) { 440 aprint_error(": could not allocate memory for firmware\n"); 441 return; 442 } 443 444 /* Allocate "Keep Warm" page. */ 445 if ((error = iwn_alloc_kw(sc)) != 0) { 446 aprint_error(": could not allocate keep warm page\n"); 447 goto fail1; 448 } 449 450 /* Allocate ICT table for 5000 Series. */ 451 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 452 (error = iwn_alloc_ict(sc)) != 0) { 453 aprint_error(": could not allocate ICT table\n"); 454 goto fail2; 455 } 456 457 /* Allocate TX scheduler "rings". */ 458 if ((error = iwn_alloc_sched(sc)) != 0) { 459 aprint_error(": could not allocate TX scheduler rings\n"); 460 goto fail3; 461 } 462 463 #ifdef IWN_USE_RBUF 464 /* Allocate RX buffers. */ 465 if ((error = iwn_alloc_rpool(sc)) != 0) { 466 aprint_error_dev(self, "could not allocate RX buffers\n"); 467 goto fail3; 468 } 469 #endif 470 471 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 472 for (i = 0; i < sc->ntxqs; i++) { 473 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 474 aprint_error(": could not allocate TX ring %d\n", i); 475 goto fail4; 476 } 477 } 478 479 /* Allocate RX ring. */ 480 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 481 aprint_error(": could not allocate RX ring\n"); 482 goto fail4; 483 } 484 485 /* Clear pending interrupts. */ 486 IWN_WRITE(sc, IWN_INT, 0xffffffff); 487 488 /* Count the number of available chains. */ 489 sc->ntxchains = 490 ((sc->txchainmask >> 2) & 1) + 491 ((sc->txchainmask >> 1) & 1) + 492 ((sc->txchainmask >> 0) & 1); 493 sc->nrxchains = 494 ((sc->rxchainmask >> 2) & 1) + 495 ((sc->rxchainmask >> 1) & 1) + 496 ((sc->rxchainmask >> 0) & 1); 497 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 498 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 499 ether_sprintf(ic->ic_myaddr)); 500 501 ic->ic_ifp = ifp; 502 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 503 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 504 ic->ic_state = IEEE80211_S_INIT; 505 506 /* Set device capabilities. */ 507 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 508 * and IEEE80211_C_PMGT too. */ 509 ic->ic_caps = 510 IEEE80211_C_IBSS | /* IBSS mode support */ 511 IEEE80211_C_WPA | /* 802.11i */ 512 IEEE80211_C_MONITOR | /* monitor mode supported */ 513 IEEE80211_C_TXPMGT | /* tx power management */ 514 IEEE80211_C_SHSLOT | /* short slot time supported */ 515 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 516 IEEE80211_C_WME; /* 802.11e */ 517 518 #ifndef IEEE80211_NO_HT 519 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 520 /* Set HT capabilities. */ 521 ic->ic_htcaps = 522 #if IWN_RBUF_SIZE == 8192 523 IEEE80211_HTCAP_AMSDU7935 | 524 #endif 525 IEEE80211_HTCAP_CBW20_40 | 526 IEEE80211_HTCAP_SGI20 | 527 IEEE80211_HTCAP_SGI40; 528 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 529 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 530 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 531 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 532 else 533 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 534 } 535 #endif /* !IEEE80211_NO_HT */ 536 537 /* Set supported legacy rates. */ 538 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 539 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 540 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 541 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 542 } 543 #ifndef IEEE80211_NO_HT 544 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 545 /* Set supported HT rates. */ 546 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 547 if (sc->nrxchains > 1) 548 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 549 if (sc->nrxchains > 2) 550 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 551 } 552 #endif 553 554 /* IBSS channel undefined for now. */ 555 ic->ic_ibss_chan = &ic->ic_channels[0]; 556 557 ifp->if_softc = sc; 558 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 559 ifp->if_init = iwn_init; 560 ifp->if_ioctl = iwn_ioctl; 561 ifp->if_start = iwn_start; 562 ifp->if_stop = iwn_stop; 563 ifp->if_watchdog = iwn_watchdog; 564 IFQ_SET_READY(&ifp->if_snd); 565 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 566 567 if_attach(ifp); 568 ieee80211_ifattach(ic); 569 ic->ic_node_alloc = iwn_node_alloc; 570 ic->ic_newassoc = iwn_newassoc; 571 #ifdef IWN_HWCRYPTO 572 ic->ic_crypto.cs_key_set = iwn_set_key; 573 ic->ic_crypto.cs_key_delete = iwn_delete_key; 574 #endif 575 ic->ic_wme.wme_update = iwn_wme_update; 576 #ifndef IEEE80211_NO_HT 577 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 578 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 579 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 580 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 581 #endif 582 583 /* Override 802.11 state transition machine. */ 584 sc->sc_newstate = ic->ic_newstate; 585 ic->ic_newstate = iwn_newstate; 586 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 587 588 sc->amrr.amrr_min_success_threshold = 1; 589 sc->amrr.amrr_max_success_threshold = 15; 590 591 iwn_radiotap_attach(sc); 592 593 /* 594 * XXX for NetBSD, OpenBSD timeout_set replaced by 595 * callout_init and callout_setfunc, above. 596 */ 597 598 if (pmf_device_register(self, NULL, iwn_resume)) 599 pmf_class_network_register(self, ifp); 600 else 601 aprint_error_dev(self, "couldn't establish power handler\n"); 602 603 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 604 ieee80211_announce(ic); 605 606 return; 607 608 /* Free allocated memory if something failed during attachment. */ 609 fail4: while (--i >= 0) 610 iwn_free_tx_ring(sc, &sc->txq[i]); 611 #ifdef IWN_USE_RBUF 612 iwn_free_rpool(sc); 613 #endif 614 iwn_free_sched(sc); 615 fail3: if (sc->ict != NULL) 616 iwn_free_ict(sc); 617 fail2: iwn_free_kw(sc); 618 fail1: iwn_free_fwmem(sc); 619 } 620 621 int 622 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 623 { 624 struct iwn_ops *ops = &sc->ops; 625 626 ops->load_firmware = iwn4965_load_firmware; 627 ops->read_eeprom = iwn4965_read_eeprom; 628 ops->post_alive = iwn4965_post_alive; 629 ops->nic_config = iwn4965_nic_config; 630 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 631 ops->update_sched = iwn4965_update_sched; 632 ops->get_temperature = iwn4965_get_temperature; 633 ops->get_rssi = iwn4965_get_rssi; 634 ops->set_txpower = iwn4965_set_txpower; 635 ops->init_gains = iwn4965_init_gains; 636 ops->set_gains = iwn4965_set_gains; 637 ops->add_node = iwn4965_add_node; 638 ops->tx_done = iwn4965_tx_done; 639 #ifndef IEEE80211_NO_HT 640 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 641 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 642 #endif 643 sc->ntxqs = IWN4965_NTXQUEUES; 644 sc->ndmachnls = IWN4965_NDMACHNLS; 645 sc->broadcast_id = IWN4965_ID_BROADCAST; 646 sc->rxonsz = IWN4965_RXONSZ; 647 sc->schedsz = IWN4965_SCHEDSZ; 648 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 649 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 650 sc->fwsz = IWN4965_FWSZ; 651 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 652 sc->limits = &iwn4965_sensitivity_limits; 653 sc->fwname = "iwlwifi-4965-2.ucode"; 654 /* Override chains masks, ROM is known to be broken. */ 655 sc->txchainmask = IWN_ANT_AB; 656 sc->rxchainmask = IWN_ANT_ABC; 657 658 return 0; 659 } 660 661 int 662 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 663 { 664 struct iwn_ops *ops = &sc->ops; 665 666 ops->load_firmware = iwn5000_load_firmware; 667 ops->read_eeprom = iwn5000_read_eeprom; 668 ops->post_alive = iwn5000_post_alive; 669 ops->nic_config = iwn5000_nic_config; 670 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 671 ops->update_sched = iwn5000_update_sched; 672 ops->get_temperature = iwn5000_get_temperature; 673 ops->get_rssi = iwn5000_get_rssi; 674 ops->set_txpower = iwn5000_set_txpower; 675 ops->init_gains = iwn5000_init_gains; 676 ops->set_gains = iwn5000_set_gains; 677 ops->add_node = iwn5000_add_node; 678 ops->tx_done = iwn5000_tx_done; 679 #ifndef IEEE80211_NO_HT 680 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 681 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 682 #endif 683 sc->ntxqs = IWN5000_NTXQUEUES; 684 sc->ndmachnls = IWN5000_NDMACHNLS; 685 sc->broadcast_id = IWN5000_ID_BROADCAST; 686 sc->rxonsz = IWN5000_RXONSZ; 687 sc->schedsz = IWN5000_SCHEDSZ; 688 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 689 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 690 sc->fwsz = IWN5000_FWSZ; 691 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 692 693 switch (sc->hw_type) { 694 case IWN_HW_REV_TYPE_5100: 695 sc->limits = &iwn5000_sensitivity_limits; 696 sc->fwname = "iwlwifi-5000-2.ucode"; 697 /* Override chains masks, ROM is known to be broken. */ 698 sc->txchainmask = IWN_ANT_B; 699 sc->rxchainmask = IWN_ANT_AB; 700 break; 701 case IWN_HW_REV_TYPE_5150: 702 sc->limits = &iwn5150_sensitivity_limits; 703 sc->fwname = "iwlwifi-5150-2.ucode"; 704 break; 705 case IWN_HW_REV_TYPE_5300: 706 case IWN_HW_REV_TYPE_5350: 707 sc->limits = &iwn5000_sensitivity_limits; 708 sc->fwname = "iwlwifi-5000-2.ucode"; 709 break; 710 case IWN_HW_REV_TYPE_1000: 711 sc->limits = &iwn1000_sensitivity_limits; 712 sc->fwname = "iwlwifi-1000-3.ucode"; 713 break; 714 case IWN_HW_REV_TYPE_6000: 715 sc->limits = &iwn6000_sensitivity_limits; 716 sc->fwname = "iwlwifi-6000-4.ucode"; 717 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 718 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 719 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 720 /* Override chains masks, ROM is known to be broken. */ 721 sc->txchainmask = IWN_ANT_BC; 722 sc->rxchainmask = IWN_ANT_BC; 723 } 724 break; 725 case IWN_HW_REV_TYPE_6050: 726 sc->limits = &iwn6000_sensitivity_limits; 727 sc->fwname = "iwlwifi-6050-5.ucode"; 728 break; 729 case IWN_HW_REV_TYPE_6005: 730 sc->limits = &iwn6000_sensitivity_limits; 731 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 732 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 733 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 734 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 735 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 736 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235) { 737 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 738 ops->config_bt_coex = iwn_config_bt_coex_adv1; 739 } 740 else 741 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 742 break; 743 default: 744 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 745 return ENOTSUP; 746 } 747 return 0; 748 } 749 750 /* 751 * Attach the interface to 802.11 radiotap. 752 */ 753 static void 754 iwn_radiotap_attach(struct iwn_softc *sc) 755 { 756 struct ifnet *ifp = sc->sc_ic.ic_ifp; 757 758 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 759 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 760 &sc->sc_drvbpf); 761 762 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 763 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 764 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 765 766 sc->sc_txtap_len = sizeof sc->sc_txtapu; 767 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 768 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 769 } 770 771 static int 772 iwn_detach(device_t self, int flags __unused) 773 { 774 struct iwn_softc *sc = device_private(self); 775 struct ifnet *ifp = sc->sc_ic.ic_ifp; 776 int qid; 777 778 callout_stop(&sc->calib_to); 779 780 /* Uninstall interrupt handler. */ 781 if (sc->sc_ih != NULL) 782 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 783 784 /* Free DMA resources. */ 785 iwn_free_rx_ring(sc, &sc->rxq); 786 for (qid = 0; qid < sc->ntxqs; qid++) 787 iwn_free_tx_ring(sc, &sc->txq[qid]); 788 #ifdef IWN_USE_RBUF 789 iwn_free_rpool(sc); 790 #endif 791 iwn_free_sched(sc); 792 iwn_free_kw(sc); 793 if (sc->ict != NULL) 794 iwn_free_ict(sc); 795 iwn_free_fwmem(sc); 796 797 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 798 799 ieee80211_ifdetach(&sc->sc_ic); 800 if_detach(ifp); 801 802 return 0; 803 } 804 805 #if 0 806 /* 807 * XXX Investigate if clearing the PCI retry timeout could eliminate 808 * the repeated scan calls. Also the calls to if_init and if_start 809 * are similar to the effect of adding the call to ifioctl_common . 810 */ 811 static void 812 iwn_power(int why, void *arg) 813 { 814 struct iwn_softc *sc = arg; 815 struct ifnet *ifp; 816 pcireg_t reg; 817 int s; 818 819 if (why != PWR_RESUME) 820 return; 821 822 /* Clear device-specific "PCI retry timeout" register (41h). */ 823 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 824 if (reg & 0xff00) 825 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 826 827 s = splnet(); 828 ifp = &sc->sc_ic.ic_if; 829 if (ifp->if_flags & IFF_UP) { 830 ifp->if_init(ifp); 831 if (ifp->if_flags & IFF_RUNNING) 832 ifp->if_start(ifp); 833 } 834 splx(s); 835 } 836 #endif 837 838 static bool 839 iwn_resume(device_t dv, const pmf_qual_t *qual) 840 { 841 return true; 842 } 843 844 static int 845 iwn_nic_lock(struct iwn_softc *sc) 846 { 847 int ntries; 848 849 /* Request exclusive access to NIC. */ 850 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 851 852 /* Spin until we actually get the lock. */ 853 for (ntries = 0; ntries < 1000; ntries++) { 854 if ((IWN_READ(sc, IWN_GP_CNTRL) & 855 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 856 IWN_GP_CNTRL_MAC_ACCESS_ENA) 857 return 0; 858 DELAY(10); 859 } 860 return ETIMEDOUT; 861 } 862 863 static __inline void 864 iwn_nic_unlock(struct iwn_softc *sc) 865 { 866 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 867 } 868 869 static __inline uint32_t 870 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 871 { 872 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 873 IWN_BARRIER_READ_WRITE(sc); 874 return IWN_READ(sc, IWN_PRPH_RDATA); 875 } 876 877 static __inline void 878 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 879 { 880 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 881 IWN_BARRIER_WRITE(sc); 882 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 883 } 884 885 static __inline void 886 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 887 { 888 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 889 } 890 891 static __inline void 892 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 893 { 894 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 895 } 896 897 static __inline void 898 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 899 const uint32_t *data, int count) 900 { 901 for (; count > 0; count--, data++, addr += 4) 902 iwn_prph_write(sc, addr, *data); 903 } 904 905 static __inline uint32_t 906 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 907 { 908 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 909 IWN_BARRIER_READ_WRITE(sc); 910 return IWN_READ(sc, IWN_MEM_RDATA); 911 } 912 913 static __inline void 914 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 915 { 916 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 917 IWN_BARRIER_WRITE(sc); 918 IWN_WRITE(sc, IWN_MEM_WDATA, data); 919 } 920 921 static __inline void 922 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 923 { 924 uint32_t tmp; 925 926 tmp = iwn_mem_read(sc, addr & ~3); 927 if (addr & 3) 928 tmp = (tmp & 0x0000ffff) | data << 16; 929 else 930 tmp = (tmp & 0xffff0000) | data; 931 iwn_mem_write(sc, addr & ~3, tmp); 932 } 933 934 static __inline void 935 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 936 int count) 937 { 938 for (; count > 0; count--, addr += 4) 939 *data++ = iwn_mem_read(sc, addr); 940 } 941 942 static __inline void 943 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 944 int count) 945 { 946 for (; count > 0; count--, addr += 4) 947 iwn_mem_write(sc, addr, val); 948 } 949 950 static int 951 iwn_eeprom_lock(struct iwn_softc *sc) 952 { 953 int i, ntries; 954 955 for (i = 0; i < 100; i++) { 956 /* Request exclusive access to EEPROM. */ 957 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 958 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 959 960 /* Spin until we actually get the lock. */ 961 for (ntries = 0; ntries < 100; ntries++) { 962 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 963 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 964 return 0; 965 DELAY(10); 966 } 967 } 968 return ETIMEDOUT; 969 } 970 971 static __inline void 972 iwn_eeprom_unlock(struct iwn_softc *sc) 973 { 974 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 975 } 976 977 /* 978 * Initialize access by host to One Time Programmable ROM. 979 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 980 */ 981 static int 982 iwn_init_otprom(struct iwn_softc *sc) 983 { 984 uint16_t prev = 0, base, next; 985 int count, error; 986 987 /* Wait for clock stabilization before accessing prph. */ 988 if ((error = iwn_clock_wait(sc)) != 0) 989 return error; 990 991 if ((error = iwn_nic_lock(sc)) != 0) 992 return error; 993 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 994 DELAY(5); 995 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 996 iwn_nic_unlock(sc); 997 998 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 999 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1000 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1001 IWN_RESET_LINK_PWR_MGMT_DIS); 1002 } 1003 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1004 /* Clear ECC status. */ 1005 IWN_SETBITS(sc, IWN_OTP_GP, 1006 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1007 1008 /* 1009 * Find the block before last block (contains the EEPROM image) 1010 * for HW without OTP shadow RAM. 1011 */ 1012 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1013 /* Switch to absolute addressing mode. */ 1014 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1015 base = 0; 1016 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1017 error = iwn_read_prom_data(sc, base, &next, 2); 1018 if (error != 0) 1019 return error; 1020 if (next == 0) /* End of linked-list. */ 1021 break; 1022 prev = base; 1023 base = le16toh(next); 1024 } 1025 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1026 return EIO; 1027 /* Skip "next" word. */ 1028 sc->prom_base = prev + 1; 1029 } 1030 return 0; 1031 } 1032 1033 static int 1034 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1035 { 1036 uint8_t *out = data; 1037 uint32_t val, tmp; 1038 int ntries; 1039 1040 addr += sc->prom_base; 1041 for (; count > 0; count -= 2, addr++) { 1042 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1043 for (ntries = 0; ntries < 10; ntries++) { 1044 val = IWN_READ(sc, IWN_EEPROM); 1045 if (val & IWN_EEPROM_READ_VALID) 1046 break; 1047 DELAY(5); 1048 } 1049 if (ntries == 10) { 1050 aprint_error_dev(sc->sc_dev, 1051 "timeout reading ROM at 0x%x\n", addr); 1052 return ETIMEDOUT; 1053 } 1054 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1055 /* OTPROM, check for ECC errors. */ 1056 tmp = IWN_READ(sc, IWN_OTP_GP); 1057 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1058 aprint_error_dev(sc->sc_dev, 1059 "OTPROM ECC error at 0x%x\n", addr); 1060 return EIO; 1061 } 1062 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1063 /* Correctable ECC error, clear bit. */ 1064 IWN_SETBITS(sc, IWN_OTP_GP, 1065 IWN_OTP_GP_ECC_CORR_STTS); 1066 } 1067 } 1068 *out++ = val >> 16; 1069 if (count > 1) 1070 *out++ = val >> 24; 1071 } 1072 return 0; 1073 } 1074 1075 static int 1076 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1077 bus_size_t size, bus_size_t alignment) 1078 { 1079 int nsegs, error; 1080 1081 dma->tag = tag; 1082 dma->size = size; 1083 1084 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1085 &dma->map); 1086 if (error != 0) 1087 goto fail; 1088 1089 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1090 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1091 if (error != 0) 1092 goto fail; 1093 1094 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1095 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1096 if (error != 0) 1097 goto fail; 1098 1099 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1100 BUS_DMA_NOWAIT); 1101 if (error != 0) 1102 goto fail; 1103 1104 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1105 memset(dma->vaddr, 0, size); 1106 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1107 1108 dma->paddr = dma->map->dm_segs[0].ds_addr; 1109 if (kvap != NULL) 1110 *kvap = dma->vaddr; 1111 1112 return 0; 1113 1114 fail: iwn_dma_contig_free(dma); 1115 return error; 1116 } 1117 1118 static void 1119 iwn_dma_contig_free(struct iwn_dma_info *dma) 1120 { 1121 if (dma->map != NULL) { 1122 if (dma->vaddr != NULL) { 1123 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1124 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1125 bus_dmamap_unload(dma->tag, dma->map); 1126 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1127 bus_dmamem_free(dma->tag, &dma->seg, 1); 1128 dma->vaddr = NULL; 1129 } 1130 bus_dmamap_destroy(dma->tag, dma->map); 1131 dma->map = NULL; 1132 } 1133 } 1134 1135 static int 1136 iwn_alloc_sched(struct iwn_softc *sc) 1137 { 1138 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1139 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1140 (void **)&sc->sched, sc->schedsz, 1024); 1141 } 1142 1143 static void 1144 iwn_free_sched(struct iwn_softc *sc) 1145 { 1146 iwn_dma_contig_free(&sc->sched_dma); 1147 } 1148 1149 static int 1150 iwn_alloc_kw(struct iwn_softc *sc) 1151 { 1152 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1153 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1154 4096); 1155 } 1156 1157 static void 1158 iwn_free_kw(struct iwn_softc *sc) 1159 { 1160 iwn_dma_contig_free(&sc->kw_dma); 1161 } 1162 1163 static int 1164 iwn_alloc_ict(struct iwn_softc *sc) 1165 { 1166 /* ICT table must be aligned on a 4KB boundary. */ 1167 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1168 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1169 } 1170 1171 static void 1172 iwn_free_ict(struct iwn_softc *sc) 1173 { 1174 iwn_dma_contig_free(&sc->ict_dma); 1175 } 1176 1177 static int 1178 iwn_alloc_fwmem(struct iwn_softc *sc) 1179 { 1180 /* Must be aligned on a 16-byte boundary. */ 1181 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1182 sc->fwsz, 16); 1183 } 1184 1185 static void 1186 iwn_free_fwmem(struct iwn_softc *sc) 1187 { 1188 iwn_dma_contig_free(&sc->fw_dma); 1189 } 1190 1191 static int 1192 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1193 { 1194 bus_size_t size; 1195 int i, error; 1196 1197 ring->cur = 0; 1198 1199 /* Allocate RX descriptors (256-byte aligned). */ 1200 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1201 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1202 (void **)&ring->desc, size, 256); 1203 if (error != 0) { 1204 aprint_error_dev(sc->sc_dev, 1205 "could not allocate RX ring DMA memory\n"); 1206 goto fail; 1207 } 1208 1209 /* Allocate RX status area (16-byte aligned). */ 1210 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1211 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1212 if (error != 0) { 1213 aprint_error_dev(sc->sc_dev, 1214 "could not allocate RX status DMA memory\n"); 1215 goto fail; 1216 } 1217 1218 /* 1219 * Allocate and map RX buffers. 1220 */ 1221 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1222 struct iwn_rx_data *data = &ring->data[i]; 1223 1224 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1225 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1226 &data->map); 1227 if (error != 0) { 1228 aprint_error_dev(sc->sc_dev, 1229 "could not create RX buf DMA map\n"); 1230 goto fail; 1231 } 1232 1233 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1234 if (data->m == NULL) { 1235 aprint_error_dev(sc->sc_dev, 1236 "could not allocate RX mbuf\n"); 1237 error = ENOBUFS; 1238 goto fail; 1239 } 1240 1241 error = bus_dmamap_load(sc->sc_dmat, data->map, 1242 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1243 BUS_DMA_NOWAIT | BUS_DMA_READ); 1244 if (error != 0) { 1245 aprint_error_dev(sc->sc_dev, 1246 "can't not map mbuf (error %d)\n", error); 1247 goto fail; 1248 } 1249 1250 /* Set physical address of RX buffer (256-byte aligned). */ 1251 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1252 } 1253 1254 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1255 BUS_DMASYNC_PREWRITE); 1256 1257 return 0; 1258 1259 fail: iwn_free_rx_ring(sc, ring); 1260 return error; 1261 } 1262 1263 static void 1264 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1265 { 1266 int ntries; 1267 1268 if (iwn_nic_lock(sc) == 0) { 1269 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1270 for (ntries = 0; ntries < 1000; ntries++) { 1271 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1272 IWN_FH_RX_STATUS_IDLE) 1273 break; 1274 DELAY(10); 1275 } 1276 iwn_nic_unlock(sc); 1277 } 1278 ring->cur = 0; 1279 sc->last_rx_valid = 0; 1280 } 1281 1282 static void 1283 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1284 { 1285 int i; 1286 1287 iwn_dma_contig_free(&ring->desc_dma); 1288 iwn_dma_contig_free(&ring->stat_dma); 1289 1290 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1291 struct iwn_rx_data *data = &ring->data[i]; 1292 1293 if (data->m != NULL) { 1294 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1295 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1296 bus_dmamap_unload(sc->sc_dmat, data->map); 1297 m_freem(data->m); 1298 } 1299 if (data->map != NULL) 1300 bus_dmamap_destroy(sc->sc_dmat, data->map); 1301 } 1302 } 1303 1304 static int 1305 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1306 { 1307 bus_addr_t paddr; 1308 bus_size_t size; 1309 int i, error; 1310 1311 ring->qid = qid; 1312 ring->queued = 0; 1313 ring->cur = 0; 1314 1315 /* Allocate TX descriptors (256-byte aligned). */ 1316 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1317 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1318 (void **)&ring->desc, size, 256); 1319 if (error != 0) { 1320 aprint_error_dev(sc->sc_dev, 1321 "could not allocate TX ring DMA memory\n"); 1322 goto fail; 1323 } 1324 /* 1325 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1326 * to allocate commands space for other rings. 1327 * XXX Do we really need to allocate descriptors for other rings? 1328 */ 1329 if (qid > 4) 1330 return 0; 1331 1332 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1333 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1334 (void **)&ring->cmd, size, 4); 1335 if (error != 0) { 1336 aprint_error_dev(sc->sc_dev, 1337 "could not allocate TX cmd DMA memory\n"); 1338 goto fail; 1339 } 1340 1341 paddr = ring->cmd_dma.paddr; 1342 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1343 struct iwn_tx_data *data = &ring->data[i]; 1344 1345 data->cmd_paddr = paddr; 1346 data->scratch_paddr = paddr + 12; 1347 paddr += sizeof (struct iwn_tx_cmd); 1348 1349 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1350 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1351 &data->map); 1352 if (error != 0) { 1353 aprint_error_dev(sc->sc_dev, 1354 "could not create TX buf DMA map\n"); 1355 goto fail; 1356 } 1357 } 1358 return 0; 1359 1360 fail: iwn_free_tx_ring(sc, ring); 1361 return error; 1362 } 1363 1364 static void 1365 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1366 { 1367 int i; 1368 1369 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1370 struct iwn_tx_data *data = &ring->data[i]; 1371 1372 if (data->m != NULL) { 1373 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1374 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1375 bus_dmamap_unload(sc->sc_dmat, data->map); 1376 m_freem(data->m); 1377 data->m = NULL; 1378 } 1379 } 1380 /* Clear TX descriptors. */ 1381 memset(ring->desc, 0, ring->desc_dma.size); 1382 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1383 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1384 sc->qfullmsk &= ~(1 << ring->qid); 1385 ring->queued = 0; 1386 ring->cur = 0; 1387 } 1388 1389 static void 1390 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1391 { 1392 int i; 1393 1394 iwn_dma_contig_free(&ring->desc_dma); 1395 iwn_dma_contig_free(&ring->cmd_dma); 1396 1397 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1398 struct iwn_tx_data *data = &ring->data[i]; 1399 1400 if (data->m != NULL) { 1401 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1402 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1403 bus_dmamap_unload(sc->sc_dmat, data->map); 1404 m_freem(data->m); 1405 } 1406 if (data->map != NULL) 1407 bus_dmamap_destroy(sc->sc_dmat, data->map); 1408 } 1409 } 1410 1411 static void 1412 iwn5000_ict_reset(struct iwn_softc *sc) 1413 { 1414 /* Disable interrupts. */ 1415 IWN_WRITE(sc, IWN_INT_MASK, 0); 1416 1417 /* Reset ICT table. */ 1418 memset(sc->ict, 0, IWN_ICT_SIZE); 1419 sc->ict_cur = 0; 1420 1421 /* Set physical address of ICT table (4KB aligned). */ 1422 DPRINTF(("enabling ICT\n")); 1423 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1424 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1425 1426 /* Enable periodic RX interrupt. */ 1427 sc->int_mask |= IWN_INT_RX_PERIODIC; 1428 /* Switch to ICT interrupt mode in driver. */ 1429 sc->sc_flags |= IWN_FLAG_USE_ICT; 1430 1431 /* Re-enable interrupts. */ 1432 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1433 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1434 } 1435 1436 static int 1437 iwn_read_eeprom(struct iwn_softc *sc) 1438 { 1439 struct iwn_ops *ops = &sc->ops; 1440 struct ieee80211com *ic = &sc->sc_ic; 1441 uint16_t val; 1442 int error; 1443 1444 /* Check whether adapter has an EEPROM or an OTPROM. */ 1445 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1446 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1447 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1448 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1449 "OTPROM" : "EEPROM")); 1450 1451 /* Adapter has to be powered on for EEPROM access to work. */ 1452 if ((error = iwn_apm_init(sc)) != 0) { 1453 aprint_error_dev(sc->sc_dev, 1454 "could not power ON adapter\n"); 1455 return error; 1456 } 1457 1458 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1459 aprint_error_dev(sc->sc_dev, 1460 "bad ROM signature\n"); 1461 return EIO; 1462 } 1463 if ((error = iwn_eeprom_lock(sc)) != 0) { 1464 aprint_error_dev(sc->sc_dev, 1465 "could not lock ROM (error=%d)\n", error); 1466 return error; 1467 } 1468 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1469 if ((error = iwn_init_otprom(sc)) != 0) { 1470 aprint_error_dev(sc->sc_dev, 1471 "could not initialize OTPROM\n"); 1472 return error; 1473 } 1474 } 1475 1476 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1477 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1478 /* Check if HT support is bonded out. */ 1479 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1480 sc->sc_flags |= IWN_FLAG_HAS_11N; 1481 1482 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1483 sc->rfcfg = le16toh(val); 1484 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1485 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1486 if (sc->txchainmask == 0) 1487 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1488 if (sc->rxchainmask == 0) 1489 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1490 1491 /* Read MAC address. */ 1492 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1493 1494 /* Read adapter-specific information from EEPROM. */ 1495 ops->read_eeprom(sc); 1496 1497 iwn_apm_stop(sc); /* Power OFF adapter. */ 1498 1499 iwn_eeprom_unlock(sc); 1500 return 0; 1501 } 1502 1503 static void 1504 iwn4965_read_eeprom(struct iwn_softc *sc) 1505 { 1506 uint32_t addr; 1507 uint16_t val; 1508 int i; 1509 1510 /* Read regulatory domain (4 ASCII characters). */ 1511 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1512 1513 /* Read the list of authorized channels (20MHz ones only). */ 1514 for (i = 0; i < 5; i++) { 1515 addr = iwn4965_regulatory_bands[i]; 1516 iwn_read_eeprom_channels(sc, i, addr); 1517 } 1518 1519 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1520 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1521 sc->maxpwr2GHz = val & 0xff; 1522 sc->maxpwr5GHz = val >> 8; 1523 /* Check that EEPROM values are within valid range. */ 1524 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1525 sc->maxpwr5GHz = 38; 1526 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1527 sc->maxpwr2GHz = 38; 1528 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1529 1530 /* Read samples for each TX power group. */ 1531 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1532 sizeof sc->bands); 1533 1534 /* Read voltage at which samples were taken. */ 1535 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1536 sc->eeprom_voltage = (int16_t)le16toh(val); 1537 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1538 1539 #ifdef IWN_DEBUG 1540 /* Print samples. */ 1541 if (iwn_debug > 0) { 1542 for (i = 0; i < IWN_NBANDS; i++) 1543 iwn4965_print_power_group(sc, i); 1544 } 1545 #endif 1546 } 1547 1548 #ifdef IWN_DEBUG 1549 static void 1550 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1551 { 1552 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1553 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1554 int j, c; 1555 1556 aprint_normal("===band %d===\n", i); 1557 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1558 aprint_normal("chan1 num=%d\n", chans[0].num); 1559 for (c = 0; c < 2; c++) { 1560 for (j = 0; j < IWN_NSAMPLES; j++) { 1561 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1562 "power=%d pa_det=%d\n", c, j, 1563 chans[0].samples[c][j].temp, 1564 chans[0].samples[c][j].gain, 1565 chans[0].samples[c][j].power, 1566 chans[0].samples[c][j].pa_det); 1567 } 1568 } 1569 aprint_normal("chan2 num=%d\n", chans[1].num); 1570 for (c = 0; c < 2; c++) { 1571 for (j = 0; j < IWN_NSAMPLES; j++) { 1572 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1573 "power=%d pa_det=%d\n", c, j, 1574 chans[1].samples[c][j].temp, 1575 chans[1].samples[c][j].gain, 1576 chans[1].samples[c][j].power, 1577 chans[1].samples[c][j].pa_det); 1578 } 1579 } 1580 } 1581 #endif 1582 1583 static void 1584 iwn5000_read_eeprom(struct iwn_softc *sc) 1585 { 1586 struct iwn5000_eeprom_calib_hdr hdr; 1587 int32_t volt; 1588 uint32_t base, addr; 1589 uint16_t val; 1590 int i; 1591 1592 /* Read regulatory domain (4 ASCII characters). */ 1593 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1594 base = le16toh(val); 1595 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1596 sc->eeprom_domain, 4); 1597 1598 /* Read the list of authorized channels (20MHz ones only). */ 1599 for (i = 0; i < 5; i++) { 1600 addr = base + iwn5000_regulatory_bands[i]; 1601 iwn_read_eeprom_channels(sc, i, addr); 1602 } 1603 1604 /* Read enhanced TX power information for 6000 Series. */ 1605 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1606 iwn_read_eeprom_enhinfo(sc); 1607 1608 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1609 base = le16toh(val); 1610 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1611 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1612 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1613 sc->calib_ver = hdr.version; 1614 1615 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1616 /* Compute temperature offset. */ 1617 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1618 sc->eeprom_temp = le16toh(val); 1619 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1620 volt = le16toh(val); 1621 sc->temp_off = sc->eeprom_temp - (volt / -5); 1622 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1623 sc->eeprom_temp, volt, sc->temp_off)); 1624 } else { 1625 /* Read crystal calibration. */ 1626 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1627 &sc->eeprom_crystal, sizeof (uint32_t)); 1628 DPRINTF(("crystal calibration 0x%08x\n", 1629 le32toh(sc->eeprom_crystal))); 1630 } 1631 } 1632 1633 static void 1634 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1635 { 1636 struct ieee80211com *ic = &sc->sc_ic; 1637 const struct iwn_chan_band *band = &iwn_bands[n]; 1638 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1639 uint8_t chan; 1640 int i; 1641 1642 iwn_read_prom_data(sc, addr, channels, 1643 band->nchan * sizeof (struct iwn_eeprom_chan)); 1644 1645 for (i = 0; i < band->nchan; i++) { 1646 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1647 continue; 1648 1649 chan = band->chan[i]; 1650 1651 if (n == 0) { /* 2GHz band */ 1652 ic->ic_channels[chan].ic_freq = 1653 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1654 ic->ic_channels[chan].ic_flags = 1655 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1656 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1657 1658 } else { /* 5GHz band */ 1659 /* 1660 * Some adapters support channels 7, 8, 11 and 12 1661 * both in the 2GHz and 4.9GHz bands. 1662 * Because of limitations in our net80211 layer, 1663 * we don't support them in the 4.9GHz band. 1664 */ 1665 if (chan <= 14) 1666 continue; 1667 1668 ic->ic_channels[chan].ic_freq = 1669 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1670 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1671 /* We have at least one valid 5GHz channel. */ 1672 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1673 } 1674 1675 /* Is active scan allowed on this channel? */ 1676 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1677 ic->ic_channels[chan].ic_flags |= 1678 IEEE80211_CHAN_PASSIVE; 1679 } 1680 1681 /* Save maximum allowed TX power for this channel. */ 1682 sc->maxpwr[chan] = channels[i].maxpwr; 1683 1684 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1685 chan, channels[i].flags, sc->maxpwr[chan])); 1686 } 1687 } 1688 1689 static void 1690 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1691 { 1692 struct iwn_eeprom_enhinfo enhinfo[35]; 1693 uint16_t val, base; 1694 int8_t maxpwr; 1695 int i; 1696 1697 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1698 base = le16toh(val); 1699 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1700 enhinfo, sizeof enhinfo); 1701 1702 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1703 for (i = 0; i < __arraycount(enhinfo); i++) { 1704 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1705 continue; /* Skip invalid entries. */ 1706 1707 maxpwr = 0; 1708 if (sc->txchainmask & IWN_ANT_A) 1709 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1710 if (sc->txchainmask & IWN_ANT_B) 1711 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1712 if (sc->txchainmask & IWN_ANT_C) 1713 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1714 if (sc->ntxchains == 2) 1715 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1716 else if (sc->ntxchains == 3) 1717 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1718 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1719 1720 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1721 sc->enh_maxpwr[i] = maxpwr; 1722 } 1723 } 1724 1725 static struct ieee80211_node * 1726 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1727 { 1728 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1729 } 1730 1731 static void 1732 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1733 { 1734 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1735 struct iwn_node *wn = (void *)ni; 1736 uint8_t rate; 1737 int ridx, i; 1738 1739 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1740 /* Start at lowest available bit-rate, AMRR will raise. */ 1741 ni->ni_txrate = 0; 1742 1743 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1744 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1745 /* Map 802.11 rate to HW rate index. */ 1746 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1747 if (iwn_rates[ridx].rate == rate) 1748 break; 1749 wn->ridx[i] = ridx; 1750 } 1751 } 1752 1753 static int 1754 iwn_media_change(struct ifnet *ifp) 1755 { 1756 struct iwn_softc *sc = ifp->if_softc; 1757 struct ieee80211com *ic = &sc->sc_ic; 1758 uint8_t rate, ridx; 1759 int error; 1760 1761 error = ieee80211_media_change(ifp); 1762 if (error != ENETRESET) 1763 return error; 1764 1765 if (ic->ic_fixed_rate != -1) { 1766 rate = ic->ic_sup_rates[ic->ic_curmode]. 1767 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1768 /* Map 802.11 rate to HW rate index. */ 1769 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1770 if (iwn_rates[ridx].rate == rate) 1771 break; 1772 sc->fixed_ridx = ridx; 1773 } 1774 1775 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1776 (IFF_UP | IFF_RUNNING)) { 1777 iwn_stop(ifp, 0); 1778 error = iwn_init(ifp); 1779 } 1780 return error; 1781 } 1782 1783 static int 1784 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1785 { 1786 struct ifnet *ifp = ic->ic_ifp; 1787 struct iwn_softc *sc = ifp->if_softc; 1788 int error; 1789 1790 callout_stop(&sc->calib_to); 1791 1792 switch (nstate) { 1793 case IEEE80211_S_SCAN: 1794 /* XXX Do not abort a running scan. */ 1795 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1796 if (ic->ic_state != nstate) 1797 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1798 "while scanning(%d) ignored\n", nstate, 1799 ic->ic_state); 1800 break; 1801 } 1802 1803 /* XXX Not sure if call and flags are needed. */ 1804 ieee80211_node_table_reset(&ic->ic_scan); 1805 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1806 sc->sc_flags |= IWN_FLAG_SCANNING; 1807 1808 /* Make the link LED blink while we're scanning. */ 1809 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1810 1811 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1812 aprint_error_dev(sc->sc_dev, 1813 "could not initiate scan\n"); 1814 return error; 1815 } 1816 ic->ic_state = nstate; 1817 return 0; 1818 1819 case IEEE80211_S_ASSOC: 1820 if (ic->ic_state != IEEE80211_S_RUN) 1821 break; 1822 /* FALLTHROUGH */ 1823 case IEEE80211_S_AUTH: 1824 /* Reset state to handle reassociations correctly. */ 1825 sc->rxon.associd = 0; 1826 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1827 sc->calib.state = IWN_CALIB_STATE_INIT; 1828 1829 if ((error = iwn_auth(sc)) != 0) { 1830 aprint_error_dev(sc->sc_dev, 1831 "could not move to auth state\n"); 1832 return error; 1833 } 1834 break; 1835 1836 case IEEE80211_S_RUN: 1837 if ((error = iwn_run(sc)) != 0) { 1838 aprint_error_dev(sc->sc_dev, 1839 "could not move to run state\n"); 1840 return error; 1841 } 1842 break; 1843 1844 case IEEE80211_S_INIT: 1845 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1846 sc->calib.state = IWN_CALIB_STATE_INIT; 1847 break; 1848 } 1849 1850 return sc->sc_newstate(ic, nstate, arg); 1851 } 1852 1853 static void 1854 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1855 { 1856 struct iwn_softc *sc = arg; 1857 struct iwn_node *wn = (struct iwn_node *)ni; 1858 1859 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1860 } 1861 1862 static void 1863 iwn_calib_timeout(void *arg) 1864 { 1865 struct iwn_softc *sc = arg; 1866 struct ieee80211com *ic = &sc->sc_ic; 1867 int s; 1868 1869 s = splnet(); 1870 if (ic->ic_fixed_rate == -1) { 1871 if (ic->ic_opmode == IEEE80211_M_STA) 1872 iwn_iter_func(sc, ic->ic_bss); 1873 else 1874 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1875 } 1876 /* Force automatic TX power calibration every 60 secs. */ 1877 if (++sc->calib_cnt >= 120) { 1878 uint32_t flags = 0; 1879 1880 DPRINTF(("sending request for statistics\n")); 1881 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1882 sizeof flags, 1); 1883 sc->calib_cnt = 0; 1884 } 1885 splx(s); 1886 1887 /* Automatic rate control triggered every 500ms. */ 1888 callout_schedule(&sc->calib_to, hz/2); 1889 } 1890 1891 /* 1892 * Process an RX_PHY firmware notification. This is usually immediately 1893 * followed by an MPDU_RX_DONE notification. 1894 */ 1895 static void 1896 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1897 struct iwn_rx_data *data) 1898 { 1899 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1900 1901 DPRINTFN(2, ("received PHY stats\n")); 1902 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1903 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1904 1905 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1906 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1907 sc->last_rx_valid = 1; 1908 } 1909 1910 /* 1911 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1912 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1913 */ 1914 static void 1915 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1916 struct iwn_rx_data *data) 1917 { 1918 struct iwn_ops *ops = &sc->ops; 1919 struct ieee80211com *ic = &sc->sc_ic; 1920 struct ifnet *ifp = ic->ic_ifp; 1921 struct iwn_rx_ring *ring = &sc->rxq; 1922 struct ieee80211_frame *wh; 1923 struct ieee80211_node *ni; 1924 struct mbuf *m, *m1; 1925 struct iwn_rx_stat *stat; 1926 char *head; 1927 uint32_t flags; 1928 int error, len, rssi; 1929 1930 if (desc->type == IWN_MPDU_RX_DONE) { 1931 /* Check for prior RX_PHY notification. */ 1932 if (!sc->last_rx_valid) { 1933 DPRINTF(("missing RX_PHY\n")); 1934 return; 1935 } 1936 sc->last_rx_valid = 0; 1937 stat = &sc->last_rx_stat; 1938 } else 1939 stat = (struct iwn_rx_stat *)(desc + 1); 1940 1941 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 1942 BUS_DMASYNC_POSTREAD); 1943 1944 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 1945 aprint_error_dev(sc->sc_dev, 1946 "invalid RX statistic header\n"); 1947 return; 1948 } 1949 if (desc->type == IWN_MPDU_RX_DONE) { 1950 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 1951 head = (char *)(mpdu + 1); 1952 len = le16toh(mpdu->len); 1953 } else { 1954 head = (char *)(stat + 1) + stat->cfg_phy_len; 1955 len = le16toh(stat->len); 1956 } 1957 1958 flags = le32toh(*(uint32_t *)(head + len)); 1959 1960 /* Discard frames with a bad FCS early. */ 1961 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 1962 DPRINTFN(2, ("RX flags error %x\n", flags)); 1963 ifp->if_ierrors++; 1964 return; 1965 } 1966 /* Discard frames that are too short. */ 1967 if (len < sizeof (*wh)) { 1968 DPRINTF(("frame too short: %d\n", len)); 1969 ic->ic_stats.is_rx_tooshort++; 1970 ifp->if_ierrors++; 1971 return; 1972 } 1973 1974 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1975 if (m1 == NULL) { 1976 ic->ic_stats.is_rx_nobuf++; 1977 ifp->if_ierrors++; 1978 return; 1979 } 1980 bus_dmamap_unload(sc->sc_dmat, data->map); 1981 1982 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 1983 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1984 if (error != 0) { 1985 m_freem(m1); 1986 1987 /* Try to reload the old mbuf. */ 1988 error = bus_dmamap_load(sc->sc_dmat, data->map, 1989 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1990 BUS_DMA_NOWAIT | BUS_DMA_READ); 1991 if (error != 0) { 1992 panic("%s: could not load old RX mbuf", 1993 device_xname(sc->sc_dev)); 1994 } 1995 /* Physical address may have changed. */ 1996 ring->desc[ring->cur] = 1997 htole32(data->map->dm_segs[0].ds_addr >> 8); 1998 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 1999 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2000 BUS_DMASYNC_PREWRITE); 2001 ifp->if_ierrors++; 2002 return; 2003 } 2004 2005 m = data->m; 2006 data->m = m1; 2007 /* Update RX descriptor. */ 2008 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2009 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2010 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2011 BUS_DMASYNC_PREWRITE); 2012 2013 /* Finalize mbuf. */ 2014 m->m_pkthdr.rcvif = ifp; 2015 m->m_data = head; 2016 m->m_pkthdr.len = m->m_len = len; 2017 2018 /* Grab a reference to the source node. */ 2019 wh = mtod(m, struct ieee80211_frame *); 2020 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2021 2022 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2023 /* NetBSD does decryption in ieee80211_input. */ 2024 2025 rssi = ops->get_rssi(stat); 2026 2027 /* XXX Added for NetBSD: scans never stop without it */ 2028 if (ic->ic_state == IEEE80211_S_SCAN) 2029 iwn_fix_channel(ic, m); 2030 2031 if (sc->sc_drvbpf != NULL) { 2032 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2033 2034 tap->wr_flags = 0; 2035 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2036 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2037 tap->wr_chan_freq = 2038 htole16(ic->ic_channels[stat->chan].ic_freq); 2039 tap->wr_chan_flags = 2040 htole16(ic->ic_channels[stat->chan].ic_flags); 2041 tap->wr_dbm_antsignal = (int8_t)rssi; 2042 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2043 tap->wr_tsft = stat->tstamp; 2044 switch (stat->rate) { 2045 /* CCK rates. */ 2046 case 10: tap->wr_rate = 2; break; 2047 case 20: tap->wr_rate = 4; break; 2048 case 55: tap->wr_rate = 11; break; 2049 case 110: tap->wr_rate = 22; break; 2050 /* OFDM rates. */ 2051 case 0xd: tap->wr_rate = 12; break; 2052 case 0xf: tap->wr_rate = 18; break; 2053 case 0x5: tap->wr_rate = 24; break; 2054 case 0x7: tap->wr_rate = 36; break; 2055 case 0x9: tap->wr_rate = 48; break; 2056 case 0xb: tap->wr_rate = 72; break; 2057 case 0x1: tap->wr_rate = 96; break; 2058 case 0x3: tap->wr_rate = 108; break; 2059 /* Unknown rate: should not happen. */ 2060 default: tap->wr_rate = 0; 2061 } 2062 2063 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2064 } 2065 2066 /* Send the frame to the 802.11 layer. */ 2067 ieee80211_input(ic, m, ni, rssi, 0); 2068 2069 /* Node is no longer needed. */ 2070 ieee80211_free_node(ni); 2071 } 2072 2073 #ifndef IEEE80211_NO_HT 2074 /* Process an incoming Compressed BlockAck. */ 2075 static void 2076 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2077 struct iwn_rx_data *data) 2078 { 2079 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2080 struct iwn_tx_ring *txq; 2081 2082 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2083 BUS_DMASYNC_POSTREAD); 2084 2085 txq = &sc->txq[le16toh(ba->qid)]; 2086 /* XXX TBD */ 2087 } 2088 #endif 2089 2090 /* 2091 * Process a CALIBRATION_RESULT notification sent by the initialization 2092 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2093 */ 2094 static void 2095 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2096 struct iwn_rx_data *data) 2097 { 2098 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2099 int len, idx = -1; 2100 2101 /* Runtime firmware should not send such a notification. */ 2102 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2103 return; 2104 2105 len = (le32toh(desc->len) & 0x3fff) - 4; 2106 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2107 BUS_DMASYNC_POSTREAD); 2108 2109 switch (calib->code) { 2110 case IWN5000_PHY_CALIB_DC: 2111 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 2112 idx = 0; 2113 break; 2114 case IWN5000_PHY_CALIB_LO: 2115 idx = 1; 2116 break; 2117 case IWN5000_PHY_CALIB_TX_IQ: 2118 idx = 2; 2119 break; 2120 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2121 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2122 sc->hw_type != IWN_HW_REV_TYPE_5150) 2123 idx = 3; 2124 break; 2125 case IWN5000_PHY_CALIB_BASE_BAND: 2126 idx = 4; 2127 break; 2128 } 2129 if (idx == -1) /* Ignore other results. */ 2130 return; 2131 2132 /* Save calibration result. */ 2133 if (sc->calibcmd[idx].buf != NULL) 2134 free(sc->calibcmd[idx].buf, M_DEVBUF); 2135 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2136 if (sc->calibcmd[idx].buf == NULL) { 2137 DPRINTF(("not enough memory for calibration result %d\n", 2138 calib->code)); 2139 return; 2140 } 2141 DPRINTF(("saving calibration result code=%d len=%d\n", 2142 calib->code, len)); 2143 sc->calibcmd[idx].len = len; 2144 memcpy(sc->calibcmd[idx].buf, calib, len); 2145 } 2146 2147 /* 2148 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2149 * The latter is sent by the firmware after each received beacon. 2150 */ 2151 static void 2152 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2153 struct iwn_rx_data *data) 2154 { 2155 struct iwn_ops *ops = &sc->ops; 2156 struct ieee80211com *ic = &sc->sc_ic; 2157 struct iwn_calib_state *calib = &sc->calib; 2158 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2159 int temp; 2160 2161 /* Ignore statistics received during a scan. */ 2162 if (ic->ic_state != IEEE80211_S_RUN) 2163 return; 2164 2165 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2166 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2167 2168 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2169 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2170 2171 /* Test if temperature has changed. */ 2172 if (stats->general.temp != sc->rawtemp) { 2173 /* Convert "raw" temperature to degC. */ 2174 sc->rawtemp = stats->general.temp; 2175 temp = ops->get_temperature(sc); 2176 DPRINTFN(2, ("temperature=%dC\n", temp)); 2177 2178 /* Update TX power if need be (4965AGN only). */ 2179 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2180 iwn4965_power_calibration(sc, temp); 2181 } 2182 2183 if (desc->type != IWN_BEACON_STATISTICS) 2184 return; /* Reply to a statistics request. */ 2185 2186 sc->noise = iwn_get_noise(&stats->rx.general); 2187 2188 /* Test that RSSI and noise are present in stats report. */ 2189 if (le32toh(stats->rx.general.flags) != 1) { 2190 DPRINTF(("received statistics without RSSI\n")); 2191 return; 2192 } 2193 2194 /* 2195 * XXX Differential gain calibration makes the 6005 firmware 2196 * crap out, so skip it for now. This effectively disables 2197 * sensitivity tuning as well. 2198 */ 2199 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2200 return; 2201 2202 if (calib->state == IWN_CALIB_STATE_ASSOC) 2203 iwn_collect_noise(sc, &stats->rx.general); 2204 else if (calib->state == IWN_CALIB_STATE_RUN) 2205 iwn_tune_sensitivity(sc, &stats->rx); 2206 } 2207 2208 /* 2209 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2210 * and 5000 adapters have different incompatible TX status formats. 2211 */ 2212 static void 2213 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2214 struct iwn_rx_data *data) 2215 { 2216 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2217 2218 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2219 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2220 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2221 } 2222 2223 static void 2224 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2225 struct iwn_rx_data *data) 2226 { 2227 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2228 2229 #ifdef notyet 2230 /* Reset TX scheduler slot. */ 2231 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2232 #endif 2233 2234 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2235 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2236 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2237 } 2238 2239 /* 2240 * Adapter-independent backend for TX_DONE firmware notifications. 2241 */ 2242 static void 2243 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2244 uint8_t status) 2245 { 2246 struct ieee80211com *ic = &sc->sc_ic; 2247 struct ifnet *ifp = ic->ic_ifp; 2248 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2249 struct iwn_tx_data *data = &ring->data[desc->idx]; 2250 struct iwn_node *wn = (struct iwn_node *)data->ni; 2251 2252 /* Update rate control statistics. */ 2253 wn->amn.amn_txcnt++; 2254 if (ackfailcnt > 0) 2255 wn->amn.amn_retrycnt++; 2256 2257 if (status != 1 && status != 2) 2258 ifp->if_oerrors++; 2259 else 2260 ifp->if_opackets++; 2261 2262 /* Unmap and free mbuf. */ 2263 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2264 BUS_DMASYNC_POSTWRITE); 2265 bus_dmamap_unload(sc->sc_dmat, data->map); 2266 m_freem(data->m); 2267 data->m = NULL; 2268 ieee80211_free_node(data->ni); 2269 data->ni = NULL; 2270 2271 sc->sc_tx_timer = 0; 2272 if (--ring->queued < IWN_TX_RING_LOMARK) { 2273 sc->qfullmsk &= ~(1 << ring->qid); 2274 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2275 ifp->if_flags &= ~IFF_OACTIVE; 2276 (*ifp->if_start)(ifp); 2277 } 2278 } 2279 } 2280 2281 /* 2282 * Process a "command done" firmware notification. This is where we wakeup 2283 * processes waiting for a synchronous command completion. 2284 */ 2285 static void 2286 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2287 { 2288 struct iwn_tx_ring *ring = &sc->txq[4]; 2289 struct iwn_tx_data *data; 2290 2291 if ((desc->qid & 0xf) != 4) 2292 return; /* Not a command ack. */ 2293 2294 data = &ring->data[desc->idx]; 2295 2296 /* If the command was mapped in an mbuf, free it. */ 2297 if (data->m != NULL) { 2298 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2299 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2300 bus_dmamap_unload(sc->sc_dmat, data->map); 2301 m_freem(data->m); 2302 data->m = NULL; 2303 } 2304 wakeup(&ring->desc[desc->idx]); 2305 } 2306 2307 /* 2308 * Process an INT_FH_RX or INT_SW_RX interrupt. 2309 */ 2310 static void 2311 iwn_notif_intr(struct iwn_softc *sc) 2312 { 2313 struct iwn_ops *ops = &sc->ops; 2314 struct ieee80211com *ic = &sc->sc_ic; 2315 struct ifnet *ifp = ic->ic_ifp; 2316 uint16_t hw; 2317 2318 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2319 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2320 2321 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2322 while (sc->rxq.cur != hw) { 2323 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2324 struct iwn_rx_desc *desc; 2325 2326 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2327 BUS_DMASYNC_POSTREAD); 2328 desc = mtod(data->m, struct iwn_rx_desc *); 2329 2330 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2331 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2332 2333 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2334 iwn_cmd_done(sc, desc); 2335 2336 switch (desc->type) { 2337 case IWN_RX_PHY: 2338 iwn_rx_phy(sc, desc, data); 2339 break; 2340 2341 case IWN_RX_DONE: /* 4965AGN only. */ 2342 case IWN_MPDU_RX_DONE: 2343 /* An 802.11 frame has been received. */ 2344 iwn_rx_done(sc, desc, data); 2345 break; 2346 #ifndef IEEE80211_NO_HT 2347 case IWN_RX_COMPRESSED_BA: 2348 /* A Compressed BlockAck has been received. */ 2349 iwn_rx_compressed_ba(sc, desc, data); 2350 break; 2351 #endif 2352 case IWN_TX_DONE: 2353 /* An 802.11 frame has been transmitted. */ 2354 ops->tx_done(sc, desc, data); 2355 break; 2356 2357 case IWN_RX_STATISTICS: 2358 case IWN_BEACON_STATISTICS: 2359 iwn_rx_statistics(sc, desc, data); 2360 break; 2361 2362 case IWN_BEACON_MISSED: 2363 { 2364 struct iwn_beacon_missed *miss = 2365 (struct iwn_beacon_missed *)(desc + 1); 2366 2367 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2368 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2369 /* 2370 * If more than 5 consecutive beacons are missed, 2371 * reinitialize the sensitivity state machine. 2372 */ 2373 DPRINTF(("beacons missed %d/%d\n", 2374 le32toh(miss->consecutive), le32toh(miss->total))); 2375 if (ic->ic_state == IEEE80211_S_RUN && 2376 le32toh(miss->consecutive) > 5) 2377 (void)iwn_init_sensitivity(sc); 2378 break; 2379 } 2380 case IWN_UC_READY: 2381 { 2382 struct iwn_ucode_info *uc = 2383 (struct iwn_ucode_info *)(desc + 1); 2384 2385 /* The microcontroller is ready. */ 2386 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2387 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2388 DPRINTF(("microcode alive notification version=%d.%d " 2389 "subtype=%x alive=%x\n", uc->major, uc->minor, 2390 uc->subtype, le32toh(uc->valid))); 2391 2392 if (le32toh(uc->valid) != 1) { 2393 aprint_error_dev(sc->sc_dev, 2394 "microcontroller initialization " 2395 "failed\n"); 2396 break; 2397 } 2398 if (uc->subtype == IWN_UCODE_INIT) { 2399 /* Save microcontroller report. */ 2400 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2401 } 2402 /* Save the address of the error log in SRAM. */ 2403 sc->errptr = le32toh(uc->errptr); 2404 break; 2405 } 2406 case IWN_STATE_CHANGED: 2407 { 2408 uint32_t *status = (uint32_t *)(desc + 1); 2409 2410 /* Enabled/disabled notification. */ 2411 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2412 sizeof (*status), BUS_DMASYNC_POSTREAD); 2413 DPRINTF(("state changed to %x\n", le32toh(*status))); 2414 2415 if (le32toh(*status) & 1) { 2416 /* The radio button has to be pushed. */ 2417 aprint_error_dev(sc->sc_dev, 2418 "Radio transmitter is off\n"); 2419 /* Turn the interface down. */ 2420 ifp->if_flags &= ~IFF_UP; 2421 iwn_stop(ifp, 1); 2422 return; /* No further processing. */ 2423 } 2424 break; 2425 } 2426 case IWN_START_SCAN: 2427 { 2428 struct iwn_start_scan *scan = 2429 (struct iwn_start_scan *)(desc + 1); 2430 2431 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2432 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2433 DPRINTFN(2, ("scanning channel %d status %x\n", 2434 scan->chan, le32toh(scan->status))); 2435 2436 /* Fix current channel. */ 2437 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2438 break; 2439 } 2440 case IWN_STOP_SCAN: 2441 { 2442 struct iwn_stop_scan *scan = 2443 (struct iwn_stop_scan *)(desc + 1); 2444 2445 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2446 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2447 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2448 scan->nchan, scan->status, scan->chan)); 2449 2450 if (scan->status == 1 && scan->chan <= 14 && 2451 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2452 /* 2453 * We just finished scanning 2GHz channels, 2454 * start scanning 5GHz ones. 2455 */ 2456 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2457 break; 2458 } 2459 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2460 ieee80211_end_scan(ic); 2461 break; 2462 } 2463 case IWN5000_CALIBRATION_RESULT: 2464 iwn5000_rx_calib_results(sc, desc, data); 2465 break; 2466 2467 case IWN5000_CALIBRATION_DONE: 2468 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2469 wakeup(sc); 2470 break; 2471 } 2472 2473 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2474 } 2475 2476 /* Tell the firmware what we have processed. */ 2477 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2478 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2479 } 2480 2481 /* 2482 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2483 * from power-down sleep mode. 2484 */ 2485 static void 2486 iwn_wakeup_intr(struct iwn_softc *sc) 2487 { 2488 int qid; 2489 2490 DPRINTF(("ucode wakeup from power-down sleep\n")); 2491 2492 /* Wakeup RX and TX rings. */ 2493 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2494 for (qid = 0; qid < sc->ntxqs; qid++) { 2495 struct iwn_tx_ring *ring = &sc->txq[qid]; 2496 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2497 } 2498 } 2499 2500 /* 2501 * Dump the error log of the firmware when a firmware panic occurs. Although 2502 * we can't debug the firmware because it is neither open source nor free, it 2503 * can help us to identify certain classes of problems. 2504 */ 2505 static void 2506 iwn_fatal_intr(struct iwn_softc *sc) 2507 { 2508 struct iwn_fw_dump dump; 2509 int i; 2510 2511 /* Force a complete recalibration on next init. */ 2512 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2513 2514 /* Check that the error log address is valid. */ 2515 if (sc->errptr < IWN_FW_DATA_BASE || 2516 sc->errptr + sizeof (dump) > 2517 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2518 aprint_error_dev(sc->sc_dev, 2519 "bad firmware error log address 0x%08x\n", sc->errptr); 2520 return; 2521 } 2522 if (iwn_nic_lock(sc) != 0) { 2523 aprint_error_dev(sc->sc_dev, 2524 "could not read firmware error log\n"); 2525 return; 2526 } 2527 /* Read firmware error log from SRAM. */ 2528 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2529 sizeof (dump) / sizeof (uint32_t)); 2530 iwn_nic_unlock(sc); 2531 2532 if (dump.valid == 0) { 2533 aprint_error_dev(sc->sc_dev, 2534 "firmware error log is empty\n"); 2535 return; 2536 } 2537 aprint_error("firmware error log:\n"); 2538 aprint_error(" error type = \"%s\" (0x%08X)\n", 2539 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2540 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2541 dump.id); 2542 aprint_error(" program counter = 0x%08X\n", dump.pc); 2543 aprint_error(" source line = 0x%08X\n", dump.src_line); 2544 aprint_error(" error data = 0x%08X%08X\n", 2545 dump.error_data[0], dump.error_data[1]); 2546 aprint_error(" branch link = 0x%08X%08X\n", 2547 dump.branch_link[0], dump.branch_link[1]); 2548 aprint_error(" interrupt link = 0x%08X%08X\n", 2549 dump.interrupt_link[0], dump.interrupt_link[1]); 2550 aprint_error(" time = %u\n", dump.time[0]); 2551 2552 /* Dump driver status (TX and RX rings) while we're here. */ 2553 aprint_error("driver status:\n"); 2554 for (i = 0; i < sc->ntxqs; i++) { 2555 struct iwn_tx_ring *ring = &sc->txq[i]; 2556 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2557 i, ring->qid, ring->cur, ring->queued); 2558 } 2559 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2560 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2561 } 2562 2563 static int 2564 iwn_intr(void *arg) 2565 { 2566 struct iwn_softc *sc = arg; 2567 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2568 uint32_t r1, r2, tmp; 2569 2570 /* Disable interrupts. */ 2571 IWN_WRITE(sc, IWN_INT_MASK, 0); 2572 2573 /* Read interrupts from ICT (fast) or from registers (slow). */ 2574 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2575 tmp = 0; 2576 while (sc->ict[sc->ict_cur] != 0) { 2577 tmp |= sc->ict[sc->ict_cur]; 2578 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2579 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2580 } 2581 tmp = le32toh(tmp); 2582 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2583 tmp = 0; 2584 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2585 tmp |= 0x8000; 2586 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2587 r2 = 0; /* Unused. */ 2588 } else { 2589 r1 = IWN_READ(sc, IWN_INT); 2590 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2591 return 0; /* Hardware gone! */ 2592 r2 = IWN_READ(sc, IWN_FH_INT); 2593 } 2594 if (r1 == 0 && r2 == 0) { 2595 if (ifp->if_flags & IFF_UP) 2596 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2597 return 0; /* Interrupt not for us. */ 2598 } 2599 2600 /* Acknowledge interrupts. */ 2601 IWN_WRITE(sc, IWN_INT, r1); 2602 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2603 IWN_WRITE(sc, IWN_FH_INT, r2); 2604 2605 if (r1 & IWN_INT_RF_TOGGLED) { 2606 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2607 aprint_error_dev(sc->sc_dev, 2608 "RF switch: radio %s\n", 2609 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2610 } 2611 if (r1 & IWN_INT_CT_REACHED) { 2612 aprint_error_dev(sc->sc_dev, 2613 "critical temperature reached!\n"); 2614 } 2615 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2616 aprint_error_dev(sc->sc_dev, 2617 "fatal firmware error\n"); 2618 /* Dump firmware error log and stop. */ 2619 iwn_fatal_intr(sc); 2620 ifp->if_flags &= ~IFF_UP; 2621 iwn_stop(ifp, 1); 2622 return 1; 2623 } 2624 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2625 (r2 & IWN_FH_INT_RX)) { 2626 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2627 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2628 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2629 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2630 IWN_INT_PERIODIC_DIS); 2631 iwn_notif_intr(sc); 2632 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2633 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2634 IWN_INT_PERIODIC_ENA); 2635 } 2636 } else 2637 iwn_notif_intr(sc); 2638 } 2639 2640 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2641 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2642 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2643 wakeup(sc); /* FH DMA transfer completed. */ 2644 } 2645 2646 if (r1 & IWN_INT_ALIVE) 2647 wakeup(sc); /* Firmware is alive. */ 2648 2649 if (r1 & IWN_INT_WAKEUP) 2650 iwn_wakeup_intr(sc); 2651 2652 /* Re-enable interrupts. */ 2653 if (ifp->if_flags & IFF_UP) 2654 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2655 2656 return 1; 2657 } 2658 2659 /* 2660 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2661 * 5000 adapters use a slightly different format). 2662 */ 2663 static void 2664 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2665 uint16_t len) 2666 { 2667 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2668 2669 *w = htole16(len + 8); 2670 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2671 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2672 sizeof (uint16_t), 2673 BUS_DMASYNC_PREWRITE); 2674 if (idx < IWN_SCHED_WINSZ) { 2675 *(w + IWN_TX_RING_COUNT) = *w; 2676 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2677 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2678 (char *)(void *)sc->sched_dma.vaddr, 2679 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2680 } 2681 } 2682 2683 static void 2684 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2685 uint16_t len) 2686 { 2687 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2688 2689 *w = htole16(id << 12 | (len + 8)); 2690 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2691 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2692 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2693 if (idx < IWN_SCHED_WINSZ) { 2694 *(w + IWN_TX_RING_COUNT) = *w; 2695 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2696 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2697 (char *)(void *)sc->sched_dma.vaddr, 2698 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2699 } 2700 } 2701 2702 #ifdef notyet 2703 static void 2704 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2705 { 2706 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2707 2708 *w = (*w & htole16(0xf000)) | htole16(1); 2709 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2710 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2711 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2712 if (idx < IWN_SCHED_WINSZ) { 2713 *(w + IWN_TX_RING_COUNT) = *w; 2714 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2715 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2716 (char *)(void *)sc->sched_dma.vaddr, 2717 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2718 } 2719 } 2720 #endif 2721 2722 static int 2723 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2724 { 2725 struct ieee80211com *ic = &sc->sc_ic; 2726 struct iwn_node *wn = (void *)ni; 2727 struct iwn_tx_ring *ring; 2728 struct iwn_tx_desc *desc; 2729 struct iwn_tx_data *data; 2730 struct iwn_tx_cmd *cmd; 2731 struct iwn_cmd_data *tx; 2732 const struct iwn_rate *rinfo; 2733 struct ieee80211_frame *wh; 2734 struct ieee80211_key *k = NULL; 2735 struct mbuf *m1; 2736 uint32_t flags; 2737 u_int hdrlen; 2738 bus_dma_segment_t *seg; 2739 uint8_t tid, ridx, txant, type; 2740 int i, totlen, error, pad; 2741 2742 const struct chanAccParams *cap; 2743 int noack; 2744 int hdrlen2; 2745 2746 wh = mtod(m, struct ieee80211_frame *); 2747 hdrlen = ieee80211_anyhdrsize(wh); 2748 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2749 2750 hdrlen2 = (ieee80211_has_qos(wh)) ? 2751 sizeof (struct ieee80211_qosframe) : 2752 sizeof (struct ieee80211_frame); 2753 2754 if (hdrlen != hdrlen2) 2755 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2756 hdrlen, hdrlen2); 2757 2758 /* XXX OpenBSD sets a different tid when using QOS */ 2759 tid = 0; 2760 if (ieee80211_has_qos(wh)) { 2761 cap = &ic->ic_wme.wme_chanParams; 2762 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2763 } 2764 else 2765 noack = 0; 2766 2767 ring = &sc->txq[ac]; 2768 desc = &ring->desc[ring->cur]; 2769 data = &ring->data[ring->cur]; 2770 2771 /* Choose a TX rate index. */ 2772 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2773 type != IEEE80211_FC0_TYPE_DATA) { 2774 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2775 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2776 } else if (ic->ic_fixed_rate != -1) { 2777 ridx = sc->fixed_ridx; 2778 } else 2779 ridx = wn->ridx[ni->ni_txrate]; 2780 rinfo = &iwn_rates[ridx]; 2781 2782 /* Encrypt the frame if need be. */ 2783 /* 2784 * XXX For now, NetBSD swaps the encryption and bpf sections 2785 * in order to match old code and other drivers. Tests with 2786 * tcpdump indicates that the order is irrelevant, however, 2787 * as bpf produces unencrypted data for both ordering choices. 2788 */ 2789 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2790 k = ieee80211_crypto_encap(ic, ni, m); 2791 if (k == NULL) { 2792 m_freem(m); 2793 return ENOBUFS; 2794 } 2795 /* Packet header may have moved, reset our local pointer. */ 2796 wh = mtod(m, struct ieee80211_frame *); 2797 } 2798 totlen = m->m_pkthdr.len; 2799 2800 if (sc->sc_drvbpf != NULL) { 2801 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2802 2803 tap->wt_flags = 0; 2804 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2805 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2806 tap->wt_rate = rinfo->rate; 2807 tap->wt_hwqueue = ac; 2808 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2809 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2810 2811 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2812 } 2813 2814 /* Prepare TX firmware command. */ 2815 cmd = &ring->cmd[ring->cur]; 2816 cmd->code = IWN_CMD_TX_DATA; 2817 cmd->flags = 0; 2818 cmd->qid = ring->qid; 2819 cmd->idx = ring->cur; 2820 2821 tx = (struct iwn_cmd_data *)cmd->data; 2822 /* NB: No need to clear tx, all fields are reinitialized here. */ 2823 tx->scratch = 0; /* clear "scratch" area */ 2824 2825 flags = 0; 2826 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2827 /* Unicast frame, check if an ACK is expected. */ 2828 if (!noack) 2829 flags |= IWN_TX_NEED_ACK; 2830 } 2831 2832 #ifdef notyet 2833 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2834 if ((wh->i_fc[0] & 2835 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2836 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2837 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2838 #endif 2839 2840 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2841 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2842 2843 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2844 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2845 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2846 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2847 flags |= IWN_TX_NEED_RTS; 2848 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2849 ridx >= IWN_RIDX_OFDM6) { 2850 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2851 flags |= IWN_TX_NEED_CTS; 2852 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2853 flags |= IWN_TX_NEED_RTS; 2854 } 2855 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2856 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2857 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2858 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2859 flags |= IWN_TX_NEED_PROTECTION; 2860 } else 2861 flags |= IWN_TX_FULL_TXOP; 2862 } 2863 } 2864 2865 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2866 type != IEEE80211_FC0_TYPE_DATA) 2867 tx->id = sc->broadcast_id; 2868 else 2869 tx->id = wn->id; 2870 2871 if (type == IEEE80211_FC0_TYPE_MGT) { 2872 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2873 2874 #ifndef IEEE80211_STA_ONLY 2875 /* Tell HW to set timestamp in probe responses. */ 2876 /* XXX NetBSD rev 1.11 added probe requests here but */ 2877 /* probe requests do not take timestamps (from Bergamini). */ 2878 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2879 flags |= IWN_TX_INSERT_TSTAMP; 2880 #endif 2881 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2882 /* changes here. These are not needed (from Bergamini). */ 2883 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2884 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2885 tx->timeout = htole16(3); 2886 else 2887 tx->timeout = htole16(2); 2888 } else 2889 tx->timeout = htole16(0); 2890 2891 if (hdrlen & 3) { 2892 /* First segment length must be a multiple of 4. */ 2893 flags |= IWN_TX_NEED_PADDING; 2894 pad = 4 - (hdrlen & 3); 2895 } else 2896 pad = 0; 2897 2898 tx->len = htole16(totlen); 2899 tx->tid = tid; 2900 tx->rts_ntries = 60; 2901 tx->data_ntries = 15; 2902 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2903 tx->plcp = rinfo->plcp; 2904 tx->rflags = rinfo->flags; 2905 if (tx->id == sc->broadcast_id) { 2906 /* Group or management frame. */ 2907 tx->linkq = 0; 2908 /* XXX Alternate between antenna A and B? */ 2909 txant = IWN_LSB(sc->txchainmask); 2910 tx->rflags |= IWN_RFLAG_ANT(txant); 2911 } else { 2912 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2913 flags |= IWN_TX_LINKQ; /* enable MRR */ 2914 } 2915 /* Set physical address of "scratch area". */ 2916 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2917 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2918 2919 /* Copy 802.11 header in TX command. */ 2920 /* XXX NetBSD changed this in rev 1.20 */ 2921 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2922 2923 /* Trim 802.11 header. */ 2924 m_adj(m, hdrlen); 2925 tx->security = 0; 2926 tx->flags = htole32(flags); 2927 2928 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2929 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2930 if (error != 0) { 2931 if (error != EFBIG) { 2932 aprint_error_dev(sc->sc_dev, 2933 "can't map mbuf (error %d)\n", error); 2934 m_freem(m); 2935 return error; 2936 } 2937 /* Too many DMA segments, linearize mbuf. */ 2938 MGETHDR(m1, M_DONTWAIT, MT_DATA); 2939 if (m1 == NULL) { 2940 m_freem(m); 2941 return ENOBUFS; 2942 } 2943 if (m->m_pkthdr.len > MHLEN) { 2944 MCLGET(m1, M_DONTWAIT); 2945 if (!(m1->m_flags & M_EXT)) { 2946 m_freem(m); 2947 m_freem(m1); 2948 return ENOBUFS; 2949 } 2950 } 2951 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 2952 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 2953 m_freem(m); 2954 m = m1; 2955 2956 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2957 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2958 if (error != 0) { 2959 aprint_error_dev(sc->sc_dev, 2960 "can't map mbuf (error %d)\n", error); 2961 m_freem(m); 2962 return error; 2963 } 2964 } 2965 2966 data->m = m; 2967 data->ni = ni; 2968 2969 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 2970 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 2971 2972 /* Fill TX descriptor. */ 2973 desc->nsegs = 1 + data->map->dm_nsegs; 2974 /* First DMA segment is used by the TX command. */ 2975 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 2976 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 2977 (4 + sizeof (*tx) + hdrlen + pad) << 4); 2978 /* Other DMA segments are for data payload. */ 2979 seg = data->map->dm_segs; 2980 for (i = 1; i <= data->map->dm_nsegs; i++) { 2981 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 2982 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 2983 seg->ds_len << 4); 2984 seg++; 2985 } 2986 2987 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2988 BUS_DMASYNC_PREWRITE); 2989 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 2990 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 2991 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 2992 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2993 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 2994 sizeof (*desc), BUS_DMASYNC_PREWRITE); 2995 2996 #ifdef notyet 2997 /* Update TX scheduler. */ 2998 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 2999 #endif 3000 3001 /* Kick TX ring. */ 3002 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3003 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3004 3005 /* Mark TX ring as full if we reach a certain threshold. */ 3006 if (++ring->queued > IWN_TX_RING_HIMARK) 3007 sc->qfullmsk |= 1 << ring->qid; 3008 3009 return 0; 3010 } 3011 3012 static void 3013 iwn_start(struct ifnet *ifp) 3014 { 3015 struct iwn_softc *sc = ifp->if_softc; 3016 struct ieee80211com *ic = &sc->sc_ic; 3017 struct ieee80211_node *ni; 3018 struct ether_header *eh; 3019 struct mbuf *m; 3020 int ac; 3021 3022 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3023 return; 3024 3025 for (;;) { 3026 if (sc->qfullmsk != 0) { 3027 ifp->if_flags |= IFF_OACTIVE; 3028 break; 3029 } 3030 /* Send pending management frames first. */ 3031 IF_DEQUEUE(&ic->ic_mgtq, m); 3032 if (m != NULL) { 3033 ni = (void *)m->m_pkthdr.rcvif; 3034 ac = 0; 3035 goto sendit; 3036 } 3037 if (ic->ic_state != IEEE80211_S_RUN) 3038 break; 3039 3040 /* Encapsulate and send data frames. */ 3041 IFQ_DEQUEUE(&ifp->if_snd, m); 3042 if (m == NULL) 3043 break; 3044 if (m->m_len < sizeof (*eh) && 3045 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3046 ifp->if_oerrors++; 3047 continue; 3048 } 3049 eh = mtod(m, struct ether_header *); 3050 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3051 if (ni == NULL) { 3052 m_freem(m); 3053 ifp->if_oerrors++; 3054 continue; 3055 } 3056 /* classify mbuf so we can find which tx ring to use */ 3057 if (ieee80211_classify(ic, m, ni) != 0) { 3058 m_freem(m); 3059 ieee80211_free_node(ni); 3060 ifp->if_oerrors++; 3061 continue; 3062 } 3063 3064 /* No QoS encapsulation for EAPOL frames. */ 3065 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3066 M_WME_GETAC(m) : WME_AC_BE; 3067 3068 bpf_mtap(ifp, m); 3069 3070 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3071 ieee80211_free_node(ni); 3072 ifp->if_oerrors++; 3073 continue; 3074 } 3075 sendit: 3076 bpf_mtap3(ic->ic_rawbpf, m); 3077 3078 if (iwn_tx(sc, m, ni, ac) != 0) { 3079 ieee80211_free_node(ni); 3080 ifp->if_oerrors++; 3081 continue; 3082 } 3083 3084 sc->sc_tx_timer = 5; 3085 ifp->if_timer = 1; 3086 } 3087 } 3088 3089 static void 3090 iwn_watchdog(struct ifnet *ifp) 3091 { 3092 struct iwn_softc *sc = ifp->if_softc; 3093 3094 ifp->if_timer = 0; 3095 3096 if (sc->sc_tx_timer > 0) { 3097 if (--sc->sc_tx_timer == 0) { 3098 aprint_error_dev(sc->sc_dev, 3099 "device timeout\n"); 3100 ifp->if_flags &= ~IFF_UP; 3101 iwn_stop(ifp, 1); 3102 ifp->if_oerrors++; 3103 return; 3104 } 3105 ifp->if_timer = 1; 3106 } 3107 3108 ieee80211_watchdog(&sc->sc_ic); 3109 } 3110 3111 static int 3112 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3113 { 3114 struct iwn_softc *sc = ifp->if_softc; 3115 struct ieee80211com *ic = &sc->sc_ic; 3116 struct ifaddr *ifa; 3117 const struct sockaddr *sa; 3118 int s, error = 0; 3119 3120 s = splnet(); 3121 3122 switch (cmd) { 3123 case SIOCSIFADDR: 3124 ifa = (struct ifaddr *)data; 3125 ifp->if_flags |= IFF_UP; 3126 #ifdef INET 3127 if (ifa->ifa_addr->sa_family == AF_INET) 3128 arp_ifinit(&ic->ic_ac, ifa); 3129 #endif 3130 /* FALLTHROUGH */ 3131 case SIOCSIFFLAGS: 3132 /* XXX Added as it is in every NetBSD driver */ 3133 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3134 break; 3135 if (ifp->if_flags & IFF_UP) { 3136 if (!(ifp->if_flags & IFF_RUNNING)) 3137 error = iwn_init(ifp); 3138 } else { 3139 if (ifp->if_flags & IFF_RUNNING) 3140 iwn_stop(ifp, 1); 3141 } 3142 break; 3143 3144 case SIOCADDMULTI: 3145 case SIOCDELMULTI: 3146 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3147 error = (cmd == SIOCADDMULTI) ? 3148 ether_addmulti(sa, &sc->sc_ec) : 3149 ether_delmulti(sa, &sc->sc_ec); 3150 3151 if (error == ENETRESET) 3152 error = 0; 3153 break; 3154 3155 default: 3156 error = ieee80211_ioctl(ic, cmd, data); 3157 } 3158 3159 if (error == ENETRESET) { 3160 error = 0; 3161 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3162 (IFF_UP | IFF_RUNNING)) { 3163 iwn_stop(ifp, 0); 3164 error = iwn_init(ifp); 3165 } 3166 } 3167 3168 splx(s); 3169 return error; 3170 } 3171 3172 /* 3173 * Send a command to the firmware. 3174 */ 3175 static int 3176 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3177 { 3178 struct iwn_tx_ring *ring = &sc->txq[4]; 3179 struct iwn_tx_desc *desc; 3180 struct iwn_tx_data *data; 3181 struct iwn_tx_cmd *cmd; 3182 struct mbuf *m; 3183 bus_addr_t paddr; 3184 int totlen, error; 3185 3186 desc = &ring->desc[ring->cur]; 3187 data = &ring->data[ring->cur]; 3188 totlen = 4 + size; 3189 3190 if (size > sizeof cmd->data) { 3191 /* Command is too large to fit in a descriptor. */ 3192 if (totlen > MCLBYTES) 3193 return EINVAL; 3194 MGETHDR(m, M_DONTWAIT, MT_DATA); 3195 if (m == NULL) 3196 return ENOMEM; 3197 if (totlen > MHLEN) { 3198 MCLGET(m, M_DONTWAIT); 3199 if (!(m->m_flags & M_EXT)) { 3200 m_freem(m); 3201 return ENOMEM; 3202 } 3203 } 3204 cmd = mtod(m, struct iwn_tx_cmd *); 3205 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3206 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3207 if (error != 0) { 3208 m_freem(m); 3209 return error; 3210 } 3211 data->m = m; 3212 paddr = data->map->dm_segs[0].ds_addr; 3213 } else { 3214 cmd = &ring->cmd[ring->cur]; 3215 paddr = data->cmd_paddr; 3216 } 3217 3218 cmd->code = code; 3219 cmd->flags = 0; 3220 cmd->qid = ring->qid; 3221 cmd->idx = ring->cur; 3222 memcpy(cmd->data, buf, size); 3223 3224 desc->nsegs = 1; 3225 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3226 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3227 3228 if (size > sizeof cmd->data) { 3229 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3230 BUS_DMASYNC_PREWRITE); 3231 } else { 3232 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3233 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3234 totlen, BUS_DMASYNC_PREWRITE); 3235 } 3236 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3237 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3238 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3239 3240 #ifdef notyet 3241 /* Update TX scheduler. */ 3242 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3243 #endif 3244 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3245 3246 /* Kick command ring. */ 3247 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3248 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3249 3250 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3251 } 3252 3253 static int 3254 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3255 { 3256 struct iwn4965_node_info hnode; 3257 char *src, *dst; 3258 3259 /* 3260 * We use the node structure for 5000 Series internally (it is 3261 * a superset of the one for 4965AGN). We thus copy the common 3262 * fields before sending the command. 3263 */ 3264 src = (char *)node; 3265 dst = (char *)&hnode; 3266 memcpy(dst, src, 48); 3267 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3268 memcpy(dst + 48, src + 72, 20); 3269 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3270 } 3271 3272 static int 3273 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3274 { 3275 /* Direct mapping. */ 3276 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3277 } 3278 3279 static int 3280 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3281 { 3282 struct iwn_node *wn = (void *)ni; 3283 struct ieee80211_rateset *rs = &ni->ni_rates; 3284 struct iwn_cmd_link_quality linkq; 3285 const struct iwn_rate *rinfo; 3286 uint8_t txant; 3287 int i, txrate; 3288 3289 /* Use the first valid TX antenna. */ 3290 txant = IWN_LSB(sc->txchainmask); 3291 3292 memset(&linkq, 0, sizeof linkq); 3293 linkq.id = wn->id; 3294 linkq.antmsk_1stream = txant; 3295 linkq.antmsk_2stream = IWN_ANT_AB; 3296 linkq.ampdu_max = 31; 3297 linkq.ampdu_threshold = 3; 3298 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3299 3300 /* Start at highest available bit-rate. */ 3301 txrate = rs->rs_nrates - 1; 3302 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3303 rinfo = &iwn_rates[wn->ridx[txrate]]; 3304 linkq.retry[i].plcp = rinfo->plcp; 3305 linkq.retry[i].rflags = rinfo->flags; 3306 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3307 /* Next retry at immediate lower bit-rate. */ 3308 if (txrate > 0) 3309 txrate--; 3310 } 3311 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3312 } 3313 3314 /* 3315 * Broadcast node is used to send group-addressed and management frames. 3316 */ 3317 static int 3318 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3319 { 3320 struct iwn_ops *ops = &sc->ops; 3321 struct iwn_node_info node; 3322 struct iwn_cmd_link_quality linkq; 3323 const struct iwn_rate *rinfo; 3324 uint8_t txant; 3325 int i, error; 3326 3327 memset(&node, 0, sizeof node); 3328 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3329 node.id = sc->broadcast_id; 3330 DPRINTF(("adding broadcast node\n")); 3331 if ((error = ops->add_node(sc, &node, async)) != 0) 3332 return error; 3333 3334 /* Use the first valid TX antenna. */ 3335 txant = IWN_LSB(sc->txchainmask); 3336 3337 memset(&linkq, 0, sizeof linkq); 3338 linkq.id = sc->broadcast_id; 3339 linkq.antmsk_1stream = txant; 3340 linkq.antmsk_2stream = IWN_ANT_AB; 3341 linkq.ampdu_max = 64; 3342 linkq.ampdu_threshold = 3; 3343 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3344 3345 /* Use lowest mandatory bit-rate. */ 3346 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3347 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3348 linkq.retry[0].plcp = rinfo->plcp; 3349 linkq.retry[0].rflags = rinfo->flags; 3350 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3351 /* Use same bit-rate for all TX retries. */ 3352 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3353 linkq.retry[i].plcp = linkq.retry[0].plcp; 3354 linkq.retry[i].rflags = linkq.retry[0].rflags; 3355 } 3356 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3357 } 3358 3359 static void 3360 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3361 { 3362 struct iwn_cmd_led led; 3363 3364 /* Clear microcode LED ownership. */ 3365 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3366 3367 led.which = which; 3368 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3369 led.off = off; 3370 led.on = on; 3371 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3372 } 3373 3374 /* 3375 * Set the critical temperature at which the firmware will stop the radio 3376 * and notify us. 3377 */ 3378 static int 3379 iwn_set_critical_temp(struct iwn_softc *sc) 3380 { 3381 struct iwn_critical_temp crit; 3382 int32_t temp; 3383 3384 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3385 3386 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3387 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3388 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3389 temp = IWN_CTOK(110); 3390 else 3391 temp = 110; 3392 memset(&crit, 0, sizeof crit); 3393 crit.tempR = htole32(temp); 3394 DPRINTF(("setting critical temperature to %d\n", temp)); 3395 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3396 } 3397 3398 static int 3399 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3400 { 3401 struct iwn_cmd_timing cmd; 3402 uint64_t val, mod; 3403 3404 memset(&cmd, 0, sizeof cmd); 3405 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3406 cmd.bintval = htole16(ni->ni_intval); 3407 cmd.lintval = htole16(10); 3408 3409 /* Compute remaining time until next beacon. */ 3410 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3411 mod = le64toh(cmd.tstamp) % val; 3412 cmd.binitval = htole32((uint32_t)(val - mod)); 3413 3414 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3415 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3416 3417 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3418 } 3419 3420 static void 3421 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3422 { 3423 /* Adjust TX power if need be (delta >= 3 degC). */ 3424 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3425 if (abs(temp - sc->temp) >= 3) { 3426 /* Record temperature of last calibration. */ 3427 sc->temp = temp; 3428 (void)iwn4965_set_txpower(sc, 1); 3429 } 3430 } 3431 3432 /* 3433 * Set TX power for current channel (each rate has its own power settings). 3434 * This function takes into account the regulatory information from EEPROM, 3435 * the current temperature and the current voltage. 3436 */ 3437 static int 3438 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3439 { 3440 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3441 #define fdivround(a, b, n) \ 3442 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3443 /* Linear interpolation. */ 3444 #define interpolate(x, x1, y1, x2, y2, n) \ 3445 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3446 3447 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3448 struct ieee80211com *ic = &sc->sc_ic; 3449 struct iwn_ucode_info *uc = &sc->ucode_info; 3450 struct ieee80211_channel *ch; 3451 struct iwn4965_cmd_txpower cmd; 3452 struct iwn4965_eeprom_chan_samples *chans; 3453 const uint8_t *rf_gain, *dsp_gain; 3454 int32_t vdiff, tdiff; 3455 int i, c, grp, maxpwr; 3456 uint8_t chan; 3457 3458 /* Retrieve current channel from last RXON. */ 3459 chan = sc->rxon.chan; 3460 DPRINTF(("setting TX power for channel %d\n", chan)); 3461 ch = &ic->ic_channels[chan]; 3462 3463 memset(&cmd, 0, sizeof cmd); 3464 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3465 cmd.chan = chan; 3466 3467 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3468 maxpwr = sc->maxpwr5GHz; 3469 rf_gain = iwn4965_rf_gain_5ghz; 3470 dsp_gain = iwn4965_dsp_gain_5ghz; 3471 } else { 3472 maxpwr = sc->maxpwr2GHz; 3473 rf_gain = iwn4965_rf_gain_2ghz; 3474 dsp_gain = iwn4965_dsp_gain_2ghz; 3475 } 3476 3477 /* Compute voltage compensation. */ 3478 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3479 if (vdiff > 0) 3480 vdiff *= 2; 3481 if (abs(vdiff) > 2) 3482 vdiff = 0; 3483 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3484 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3485 3486 /* Get channel attenuation group. */ 3487 if (chan <= 20) /* 1-20 */ 3488 grp = 4; 3489 else if (chan <= 43) /* 34-43 */ 3490 grp = 0; 3491 else if (chan <= 70) /* 44-70 */ 3492 grp = 1; 3493 else if (chan <= 124) /* 71-124 */ 3494 grp = 2; 3495 else /* 125-200 */ 3496 grp = 3; 3497 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3498 3499 /* Get channel sub-band. */ 3500 for (i = 0; i < IWN_NBANDS; i++) 3501 if (sc->bands[i].lo != 0 && 3502 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3503 break; 3504 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3505 return EINVAL; 3506 chans = sc->bands[i].chans; 3507 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3508 3509 for (c = 0; c < 2; c++) { 3510 uint8_t power, gain, temp; 3511 int maxchpwr, pwr, ridx, idx; 3512 3513 power = interpolate(chan, 3514 chans[0].num, chans[0].samples[c][1].power, 3515 chans[1].num, chans[1].samples[c][1].power, 1); 3516 gain = interpolate(chan, 3517 chans[0].num, chans[0].samples[c][1].gain, 3518 chans[1].num, chans[1].samples[c][1].gain, 1); 3519 temp = interpolate(chan, 3520 chans[0].num, chans[0].samples[c][1].temp, 3521 chans[1].num, chans[1].samples[c][1].temp, 1); 3522 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3523 c, power, gain, temp)); 3524 3525 /* Compute temperature compensation. */ 3526 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3527 DPRINTF(("temperature compensation=%d (current=%d, " 3528 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3529 3530 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3531 /* Convert dBm to half-dBm. */ 3532 maxchpwr = sc->maxpwr[chan] * 2; 3533 if ((ridx / 8) & 1) 3534 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3535 3536 pwr = maxpwr; 3537 3538 /* Adjust TX power based on rate. */ 3539 if ((ridx % 8) == 5) 3540 pwr -= 15; /* OFDM48: -7.5dB */ 3541 else if ((ridx % 8) == 6) 3542 pwr -= 17; /* OFDM54: -8.5dB */ 3543 else if ((ridx % 8) == 7) 3544 pwr -= 20; /* OFDM60: -10dB */ 3545 else 3546 pwr -= 10; /* Others: -5dB */ 3547 3548 /* Do not exceed channel max TX power. */ 3549 if (pwr > maxchpwr) 3550 pwr = maxchpwr; 3551 3552 idx = gain - (pwr - power) - tdiff - vdiff; 3553 if ((ridx / 8) & 1) /* MIMO */ 3554 idx += (int32_t)le32toh(uc->atten[grp][c]); 3555 3556 if (cmd.band == 0) 3557 idx += 9; /* 5GHz */ 3558 if (ridx == IWN_RIDX_MAX) 3559 idx += 5; /* CCK */ 3560 3561 /* Make sure idx stays in a valid range. */ 3562 if (idx < 0) 3563 idx = 0; 3564 else if (idx > IWN4965_MAX_PWR_INDEX) 3565 idx = IWN4965_MAX_PWR_INDEX; 3566 3567 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3568 c, ridx, idx)); 3569 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3570 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3571 } 3572 } 3573 3574 DPRINTF(("setting TX power for chan %d\n", chan)); 3575 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3576 3577 #undef interpolate 3578 #undef fdivround 3579 } 3580 3581 static int 3582 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3583 { 3584 struct iwn5000_cmd_txpower cmd; 3585 3586 /* 3587 * TX power calibration is handled automatically by the firmware 3588 * for 5000 Series. 3589 */ 3590 memset(&cmd, 0, sizeof cmd); 3591 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3592 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3593 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3594 DPRINTF(("setting TX power\n")); 3595 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3596 } 3597 3598 /* 3599 * Retrieve the maximum RSSI (in dBm) among receivers. 3600 */ 3601 static int 3602 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3603 { 3604 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3605 uint8_t mask, agc; 3606 int rssi; 3607 3608 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3609 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3610 3611 rssi = 0; 3612 if (mask & IWN_ANT_A) 3613 rssi = MAX(rssi, phy->rssi[0]); 3614 if (mask & IWN_ANT_B) 3615 rssi = MAX(rssi, phy->rssi[2]); 3616 if (mask & IWN_ANT_C) 3617 rssi = MAX(rssi, phy->rssi[4]); 3618 3619 return rssi - agc - IWN_RSSI_TO_DBM; 3620 } 3621 3622 static int 3623 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3624 { 3625 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3626 uint8_t agc; 3627 int rssi; 3628 3629 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3630 3631 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3632 le16toh(phy->rssi[1]) & 0xff); 3633 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3634 3635 return rssi - agc - IWN_RSSI_TO_DBM; 3636 } 3637 3638 /* 3639 * Retrieve the average noise (in dBm) among receivers. 3640 */ 3641 static int 3642 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3643 { 3644 int i, total, nbant, noise; 3645 3646 total = nbant = 0; 3647 for (i = 0; i < 3; i++) { 3648 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3649 continue; 3650 total += noise; 3651 nbant++; 3652 } 3653 /* There should be at least one antenna but check anyway. */ 3654 return (nbant == 0) ? -127 : (total / nbant) - 107; 3655 } 3656 3657 /* 3658 * Compute temperature (in degC) from last received statistics. 3659 */ 3660 static int 3661 iwn4965_get_temperature(struct iwn_softc *sc) 3662 { 3663 struct iwn_ucode_info *uc = &sc->ucode_info; 3664 int32_t r1, r2, r3, r4, temp; 3665 3666 r1 = le32toh(uc->temp[0].chan20MHz); 3667 r2 = le32toh(uc->temp[1].chan20MHz); 3668 r3 = le32toh(uc->temp[2].chan20MHz); 3669 r4 = le32toh(sc->rawtemp); 3670 3671 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3672 return 0; 3673 3674 /* Sign-extend 23-bit R4 value to 32-bit. */ 3675 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3676 /* Compute temperature in Kelvin. */ 3677 temp = (259 * (r4 - r2)) / (r3 - r1); 3678 temp = (temp * 97) / 100 + 8; 3679 3680 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3681 return IWN_KTOC(temp); 3682 } 3683 3684 static int 3685 iwn5000_get_temperature(struct iwn_softc *sc) 3686 { 3687 int32_t temp; 3688 3689 /* 3690 * Temperature is not used by the driver for 5000 Series because 3691 * TX power calibration is handled by firmware. We export it to 3692 * users through the sensor framework though. 3693 */ 3694 temp = le32toh(sc->rawtemp); 3695 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3696 temp = (temp / -5) + sc->temp_off; 3697 temp = IWN_KTOC(temp); 3698 } 3699 return temp; 3700 } 3701 3702 /* 3703 * Initialize sensitivity calibration state machine. 3704 */ 3705 static int 3706 iwn_init_sensitivity(struct iwn_softc *sc) 3707 { 3708 struct iwn_ops *ops = &sc->ops; 3709 struct iwn_calib_state *calib = &sc->calib; 3710 uint32_t flags; 3711 int error; 3712 3713 /* Reset calibration state machine. */ 3714 memset(calib, 0, sizeof (*calib)); 3715 calib->state = IWN_CALIB_STATE_INIT; 3716 calib->cck_state = IWN_CCK_STATE_HIFA; 3717 /* Set initial correlation values. */ 3718 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3719 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3720 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3721 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3722 calib->cck_x4 = 125; 3723 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3724 calib->energy_cck = sc->limits->energy_cck; 3725 3726 /* Write initial sensitivity. */ 3727 if ((error = iwn_send_sensitivity(sc)) != 0) 3728 return error; 3729 3730 /* Write initial gains. */ 3731 if ((error = ops->init_gains(sc)) != 0) 3732 return error; 3733 3734 /* Request statistics at each beacon interval. */ 3735 flags = 0; 3736 DPRINTF(("sending request for statistics\n")); 3737 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3738 } 3739 3740 /* 3741 * Collect noise and RSSI statistics for the first 20 beacons received 3742 * after association and use them to determine connected antennas and 3743 * to set differential gains. 3744 */ 3745 static void 3746 iwn_collect_noise(struct iwn_softc *sc, 3747 const struct iwn_rx_general_stats *stats) 3748 { 3749 struct iwn_ops *ops = &sc->ops; 3750 struct iwn_calib_state *calib = &sc->calib; 3751 uint32_t val; 3752 int i; 3753 3754 /* Accumulate RSSI and noise for all 3 antennas. */ 3755 for (i = 0; i < 3; i++) { 3756 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3757 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3758 } 3759 /* NB: We update differential gains only once after 20 beacons. */ 3760 if (++calib->nbeacons < 20) 3761 return; 3762 3763 /* Determine highest average RSSI. */ 3764 val = MAX(calib->rssi[0], calib->rssi[1]); 3765 val = MAX(calib->rssi[2], val); 3766 3767 /* Determine which antennas are connected. */ 3768 sc->chainmask = sc->rxchainmask; 3769 for (i = 0; i < 3; i++) 3770 if (val - calib->rssi[i] > 15 * 20) 3771 sc->chainmask &= ~(1 << i); 3772 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3773 sc->rxchainmask, sc->chainmask)); 3774 3775 /* If none of the TX antennas are connected, keep at least one. */ 3776 if ((sc->chainmask & sc->txchainmask) == 0) 3777 sc->chainmask |= IWN_LSB(sc->txchainmask); 3778 3779 (void)ops->set_gains(sc); 3780 calib->state = IWN_CALIB_STATE_RUN; 3781 3782 #ifdef notyet 3783 /* XXX Disable RX chains with no antennas connected. */ 3784 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3785 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3786 #endif 3787 3788 /* Enable power-saving mode if requested by user. */ 3789 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3790 (void)iwn_set_pslevel(sc, 0, 3, 1); 3791 } 3792 3793 static int 3794 iwn4965_init_gains(struct iwn_softc *sc) 3795 { 3796 struct iwn_phy_calib_gain cmd; 3797 3798 memset(&cmd, 0, sizeof cmd); 3799 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3800 /* Differential gains initially set to 0 for all 3 antennas. */ 3801 DPRINTF(("setting initial differential gains\n")); 3802 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3803 } 3804 3805 static int 3806 iwn5000_init_gains(struct iwn_softc *sc) 3807 { 3808 struct iwn_phy_calib cmd; 3809 3810 memset(&cmd, 0, sizeof cmd); 3811 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 3812 cmd.ngroups = 1; 3813 cmd.isvalid = 1; 3814 DPRINTF(("setting initial differential gains\n")); 3815 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3816 } 3817 3818 static int 3819 iwn4965_set_gains(struct iwn_softc *sc) 3820 { 3821 struct iwn_calib_state *calib = &sc->calib; 3822 struct iwn_phy_calib_gain cmd; 3823 int i, delta, noise; 3824 3825 /* Get minimal noise among connected antennas. */ 3826 noise = INT_MAX; /* NB: There's at least one antenna. */ 3827 for (i = 0; i < 3; i++) 3828 if (sc->chainmask & (1 << i)) 3829 noise = MIN(calib->noise[i], noise); 3830 3831 memset(&cmd, 0, sizeof cmd); 3832 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3833 /* Set differential gains for connected antennas. */ 3834 for (i = 0; i < 3; i++) { 3835 if (sc->chainmask & (1 << i)) { 3836 /* Compute attenuation (in unit of 1.5dB). */ 3837 delta = (noise - (int32_t)calib->noise[i]) / 30; 3838 /* NB: delta <= 0 */ 3839 /* Limit to [-4.5dB,0]. */ 3840 cmd.gain[i] = MIN(abs(delta), 3); 3841 if (delta < 0) 3842 cmd.gain[i] |= 1 << 2; /* sign bit */ 3843 } 3844 } 3845 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3846 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3847 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3848 } 3849 3850 static int 3851 iwn5000_set_gains(struct iwn_softc *sc) 3852 { 3853 struct iwn_calib_state *calib = &sc->calib; 3854 struct iwn_phy_calib_gain cmd; 3855 int i, ant, div, delta; 3856 3857 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3858 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3859 3860 memset(&cmd, 0, sizeof cmd); 3861 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN; 3862 cmd.ngroups = 1; 3863 cmd.isvalid = 1; 3864 /* Get first available RX antenna as referential. */ 3865 ant = IWN_LSB(sc->rxchainmask); 3866 /* Set differential gains for other antennas. */ 3867 for (i = ant + 1; i < 3; i++) { 3868 if (sc->chainmask & (1 << i)) { 3869 /* The delta is relative to antenna "ant". */ 3870 delta = ((int32_t)calib->noise[ant] - 3871 (int32_t)calib->noise[i]) / div; 3872 /* Limit to [-4.5dB,+4.5dB]. */ 3873 cmd.gain[i - 1] = MIN(abs(delta), 3); 3874 if (delta < 0) 3875 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3876 } 3877 } 3878 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3879 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3880 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3881 } 3882 3883 /* 3884 * Tune RF RX sensitivity based on the number of false alarms detected 3885 * during the last beacon period. 3886 */ 3887 static void 3888 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3889 { 3890 #define inc(val, inc, max) \ 3891 if ((val) < (max)) { \ 3892 if ((val) < (max) - (inc)) \ 3893 (val) += (inc); \ 3894 else \ 3895 (val) = (max); \ 3896 needs_update = 1; \ 3897 } 3898 #define dec(val, dec, min) \ 3899 if ((val) > (min)) { \ 3900 if ((val) > (min) + (dec)) \ 3901 (val) -= (dec); \ 3902 else \ 3903 (val) = (min); \ 3904 needs_update = 1; \ 3905 } 3906 3907 const struct iwn_sensitivity_limits *limits = sc->limits; 3908 struct iwn_calib_state *calib = &sc->calib; 3909 uint32_t val, rxena, fa; 3910 uint32_t energy[3], energy_min; 3911 uint8_t noise[3], noise_ref; 3912 int i, needs_update = 0; 3913 3914 /* Check that we've been enabled long enough. */ 3915 if ((rxena = le32toh(stats->general.load)) == 0) 3916 return; 3917 3918 /* Compute number of false alarms since last call for OFDM. */ 3919 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3920 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3921 fa *= 200 * 1024; /* 200TU */ 3922 3923 /* Save counters values for next call. */ 3924 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3925 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3926 3927 if (fa > 50 * rxena) { 3928 /* High false alarm count, decrease sensitivity. */ 3929 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3930 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3931 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3932 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3933 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3934 3935 } else if (fa < 5 * rxena) { 3936 /* Low false alarm count, increase sensitivity. */ 3937 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3938 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 3939 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 3940 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 3941 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 3942 } 3943 3944 /* Compute maximum noise among 3 receivers. */ 3945 for (i = 0; i < 3; i++) 3946 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 3947 val = MAX(noise[0], noise[1]); 3948 val = MAX(noise[2], val); 3949 /* Insert it into our samples table. */ 3950 calib->noise_samples[calib->cur_noise_sample] = val; 3951 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 3952 3953 /* Compute maximum noise among last 20 samples. */ 3954 noise_ref = calib->noise_samples[0]; 3955 for (i = 1; i < 20; i++) 3956 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 3957 3958 /* Compute maximum energy among 3 receivers. */ 3959 for (i = 0; i < 3; i++) 3960 energy[i] = le32toh(stats->general.energy[i]); 3961 val = MIN(energy[0], energy[1]); 3962 val = MIN(energy[2], val); 3963 /* Insert it into our samples table. */ 3964 calib->energy_samples[calib->cur_energy_sample] = val; 3965 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 3966 3967 /* Compute minimum energy among last 10 samples. */ 3968 energy_min = calib->energy_samples[0]; 3969 for (i = 1; i < 10; i++) 3970 energy_min = MAX(energy_min, calib->energy_samples[i]); 3971 energy_min += 6; 3972 3973 /* Compute number of false alarms since last call for CCK. */ 3974 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 3975 fa += le32toh(stats->cck.fa) - calib->fa_cck; 3976 fa *= 200 * 1024; /* 200TU */ 3977 3978 /* Save counters values for next call. */ 3979 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 3980 calib->fa_cck = le32toh(stats->cck.fa); 3981 3982 if (fa > 50 * rxena) { 3983 /* High false alarm count, decrease sensitivity. */ 3984 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 3985 calib->cck_state = IWN_CCK_STATE_HIFA; 3986 calib->low_fa = 0; 3987 3988 if (calib->cck_x4 > 160) { 3989 calib->noise_ref = noise_ref; 3990 if (calib->energy_cck > 2) 3991 dec(calib->energy_cck, 2, energy_min); 3992 } 3993 if (calib->cck_x4 < 160) { 3994 calib->cck_x4 = 161; 3995 needs_update = 1; 3996 } else 3997 inc(calib->cck_x4, 3, limits->max_cck_x4); 3998 3999 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4000 4001 } else if (fa < 5 * rxena) { 4002 /* Low false alarm count, increase sensitivity. */ 4003 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4004 calib->cck_state = IWN_CCK_STATE_LOFA; 4005 calib->low_fa++; 4006 4007 if (calib->cck_state != IWN_CCK_STATE_INIT && 4008 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4009 calib->low_fa > 100)) { 4010 inc(calib->energy_cck, 2, limits->min_energy_cck); 4011 dec(calib->cck_x4, 3, limits->min_cck_x4); 4012 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4013 } 4014 } else { 4015 /* Not worth to increase or decrease sensitivity. */ 4016 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4017 calib->low_fa = 0; 4018 calib->noise_ref = noise_ref; 4019 4020 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4021 /* Previous interval had many false alarms. */ 4022 dec(calib->energy_cck, 8, energy_min); 4023 } 4024 calib->cck_state = IWN_CCK_STATE_INIT; 4025 } 4026 4027 if (needs_update) 4028 (void)iwn_send_sensitivity(sc); 4029 #undef dec 4030 #undef inc 4031 } 4032 4033 static int 4034 iwn_send_sensitivity(struct iwn_softc *sc) 4035 { 4036 struct iwn_calib_state *calib = &sc->calib; 4037 struct iwn_sensitivity_cmd cmd; 4038 4039 memset(&cmd, 0, sizeof cmd); 4040 cmd.which = IWN_SENSITIVITY_WORKTBL; 4041 /* OFDM modulation. */ 4042 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4043 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4044 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4045 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4046 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4047 cmd.energy_ofdm_th = htole16(62); 4048 /* CCK modulation. */ 4049 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4050 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4051 cmd.energy_cck = htole16(calib->energy_cck); 4052 /* Barker modulation: use default values. */ 4053 cmd.corr_barker = htole16(190); 4054 cmd.corr_barker_mrc = htole16(390); 4055 4056 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4057 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4058 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4059 calib->energy_cck)); 4060 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1); 4061 } 4062 4063 /* 4064 * Set STA mode power saving level (between 0 and 5). 4065 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4066 */ 4067 static int 4068 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4069 { 4070 struct iwn_pmgt_cmd cmd; 4071 const struct iwn_pmgt *pmgt; 4072 uint32_t maxp, skip_dtim; 4073 pcireg_t reg; 4074 int i; 4075 4076 /* Select which PS parameters to use. */ 4077 if (dtim <= 2) 4078 pmgt = &iwn_pmgt[0][level]; 4079 else if (dtim <= 10) 4080 pmgt = &iwn_pmgt[1][level]; 4081 else 4082 pmgt = &iwn_pmgt[2][level]; 4083 4084 memset(&cmd, 0, sizeof cmd); 4085 if (level != 0) /* not CAM */ 4086 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4087 if (level == 5) 4088 cmd.flags |= htole16(IWN_PS_FAST_PD); 4089 /* Retrieve PCIe Active State Power Management (ASPM). */ 4090 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4091 sc->sc_cap_off + PCIE_LCSR); 4092 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4093 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4094 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4095 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4096 4097 if (dtim == 0) { 4098 dtim = 1; 4099 skip_dtim = 0; 4100 } else 4101 skip_dtim = pmgt->skip_dtim; 4102 if (skip_dtim != 0) { 4103 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4104 maxp = pmgt->intval[4]; 4105 if (maxp == (uint32_t)-1) 4106 maxp = dtim * (skip_dtim + 1); 4107 else if (maxp > dtim) 4108 maxp = (maxp / dtim) * dtim; 4109 } else 4110 maxp = dtim; 4111 for (i = 0; i < 5; i++) 4112 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4113 4114 DPRINTF(("setting power saving level to %d\n", level)); 4115 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4116 } 4117 4118 int 4119 iwn5000_runtime_calib(struct iwn_softc *sc) 4120 { 4121 struct iwn5000_calib_config cmd; 4122 4123 memset(&cmd, 0, sizeof cmd); 4124 cmd.ucode.once.enable = 0xffffffff; 4125 cmd.ucode.once.start = IWN5000_CALIB_DC; 4126 DPRINTF(("configuring runtime calibration\n")); 4127 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4128 } 4129 4130 static int 4131 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc) 4132 { 4133 struct iwn_bluetooth bluetooth; 4134 4135 memset(&bluetooth, 0, sizeof bluetooth); 4136 bluetooth.flags = IWN_BT_COEX_ENABLE; 4137 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4138 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4139 4140 DPRINTF(("configuring bluetooth coexistence\n")); 4141 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4142 } 4143 4144 static int 4145 iwn_config_bt_coex_prio_table(struct iwn_softc *sc) 4146 { 4147 uint8_t prio_table[16]; 4148 4149 memset(&prio_table, 0, sizeof prio_table); 4150 prio_table[ 0] = 6; /* init calibration 1 */ 4151 prio_table[ 1] = 7; /* init calibration 2 */ 4152 prio_table[ 2] = 2; /* periodic calib low 1 */ 4153 prio_table[ 3] = 3; /* periodic calib low 2 */ 4154 prio_table[ 4] = 4; /* periodic calib high 1 */ 4155 prio_table[ 5] = 5; /* periodic calib high 2 */ 4156 prio_table[ 6] = 6; /* dtim */ 4157 prio_table[ 7] = 8; /* scan52 */ 4158 prio_table[ 8] = 10; /* scan24 */ 4159 4160 DPRINTF(("sending priority lookup table\n")); 4161 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE, 4162 &prio_table, sizeof prio_table, 0); 4163 } 4164 4165 static int 4166 iwn_config_bt_coex_adv1(struct iwn_softc *sc) 4167 { 4168 int error; 4169 struct iwn_bt_adv1 d; 4170 4171 memset(&d, 0, sizeof d); 4172 d.basic.bt.flags = IWN_BT_COEX_ENABLE; 4173 d.basic.bt.lead_time = IWN_BT_LEAD_TIME_DEF; 4174 d.basic.bt.max_kill = IWN_BT_MAX_KILL_DEF; 4175 d.basic.bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF; 4176 d.basic.bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF; 4177 d.basic.bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF; 4178 d.basic.bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF; 4179 d.basic.bt3_timer_t2_value = IWN_BT_BT3_T2_DEF; 4180 d.basic.bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */ 4181 d.basic.bt3_lookup_table[ 1] = htole32(0xaaaaaaaa); 4182 d.basic.bt3_lookup_table[ 2] = htole32(0xaeaaaaaa); 4183 d.basic.bt3_lookup_table[ 3] = htole32(0xaaaaaaaa); 4184 d.basic.bt3_lookup_table[ 4] = htole32(0xcc00ff28); 4185 d.basic.bt3_lookup_table[ 5] = htole32(0x0000aaaa); 4186 d.basic.bt3_lookup_table[ 6] = htole32(0xcc00aaaa); 4187 d.basic.bt3_lookup_table[ 7] = htole32(0x0000aaaa); 4188 d.basic.bt3_lookup_table[ 8] = htole32(0xc0004000); 4189 d.basic.bt3_lookup_table[ 9] = htole32(0x00004000); 4190 d.basic.bt3_lookup_table[10] = htole32(0xf0005000); 4191 d.basic.bt3_lookup_table[11] = htole32(0xf0005000); 4192 d.basic.reduce_txpower = 0; /* as not implemented */ 4193 d.basic.valid = IWN_BT_ALL_VALID_MASK; 4194 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4195 d.tx_prio_boost = 0; 4196 d.rx_prio_boost = 0; 4197 4198 DPRINTF(("configuring advanced bluetooth coexistence v1\n")); 4199 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &d, sizeof d, 0); 4200 if (error != 0) { 4201 aprint_error_dev(sc->sc_dev, 4202 "could not configure advanced bluetooth coexistence\n"); 4203 return error; 4204 } 4205 4206 error = iwn_config_bt_coex_prio_table(sc); 4207 if (error != 0) { 4208 aprint_error_dev(sc->sc_dev, 4209 "could not configure send BT priority table\n"); 4210 return error; 4211 } 4212 4213 return error; 4214 } 4215 4216 static int 4217 iwn_config(struct iwn_softc *sc) 4218 { 4219 struct iwn_ops *ops = &sc->ops; 4220 struct ieee80211com *ic = &sc->sc_ic; 4221 struct ifnet *ifp = ic->ic_ifp; 4222 uint32_t txmask; 4223 uint16_t rxchain; 4224 int error; 4225 4226 error = ops->config_bt_coex(sc); 4227 if (error != 0) { 4228 aprint_error_dev(sc->sc_dev, 4229 "could not configure bluetooth coexistence\n"); 4230 return error; 4231 } 4232 4233 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4234 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4235 /* Configure runtime DC calibration. */ 4236 error = iwn5000_runtime_calib(sc); 4237 if (error != 0) { 4238 aprint_error_dev(sc->sc_dev, 4239 "could not configure runtime calibration\n"); 4240 return error; 4241 } 4242 } 4243 4244 /* Configure valid TX chains for 5000 Series. */ 4245 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4246 txmask = htole32(sc->txchainmask); 4247 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4248 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4249 sizeof txmask, 0); 4250 if (error != 0) { 4251 aprint_error_dev(sc->sc_dev, 4252 "could not configure valid TX chains\n"); 4253 return error; 4254 } 4255 } 4256 4257 /* Set mode, channel, RX filter and enable RX. */ 4258 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4259 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4260 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4261 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4262 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4263 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4264 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4265 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4266 switch (ic->ic_opmode) { 4267 case IEEE80211_M_STA: 4268 sc->rxon.mode = IWN_MODE_STA; 4269 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4270 break; 4271 case IEEE80211_M_MONITOR: 4272 sc->rxon.mode = IWN_MODE_MONITOR; 4273 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4274 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4275 break; 4276 default: 4277 /* Should not get there. */ 4278 break; 4279 } 4280 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4281 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4282 sc->rxon.ht_single_mask = 0xff; 4283 sc->rxon.ht_dual_mask = 0xff; 4284 sc->rxon.ht_triple_mask = 0xff; 4285 rxchain = 4286 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4287 IWN_RXCHAIN_MIMO_COUNT(2) | 4288 IWN_RXCHAIN_IDLE_COUNT(2); 4289 sc->rxon.rxchain = htole16(rxchain); 4290 DPRINTF(("setting configuration\n")); 4291 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4292 if (error != 0) { 4293 aprint_error_dev(sc->sc_dev, 4294 "RXON command failed\n"); 4295 return error; 4296 } 4297 4298 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4299 aprint_error_dev(sc->sc_dev, 4300 "could not add broadcast node\n"); 4301 return error; 4302 } 4303 4304 /* Configuration has changed, set TX power accordingly. */ 4305 if ((error = ops->set_txpower(sc, 0)) != 0) { 4306 aprint_error_dev(sc->sc_dev, 4307 "could not set TX power\n"); 4308 return error; 4309 } 4310 4311 if ((error = iwn_set_critical_temp(sc)) != 0) { 4312 aprint_error_dev(sc->sc_dev, 4313 "could not set critical temperature\n"); 4314 return error; 4315 } 4316 4317 /* Set power saving level to CAM during initialization. */ 4318 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4319 aprint_error_dev(sc->sc_dev, 4320 "could not set power saving level\n"); 4321 return error; 4322 } 4323 return 0; 4324 } 4325 4326 static int 4327 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4328 { 4329 struct ieee80211com *ic = &sc->sc_ic; 4330 struct iwn_scan_hdr *hdr; 4331 struct iwn_cmd_data *tx; 4332 struct iwn_scan_essid *essid; 4333 struct iwn_scan_chan *chan; 4334 struct ieee80211_frame *wh; 4335 struct ieee80211_rateset *rs; 4336 struct ieee80211_channel *c; 4337 uint8_t *buf, *frm; 4338 uint16_t rxchain; 4339 uint8_t txant; 4340 int buflen, error; 4341 4342 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4343 if (buf == NULL) { 4344 aprint_error_dev(sc->sc_dev, 4345 "could not allocate buffer for scan command\n"); 4346 return ENOMEM; 4347 } 4348 hdr = (struct iwn_scan_hdr *)buf; 4349 /* 4350 * Move to the next channel if no frames are received within 10ms 4351 * after sending the probe request. 4352 */ 4353 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4354 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4355 4356 /* Select antennas for scanning. */ 4357 rxchain = 4358 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4359 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4360 IWN_RXCHAIN_DRIVER_FORCE; 4361 if ((flags & IEEE80211_CHAN_5GHZ) && 4362 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4363 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4364 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4365 } else /* Use all available RX antennas. */ 4366 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4367 hdr->rxchain = htole16(rxchain); 4368 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4369 4370 tx = (struct iwn_cmd_data *)(hdr + 1); 4371 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4372 tx->id = sc->broadcast_id; 4373 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4374 4375 if (flags & IEEE80211_CHAN_5GHZ) { 4376 hdr->crc_threshold = 0xffff; 4377 /* Send probe requests at 6Mbps. */ 4378 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4379 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4380 } else { 4381 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4382 /* Send probe requests at 1Mbps. */ 4383 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4384 tx->rflags = IWN_RFLAG_CCK; 4385 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4386 } 4387 /* Use the first valid TX antenna. */ 4388 txant = IWN_LSB(sc->txchainmask); 4389 tx->rflags |= IWN_RFLAG_ANT(txant); 4390 4391 essid = (struct iwn_scan_essid *)(tx + 1); 4392 if (ic->ic_des_esslen != 0) { 4393 essid[0].id = IEEE80211_ELEMID_SSID; 4394 essid[0].len = ic->ic_des_esslen; 4395 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4396 } 4397 /* 4398 * Build a probe request frame. Most of the following code is a 4399 * copy & paste of what is done in net80211. 4400 */ 4401 wh = (struct ieee80211_frame *)(essid + 20); 4402 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4403 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4404 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4405 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4406 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4407 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4408 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4409 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4410 4411 frm = (uint8_t *)(wh + 1); 4412 frm = ieee80211_add_ssid(frm, NULL, 0); 4413 frm = ieee80211_add_rates(frm, rs); 4414 #ifndef IEEE80211_NO_HT 4415 if (ic->ic_flags & IEEE80211_F_HTON) 4416 frm = ieee80211_add_htcaps(frm, ic); 4417 #endif 4418 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4419 frm = ieee80211_add_xrates(frm, rs); 4420 4421 /* Set length of probe request. */ 4422 tx->len = htole16(frm - (uint8_t *)wh); 4423 4424 chan = (struct iwn_scan_chan *)frm; 4425 for (c = &ic->ic_channels[1]; 4426 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4427 if ((c->ic_flags & flags) != flags) 4428 continue; 4429 4430 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4431 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4432 chan->flags = 0; 4433 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4434 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4435 if (ic->ic_des_esslen != 0) 4436 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4437 chan->dsp_gain = 0x6e; 4438 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4439 chan->rf_gain = 0x3b; 4440 chan->active = htole16(24); 4441 chan->passive = htole16(110); 4442 } else { 4443 chan->rf_gain = 0x28; 4444 chan->active = htole16(36); 4445 chan->passive = htole16(120); 4446 } 4447 hdr->nchan++; 4448 chan++; 4449 } 4450 4451 buflen = (uint8_t *)chan - buf; 4452 hdr->len = htole16(buflen); 4453 4454 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4455 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4456 free(buf, M_DEVBUF); 4457 return error; 4458 } 4459 4460 static int 4461 iwn_auth(struct iwn_softc *sc) 4462 { 4463 struct iwn_ops *ops = &sc->ops; 4464 struct ieee80211com *ic = &sc->sc_ic; 4465 struct ieee80211_node *ni = ic->ic_bss; 4466 int error; 4467 4468 /* Update adapter configuration. */ 4469 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4470 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4471 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4472 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4473 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4474 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4475 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4476 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4477 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4478 switch (ic->ic_curmode) { 4479 case IEEE80211_MODE_11A: 4480 sc->rxon.cck_mask = 0; 4481 sc->rxon.ofdm_mask = 0x15; 4482 break; 4483 case IEEE80211_MODE_11B: 4484 sc->rxon.cck_mask = 0x03; 4485 sc->rxon.ofdm_mask = 0; 4486 break; 4487 default: /* Assume 802.11b/g. */ 4488 sc->rxon.cck_mask = 0x0f; 4489 sc->rxon.ofdm_mask = 0x15; 4490 } 4491 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4492 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4493 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4494 if (error != 0) { 4495 aprint_error_dev(sc->sc_dev, 4496 "RXON command failed\n"); 4497 return error; 4498 } 4499 4500 /* Configuration has changed, set TX power accordingly. */ 4501 if ((error = ops->set_txpower(sc, 1)) != 0) { 4502 aprint_error_dev(sc->sc_dev, 4503 "could not set TX power\n"); 4504 return error; 4505 } 4506 /* 4507 * Reconfiguring RXON clears the firmware nodes table so we must 4508 * add the broadcast node again. 4509 */ 4510 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4511 aprint_error_dev(sc->sc_dev, 4512 "could not add broadcast node\n"); 4513 return error; 4514 } 4515 return 0; 4516 } 4517 4518 static int 4519 iwn_run(struct iwn_softc *sc) 4520 { 4521 struct iwn_ops *ops = &sc->ops; 4522 struct ieee80211com *ic = &sc->sc_ic; 4523 struct ieee80211_node *ni = ic->ic_bss; 4524 struct iwn_node_info node; 4525 int error; 4526 4527 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4528 /* Link LED blinks while monitoring. */ 4529 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4530 return 0; 4531 } 4532 if ((error = iwn_set_timing(sc, ni)) != 0) { 4533 aprint_error_dev(sc->sc_dev, 4534 "could not set timing\n"); 4535 return error; 4536 } 4537 4538 /* Update adapter configuration. */ 4539 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4540 /* Short preamble and slot time are negotiated when associating. */ 4541 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4542 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4543 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4544 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4545 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4546 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4547 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4548 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4549 if (error != 0) { 4550 aprint_error_dev(sc->sc_dev, 4551 "could not update configuration\n"); 4552 return error; 4553 } 4554 4555 /* Configuration has changed, set TX power accordingly. */ 4556 if ((error = ops->set_txpower(sc, 1)) != 0) { 4557 aprint_error_dev(sc->sc_dev, 4558 "could not set TX power\n"); 4559 return error; 4560 } 4561 4562 /* Fake a join to initialize the TX rate. */ 4563 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4564 iwn_newassoc(ni, 1); 4565 4566 /* Add BSS node. */ 4567 memset(&node, 0, sizeof node); 4568 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4569 node.id = IWN_ID_BSS; 4570 #ifdef notyet 4571 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4572 IWN_AMDPU_DENSITY(5)); /* 2us */ 4573 #endif 4574 DPRINTF(("adding BSS node\n")); 4575 error = ops->add_node(sc, &node, 1); 4576 if (error != 0) { 4577 aprint_error_dev(sc->sc_dev, 4578 "could not add BSS node\n"); 4579 return error; 4580 } 4581 DPRINTF(("setting link quality for node %d\n", node.id)); 4582 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4583 aprint_error_dev(sc->sc_dev, 4584 "could not setup link quality for node %d\n", node.id); 4585 return error; 4586 } 4587 4588 if ((error = iwn_init_sensitivity(sc)) != 0) { 4589 aprint_error_dev(sc->sc_dev, 4590 "could not set sensitivity\n"); 4591 return error; 4592 } 4593 /* Start periodic calibration timer. */ 4594 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4595 sc->calib_cnt = 0; 4596 callout_schedule(&sc->calib_to, hz/2); 4597 4598 /* Link LED always on while associated. */ 4599 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4600 return 0; 4601 } 4602 4603 #ifdef IWN_HWCRYPTO 4604 /* 4605 * We support CCMP hardware encryption/decryption of unicast frames only. 4606 * HW support for TKIP really sucks. We should let TKIP die anyway. 4607 */ 4608 static int 4609 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4610 struct ieee80211_key *k) 4611 { 4612 struct iwn_softc *sc = ic->ic_softc; 4613 struct iwn_ops *ops = &sc->ops; 4614 struct iwn_node *wn = (void *)ni; 4615 struct iwn_node_info node; 4616 uint16_t kflags; 4617 4618 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4619 k->k_cipher != IEEE80211_CIPHER_CCMP) 4620 return ieee80211_set_key(ic, ni, k); 4621 4622 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4623 if (k->k_flags & IEEE80211_KEY_GROUP) 4624 kflags |= IWN_KFLAG_GROUP; 4625 4626 memset(&node, 0, sizeof node); 4627 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4628 sc->broadcast_id : wn->id; 4629 node.control = IWN_NODE_UPDATE; 4630 node.flags = IWN_FLAG_SET_KEY; 4631 node.kflags = htole16(kflags); 4632 node.kid = k->k_id; 4633 memcpy(node.key, k->k_key, k->k_len); 4634 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4635 return ops->add_node(sc, &node, 1); 4636 } 4637 4638 static void 4639 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4640 struct ieee80211_key *k) 4641 { 4642 struct iwn_softc *sc = ic->ic_softc; 4643 struct iwn_ops *ops = &sc->ops; 4644 struct iwn_node *wn = (void *)ni; 4645 struct iwn_node_info node; 4646 4647 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4648 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4649 /* See comment about other ciphers above. */ 4650 ieee80211_delete_key(ic, ni, k); 4651 return; 4652 } 4653 if (ic->ic_state != IEEE80211_S_RUN) 4654 return; /* Nothing to do. */ 4655 memset(&node, 0, sizeof node); 4656 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4657 sc->broadcast_id : wn->id; 4658 node.control = IWN_NODE_UPDATE; 4659 node.flags = IWN_FLAG_SET_KEY; 4660 node.kflags = htole16(IWN_KFLAG_INVALID); 4661 node.kid = 0xff; 4662 DPRINTF(("delete keys for node %d\n", node.id)); 4663 (void)ops->add_node(sc, &node, 1); 4664 } 4665 #endif 4666 4667 /* XXX Added for NetBSD (copied from rev 1.39). */ 4668 4669 static int 4670 iwn_wme_update(struct ieee80211com *ic) 4671 { 4672 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4673 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4674 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4675 const struct wmeParams *wmep; 4676 struct iwn_edca_params cmd; 4677 int ac; 4678 4679 /* don't override default WME values if WME is not actually enabled */ 4680 if (!(ic->ic_flags & IEEE80211_F_WME)) 4681 return 0; 4682 cmd.flags = 0; 4683 for (ac = 0; ac < WME_NUM_AC; ac++) { 4684 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4685 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4686 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4687 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4688 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4689 4690 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4691 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4692 cmd.ac[ac].cwmin, 4693 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4694 } 4695 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4696 #undef IWN_USEC 4697 #undef IWN_EXP2 4698 } 4699 4700 #ifndef IEEE80211_NO_HT 4701 /* 4702 * This function is called by upper layer when an ADDBA request is received 4703 * from another STA and before the ADDBA response is sent. 4704 */ 4705 static int 4706 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4707 uint8_t tid) 4708 { 4709 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4710 struct iwn_softc *sc = ic->ic_softc; 4711 struct iwn_ops *ops = &sc->ops; 4712 struct iwn_node *wn = (void *)ni; 4713 struct iwn_node_info node; 4714 4715 memset(&node, 0, sizeof node); 4716 node.id = wn->id; 4717 node.control = IWN_NODE_UPDATE; 4718 node.flags = IWN_FLAG_SET_ADDBA; 4719 node.addba_tid = tid; 4720 node.addba_ssn = htole16(ba->ba_winstart); 4721 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4722 ba->ba_winstart)); 4723 return ops->add_node(sc, &node, 1); 4724 } 4725 4726 /* 4727 * This function is called by upper layer on teardown of an HT-immediate 4728 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4729 */ 4730 static void 4731 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4732 uint8_t tid) 4733 { 4734 struct iwn_softc *sc = ic->ic_softc; 4735 struct iwn_ops *ops = &sc->ops; 4736 struct iwn_node *wn = (void *)ni; 4737 struct iwn_node_info node; 4738 4739 memset(&node, 0, sizeof node); 4740 node.id = wn->id; 4741 node.control = IWN_NODE_UPDATE; 4742 node.flags = IWN_FLAG_SET_DELBA; 4743 node.delba_tid = tid; 4744 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4745 (void)ops->add_node(sc, &node, 1); 4746 } 4747 4748 /* 4749 * This function is called by upper layer when an ADDBA response is received 4750 * from another STA. 4751 */ 4752 static int 4753 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4754 uint8_t tid) 4755 { 4756 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4757 struct iwn_softc *sc = ic->ic_softc; 4758 struct iwn_ops *ops = &sc->ops; 4759 struct iwn_node *wn = (void *)ni; 4760 struct iwn_node_info node; 4761 int error; 4762 4763 /* Enable TX for the specified RA/TID. */ 4764 wn->disable_tid &= ~(1 << tid); 4765 memset(&node, 0, sizeof node); 4766 node.id = wn->id; 4767 node.control = IWN_NODE_UPDATE; 4768 node.flags = IWN_FLAG_SET_DISABLE_TID; 4769 node.disable_tid = htole16(wn->disable_tid); 4770 error = ops->add_node(sc, &node, 1); 4771 if (error != 0) 4772 return error; 4773 4774 if ((error = iwn_nic_lock(sc)) != 0) 4775 return error; 4776 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 4777 iwn_nic_unlock(sc); 4778 return 0; 4779 } 4780 4781 static void 4782 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4783 uint8_t tid) 4784 { 4785 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 4786 struct iwn_softc *sc = ic->ic_softc; 4787 struct iwn_ops *ops = &sc->ops; 4788 4789 if (iwn_nic_lock(sc) != 0) 4790 return; 4791 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 4792 iwn_nic_unlock(sc); 4793 } 4794 4795 static void 4796 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4797 uint8_t tid, uint16_t ssn) 4798 { 4799 struct iwn_node *wn = (void *)ni; 4800 int qid = 7 + tid; 4801 4802 /* Stop TX scheduler while we're changing its configuration. */ 4803 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4804 IWN4965_TXQ_STATUS_CHGACT); 4805 4806 /* Assign RA/TID translation to the queue. */ 4807 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 4808 wn->id << 4 | tid); 4809 4810 /* Enable chain-building mode for the queue. */ 4811 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 4812 4813 /* Set starting sequence number from the ADDBA request. */ 4814 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4815 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4816 4817 /* Set scheduler window size. */ 4818 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 4819 IWN_SCHED_WINSZ); 4820 /* Set scheduler frame limit. */ 4821 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 4822 IWN_SCHED_LIMIT << 16); 4823 4824 /* Enable interrupts for the queue. */ 4825 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4826 4827 /* Mark the queue as active. */ 4828 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4829 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 4830 iwn_tid2fifo[tid] << 1); 4831 } 4832 4833 static void 4834 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4835 { 4836 int qid = 7 + tid; 4837 4838 /* Stop TX scheduler while we're changing its configuration. */ 4839 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4840 IWN4965_TXQ_STATUS_CHGACT); 4841 4842 /* Set starting sequence number from the ADDBA request. */ 4843 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4844 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 4845 4846 /* Disable interrupts for the queue. */ 4847 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 4848 4849 /* Mark the queue as inactive. */ 4850 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 4851 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 4852 } 4853 4854 static void 4855 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 4856 uint8_t tid, uint16_t ssn) 4857 { 4858 struct iwn_node *wn = (void *)ni; 4859 int qid = 10 + tid; 4860 4861 /* Stop TX scheduler while we're changing its configuration. */ 4862 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4863 IWN5000_TXQ_STATUS_CHGACT); 4864 4865 /* Assign RA/TID translation to the queue. */ 4866 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 4867 wn->id << 4 | tid); 4868 4869 /* Enable chain-building mode for the queue. */ 4870 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 4871 4872 /* Enable aggregation for the queue. */ 4873 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4874 4875 /* Set starting sequence number from the ADDBA request. */ 4876 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4877 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4878 4879 /* Set scheduler window size and frame limit. */ 4880 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 4881 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 4882 4883 /* Enable interrupts for the queue. */ 4884 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4885 4886 /* Mark the queue as active. */ 4887 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4888 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 4889 } 4890 4891 static void 4892 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 4893 { 4894 int qid = 10 + tid; 4895 4896 /* Stop TX scheduler while we're changing its configuration. */ 4897 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4898 IWN5000_TXQ_STATUS_CHGACT); 4899 4900 /* Disable aggregation for the queue. */ 4901 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 4902 4903 /* Set starting sequence number from the ADDBA request. */ 4904 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 4905 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 4906 4907 /* Disable interrupts for the queue. */ 4908 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 4909 4910 /* Mark the queue as inactive. */ 4911 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 4912 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 4913 } 4914 #endif /* !IEEE80211_NO_HT */ 4915 4916 /* 4917 * Query calibration tables from the initialization firmware. We do this 4918 * only once at first boot. Called from a process context. 4919 */ 4920 static int 4921 iwn5000_query_calibration(struct iwn_softc *sc) 4922 { 4923 struct iwn5000_calib_config cmd; 4924 int error; 4925 4926 memset(&cmd, 0, sizeof cmd); 4927 cmd.ucode.once.enable = 0xffffffff; 4928 cmd.ucode.once.start = 0xffffffff; 4929 cmd.ucode.once.send = 0xffffffff; 4930 cmd.ucode.flags = 0xffffffff; 4931 DPRINTF(("sending calibration query\n")); 4932 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 4933 if (error != 0) 4934 return error; 4935 4936 /* Wait at most two seconds for calibration to complete. */ 4937 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 4938 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 4939 return error; 4940 } 4941 4942 /* 4943 * Send calibration results to the runtime firmware. These results were 4944 * obtained on first boot from the initialization firmware. 4945 */ 4946 static int 4947 iwn5000_send_calibration(struct iwn_softc *sc) 4948 { 4949 int idx, error; 4950 4951 for (idx = 0; idx < 5; idx++) { 4952 if (sc->calibcmd[idx].buf == NULL) 4953 continue; /* No results available. */ 4954 DPRINTF(("send calibration result idx=%d len=%d\n", 4955 idx, sc->calibcmd[idx].len)); 4956 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 4957 sc->calibcmd[idx].len, 0); 4958 if (error != 0) { 4959 aprint_error_dev(sc->sc_dev, 4960 "could not send calibration result\n"); 4961 return error; 4962 } 4963 } 4964 return 0; 4965 } 4966 4967 static int 4968 iwn5000_send_wimax_coex(struct iwn_softc *sc) 4969 { 4970 struct iwn5000_wimax_coex wimax; 4971 4972 #ifdef notyet 4973 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 4974 /* Enable WiMAX coexistence for combo adapters. */ 4975 wimax.flags = 4976 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 4977 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 4978 IWN_WIMAX_COEX_STA_TABLE_VALID | 4979 IWN_WIMAX_COEX_ENABLE; 4980 memcpy(wimax.events, iwn6050_wimax_events, 4981 sizeof iwn6050_wimax_events); 4982 } else 4983 #endif 4984 { 4985 /* Disable WiMAX coexistence. */ 4986 wimax.flags = 0; 4987 memset(wimax.events, 0, sizeof wimax.events); 4988 } 4989 DPRINTF(("Configuring WiMAX coexistence\n")); 4990 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 4991 } 4992 4993 /* 4994 * This function is called after the runtime firmware notifies us of its 4995 * readiness (called in a process context). 4996 */ 4997 static int 4998 iwn4965_post_alive(struct iwn_softc *sc) 4999 { 5000 int error, qid; 5001 5002 if ((error = iwn_nic_lock(sc)) != 0) 5003 return error; 5004 5005 /* Clear TX scheduler state in SRAM. */ 5006 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5007 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5008 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5009 5010 /* Set physical address of TX scheduler rings (1KB aligned). */ 5011 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5012 5013 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5014 5015 /* Disable chain mode for all our 16 queues. */ 5016 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5017 5018 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5019 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5020 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5021 5022 /* Set scheduler window size. */ 5023 iwn_mem_write(sc, sc->sched_base + 5024 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5025 /* Set scheduler frame limit. */ 5026 iwn_mem_write(sc, sc->sched_base + 5027 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5028 IWN_SCHED_LIMIT << 16); 5029 } 5030 5031 /* Enable interrupts for all our 16 queues. */ 5032 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5033 /* Identify TX FIFO rings (0-7). */ 5034 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5035 5036 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5037 for (qid = 0; qid < 7; qid++) { 5038 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5039 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5040 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5041 } 5042 iwn_nic_unlock(sc); 5043 return 0; 5044 } 5045 5046 /* 5047 * This function is called after the initialization or runtime firmware 5048 * notifies us of its readiness (called in a process context). 5049 */ 5050 static int 5051 iwn5000_post_alive(struct iwn_softc *sc) 5052 { 5053 int error, qid; 5054 5055 /* Switch to using ICT interrupt mode. */ 5056 iwn5000_ict_reset(sc); 5057 5058 if ((error = iwn_nic_lock(sc)) != 0) 5059 return error; 5060 5061 /* Clear TX scheduler state in SRAM. */ 5062 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5063 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5064 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5065 5066 /* Set physical address of TX scheduler rings (1KB aligned). */ 5067 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5068 5069 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5070 5071 /* Enable chain mode for all queues, except command queue. */ 5072 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5073 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5074 5075 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5076 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5077 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5078 5079 iwn_mem_write(sc, sc->sched_base + 5080 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5081 /* Set scheduler window size and frame limit. */ 5082 iwn_mem_write(sc, sc->sched_base + 5083 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5084 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5085 } 5086 5087 /* Enable interrupts for all our 20 queues. */ 5088 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5089 /* Identify TX FIFO rings (0-7). */ 5090 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5091 5092 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5093 for (qid = 0; qid < 7; qid++) { 5094 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5095 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5096 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5097 } 5098 iwn_nic_unlock(sc); 5099 5100 /* Configure WiMAX coexistence for combo adapters. */ 5101 error = iwn5000_send_wimax_coex(sc); 5102 if (error != 0) { 5103 aprint_error_dev(sc->sc_dev, 5104 "could not configure WiMAX coexistence\n"); 5105 return error; 5106 } 5107 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5108 struct iwn5000_phy_calib_crystal cmd; 5109 5110 /* Perform crystal calibration. */ 5111 memset(&cmd, 0, sizeof cmd); 5112 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5113 cmd.ngroups = 1; 5114 cmd.isvalid = 1; 5115 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5116 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5117 DPRINTF(("sending crystal calibration %d, %d\n", 5118 cmd.cap_pin[0], cmd.cap_pin[1])); 5119 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5120 if (error != 0) { 5121 aprint_error_dev(sc->sc_dev, 5122 "crystal calibration failed\n"); 5123 return error; 5124 } 5125 } 5126 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5127 /* Query calibration from the initialization firmware. */ 5128 if ((error = iwn5000_query_calibration(sc)) != 0) { 5129 aprint_error_dev(sc->sc_dev, 5130 "could not query calibration\n"); 5131 return error; 5132 } 5133 /* 5134 * We have the calibration results now, reboot with the 5135 * runtime firmware (call ourselves recursively!) 5136 */ 5137 iwn_hw_stop(sc); 5138 error = iwn_hw_init(sc); 5139 } else { 5140 /* Send calibration results to runtime firmware. */ 5141 error = iwn5000_send_calibration(sc); 5142 } 5143 return error; 5144 } 5145 5146 /* 5147 * The firmware boot code is small and is intended to be copied directly into 5148 * the NIC internal memory (no DMA transfer). 5149 */ 5150 static int 5151 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5152 { 5153 int error, ntries; 5154 5155 size /= sizeof (uint32_t); 5156 5157 if ((error = iwn_nic_lock(sc)) != 0) 5158 return error; 5159 5160 /* Copy microcode image into NIC memory. */ 5161 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5162 (const uint32_t *)ucode, size); 5163 5164 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5165 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5166 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5167 5168 /* Start boot load now. */ 5169 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5170 5171 /* Wait for transfer to complete. */ 5172 for (ntries = 0; ntries < 1000; ntries++) { 5173 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5174 IWN_BSM_WR_CTRL_START)) 5175 break; 5176 DELAY(10); 5177 } 5178 if (ntries == 1000) { 5179 aprint_error_dev(sc->sc_dev, 5180 "could not load boot firmware\n"); 5181 iwn_nic_unlock(sc); 5182 return ETIMEDOUT; 5183 } 5184 5185 /* Enable boot after power up. */ 5186 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5187 5188 iwn_nic_unlock(sc); 5189 return 0; 5190 } 5191 5192 static int 5193 iwn4965_load_firmware(struct iwn_softc *sc) 5194 { 5195 struct iwn_fw_info *fw = &sc->fw; 5196 struct iwn_dma_info *dma = &sc->fw_dma; 5197 int error; 5198 5199 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5200 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5201 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5202 BUS_DMASYNC_PREWRITE); 5203 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5204 fw->init.text, fw->init.textsz); 5205 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5206 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5207 5208 /* Tell adapter where to find initialization sections. */ 5209 if ((error = iwn_nic_lock(sc)) != 0) 5210 return error; 5211 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5212 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5213 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5214 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5215 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5216 iwn_nic_unlock(sc); 5217 5218 /* Load firmware boot code. */ 5219 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5220 if (error != 0) { 5221 aprint_error_dev(sc->sc_dev, 5222 "could not load boot firmware\n"); 5223 return error; 5224 } 5225 /* Now press "execute". */ 5226 IWN_WRITE(sc, IWN_RESET, 0); 5227 5228 /* Wait at most one second for first alive notification. */ 5229 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5230 aprint_error_dev(sc->sc_dev, 5231 "timeout waiting for adapter to initialize\n"); 5232 return error; 5233 } 5234 5235 /* Retrieve current temperature for initial TX power calibration. */ 5236 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5237 sc->temp = iwn4965_get_temperature(sc); 5238 5239 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5240 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5241 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5242 BUS_DMASYNC_PREWRITE); 5243 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5244 fw->main.text, fw->main.textsz); 5245 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5246 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5247 5248 /* Tell adapter where to find runtime sections. */ 5249 if ((error = iwn_nic_lock(sc)) != 0) 5250 return error; 5251 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5252 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5253 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5254 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5255 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5256 IWN_FW_UPDATED | fw->main.textsz); 5257 iwn_nic_unlock(sc); 5258 5259 return 0; 5260 } 5261 5262 static int 5263 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5264 const uint8_t *section, int size) 5265 { 5266 struct iwn_dma_info *dma = &sc->fw_dma; 5267 int error; 5268 5269 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5270 memcpy(dma->vaddr, section, size); 5271 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5272 5273 if ((error = iwn_nic_lock(sc)) != 0) 5274 return error; 5275 5276 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5277 IWN_FH_TX_CONFIG_DMA_PAUSE); 5278 5279 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5280 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5281 IWN_LOADDR(dma->paddr)); 5282 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5283 IWN_HIADDR(dma->paddr) << 28 | size); 5284 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5285 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5286 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5287 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5288 5289 /* Kick Flow Handler to start DMA transfer. */ 5290 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5291 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5292 5293 iwn_nic_unlock(sc); 5294 5295 /* Wait at most five seconds for FH DMA transfer to complete. */ 5296 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5297 } 5298 5299 static int 5300 iwn5000_load_firmware(struct iwn_softc *sc) 5301 { 5302 struct iwn_fw_part *fw; 5303 int error; 5304 5305 /* Load the initialization firmware on first boot only. */ 5306 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5307 &sc->fw.main : &sc->fw.init; 5308 5309 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5310 fw->text, fw->textsz); 5311 if (error != 0) { 5312 aprint_error_dev(sc->sc_dev, 5313 "could not load firmware %s section\n", ".text"); 5314 return error; 5315 } 5316 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5317 fw->data, fw->datasz); 5318 if (error != 0) { 5319 aprint_error_dev(sc->sc_dev, 5320 "could not load firmware %s section\n", ".data"); 5321 return error; 5322 } 5323 5324 /* Now press "execute". */ 5325 IWN_WRITE(sc, IWN_RESET, 0); 5326 return 0; 5327 } 5328 5329 /* 5330 * Extract text and data sections from a legacy firmware image. 5331 */ 5332 static int 5333 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5334 { 5335 const uint32_t *ptr; 5336 size_t hdrlen = 24; 5337 uint32_t rev; 5338 5339 ptr = (const uint32_t *)fw->data; 5340 rev = le32toh(*ptr++); 5341 5342 /* Check firmware API version. */ 5343 if (IWN_FW_API(rev) <= 1) { 5344 aprint_error_dev(sc->sc_dev, 5345 "bad firmware, need API version >=2\n"); 5346 return EINVAL; 5347 } 5348 if (IWN_FW_API(rev) >= 3) { 5349 /* Skip build number (version 2 header). */ 5350 hdrlen += 4; 5351 ptr++; 5352 } 5353 if (fw->size < hdrlen) { 5354 aprint_error_dev(sc->sc_dev, 5355 "firmware too short: %zd bytes\n", fw->size); 5356 return EINVAL; 5357 } 5358 fw->main.textsz = le32toh(*ptr++); 5359 fw->main.datasz = le32toh(*ptr++); 5360 fw->init.textsz = le32toh(*ptr++); 5361 fw->init.datasz = le32toh(*ptr++); 5362 fw->boot.textsz = le32toh(*ptr++); 5363 5364 /* Check that all firmware sections fit. */ 5365 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5366 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5367 aprint_error_dev(sc->sc_dev, 5368 "firmware too short: %zd bytes\n", fw->size); 5369 return EINVAL; 5370 } 5371 5372 /* Get pointers to firmware sections. */ 5373 fw->main.text = (const uint8_t *)ptr; 5374 fw->main.data = fw->main.text + fw->main.textsz; 5375 fw->init.text = fw->main.data + fw->main.datasz; 5376 fw->init.data = fw->init.text + fw->init.textsz; 5377 fw->boot.text = fw->init.data + fw->init.datasz; 5378 return 0; 5379 } 5380 5381 /* 5382 * Extract text and data sections from a TLV firmware image. 5383 */ 5384 static int 5385 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5386 uint16_t alt) 5387 { 5388 const struct iwn_fw_tlv_hdr *hdr; 5389 const struct iwn_fw_tlv *tlv; 5390 const uint8_t *ptr, *end; 5391 uint64_t altmask; 5392 uint32_t len; 5393 5394 if (fw->size < sizeof (*hdr)) { 5395 aprint_error_dev(sc->sc_dev, 5396 "firmware too short: %zd bytes\n", fw->size); 5397 return EINVAL; 5398 } 5399 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5400 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5401 aprint_error_dev(sc->sc_dev, 5402 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5403 return EINVAL; 5404 } 5405 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5406 le32toh(hdr->build))); 5407 5408 /* 5409 * Select the closest supported alternative that is less than 5410 * or equal to the specified one. 5411 */ 5412 altmask = le64toh(hdr->altmask); 5413 while (alt > 0 && !(altmask & (1ULL << alt))) 5414 alt--; /* Downgrade. */ 5415 DPRINTF(("using alternative %d\n", alt)); 5416 5417 ptr = (const uint8_t *)(hdr + 1); 5418 end = (const uint8_t *)(fw->data + fw->size); 5419 5420 /* Parse type-length-value fields. */ 5421 while (ptr + sizeof (*tlv) <= end) { 5422 tlv = (const struct iwn_fw_tlv *)ptr; 5423 len = le32toh(tlv->len); 5424 5425 ptr += sizeof (*tlv); 5426 if (ptr + len > end) { 5427 aprint_error_dev(sc->sc_dev, 5428 "firmware too short: %zd bytes\n", fw->size); 5429 return EINVAL; 5430 } 5431 /* Skip other alternatives. */ 5432 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5433 goto next; 5434 5435 switch (le16toh(tlv->type)) { 5436 case IWN_FW_TLV_MAIN_TEXT: 5437 fw->main.text = ptr; 5438 fw->main.textsz = len; 5439 break; 5440 case IWN_FW_TLV_MAIN_DATA: 5441 fw->main.data = ptr; 5442 fw->main.datasz = len; 5443 break; 5444 case IWN_FW_TLV_INIT_TEXT: 5445 fw->init.text = ptr; 5446 fw->init.textsz = len; 5447 break; 5448 case IWN_FW_TLV_INIT_DATA: 5449 fw->init.data = ptr; 5450 fw->init.datasz = len; 5451 break; 5452 case IWN_FW_TLV_BOOT_TEXT: 5453 fw->boot.text = ptr; 5454 fw->boot.textsz = len; 5455 break; 5456 default: 5457 DPRINTF(("TLV type %d not handled\n", 5458 le16toh(tlv->type))); 5459 break; 5460 } 5461 next: /* TLV fields are 32-bit aligned. */ 5462 ptr += (len + 3) & ~3; 5463 } 5464 return 0; 5465 } 5466 5467 static int 5468 iwn_read_firmware(struct iwn_softc *sc) 5469 { 5470 struct iwn_fw_info *fw = &sc->fw; 5471 firmware_handle_t fwh; 5472 int error; 5473 5474 /* Initialize for error returns */ 5475 fw->data = NULL; 5476 fw->size = 0; 5477 5478 /* Open firmware image. */ 5479 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5480 aprint_error_dev(sc->sc_dev, 5481 "could not get firmware handle %s\n", sc->fwname); 5482 return error; 5483 } 5484 fw->size = firmware_get_size(fwh); 5485 if (fw->size < sizeof (uint32_t)) { 5486 aprint_error_dev(sc->sc_dev, 5487 "firmware too short: %zd bytes\n", fw->size); 5488 firmware_close(fwh); 5489 return EINVAL; 5490 } 5491 5492 /* Read the firmware. */ 5493 fw->data = firmware_malloc(fw->size); 5494 if (fw->data == NULL) { 5495 aprint_error_dev(sc->sc_dev, 5496 "not enough memory to stock firmware %s\n", sc->fwname); 5497 firmware_close(fwh); 5498 return ENOMEM; 5499 } 5500 error = firmware_read(fwh, 0, fw->data, fw->size); 5501 firmware_close(fwh); 5502 if (error != 0) { 5503 aprint_error_dev(sc->sc_dev, 5504 "could not read firmware %s\n", sc->fwname); 5505 goto out; 5506 } 5507 5508 /* Retrieve text and data sections. */ 5509 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5510 error = iwn_read_firmware_leg(sc, fw); 5511 else 5512 error = iwn_read_firmware_tlv(sc, fw, 1); 5513 if (error != 0) { 5514 aprint_error_dev(sc->sc_dev, 5515 "could not read firmware sections\n"); 5516 goto out; 5517 } 5518 5519 /* Make sure text and data sections fit in hardware memory. */ 5520 if (fw->main.textsz > sc->fw_text_maxsz || 5521 fw->main.datasz > sc->fw_data_maxsz || 5522 fw->init.textsz > sc->fw_text_maxsz || 5523 fw->init.datasz > sc->fw_data_maxsz || 5524 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5525 (fw->boot.textsz & 3) != 0) { 5526 aprint_error_dev(sc->sc_dev, 5527 "firmware sections too large\n"); 5528 goto out; 5529 } 5530 5531 /* We can proceed with loading the firmware. */ 5532 return 0; 5533 out: 5534 firmware_free(fw->data, fw->size); 5535 fw->data = NULL; 5536 fw->size = 0; 5537 return error ? error : EINVAL; 5538 } 5539 5540 static int 5541 iwn_clock_wait(struct iwn_softc *sc) 5542 { 5543 int ntries; 5544 5545 /* Set "initialization complete" bit. */ 5546 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5547 5548 /* Wait for clock stabilization. */ 5549 for (ntries = 0; ntries < 2500; ntries++) { 5550 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5551 return 0; 5552 DELAY(10); 5553 } 5554 aprint_error_dev(sc->sc_dev, 5555 "timeout waiting for clock stabilization\n"); 5556 return ETIMEDOUT; 5557 } 5558 5559 static int 5560 iwn_apm_init(struct iwn_softc *sc) 5561 { 5562 pcireg_t reg; 5563 int error; 5564 5565 /* Disable L0s exit timer (NMI bug workaround). */ 5566 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5567 /* Don't wait for ICH L0s (ICH bug workaround). */ 5568 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5569 5570 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5571 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5572 5573 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5574 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5575 5576 /* Retrieve PCIe Active State Power Management (ASPM). */ 5577 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5578 sc->sc_cap_off + PCIE_LCSR); 5579 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5580 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5581 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5582 else 5583 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5584 5585 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5586 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5587 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5588 5589 /* Wait for clock stabilization before accessing prph. */ 5590 if ((error = iwn_clock_wait(sc)) != 0) 5591 return error; 5592 5593 if ((error = iwn_nic_lock(sc)) != 0) 5594 return error; 5595 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5596 /* Enable DMA and BSM (Bootstrap State Machine). */ 5597 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5598 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5599 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5600 } else { 5601 /* Enable DMA. */ 5602 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5603 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5604 } 5605 DELAY(20); 5606 /* Disable L1-Active. */ 5607 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5608 iwn_nic_unlock(sc); 5609 5610 return 0; 5611 } 5612 5613 static void 5614 iwn_apm_stop_master(struct iwn_softc *sc) 5615 { 5616 int ntries; 5617 5618 /* Stop busmaster DMA activity. */ 5619 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5620 for (ntries = 0; ntries < 100; ntries++) { 5621 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5622 return; 5623 DELAY(10); 5624 } 5625 aprint_error_dev(sc->sc_dev, 5626 "timeout waiting for master\n"); 5627 } 5628 5629 static void 5630 iwn_apm_stop(struct iwn_softc *sc) 5631 { 5632 iwn_apm_stop_master(sc); 5633 5634 /* Reset the entire device. */ 5635 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5636 DELAY(10); 5637 /* Clear "initialization complete" bit. */ 5638 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5639 } 5640 5641 static int 5642 iwn4965_nic_config(struct iwn_softc *sc) 5643 { 5644 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5645 /* 5646 * I don't believe this to be correct but this is what the 5647 * vendor driver is doing. Probably the bits should not be 5648 * shifted in IWN_RFCFG_*. 5649 */ 5650 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5651 IWN_RFCFG_TYPE(sc->rfcfg) | 5652 IWN_RFCFG_STEP(sc->rfcfg) | 5653 IWN_RFCFG_DASH(sc->rfcfg)); 5654 } 5655 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5656 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5657 return 0; 5658 } 5659 5660 static int 5661 iwn5000_nic_config(struct iwn_softc *sc) 5662 { 5663 uint32_t tmp; 5664 int error; 5665 5666 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5667 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5668 IWN_RFCFG_TYPE(sc->rfcfg) | 5669 IWN_RFCFG_STEP(sc->rfcfg) | 5670 IWN_RFCFG_DASH(sc->rfcfg)); 5671 } 5672 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5673 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5674 5675 if ((error = iwn_nic_lock(sc)) != 0) 5676 return error; 5677 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 5678 5679 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 5680 /* 5681 * Select first Switching Voltage Regulator (1.32V) to 5682 * solve a stability issue related to noisy DC2DC line 5683 * in the silicon of 1000 Series. 5684 */ 5685 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 5686 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 5687 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 5688 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 5689 } 5690 iwn_nic_unlock(sc); 5691 5692 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 5693 /* Use internal power amplifier only. */ 5694 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 5695 } 5696 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 5697 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 5698 /* Indicate that ROM calibration version is >=6. */ 5699 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 5700 } 5701 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 5702 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 5703 return 0; 5704 } 5705 5706 /* 5707 * Take NIC ownership over Intel Active Management Technology (AMT). 5708 */ 5709 static int 5710 iwn_hw_prepare(struct iwn_softc *sc) 5711 { 5712 int ntries; 5713 5714 /* Check if hardware is ready. */ 5715 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5716 for (ntries = 0; ntries < 5; ntries++) { 5717 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5718 IWN_HW_IF_CONFIG_NIC_READY) 5719 return 0; 5720 DELAY(10); 5721 } 5722 5723 /* Hardware not ready, force into ready state. */ 5724 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 5725 for (ntries = 0; ntries < 15000; ntries++) { 5726 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 5727 IWN_HW_IF_CONFIG_PREPARE_DONE)) 5728 break; 5729 DELAY(10); 5730 } 5731 if (ntries == 15000) 5732 return ETIMEDOUT; 5733 5734 /* Hardware should be ready now. */ 5735 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 5736 for (ntries = 0; ntries < 5; ntries++) { 5737 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 5738 IWN_HW_IF_CONFIG_NIC_READY) 5739 return 0; 5740 DELAY(10); 5741 } 5742 return ETIMEDOUT; 5743 } 5744 5745 static int 5746 iwn_hw_init(struct iwn_softc *sc) 5747 { 5748 struct iwn_ops *ops = &sc->ops; 5749 int error, chnl, qid; 5750 5751 /* Clear pending interrupts. */ 5752 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5753 5754 if ((error = iwn_apm_init(sc)) != 0) { 5755 aprint_error_dev(sc->sc_dev, 5756 "could not power ON adapter\n"); 5757 return error; 5758 } 5759 5760 /* Select VMAIN power source. */ 5761 if ((error = iwn_nic_lock(sc)) != 0) 5762 return error; 5763 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 5764 iwn_nic_unlock(sc); 5765 5766 /* Perform adapter-specific initialization. */ 5767 if ((error = ops->nic_config(sc)) != 0) 5768 return error; 5769 5770 /* Initialize RX ring. */ 5771 if ((error = iwn_nic_lock(sc)) != 0) 5772 return error; 5773 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 5774 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 5775 /* Set physical address of RX ring (256-byte aligned). */ 5776 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 5777 /* Set physical address of RX status (16-byte aligned). */ 5778 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 5779 /* Enable RX. */ 5780 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 5781 IWN_FH_RX_CONFIG_ENA | 5782 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 5783 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 5784 IWN_FH_RX_CONFIG_SINGLE_FRAME | 5785 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 5786 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 5787 iwn_nic_unlock(sc); 5788 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 5789 5790 if ((error = iwn_nic_lock(sc)) != 0) 5791 return error; 5792 5793 /* Initialize TX scheduler. */ 5794 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5795 5796 /* Set physical address of "keep warm" page (16-byte aligned). */ 5797 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 5798 5799 /* Initialize TX rings. */ 5800 for (qid = 0; qid < sc->ntxqs; qid++) { 5801 struct iwn_tx_ring *txq = &sc->txq[qid]; 5802 5803 /* Set physical address of TX ring (256-byte aligned). */ 5804 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 5805 txq->desc_dma.paddr >> 8); 5806 } 5807 iwn_nic_unlock(sc); 5808 5809 /* Enable DMA channels. */ 5810 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5811 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 5812 IWN_FH_TX_CONFIG_DMA_ENA | 5813 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 5814 } 5815 5816 /* Clear "radio off" and "commands blocked" bits. */ 5817 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5818 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 5819 5820 /* Clear pending interrupts. */ 5821 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5822 /* Enable interrupt coalescing. */ 5823 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 5824 /* Enable interrupts. */ 5825 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 5826 5827 /* _Really_ make sure "radio off" bit is cleared! */ 5828 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5829 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 5830 5831 /* Enable shadow registers. */ 5832 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 5833 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 5834 5835 if ((error = ops->load_firmware(sc)) != 0) { 5836 aprint_error_dev(sc->sc_dev, 5837 "could not load firmware\n"); 5838 return error; 5839 } 5840 /* Wait at most one second for firmware alive notification. */ 5841 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5842 aprint_error_dev(sc->sc_dev, 5843 "timeout waiting for adapter to initialize\n"); 5844 return error; 5845 } 5846 /* Do post-firmware initialization. */ 5847 return ops->post_alive(sc); 5848 } 5849 5850 static void 5851 iwn_hw_stop(struct iwn_softc *sc) 5852 { 5853 int chnl, qid, ntries; 5854 5855 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 5856 5857 /* Disable interrupts. */ 5858 IWN_WRITE(sc, IWN_INT_MASK, 0); 5859 IWN_WRITE(sc, IWN_INT, 0xffffffff); 5860 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 5861 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5862 5863 /* Make sure we no longer hold the NIC lock. */ 5864 iwn_nic_unlock(sc); 5865 5866 /* Stop TX scheduler. */ 5867 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 5868 5869 /* Stop all DMA channels. */ 5870 if (iwn_nic_lock(sc) == 0) { 5871 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 5872 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 5873 for (ntries = 0; ntries < 200; ntries++) { 5874 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 5875 IWN_FH_TX_STATUS_IDLE(chnl)) 5876 break; 5877 DELAY(10); 5878 } 5879 } 5880 iwn_nic_unlock(sc); 5881 } 5882 5883 /* Stop RX ring. */ 5884 iwn_reset_rx_ring(sc, &sc->rxq); 5885 5886 /* Reset all TX rings. */ 5887 for (qid = 0; qid < sc->ntxqs; qid++) 5888 iwn_reset_tx_ring(sc, &sc->txq[qid]); 5889 5890 if (iwn_nic_lock(sc) == 0) { 5891 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 5892 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5893 iwn_nic_unlock(sc); 5894 } 5895 DELAY(5); 5896 /* Power OFF adapter. */ 5897 iwn_apm_stop(sc); 5898 } 5899 5900 static int 5901 iwn_init(struct ifnet *ifp) 5902 { 5903 struct iwn_softc *sc = ifp->if_softc; 5904 struct ieee80211com *ic = &sc->sc_ic; 5905 int error; 5906 5907 mutex_enter(&sc->sc_mtx); 5908 if (sc->sc_flags & IWN_FLAG_HW_INITED) 5909 goto out; 5910 if ((error = iwn_hw_prepare(sc)) != 0) { 5911 aprint_error_dev(sc->sc_dev, 5912 "hardware not ready\n"); 5913 goto fail; 5914 } 5915 5916 /* Check that the radio is not disabled by hardware switch. */ 5917 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 5918 aprint_error_dev(sc->sc_dev, 5919 "radio is disabled by hardware switch\n"); 5920 error = EPERM; /* :-) */ 5921 goto fail; 5922 } 5923 5924 /* Read firmware images from the filesystem. */ 5925 if ((error = iwn_read_firmware(sc)) != 0) { 5926 aprint_error_dev(sc->sc_dev, 5927 "could not read firmware\n"); 5928 goto fail; 5929 } 5930 5931 /* Initialize interrupt mask to default value. */ 5932 sc->int_mask = IWN_INT_MASK_DEF; 5933 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 5934 5935 /* Initialize hardware and upload firmware. */ 5936 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 5937 error = iwn_hw_init(sc); 5938 firmware_free(sc->fw.data, sc->fw.size); 5939 sc->fw.data = NULL; 5940 sc->fw.size = 0; 5941 if (error != 0) { 5942 aprint_error_dev(sc->sc_dev, 5943 "could not initialize hardware\n"); 5944 goto fail; 5945 } 5946 5947 /* Configure adapter now that it is ready. */ 5948 if ((error = iwn_config(sc)) != 0) { 5949 aprint_error_dev(sc->sc_dev, 5950 "could not configure device\n"); 5951 goto fail; 5952 } 5953 5954 ifp->if_flags &= ~IFF_OACTIVE; 5955 ifp->if_flags |= IFF_RUNNING; 5956 5957 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5958 ieee80211_begin_scan(ic, 0); 5959 else 5960 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5961 5962 sc->sc_flags |= IWN_FLAG_HW_INITED; 5963 out: 5964 mutex_exit(&sc->sc_mtx); 5965 return 0; 5966 5967 fail: mutex_exit(&sc->sc_mtx); 5968 iwn_stop(ifp, 1); 5969 return error; 5970 } 5971 5972 static void 5973 iwn_stop(struct ifnet *ifp, int disable) 5974 { 5975 struct iwn_softc *sc = ifp->if_softc; 5976 struct ieee80211com *ic = &sc->sc_ic; 5977 5978 if (!disable) 5979 mutex_enter(&sc->sc_mtx); 5980 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 5981 ifp->if_timer = sc->sc_tx_timer = 0; 5982 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5983 5984 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5985 5986 /* Power OFF hardware. */ 5987 iwn_hw_stop(sc); 5988 5989 if (!disable) 5990 mutex_exit(&sc->sc_mtx); 5991 } 5992 5993 /* 5994 * XXX MCLGETI alternative 5995 * 5996 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 5997 * as long as there are available free buffers then it uses MEXTMALLOC., 5998 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 5999 * The MCLGET4K code is used for testing an alternative mbuf cache. 6000 */ 6001 6002 static struct mbuf * 6003 MCLGETIalt(struct iwn_softc *sc, int how, 6004 struct ifnet *ifp __unused, u_int size) 6005 { 6006 struct mbuf *m; 6007 #ifdef IWN_USE_RBUF 6008 struct iwn_rbuf *rbuf; 6009 #endif 6010 6011 MGETHDR(m, how, MT_DATA); 6012 if (m == NULL) 6013 return NULL; 6014 6015 #ifdef IWN_USE_RBUF 6016 if (sc->rxq.nb_free_entries > 0 && 6017 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 6018 /* Attach buffer to mbuf header. */ 6019 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 6020 m->m_flags |= M_EXT_RW; 6021 } 6022 else { 6023 MEXTMALLOC(m, size, how); 6024 if ((m->m_flags & M_EXT) == 0) { 6025 m_freem(m); 6026 return NULL; 6027 } 6028 } 6029 6030 #else 6031 #ifdef MCLGET4K 6032 if (size == 4096) 6033 MCLGET4K(m, how); 6034 else 6035 panic("size must be 4k"); 6036 #else 6037 MEXTMALLOC(m, size, how); 6038 #endif 6039 if ((m->m_flags & M_EXT) == 0) { 6040 m_freem(m); 6041 return NULL; 6042 } 6043 #endif 6044 6045 return m; 6046 } 6047 6048 #ifdef IWN_USE_RBUF 6049 static struct iwn_rbuf * 6050 iwn_alloc_rbuf(struct iwn_softc *sc) 6051 { 6052 struct iwn_rbuf *rbuf; 6053 mutex_enter(&sc->rxq.freelist_mtx); 6054 6055 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6056 if (rbuf != NULL) { 6057 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6058 sc->rxq.nb_free_entries --; 6059 } 6060 mutex_exit(&sc->rxq.freelist_mtx); 6061 return rbuf; 6062 } 6063 6064 /* 6065 * This is called automatically by the network stack when the mbuf to which 6066 * our RX buffer is attached is freed. 6067 */ 6068 static void 6069 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6070 { 6071 struct iwn_rbuf *rbuf = arg; 6072 struct iwn_softc *sc = rbuf->sc; 6073 6074 /* Put the RX buffer back in the free list. */ 6075 mutex_enter(&sc->rxq.freelist_mtx); 6076 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6077 mutex_exit(&sc->rxq.freelist_mtx); 6078 6079 sc->rxq.nb_free_entries ++; 6080 if (__predict_true(m != NULL)) 6081 pool_cache_put(mb_cache, m); 6082 } 6083 6084 static int 6085 iwn_alloc_rpool(struct iwn_softc *sc) 6086 { 6087 struct iwn_rx_ring *ring = &sc->rxq; 6088 struct iwn_rbuf *rbuf; 6089 int i, error; 6090 6091 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6092 6093 /* Allocate a big chunk of DMA'able memory... */ 6094 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6095 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6096 if (error != 0) { 6097 aprint_error_dev(sc->sc_dev, 6098 "could not allocate RX buffers DMA memory\n"); 6099 return error; 6100 } 6101 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6102 SLIST_INIT(&ring->freelist); 6103 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6104 rbuf = &ring->rbuf[i]; 6105 6106 rbuf->sc = sc; /* Backpointer for callbacks. */ 6107 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6108 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6109 6110 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6111 } 6112 ring->nb_free_entries = IWN_RBUF_COUNT; 6113 return 0; 6114 } 6115 6116 static void 6117 iwn_free_rpool(struct iwn_softc *sc) 6118 { 6119 iwn_dma_contig_free(&sc->rxq.buf_dma); 6120 } 6121 #endif 6122 6123 /* 6124 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6125 * Copyright (c) 2001 Atsushi Onoe 6126 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6127 * Copyright (c) 2007-2009 Damien Bergamini 6128 * All rights reserved. 6129 */ 6130 6131 /* 6132 * Add an SSID element to a frame (see 7.3.2.1). 6133 */ 6134 static u_int8_t * 6135 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6136 { 6137 *frm++ = IEEE80211_ELEMID_SSID; 6138 *frm++ = len; 6139 memcpy(frm, ssid, len); 6140 return frm + len; 6141 } 6142 6143 /* 6144 * Add a supported rates element to a frame (see 7.3.2.2). 6145 */ 6146 static u_int8_t * 6147 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6148 { 6149 int nrates; 6150 6151 *frm++ = IEEE80211_ELEMID_RATES; 6152 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6153 *frm++ = nrates; 6154 memcpy(frm, rs->rs_rates, nrates); 6155 return frm + nrates; 6156 } 6157 6158 /* 6159 * Add an extended supported rates element to a frame (see 7.3.2.14). 6160 */ 6161 static u_int8_t * 6162 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6163 { 6164 int nrates; 6165 6166 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6167 6168 *frm++ = IEEE80211_ELEMID_XRATES; 6169 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6170 *frm++ = nrates; 6171 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6172 return frm + nrates; 6173 } 6174 6175 /* 6176 * XXX: Hack to set the current channel to the value advertised in beacons or 6177 * probe responses. Only used during AP detection. 6178 * XXX: Duplicated from if_iwi.c 6179 */ 6180 static void 6181 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6182 { 6183 struct ieee80211_frame *wh; 6184 uint8_t subtype; 6185 uint8_t *frm, *efrm; 6186 6187 wh = mtod(m, struct ieee80211_frame *); 6188 6189 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6190 return; 6191 6192 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6193 6194 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6195 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6196 return; 6197 6198 frm = (uint8_t *)(wh + 1); 6199 efrm = mtod(m, uint8_t *) + m->m_len; 6200 6201 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6202 while (frm < efrm) { 6203 if (*frm == IEEE80211_ELEMID_DSPARMS) 6204 #if IEEE80211_CHAN_MAX < 255 6205 if (frm[2] <= IEEE80211_CHAN_MAX) 6206 #endif 6207 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6208 6209 frm += frm[1] + 2; 6210 } 6211 } 6212 6213 #ifdef notyetMODULE 6214 6215 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci"); 6216 6217 #ifdef _MODULE 6218 #include "ioconf.c" 6219 #endif 6220 6221 static int 6222 if_iwn_modcmd(modcmd_t cmd, void *data) 6223 { 6224 int error = 0; 6225 6226 switch (cmd) { 6227 case MODULE_CMD_INIT: 6228 #ifdef _MODULE 6229 error = config_init_component(cfdriver_ioconf_if_iwn, 6230 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6231 #endif 6232 return error; 6233 case MODULE_CMD_FINI: 6234 #ifdef _MODULE 6235 error = config_fini_component(cfdriver_ioconf_if_iwn, 6236 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6237 #endif 6238 return error; 6239 case MODULE_CMD_AUTOUNLOAD: 6240 #ifdef _MODULE 6241 /* XXX This is not optional! */ 6242 #endif 6243 return error; 6244 default: 6245 return ENOTTY; 6246 } 6247 } 6248 #endif 6249
Indexes created Mon Sep 29 03:10:08 GMT 2025