if_iwn.c revision 1.71.4.2
1 /* $NetBSD: if_iwn.c,v 1.71.4.2 2015/11/06 00:50:52 riz Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.71.4.2 2015/11/06 00:50:52 riz Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #ifdef notyetMODULE 39 #include <sys/module.h> 40 #endif 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <sys/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2, 107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1, 108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2, 109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1, 110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2, 111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1, 112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2, 113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1, 114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2, 115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1, 116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2, 117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1, 118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2, 119 }; 120 121 /* 122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 123 */ 124 static const struct ieee80211_rateset iwn_rateset_11a = 125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 126 127 static const struct ieee80211_rateset iwn_rateset_11b = 128 { 4, { 2, 4, 11, 22 } }; 129 130 static const struct ieee80211_rateset iwn_rateset_11g = 131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 132 133 static int iwn_match(device_t , struct cfdata *, void *); 134 static void iwn_attach(device_t , device_t , void *); 135 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 136 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static int iwn_detach(device_t , int); 139 #if 0 140 static void iwn_power(int, void *); 141 #endif 142 static bool iwn_resume(device_t, const pmf_qual_t *); 143 static int iwn_nic_lock(struct iwn_softc *); 144 static int iwn_eeprom_lock(struct iwn_softc *); 145 static int iwn_init_otprom(struct iwn_softc *); 146 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 147 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 148 void **, bus_size_t, bus_size_t); 149 static void iwn_dma_contig_free(struct iwn_dma_info *); 150 static int iwn_alloc_sched(struct iwn_softc *); 151 static void iwn_free_sched(struct iwn_softc *); 152 static int iwn_alloc_kw(struct iwn_softc *); 153 static void iwn_free_kw(struct iwn_softc *); 154 static int iwn_alloc_ict(struct iwn_softc *); 155 static void iwn_free_ict(struct iwn_softc *); 156 static int iwn_alloc_fwmem(struct iwn_softc *); 157 static void iwn_free_fwmem(struct iwn_softc *); 158 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 159 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 160 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 161 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 162 int); 163 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 164 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 165 static void iwn5000_ict_reset(struct iwn_softc *); 166 static int iwn_read_eeprom(struct iwn_softc *); 167 static void iwn4965_read_eeprom(struct iwn_softc *); 168 169 #ifdef IWN_DEBUG 170 static void iwn4965_print_power_group(struct iwn_softc *, int); 171 #endif 172 static void iwn5000_read_eeprom(struct iwn_softc *); 173 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 174 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 175 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 176 static void iwn_newassoc(struct ieee80211_node *, int); 177 static int iwn_media_change(struct ifnet *); 178 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 179 static void iwn_iter_func(void *, struct ieee80211_node *); 180 static void iwn_calib_timeout(void *); 181 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 #ifndef IEEE80211_NO_HT 186 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 187 struct iwn_rx_data *); 188 #endif 189 static void iwn5000_rx_calib_results(struct iwn_softc *, 190 struct iwn_rx_desc *, struct iwn_rx_data *); 191 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 192 struct iwn_rx_data *); 193 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 194 struct iwn_rx_data *); 195 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 196 struct iwn_rx_data *); 197 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 198 uint8_t); 199 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 200 static void iwn_notif_intr(struct iwn_softc *); 201 static void iwn_wakeup_intr(struct iwn_softc *); 202 static void iwn_fatal_intr(struct iwn_softc *); 203 static int iwn_intr(void *); 204 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 205 uint16_t); 206 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 207 uint16_t); 208 #ifdef notyet 209 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 210 #endif 211 static int iwn_tx(struct iwn_softc *, struct mbuf *, 212 struct ieee80211_node *, int); 213 static void iwn_start(struct ifnet *); 214 static void iwn_watchdog(struct ifnet *); 215 static int iwn_ioctl(struct ifnet *, u_long, void *); 216 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 217 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 218 int); 219 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 220 int); 221 static int iwn_set_link_quality(struct iwn_softc *, 222 struct ieee80211_node *); 223 static int iwn_add_broadcast_node(struct iwn_softc *, int); 224 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 225 static int iwn_set_critical_temp(struct iwn_softc *); 226 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 227 static void iwn4965_power_calibration(struct iwn_softc *, int); 228 static int iwn4965_set_txpower(struct iwn_softc *, int); 229 static int iwn5000_set_txpower(struct iwn_softc *, int); 230 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 231 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 232 static int iwn_get_noise(const struct iwn_rx_general_stats *); 233 static int iwn4965_get_temperature(struct iwn_softc *); 234 static int iwn5000_get_temperature(struct iwn_softc *); 235 static int iwn_init_sensitivity(struct iwn_softc *); 236 static void iwn_collect_noise(struct iwn_softc *, 237 const struct iwn_rx_general_stats *); 238 static int iwn4965_init_gains(struct iwn_softc *); 239 static int iwn5000_init_gains(struct iwn_softc *); 240 static int iwn4965_set_gains(struct iwn_softc *); 241 static int iwn5000_set_gains(struct iwn_softc *); 242 static void iwn_tune_sensitivity(struct iwn_softc *, 243 const struct iwn_rx_stats *); 244 static int iwn_send_sensitivity(struct iwn_softc *); 245 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 246 static int iwn5000_runtime_calib(struct iwn_softc *); 247 248 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 249 static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 250 static int iwn_config_bt_coex_adv1(struct iwn_softc *); 251 static int iwn_config_bt_coex_adv2(struct iwn_softc *); 252 253 static int iwn_config(struct iwn_softc *); 254 static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, 255 uint8_t); 256 static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 257 static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 258 static int iwn_scan(struct iwn_softc *, uint16_t); 259 static int iwn_auth(struct iwn_softc *); 260 static int iwn_run(struct iwn_softc *); 261 #ifdef IWN_HWCRYPTO 262 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 263 struct ieee80211_key *); 264 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 265 struct ieee80211_key *); 266 #endif 267 static int iwn_wme_update(struct ieee80211com *); 268 #ifndef IEEE80211_NO_HT 269 static int iwn_ampdu_rx_start(struct ieee80211com *, 270 struct ieee80211_node *, uint8_t); 271 static void iwn_ampdu_rx_stop(struct ieee80211com *, 272 struct ieee80211_node *, uint8_t); 273 static int iwn_ampdu_tx_start(struct ieee80211com *, 274 struct ieee80211_node *, uint8_t); 275 static void iwn_ampdu_tx_stop(struct ieee80211com *, 276 struct ieee80211_node *, uint8_t); 277 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 278 struct ieee80211_node *, uint8_t, uint16_t); 279 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 280 uint8_t, uint16_t); 281 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 282 struct ieee80211_node *, uint8_t, uint16_t); 283 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 284 uint8_t, uint16_t); 285 #endif 286 static int iwn5000_query_calibration(struct iwn_softc *); 287 static int iwn5000_send_calibration(struct iwn_softc *); 288 static int iwn5000_send_wimax_coex(struct iwn_softc *); 289 static int iwn6000_temp_offset_calib(struct iwn_softc *); 290 static int iwn2000_temp_offset_calib(struct iwn_softc *); 291 static int iwn4965_post_alive(struct iwn_softc *); 292 static int iwn5000_post_alive(struct iwn_softc *); 293 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 294 int); 295 static int iwn4965_load_firmware(struct iwn_softc *); 296 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 297 const uint8_t *, int); 298 static int iwn5000_load_firmware(struct iwn_softc *); 299 static int iwn_read_firmware_leg(struct iwn_softc *, 300 struct iwn_fw_info *); 301 static int iwn_read_firmware_tlv(struct iwn_softc *, 302 struct iwn_fw_info *, uint16_t); 303 static int iwn_read_firmware(struct iwn_softc *); 304 static int iwn_clock_wait(struct iwn_softc *); 305 static int iwn_apm_init(struct iwn_softc *); 306 static void iwn_apm_stop_master(struct iwn_softc *); 307 static void iwn_apm_stop(struct iwn_softc *); 308 static int iwn4965_nic_config(struct iwn_softc *); 309 static int iwn5000_nic_config(struct iwn_softc *); 310 static int iwn_hw_prepare(struct iwn_softc *); 311 static int iwn_hw_init(struct iwn_softc *); 312 static void iwn_hw_stop(struct iwn_softc *); 313 static int iwn_init(struct ifnet *); 314 static void iwn_stop(struct ifnet *, int); 315 316 /* XXX MCLGETI alternative */ 317 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 318 struct ifnet *, u_int); 319 #ifdef IWN_USE_RBUF 320 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 321 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 322 static int iwn_alloc_rpool(struct iwn_softc *); 323 static void iwn_free_rpool(struct iwn_softc *); 324 #endif 325 326 /* XXX needed by iwn_scan */ 327 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 328 static u_int8_t *ieee80211_add_rates(u_int8_t *, 329 const struct ieee80211_rateset *); 330 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 331 const struct ieee80211_rateset *); 332 333 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *, 334 struct iwn_rx_stat *); 335 336 #ifdef IWN_DEBUG 337 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 338 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 339 int iwn_debug = 0; 340 #else 341 #define DPRINTF(x) 342 #define DPRINTFN(n, x) 343 #endif 344 345 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 346 iwn_detach, NULL); 347 348 static int 349 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 350 { 351 struct pci_attach_args *pa = aux; 352 size_t i; 353 354 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 355 return 0; 356 357 for (i = 0; i < __arraycount(iwn_devices); i++) 358 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 359 return 1; 360 361 return 0; 362 } 363 364 static void 365 iwn_attach(device_t parent __unused, device_t self, void *aux) 366 { 367 struct iwn_softc *sc = device_private(self); 368 struct ieee80211com *ic = &sc->sc_ic; 369 struct ifnet *ifp = &sc->sc_ec.ec_if; 370 struct pci_attach_args *pa = aux; 371 const char *intrstr; 372 pci_intr_handle_t ih; 373 pcireg_t memtype, reg; 374 int i, error; 375 char intrbuf[PCI_INTRSTR_LEN]; 376 377 sc->sc_dev = self; 378 sc->sc_pct = pa->pa_pc; 379 sc->sc_pcitag = pa->pa_tag; 380 sc->sc_dmat = pa->pa_dmat; 381 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 382 383 callout_init(&sc->calib_to, 0); 384 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 385 386 pci_aprint_devinfo(pa, NULL); 387 388 /* 389 * Get the offset of the PCI Express Capability Structure in PCI 390 * Configuration Space. 391 */ 392 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 393 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 394 if (error == 0) { 395 aprint_error(": PCIe capability structure not found!\n"); 396 return; 397 } 398 399 /* Clear device-specific "PCI retry timeout" register (41h). */ 400 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 401 if (reg & 0xff00) 402 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 403 404 /* Enable bus-mastering and hardware bug workaround. */ 405 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 406 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 407 reg |= PCI_COMMAND_MASTER_ENABLE; 408 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 409 DPRINTF(("PCIe INTx Disable set\n")); 410 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 411 } 412 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 413 414 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 415 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 416 &sc->sc_sh, NULL, &sc->sc_sz); 417 if (error != 0) { 418 aprint_error(": can't map mem space\n"); 419 return; 420 } 421 422 /* Install interrupt handler. */ 423 if (pci_intr_map(pa, &ih) != 0) { 424 aprint_error(": can't map interrupt\n"); 425 return; 426 } 427 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 428 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 429 if (sc->sc_ih == NULL) { 430 aprint_error(": can't establish interrupt"); 431 if (intrstr != NULL) 432 aprint_error(" at %s", intrstr); 433 aprint_error("\n"); 434 return; 435 } 436 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 437 438 /* Read hardware revision and attach. */ 439 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 440 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 441 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 442 else 443 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 444 if (error != 0) { 445 aprint_error(": could not attach device\n"); 446 return; 447 } 448 449 if ((error = iwn_hw_prepare(sc)) != 0) { 450 aprint_error(": hardware not ready\n"); 451 return; 452 } 453 454 /* Read MAC address, channels, etc from EEPROM. */ 455 if ((error = iwn_read_eeprom(sc)) != 0) { 456 aprint_error(": could not read EEPROM\n"); 457 return; 458 } 459 460 /* Allocate DMA memory for firmware transfers. */ 461 if ((error = iwn_alloc_fwmem(sc)) != 0) { 462 aprint_error(": could not allocate memory for firmware\n"); 463 return; 464 } 465 466 /* Allocate "Keep Warm" page. */ 467 if ((error = iwn_alloc_kw(sc)) != 0) { 468 aprint_error(": could not allocate keep warm page\n"); 469 goto fail1; 470 } 471 472 /* Allocate ICT table for 5000 Series. */ 473 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 474 (error = iwn_alloc_ict(sc)) != 0) { 475 aprint_error(": could not allocate ICT table\n"); 476 goto fail2; 477 } 478 479 /* Allocate TX scheduler "rings". */ 480 if ((error = iwn_alloc_sched(sc)) != 0) { 481 aprint_error(": could not allocate TX scheduler rings\n"); 482 goto fail3; 483 } 484 485 #ifdef IWN_USE_RBUF 486 /* Allocate RX buffers. */ 487 if ((error = iwn_alloc_rpool(sc)) != 0) { 488 aprint_error_dev(self, "could not allocate RX buffers\n"); 489 goto fail3; 490 } 491 #endif 492 493 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 494 for (i = 0; i < sc->ntxqs; i++) { 495 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 496 aprint_error(": could not allocate TX ring %d\n", i); 497 goto fail4; 498 } 499 } 500 501 /* Allocate RX ring. */ 502 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 503 aprint_error(": could not allocate RX ring\n"); 504 goto fail4; 505 } 506 507 /* Clear pending interrupts. */ 508 IWN_WRITE(sc, IWN_INT, 0xffffffff); 509 510 /* Count the number of available chains. */ 511 sc->ntxchains = 512 ((sc->txchainmask >> 2) & 1) + 513 ((sc->txchainmask >> 1) & 1) + 514 ((sc->txchainmask >> 0) & 1); 515 sc->nrxchains = 516 ((sc->rxchainmask >> 2) & 1) + 517 ((sc->rxchainmask >> 1) & 1) + 518 ((sc->rxchainmask >> 0) & 1); 519 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 520 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 521 ether_sprintf(ic->ic_myaddr)); 522 523 ic->ic_ifp = ifp; 524 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 525 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 526 ic->ic_state = IEEE80211_S_INIT; 527 528 /* Set device capabilities. */ 529 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 530 * and IEEE80211_C_PMGT too. */ 531 ic->ic_caps = 532 IEEE80211_C_IBSS | /* IBSS mode support */ 533 IEEE80211_C_WPA | /* 802.11i */ 534 IEEE80211_C_MONITOR | /* monitor mode supported */ 535 IEEE80211_C_TXPMGT | /* tx power management */ 536 IEEE80211_C_SHSLOT | /* short slot time supported */ 537 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 538 IEEE80211_C_WME; /* 802.11e */ 539 540 #ifndef IEEE80211_NO_HT 541 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 542 /* Set HT capabilities. */ 543 ic->ic_htcaps = 544 #if IWN_RBUF_SIZE == 8192 545 IEEE80211_HTCAP_AMSDU7935 | 546 #endif 547 IEEE80211_HTCAP_CBW20_40 | 548 IEEE80211_HTCAP_SGI20 | 549 IEEE80211_HTCAP_SGI40; 550 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 551 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 552 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 553 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 554 else 555 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 556 } 557 #endif /* !IEEE80211_NO_HT */ 558 559 /* Set supported legacy rates. */ 560 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 561 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 562 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 563 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 564 } 565 #ifndef IEEE80211_NO_HT 566 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 567 /* Set supported HT rates. */ 568 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 569 if (sc->nrxchains > 1) 570 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 571 if (sc->nrxchains > 2) 572 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 573 } 574 #endif 575 576 /* IBSS channel undefined for now. */ 577 ic->ic_ibss_chan = &ic->ic_channels[0]; 578 579 ifp->if_softc = sc; 580 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 581 ifp->if_init = iwn_init; 582 ifp->if_ioctl = iwn_ioctl; 583 ifp->if_start = iwn_start; 584 ifp->if_stop = iwn_stop; 585 ifp->if_watchdog = iwn_watchdog; 586 IFQ_SET_READY(&ifp->if_snd); 587 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 588 589 if_attach(ifp); 590 ieee80211_ifattach(ic); 591 ic->ic_node_alloc = iwn_node_alloc; 592 ic->ic_newassoc = iwn_newassoc; 593 #ifdef IWN_HWCRYPTO 594 ic->ic_crypto.cs_key_set = iwn_set_key; 595 ic->ic_crypto.cs_key_delete = iwn_delete_key; 596 #endif 597 ic->ic_wme.wme_update = iwn_wme_update; 598 #ifndef IEEE80211_NO_HT 599 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 600 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 601 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 602 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 603 #endif 604 605 /* Override 802.11 state transition machine. */ 606 sc->sc_newstate = ic->ic_newstate; 607 ic->ic_newstate = iwn_newstate; 608 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 609 610 sc->amrr.amrr_min_success_threshold = 1; 611 sc->amrr.amrr_max_success_threshold = 15; 612 613 iwn_radiotap_attach(sc); 614 615 /* 616 * XXX for NetBSD, OpenBSD timeout_set replaced by 617 * callout_init and callout_setfunc, above. 618 */ 619 620 if (pmf_device_register(self, NULL, iwn_resume)) 621 pmf_class_network_register(self, ifp); 622 else 623 aprint_error_dev(self, "couldn't establish power handler\n"); 624 625 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 626 ieee80211_announce(ic); 627 628 return; 629 630 /* Free allocated memory if something failed during attachment. */ 631 fail4: while (--i >= 0) 632 iwn_free_tx_ring(sc, &sc->txq[i]); 633 #ifdef IWN_USE_RBUF 634 iwn_free_rpool(sc); 635 #endif 636 iwn_free_sched(sc); 637 fail3: if (sc->ict != NULL) 638 iwn_free_ict(sc); 639 fail2: iwn_free_kw(sc); 640 fail1: iwn_free_fwmem(sc); 641 } 642 643 int 644 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 645 { 646 struct iwn_ops *ops = &sc->ops; 647 648 ops->load_firmware = iwn4965_load_firmware; 649 ops->read_eeprom = iwn4965_read_eeprom; 650 ops->post_alive = iwn4965_post_alive; 651 ops->nic_config = iwn4965_nic_config; 652 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 653 ops->update_sched = iwn4965_update_sched; 654 ops->get_temperature = iwn4965_get_temperature; 655 ops->get_rssi = iwn4965_get_rssi; 656 ops->set_txpower = iwn4965_set_txpower; 657 ops->init_gains = iwn4965_init_gains; 658 ops->set_gains = iwn4965_set_gains; 659 ops->add_node = iwn4965_add_node; 660 ops->tx_done = iwn4965_tx_done; 661 #ifndef IEEE80211_NO_HT 662 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 663 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 664 #endif 665 sc->ntxqs = IWN4965_NTXQUEUES; 666 sc->ndmachnls = IWN4965_NDMACHNLS; 667 sc->broadcast_id = IWN4965_ID_BROADCAST; 668 sc->rxonsz = IWN4965_RXONSZ; 669 sc->schedsz = IWN4965_SCHEDSZ; 670 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 671 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 672 sc->fwsz = IWN4965_FWSZ; 673 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 674 sc->limits = &iwn4965_sensitivity_limits; 675 sc->fwname = "iwlwifi-4965-2.ucode"; 676 /* Override chains masks, ROM is known to be broken. */ 677 sc->txchainmask = IWN_ANT_AB; 678 sc->rxchainmask = IWN_ANT_ABC; 679 680 return 0; 681 } 682 683 int 684 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 685 { 686 struct iwn_ops *ops = &sc->ops; 687 688 ops->load_firmware = iwn5000_load_firmware; 689 ops->read_eeprom = iwn5000_read_eeprom; 690 ops->post_alive = iwn5000_post_alive; 691 ops->nic_config = iwn5000_nic_config; 692 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 693 ops->update_sched = iwn5000_update_sched; 694 ops->get_temperature = iwn5000_get_temperature; 695 ops->get_rssi = iwn5000_get_rssi; 696 ops->set_txpower = iwn5000_set_txpower; 697 ops->init_gains = iwn5000_init_gains; 698 ops->set_gains = iwn5000_set_gains; 699 ops->add_node = iwn5000_add_node; 700 ops->tx_done = iwn5000_tx_done; 701 #ifndef IEEE80211_NO_HT 702 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 703 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 704 #endif 705 sc->ntxqs = IWN5000_NTXQUEUES; 706 sc->ndmachnls = IWN5000_NDMACHNLS; 707 sc->broadcast_id = IWN5000_ID_BROADCAST; 708 sc->rxonsz = IWN5000_RXONSZ; 709 sc->schedsz = IWN5000_SCHEDSZ; 710 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 711 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 712 sc->fwsz = IWN5000_FWSZ; 713 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 714 715 switch (sc->hw_type) { 716 case IWN_HW_REV_TYPE_5100: 717 sc->limits = &iwn5000_sensitivity_limits; 718 sc->fwname = "iwlwifi-5000-2.ucode"; 719 /* Override chains masks, ROM is known to be broken. */ 720 sc->txchainmask = IWN_ANT_B; 721 sc->rxchainmask = IWN_ANT_AB; 722 break; 723 case IWN_HW_REV_TYPE_5150: 724 sc->limits = &iwn5150_sensitivity_limits; 725 sc->fwname = "iwlwifi-5150-2.ucode"; 726 break; 727 case IWN_HW_REV_TYPE_5300: 728 case IWN_HW_REV_TYPE_5350: 729 sc->limits = &iwn5000_sensitivity_limits; 730 sc->fwname = "iwlwifi-5000-2.ucode"; 731 break; 732 case IWN_HW_REV_TYPE_1000: 733 sc->limits = &iwn1000_sensitivity_limits; 734 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 || 735 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2) 736 sc->fwname = "iwlwifi-100-5.ucode"; 737 else 738 sc->fwname = "iwlwifi-1000-3.ucode"; 739 break; 740 case IWN_HW_REV_TYPE_6000: 741 sc->limits = &iwn6000_sensitivity_limits; 742 sc->fwname = "iwlwifi-6000-4.ucode"; 743 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 744 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 745 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 746 /* Override chains masks, ROM is known to be broken. */ 747 sc->txchainmask = IWN_ANT_BC; 748 sc->rxchainmask = IWN_ANT_BC; 749 } 750 break; 751 case IWN_HW_REV_TYPE_6050: 752 sc->limits = &iwn6000_sensitivity_limits; 753 sc->fwname = "iwlwifi-6050-5.ucode"; 754 break; 755 case IWN_HW_REV_TYPE_6005: 756 sc->limits = &iwn6000_sensitivity_limits; 757 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 758 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 759 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 760 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 761 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 762 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 || 763 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) { 764 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 765 ops->config_bt_coex = iwn_config_bt_coex_adv1; 766 } 767 else 768 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 769 break; 770 case IWN_HW_REV_TYPE_2030: 771 sc->limits = &iwn2000_sensitivity_limits; 772 sc->fwname = "iwlwifi-2030-6.ucode"; 773 ops->config_bt_coex = iwn_config_bt_coex_adv2; 774 break; 775 case IWN_HW_REV_TYPE_2000: 776 sc->limits = &iwn2000_sensitivity_limits; 777 sc->fwname = "iwlwifi-2000-6.ucode"; 778 break; 779 case IWN_HW_REV_TYPE_135: 780 sc->limits = &iwn2000_sensitivity_limits; 781 sc->fwname = "iwlwifi-135-6.ucode"; 782 ops->config_bt_coex = iwn_config_bt_coex_adv2; 783 break; 784 case IWN_HW_REV_TYPE_105: 785 sc->limits = &iwn2000_sensitivity_limits; 786 sc->fwname = "iwlwifi-105-6.ucode"; 787 break; 788 default: 789 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 790 return ENOTSUP; 791 } 792 return 0; 793 } 794 795 /* 796 * Attach the interface to 802.11 radiotap. 797 */ 798 static void 799 iwn_radiotap_attach(struct iwn_softc *sc) 800 { 801 struct ifnet *ifp = sc->sc_ic.ic_ifp; 802 803 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 804 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 805 &sc->sc_drvbpf); 806 807 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 808 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 809 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 810 811 sc->sc_txtap_len = sizeof sc->sc_txtapu; 812 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 813 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 814 } 815 816 static int 817 iwn_detach(device_t self, int flags __unused) 818 { 819 struct iwn_softc *sc = device_private(self); 820 struct ifnet *ifp = sc->sc_ic.ic_ifp; 821 int qid; 822 823 callout_stop(&sc->calib_to); 824 825 /* Uninstall interrupt handler. */ 826 if (sc->sc_ih != NULL) 827 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 828 829 /* Free DMA resources. */ 830 iwn_free_rx_ring(sc, &sc->rxq); 831 for (qid = 0; qid < sc->ntxqs; qid++) 832 iwn_free_tx_ring(sc, &sc->txq[qid]); 833 #ifdef IWN_USE_RBUF 834 iwn_free_rpool(sc); 835 #endif 836 iwn_free_sched(sc); 837 iwn_free_kw(sc); 838 if (sc->ict != NULL) 839 iwn_free_ict(sc); 840 iwn_free_fwmem(sc); 841 842 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 843 844 ieee80211_ifdetach(&sc->sc_ic); 845 if_detach(ifp); 846 847 return 0; 848 } 849 850 #if 0 851 /* 852 * XXX Investigate if clearing the PCI retry timeout could eliminate 853 * the repeated scan calls. Also the calls to if_init and if_start 854 * are similar to the effect of adding the call to ifioctl_common . 855 */ 856 static void 857 iwn_power(int why, void *arg) 858 { 859 struct iwn_softc *sc = arg; 860 struct ifnet *ifp; 861 pcireg_t reg; 862 int s; 863 864 if (why != PWR_RESUME) 865 return; 866 867 /* Clear device-specific "PCI retry timeout" register (41h). */ 868 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 869 if (reg & 0xff00) 870 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 871 872 s = splnet(); 873 ifp = &sc->sc_ic.ic_if; 874 if (ifp->if_flags & IFF_UP) { 875 ifp->if_init(ifp); 876 if (ifp->if_flags & IFF_RUNNING) 877 ifp->if_start(ifp); 878 } 879 splx(s); 880 } 881 #endif 882 883 static bool 884 iwn_resume(device_t dv, const pmf_qual_t *qual) 885 { 886 return true; 887 } 888 889 static int 890 iwn_nic_lock(struct iwn_softc *sc) 891 { 892 int ntries; 893 894 /* Request exclusive access to NIC. */ 895 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 896 897 /* Spin until we actually get the lock. */ 898 for (ntries = 0; ntries < 1000; ntries++) { 899 if ((IWN_READ(sc, IWN_GP_CNTRL) & 900 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 901 IWN_GP_CNTRL_MAC_ACCESS_ENA) 902 return 0; 903 DELAY(10); 904 } 905 return ETIMEDOUT; 906 } 907 908 static __inline void 909 iwn_nic_unlock(struct iwn_softc *sc) 910 { 911 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 912 } 913 914 static __inline uint32_t 915 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 916 { 917 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 918 IWN_BARRIER_READ_WRITE(sc); 919 return IWN_READ(sc, IWN_PRPH_RDATA); 920 } 921 922 static __inline void 923 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 924 { 925 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 926 IWN_BARRIER_WRITE(sc); 927 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 928 } 929 930 static __inline void 931 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 932 { 933 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 934 } 935 936 static __inline void 937 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 938 { 939 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 940 } 941 942 static __inline void 943 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 944 const uint32_t *data, int count) 945 { 946 for (; count > 0; count--, data++, addr += 4) 947 iwn_prph_write(sc, addr, *data); 948 } 949 950 static __inline uint32_t 951 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 952 { 953 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 954 IWN_BARRIER_READ_WRITE(sc); 955 return IWN_READ(sc, IWN_MEM_RDATA); 956 } 957 958 static __inline void 959 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 960 { 961 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 962 IWN_BARRIER_WRITE(sc); 963 IWN_WRITE(sc, IWN_MEM_WDATA, data); 964 } 965 966 #ifndef IEEE80211_NO_HT 967 static __inline void 968 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 969 { 970 uint32_t tmp; 971 972 tmp = iwn_mem_read(sc, addr & ~3); 973 if (addr & 3) 974 tmp = (tmp & 0x0000ffff) | data << 16; 975 else 976 tmp = (tmp & 0xffff0000) | data; 977 iwn_mem_write(sc, addr & ~3, tmp); 978 } 979 #endif 980 981 static __inline void 982 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 983 int count) 984 { 985 for (; count > 0; count--, addr += 4) 986 *data++ = iwn_mem_read(sc, addr); 987 } 988 989 static __inline void 990 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 991 int count) 992 { 993 for (; count > 0; count--, addr += 4) 994 iwn_mem_write(sc, addr, val); 995 } 996 997 static int 998 iwn_eeprom_lock(struct iwn_softc *sc) 999 { 1000 int i, ntries; 1001 1002 for (i = 0; i < 100; i++) { 1003 /* Request exclusive access to EEPROM. */ 1004 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1005 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1006 1007 /* Spin until we actually get the lock. */ 1008 for (ntries = 0; ntries < 100; ntries++) { 1009 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1010 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1011 return 0; 1012 DELAY(10); 1013 } 1014 } 1015 return ETIMEDOUT; 1016 } 1017 1018 static __inline void 1019 iwn_eeprom_unlock(struct iwn_softc *sc) 1020 { 1021 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1022 } 1023 1024 /* 1025 * Initialize access by host to One Time Programmable ROM. 1026 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1027 */ 1028 static int 1029 iwn_init_otprom(struct iwn_softc *sc) 1030 { 1031 uint16_t prev = 0, base, next; 1032 int count, error; 1033 1034 /* Wait for clock stabilization before accessing prph. */ 1035 if ((error = iwn_clock_wait(sc)) != 0) 1036 return error; 1037 1038 if ((error = iwn_nic_lock(sc)) != 0) 1039 return error; 1040 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1041 DELAY(5); 1042 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1043 iwn_nic_unlock(sc); 1044 1045 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1046 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1047 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1048 IWN_RESET_LINK_PWR_MGMT_DIS); 1049 } 1050 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1051 /* Clear ECC status. */ 1052 IWN_SETBITS(sc, IWN_OTP_GP, 1053 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1054 1055 /* 1056 * Find the block before last block (contains the EEPROM image) 1057 * for HW without OTP shadow RAM. 1058 */ 1059 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1060 /* Switch to absolute addressing mode. */ 1061 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1062 base = 0; 1063 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1064 error = iwn_read_prom_data(sc, base, &next, 2); 1065 if (error != 0) 1066 return error; 1067 if (next == 0) /* End of linked-list. */ 1068 break; 1069 prev = base; 1070 base = le16toh(next); 1071 } 1072 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1073 return EIO; 1074 /* Skip "next" word. */ 1075 sc->prom_base = prev + 1; 1076 } 1077 return 0; 1078 } 1079 1080 static int 1081 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1082 { 1083 uint8_t *out = data; 1084 uint32_t val, tmp; 1085 int ntries; 1086 1087 addr += sc->prom_base; 1088 for (; count > 0; count -= 2, addr++) { 1089 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1090 for (ntries = 0; ntries < 10; ntries++) { 1091 val = IWN_READ(sc, IWN_EEPROM); 1092 if (val & IWN_EEPROM_READ_VALID) 1093 break; 1094 DELAY(5); 1095 } 1096 if (ntries == 10) { 1097 aprint_error_dev(sc->sc_dev, 1098 "timeout reading ROM at 0x%x\n", addr); 1099 return ETIMEDOUT; 1100 } 1101 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1102 /* OTPROM, check for ECC errors. */ 1103 tmp = IWN_READ(sc, IWN_OTP_GP); 1104 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1105 aprint_error_dev(sc->sc_dev, 1106 "OTPROM ECC error at 0x%x\n", addr); 1107 return EIO; 1108 } 1109 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1110 /* Correctable ECC error, clear bit. */ 1111 IWN_SETBITS(sc, IWN_OTP_GP, 1112 IWN_OTP_GP_ECC_CORR_STTS); 1113 } 1114 } 1115 *out++ = val >> 16; 1116 if (count > 1) 1117 *out++ = val >> 24; 1118 } 1119 return 0; 1120 } 1121 1122 static int 1123 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1124 bus_size_t size, bus_size_t alignment) 1125 { 1126 int nsegs, error; 1127 1128 dma->tag = tag; 1129 dma->size = size; 1130 1131 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1132 &dma->map); 1133 if (error != 0) 1134 goto fail; 1135 1136 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1137 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1138 if (error != 0) 1139 goto fail; 1140 1141 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1142 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1143 if (error != 0) 1144 goto fail; 1145 1146 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1147 BUS_DMA_NOWAIT); 1148 if (error != 0) 1149 goto fail; 1150 1151 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1152 memset(dma->vaddr, 0, size); 1153 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1154 1155 dma->paddr = dma->map->dm_segs[0].ds_addr; 1156 if (kvap != NULL) 1157 *kvap = dma->vaddr; 1158 1159 return 0; 1160 1161 fail: iwn_dma_contig_free(dma); 1162 return error; 1163 } 1164 1165 static void 1166 iwn_dma_contig_free(struct iwn_dma_info *dma) 1167 { 1168 if (dma->map != NULL) { 1169 if (dma->vaddr != NULL) { 1170 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1172 bus_dmamap_unload(dma->tag, dma->map); 1173 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1174 bus_dmamem_free(dma->tag, &dma->seg, 1); 1175 dma->vaddr = NULL; 1176 } 1177 bus_dmamap_destroy(dma->tag, dma->map); 1178 dma->map = NULL; 1179 } 1180 } 1181 1182 static int 1183 iwn_alloc_sched(struct iwn_softc *sc) 1184 { 1185 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1186 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1187 (void **)&sc->sched, sc->schedsz, 1024); 1188 } 1189 1190 static void 1191 iwn_free_sched(struct iwn_softc *sc) 1192 { 1193 iwn_dma_contig_free(&sc->sched_dma); 1194 } 1195 1196 static int 1197 iwn_alloc_kw(struct iwn_softc *sc) 1198 { 1199 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1200 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1201 4096); 1202 } 1203 1204 static void 1205 iwn_free_kw(struct iwn_softc *sc) 1206 { 1207 iwn_dma_contig_free(&sc->kw_dma); 1208 } 1209 1210 static int 1211 iwn_alloc_ict(struct iwn_softc *sc) 1212 { 1213 /* ICT table must be aligned on a 4KB boundary. */ 1214 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1215 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1216 } 1217 1218 static void 1219 iwn_free_ict(struct iwn_softc *sc) 1220 { 1221 iwn_dma_contig_free(&sc->ict_dma); 1222 } 1223 1224 static int 1225 iwn_alloc_fwmem(struct iwn_softc *sc) 1226 { 1227 /* Must be aligned on a 16-byte boundary. */ 1228 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1229 sc->fwsz, 16); 1230 } 1231 1232 static void 1233 iwn_free_fwmem(struct iwn_softc *sc) 1234 { 1235 iwn_dma_contig_free(&sc->fw_dma); 1236 } 1237 1238 static int 1239 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1240 { 1241 bus_size_t size; 1242 int i, error; 1243 1244 ring->cur = 0; 1245 1246 /* Allocate RX descriptors (256-byte aligned). */ 1247 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1248 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1249 (void **)&ring->desc, size, 256); 1250 if (error != 0) { 1251 aprint_error_dev(sc->sc_dev, 1252 "could not allocate RX ring DMA memory\n"); 1253 goto fail; 1254 } 1255 1256 /* Allocate RX status area (16-byte aligned). */ 1257 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1258 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1259 if (error != 0) { 1260 aprint_error_dev(sc->sc_dev, 1261 "could not allocate RX status DMA memory\n"); 1262 goto fail; 1263 } 1264 1265 /* 1266 * Allocate and map RX buffers. 1267 */ 1268 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1269 struct iwn_rx_data *data = &ring->data[i]; 1270 1271 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1272 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1273 &data->map); 1274 if (error != 0) { 1275 aprint_error_dev(sc->sc_dev, 1276 "could not create RX buf DMA map\n"); 1277 goto fail; 1278 } 1279 1280 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1281 if (data->m == NULL) { 1282 aprint_error_dev(sc->sc_dev, 1283 "could not allocate RX mbuf\n"); 1284 error = ENOBUFS; 1285 goto fail; 1286 } 1287 1288 error = bus_dmamap_load(sc->sc_dmat, data->map, 1289 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1290 BUS_DMA_NOWAIT | BUS_DMA_READ); 1291 if (error != 0) { 1292 aprint_error_dev(sc->sc_dev, 1293 "can't not map mbuf (error %d)\n", error); 1294 goto fail; 1295 } 1296 1297 /* Set physical address of RX buffer (256-byte aligned). */ 1298 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1299 } 1300 1301 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1302 BUS_DMASYNC_PREWRITE); 1303 1304 return 0; 1305 1306 fail: iwn_free_rx_ring(sc, ring); 1307 return error; 1308 } 1309 1310 static void 1311 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1312 { 1313 int ntries; 1314 1315 if (iwn_nic_lock(sc) == 0) { 1316 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1317 for (ntries = 0; ntries < 1000; ntries++) { 1318 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1319 IWN_FH_RX_STATUS_IDLE) 1320 break; 1321 DELAY(10); 1322 } 1323 iwn_nic_unlock(sc); 1324 } 1325 ring->cur = 0; 1326 sc->last_rx_valid = 0; 1327 } 1328 1329 static void 1330 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1331 { 1332 int i; 1333 1334 iwn_dma_contig_free(&ring->desc_dma); 1335 iwn_dma_contig_free(&ring->stat_dma); 1336 1337 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1338 struct iwn_rx_data *data = &ring->data[i]; 1339 1340 if (data->m != NULL) { 1341 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1342 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1343 bus_dmamap_unload(sc->sc_dmat, data->map); 1344 m_freem(data->m); 1345 } 1346 if (data->map != NULL) 1347 bus_dmamap_destroy(sc->sc_dmat, data->map); 1348 } 1349 } 1350 1351 static int 1352 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1353 { 1354 bus_addr_t paddr; 1355 bus_size_t size; 1356 int i, error; 1357 1358 ring->qid = qid; 1359 ring->queued = 0; 1360 ring->cur = 0; 1361 1362 /* Allocate TX descriptors (256-byte aligned). */ 1363 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1364 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1365 (void **)&ring->desc, size, 256); 1366 if (error != 0) { 1367 aprint_error_dev(sc->sc_dev, 1368 "could not allocate TX ring DMA memory\n"); 1369 goto fail; 1370 } 1371 /* 1372 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1373 * to allocate commands space for other rings. 1374 * XXX Do we really need to allocate descriptors for other rings? 1375 */ 1376 if (qid > 4) 1377 return 0; 1378 1379 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1380 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1381 (void **)&ring->cmd, size, 4); 1382 if (error != 0) { 1383 aprint_error_dev(sc->sc_dev, 1384 "could not allocate TX cmd DMA memory\n"); 1385 goto fail; 1386 } 1387 1388 paddr = ring->cmd_dma.paddr; 1389 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1390 struct iwn_tx_data *data = &ring->data[i]; 1391 1392 data->cmd_paddr = paddr; 1393 data->scratch_paddr = paddr + 12; 1394 paddr += sizeof (struct iwn_tx_cmd); 1395 1396 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1397 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1398 &data->map); 1399 if (error != 0) { 1400 aprint_error_dev(sc->sc_dev, 1401 "could not create TX buf DMA map\n"); 1402 goto fail; 1403 } 1404 } 1405 return 0; 1406 1407 fail: iwn_free_tx_ring(sc, ring); 1408 return error; 1409 } 1410 1411 static void 1412 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1413 { 1414 int i; 1415 1416 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1417 struct iwn_tx_data *data = &ring->data[i]; 1418 1419 if (data->m != NULL) { 1420 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1421 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1422 bus_dmamap_unload(sc->sc_dmat, data->map); 1423 m_freem(data->m); 1424 data->m = NULL; 1425 } 1426 } 1427 /* Clear TX descriptors. */ 1428 memset(ring->desc, 0, ring->desc_dma.size); 1429 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1430 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1431 sc->qfullmsk &= ~(1 << ring->qid); 1432 ring->queued = 0; 1433 ring->cur = 0; 1434 } 1435 1436 static void 1437 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1438 { 1439 int i; 1440 1441 iwn_dma_contig_free(&ring->desc_dma); 1442 iwn_dma_contig_free(&ring->cmd_dma); 1443 1444 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1445 struct iwn_tx_data *data = &ring->data[i]; 1446 1447 if (data->m != NULL) { 1448 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1449 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1450 bus_dmamap_unload(sc->sc_dmat, data->map); 1451 m_freem(data->m); 1452 } 1453 if (data->map != NULL) 1454 bus_dmamap_destroy(sc->sc_dmat, data->map); 1455 } 1456 } 1457 1458 static void 1459 iwn5000_ict_reset(struct iwn_softc *sc) 1460 { 1461 /* Disable interrupts. */ 1462 IWN_WRITE(sc, IWN_INT_MASK, 0); 1463 1464 /* Reset ICT table. */ 1465 memset(sc->ict, 0, IWN_ICT_SIZE); 1466 sc->ict_cur = 0; 1467 1468 /* Set physical address of ICT table (4KB aligned). */ 1469 DPRINTF(("enabling ICT\n")); 1470 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1471 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1472 1473 /* Enable periodic RX interrupt. */ 1474 sc->int_mask |= IWN_INT_RX_PERIODIC; 1475 /* Switch to ICT interrupt mode in driver. */ 1476 sc->sc_flags |= IWN_FLAG_USE_ICT; 1477 1478 /* Re-enable interrupts. */ 1479 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1480 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1481 } 1482 1483 static int 1484 iwn_read_eeprom(struct iwn_softc *sc) 1485 { 1486 struct iwn_ops *ops = &sc->ops; 1487 struct ieee80211com *ic = &sc->sc_ic; 1488 uint16_t val; 1489 int error; 1490 1491 /* Check whether adapter has an EEPROM or an OTPROM. */ 1492 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1493 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1494 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1495 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1496 "OTPROM" : "EEPROM")); 1497 1498 /* Adapter has to be powered on for EEPROM access to work. */ 1499 if ((error = iwn_apm_init(sc)) != 0) { 1500 aprint_error_dev(sc->sc_dev, 1501 "could not power ON adapter\n"); 1502 return error; 1503 } 1504 1505 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1506 aprint_error_dev(sc->sc_dev, 1507 "bad ROM signature\n"); 1508 return EIO; 1509 } 1510 if ((error = iwn_eeprom_lock(sc)) != 0) { 1511 aprint_error_dev(sc->sc_dev, 1512 "could not lock ROM (error=%d)\n", error); 1513 return error; 1514 } 1515 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1516 if ((error = iwn_init_otprom(sc)) != 0) { 1517 aprint_error_dev(sc->sc_dev, 1518 "could not initialize OTPROM\n"); 1519 return error; 1520 } 1521 } 1522 1523 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1524 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1525 /* Check if HT support is bonded out. */ 1526 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1527 sc->sc_flags |= IWN_FLAG_HAS_11N; 1528 1529 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1530 sc->rfcfg = le16toh(val); 1531 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1532 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1533 if (sc->txchainmask == 0) 1534 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1535 if (sc->rxchainmask == 0) 1536 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1537 1538 /* Read MAC address. */ 1539 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1540 1541 /* Read adapter-specific information from EEPROM. */ 1542 ops->read_eeprom(sc); 1543 1544 iwn_apm_stop(sc); /* Power OFF adapter. */ 1545 1546 iwn_eeprom_unlock(sc); 1547 return 0; 1548 } 1549 1550 static void 1551 iwn4965_read_eeprom(struct iwn_softc *sc) 1552 { 1553 uint32_t addr; 1554 uint16_t val; 1555 int i; 1556 1557 /* Read regulatory domain (4 ASCII characters). */ 1558 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1559 1560 /* Read the list of authorized channels (20MHz ones only). */ 1561 for (i = 0; i < 5; i++) { 1562 addr = iwn4965_regulatory_bands[i]; 1563 iwn_read_eeprom_channels(sc, i, addr); 1564 } 1565 1566 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1567 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1568 sc->maxpwr2GHz = val & 0xff; 1569 sc->maxpwr5GHz = val >> 8; 1570 /* Check that EEPROM values are within valid range. */ 1571 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1572 sc->maxpwr5GHz = 38; 1573 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1574 sc->maxpwr2GHz = 38; 1575 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1576 1577 /* Read samples for each TX power group. */ 1578 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1579 sizeof sc->bands); 1580 1581 /* Read voltage at which samples were taken. */ 1582 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1583 sc->eeprom_voltage = (int16_t)le16toh(val); 1584 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1585 1586 #ifdef IWN_DEBUG 1587 /* Print samples. */ 1588 if (iwn_debug > 0) { 1589 for (i = 0; i < IWN_NBANDS; i++) 1590 iwn4965_print_power_group(sc, i); 1591 } 1592 #endif 1593 } 1594 1595 #ifdef IWN_DEBUG 1596 static void 1597 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1598 { 1599 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1600 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1601 int j, c; 1602 1603 aprint_normal("===band %d===\n", i); 1604 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1605 aprint_normal("chan1 num=%d\n", chans[0].num); 1606 for (c = 0; c < 2; c++) { 1607 for (j = 0; j < IWN_NSAMPLES; j++) { 1608 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1609 "power=%d pa_det=%d\n", c, j, 1610 chans[0].samples[c][j].temp, 1611 chans[0].samples[c][j].gain, 1612 chans[0].samples[c][j].power, 1613 chans[0].samples[c][j].pa_det); 1614 } 1615 } 1616 aprint_normal("chan2 num=%d\n", chans[1].num); 1617 for (c = 0; c < 2; c++) { 1618 for (j = 0; j < IWN_NSAMPLES; j++) { 1619 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1620 "power=%d pa_det=%d\n", c, j, 1621 chans[1].samples[c][j].temp, 1622 chans[1].samples[c][j].gain, 1623 chans[1].samples[c][j].power, 1624 chans[1].samples[c][j].pa_det); 1625 } 1626 } 1627 } 1628 #endif 1629 1630 static void 1631 iwn5000_read_eeprom(struct iwn_softc *sc) 1632 { 1633 struct iwn5000_eeprom_calib_hdr hdr; 1634 int32_t volt; 1635 uint32_t base, addr; 1636 uint16_t val; 1637 int i; 1638 1639 /* Read regulatory domain (4 ASCII characters). */ 1640 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1641 base = le16toh(val); 1642 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1643 sc->eeprom_domain, 4); 1644 1645 /* Read the list of authorized channels (20MHz ones only). */ 1646 for (i = 0; i < 5; i++) { 1647 addr = base + iwn5000_regulatory_bands[i]; 1648 iwn_read_eeprom_channels(sc, i, addr); 1649 } 1650 1651 /* Read enhanced TX power information for 6000 Series. */ 1652 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1653 iwn_read_eeprom_enhinfo(sc); 1654 1655 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1656 base = le16toh(val); 1657 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1658 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1659 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1660 sc->calib_ver = hdr.version; 1661 1662 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1663 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1664 sc->hw_type == IWN_HW_REV_TYPE_135 || 1665 sc->hw_type == IWN_HW_REV_TYPE_105) { 1666 sc->eeprom_voltage = le16toh(hdr.volt); 1667 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1668 sc->eeprom_temp = le16toh(val); 1669 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1670 sc->eeprom_rawtemp = le16toh(val); 1671 } 1672 1673 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1674 /* Compute temperature offset. */ 1675 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1676 sc->eeprom_temp = le16toh(val); 1677 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1678 volt = le16toh(val); 1679 sc->temp_off = sc->eeprom_temp - (volt / -5); 1680 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1681 sc->eeprom_temp, volt, sc->temp_off)); 1682 } else { 1683 /* Read crystal calibration. */ 1684 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1685 &sc->eeprom_crystal, sizeof (uint32_t)); 1686 DPRINTF(("crystal calibration 0x%08x\n", 1687 le32toh(sc->eeprom_crystal))); 1688 } 1689 } 1690 1691 static void 1692 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1693 { 1694 struct ieee80211com *ic = &sc->sc_ic; 1695 const struct iwn_chan_band *band = &iwn_bands[n]; 1696 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1697 uint8_t chan; 1698 int i; 1699 1700 iwn_read_prom_data(sc, addr, channels, 1701 band->nchan * sizeof (struct iwn_eeprom_chan)); 1702 1703 for (i = 0; i < band->nchan; i++) { 1704 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1705 continue; 1706 1707 chan = band->chan[i]; 1708 1709 if (n == 0) { /* 2GHz band */ 1710 ic->ic_channels[chan].ic_freq = 1711 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1712 ic->ic_channels[chan].ic_flags = 1713 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1714 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1715 1716 } else { /* 5GHz band */ 1717 /* 1718 * Some adapters support channels 7, 8, 11 and 12 1719 * both in the 2GHz and 4.9GHz bands. 1720 * Because of limitations in our net80211 layer, 1721 * we don't support them in the 4.9GHz band. 1722 */ 1723 if (chan <= 14) 1724 continue; 1725 1726 ic->ic_channels[chan].ic_freq = 1727 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1728 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1729 /* We have at least one valid 5GHz channel. */ 1730 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1731 } 1732 1733 /* Is active scan allowed on this channel? */ 1734 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1735 ic->ic_channels[chan].ic_flags |= 1736 IEEE80211_CHAN_PASSIVE; 1737 } 1738 1739 /* Save maximum allowed TX power for this channel. */ 1740 sc->maxpwr[chan] = channels[i].maxpwr; 1741 1742 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1743 chan, channels[i].flags, sc->maxpwr[chan])); 1744 } 1745 } 1746 1747 static void 1748 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1749 { 1750 struct iwn_eeprom_enhinfo enhinfo[35]; 1751 uint16_t val, base; 1752 int8_t maxpwr; 1753 int i; 1754 1755 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1756 base = le16toh(val); 1757 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1758 enhinfo, sizeof enhinfo); 1759 1760 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1761 for (i = 0; i < __arraycount(enhinfo); i++) { 1762 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1763 continue; /* Skip invalid entries. */ 1764 1765 maxpwr = 0; 1766 if (sc->txchainmask & IWN_ANT_A) 1767 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1768 if (sc->txchainmask & IWN_ANT_B) 1769 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1770 if (sc->txchainmask & IWN_ANT_C) 1771 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1772 if (sc->ntxchains == 2) 1773 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1774 else if (sc->ntxchains == 3) 1775 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1776 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1777 1778 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1779 sc->enh_maxpwr[i] = maxpwr; 1780 } 1781 } 1782 1783 static struct ieee80211_node * 1784 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1785 { 1786 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1787 } 1788 1789 static void 1790 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1791 { 1792 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1793 struct iwn_node *wn = (void *)ni; 1794 uint8_t rate; 1795 int ridx, i; 1796 1797 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1798 /* Start at lowest available bit-rate, AMRR will raise. */ 1799 ni->ni_txrate = 0; 1800 1801 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1802 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1803 /* Map 802.11 rate to HW rate index. */ 1804 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1805 if (iwn_rates[ridx].rate == rate) 1806 break; 1807 wn->ridx[i] = ridx; 1808 } 1809 } 1810 1811 static int 1812 iwn_media_change(struct ifnet *ifp) 1813 { 1814 struct iwn_softc *sc = ifp->if_softc; 1815 struct ieee80211com *ic = &sc->sc_ic; 1816 uint8_t rate, ridx; 1817 int error; 1818 1819 error = ieee80211_media_change(ifp); 1820 if (error != ENETRESET) 1821 return error; 1822 1823 if (ic->ic_fixed_rate != -1) { 1824 rate = ic->ic_sup_rates[ic->ic_curmode]. 1825 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1826 /* Map 802.11 rate to HW rate index. */ 1827 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1828 if (iwn_rates[ridx].rate == rate) 1829 break; 1830 sc->fixed_ridx = ridx; 1831 } 1832 1833 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1834 (IFF_UP | IFF_RUNNING)) { 1835 iwn_stop(ifp, 0); 1836 error = iwn_init(ifp); 1837 } 1838 return error; 1839 } 1840 1841 static int 1842 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1843 { 1844 struct ifnet *ifp = ic->ic_ifp; 1845 struct iwn_softc *sc = ifp->if_softc; 1846 int error; 1847 1848 callout_stop(&sc->calib_to); 1849 1850 switch (nstate) { 1851 case IEEE80211_S_SCAN: 1852 /* XXX Do not abort a running scan. */ 1853 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1854 if (ic->ic_state != nstate) 1855 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1856 "while scanning(%d) ignored\n", nstate, 1857 ic->ic_state); 1858 break; 1859 } 1860 1861 /* XXX Not sure if call and flags are needed. */ 1862 ieee80211_node_table_reset(&ic->ic_scan); 1863 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1864 sc->sc_flags |= IWN_FLAG_SCANNING_2GHZ; 1865 1866 /* Make the link LED blink while we're scanning. */ 1867 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1868 1869 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1870 aprint_error_dev(sc->sc_dev, 1871 "could not initiate scan\n"); 1872 return error; 1873 } 1874 ic->ic_state = nstate; 1875 return 0; 1876 1877 case IEEE80211_S_ASSOC: 1878 if (ic->ic_state != IEEE80211_S_RUN) 1879 break; 1880 /* FALLTHROUGH */ 1881 case IEEE80211_S_AUTH: 1882 /* Reset state to handle reassociations correctly. */ 1883 sc->rxon.associd = 0; 1884 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1885 sc->calib.state = IWN_CALIB_STATE_INIT; 1886 1887 if ((error = iwn_auth(sc)) != 0) { 1888 aprint_error_dev(sc->sc_dev, 1889 "could not move to auth state\n"); 1890 return error; 1891 } 1892 break; 1893 1894 case IEEE80211_S_RUN: 1895 if ((error = iwn_run(sc)) != 0) { 1896 aprint_error_dev(sc->sc_dev, 1897 "could not move to run state\n"); 1898 return error; 1899 } 1900 break; 1901 1902 case IEEE80211_S_INIT: 1903 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1904 sc->calib.state = IWN_CALIB_STATE_INIT; 1905 break; 1906 } 1907 1908 return sc->sc_newstate(ic, nstate, arg); 1909 } 1910 1911 static void 1912 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1913 { 1914 struct iwn_softc *sc = arg; 1915 struct iwn_node *wn = (struct iwn_node *)ni; 1916 1917 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1918 } 1919 1920 static void 1921 iwn_calib_timeout(void *arg) 1922 { 1923 struct iwn_softc *sc = arg; 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 int s; 1926 1927 s = splnet(); 1928 if (ic->ic_fixed_rate == -1) { 1929 if (ic->ic_opmode == IEEE80211_M_STA) 1930 iwn_iter_func(sc, ic->ic_bss); 1931 else 1932 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1933 } 1934 /* Force automatic TX power calibration every 60 secs. */ 1935 if (++sc->calib_cnt >= 120) { 1936 uint32_t flags = 0; 1937 1938 DPRINTF(("sending request for statistics\n")); 1939 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1940 sizeof flags, 1); 1941 sc->calib_cnt = 0; 1942 } 1943 splx(s); 1944 1945 /* Automatic rate control triggered every 500ms. */ 1946 callout_schedule(&sc->calib_to, hz/2); 1947 } 1948 1949 /* 1950 * Process an RX_PHY firmware notification. This is usually immediately 1951 * followed by an MPDU_RX_DONE notification. 1952 */ 1953 static void 1954 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1955 struct iwn_rx_data *data) 1956 { 1957 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1958 1959 DPRINTFN(2, ("received PHY stats\n")); 1960 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1961 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1962 1963 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1964 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1965 sc->last_rx_valid = 1; 1966 } 1967 1968 /* 1969 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1970 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1971 */ 1972 static void 1973 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1974 struct iwn_rx_data *data) 1975 { 1976 struct iwn_ops *ops = &sc->ops; 1977 struct ieee80211com *ic = &sc->sc_ic; 1978 struct ifnet *ifp = ic->ic_ifp; 1979 struct iwn_rx_ring *ring = &sc->rxq; 1980 struct ieee80211_frame *wh; 1981 struct ieee80211_node *ni; 1982 struct mbuf *m, *m1; 1983 struct iwn_rx_stat *stat; 1984 char *head; 1985 uint32_t flags; 1986 int error, len, rssi; 1987 1988 if (desc->type == IWN_MPDU_RX_DONE) { 1989 /* Check for prior RX_PHY notification. */ 1990 if (!sc->last_rx_valid) { 1991 DPRINTF(("missing RX_PHY\n")); 1992 return; 1993 } 1994 sc->last_rx_valid = 0; 1995 stat = &sc->last_rx_stat; 1996 } else 1997 stat = (struct iwn_rx_stat *)(desc + 1); 1998 1999 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2000 BUS_DMASYNC_POSTREAD); 2001 2002 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2003 aprint_error_dev(sc->sc_dev, 2004 "invalid RX statistic header\n"); 2005 return; 2006 } 2007 if (desc->type == IWN_MPDU_RX_DONE) { 2008 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2009 head = (char *)(mpdu + 1); 2010 len = le16toh(mpdu->len); 2011 } else { 2012 head = (char *)(stat + 1) + stat->cfg_phy_len; 2013 len = le16toh(stat->len); 2014 } 2015 2016 flags = le32toh(*(uint32_t *)(head + len)); 2017 2018 /* Discard frames with a bad FCS early. */ 2019 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2020 DPRINTFN(2, ("RX flags error %x\n", flags)); 2021 ifp->if_ierrors++; 2022 return; 2023 } 2024 /* Discard frames that are too short. */ 2025 if (len < sizeof (*wh)) { 2026 DPRINTF(("frame too short: %d\n", len)); 2027 ic->ic_stats.is_rx_tooshort++; 2028 ifp->if_ierrors++; 2029 return; 2030 } 2031 2032 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2033 if (m1 == NULL) { 2034 ic->ic_stats.is_rx_nobuf++; 2035 ifp->if_ierrors++; 2036 return; 2037 } 2038 bus_dmamap_unload(sc->sc_dmat, data->map); 2039 2040 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2041 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2042 if (error != 0) { 2043 m_freem(m1); 2044 2045 /* Try to reload the old mbuf. */ 2046 error = bus_dmamap_load(sc->sc_dmat, data->map, 2047 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2048 BUS_DMA_NOWAIT | BUS_DMA_READ); 2049 if (error != 0) { 2050 panic("%s: could not load old RX mbuf", 2051 device_xname(sc->sc_dev)); 2052 } 2053 /* Physical address may have changed. */ 2054 ring->desc[ring->cur] = 2055 htole32(data->map->dm_segs[0].ds_addr >> 8); 2056 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2057 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2058 BUS_DMASYNC_PREWRITE); 2059 ifp->if_ierrors++; 2060 return; 2061 } 2062 2063 m = data->m; 2064 data->m = m1; 2065 /* Update RX descriptor. */ 2066 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2067 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2068 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2069 BUS_DMASYNC_PREWRITE); 2070 2071 /* Finalize mbuf. */ 2072 m->m_pkthdr.rcvif = ifp; 2073 m->m_data = head; 2074 m->m_pkthdr.len = m->m_len = len; 2075 2076 /* Grab a reference to the source node. */ 2077 wh = mtod(m, struct ieee80211_frame *); 2078 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2079 2080 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2081 /* NetBSD does decryption in ieee80211_input. */ 2082 2083 rssi = ops->get_rssi(stat); 2084 2085 /* XXX Added for NetBSD: scans never stop without it */ 2086 if (ic->ic_state == IEEE80211_S_SCAN) 2087 iwn_fix_channel(ic, m, stat); 2088 2089 if (sc->sc_drvbpf != NULL) { 2090 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2091 2092 tap->wr_flags = 0; 2093 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2094 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2095 tap->wr_chan_freq = 2096 htole16(ic->ic_channels[stat->chan].ic_freq); 2097 tap->wr_chan_flags = 2098 htole16(ic->ic_channels[stat->chan].ic_flags); 2099 tap->wr_dbm_antsignal = (int8_t)rssi; 2100 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2101 tap->wr_tsft = stat->tstamp; 2102 switch (stat->rate) { 2103 /* CCK rates. */ 2104 case 10: tap->wr_rate = 2; break; 2105 case 20: tap->wr_rate = 4; break; 2106 case 55: tap->wr_rate = 11; break; 2107 case 110: tap->wr_rate = 22; break; 2108 /* OFDM rates. */ 2109 case 0xd: tap->wr_rate = 12; break; 2110 case 0xf: tap->wr_rate = 18; break; 2111 case 0x5: tap->wr_rate = 24; break; 2112 case 0x7: tap->wr_rate = 36; break; 2113 case 0x9: tap->wr_rate = 48; break; 2114 case 0xb: tap->wr_rate = 72; break; 2115 case 0x1: tap->wr_rate = 96; break; 2116 case 0x3: tap->wr_rate = 108; break; 2117 /* Unknown rate: should not happen. */ 2118 default: tap->wr_rate = 0; 2119 } 2120 2121 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2122 } 2123 2124 /* Send the frame to the 802.11 layer. */ 2125 ieee80211_input(ic, m, ni, rssi, 0); 2126 2127 /* Node is no longer needed. */ 2128 ieee80211_free_node(ni); 2129 } 2130 2131 #ifndef IEEE80211_NO_HT 2132 /* Process an incoming Compressed BlockAck. */ 2133 static void 2134 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2135 struct iwn_rx_data *data) 2136 { 2137 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2138 struct iwn_tx_ring *txq; 2139 2140 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2141 BUS_DMASYNC_POSTREAD); 2142 2143 txq = &sc->txq[le16toh(ba->qid)]; 2144 /* XXX TBD */ 2145 } 2146 #endif 2147 2148 /* 2149 * Process a CALIBRATION_RESULT notification sent by the initialization 2150 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2151 */ 2152 static void 2153 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2154 struct iwn_rx_data *data) 2155 { 2156 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2157 int len, idx = -1; 2158 2159 /* Runtime firmware should not send such a notification. */ 2160 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2161 return; 2162 2163 len = (le32toh(desc->len) & 0x3fff) - 4; 2164 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2165 BUS_DMASYNC_POSTREAD); 2166 2167 switch (calib->code) { 2168 case IWN5000_PHY_CALIB_DC: 2169 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2170 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2171 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2172 sc->hw_type == IWN_HW_REV_TYPE_135 || 2173 sc->hw_type == IWN_HW_REV_TYPE_105) 2174 idx = 0; 2175 break; 2176 case IWN5000_PHY_CALIB_LO: 2177 idx = 1; 2178 break; 2179 case IWN5000_PHY_CALIB_TX_IQ: 2180 idx = 2; 2181 break; 2182 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2183 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2184 sc->hw_type != IWN_HW_REV_TYPE_5150) 2185 idx = 3; 2186 break; 2187 case IWN5000_PHY_CALIB_BASE_BAND: 2188 idx = 4; 2189 break; 2190 } 2191 if (idx == -1) /* Ignore other results. */ 2192 return; 2193 2194 /* Save calibration result. */ 2195 if (sc->calibcmd[idx].buf != NULL) 2196 free(sc->calibcmd[idx].buf, M_DEVBUF); 2197 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2198 if (sc->calibcmd[idx].buf == NULL) { 2199 DPRINTF(("not enough memory for calibration result %d\n", 2200 calib->code)); 2201 return; 2202 } 2203 DPRINTF(("saving calibration result code=%d len=%d\n", 2204 calib->code, len)); 2205 sc->calibcmd[idx].len = len; 2206 memcpy(sc->calibcmd[idx].buf, calib, len); 2207 } 2208 2209 /* 2210 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2211 * The latter is sent by the firmware after each received beacon. 2212 */ 2213 static void 2214 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2215 struct iwn_rx_data *data) 2216 { 2217 struct iwn_ops *ops = &sc->ops; 2218 struct ieee80211com *ic = &sc->sc_ic; 2219 struct iwn_calib_state *calib = &sc->calib; 2220 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2221 int temp; 2222 2223 /* Ignore statistics received during a scan. */ 2224 if (ic->ic_state != IEEE80211_S_RUN) 2225 return; 2226 2227 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2228 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2229 2230 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2231 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2232 2233 /* Test if temperature has changed. */ 2234 if (stats->general.temp != sc->rawtemp) { 2235 /* Convert "raw" temperature to degC. */ 2236 sc->rawtemp = stats->general.temp; 2237 temp = ops->get_temperature(sc); 2238 DPRINTFN(2, ("temperature=%dC\n", temp)); 2239 2240 /* Update TX power if need be (4965AGN only). */ 2241 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2242 iwn4965_power_calibration(sc, temp); 2243 } 2244 2245 if (desc->type != IWN_BEACON_STATISTICS) 2246 return; /* Reply to a statistics request. */ 2247 2248 sc->noise = iwn_get_noise(&stats->rx.general); 2249 2250 /* Test that RSSI and noise are present in stats report. */ 2251 if (le32toh(stats->rx.general.flags) != 1) { 2252 DPRINTF(("received statistics without RSSI\n")); 2253 return; 2254 } 2255 2256 /* 2257 * XXX Differential gain calibration makes the 6005 firmware 2258 * crap out, so skip it for now. This effectively disables 2259 * sensitivity tuning as well. 2260 */ 2261 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2262 return; 2263 2264 if (calib->state == IWN_CALIB_STATE_ASSOC) 2265 iwn_collect_noise(sc, &stats->rx.general); 2266 else if (calib->state == IWN_CALIB_STATE_RUN) 2267 iwn_tune_sensitivity(sc, &stats->rx); 2268 } 2269 2270 /* 2271 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2272 * and 5000 adapters have different incompatible TX status formats. 2273 */ 2274 static void 2275 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2276 struct iwn_rx_data *data) 2277 { 2278 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2279 2280 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2281 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2282 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2283 } 2284 2285 static void 2286 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2287 struct iwn_rx_data *data) 2288 { 2289 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2290 2291 #ifdef notyet 2292 /* Reset TX scheduler slot. */ 2293 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2294 #endif 2295 2296 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2297 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2298 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2299 } 2300 2301 /* 2302 * Adapter-independent backend for TX_DONE firmware notifications. 2303 */ 2304 static void 2305 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2306 uint8_t status) 2307 { 2308 struct ieee80211com *ic = &sc->sc_ic; 2309 struct ifnet *ifp = ic->ic_ifp; 2310 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2311 struct iwn_tx_data *data = &ring->data[desc->idx]; 2312 struct iwn_node *wn = (struct iwn_node *)data->ni; 2313 2314 /* Update rate control statistics. */ 2315 wn->amn.amn_txcnt++; 2316 if (ackfailcnt > 0) 2317 wn->amn.amn_retrycnt++; 2318 2319 if (status != 1 && status != 2) 2320 ifp->if_oerrors++; 2321 else 2322 ifp->if_opackets++; 2323 2324 /* Unmap and free mbuf. */ 2325 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2326 BUS_DMASYNC_POSTWRITE); 2327 bus_dmamap_unload(sc->sc_dmat, data->map); 2328 m_freem(data->m); 2329 data->m = NULL; 2330 ieee80211_free_node(data->ni); 2331 data->ni = NULL; 2332 2333 sc->sc_tx_timer = 0; 2334 if (--ring->queued < IWN_TX_RING_LOMARK) { 2335 sc->qfullmsk &= ~(1 << ring->qid); 2336 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2337 ifp->if_flags &= ~IFF_OACTIVE; 2338 (*ifp->if_start)(ifp); 2339 } 2340 } 2341 } 2342 2343 /* 2344 * Process a "command done" firmware notification. This is where we wakeup 2345 * processes waiting for a synchronous command completion. 2346 */ 2347 static void 2348 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2349 { 2350 struct iwn_tx_ring *ring = &sc->txq[4]; 2351 struct iwn_tx_data *data; 2352 2353 if ((desc->qid & 0xf) != 4) 2354 return; /* Not a command ack. */ 2355 2356 data = &ring->data[desc->idx]; 2357 2358 /* If the command was mapped in an mbuf, free it. */ 2359 if (data->m != NULL) { 2360 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2361 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2362 bus_dmamap_unload(sc->sc_dmat, data->map); 2363 m_freem(data->m); 2364 data->m = NULL; 2365 } 2366 wakeup(&ring->desc[desc->idx]); 2367 } 2368 2369 /* 2370 * Process an INT_FH_RX or INT_SW_RX interrupt. 2371 */ 2372 static void 2373 iwn_notif_intr(struct iwn_softc *sc) 2374 { 2375 struct iwn_ops *ops = &sc->ops; 2376 struct ieee80211com *ic = &sc->sc_ic; 2377 struct ifnet *ifp = ic->ic_ifp; 2378 uint16_t hw; 2379 2380 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2381 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2382 2383 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2384 while (sc->rxq.cur != hw) { 2385 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2386 struct iwn_rx_desc *desc; 2387 2388 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2389 BUS_DMASYNC_POSTREAD); 2390 desc = mtod(data->m, struct iwn_rx_desc *); 2391 2392 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2393 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2394 2395 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2396 iwn_cmd_done(sc, desc); 2397 2398 switch (desc->type) { 2399 case IWN_RX_PHY: 2400 iwn_rx_phy(sc, desc, data); 2401 break; 2402 2403 case IWN_RX_DONE: /* 4965AGN only. */ 2404 case IWN_MPDU_RX_DONE: 2405 /* An 802.11 frame has been received. */ 2406 iwn_rx_done(sc, desc, data); 2407 break; 2408 #ifndef IEEE80211_NO_HT 2409 case IWN_RX_COMPRESSED_BA: 2410 /* A Compressed BlockAck has been received. */ 2411 iwn_rx_compressed_ba(sc, desc, data); 2412 break; 2413 #endif 2414 case IWN_TX_DONE: 2415 /* An 802.11 frame has been transmitted. */ 2416 ops->tx_done(sc, desc, data); 2417 break; 2418 2419 case IWN_RX_STATISTICS: 2420 case IWN_BEACON_STATISTICS: 2421 iwn_rx_statistics(sc, desc, data); 2422 break; 2423 2424 case IWN_BEACON_MISSED: 2425 { 2426 struct iwn_beacon_missed *miss = 2427 (struct iwn_beacon_missed *)(desc + 1); 2428 2429 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2430 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2431 /* 2432 * If more than 5 consecutive beacons are missed, 2433 * reinitialize the sensitivity state machine. 2434 */ 2435 DPRINTF(("beacons missed %d/%d\n", 2436 le32toh(miss->consecutive), le32toh(miss->total))); 2437 if (ic->ic_state == IEEE80211_S_RUN && 2438 le32toh(miss->consecutive) > 5) 2439 (void)iwn_init_sensitivity(sc); 2440 break; 2441 } 2442 case IWN_UC_READY: 2443 { 2444 struct iwn_ucode_info *uc = 2445 (struct iwn_ucode_info *)(desc + 1); 2446 2447 /* The microcontroller is ready. */ 2448 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2449 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2450 DPRINTF(("microcode alive notification version=%d.%d " 2451 "subtype=%x alive=%x\n", uc->major, uc->minor, 2452 uc->subtype, le32toh(uc->valid))); 2453 2454 if (le32toh(uc->valid) != 1) { 2455 aprint_error_dev(sc->sc_dev, 2456 "microcontroller initialization " 2457 "failed\n"); 2458 break; 2459 } 2460 if (uc->subtype == IWN_UCODE_INIT) { 2461 /* Save microcontroller report. */ 2462 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2463 } 2464 /* Save the address of the error log in SRAM. */ 2465 sc->errptr = le32toh(uc->errptr); 2466 break; 2467 } 2468 case IWN_STATE_CHANGED: 2469 { 2470 uint32_t *status = (uint32_t *)(desc + 1); 2471 2472 /* Enabled/disabled notification. */ 2473 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2474 sizeof (*status), BUS_DMASYNC_POSTREAD); 2475 DPRINTF(("state changed to %x\n", le32toh(*status))); 2476 2477 if (le32toh(*status) & 1) { 2478 /* The radio button has to be pushed. */ 2479 aprint_error_dev(sc->sc_dev, 2480 "Radio transmitter is off\n"); 2481 /* Turn the interface down. */ 2482 ifp->if_flags &= ~IFF_UP; 2483 iwn_stop(ifp, 1); 2484 return; /* No further processing. */ 2485 } 2486 break; 2487 } 2488 case IWN_START_SCAN: 2489 { 2490 struct iwn_start_scan *scan = 2491 (struct iwn_start_scan *)(desc + 1); 2492 2493 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2494 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2495 DPRINTFN(2, ("scanning channel %d status %x\n", 2496 scan->chan, le32toh(scan->status))); 2497 2498 /* Fix current channel. */ 2499 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2500 break; 2501 } 2502 case IWN_STOP_SCAN: 2503 { 2504 struct iwn_stop_scan *scan = 2505 (struct iwn_stop_scan *)(desc + 1); 2506 2507 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2508 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2509 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2510 scan->nchan, scan->status, scan->chan)); 2511 2512 if (scan->status == 1 && scan->chan <= 14 && 2513 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2514 /* 2515 * We just finished scanning 2GHz channels, 2516 * start scanning 5GHz ones. 2517 */ 2518 sc->sc_flags &= ~IWN_FLAG_SCANNING_2GHZ; 2519 sc->sc_flags |= IWN_FLAG_SCANNING_5GHZ; 2520 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2521 break; 2522 } 2523 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2524 ieee80211_end_scan(ic); 2525 break; 2526 } 2527 case IWN5000_CALIBRATION_RESULT: 2528 iwn5000_rx_calib_results(sc, desc, data); 2529 break; 2530 2531 case IWN5000_CALIBRATION_DONE: 2532 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2533 wakeup(sc); 2534 break; 2535 } 2536 2537 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2538 } 2539 2540 /* Tell the firmware what we have processed. */ 2541 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2542 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2543 } 2544 2545 /* 2546 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2547 * from power-down sleep mode. 2548 */ 2549 static void 2550 iwn_wakeup_intr(struct iwn_softc *sc) 2551 { 2552 int qid; 2553 2554 DPRINTF(("ucode wakeup from power-down sleep\n")); 2555 2556 /* Wakeup RX and TX rings. */ 2557 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2558 for (qid = 0; qid < sc->ntxqs; qid++) { 2559 struct iwn_tx_ring *ring = &sc->txq[qid]; 2560 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2561 } 2562 } 2563 2564 /* 2565 * Dump the error log of the firmware when a firmware panic occurs. Although 2566 * we can't debug the firmware because it is neither open source nor free, it 2567 * can help us to identify certain classes of problems. 2568 */ 2569 static void 2570 iwn_fatal_intr(struct iwn_softc *sc) 2571 { 2572 struct iwn_fw_dump dump; 2573 int i; 2574 2575 /* Force a complete recalibration on next init. */ 2576 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2577 2578 /* Check that the error log address is valid. */ 2579 if (sc->errptr < IWN_FW_DATA_BASE || 2580 sc->errptr + sizeof (dump) > 2581 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2582 aprint_error_dev(sc->sc_dev, 2583 "bad firmware error log address 0x%08x\n", sc->errptr); 2584 return; 2585 } 2586 if (iwn_nic_lock(sc) != 0) { 2587 aprint_error_dev(sc->sc_dev, 2588 "could not read firmware error log\n"); 2589 return; 2590 } 2591 /* Read firmware error log from SRAM. */ 2592 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2593 sizeof (dump) / sizeof (uint32_t)); 2594 iwn_nic_unlock(sc); 2595 2596 if (dump.valid == 0) { 2597 aprint_error_dev(sc->sc_dev, 2598 "firmware error log is empty\n"); 2599 return; 2600 } 2601 aprint_error("firmware error log:\n"); 2602 aprint_error(" error type = \"%s\" (0x%08X)\n", 2603 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2604 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2605 dump.id); 2606 aprint_error(" program counter = 0x%08X\n", dump.pc); 2607 aprint_error(" source line = 0x%08X\n", dump.src_line); 2608 aprint_error(" error data = 0x%08X%08X\n", 2609 dump.error_data[0], dump.error_data[1]); 2610 aprint_error(" branch link = 0x%08X%08X\n", 2611 dump.branch_link[0], dump.branch_link[1]); 2612 aprint_error(" interrupt link = 0x%08X%08X\n", 2613 dump.interrupt_link[0], dump.interrupt_link[1]); 2614 aprint_error(" time = %u\n", dump.time[0]); 2615 2616 /* Dump driver status (TX and RX rings) while we're here. */ 2617 aprint_error("driver status:\n"); 2618 for (i = 0; i < sc->ntxqs; i++) { 2619 struct iwn_tx_ring *ring = &sc->txq[i]; 2620 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2621 i, ring->qid, ring->cur, ring->queued); 2622 } 2623 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2624 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2625 } 2626 2627 static int 2628 iwn_intr(void *arg) 2629 { 2630 struct iwn_softc *sc = arg; 2631 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2632 uint32_t r1, r2, tmp; 2633 2634 /* Disable interrupts. */ 2635 IWN_WRITE(sc, IWN_INT_MASK, 0); 2636 2637 /* Read interrupts from ICT (fast) or from registers (slow). */ 2638 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2639 tmp = 0; 2640 while (sc->ict[sc->ict_cur] != 0) { 2641 tmp |= sc->ict[sc->ict_cur]; 2642 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2643 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2644 } 2645 tmp = le32toh(tmp); 2646 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2647 tmp = 0; 2648 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2649 tmp |= 0x8000; 2650 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2651 r2 = 0; /* Unused. */ 2652 } else { 2653 r1 = IWN_READ(sc, IWN_INT); 2654 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2655 return 0; /* Hardware gone! */ 2656 r2 = IWN_READ(sc, IWN_FH_INT); 2657 } 2658 if (r1 == 0 && r2 == 0) { 2659 if (ifp->if_flags & IFF_UP) 2660 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2661 return 0; /* Interrupt not for us. */ 2662 } 2663 2664 /* Acknowledge interrupts. */ 2665 IWN_WRITE(sc, IWN_INT, r1); 2666 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2667 IWN_WRITE(sc, IWN_FH_INT, r2); 2668 2669 if (r1 & IWN_INT_RF_TOGGLED) { 2670 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2671 aprint_error_dev(sc->sc_dev, 2672 "RF switch: radio %s\n", 2673 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2674 } 2675 if (r1 & IWN_INT_CT_REACHED) { 2676 aprint_error_dev(sc->sc_dev, 2677 "critical temperature reached!\n"); 2678 } 2679 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2680 aprint_error_dev(sc->sc_dev, 2681 "fatal firmware error\n"); 2682 /* Dump firmware error log and stop. */ 2683 iwn_fatal_intr(sc); 2684 ifp->if_flags &= ~IFF_UP; 2685 iwn_stop(ifp, 1); 2686 return 1; 2687 } 2688 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2689 (r2 & IWN_FH_INT_RX)) { 2690 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2691 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2692 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2693 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2694 IWN_INT_PERIODIC_DIS); 2695 iwn_notif_intr(sc); 2696 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2697 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2698 IWN_INT_PERIODIC_ENA); 2699 } 2700 } else 2701 iwn_notif_intr(sc); 2702 } 2703 2704 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2705 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2706 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2707 wakeup(sc); /* FH DMA transfer completed. */ 2708 } 2709 2710 if (r1 & IWN_INT_ALIVE) 2711 wakeup(sc); /* Firmware is alive. */ 2712 2713 if (r1 & IWN_INT_WAKEUP) 2714 iwn_wakeup_intr(sc); 2715 2716 /* Re-enable interrupts. */ 2717 if (ifp->if_flags & IFF_UP) 2718 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2719 2720 return 1; 2721 } 2722 2723 /* 2724 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2725 * 5000 adapters use a slightly different format). 2726 */ 2727 static void 2728 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2729 uint16_t len) 2730 { 2731 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2732 2733 *w = htole16(len + 8); 2734 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2735 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2736 sizeof (uint16_t), 2737 BUS_DMASYNC_PREWRITE); 2738 if (idx < IWN_SCHED_WINSZ) { 2739 *(w + IWN_TX_RING_COUNT) = *w; 2740 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2741 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2742 (char *)(void *)sc->sched_dma.vaddr, 2743 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2744 } 2745 } 2746 2747 static void 2748 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2749 uint16_t len) 2750 { 2751 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2752 2753 *w = htole16(id << 12 | (len + 8)); 2754 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2755 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2756 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2757 if (idx < IWN_SCHED_WINSZ) { 2758 *(w + IWN_TX_RING_COUNT) = *w; 2759 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2760 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2761 (char *)(void *)sc->sched_dma.vaddr, 2762 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2763 } 2764 } 2765 2766 #ifdef notyet 2767 static void 2768 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2769 { 2770 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2771 2772 *w = (*w & htole16(0xf000)) | htole16(1); 2773 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2774 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2775 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2776 if (idx < IWN_SCHED_WINSZ) { 2777 *(w + IWN_TX_RING_COUNT) = *w; 2778 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2779 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2780 (char *)(void *)sc->sched_dma.vaddr, 2781 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2782 } 2783 } 2784 #endif 2785 2786 static int 2787 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2788 { 2789 struct ieee80211com *ic = &sc->sc_ic; 2790 struct iwn_node *wn = (void *)ni; 2791 struct iwn_tx_ring *ring; 2792 struct iwn_tx_desc *desc; 2793 struct iwn_tx_data *data; 2794 struct iwn_tx_cmd *cmd; 2795 struct iwn_cmd_data *tx; 2796 const struct iwn_rate *rinfo; 2797 struct ieee80211_frame *wh; 2798 struct ieee80211_key *k = NULL; 2799 struct mbuf *m1; 2800 uint32_t flags; 2801 u_int hdrlen; 2802 bus_dma_segment_t *seg; 2803 uint8_t tid, ridx, txant, type; 2804 int i, totlen, error, pad; 2805 2806 const struct chanAccParams *cap; 2807 int noack; 2808 int hdrlen2; 2809 2810 wh = mtod(m, struct ieee80211_frame *); 2811 hdrlen = ieee80211_anyhdrsize(wh); 2812 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2813 2814 hdrlen2 = (ieee80211_has_qos(wh)) ? 2815 sizeof (struct ieee80211_qosframe) : 2816 sizeof (struct ieee80211_frame); 2817 2818 if (hdrlen != hdrlen2) 2819 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2820 hdrlen, hdrlen2); 2821 2822 /* XXX OpenBSD sets a different tid when using QOS */ 2823 tid = 0; 2824 if (ieee80211_has_qos(wh)) { 2825 cap = &ic->ic_wme.wme_chanParams; 2826 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2827 } 2828 else 2829 noack = 0; 2830 2831 ring = &sc->txq[ac]; 2832 desc = &ring->desc[ring->cur]; 2833 data = &ring->data[ring->cur]; 2834 2835 /* Choose a TX rate index. */ 2836 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2837 type != IEEE80211_FC0_TYPE_DATA) { 2838 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2839 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2840 } else if (ic->ic_fixed_rate != -1) { 2841 ridx = sc->fixed_ridx; 2842 } else 2843 ridx = wn->ridx[ni->ni_txrate]; 2844 rinfo = &iwn_rates[ridx]; 2845 2846 /* Encrypt the frame if need be. */ 2847 /* 2848 * XXX For now, NetBSD swaps the encryption and bpf sections 2849 * in order to match old code and other drivers. Tests with 2850 * tcpdump indicates that the order is irrelevant, however, 2851 * as bpf produces unencrypted data for both ordering choices. 2852 */ 2853 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2854 k = ieee80211_crypto_encap(ic, ni, m); 2855 if (k == NULL) { 2856 m_freem(m); 2857 return ENOBUFS; 2858 } 2859 /* Packet header may have moved, reset our local pointer. */ 2860 wh = mtod(m, struct ieee80211_frame *); 2861 } 2862 totlen = m->m_pkthdr.len; 2863 2864 if (sc->sc_drvbpf != NULL) { 2865 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2866 2867 tap->wt_flags = 0; 2868 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2869 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2870 tap->wt_rate = rinfo->rate; 2871 tap->wt_hwqueue = ac; 2872 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2873 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2874 2875 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2876 } 2877 2878 /* Prepare TX firmware command. */ 2879 cmd = &ring->cmd[ring->cur]; 2880 cmd->code = IWN_CMD_TX_DATA; 2881 cmd->flags = 0; 2882 cmd->qid = ring->qid; 2883 cmd->idx = ring->cur; 2884 2885 tx = (struct iwn_cmd_data *)cmd->data; 2886 /* NB: No need to clear tx, all fields are reinitialized here. */ 2887 tx->scratch = 0; /* clear "scratch" area */ 2888 2889 flags = 0; 2890 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2891 /* Unicast frame, check if an ACK is expected. */ 2892 if (!noack) 2893 flags |= IWN_TX_NEED_ACK; 2894 } 2895 2896 #ifdef notyet 2897 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2898 if ((wh->i_fc[0] & 2899 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2900 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2901 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2902 #endif 2903 2904 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2905 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2906 2907 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2908 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2909 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2910 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2911 flags |= IWN_TX_NEED_RTS; 2912 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2913 ridx >= IWN_RIDX_OFDM6) { 2914 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2915 flags |= IWN_TX_NEED_CTS; 2916 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2917 flags |= IWN_TX_NEED_RTS; 2918 } 2919 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2920 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2921 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2922 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2923 flags |= IWN_TX_NEED_PROTECTION; 2924 } else 2925 flags |= IWN_TX_FULL_TXOP; 2926 } 2927 } 2928 2929 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2930 type != IEEE80211_FC0_TYPE_DATA) 2931 tx->id = sc->broadcast_id; 2932 else 2933 tx->id = wn->id; 2934 2935 if (type == IEEE80211_FC0_TYPE_MGT) { 2936 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2937 2938 #ifndef IEEE80211_STA_ONLY 2939 /* Tell HW to set timestamp in probe responses. */ 2940 /* XXX NetBSD rev 1.11 added probe requests here but */ 2941 /* probe requests do not take timestamps (from Bergamini). */ 2942 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2943 flags |= IWN_TX_INSERT_TSTAMP; 2944 #endif 2945 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2946 /* changes here. These are not needed (from Bergamini). */ 2947 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2948 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2949 tx->timeout = htole16(3); 2950 else 2951 tx->timeout = htole16(2); 2952 } else 2953 tx->timeout = htole16(0); 2954 2955 if (hdrlen & 3) { 2956 /* First segment length must be a multiple of 4. */ 2957 flags |= IWN_TX_NEED_PADDING; 2958 pad = 4 - (hdrlen & 3); 2959 } else 2960 pad = 0; 2961 2962 tx->len = htole16(totlen); 2963 tx->tid = tid; 2964 tx->rts_ntries = 60; 2965 tx->data_ntries = 15; 2966 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2967 tx->plcp = rinfo->plcp; 2968 tx->rflags = rinfo->flags; 2969 if (tx->id == sc->broadcast_id) { 2970 /* Group or management frame. */ 2971 tx->linkq = 0; 2972 /* XXX Alternate between antenna A and B? */ 2973 txant = IWN_LSB(sc->txchainmask); 2974 tx->rflags |= IWN_RFLAG_ANT(txant); 2975 } else { 2976 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2977 flags |= IWN_TX_LINKQ; /* enable MRR */ 2978 } 2979 /* Set physical address of "scratch area". */ 2980 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2981 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2982 2983 /* Copy 802.11 header in TX command. */ 2984 /* XXX NetBSD changed this in rev 1.20 */ 2985 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2986 2987 /* Trim 802.11 header. */ 2988 m_adj(m, hdrlen); 2989 tx->security = 0; 2990 tx->flags = htole32(flags); 2991 2992 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2993 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2994 if (error != 0) { 2995 if (error != EFBIG) { 2996 aprint_error_dev(sc->sc_dev, 2997 "can't map mbuf (error %d)\n", error); 2998 m_freem(m); 2999 return error; 3000 } 3001 /* Too many DMA segments, linearize mbuf. */ 3002 MGETHDR(m1, M_DONTWAIT, MT_DATA); 3003 if (m1 == NULL) { 3004 m_freem(m); 3005 return ENOBUFS; 3006 } 3007 if (m->m_pkthdr.len > MHLEN) { 3008 MCLGET(m1, M_DONTWAIT); 3009 if (!(m1->m_flags & M_EXT)) { 3010 m_freem(m); 3011 m_freem(m1); 3012 return ENOBUFS; 3013 } 3014 } 3015 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 3016 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3017 m_freem(m); 3018 m = m1; 3019 3020 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3021 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3022 if (error != 0) { 3023 aprint_error_dev(sc->sc_dev, 3024 "can't map mbuf (error %d)\n", error); 3025 m_freem(m); 3026 return error; 3027 } 3028 } 3029 3030 data->m = m; 3031 data->ni = ni; 3032 3033 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3034 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3035 3036 /* Fill TX descriptor. */ 3037 desc->nsegs = 1 + data->map->dm_nsegs; 3038 /* First DMA segment is used by the TX command. */ 3039 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3040 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3041 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3042 /* Other DMA segments are for data payload. */ 3043 seg = data->map->dm_segs; 3044 for (i = 1; i <= data->map->dm_nsegs; i++) { 3045 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3046 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3047 seg->ds_len << 4); 3048 seg++; 3049 } 3050 3051 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3052 BUS_DMASYNC_PREWRITE); 3053 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3054 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3055 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3056 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3057 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3058 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3059 3060 #ifdef notyet 3061 /* Update TX scheduler. */ 3062 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3063 #endif 3064 3065 /* Kick TX ring. */ 3066 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3067 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3068 3069 /* Mark TX ring as full if we reach a certain threshold. */ 3070 if (++ring->queued > IWN_TX_RING_HIMARK) 3071 sc->qfullmsk |= 1 << ring->qid; 3072 3073 return 0; 3074 } 3075 3076 static void 3077 iwn_start(struct ifnet *ifp) 3078 { 3079 struct iwn_softc *sc = ifp->if_softc; 3080 struct ieee80211com *ic = &sc->sc_ic; 3081 struct ieee80211_node *ni; 3082 struct ether_header *eh; 3083 struct mbuf *m; 3084 int ac; 3085 3086 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3087 return; 3088 3089 for (;;) { 3090 if (sc->qfullmsk != 0) { 3091 ifp->if_flags |= IFF_OACTIVE; 3092 break; 3093 } 3094 /* Send pending management frames first. */ 3095 IF_DEQUEUE(&ic->ic_mgtq, m); 3096 if (m != NULL) { 3097 ni = (void *)m->m_pkthdr.rcvif; 3098 ac = 0; 3099 goto sendit; 3100 } 3101 if (ic->ic_state != IEEE80211_S_RUN) 3102 break; 3103 3104 /* Encapsulate and send data frames. */ 3105 IFQ_DEQUEUE(&ifp->if_snd, m); 3106 if (m == NULL) 3107 break; 3108 if (m->m_len < sizeof (*eh) && 3109 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3110 ifp->if_oerrors++; 3111 continue; 3112 } 3113 eh = mtod(m, struct ether_header *); 3114 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3115 if (ni == NULL) { 3116 m_freem(m); 3117 ifp->if_oerrors++; 3118 continue; 3119 } 3120 /* classify mbuf so we can find which tx ring to use */ 3121 if (ieee80211_classify(ic, m, ni) != 0) { 3122 m_freem(m); 3123 ieee80211_free_node(ni); 3124 ifp->if_oerrors++; 3125 continue; 3126 } 3127 3128 /* No QoS encapsulation for EAPOL frames. */ 3129 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3130 M_WME_GETAC(m) : WME_AC_BE; 3131 3132 bpf_mtap(ifp, m); 3133 3134 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3135 ieee80211_free_node(ni); 3136 ifp->if_oerrors++; 3137 continue; 3138 } 3139 sendit: 3140 bpf_mtap3(ic->ic_rawbpf, m); 3141 3142 if (iwn_tx(sc, m, ni, ac) != 0) { 3143 ieee80211_free_node(ni); 3144 ifp->if_oerrors++; 3145 continue; 3146 } 3147 3148 sc->sc_tx_timer = 5; 3149 ifp->if_timer = 1; 3150 } 3151 } 3152 3153 static void 3154 iwn_watchdog(struct ifnet *ifp) 3155 { 3156 struct iwn_softc *sc = ifp->if_softc; 3157 3158 ifp->if_timer = 0; 3159 3160 if (sc->sc_tx_timer > 0) { 3161 if (--sc->sc_tx_timer == 0) { 3162 aprint_error_dev(sc->sc_dev, 3163 "device timeout\n"); 3164 ifp->if_flags &= ~IFF_UP; 3165 iwn_stop(ifp, 1); 3166 ifp->if_oerrors++; 3167 return; 3168 } 3169 ifp->if_timer = 1; 3170 } 3171 3172 ieee80211_watchdog(&sc->sc_ic); 3173 } 3174 3175 static int 3176 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3177 { 3178 struct iwn_softc *sc = ifp->if_softc; 3179 struct ieee80211com *ic = &sc->sc_ic; 3180 const struct sockaddr *sa; 3181 int s, error = 0; 3182 3183 s = splnet(); 3184 3185 switch (cmd) { 3186 case SIOCSIFADDR: 3187 ifp->if_flags |= IFF_UP; 3188 #ifdef INET 3189 struct ifaddr *ifa = (struct ifaddr *)data; 3190 if (ifa->ifa_addr->sa_family == AF_INET) 3191 arp_ifinit(&ic->ic_ac, ifa); 3192 #endif 3193 /* FALLTHROUGH */ 3194 case SIOCSIFFLAGS: 3195 /* XXX Added as it is in every NetBSD driver */ 3196 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3197 break; 3198 if (ifp->if_flags & IFF_UP) { 3199 if (!(ifp->if_flags & IFF_RUNNING)) 3200 error = iwn_init(ifp); 3201 } else { 3202 if (ifp->if_flags & IFF_RUNNING) 3203 iwn_stop(ifp, 1); 3204 } 3205 break; 3206 3207 case SIOCADDMULTI: 3208 case SIOCDELMULTI: 3209 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3210 error = (cmd == SIOCADDMULTI) ? 3211 ether_addmulti(sa, &sc->sc_ec) : 3212 ether_delmulti(sa, &sc->sc_ec); 3213 3214 if (error == ENETRESET) 3215 error = 0; 3216 break; 3217 3218 default: 3219 error = ieee80211_ioctl(ic, cmd, data); 3220 } 3221 3222 if (error == ENETRESET) { 3223 error = 0; 3224 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3225 (IFF_UP | IFF_RUNNING)) { 3226 iwn_stop(ifp, 0); 3227 error = iwn_init(ifp); 3228 } 3229 } 3230 3231 splx(s); 3232 return error; 3233 } 3234 3235 /* 3236 * Send a command to the firmware. 3237 */ 3238 static int 3239 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3240 { 3241 struct iwn_tx_ring *ring = &sc->txq[4]; 3242 struct iwn_tx_desc *desc; 3243 struct iwn_tx_data *data; 3244 struct iwn_tx_cmd *cmd; 3245 struct mbuf *m; 3246 bus_addr_t paddr; 3247 int totlen, error; 3248 3249 desc = &ring->desc[ring->cur]; 3250 data = &ring->data[ring->cur]; 3251 totlen = 4 + size; 3252 3253 if (size > sizeof cmd->data) { 3254 /* Command is too large to fit in a descriptor. */ 3255 if (totlen > MCLBYTES) 3256 return EINVAL; 3257 MGETHDR(m, M_DONTWAIT, MT_DATA); 3258 if (m == NULL) 3259 return ENOMEM; 3260 if (totlen > MHLEN) { 3261 MCLGET(m, M_DONTWAIT); 3262 if (!(m->m_flags & M_EXT)) { 3263 m_freem(m); 3264 return ENOMEM; 3265 } 3266 } 3267 cmd = mtod(m, struct iwn_tx_cmd *); 3268 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3269 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3270 if (error != 0) { 3271 m_freem(m); 3272 return error; 3273 } 3274 data->m = m; 3275 paddr = data->map->dm_segs[0].ds_addr; 3276 } else { 3277 cmd = &ring->cmd[ring->cur]; 3278 paddr = data->cmd_paddr; 3279 } 3280 3281 cmd->code = code; 3282 cmd->flags = 0; 3283 cmd->qid = ring->qid; 3284 cmd->idx = ring->cur; 3285 memcpy(cmd->data, buf, size); 3286 3287 desc->nsegs = 1; 3288 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3289 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3290 3291 if (size > sizeof cmd->data) { 3292 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3293 BUS_DMASYNC_PREWRITE); 3294 } else { 3295 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3296 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3297 totlen, BUS_DMASYNC_PREWRITE); 3298 } 3299 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3300 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3301 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3302 3303 #ifdef notyet 3304 /* Update TX scheduler. */ 3305 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3306 #endif 3307 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3308 3309 /* Kick command ring. */ 3310 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3311 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3312 3313 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3314 } 3315 3316 static int 3317 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3318 { 3319 struct iwn4965_node_info hnode; 3320 char *src, *dst; 3321 3322 /* 3323 * We use the node structure for 5000 Series internally (it is 3324 * a superset of the one for 4965AGN). We thus copy the common 3325 * fields before sending the command. 3326 */ 3327 src = (char *)node; 3328 dst = (char *)&hnode; 3329 memcpy(dst, src, 48); 3330 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3331 memcpy(dst + 48, src + 72, 20); 3332 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3333 } 3334 3335 static int 3336 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3337 { 3338 /* Direct mapping. */ 3339 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3340 } 3341 3342 static int 3343 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3344 { 3345 struct iwn_node *wn = (void *)ni; 3346 struct ieee80211_rateset *rs = &ni->ni_rates; 3347 struct iwn_cmd_link_quality linkq; 3348 const struct iwn_rate *rinfo; 3349 uint8_t txant; 3350 int i, txrate; 3351 3352 /* Use the first valid TX antenna. */ 3353 txant = IWN_LSB(sc->txchainmask); 3354 3355 memset(&linkq, 0, sizeof linkq); 3356 linkq.id = wn->id; 3357 linkq.antmsk_1stream = txant; 3358 linkq.antmsk_2stream = IWN_ANT_AB; 3359 linkq.ampdu_max = 31; 3360 linkq.ampdu_threshold = 3; 3361 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3362 3363 /* Start at highest available bit-rate. */ 3364 txrate = rs->rs_nrates - 1; 3365 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3366 rinfo = &iwn_rates[wn->ridx[txrate]]; 3367 linkq.retry[i].plcp = rinfo->plcp; 3368 linkq.retry[i].rflags = rinfo->flags; 3369 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3370 /* Next retry at immediate lower bit-rate. */ 3371 if (txrate > 0) 3372 txrate--; 3373 } 3374 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3375 } 3376 3377 /* 3378 * Broadcast node is used to send group-addressed and management frames. 3379 */ 3380 static int 3381 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3382 { 3383 struct iwn_ops *ops = &sc->ops; 3384 struct iwn_node_info node; 3385 struct iwn_cmd_link_quality linkq; 3386 const struct iwn_rate *rinfo; 3387 uint8_t txant; 3388 int i, error; 3389 3390 memset(&node, 0, sizeof node); 3391 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3392 node.id = sc->broadcast_id; 3393 DPRINTF(("adding broadcast node\n")); 3394 if ((error = ops->add_node(sc, &node, async)) != 0) 3395 return error; 3396 3397 /* Use the first valid TX antenna. */ 3398 txant = IWN_LSB(sc->txchainmask); 3399 3400 memset(&linkq, 0, sizeof linkq); 3401 linkq.id = sc->broadcast_id; 3402 linkq.antmsk_1stream = txant; 3403 linkq.antmsk_2stream = IWN_ANT_AB; 3404 linkq.ampdu_max = 64; 3405 linkq.ampdu_threshold = 3; 3406 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3407 3408 /* Use lowest mandatory bit-rate. */ 3409 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3410 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3411 linkq.retry[0].plcp = rinfo->plcp; 3412 linkq.retry[0].rflags = rinfo->flags; 3413 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3414 /* Use same bit-rate for all TX retries. */ 3415 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3416 linkq.retry[i].plcp = linkq.retry[0].plcp; 3417 linkq.retry[i].rflags = linkq.retry[0].rflags; 3418 } 3419 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3420 } 3421 3422 static void 3423 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3424 { 3425 struct iwn_cmd_led led; 3426 3427 /* Clear microcode LED ownership. */ 3428 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3429 3430 led.which = which; 3431 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3432 led.off = off; 3433 led.on = on; 3434 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3435 } 3436 3437 /* 3438 * Set the critical temperature at which the firmware will stop the radio 3439 * and notify us. 3440 */ 3441 static int 3442 iwn_set_critical_temp(struct iwn_softc *sc) 3443 { 3444 struct iwn_critical_temp crit; 3445 int32_t temp; 3446 3447 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3448 3449 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3450 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3451 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3452 temp = IWN_CTOK(110); 3453 else 3454 temp = 110; 3455 memset(&crit, 0, sizeof crit); 3456 crit.tempR = htole32(temp); 3457 DPRINTF(("setting critical temperature to %d\n", temp)); 3458 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3459 } 3460 3461 static int 3462 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3463 { 3464 struct iwn_cmd_timing cmd; 3465 uint64_t val, mod; 3466 3467 memset(&cmd, 0, sizeof cmd); 3468 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3469 cmd.bintval = htole16(ni->ni_intval); 3470 cmd.lintval = htole16(10); 3471 3472 /* Compute remaining time until next beacon. */ 3473 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3474 mod = le64toh(cmd.tstamp) % val; 3475 cmd.binitval = htole32((uint32_t)(val - mod)); 3476 3477 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3478 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3479 3480 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3481 } 3482 3483 static void 3484 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3485 { 3486 /* Adjust TX power if need be (delta >= 3 degC). */ 3487 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3488 if (abs(temp - sc->temp) >= 3) { 3489 /* Record temperature of last calibration. */ 3490 sc->temp = temp; 3491 (void)iwn4965_set_txpower(sc, 1); 3492 } 3493 } 3494 3495 /* 3496 * Set TX power for current channel (each rate has its own power settings). 3497 * This function takes into account the regulatory information from EEPROM, 3498 * the current temperature and the current voltage. 3499 */ 3500 static int 3501 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3502 { 3503 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3504 #define fdivround(a, b, n) \ 3505 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3506 /* Linear interpolation. */ 3507 #define interpolate(x, x1, y1, x2, y2, n) \ 3508 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3509 3510 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3511 struct ieee80211com *ic = &sc->sc_ic; 3512 struct iwn_ucode_info *uc = &sc->ucode_info; 3513 struct ieee80211_channel *ch; 3514 struct iwn4965_cmd_txpower cmd; 3515 struct iwn4965_eeprom_chan_samples *chans; 3516 const uint8_t *rf_gain, *dsp_gain; 3517 int32_t vdiff, tdiff; 3518 int i, c, grp, maxpwr; 3519 uint8_t chan; 3520 3521 /* Retrieve current channel from last RXON. */ 3522 chan = sc->rxon.chan; 3523 DPRINTF(("setting TX power for channel %d\n", chan)); 3524 ch = &ic->ic_channels[chan]; 3525 3526 memset(&cmd, 0, sizeof cmd); 3527 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3528 cmd.chan = chan; 3529 3530 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3531 maxpwr = sc->maxpwr5GHz; 3532 rf_gain = iwn4965_rf_gain_5ghz; 3533 dsp_gain = iwn4965_dsp_gain_5ghz; 3534 } else { 3535 maxpwr = sc->maxpwr2GHz; 3536 rf_gain = iwn4965_rf_gain_2ghz; 3537 dsp_gain = iwn4965_dsp_gain_2ghz; 3538 } 3539 3540 /* Compute voltage compensation. */ 3541 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3542 if (vdiff > 0) 3543 vdiff *= 2; 3544 if (abs(vdiff) > 2) 3545 vdiff = 0; 3546 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3547 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3548 3549 /* Get channel attenuation group. */ 3550 if (chan <= 20) /* 1-20 */ 3551 grp = 4; 3552 else if (chan <= 43) /* 34-43 */ 3553 grp = 0; 3554 else if (chan <= 70) /* 44-70 */ 3555 grp = 1; 3556 else if (chan <= 124) /* 71-124 */ 3557 grp = 2; 3558 else /* 125-200 */ 3559 grp = 3; 3560 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3561 3562 /* Get channel sub-band. */ 3563 for (i = 0; i < IWN_NBANDS; i++) 3564 if (sc->bands[i].lo != 0 && 3565 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3566 break; 3567 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3568 return EINVAL; 3569 chans = sc->bands[i].chans; 3570 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3571 3572 for (c = 0; c < 2; c++) { 3573 uint8_t power, gain, temp; 3574 int maxchpwr, pwr, ridx, idx; 3575 3576 power = interpolate(chan, 3577 chans[0].num, chans[0].samples[c][1].power, 3578 chans[1].num, chans[1].samples[c][1].power, 1); 3579 gain = interpolate(chan, 3580 chans[0].num, chans[0].samples[c][1].gain, 3581 chans[1].num, chans[1].samples[c][1].gain, 1); 3582 temp = interpolate(chan, 3583 chans[0].num, chans[0].samples[c][1].temp, 3584 chans[1].num, chans[1].samples[c][1].temp, 1); 3585 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3586 c, power, gain, temp)); 3587 3588 /* Compute temperature compensation. */ 3589 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3590 DPRINTF(("temperature compensation=%d (current=%d, " 3591 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3592 3593 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3594 /* Convert dBm to half-dBm. */ 3595 maxchpwr = sc->maxpwr[chan] * 2; 3596 if ((ridx / 8) & 1) 3597 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3598 3599 pwr = maxpwr; 3600 3601 /* Adjust TX power based on rate. */ 3602 if ((ridx % 8) == 5) 3603 pwr -= 15; /* OFDM48: -7.5dB */ 3604 else if ((ridx % 8) == 6) 3605 pwr -= 17; /* OFDM54: -8.5dB */ 3606 else if ((ridx % 8) == 7) 3607 pwr -= 20; /* OFDM60: -10dB */ 3608 else 3609 pwr -= 10; /* Others: -5dB */ 3610 3611 /* Do not exceed channel max TX power. */ 3612 if (pwr > maxchpwr) 3613 pwr = maxchpwr; 3614 3615 idx = gain - (pwr - power) - tdiff - vdiff; 3616 if ((ridx / 8) & 1) /* MIMO */ 3617 idx += (int32_t)le32toh(uc->atten[grp][c]); 3618 3619 if (cmd.band == 0) 3620 idx += 9; /* 5GHz */ 3621 if (ridx == IWN_RIDX_MAX) 3622 idx += 5; /* CCK */ 3623 3624 /* Make sure idx stays in a valid range. */ 3625 if (idx < 0) 3626 idx = 0; 3627 else if (idx > IWN4965_MAX_PWR_INDEX) 3628 idx = IWN4965_MAX_PWR_INDEX; 3629 3630 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3631 c, ridx, idx)); 3632 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3633 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3634 } 3635 } 3636 3637 DPRINTF(("setting TX power for chan %d\n", chan)); 3638 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3639 3640 #undef interpolate 3641 #undef fdivround 3642 } 3643 3644 static int 3645 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3646 { 3647 struct iwn5000_cmd_txpower cmd; 3648 3649 /* 3650 * TX power calibration is handled automatically by the firmware 3651 * for 5000 Series. 3652 */ 3653 memset(&cmd, 0, sizeof cmd); 3654 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3655 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3656 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3657 DPRINTF(("setting TX power\n")); 3658 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3659 } 3660 3661 /* 3662 * Retrieve the maximum RSSI (in dBm) among receivers. 3663 */ 3664 static int 3665 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3666 { 3667 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3668 uint8_t mask, agc; 3669 int rssi; 3670 3671 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3672 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3673 3674 rssi = 0; 3675 if (mask & IWN_ANT_A) 3676 rssi = MAX(rssi, phy->rssi[0]); 3677 if (mask & IWN_ANT_B) 3678 rssi = MAX(rssi, phy->rssi[2]); 3679 if (mask & IWN_ANT_C) 3680 rssi = MAX(rssi, phy->rssi[4]); 3681 3682 return rssi - agc - IWN_RSSI_TO_DBM; 3683 } 3684 3685 static int 3686 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3687 { 3688 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3689 uint8_t agc; 3690 int rssi; 3691 3692 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3693 3694 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3695 le16toh(phy->rssi[1]) & 0xff); 3696 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3697 3698 return rssi - agc - IWN_RSSI_TO_DBM; 3699 } 3700 3701 /* 3702 * Retrieve the average noise (in dBm) among receivers. 3703 */ 3704 static int 3705 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3706 { 3707 int i, total, nbant, noise; 3708 3709 total = nbant = 0; 3710 for (i = 0; i < 3; i++) { 3711 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3712 continue; 3713 total += noise; 3714 nbant++; 3715 } 3716 /* There should be at least one antenna but check anyway. */ 3717 return (nbant == 0) ? -127 : (total / nbant) - 107; 3718 } 3719 3720 /* 3721 * Compute temperature (in degC) from last received statistics. 3722 */ 3723 static int 3724 iwn4965_get_temperature(struct iwn_softc *sc) 3725 { 3726 struct iwn_ucode_info *uc = &sc->ucode_info; 3727 int32_t r1, r2, r3, r4, temp; 3728 3729 r1 = le32toh(uc->temp[0].chan20MHz); 3730 r2 = le32toh(uc->temp[1].chan20MHz); 3731 r3 = le32toh(uc->temp[2].chan20MHz); 3732 r4 = le32toh(sc->rawtemp); 3733 3734 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3735 return 0; 3736 3737 /* Sign-extend 23-bit R4 value to 32-bit. */ 3738 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3739 /* Compute temperature in Kelvin. */ 3740 temp = (259 * (r4 - r2)) / (r3 - r1); 3741 temp = (temp * 97) / 100 + 8; 3742 3743 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3744 return IWN_KTOC(temp); 3745 } 3746 3747 static int 3748 iwn5000_get_temperature(struct iwn_softc *sc) 3749 { 3750 int32_t temp; 3751 3752 /* 3753 * Temperature is not used by the driver for 5000 Series because 3754 * TX power calibration is handled by firmware. We export it to 3755 * users through the sensor framework though. 3756 */ 3757 temp = le32toh(sc->rawtemp); 3758 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3759 temp = (temp / -5) + sc->temp_off; 3760 temp = IWN_KTOC(temp); 3761 } 3762 return temp; 3763 } 3764 3765 /* 3766 * Initialize sensitivity calibration state machine. 3767 */ 3768 static int 3769 iwn_init_sensitivity(struct iwn_softc *sc) 3770 { 3771 struct iwn_ops *ops = &sc->ops; 3772 struct iwn_calib_state *calib = &sc->calib; 3773 uint32_t flags; 3774 int error; 3775 3776 /* Reset calibration state machine. */ 3777 memset(calib, 0, sizeof (*calib)); 3778 calib->state = IWN_CALIB_STATE_INIT; 3779 calib->cck_state = IWN_CCK_STATE_HIFA; 3780 /* Set initial correlation values. */ 3781 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3782 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3783 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3784 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3785 calib->cck_x4 = 125; 3786 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3787 calib->energy_cck = sc->limits->energy_cck; 3788 3789 /* Write initial sensitivity. */ 3790 if ((error = iwn_send_sensitivity(sc)) != 0) 3791 return error; 3792 3793 /* Write initial gains. */ 3794 if ((error = ops->init_gains(sc)) != 0) 3795 return error; 3796 3797 /* Request statistics at each beacon interval. */ 3798 flags = 0; 3799 DPRINTF(("sending request for statistics\n")); 3800 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3801 } 3802 3803 /* 3804 * Collect noise and RSSI statistics for the first 20 beacons received 3805 * after association and use them to determine connected antennas and 3806 * to set differential gains. 3807 */ 3808 static void 3809 iwn_collect_noise(struct iwn_softc *sc, 3810 const struct iwn_rx_general_stats *stats) 3811 { 3812 struct iwn_ops *ops = &sc->ops; 3813 struct iwn_calib_state *calib = &sc->calib; 3814 uint32_t val; 3815 int i; 3816 3817 /* Accumulate RSSI and noise for all 3 antennas. */ 3818 for (i = 0; i < 3; i++) { 3819 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3820 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3821 } 3822 /* NB: We update differential gains only once after 20 beacons. */ 3823 if (++calib->nbeacons < 20) 3824 return; 3825 3826 /* Determine highest average RSSI. */ 3827 val = MAX(calib->rssi[0], calib->rssi[1]); 3828 val = MAX(calib->rssi[2], val); 3829 3830 /* Determine which antennas are connected. */ 3831 sc->chainmask = sc->rxchainmask; 3832 for (i = 0; i < 3; i++) 3833 if (val - calib->rssi[i] > 15 * 20) 3834 sc->chainmask &= ~(1 << i); 3835 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3836 sc->rxchainmask, sc->chainmask)); 3837 3838 /* If none of the TX antennas are connected, keep at least one. */ 3839 if ((sc->chainmask & sc->txchainmask) == 0) 3840 sc->chainmask |= IWN_LSB(sc->txchainmask); 3841 3842 (void)ops->set_gains(sc); 3843 calib->state = IWN_CALIB_STATE_RUN; 3844 3845 #ifdef notyet 3846 /* XXX Disable RX chains with no antennas connected. */ 3847 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3848 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3849 #endif 3850 3851 /* Enable power-saving mode if requested by user. */ 3852 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3853 (void)iwn_set_pslevel(sc, 0, 3, 1); 3854 } 3855 3856 static int 3857 iwn4965_init_gains(struct iwn_softc *sc) 3858 { 3859 struct iwn_phy_calib_gain cmd; 3860 3861 memset(&cmd, 0, sizeof cmd); 3862 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3863 /* Differential gains initially set to 0 for all 3 antennas. */ 3864 DPRINTF(("setting initial differential gains\n")); 3865 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3866 } 3867 3868 static int 3869 iwn5000_init_gains(struct iwn_softc *sc) 3870 { 3871 struct iwn_phy_calib cmd; 3872 3873 memset(&cmd, 0, sizeof cmd); 3874 cmd.code = sc->reset_noise_gain; 3875 cmd.ngroups = 1; 3876 cmd.isvalid = 1; 3877 DPRINTF(("setting initial differential gains\n")); 3878 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3879 } 3880 3881 static int 3882 iwn4965_set_gains(struct iwn_softc *sc) 3883 { 3884 struct iwn_calib_state *calib = &sc->calib; 3885 struct iwn_phy_calib_gain cmd; 3886 int i, delta, noise; 3887 3888 /* Get minimal noise among connected antennas. */ 3889 noise = INT_MAX; /* NB: There's at least one antenna. */ 3890 for (i = 0; i < 3; i++) 3891 if (sc->chainmask & (1 << i)) 3892 noise = MIN(calib->noise[i], noise); 3893 3894 memset(&cmd, 0, sizeof cmd); 3895 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3896 /* Set differential gains for connected antennas. */ 3897 for (i = 0; i < 3; i++) { 3898 if (sc->chainmask & (1 << i)) { 3899 /* Compute attenuation (in unit of 1.5dB). */ 3900 delta = (noise - (int32_t)calib->noise[i]) / 30; 3901 /* NB: delta <= 0 */ 3902 /* Limit to [-4.5dB,0]. */ 3903 cmd.gain[i] = MIN(abs(delta), 3); 3904 if (delta < 0) 3905 cmd.gain[i] |= 1 << 2; /* sign bit */ 3906 } 3907 } 3908 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3909 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3910 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3911 } 3912 3913 static int 3914 iwn5000_set_gains(struct iwn_softc *sc) 3915 { 3916 struct iwn_calib_state *calib = &sc->calib; 3917 struct iwn_phy_calib_gain cmd; 3918 int i, ant, div, delta; 3919 3920 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3921 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3922 3923 memset(&cmd, 0, sizeof cmd); 3924 cmd.code = sc->noise_gain; 3925 cmd.ngroups = 1; 3926 cmd.isvalid = 1; 3927 /* Get first available RX antenna as referential. */ 3928 ant = IWN_LSB(sc->rxchainmask); 3929 /* Set differential gains for other antennas. */ 3930 for (i = ant + 1; i < 3; i++) { 3931 if (sc->chainmask & (1 << i)) { 3932 /* The delta is relative to antenna "ant". */ 3933 delta = ((int32_t)calib->noise[ant] - 3934 (int32_t)calib->noise[i]) / div; 3935 /* Limit to [-4.5dB,+4.5dB]. */ 3936 cmd.gain[i - 1] = MIN(abs(delta), 3); 3937 if (delta < 0) 3938 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3939 } 3940 } 3941 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3942 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3943 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3944 } 3945 3946 /* 3947 * Tune RF RX sensitivity based on the number of false alarms detected 3948 * during the last beacon period. 3949 */ 3950 static void 3951 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3952 { 3953 #define inc(val, inc, max) \ 3954 if ((val) < (max)) { \ 3955 if ((val) < (max) - (inc)) \ 3956 (val) += (inc); \ 3957 else \ 3958 (val) = (max); \ 3959 needs_update = 1; \ 3960 } 3961 #define dec(val, dec, min) \ 3962 if ((val) > (min)) { \ 3963 if ((val) > (min) + (dec)) \ 3964 (val) -= (dec); \ 3965 else \ 3966 (val) = (min); \ 3967 needs_update = 1; \ 3968 } 3969 3970 const struct iwn_sensitivity_limits *limits = sc->limits; 3971 struct iwn_calib_state *calib = &sc->calib; 3972 uint32_t val, rxena, fa; 3973 uint32_t energy[3], energy_min; 3974 uint8_t noise[3], noise_ref; 3975 int i, needs_update = 0; 3976 3977 /* Check that we've been enabled long enough. */ 3978 if ((rxena = le32toh(stats->general.load)) == 0) 3979 return; 3980 3981 /* Compute number of false alarms since last call for OFDM. */ 3982 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3983 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3984 fa *= 200 * 1024; /* 200TU */ 3985 3986 /* Save counters values for next call. */ 3987 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3988 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3989 3990 if (fa > 50 * rxena) { 3991 /* High false alarm count, decrease sensitivity. */ 3992 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3993 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3994 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3995 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3996 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3997 3998 } else if (fa < 5 * rxena) { 3999 /* Low false alarm count, increase sensitivity. */ 4000 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4001 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4002 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4003 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4004 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4005 } 4006 4007 /* Compute maximum noise among 3 receivers. */ 4008 for (i = 0; i < 3; i++) 4009 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4010 val = MAX(noise[0], noise[1]); 4011 val = MAX(noise[2], val); 4012 /* Insert it into our samples table. */ 4013 calib->noise_samples[calib->cur_noise_sample] = val; 4014 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4015 4016 /* Compute maximum noise among last 20 samples. */ 4017 noise_ref = calib->noise_samples[0]; 4018 for (i = 1; i < 20; i++) 4019 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4020 4021 /* Compute maximum energy among 3 receivers. */ 4022 for (i = 0; i < 3; i++) 4023 energy[i] = le32toh(stats->general.energy[i]); 4024 val = MIN(energy[0], energy[1]); 4025 val = MIN(energy[2], val); 4026 /* Insert it into our samples table. */ 4027 calib->energy_samples[calib->cur_energy_sample] = val; 4028 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4029 4030 /* Compute minimum energy among last 10 samples. */ 4031 energy_min = calib->energy_samples[0]; 4032 for (i = 1; i < 10; i++) 4033 energy_min = MAX(energy_min, calib->energy_samples[i]); 4034 energy_min += 6; 4035 4036 /* Compute number of false alarms since last call for CCK. */ 4037 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4038 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4039 fa *= 200 * 1024; /* 200TU */ 4040 4041 /* Save counters values for next call. */ 4042 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4043 calib->fa_cck = le32toh(stats->cck.fa); 4044 4045 if (fa > 50 * rxena) { 4046 /* High false alarm count, decrease sensitivity. */ 4047 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4048 calib->cck_state = IWN_CCK_STATE_HIFA; 4049 calib->low_fa = 0; 4050 4051 if (calib->cck_x4 > 160) { 4052 calib->noise_ref = noise_ref; 4053 if (calib->energy_cck > 2) 4054 dec(calib->energy_cck, 2, energy_min); 4055 } 4056 if (calib->cck_x4 < 160) { 4057 calib->cck_x4 = 161; 4058 needs_update = 1; 4059 } else 4060 inc(calib->cck_x4, 3, limits->max_cck_x4); 4061 4062 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4063 4064 } else if (fa < 5 * rxena) { 4065 /* Low false alarm count, increase sensitivity. */ 4066 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4067 calib->cck_state = IWN_CCK_STATE_LOFA; 4068 calib->low_fa++; 4069 4070 if (calib->cck_state != IWN_CCK_STATE_INIT && 4071 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4072 calib->low_fa > 100)) { 4073 inc(calib->energy_cck, 2, limits->min_energy_cck); 4074 dec(calib->cck_x4, 3, limits->min_cck_x4); 4075 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4076 } 4077 } else { 4078 /* Not worth to increase or decrease sensitivity. */ 4079 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4080 calib->low_fa = 0; 4081 calib->noise_ref = noise_ref; 4082 4083 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4084 /* Previous interval had many false alarms. */ 4085 dec(calib->energy_cck, 8, energy_min); 4086 } 4087 calib->cck_state = IWN_CCK_STATE_INIT; 4088 } 4089 4090 if (needs_update) 4091 (void)iwn_send_sensitivity(sc); 4092 #undef dec 4093 #undef inc 4094 } 4095 4096 static int 4097 iwn_send_sensitivity(struct iwn_softc *sc) 4098 { 4099 struct iwn_calib_state *calib = &sc->calib; 4100 struct iwn_enhanced_sensitivity_cmd cmd; 4101 int len; 4102 4103 memset(&cmd, 0, sizeof cmd); 4104 len = sizeof (struct iwn_sensitivity_cmd); 4105 cmd.which = IWN_SENSITIVITY_WORKTBL; 4106 /* OFDM modulation. */ 4107 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4108 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4109 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4110 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4111 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4112 cmd.energy_ofdm_th = htole16(62); 4113 /* CCK modulation. */ 4114 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4115 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4116 cmd.energy_cck = htole16(calib->energy_cck); 4117 /* Barker modulation: use default values. */ 4118 cmd.corr_barker = htole16(190); 4119 cmd.corr_barker_mrc = htole16(390); 4120 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4121 goto send; 4122 /* Enhanced sensitivity settings. */ 4123 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4124 cmd.ofdm_det_slope_mrc = htole16(668); 4125 cmd.ofdm_det_icept_mrc = htole16(4); 4126 cmd.ofdm_det_slope = htole16(486); 4127 cmd.ofdm_det_icept = htole16(37); 4128 cmd.cck_det_slope_mrc = htole16(853); 4129 cmd.cck_det_icept_mrc = htole16(4); 4130 cmd.cck_det_slope = htole16(476); 4131 cmd.cck_det_icept = htole16(99); 4132 send: 4133 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4134 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4135 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4136 calib->energy_cck)); 4137 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4138 } 4139 4140 /* 4141 * Set STA mode power saving level (between 0 and 5). 4142 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4143 */ 4144 static int 4145 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4146 { 4147 struct iwn_pmgt_cmd cmd; 4148 const struct iwn_pmgt *pmgt; 4149 uint32_t maxp, skip_dtim; 4150 pcireg_t reg; 4151 int i; 4152 4153 /* Select which PS parameters to use. */ 4154 if (dtim <= 2) 4155 pmgt = &iwn_pmgt[0][level]; 4156 else if (dtim <= 10) 4157 pmgt = &iwn_pmgt[1][level]; 4158 else 4159 pmgt = &iwn_pmgt[2][level]; 4160 4161 memset(&cmd, 0, sizeof cmd); 4162 if (level != 0) /* not CAM */ 4163 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4164 if (level == 5) 4165 cmd.flags |= htole16(IWN_PS_FAST_PD); 4166 /* Retrieve PCIe Active State Power Management (ASPM). */ 4167 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4168 sc->sc_cap_off + PCIE_LCSR); 4169 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4170 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4171 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4172 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4173 4174 if (dtim == 0) { 4175 dtim = 1; 4176 skip_dtim = 0; 4177 } else 4178 skip_dtim = pmgt->skip_dtim; 4179 if (skip_dtim != 0) { 4180 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4181 maxp = pmgt->intval[4]; 4182 if (maxp == (uint32_t)-1) 4183 maxp = dtim * (skip_dtim + 1); 4184 else if (maxp > dtim) 4185 maxp = (maxp / dtim) * dtim; 4186 } else 4187 maxp = dtim; 4188 for (i = 0; i < 5; i++) 4189 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4190 4191 DPRINTF(("setting power saving level to %d\n", level)); 4192 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4193 } 4194 4195 int 4196 iwn5000_runtime_calib(struct iwn_softc *sc) 4197 { 4198 struct iwn5000_calib_config cmd; 4199 4200 memset(&cmd, 0, sizeof cmd); 4201 cmd.ucode.once.enable = 0xffffffff; 4202 cmd.ucode.once.start = IWN5000_CALIB_DC; 4203 DPRINTF(("configuring runtime calibration\n")); 4204 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4205 } 4206 4207 static int 4208 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc) 4209 { 4210 struct iwn_bluetooth bluetooth; 4211 4212 memset(&bluetooth, 0, sizeof bluetooth); 4213 bluetooth.flags = IWN_BT_COEX_ENABLE; 4214 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4215 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4216 4217 DPRINTF(("configuring bluetooth coexistence\n")); 4218 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4219 } 4220 4221 static int 4222 iwn_config_bt_coex_prio_table(struct iwn_softc *sc) 4223 { 4224 uint8_t prio_table[16]; 4225 4226 memset(&prio_table, 0, sizeof prio_table); 4227 prio_table[ 0] = 6; /* init calibration 1 */ 4228 prio_table[ 1] = 7; /* init calibration 2 */ 4229 prio_table[ 2] = 2; /* periodic calib low 1 */ 4230 prio_table[ 3] = 3; /* periodic calib low 2 */ 4231 prio_table[ 4] = 4; /* periodic calib high 1 */ 4232 prio_table[ 5] = 5; /* periodic calib high 2 */ 4233 prio_table[ 6] = 6; /* dtim */ 4234 prio_table[ 7] = 8; /* scan52 */ 4235 prio_table[ 8] = 10; /* scan24 */ 4236 4237 DPRINTF(("sending priority lookup table\n")); 4238 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE, 4239 &prio_table, sizeof prio_table, 0); 4240 } 4241 4242 static int 4243 iwn_config_bt_coex_adv_config(struct iwn_softc *sc, struct iwn_bt_basic *basic, 4244 size_t len) 4245 { 4246 struct iwn_btcoex_prot btprot; 4247 int error; 4248 4249 basic->bt.flags = IWN_BT_COEX_ENABLE; 4250 basic->bt.lead_time = IWN_BT_LEAD_TIME_DEF; 4251 basic->bt.max_kill = IWN_BT_MAX_KILL_DEF; 4252 basic->bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF; 4253 basic->bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF; 4254 basic->bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF; 4255 basic->bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF; 4256 basic->bt3_timer_t2_value = IWN_BT_BT3_T2_DEF; 4257 basic->bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */ 4258 basic->bt3_lookup_table[ 1] = htole32(0xaaaaaaaa); 4259 basic->bt3_lookup_table[ 2] = htole32(0xaeaaaaaa); 4260 basic->bt3_lookup_table[ 3] = htole32(0xaaaaaaaa); 4261 basic->bt3_lookup_table[ 4] = htole32(0xcc00ff28); 4262 basic->bt3_lookup_table[ 5] = htole32(0x0000aaaa); 4263 basic->bt3_lookup_table[ 6] = htole32(0xcc00aaaa); 4264 basic->bt3_lookup_table[ 7] = htole32(0x0000aaaa); 4265 basic->bt3_lookup_table[ 8] = htole32(0xc0004000); 4266 basic->bt3_lookup_table[ 9] = htole32(0x00004000); 4267 basic->bt3_lookup_table[10] = htole32(0xf0005000); 4268 basic->bt3_lookup_table[11] = htole32(0xf0005000); 4269 basic->reduce_txpower = 0; /* as not implemented */ 4270 basic->valid = IWN_BT_ALL_VALID_MASK; 4271 4272 DPRINTF(("configuring advanced bluetooth coexistence v1\n")); 4273 error = iwn_cmd(sc, IWN_CMD_BT_COEX, basic, len, 0); 4274 if (error != 0) { 4275 aprint_error_dev(sc->sc_dev, 4276 "could not configure advanced bluetooth coexistence\n"); 4277 return error; 4278 } 4279 4280 error = iwn_config_bt_coex_prio_table(sc); 4281 if (error != 0) { 4282 aprint_error_dev(sc->sc_dev, 4283 "could not configure send BT priority table\n"); 4284 return error; 4285 } 4286 4287 /* Force BT state machine change */ 4288 memset(&btprot, 0, sizeof btprot); 4289 btprot.open = 1; 4290 btprot.type = 1; 4291 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4292 if (error != 0) { 4293 aprint_error_dev(sc->sc_dev, "could not open BT protcol\n"); 4294 return error; 4295 } 4296 4297 btprot.open = 0; 4298 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4299 if (error != 0) { 4300 aprint_error_dev(sc->sc_dev, "could not close BT protcol\n"); 4301 return error; 4302 } 4303 return 0; 4304 } 4305 4306 static int 4307 iwn_config_bt_coex_adv1(struct iwn_softc *sc) 4308 { 4309 struct iwn_bt_adv1 d; 4310 4311 memset(&d, 0, sizeof d); 4312 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4313 d.tx_prio_boost = 0; 4314 d.rx_prio_boost = 0; 4315 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4316 } 4317 4318 static int 4319 iwn_config_bt_coex_adv2(struct iwn_softc *sc) 4320 { 4321 struct iwn_bt_adv2 d; 4322 4323 memset(&d, 0, sizeof d); 4324 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4325 d.tx_prio_boost = 0; 4326 d.rx_prio_boost = 0; 4327 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4328 } 4329 4330 static int 4331 iwn_config(struct iwn_softc *sc) 4332 { 4333 struct iwn_ops *ops = &sc->ops; 4334 struct ieee80211com *ic = &sc->sc_ic; 4335 struct ifnet *ifp = ic->ic_ifp; 4336 uint32_t txmask; 4337 uint16_t rxchain; 4338 int error; 4339 4340 error = ops->config_bt_coex(sc); 4341 if (error != 0) { 4342 aprint_error_dev(sc->sc_dev, 4343 "could not configure bluetooth coexistence\n"); 4344 return error; 4345 } 4346 4347 /* Set radio temperature sensor offset. */ 4348 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4349 error = iwn6000_temp_offset_calib(sc); 4350 if (error != 0) { 4351 aprint_error_dev(sc->sc_dev, 4352 "could not set temperature offset\n"); 4353 return error; 4354 } 4355 } 4356 4357 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4358 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4359 sc->hw_type == IWN_HW_REV_TYPE_135 || 4360 sc->hw_type == IWN_HW_REV_TYPE_105) { 4361 error = iwn2000_temp_offset_calib(sc); 4362 if (error != 0) { 4363 aprint_error_dev(sc->sc_dev, 4364 "could not set temperature offset\n"); 4365 return error; 4366 } 4367 } 4368 4369 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4370 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4371 /* Configure runtime DC calibration. */ 4372 error = iwn5000_runtime_calib(sc); 4373 if (error != 0) { 4374 aprint_error_dev(sc->sc_dev, 4375 "could not configure runtime calibration\n"); 4376 return error; 4377 } 4378 } 4379 4380 /* Configure valid TX chains for 5000 Series. */ 4381 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4382 txmask = htole32(sc->txchainmask); 4383 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4384 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4385 sizeof txmask, 0); 4386 if (error != 0) { 4387 aprint_error_dev(sc->sc_dev, 4388 "could not configure valid TX chains\n"); 4389 return error; 4390 } 4391 } 4392 4393 /* Set mode, channel, RX filter and enable RX. */ 4394 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4395 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4396 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4397 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4398 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4399 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4400 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4401 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4402 switch (ic->ic_opmode) { 4403 case IEEE80211_M_STA: 4404 sc->rxon.mode = IWN_MODE_STA; 4405 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4406 break; 4407 case IEEE80211_M_MONITOR: 4408 sc->rxon.mode = IWN_MODE_MONITOR; 4409 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4410 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4411 break; 4412 default: 4413 /* Should not get there. */ 4414 break; 4415 } 4416 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4417 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4418 sc->rxon.ht_single_mask = 0xff; 4419 sc->rxon.ht_dual_mask = 0xff; 4420 sc->rxon.ht_triple_mask = 0xff; 4421 rxchain = 4422 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4423 IWN_RXCHAIN_MIMO_COUNT(2) | 4424 IWN_RXCHAIN_IDLE_COUNT(2); 4425 sc->rxon.rxchain = htole16(rxchain); 4426 DPRINTF(("setting configuration\n")); 4427 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4428 if (error != 0) { 4429 aprint_error_dev(sc->sc_dev, 4430 "RXON command failed\n"); 4431 return error; 4432 } 4433 4434 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4435 aprint_error_dev(sc->sc_dev, 4436 "could not add broadcast node\n"); 4437 return error; 4438 } 4439 4440 /* Configuration has changed, set TX power accordingly. */ 4441 if ((error = ops->set_txpower(sc, 0)) != 0) { 4442 aprint_error_dev(sc->sc_dev, 4443 "could not set TX power\n"); 4444 return error; 4445 } 4446 4447 if ((error = iwn_set_critical_temp(sc)) != 0) { 4448 aprint_error_dev(sc->sc_dev, 4449 "could not set critical temperature\n"); 4450 return error; 4451 } 4452 4453 /* Set power saving level to CAM during initialization. */ 4454 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4455 aprint_error_dev(sc->sc_dev, 4456 "could not set power saving level\n"); 4457 return error; 4458 } 4459 return 0; 4460 } 4461 4462 static uint16_t 4463 iwn_get_active_dwell_time(struct iwn_softc *sc, uint16_t flags, 4464 uint8_t n_probes) 4465 { 4466 /* No channel? Default to 2GHz settings */ 4467 if (flags & IEEE80211_CHAN_2GHZ) 4468 return IWN_ACTIVE_DWELL_TIME_2GHZ + 4469 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1); 4470 4471 /* 5GHz dwell time */ 4472 return IWN_ACTIVE_DWELL_TIME_5GHZ + 4473 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1); 4474 } 4475 4476 /* 4477 * Limit the total dwell time to 85% of the beacon interval. 4478 * 4479 * Returns the dwell time in milliseconds. 4480 */ 4481 static uint16_t 4482 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 4483 { 4484 struct ieee80211com *ic = &sc->sc_ic; 4485 struct ieee80211_node *ni = ic->ic_bss; 4486 int bintval = 0; 4487 4488 /* bintval is in TU (1.024mS) */ 4489 if (ni != NULL) 4490 bintval = ni->ni_intval; 4491 4492 /* 4493 * If it's non-zero, we should calculate the minimum of 4494 * it and the DWELL_BASE. 4495 * 4496 * XXX Yes, the math should take into account that bintval 4497 * is 1.024mS, not 1mS.. 4498 */ 4499 if (bintval > 0) 4500 return MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)); 4501 4502 /* No association context? Default */ 4503 return IWN_PASSIVE_DWELL_BASE; 4504 } 4505 4506 static uint16_t 4507 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 4508 { 4509 uint16_t passive; 4510 if (flags & IEEE80211_CHAN_2GHZ) 4511 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 4512 else 4513 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 4514 4515 /* Clamp to the beacon interval if we're associated */ 4516 return iwn_limit_dwell(sc, passive); 4517 } 4518 4519 static int 4520 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4521 { 4522 struct ieee80211com *ic = &sc->sc_ic; 4523 struct iwn_scan_hdr *hdr; 4524 struct iwn_cmd_data *tx; 4525 struct iwn_scan_essid *essid; 4526 struct iwn_scan_chan *chan; 4527 struct ieee80211_frame *wh; 4528 struct ieee80211_rateset *rs; 4529 struct ieee80211_channel *c; 4530 uint8_t *buf, *frm; 4531 uint16_t rxchain, dwell_active, dwell_passive; 4532 uint8_t txant; 4533 int buflen, error, is_active; 4534 4535 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4536 if (buf == NULL) { 4537 aprint_error_dev(sc->sc_dev, 4538 "could not allocate buffer for scan command\n"); 4539 return ENOMEM; 4540 } 4541 hdr = (struct iwn_scan_hdr *)buf; 4542 /* 4543 * Move to the next channel if no frames are received within 10ms 4544 * after sending the probe request. 4545 */ 4546 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4547 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4548 4549 /* Select antennas for scanning. */ 4550 rxchain = 4551 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4552 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4553 IWN_RXCHAIN_DRIVER_FORCE; 4554 if ((flags & IEEE80211_CHAN_5GHZ) && 4555 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4556 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4557 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4558 } else /* Use all available RX antennas. */ 4559 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4560 hdr->rxchain = htole16(rxchain); 4561 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4562 4563 tx = (struct iwn_cmd_data *)(hdr + 1); 4564 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4565 tx->id = sc->broadcast_id; 4566 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4567 4568 if (flags & IEEE80211_CHAN_5GHZ) { 4569 hdr->crc_threshold = 0xffff; 4570 /* Send probe requests at 6Mbps. */ 4571 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4572 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4573 } else { 4574 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4575 /* Send probe requests at 1Mbps. */ 4576 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4577 tx->rflags = IWN_RFLAG_CCK; 4578 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4579 } 4580 /* Use the first valid TX antenna. */ 4581 txant = IWN_LSB(sc->txchainmask); 4582 tx->rflags |= IWN_RFLAG_ANT(txant); 4583 4584 /* 4585 * Only do active scanning if we're announcing a probe request 4586 * for a given SSID (or more, if we ever add it to the driver.) 4587 */ 4588 is_active = 0; 4589 4590 essid = (struct iwn_scan_essid *)(tx + 1); 4591 if (ic->ic_des_esslen != 0) { 4592 essid[0].id = IEEE80211_ELEMID_SSID; 4593 essid[0].len = ic->ic_des_esslen; 4594 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4595 4596 is_active = 1; 4597 } 4598 /* 4599 * Build a probe request frame. Most of the following code is a 4600 * copy & paste of what is done in net80211. 4601 */ 4602 wh = (struct ieee80211_frame *)(essid + 20); 4603 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4604 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4605 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4606 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4607 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4608 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4609 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4610 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4611 4612 frm = (uint8_t *)(wh + 1); 4613 frm = ieee80211_add_ssid(frm, NULL, 0); 4614 frm = ieee80211_add_rates(frm, rs); 4615 #ifndef IEEE80211_NO_HT 4616 if (ic->ic_flags & IEEE80211_F_HTON) 4617 frm = ieee80211_add_htcaps(frm, ic); 4618 #endif 4619 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4620 frm = ieee80211_add_xrates(frm, rs); 4621 4622 /* Set length of probe request. */ 4623 tx->len = htole16(frm - (uint8_t *)wh); 4624 4625 4626 /* 4627 * If active scanning is requested but a certain channel is 4628 * marked passive, we can do active scanning if we detect 4629 * transmissions. 4630 * 4631 * There is an issue with some firmware versions that triggers 4632 * a sysassert on a "good CRC threshold" of zero (== disabled), 4633 * on a radar channel even though this means that we should NOT 4634 * send probes. 4635 * 4636 * The "good CRC threshold" is the number of frames that we 4637 * need to receive during our dwell time on a channel before 4638 * sending out probes -- setting this to a huge value will 4639 * mean we never reach it, but at the same time work around 4640 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 4641 * here instead of IWN_GOOD_CRC_TH_DISABLED. 4642 * 4643 * This was fixed in later versions along with some other 4644 * scan changes, and the threshold behaves as a flag in those 4645 * versions. 4646 */ 4647 4648 /* 4649 * If we're doing active scanning, set the crc_threshold 4650 * to a suitable value. This is different to active veruss 4651 * passive scanning depending upon the channel flags; the 4652 * firmware will obey that particular check for us. 4653 */ 4654 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 4655 hdr->crc_threshold = is_active ? 4656 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 4657 else 4658 hdr->crc_threshold = is_active ? 4659 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 4660 4661 chan = (struct iwn_scan_chan *)frm; 4662 for (c = &ic->ic_channels[1]; 4663 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4664 if ((c->ic_flags & flags) != flags) 4665 continue; 4666 4667 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4668 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4669 chan->flags = 0; 4670 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4671 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4672 if (ic->ic_des_esslen != 0) 4673 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4674 4675 /* 4676 * Calculate the active/passive dwell times. 4677 */ 4678 4679 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 4680 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 4681 4682 /* Make sure they're valid */ 4683 if (dwell_passive <= dwell_active) 4684 dwell_passive = dwell_active + 1; 4685 4686 chan->active = htole16(dwell_active); 4687 chan->passive = htole16(dwell_passive); 4688 4689 chan->dsp_gain = 0x6e; 4690 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4691 chan->rf_gain = 0x3b; 4692 } else { 4693 chan->rf_gain = 0x28; 4694 } 4695 hdr->nchan++; 4696 chan++; 4697 } 4698 4699 buflen = (uint8_t *)chan - buf; 4700 hdr->len = htole16(buflen); 4701 4702 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4703 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4704 free(buf, M_DEVBUF); 4705 return error; 4706 } 4707 4708 static int 4709 iwn_auth(struct iwn_softc *sc) 4710 { 4711 struct iwn_ops *ops = &sc->ops; 4712 struct ieee80211com *ic = &sc->sc_ic; 4713 struct ieee80211_node *ni = ic->ic_bss; 4714 int error; 4715 4716 /* Update adapter configuration. */ 4717 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4718 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4719 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4720 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4721 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4722 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4723 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4724 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4725 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4726 switch (ic->ic_curmode) { 4727 case IEEE80211_MODE_11A: 4728 sc->rxon.cck_mask = 0; 4729 sc->rxon.ofdm_mask = 0x15; 4730 break; 4731 case IEEE80211_MODE_11B: 4732 sc->rxon.cck_mask = 0x03; 4733 sc->rxon.ofdm_mask = 0; 4734 break; 4735 default: /* Assume 802.11b/g. */ 4736 sc->rxon.cck_mask = 0x0f; 4737 sc->rxon.ofdm_mask = 0x15; 4738 } 4739 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4740 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4741 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4742 if (error != 0) { 4743 aprint_error_dev(sc->sc_dev, 4744 "RXON command failed\n"); 4745 return error; 4746 } 4747 4748 /* Configuration has changed, set TX power accordingly. */ 4749 if ((error = ops->set_txpower(sc, 1)) != 0) { 4750 aprint_error_dev(sc->sc_dev, 4751 "could not set TX power\n"); 4752 return error; 4753 } 4754 /* 4755 * Reconfiguring RXON clears the firmware nodes table so we must 4756 * add the broadcast node again. 4757 */ 4758 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4759 aprint_error_dev(sc->sc_dev, 4760 "could not add broadcast node\n"); 4761 return error; 4762 } 4763 return 0; 4764 } 4765 4766 static int 4767 iwn_run(struct iwn_softc *sc) 4768 { 4769 struct iwn_ops *ops = &sc->ops; 4770 struct ieee80211com *ic = &sc->sc_ic; 4771 struct ieee80211_node *ni = ic->ic_bss; 4772 struct iwn_node_info node; 4773 int error; 4774 4775 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4776 /* Link LED blinks while monitoring. */ 4777 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4778 return 0; 4779 } 4780 if ((error = iwn_set_timing(sc, ni)) != 0) { 4781 aprint_error_dev(sc->sc_dev, 4782 "could not set timing\n"); 4783 return error; 4784 } 4785 4786 /* Update adapter configuration. */ 4787 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4788 /* Short preamble and slot time are negotiated when associating. */ 4789 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4790 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4791 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4792 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4793 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4794 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4795 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4796 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4797 if (error != 0) { 4798 aprint_error_dev(sc->sc_dev, 4799 "could not update configuration\n"); 4800 return error; 4801 } 4802 4803 /* Configuration has changed, set TX power accordingly. */ 4804 if ((error = ops->set_txpower(sc, 1)) != 0) { 4805 aprint_error_dev(sc->sc_dev, 4806 "could not set TX power\n"); 4807 return error; 4808 } 4809 4810 /* Fake a join to initialize the TX rate. */ 4811 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4812 iwn_newassoc(ni, 1); 4813 4814 /* Add BSS node. */ 4815 memset(&node, 0, sizeof node); 4816 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4817 node.id = IWN_ID_BSS; 4818 #ifdef notyet 4819 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4820 IWN_AMDPU_DENSITY(5)); /* 2us */ 4821 #endif 4822 DPRINTF(("adding BSS node\n")); 4823 error = ops->add_node(sc, &node, 1); 4824 if (error != 0) { 4825 aprint_error_dev(sc->sc_dev, 4826 "could not add BSS node\n"); 4827 return error; 4828 } 4829 DPRINTF(("setting link quality for node %d\n", node.id)); 4830 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4831 aprint_error_dev(sc->sc_dev, 4832 "could not setup link quality for node %d\n", node.id); 4833 return error; 4834 } 4835 4836 if ((error = iwn_init_sensitivity(sc)) != 0) { 4837 aprint_error_dev(sc->sc_dev, 4838 "could not set sensitivity\n"); 4839 return error; 4840 } 4841 /* Start periodic calibration timer. */ 4842 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4843 sc->calib_cnt = 0; 4844 callout_schedule(&sc->calib_to, hz/2); 4845 4846 /* Link LED always on while associated. */ 4847 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4848 return 0; 4849 } 4850 4851 #ifdef IWN_HWCRYPTO 4852 /* 4853 * We support CCMP hardware encryption/decryption of unicast frames only. 4854 * HW support for TKIP really sucks. We should let TKIP die anyway. 4855 */ 4856 static int 4857 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4858 struct ieee80211_key *k) 4859 { 4860 struct iwn_softc *sc = ic->ic_softc; 4861 struct iwn_ops *ops = &sc->ops; 4862 struct iwn_node *wn = (void *)ni; 4863 struct iwn_node_info node; 4864 uint16_t kflags; 4865 4866 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4867 k->k_cipher != IEEE80211_CIPHER_CCMP) 4868 return ieee80211_set_key(ic, ni, k); 4869 4870 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4871 if (k->k_flags & IEEE80211_KEY_GROUP) 4872 kflags |= IWN_KFLAG_GROUP; 4873 4874 memset(&node, 0, sizeof node); 4875 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4876 sc->broadcast_id : wn->id; 4877 node.control = IWN_NODE_UPDATE; 4878 node.flags = IWN_FLAG_SET_KEY; 4879 node.kflags = htole16(kflags); 4880 node.kid = k->k_id; 4881 memcpy(node.key, k->k_key, k->k_len); 4882 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4883 return ops->add_node(sc, &node, 1); 4884 } 4885 4886 static void 4887 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4888 struct ieee80211_key *k) 4889 { 4890 struct iwn_softc *sc = ic->ic_softc; 4891 struct iwn_ops *ops = &sc->ops; 4892 struct iwn_node *wn = (void *)ni; 4893 struct iwn_node_info node; 4894 4895 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4896 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4897 /* See comment about other ciphers above. */ 4898 ieee80211_delete_key(ic, ni, k); 4899 return; 4900 } 4901 if (ic->ic_state != IEEE80211_S_RUN) 4902 return; /* Nothing to do. */ 4903 memset(&node, 0, sizeof node); 4904 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4905 sc->broadcast_id : wn->id; 4906 node.control = IWN_NODE_UPDATE; 4907 node.flags = IWN_FLAG_SET_KEY; 4908 node.kflags = htole16(IWN_KFLAG_INVALID); 4909 node.kid = 0xff; 4910 DPRINTF(("delete keys for node %d\n", node.id)); 4911 (void)ops->add_node(sc, &node, 1); 4912 } 4913 #endif 4914 4915 /* XXX Added for NetBSD (copied from rev 1.39). */ 4916 4917 static int 4918 iwn_wme_update(struct ieee80211com *ic) 4919 { 4920 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4921 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4922 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4923 const struct wmeParams *wmep; 4924 struct iwn_edca_params cmd; 4925 int ac; 4926 4927 /* don't override default WME values if WME is not actually enabled */ 4928 if (!(ic->ic_flags & IEEE80211_F_WME)) 4929 return 0; 4930 cmd.flags = 0; 4931 for (ac = 0; ac < WME_NUM_AC; ac++) { 4932 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4933 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4934 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4935 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4936 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4937 4938 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4939 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4940 cmd.ac[ac].cwmin, 4941 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4942 } 4943 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4944 #undef IWN_USEC 4945 #undef IWN_EXP2 4946 } 4947 4948 #ifndef IEEE80211_NO_HT 4949 /* 4950 * This function is called by upper layer when an ADDBA request is received 4951 * from another STA and before the ADDBA response is sent. 4952 */ 4953 static int 4954 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4955 uint8_t tid) 4956 { 4957 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4958 struct iwn_softc *sc = ic->ic_softc; 4959 struct iwn_ops *ops = &sc->ops; 4960 struct iwn_node *wn = (void *)ni; 4961 struct iwn_node_info node; 4962 4963 memset(&node, 0, sizeof node); 4964 node.id = wn->id; 4965 node.control = IWN_NODE_UPDATE; 4966 node.flags = IWN_FLAG_SET_ADDBA; 4967 node.addba_tid = tid; 4968 node.addba_ssn = htole16(ba->ba_winstart); 4969 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4970 ba->ba_winstart)); 4971 return ops->add_node(sc, &node, 1); 4972 } 4973 4974 /* 4975 * This function is called by upper layer on teardown of an HT-immediate 4976 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4977 */ 4978 static void 4979 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4980 uint8_t tid) 4981 { 4982 struct iwn_softc *sc = ic->ic_softc; 4983 struct iwn_ops *ops = &sc->ops; 4984 struct iwn_node *wn = (void *)ni; 4985 struct iwn_node_info node; 4986 4987 memset(&node, 0, sizeof node); 4988 node.id = wn->id; 4989 node.control = IWN_NODE_UPDATE; 4990 node.flags = IWN_FLAG_SET_DELBA; 4991 node.delba_tid = tid; 4992 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4993 (void)ops->add_node(sc, &node, 1); 4994 } 4995 4996 /* 4997 * This function is called by upper layer when an ADDBA response is received 4998 * from another STA. 4999 */ 5000 static int 5001 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5002 uint8_t tid) 5003 { 5004 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5005 struct iwn_softc *sc = ic->ic_softc; 5006 struct iwn_ops *ops = &sc->ops; 5007 struct iwn_node *wn = (void *)ni; 5008 struct iwn_node_info node; 5009 int error; 5010 5011 /* Enable TX for the specified RA/TID. */ 5012 wn->disable_tid &= ~(1 << tid); 5013 memset(&node, 0, sizeof node); 5014 node.id = wn->id; 5015 node.control = IWN_NODE_UPDATE; 5016 node.flags = IWN_FLAG_SET_DISABLE_TID; 5017 node.disable_tid = htole16(wn->disable_tid); 5018 error = ops->add_node(sc, &node, 1); 5019 if (error != 0) 5020 return error; 5021 5022 if ((error = iwn_nic_lock(sc)) != 0) 5023 return error; 5024 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5025 iwn_nic_unlock(sc); 5026 return 0; 5027 } 5028 5029 static void 5030 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5031 uint8_t tid) 5032 { 5033 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5034 struct iwn_softc *sc = ic->ic_softc; 5035 struct iwn_ops *ops = &sc->ops; 5036 5037 if (iwn_nic_lock(sc) != 0) 5038 return; 5039 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5040 iwn_nic_unlock(sc); 5041 } 5042 5043 static void 5044 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5045 uint8_t tid, uint16_t ssn) 5046 { 5047 struct iwn_node *wn = (void *)ni; 5048 int qid = 7 + tid; 5049 5050 /* Stop TX scheduler while we're changing its configuration. */ 5051 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5052 IWN4965_TXQ_STATUS_CHGACT); 5053 5054 /* Assign RA/TID translation to the queue. */ 5055 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5056 wn->id << 4 | tid); 5057 5058 /* Enable chain-building mode for the queue. */ 5059 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5060 5061 /* Set starting sequence number from the ADDBA request. */ 5062 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5063 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5064 5065 /* Set scheduler window size. */ 5066 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5067 IWN_SCHED_WINSZ); 5068 /* Set scheduler frame limit. */ 5069 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5070 IWN_SCHED_LIMIT << 16); 5071 5072 /* Enable interrupts for the queue. */ 5073 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5074 5075 /* Mark the queue as active. */ 5076 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5077 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5078 iwn_tid2fifo[tid] << 1); 5079 } 5080 5081 static void 5082 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5083 { 5084 int qid = 7 + tid; 5085 5086 /* Stop TX scheduler while we're changing its configuration. */ 5087 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5088 IWN4965_TXQ_STATUS_CHGACT); 5089 5090 /* Set starting sequence number from the ADDBA request. */ 5091 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5092 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5093 5094 /* Disable interrupts for the queue. */ 5095 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5096 5097 /* Mark the queue as inactive. */ 5098 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5099 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5100 } 5101 5102 static void 5103 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5104 uint8_t tid, uint16_t ssn) 5105 { 5106 struct iwn_node *wn = (void *)ni; 5107 int qid = 10 + tid; 5108 5109 /* Stop TX scheduler while we're changing its configuration. */ 5110 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5111 IWN5000_TXQ_STATUS_CHGACT); 5112 5113 /* Assign RA/TID translation to the queue. */ 5114 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5115 wn->id << 4 | tid); 5116 5117 /* Enable chain-building mode for the queue. */ 5118 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5119 5120 /* Enable aggregation for the queue. */ 5121 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5122 5123 /* Set starting sequence number from the ADDBA request. */ 5124 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5125 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5126 5127 /* Set scheduler window size and frame limit. */ 5128 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5129 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5130 5131 /* Enable interrupts for the queue. */ 5132 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5133 5134 /* Mark the queue as active. */ 5135 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5136 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5137 } 5138 5139 static void 5140 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5141 { 5142 int qid = 10 + tid; 5143 5144 /* Stop TX scheduler while we're changing its configuration. */ 5145 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5146 IWN5000_TXQ_STATUS_CHGACT); 5147 5148 /* Disable aggregation for the queue. */ 5149 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5150 5151 /* Set starting sequence number from the ADDBA request. */ 5152 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5153 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5154 5155 /* Disable interrupts for the queue. */ 5156 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5157 5158 /* Mark the queue as inactive. */ 5159 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5160 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5161 } 5162 #endif /* !IEEE80211_NO_HT */ 5163 5164 /* 5165 * Query calibration tables from the initialization firmware. We do this 5166 * only once at first boot. Called from a process context. 5167 */ 5168 static int 5169 iwn5000_query_calibration(struct iwn_softc *sc) 5170 { 5171 struct iwn5000_calib_config cmd; 5172 int error; 5173 5174 memset(&cmd, 0, sizeof cmd); 5175 cmd.ucode.once.enable = 0xffffffff; 5176 cmd.ucode.once.start = 0xffffffff; 5177 cmd.ucode.once.send = 0xffffffff; 5178 cmd.ucode.flags = 0xffffffff; 5179 DPRINTF(("sending calibration query\n")); 5180 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5181 if (error != 0) 5182 return error; 5183 5184 /* Wait at most two seconds for calibration to complete. */ 5185 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5186 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 5187 return error; 5188 } 5189 5190 /* 5191 * Send calibration results to the runtime firmware. These results were 5192 * obtained on first boot from the initialization firmware. 5193 */ 5194 static int 5195 iwn5000_send_calibration(struct iwn_softc *sc) 5196 { 5197 int idx, error; 5198 5199 for (idx = 0; idx < 5; idx++) { 5200 if (sc->calibcmd[idx].buf == NULL) 5201 continue; /* No results available. */ 5202 DPRINTF(("send calibration result idx=%d len=%d\n", 5203 idx, sc->calibcmd[idx].len)); 5204 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5205 sc->calibcmd[idx].len, 0); 5206 if (error != 0) { 5207 aprint_error_dev(sc->sc_dev, 5208 "could not send calibration result\n"); 5209 return error; 5210 } 5211 } 5212 return 0; 5213 } 5214 5215 static int 5216 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5217 { 5218 struct iwn5000_wimax_coex wimax; 5219 5220 #ifdef notyet 5221 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5222 /* Enable WiMAX coexistence for combo adapters. */ 5223 wimax.flags = 5224 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5225 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5226 IWN_WIMAX_COEX_STA_TABLE_VALID | 5227 IWN_WIMAX_COEX_ENABLE; 5228 memcpy(wimax.events, iwn6050_wimax_events, 5229 sizeof iwn6050_wimax_events); 5230 } else 5231 #endif 5232 { 5233 /* Disable WiMAX coexistence. */ 5234 wimax.flags = 0; 5235 memset(wimax.events, 0, sizeof wimax.events); 5236 } 5237 DPRINTF(("Configuring WiMAX coexistence\n")); 5238 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5239 } 5240 5241 static int 5242 iwn6000_temp_offset_calib(struct iwn_softc *sc) 5243 { 5244 struct iwn6000_phy_calib_temp_offset cmd; 5245 5246 memset(&cmd, 0, sizeof cmd); 5247 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 5248 cmd.ngroups = 1; 5249 cmd.isvalid = 1; 5250 if (sc->eeprom_temp != 0) 5251 cmd.offset = htole16(sc->eeprom_temp); 5252 else 5253 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5254 DPRINTF(("setting radio sensor offset to %d\n", le16toh(cmd.offset))); 5255 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5256 } 5257 5258 static int 5259 iwn2000_temp_offset_calib(struct iwn_softc *sc) 5260 { 5261 struct iwn2000_phy_calib_temp_offset cmd; 5262 5263 memset(&cmd, 0, sizeof cmd); 5264 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 5265 cmd.ngroups = 1; 5266 cmd.isvalid = 1; 5267 if (sc->eeprom_rawtemp != 0) { 5268 cmd.offset_low = htole16(sc->eeprom_rawtemp); 5269 cmd.offset_high = htole16(sc->eeprom_temp); 5270 } else { 5271 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 5272 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 5273 } 5274 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 5275 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 5276 le16toh(cmd.offset_low), le16toh(cmd.offset_high), 5277 le16toh(cmd.burnt_voltage_ref))); 5278 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5279 } 5280 5281 /* 5282 * This function is called after the runtime firmware notifies us of its 5283 * readiness (called in a process context). 5284 */ 5285 static int 5286 iwn4965_post_alive(struct iwn_softc *sc) 5287 { 5288 int error, qid; 5289 5290 if ((error = iwn_nic_lock(sc)) != 0) 5291 return error; 5292 5293 /* Clear TX scheduler state in SRAM. */ 5294 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5295 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5296 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5297 5298 /* Set physical address of TX scheduler rings (1KB aligned). */ 5299 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5300 5301 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5302 5303 /* Disable chain mode for all our 16 queues. */ 5304 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5305 5306 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5307 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5308 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5309 5310 /* Set scheduler window size. */ 5311 iwn_mem_write(sc, sc->sched_base + 5312 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5313 /* Set scheduler frame limit. */ 5314 iwn_mem_write(sc, sc->sched_base + 5315 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5316 IWN_SCHED_LIMIT << 16); 5317 } 5318 5319 /* Enable interrupts for all our 16 queues. */ 5320 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5321 /* Identify TX FIFO rings (0-7). */ 5322 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5323 5324 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5325 for (qid = 0; qid < 7; qid++) { 5326 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5327 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5328 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5329 } 5330 iwn_nic_unlock(sc); 5331 return 0; 5332 } 5333 5334 /* 5335 * This function is called after the initialization or runtime firmware 5336 * notifies us of its readiness (called in a process context). 5337 */ 5338 static int 5339 iwn5000_post_alive(struct iwn_softc *sc) 5340 { 5341 int error, qid; 5342 5343 /* Switch to using ICT interrupt mode. */ 5344 iwn5000_ict_reset(sc); 5345 5346 if ((error = iwn_nic_lock(sc)) != 0) 5347 return error; 5348 5349 /* Clear TX scheduler state in SRAM. */ 5350 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5351 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5352 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5353 5354 /* Set physical address of TX scheduler rings (1KB aligned). */ 5355 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5356 5357 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5358 5359 /* Enable chain mode for all queues, except command queue. */ 5360 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5361 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5362 5363 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5364 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5365 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5366 5367 iwn_mem_write(sc, sc->sched_base + 5368 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5369 /* Set scheduler window size and frame limit. */ 5370 iwn_mem_write(sc, sc->sched_base + 5371 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5372 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5373 } 5374 5375 /* Enable interrupts for all our 20 queues. */ 5376 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5377 /* Identify TX FIFO rings (0-7). */ 5378 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5379 5380 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5381 for (qid = 0; qid < 7; qid++) { 5382 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5383 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5384 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5385 } 5386 iwn_nic_unlock(sc); 5387 5388 /* Configure WiMAX coexistence for combo adapters. */ 5389 error = iwn5000_send_wimax_coex(sc); 5390 if (error != 0) { 5391 aprint_error_dev(sc->sc_dev, 5392 "could not configure WiMAX coexistence\n"); 5393 return error; 5394 } 5395 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5396 struct iwn5000_phy_calib_crystal cmd; 5397 5398 /* Perform crystal calibration. */ 5399 memset(&cmd, 0, sizeof cmd); 5400 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5401 cmd.ngroups = 1; 5402 cmd.isvalid = 1; 5403 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5404 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5405 DPRINTF(("sending crystal calibration %d, %d\n", 5406 cmd.cap_pin[0], cmd.cap_pin[1])); 5407 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5408 if (error != 0) { 5409 aprint_error_dev(sc->sc_dev, 5410 "crystal calibration failed\n"); 5411 return error; 5412 } 5413 } 5414 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5415 /* Query calibration from the initialization firmware. */ 5416 if ((error = iwn5000_query_calibration(sc)) != 0) { 5417 aprint_error_dev(sc->sc_dev, 5418 "could not query calibration\n"); 5419 return error; 5420 } 5421 /* 5422 * We have the calibration results now, reboot with the 5423 * runtime firmware (call ourselves recursively!) 5424 */ 5425 iwn_hw_stop(sc); 5426 error = iwn_hw_init(sc); 5427 } else { 5428 /* Send calibration results to runtime firmware. */ 5429 error = iwn5000_send_calibration(sc); 5430 } 5431 return error; 5432 } 5433 5434 /* 5435 * The firmware boot code is small and is intended to be copied directly into 5436 * the NIC internal memory (no DMA transfer). 5437 */ 5438 static int 5439 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5440 { 5441 int error, ntries; 5442 5443 size /= sizeof (uint32_t); 5444 5445 if ((error = iwn_nic_lock(sc)) != 0) 5446 return error; 5447 5448 /* Copy microcode image into NIC memory. */ 5449 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5450 (const uint32_t *)ucode, size); 5451 5452 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5453 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5454 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5455 5456 /* Start boot load now. */ 5457 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5458 5459 /* Wait for transfer to complete. */ 5460 for (ntries = 0; ntries < 1000; ntries++) { 5461 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5462 IWN_BSM_WR_CTRL_START)) 5463 break; 5464 DELAY(10); 5465 } 5466 if (ntries == 1000) { 5467 aprint_error_dev(sc->sc_dev, 5468 "could not load boot firmware\n"); 5469 iwn_nic_unlock(sc); 5470 return ETIMEDOUT; 5471 } 5472 5473 /* Enable boot after power up. */ 5474 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5475 5476 iwn_nic_unlock(sc); 5477 return 0; 5478 } 5479 5480 static int 5481 iwn4965_load_firmware(struct iwn_softc *sc) 5482 { 5483 struct iwn_fw_info *fw = &sc->fw; 5484 struct iwn_dma_info *dma = &sc->fw_dma; 5485 int error; 5486 5487 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5488 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5489 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5490 BUS_DMASYNC_PREWRITE); 5491 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5492 fw->init.text, fw->init.textsz); 5493 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5494 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5495 5496 /* Tell adapter where to find initialization sections. */ 5497 if ((error = iwn_nic_lock(sc)) != 0) 5498 return error; 5499 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5500 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5501 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5502 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5503 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5504 iwn_nic_unlock(sc); 5505 5506 /* Load firmware boot code. */ 5507 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5508 if (error != 0) { 5509 aprint_error_dev(sc->sc_dev, 5510 "could not load boot firmware\n"); 5511 return error; 5512 } 5513 /* Now press "execute". */ 5514 IWN_WRITE(sc, IWN_RESET, 0); 5515 5516 /* Wait at most one second for first alive notification. */ 5517 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5518 aprint_error_dev(sc->sc_dev, 5519 "timeout waiting for adapter to initialize\n"); 5520 return error; 5521 } 5522 5523 /* Retrieve current temperature for initial TX power calibration. */ 5524 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5525 sc->temp = iwn4965_get_temperature(sc); 5526 5527 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5528 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5529 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5530 BUS_DMASYNC_PREWRITE); 5531 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5532 fw->main.text, fw->main.textsz); 5533 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5534 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5535 5536 /* Tell adapter where to find runtime sections. */ 5537 if ((error = iwn_nic_lock(sc)) != 0) 5538 return error; 5539 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5540 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5541 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5542 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5543 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5544 IWN_FW_UPDATED | fw->main.textsz); 5545 iwn_nic_unlock(sc); 5546 5547 return 0; 5548 } 5549 5550 static int 5551 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5552 const uint8_t *section, int size) 5553 { 5554 struct iwn_dma_info *dma = &sc->fw_dma; 5555 int error; 5556 5557 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5558 memcpy(dma->vaddr, section, size); 5559 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5560 5561 if ((error = iwn_nic_lock(sc)) != 0) 5562 return error; 5563 5564 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5565 IWN_FH_TX_CONFIG_DMA_PAUSE); 5566 5567 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5568 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5569 IWN_LOADDR(dma->paddr)); 5570 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5571 IWN_HIADDR(dma->paddr) << 28 | size); 5572 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5573 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5574 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5575 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5576 5577 /* Kick Flow Handler to start DMA transfer. */ 5578 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5579 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5580 5581 iwn_nic_unlock(sc); 5582 5583 /* Wait at most five seconds for FH DMA transfer to complete. */ 5584 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5585 } 5586 5587 static int 5588 iwn5000_load_firmware(struct iwn_softc *sc) 5589 { 5590 struct iwn_fw_part *fw; 5591 int error; 5592 5593 /* Load the initialization firmware on first boot only. */ 5594 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5595 &sc->fw.main : &sc->fw.init; 5596 5597 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5598 fw->text, fw->textsz); 5599 if (error != 0) { 5600 aprint_error_dev(sc->sc_dev, 5601 "could not load firmware %s section\n", ".text"); 5602 return error; 5603 } 5604 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5605 fw->data, fw->datasz); 5606 if (error != 0) { 5607 aprint_error_dev(sc->sc_dev, 5608 "could not load firmware %s section\n", ".data"); 5609 return error; 5610 } 5611 5612 /* Now press "execute". */ 5613 IWN_WRITE(sc, IWN_RESET, 0); 5614 return 0; 5615 } 5616 5617 /* 5618 * Extract text and data sections from a legacy firmware image. 5619 */ 5620 static int 5621 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5622 { 5623 const uint32_t *ptr; 5624 size_t hdrlen = 24; 5625 uint32_t rev; 5626 5627 ptr = (const uint32_t *)fw->data; 5628 rev = le32toh(*ptr++); 5629 5630 /* Check firmware API version. */ 5631 if (IWN_FW_API(rev) <= 1) { 5632 aprint_error_dev(sc->sc_dev, 5633 "bad firmware, need API version >=2\n"); 5634 return EINVAL; 5635 } 5636 if (IWN_FW_API(rev) >= 3) { 5637 /* Skip build number (version 2 header). */ 5638 hdrlen += 4; 5639 ptr++; 5640 } 5641 if (fw->size < hdrlen) { 5642 aprint_error_dev(sc->sc_dev, 5643 "firmware too short: %zd bytes\n", fw->size); 5644 return EINVAL; 5645 } 5646 fw->main.textsz = le32toh(*ptr++); 5647 fw->main.datasz = le32toh(*ptr++); 5648 fw->init.textsz = le32toh(*ptr++); 5649 fw->init.datasz = le32toh(*ptr++); 5650 fw->boot.textsz = le32toh(*ptr++); 5651 5652 /* Check that all firmware sections fit. */ 5653 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5654 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5655 aprint_error_dev(sc->sc_dev, 5656 "firmware too short: %zd bytes\n", fw->size); 5657 return EINVAL; 5658 } 5659 5660 /* Get pointers to firmware sections. */ 5661 fw->main.text = (const uint8_t *)ptr; 5662 fw->main.data = fw->main.text + fw->main.textsz; 5663 fw->init.text = fw->main.data + fw->main.datasz; 5664 fw->init.data = fw->init.text + fw->init.textsz; 5665 fw->boot.text = fw->init.data + fw->init.datasz; 5666 return 0; 5667 } 5668 5669 /* 5670 * Extract text and data sections from a TLV firmware image. 5671 */ 5672 static int 5673 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5674 uint16_t alt) 5675 { 5676 const struct iwn_fw_tlv_hdr *hdr; 5677 const struct iwn_fw_tlv *tlv; 5678 const uint8_t *ptr, *end; 5679 uint64_t altmask; 5680 uint32_t len; 5681 5682 if (fw->size < sizeof (*hdr)) { 5683 aprint_error_dev(sc->sc_dev, 5684 "firmware too short: %zd bytes\n", fw->size); 5685 return EINVAL; 5686 } 5687 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5688 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5689 aprint_error_dev(sc->sc_dev, 5690 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5691 return EINVAL; 5692 } 5693 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5694 le32toh(hdr->build))); 5695 5696 /* 5697 * Select the closest supported alternative that is less than 5698 * or equal to the specified one. 5699 */ 5700 altmask = le64toh(hdr->altmask); 5701 while (alt > 0 && !(altmask & (1ULL << alt))) 5702 alt--; /* Downgrade. */ 5703 DPRINTF(("using alternative %d\n", alt)); 5704 5705 ptr = (const uint8_t *)(hdr + 1); 5706 end = (const uint8_t *)(fw->data + fw->size); 5707 5708 /* Parse type-length-value fields. */ 5709 while (ptr + sizeof (*tlv) <= end) { 5710 tlv = (const struct iwn_fw_tlv *)ptr; 5711 len = le32toh(tlv->len); 5712 5713 ptr += sizeof (*tlv); 5714 if (ptr + len > end) { 5715 aprint_error_dev(sc->sc_dev, 5716 "firmware too short: %zd bytes\n", fw->size); 5717 return EINVAL; 5718 } 5719 /* Skip other alternatives. */ 5720 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5721 goto next; 5722 5723 switch (le16toh(tlv->type)) { 5724 case IWN_FW_TLV_MAIN_TEXT: 5725 fw->main.text = ptr; 5726 fw->main.textsz = len; 5727 break; 5728 case IWN_FW_TLV_MAIN_DATA: 5729 fw->main.data = ptr; 5730 fw->main.datasz = len; 5731 break; 5732 case IWN_FW_TLV_INIT_TEXT: 5733 fw->init.text = ptr; 5734 fw->init.textsz = len; 5735 break; 5736 case IWN_FW_TLV_INIT_DATA: 5737 fw->init.data = ptr; 5738 fw->init.datasz = len; 5739 break; 5740 case IWN_FW_TLV_BOOT_TEXT: 5741 fw->boot.text = ptr; 5742 fw->boot.textsz = len; 5743 break; 5744 case IWN_FW_TLV_ENH_SENS: 5745 if (len != 0) { 5746 aprint_error_dev(sc->sc_dev, 5747 "TLV type %d has invalid size %u\n", 5748 le16toh(tlv->type), len); 5749 goto next; 5750 } 5751 sc->sc_flags |= IWN_FLAG_ENH_SENS; 5752 break; 5753 case IWN_FW_TLV_PHY_CALIB: 5754 if (len != sizeof(uint32_t)) { 5755 aprint_error_dev(sc->sc_dev, 5756 "TLV type %d has invalid size %u\n", 5757 le16toh(tlv->type), len); 5758 goto next; 5759 } 5760 if (le32toh(*ptr) <= IWN5000_PHY_CALIB_MAX) { 5761 sc->reset_noise_gain = le32toh(*ptr); 5762 sc->noise_gain = le32toh(*ptr) + 1; 5763 } 5764 break; 5765 case IWN_FW_TLV_FLAGS: 5766 if (len < sizeof(uint32_t)) 5767 break; 5768 if (len % sizeof(uint32_t)) 5769 break; 5770 sc->tlv_feature_flags = le32toh(*ptr); 5771 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 5772 break; 5773 default: 5774 DPRINTF(("TLV type %d not handled\n", 5775 le16toh(tlv->type))); 5776 break; 5777 } 5778 next: /* TLV fields are 32-bit aligned. */ 5779 ptr += (len + 3) & ~3; 5780 } 5781 return 0; 5782 } 5783 5784 static int 5785 iwn_read_firmware(struct iwn_softc *sc) 5786 { 5787 struct iwn_fw_info *fw = &sc->fw; 5788 firmware_handle_t fwh; 5789 int error; 5790 5791 /* 5792 * Some PHY calibration commands are firmware-dependent; these 5793 * are the default values that will be overridden if 5794 * necessary. 5795 */ 5796 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 5797 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 5798 5799 /* Initialize for error returns */ 5800 fw->data = NULL; 5801 fw->size = 0; 5802 5803 /* Open firmware image. */ 5804 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5805 aprint_error_dev(sc->sc_dev, 5806 "could not get firmware handle %s\n", sc->fwname); 5807 return error; 5808 } 5809 fw->size = firmware_get_size(fwh); 5810 if (fw->size < sizeof (uint32_t)) { 5811 aprint_error_dev(sc->sc_dev, 5812 "firmware too short: %zd bytes\n", fw->size); 5813 firmware_close(fwh); 5814 return EINVAL; 5815 } 5816 5817 /* Read the firmware. */ 5818 fw->data = firmware_malloc(fw->size); 5819 if (fw->data == NULL) { 5820 aprint_error_dev(sc->sc_dev, 5821 "not enough memory to stock firmware %s\n", sc->fwname); 5822 firmware_close(fwh); 5823 return ENOMEM; 5824 } 5825 error = firmware_read(fwh, 0, fw->data, fw->size); 5826 firmware_close(fwh); 5827 if (error != 0) { 5828 aprint_error_dev(sc->sc_dev, 5829 "could not read firmware %s\n", sc->fwname); 5830 goto out; 5831 } 5832 5833 /* Retrieve text and data sections. */ 5834 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5835 error = iwn_read_firmware_leg(sc, fw); 5836 else 5837 error = iwn_read_firmware_tlv(sc, fw, 1); 5838 if (error != 0) { 5839 aprint_error_dev(sc->sc_dev, 5840 "could not read firmware sections\n"); 5841 goto out; 5842 } 5843 5844 /* Make sure text and data sections fit in hardware memory. */ 5845 if (fw->main.textsz > sc->fw_text_maxsz || 5846 fw->main.datasz > sc->fw_data_maxsz || 5847 fw->init.textsz > sc->fw_text_maxsz || 5848 fw->init.datasz > sc->fw_data_maxsz || 5849 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5850 (fw->boot.textsz & 3) != 0) { 5851 aprint_error_dev(sc->sc_dev, 5852 "firmware sections too large\n"); 5853 goto out; 5854 } 5855 5856 /* We can proceed with loading the firmware. */ 5857 return 0; 5858 out: 5859 firmware_free(fw->data, fw->size); 5860 fw->data = NULL; 5861 fw->size = 0; 5862 return error ? error : EINVAL; 5863 } 5864 5865 static int 5866 iwn_clock_wait(struct iwn_softc *sc) 5867 { 5868 int ntries; 5869 5870 /* Set "initialization complete" bit. */ 5871 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5872 5873 /* Wait for clock stabilization. */ 5874 for (ntries = 0; ntries < 2500; ntries++) { 5875 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5876 return 0; 5877 DELAY(10); 5878 } 5879 aprint_error_dev(sc->sc_dev, 5880 "timeout waiting for clock stabilization\n"); 5881 return ETIMEDOUT; 5882 } 5883 5884 static int 5885 iwn_apm_init(struct iwn_softc *sc) 5886 { 5887 pcireg_t reg; 5888 int error; 5889 5890 /* Disable L0s exit timer (NMI bug workaround). */ 5891 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5892 /* Don't wait for ICH L0s (ICH bug workaround). */ 5893 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5894 5895 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5896 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5897 5898 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5899 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5900 5901 /* Retrieve PCIe Active State Power Management (ASPM). */ 5902 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5903 sc->sc_cap_off + PCIE_LCSR); 5904 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5905 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5906 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5907 else 5908 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5909 5910 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5911 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5912 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5913 5914 /* Wait for clock stabilization before accessing prph. */ 5915 if ((error = iwn_clock_wait(sc)) != 0) 5916 return error; 5917 5918 if ((error = iwn_nic_lock(sc)) != 0) 5919 return error; 5920 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5921 /* Enable DMA and BSM (Bootstrap State Machine). */ 5922 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5923 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5924 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5925 } else { 5926 /* Enable DMA. */ 5927 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5928 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5929 } 5930 DELAY(20); 5931 /* Disable L1-Active. */ 5932 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5933 iwn_nic_unlock(sc); 5934 5935 return 0; 5936 } 5937 5938 static void 5939 iwn_apm_stop_master(struct iwn_softc *sc) 5940 { 5941 int ntries; 5942 5943 /* Stop busmaster DMA activity. */ 5944 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5945 for (ntries = 0; ntries < 100; ntries++) { 5946 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5947 return; 5948 DELAY(10); 5949 } 5950 aprint_error_dev(sc->sc_dev, 5951 "timeout waiting for master\n"); 5952 } 5953 5954 static void 5955 iwn_apm_stop(struct iwn_softc *sc) 5956 { 5957 iwn_apm_stop_master(sc); 5958 5959 /* Reset the entire device. */ 5960 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5961 DELAY(10); 5962 /* Clear "initialization complete" bit. */ 5963 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5964 } 5965 5966 static int 5967 iwn4965_nic_config(struct iwn_softc *sc) 5968 { 5969 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5970 /* 5971 * I don't believe this to be correct but this is what the 5972 * vendor driver is doing. Probably the bits should not be 5973 * shifted in IWN_RFCFG_*. 5974 */ 5975 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5976 IWN_RFCFG_TYPE(sc->rfcfg) | 5977 IWN_RFCFG_STEP(sc->rfcfg) | 5978 IWN_RFCFG_DASH(sc->rfcfg)); 5979 } 5980 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5981 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5982 return 0; 5983 } 5984 5985 static int 5986 iwn5000_nic_config(struct iwn_softc *sc) 5987 { 5988 uint32_t tmp; 5989 int error; 5990 5991 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5992 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5993 IWN_RFCFG_TYPE(sc->rfcfg) | 5994 IWN_RFCFG_STEP(sc->rfcfg) | 5995 IWN_RFCFG_DASH(sc->rfcfg)); 5996 } 5997 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5998 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5999 6000 if ((error = iwn_nic_lock(sc)) != 0) 6001 return error; 6002 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6003 6004 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6005 /* 6006 * Select first Switching Voltage Regulator (1.32V) to 6007 * solve a stability issue related to noisy DC2DC line 6008 * in the silicon of 1000 Series. 6009 */ 6010 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6011 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6012 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6013 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6014 } 6015 iwn_nic_unlock(sc); 6016 6017 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6018 /* Use internal power amplifier only. */ 6019 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6020 } 6021 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6022 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6023 /* Indicate that ROM calibration version is >=6. */ 6024 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6025 } 6026 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6027 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6028 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6029 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6030 sc->hw_type == IWN_HW_REV_TYPE_135 || 6031 sc->hw_type == IWN_HW_REV_TYPE_105) 6032 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6033 return 0; 6034 } 6035 6036 /* 6037 * Take NIC ownership over Intel Active Management Technology (AMT). 6038 */ 6039 static int 6040 iwn_hw_prepare(struct iwn_softc *sc) 6041 { 6042 int ntries; 6043 6044 /* Check if hardware is ready. */ 6045 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6046 for (ntries = 0; ntries < 5; ntries++) { 6047 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6048 IWN_HW_IF_CONFIG_NIC_READY) 6049 return 0; 6050 DELAY(10); 6051 } 6052 6053 /* Hardware not ready, force into ready state. */ 6054 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6055 for (ntries = 0; ntries < 15000; ntries++) { 6056 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6057 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6058 break; 6059 DELAY(10); 6060 } 6061 if (ntries == 15000) 6062 return ETIMEDOUT; 6063 6064 /* Hardware should be ready now. */ 6065 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6066 for (ntries = 0; ntries < 5; ntries++) { 6067 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6068 IWN_HW_IF_CONFIG_NIC_READY) 6069 return 0; 6070 DELAY(10); 6071 } 6072 return ETIMEDOUT; 6073 } 6074 6075 static int 6076 iwn_hw_init(struct iwn_softc *sc) 6077 { 6078 struct iwn_ops *ops = &sc->ops; 6079 int error, chnl, qid; 6080 6081 /* Clear pending interrupts. */ 6082 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6083 6084 if ((error = iwn_apm_init(sc)) != 0) { 6085 aprint_error_dev(sc->sc_dev, 6086 "could not power ON adapter\n"); 6087 return error; 6088 } 6089 6090 /* Select VMAIN power source. */ 6091 if ((error = iwn_nic_lock(sc)) != 0) 6092 return error; 6093 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6094 iwn_nic_unlock(sc); 6095 6096 /* Perform adapter-specific initialization. */ 6097 if ((error = ops->nic_config(sc)) != 0) 6098 return error; 6099 6100 /* Initialize RX ring. */ 6101 if ((error = iwn_nic_lock(sc)) != 0) 6102 return error; 6103 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6104 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6105 /* Set physical address of RX ring (256-byte aligned). */ 6106 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6107 /* Set physical address of RX status (16-byte aligned). */ 6108 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6109 /* Enable RX. */ 6110 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6111 IWN_FH_RX_CONFIG_ENA | 6112 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6113 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6114 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6115 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6116 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6117 iwn_nic_unlock(sc); 6118 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6119 6120 if ((error = iwn_nic_lock(sc)) != 0) 6121 return error; 6122 6123 /* Initialize TX scheduler. */ 6124 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6125 6126 /* Set physical address of "keep warm" page (16-byte aligned). */ 6127 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6128 6129 /* Initialize TX rings. */ 6130 for (qid = 0; qid < sc->ntxqs; qid++) { 6131 struct iwn_tx_ring *txq = &sc->txq[qid]; 6132 6133 /* Set physical address of TX ring (256-byte aligned). */ 6134 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6135 txq->desc_dma.paddr >> 8); 6136 } 6137 iwn_nic_unlock(sc); 6138 6139 /* Enable DMA channels. */ 6140 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6141 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6142 IWN_FH_TX_CONFIG_DMA_ENA | 6143 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6144 } 6145 6146 /* Clear "radio off" and "commands blocked" bits. */ 6147 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6148 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6149 6150 /* Clear pending interrupts. */ 6151 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6152 /* Enable interrupt coalescing. */ 6153 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6154 /* Enable interrupts. */ 6155 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6156 6157 /* _Really_ make sure "radio off" bit is cleared! */ 6158 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6159 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6160 6161 /* Enable shadow registers. */ 6162 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6163 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6164 6165 if ((error = ops->load_firmware(sc)) != 0) { 6166 aprint_error_dev(sc->sc_dev, 6167 "could not load firmware\n"); 6168 return error; 6169 } 6170 /* Wait at most one second for firmware alive notification. */ 6171 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 6172 aprint_error_dev(sc->sc_dev, 6173 "timeout waiting for adapter to initialize\n"); 6174 return error; 6175 } 6176 /* Do post-firmware initialization. */ 6177 return ops->post_alive(sc); 6178 } 6179 6180 static void 6181 iwn_hw_stop(struct iwn_softc *sc) 6182 { 6183 int chnl, qid, ntries; 6184 6185 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6186 6187 /* Disable interrupts. */ 6188 IWN_WRITE(sc, IWN_INT_MASK, 0); 6189 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6190 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6191 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6192 6193 /* Make sure we no longer hold the NIC lock. */ 6194 iwn_nic_unlock(sc); 6195 6196 /* Stop TX scheduler. */ 6197 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6198 6199 /* Stop all DMA channels. */ 6200 if (iwn_nic_lock(sc) == 0) { 6201 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6202 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6203 for (ntries = 0; ntries < 200; ntries++) { 6204 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6205 IWN_FH_TX_STATUS_IDLE(chnl)) 6206 break; 6207 DELAY(10); 6208 } 6209 } 6210 iwn_nic_unlock(sc); 6211 } 6212 6213 /* Stop RX ring. */ 6214 iwn_reset_rx_ring(sc, &sc->rxq); 6215 6216 /* Reset all TX rings. */ 6217 for (qid = 0; qid < sc->ntxqs; qid++) 6218 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6219 6220 if (iwn_nic_lock(sc) == 0) { 6221 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6222 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6223 iwn_nic_unlock(sc); 6224 } 6225 DELAY(5); 6226 /* Power OFF adapter. */ 6227 iwn_apm_stop(sc); 6228 } 6229 6230 static int 6231 iwn_init(struct ifnet *ifp) 6232 { 6233 struct iwn_softc *sc = ifp->if_softc; 6234 struct ieee80211com *ic = &sc->sc_ic; 6235 int error; 6236 6237 mutex_enter(&sc->sc_mtx); 6238 if (sc->sc_flags & IWN_FLAG_HW_INITED) 6239 goto out; 6240 if ((error = iwn_hw_prepare(sc)) != 0) { 6241 aprint_error_dev(sc->sc_dev, 6242 "hardware not ready\n"); 6243 goto fail; 6244 } 6245 6246 /* Check that the radio is not disabled by hardware switch. */ 6247 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6248 aprint_error_dev(sc->sc_dev, 6249 "radio is disabled by hardware switch\n"); 6250 error = EPERM; /* :-) */ 6251 goto fail; 6252 } 6253 6254 /* Read firmware images from the filesystem. */ 6255 if ((error = iwn_read_firmware(sc)) != 0) { 6256 aprint_error_dev(sc->sc_dev, 6257 "could not read firmware\n"); 6258 goto fail; 6259 } 6260 6261 /* Initialize interrupt mask to default value. */ 6262 sc->int_mask = IWN_INT_MASK_DEF; 6263 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6264 6265 /* Initialize hardware and upload firmware. */ 6266 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 6267 error = iwn_hw_init(sc); 6268 firmware_free(sc->fw.data, sc->fw.size); 6269 sc->fw.data = NULL; 6270 sc->fw.size = 0; 6271 if (error != 0) { 6272 aprint_error_dev(sc->sc_dev, 6273 "could not initialize hardware\n"); 6274 goto fail; 6275 } 6276 6277 /* Configure adapter now that it is ready. */ 6278 if ((error = iwn_config(sc)) != 0) { 6279 aprint_error_dev(sc->sc_dev, 6280 "could not configure device\n"); 6281 goto fail; 6282 } 6283 6284 ifp->if_flags &= ~IFF_OACTIVE; 6285 ifp->if_flags |= IFF_RUNNING; 6286 6287 if (ic->ic_opmode != IEEE80211_M_MONITOR) 6288 ieee80211_begin_scan(ic, 0); 6289 else 6290 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 6291 6292 sc->sc_flags |= IWN_FLAG_HW_INITED; 6293 out: 6294 mutex_exit(&sc->sc_mtx); 6295 return 0; 6296 6297 fail: mutex_exit(&sc->sc_mtx); 6298 iwn_stop(ifp, 1); 6299 return error; 6300 } 6301 6302 static void 6303 iwn_stop(struct ifnet *ifp, int disable) 6304 { 6305 struct iwn_softc *sc = ifp->if_softc; 6306 struct ieee80211com *ic = &sc->sc_ic; 6307 6308 if (!disable) 6309 mutex_enter(&sc->sc_mtx); 6310 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 6311 ifp->if_timer = sc->sc_tx_timer = 0; 6312 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6313 6314 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6315 6316 /* Power OFF hardware. */ 6317 iwn_hw_stop(sc); 6318 6319 if (!disable) 6320 mutex_exit(&sc->sc_mtx); 6321 } 6322 6323 /* 6324 * XXX MCLGETI alternative 6325 * 6326 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 6327 * as long as there are available free buffers then it uses MEXTMALLOC., 6328 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 6329 * The MCLGET4K code is used for testing an alternative mbuf cache. 6330 */ 6331 6332 static struct mbuf * 6333 MCLGETIalt(struct iwn_softc *sc, int how, 6334 struct ifnet *ifp __unused, u_int size) 6335 { 6336 struct mbuf *m; 6337 #ifdef IWN_USE_RBUF 6338 struct iwn_rbuf *rbuf; 6339 #endif 6340 6341 MGETHDR(m, how, MT_DATA); 6342 if (m == NULL) 6343 return NULL; 6344 6345 #ifdef IWN_USE_RBUF 6346 if (sc->rxq.nb_free_entries > 0 && 6347 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 6348 /* Attach buffer to mbuf header. */ 6349 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 6350 m->m_flags |= M_EXT_RW; 6351 } 6352 else { 6353 MEXTMALLOC(m, size, how); 6354 if ((m->m_flags & M_EXT) == 0) { 6355 m_freem(m); 6356 return NULL; 6357 } 6358 } 6359 6360 #else 6361 #ifdef MCLGET4K 6362 if (size == 4096) 6363 MCLGET4K(m, how); 6364 else 6365 panic("size must be 4k"); 6366 #else 6367 MEXTMALLOC(m, size, how); 6368 #endif 6369 if ((m->m_flags & M_EXT) == 0) { 6370 m_freem(m); 6371 return NULL; 6372 } 6373 #endif 6374 6375 return m; 6376 } 6377 6378 #ifdef IWN_USE_RBUF 6379 static struct iwn_rbuf * 6380 iwn_alloc_rbuf(struct iwn_softc *sc) 6381 { 6382 struct iwn_rbuf *rbuf; 6383 mutex_enter(&sc->rxq.freelist_mtx); 6384 6385 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6386 if (rbuf != NULL) { 6387 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6388 sc->rxq.nb_free_entries --; 6389 } 6390 mutex_exit(&sc->rxq.freelist_mtx); 6391 return rbuf; 6392 } 6393 6394 /* 6395 * This is called automatically by the network stack when the mbuf to which 6396 * our RX buffer is attached is freed. 6397 */ 6398 static void 6399 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6400 { 6401 struct iwn_rbuf *rbuf = arg; 6402 struct iwn_softc *sc = rbuf->sc; 6403 6404 /* Put the RX buffer back in the free list. */ 6405 mutex_enter(&sc->rxq.freelist_mtx); 6406 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6407 mutex_exit(&sc->rxq.freelist_mtx); 6408 6409 sc->rxq.nb_free_entries ++; 6410 if (__predict_true(m != NULL)) 6411 pool_cache_put(mb_cache, m); 6412 } 6413 6414 static int 6415 iwn_alloc_rpool(struct iwn_softc *sc) 6416 { 6417 struct iwn_rx_ring *ring = &sc->rxq; 6418 struct iwn_rbuf *rbuf; 6419 int i, error; 6420 6421 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6422 6423 /* Allocate a big chunk of DMA'able memory... */ 6424 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6425 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6426 if (error != 0) { 6427 aprint_error_dev(sc->sc_dev, 6428 "could not allocate RX buffers DMA memory\n"); 6429 return error; 6430 } 6431 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6432 SLIST_INIT(&ring->freelist); 6433 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6434 rbuf = &ring->rbuf[i]; 6435 6436 rbuf->sc = sc; /* Backpointer for callbacks. */ 6437 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6438 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6439 6440 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6441 } 6442 ring->nb_free_entries = IWN_RBUF_COUNT; 6443 return 0; 6444 } 6445 6446 static void 6447 iwn_free_rpool(struct iwn_softc *sc) 6448 { 6449 iwn_dma_contig_free(&sc->rxq.buf_dma); 6450 } 6451 #endif 6452 6453 /* 6454 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6455 * Copyright (c) 2001 Atsushi Onoe 6456 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6457 * Copyright (c) 2007-2009 Damien Bergamini 6458 * All rights reserved. 6459 */ 6460 6461 /* 6462 * Add an SSID element to a frame (see 7.3.2.1). 6463 */ 6464 static u_int8_t * 6465 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6466 { 6467 *frm++ = IEEE80211_ELEMID_SSID; 6468 *frm++ = len; 6469 memcpy(frm, ssid, len); 6470 return frm + len; 6471 } 6472 6473 /* 6474 * Add a supported rates element to a frame (see 7.3.2.2). 6475 */ 6476 static u_int8_t * 6477 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6478 { 6479 int nrates; 6480 6481 *frm++ = IEEE80211_ELEMID_RATES; 6482 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6483 *frm++ = nrates; 6484 memcpy(frm, rs->rs_rates, nrates); 6485 return frm + nrates; 6486 } 6487 6488 /* 6489 * Add an extended supported rates element to a frame (see 7.3.2.14). 6490 */ 6491 static u_int8_t * 6492 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6493 { 6494 int nrates; 6495 6496 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6497 6498 *frm++ = IEEE80211_ELEMID_XRATES; 6499 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6500 *frm++ = nrates; 6501 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6502 return frm + nrates; 6503 } 6504 6505 /* 6506 * XXX: Hack to set the current channel to the value advertised in beacons or 6507 * probe responses. Only used during AP detection. 6508 * XXX: Duplicated from if_iwi.c 6509 */ 6510 static void 6511 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m, 6512 struct iwn_rx_stat *stat) 6513 { 6514 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6515 struct ieee80211_frame *wh; 6516 uint8_t subtype; 6517 uint8_t *frm, *efrm; 6518 6519 wh = mtod(m, struct ieee80211_frame *); 6520 6521 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6522 return; 6523 6524 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6525 6526 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6527 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6528 return; 6529 6530 if (sc->sc_flags & IWN_FLAG_SCANNING_5GHZ) { 6531 int chan = le16toh(stat->chan); 6532 if (chan < __arraycount(ic->ic_channels)) 6533 ic->ic_curchan = &ic->ic_channels[chan]; 6534 return; 6535 } 6536 6537 frm = (uint8_t *)(wh + 1); 6538 efrm = mtod(m, uint8_t *) + m->m_len; 6539 6540 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6541 while (frm < efrm) { 6542 if (*frm == IEEE80211_ELEMID_DSPARMS) 6543 #if IEEE80211_CHAN_MAX < 255 6544 if (frm[2] <= IEEE80211_CHAN_MAX) 6545 #endif 6546 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6547 6548 frm += frm[1] + 2; 6549 } 6550 } 6551 6552 #ifdef notyetMODULE 6553 6554 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci"); 6555 6556 #ifdef _MODULE 6557 #include "ioconf.c" 6558 #endif 6559 6560 static int 6561 if_iwn_modcmd(modcmd_t cmd, void *data) 6562 { 6563 int error = 0; 6564 6565 switch (cmd) { 6566 case MODULE_CMD_INIT: 6567 #ifdef _MODULE 6568 error = config_init_component(cfdriver_ioconf_if_iwn, 6569 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6570 #endif 6571 return error; 6572 case MODULE_CMD_FINI: 6573 #ifdef _MODULE 6574 error = config_fini_component(cfdriver_ioconf_if_iwn, 6575 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6576 #endif 6577 return error; 6578 case MODULE_CMD_AUTOUNLOAD: 6579 #ifdef _MODULE 6580 /* XXX This is not optional! */ 6581 #endif 6582 return error; 6583 default: 6584 return ENOTTY; 6585 } 6586 } 6587 #endif 6588
Indexes created Thu Oct 02 14:10:14 GMT 2025