if_iwn.c revision 1.74
1 /* $NetBSD: if_iwn.c,v 1.74 2014/11/09 14:40:54 nonaka Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.74 2014/11/09 14:40:54 nonaka Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #ifdef notyetMODULE 39 #include <sys/module.h> 40 #endif 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <sys/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2, 107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1, 108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2, 109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1, 110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2, 111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1, 112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2, 113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1, 114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2, 115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1, 116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2, 117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1, 118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2, 119 }; 120 121 /* 122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 123 */ 124 static const struct ieee80211_rateset iwn_rateset_11a = 125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 126 127 static const struct ieee80211_rateset iwn_rateset_11b = 128 { 4, { 2, 4, 11, 22 } }; 129 130 static const struct ieee80211_rateset iwn_rateset_11g = 131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 132 133 static int iwn_match(device_t , struct cfdata *, void *); 134 static void iwn_attach(device_t , device_t , void *); 135 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 136 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static int iwn_detach(device_t , int); 139 #if 0 140 static void iwn_power(int, void *); 141 #endif 142 static bool iwn_resume(device_t, const pmf_qual_t *); 143 static int iwn_nic_lock(struct iwn_softc *); 144 static int iwn_eeprom_lock(struct iwn_softc *); 145 static int iwn_init_otprom(struct iwn_softc *); 146 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 147 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 148 void **, bus_size_t, bus_size_t); 149 static void iwn_dma_contig_free(struct iwn_dma_info *); 150 static int iwn_alloc_sched(struct iwn_softc *); 151 static void iwn_free_sched(struct iwn_softc *); 152 static int iwn_alloc_kw(struct iwn_softc *); 153 static void iwn_free_kw(struct iwn_softc *); 154 static int iwn_alloc_ict(struct iwn_softc *); 155 static void iwn_free_ict(struct iwn_softc *); 156 static int iwn_alloc_fwmem(struct iwn_softc *); 157 static void iwn_free_fwmem(struct iwn_softc *); 158 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 159 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 160 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 161 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 162 int); 163 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 164 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 165 static void iwn5000_ict_reset(struct iwn_softc *); 166 static int iwn_read_eeprom(struct iwn_softc *); 167 static void iwn4965_read_eeprom(struct iwn_softc *); 168 169 #ifdef IWN_DEBUG 170 static void iwn4965_print_power_group(struct iwn_softc *, int); 171 #endif 172 static void iwn5000_read_eeprom(struct iwn_softc *); 173 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 174 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 175 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 176 static void iwn_newassoc(struct ieee80211_node *, int); 177 static int iwn_media_change(struct ifnet *); 178 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 179 static void iwn_iter_func(void *, struct ieee80211_node *); 180 static void iwn_calib_timeout(void *); 181 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 #ifndef IEEE80211_NO_HT 186 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 187 struct iwn_rx_data *); 188 #endif 189 static void iwn5000_rx_calib_results(struct iwn_softc *, 190 struct iwn_rx_desc *, struct iwn_rx_data *); 191 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 192 struct iwn_rx_data *); 193 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 194 struct iwn_rx_data *); 195 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 196 struct iwn_rx_data *); 197 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 198 uint8_t); 199 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 200 static void iwn_notif_intr(struct iwn_softc *); 201 static void iwn_wakeup_intr(struct iwn_softc *); 202 static void iwn_fatal_intr(struct iwn_softc *); 203 static int iwn_intr(void *); 204 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 205 uint16_t); 206 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 207 uint16_t); 208 #ifdef notyet 209 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 210 #endif 211 static int iwn_tx(struct iwn_softc *, struct mbuf *, 212 struct ieee80211_node *, int); 213 static void iwn_start(struct ifnet *); 214 static void iwn_watchdog(struct ifnet *); 215 static int iwn_ioctl(struct ifnet *, u_long, void *); 216 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 217 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 218 int); 219 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 220 int); 221 static int iwn_set_link_quality(struct iwn_softc *, 222 struct ieee80211_node *); 223 static int iwn_add_broadcast_node(struct iwn_softc *, int); 224 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 225 static int iwn_set_critical_temp(struct iwn_softc *); 226 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 227 static void iwn4965_power_calibration(struct iwn_softc *, int); 228 static int iwn4965_set_txpower(struct iwn_softc *, int); 229 static int iwn5000_set_txpower(struct iwn_softc *, int); 230 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 231 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 232 static int iwn_get_noise(const struct iwn_rx_general_stats *); 233 static int iwn4965_get_temperature(struct iwn_softc *); 234 static int iwn5000_get_temperature(struct iwn_softc *); 235 static int iwn_init_sensitivity(struct iwn_softc *); 236 static void iwn_collect_noise(struct iwn_softc *, 237 const struct iwn_rx_general_stats *); 238 static int iwn4965_init_gains(struct iwn_softc *); 239 static int iwn5000_init_gains(struct iwn_softc *); 240 static int iwn4965_set_gains(struct iwn_softc *); 241 static int iwn5000_set_gains(struct iwn_softc *); 242 static void iwn_tune_sensitivity(struct iwn_softc *, 243 const struct iwn_rx_stats *); 244 static int iwn_send_sensitivity(struct iwn_softc *); 245 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 246 static int iwn5000_runtime_calib(struct iwn_softc *); 247 248 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 249 static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 250 static int iwn_config_bt_coex_adv1(struct iwn_softc *); 251 static int iwn_config_bt_coex_adv2(struct iwn_softc *); 252 253 static int iwn_config(struct iwn_softc *); 254 static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, 255 uint8_t); 256 static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 257 static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 258 static int iwn_scan(struct iwn_softc *, uint16_t); 259 static int iwn_auth(struct iwn_softc *); 260 static int iwn_run(struct iwn_softc *); 261 #ifdef IWN_HWCRYPTO 262 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 263 struct ieee80211_key *); 264 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 265 struct ieee80211_key *); 266 #endif 267 static int iwn_wme_update(struct ieee80211com *); 268 #ifndef IEEE80211_NO_HT 269 static int iwn_ampdu_rx_start(struct ieee80211com *, 270 struct ieee80211_node *, uint8_t); 271 static void iwn_ampdu_rx_stop(struct ieee80211com *, 272 struct ieee80211_node *, uint8_t); 273 static int iwn_ampdu_tx_start(struct ieee80211com *, 274 struct ieee80211_node *, uint8_t); 275 static void iwn_ampdu_tx_stop(struct ieee80211com *, 276 struct ieee80211_node *, uint8_t); 277 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 278 struct ieee80211_node *, uint8_t, uint16_t); 279 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 280 uint8_t, uint16_t); 281 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 282 struct ieee80211_node *, uint8_t, uint16_t); 283 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 284 uint8_t, uint16_t); 285 #endif 286 static int iwn5000_query_calibration(struct iwn_softc *); 287 static int iwn5000_send_calibration(struct iwn_softc *); 288 static int iwn5000_send_wimax_coex(struct iwn_softc *); 289 static int iwn6000_temp_offset_calib(struct iwn_softc *); 290 static int iwn2000_temp_offset_calib(struct iwn_softc *); 291 static int iwn4965_post_alive(struct iwn_softc *); 292 static int iwn5000_post_alive(struct iwn_softc *); 293 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 294 int); 295 static int iwn4965_load_firmware(struct iwn_softc *); 296 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 297 const uint8_t *, int); 298 static int iwn5000_load_firmware(struct iwn_softc *); 299 static int iwn_read_firmware_leg(struct iwn_softc *, 300 struct iwn_fw_info *); 301 static int iwn_read_firmware_tlv(struct iwn_softc *, 302 struct iwn_fw_info *, uint16_t); 303 static int iwn_read_firmware(struct iwn_softc *); 304 static int iwn_clock_wait(struct iwn_softc *); 305 static int iwn_apm_init(struct iwn_softc *); 306 static void iwn_apm_stop_master(struct iwn_softc *); 307 static void iwn_apm_stop(struct iwn_softc *); 308 static int iwn4965_nic_config(struct iwn_softc *); 309 static int iwn5000_nic_config(struct iwn_softc *); 310 static int iwn_hw_prepare(struct iwn_softc *); 311 static int iwn_hw_init(struct iwn_softc *); 312 static void iwn_hw_stop(struct iwn_softc *); 313 static int iwn_init(struct ifnet *); 314 static void iwn_stop(struct ifnet *, int); 315 316 /* XXX MCLGETI alternative */ 317 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 318 struct ifnet *, u_int); 319 #ifdef IWN_USE_RBUF 320 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 321 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 322 static int iwn_alloc_rpool(struct iwn_softc *); 323 static void iwn_free_rpool(struct iwn_softc *); 324 #endif 325 326 /* XXX needed by iwn_scan */ 327 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 328 static u_int8_t *ieee80211_add_rates(u_int8_t *, 329 const struct ieee80211_rateset *); 330 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 331 const struct ieee80211_rateset *); 332 333 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 334 335 #ifdef IWN_DEBUG 336 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 337 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 338 int iwn_debug = 0; 339 #else 340 #define DPRINTF(x) 341 #define DPRINTFN(n, x) 342 #endif 343 344 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 345 iwn_detach, NULL); 346 347 static int 348 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 349 { 350 struct pci_attach_args *pa = aux; 351 size_t i; 352 353 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 354 return 0; 355 356 for (i = 0; i < __arraycount(iwn_devices); i++) 357 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 358 return 1; 359 360 return 0; 361 } 362 363 static void 364 iwn_attach(device_t parent __unused, device_t self, void *aux) 365 { 366 struct iwn_softc *sc = device_private(self); 367 struct ieee80211com *ic = &sc->sc_ic; 368 struct ifnet *ifp = &sc->sc_ec.ec_if; 369 struct pci_attach_args *pa = aux; 370 const char *intrstr; 371 pci_intr_handle_t ih; 372 pcireg_t memtype, reg; 373 int i, error; 374 char intrbuf[PCI_INTRSTR_LEN]; 375 376 sc->sc_dev = self; 377 sc->sc_pct = pa->pa_pc; 378 sc->sc_pcitag = pa->pa_tag; 379 sc->sc_dmat = pa->pa_dmat; 380 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 381 382 callout_init(&sc->calib_to, 0); 383 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 384 385 pci_aprint_devinfo(pa, NULL); 386 387 /* 388 * Get the offset of the PCI Express Capability Structure in PCI 389 * Configuration Space. 390 */ 391 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 392 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 393 if (error == 0) { 394 aprint_error_dev(self, 395 "PCIe capability structure not found!\n"); 396 return; 397 } 398 399 /* Clear device-specific "PCI retry timeout" register (41h). */ 400 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 401 if (reg & 0xff00) 402 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 403 404 /* Enable bus-mastering and hardware bug workaround. */ 405 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 406 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 407 reg |= PCI_COMMAND_MASTER_ENABLE; 408 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 409 DPRINTF(("PCIe INTx Disable set\n")); 410 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 411 } 412 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 413 414 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 415 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 416 &sc->sc_sh, NULL, &sc->sc_sz); 417 if (error != 0) { 418 aprint_error_dev(self, "can't map mem space\n"); 419 return; 420 } 421 422 /* Install interrupt handler. */ 423 if (pci_intr_map(pa, &ih) != 0) { 424 aprint_error_dev(self, "can't map interrupt\n"); 425 return; 426 } 427 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 428 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 429 if (sc->sc_ih == NULL) { 430 aprint_error_dev(self, "can't establish interrupt"); 431 if (intrstr != NULL) 432 aprint_error(" at %s", intrstr); 433 aprint_error("\n"); 434 return; 435 } 436 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 437 438 /* Read hardware revision and attach. */ 439 sc->hw_type = 440 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK) 441 >> IWN_HW_REV_TYPE_SHIFT; 442 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 443 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 444 else 445 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 446 if (error != 0) { 447 aprint_error_dev(self, "could not attach device\n"); 448 return; 449 } 450 451 if ((error = iwn_hw_prepare(sc)) != 0) { 452 aprint_error_dev(self, "hardware not ready\n"); 453 return; 454 } 455 456 /* Read MAC address, channels, etc from EEPROM. */ 457 if ((error = iwn_read_eeprom(sc)) != 0) { 458 aprint_error_dev(self, "could not read EEPROM\n"); 459 return; 460 } 461 462 /* Allocate DMA memory for firmware transfers. */ 463 if ((error = iwn_alloc_fwmem(sc)) != 0) { 464 aprint_error_dev(self, 465 "could not allocate memory for firmware\n"); 466 return; 467 } 468 469 /* Allocate "Keep Warm" page. */ 470 if ((error = iwn_alloc_kw(sc)) != 0) { 471 aprint_error_dev(self, "could not allocate keep warm page\n"); 472 goto fail1; 473 } 474 475 /* Allocate ICT table for 5000 Series. */ 476 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 477 (error = iwn_alloc_ict(sc)) != 0) { 478 aprint_error_dev(self, "could not allocate ICT table\n"); 479 goto fail2; 480 } 481 482 /* Allocate TX scheduler "rings". */ 483 if ((error = iwn_alloc_sched(sc)) != 0) { 484 aprint_error_dev(self, 485 "could not allocate TX scheduler rings\n"); 486 goto fail3; 487 } 488 489 #ifdef IWN_USE_RBUF 490 /* Allocate RX buffers. */ 491 if ((error = iwn_alloc_rpool(sc)) != 0) { 492 aprint_error_dev(self, "could not allocate RX buffers\n"); 493 goto fail3; 494 } 495 #endif 496 497 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 498 for (i = 0; i < sc->ntxqs; i++) { 499 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 500 aprint_error_dev(self, 501 "could not allocate TX ring %d\n", i); 502 goto fail4; 503 } 504 } 505 506 /* Allocate RX ring. */ 507 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 508 aprint_error_dev(self, "could not allocate RX ring\n"); 509 goto fail4; 510 } 511 512 /* Clear pending interrupts. */ 513 IWN_WRITE(sc, IWN_INT, 0xffffffff); 514 515 /* Count the number of available chains. */ 516 sc->ntxchains = 517 ((sc->txchainmask >> 2) & 1) + 518 ((sc->txchainmask >> 1) & 1) + 519 ((sc->txchainmask >> 0) & 1); 520 sc->nrxchains = 521 ((sc->rxchainmask >> 2) & 1) + 522 ((sc->rxchainmask >> 1) & 1) + 523 ((sc->rxchainmask >> 0) & 1); 524 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 525 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 526 ether_sprintf(ic->ic_myaddr)); 527 528 ic->ic_ifp = ifp; 529 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 530 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 531 ic->ic_state = IEEE80211_S_INIT; 532 533 /* Set device capabilities. */ 534 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 535 * and IEEE80211_C_PMGT too. */ 536 ic->ic_caps = 537 IEEE80211_C_IBSS | /* IBSS mode support */ 538 IEEE80211_C_WPA | /* 802.11i */ 539 IEEE80211_C_MONITOR | /* monitor mode supported */ 540 IEEE80211_C_TXPMGT | /* tx power management */ 541 IEEE80211_C_SHSLOT | /* short slot time supported */ 542 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 543 IEEE80211_C_WME; /* 802.11e */ 544 545 #ifndef IEEE80211_NO_HT 546 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 547 /* Set HT capabilities. */ 548 ic->ic_htcaps = 549 #if IWN_RBUF_SIZE == 8192 550 IEEE80211_HTCAP_AMSDU7935 | 551 #endif 552 IEEE80211_HTCAP_CBW20_40 | 553 IEEE80211_HTCAP_SGI20 | 554 IEEE80211_HTCAP_SGI40; 555 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 556 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 557 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 558 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 559 else 560 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 561 } 562 #endif /* !IEEE80211_NO_HT */ 563 564 /* Set supported legacy rates. */ 565 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 566 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 567 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 568 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 569 } 570 #ifndef IEEE80211_NO_HT 571 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 572 /* Set supported HT rates. */ 573 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 574 if (sc->nrxchains > 1) 575 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 576 if (sc->nrxchains > 2) 577 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 578 } 579 #endif 580 581 /* IBSS channel undefined for now. */ 582 ic->ic_ibss_chan = &ic->ic_channels[0]; 583 584 ifp->if_softc = sc; 585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 586 ifp->if_init = iwn_init; 587 ifp->if_ioctl = iwn_ioctl; 588 ifp->if_start = iwn_start; 589 ifp->if_stop = iwn_stop; 590 ifp->if_watchdog = iwn_watchdog; 591 IFQ_SET_READY(&ifp->if_snd); 592 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 593 594 if_attach(ifp); 595 ieee80211_ifattach(ic); 596 ic->ic_node_alloc = iwn_node_alloc; 597 ic->ic_newassoc = iwn_newassoc; 598 #ifdef IWN_HWCRYPTO 599 ic->ic_crypto.cs_key_set = iwn_set_key; 600 ic->ic_crypto.cs_key_delete = iwn_delete_key; 601 #endif 602 ic->ic_wme.wme_update = iwn_wme_update; 603 #ifndef IEEE80211_NO_HT 604 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 605 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 606 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 607 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 608 #endif 609 610 /* Override 802.11 state transition machine. */ 611 sc->sc_newstate = ic->ic_newstate; 612 ic->ic_newstate = iwn_newstate; 613 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 614 615 sc->amrr.amrr_min_success_threshold = 1; 616 sc->amrr.amrr_max_success_threshold = 15; 617 618 iwn_radiotap_attach(sc); 619 620 /* 621 * XXX for NetBSD, OpenBSD timeout_set replaced by 622 * callout_init and callout_setfunc, above. 623 */ 624 625 if (pmf_device_register(self, NULL, iwn_resume)) 626 pmf_class_network_register(self, ifp); 627 else 628 aprint_error_dev(self, "couldn't establish power handler\n"); 629 630 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 631 ieee80211_announce(ic); 632 633 return; 634 635 /* Free allocated memory if something failed during attachment. */ 636 fail4: while (--i >= 0) 637 iwn_free_tx_ring(sc, &sc->txq[i]); 638 #ifdef IWN_USE_RBUF 639 iwn_free_rpool(sc); 640 #endif 641 iwn_free_sched(sc); 642 fail3: if (sc->ict != NULL) 643 iwn_free_ict(sc); 644 fail2: iwn_free_kw(sc); 645 fail1: iwn_free_fwmem(sc); 646 } 647 648 int 649 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 650 { 651 struct iwn_ops *ops = &sc->ops; 652 653 ops->load_firmware = iwn4965_load_firmware; 654 ops->read_eeprom = iwn4965_read_eeprom; 655 ops->post_alive = iwn4965_post_alive; 656 ops->nic_config = iwn4965_nic_config; 657 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 658 ops->update_sched = iwn4965_update_sched; 659 ops->get_temperature = iwn4965_get_temperature; 660 ops->get_rssi = iwn4965_get_rssi; 661 ops->set_txpower = iwn4965_set_txpower; 662 ops->init_gains = iwn4965_init_gains; 663 ops->set_gains = iwn4965_set_gains; 664 ops->add_node = iwn4965_add_node; 665 ops->tx_done = iwn4965_tx_done; 666 #ifndef IEEE80211_NO_HT 667 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 668 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 669 #endif 670 sc->ntxqs = IWN4965_NTXQUEUES; 671 sc->ndmachnls = IWN4965_NDMACHNLS; 672 sc->broadcast_id = IWN4965_ID_BROADCAST; 673 sc->rxonsz = IWN4965_RXONSZ; 674 sc->schedsz = IWN4965_SCHEDSZ; 675 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 676 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 677 sc->fwsz = IWN4965_FWSZ; 678 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 679 sc->limits = &iwn4965_sensitivity_limits; 680 sc->fwname = "iwlwifi-4965-2.ucode"; 681 /* Override chains masks, ROM is known to be broken. */ 682 sc->txchainmask = IWN_ANT_AB; 683 sc->rxchainmask = IWN_ANT_ABC; 684 685 return 0; 686 } 687 688 int 689 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 690 { 691 struct iwn_ops *ops = &sc->ops; 692 693 ops->load_firmware = iwn5000_load_firmware; 694 ops->read_eeprom = iwn5000_read_eeprom; 695 ops->post_alive = iwn5000_post_alive; 696 ops->nic_config = iwn5000_nic_config; 697 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 698 ops->update_sched = iwn5000_update_sched; 699 ops->get_temperature = iwn5000_get_temperature; 700 ops->get_rssi = iwn5000_get_rssi; 701 ops->set_txpower = iwn5000_set_txpower; 702 ops->init_gains = iwn5000_init_gains; 703 ops->set_gains = iwn5000_set_gains; 704 ops->add_node = iwn5000_add_node; 705 ops->tx_done = iwn5000_tx_done; 706 #ifndef IEEE80211_NO_HT 707 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 708 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 709 #endif 710 sc->ntxqs = IWN5000_NTXQUEUES; 711 sc->ndmachnls = IWN5000_NDMACHNLS; 712 sc->broadcast_id = IWN5000_ID_BROADCAST; 713 sc->rxonsz = IWN5000_RXONSZ; 714 sc->schedsz = IWN5000_SCHEDSZ; 715 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 716 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 717 sc->fwsz = IWN5000_FWSZ; 718 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 719 720 switch (sc->hw_type) { 721 case IWN_HW_REV_TYPE_5100: 722 sc->limits = &iwn5000_sensitivity_limits; 723 sc->fwname = "iwlwifi-5000-2.ucode"; 724 /* Override chains masks, ROM is known to be broken. */ 725 sc->txchainmask = IWN_ANT_B; 726 sc->rxchainmask = IWN_ANT_AB; 727 break; 728 case IWN_HW_REV_TYPE_5150: 729 sc->limits = &iwn5150_sensitivity_limits; 730 sc->fwname = "iwlwifi-5150-2.ucode"; 731 break; 732 case IWN_HW_REV_TYPE_5300: 733 case IWN_HW_REV_TYPE_5350: 734 sc->limits = &iwn5000_sensitivity_limits; 735 sc->fwname = "iwlwifi-5000-2.ucode"; 736 break; 737 case IWN_HW_REV_TYPE_1000: 738 sc->limits = &iwn1000_sensitivity_limits; 739 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 || 740 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2) 741 sc->fwname = "iwlwifi-100-5.ucode"; 742 else 743 sc->fwname = "iwlwifi-1000-3.ucode"; 744 break; 745 case IWN_HW_REV_TYPE_6000: 746 sc->limits = &iwn6000_sensitivity_limits; 747 sc->fwname = "iwlwifi-6000-4.ucode"; 748 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 749 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 750 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 751 /* Override chains masks, ROM is known to be broken. */ 752 sc->txchainmask = IWN_ANT_BC; 753 sc->rxchainmask = IWN_ANT_BC; 754 } 755 break; 756 case IWN_HW_REV_TYPE_6050: 757 sc->limits = &iwn6000_sensitivity_limits; 758 sc->fwname = "iwlwifi-6050-5.ucode"; 759 break; 760 case IWN_HW_REV_TYPE_6005: 761 sc->limits = &iwn6000_sensitivity_limits; 762 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 763 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 764 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 765 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 766 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 767 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 || 768 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) { 769 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 770 ops->config_bt_coex = iwn_config_bt_coex_adv1; 771 } 772 else 773 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 774 break; 775 case IWN_HW_REV_TYPE_2030: 776 sc->limits = &iwn2000_sensitivity_limits; 777 sc->fwname = "iwlwifi-2030-6.ucode"; 778 ops->config_bt_coex = iwn_config_bt_coex_adv2; 779 break; 780 case IWN_HW_REV_TYPE_2000: 781 sc->limits = &iwn2000_sensitivity_limits; 782 sc->fwname = "iwlwifi-2000-6.ucode"; 783 break; 784 case IWN_HW_REV_TYPE_135: 785 sc->limits = &iwn2000_sensitivity_limits; 786 sc->fwname = "iwlwifi-135-6.ucode"; 787 ops->config_bt_coex = iwn_config_bt_coex_adv2; 788 break; 789 case IWN_HW_REV_TYPE_105: 790 sc->limits = &iwn2000_sensitivity_limits; 791 sc->fwname = "iwlwifi-105-6.ucode"; 792 break; 793 default: 794 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 795 return ENOTSUP; 796 } 797 return 0; 798 } 799 800 /* 801 * Attach the interface to 802.11 radiotap. 802 */ 803 static void 804 iwn_radiotap_attach(struct iwn_softc *sc) 805 { 806 struct ifnet *ifp = sc->sc_ic.ic_ifp; 807 808 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 809 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 810 &sc->sc_drvbpf); 811 812 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 813 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 814 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 815 816 sc->sc_txtap_len = sizeof sc->sc_txtapu; 817 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 818 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 819 } 820 821 static int 822 iwn_detach(device_t self, int flags __unused) 823 { 824 struct iwn_softc *sc = device_private(self); 825 struct ifnet *ifp = sc->sc_ic.ic_ifp; 826 int qid; 827 828 callout_stop(&sc->calib_to); 829 830 /* Uninstall interrupt handler. */ 831 if (sc->sc_ih != NULL) 832 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 833 834 /* Free DMA resources. */ 835 iwn_free_rx_ring(sc, &sc->rxq); 836 for (qid = 0; qid < sc->ntxqs; qid++) 837 iwn_free_tx_ring(sc, &sc->txq[qid]); 838 #ifdef IWN_USE_RBUF 839 iwn_free_rpool(sc); 840 #endif 841 iwn_free_sched(sc); 842 iwn_free_kw(sc); 843 if (sc->ict != NULL) 844 iwn_free_ict(sc); 845 iwn_free_fwmem(sc); 846 847 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 848 849 ieee80211_ifdetach(&sc->sc_ic); 850 if_detach(ifp); 851 852 return 0; 853 } 854 855 #if 0 856 /* 857 * XXX Investigate if clearing the PCI retry timeout could eliminate 858 * the repeated scan calls. Also the calls to if_init and if_start 859 * are similar to the effect of adding the call to ifioctl_common . 860 */ 861 static void 862 iwn_power(int why, void *arg) 863 { 864 struct iwn_softc *sc = arg; 865 struct ifnet *ifp; 866 pcireg_t reg; 867 int s; 868 869 if (why != PWR_RESUME) 870 return; 871 872 /* Clear device-specific "PCI retry timeout" register (41h). */ 873 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 874 if (reg & 0xff00) 875 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 876 877 s = splnet(); 878 ifp = &sc->sc_ic.ic_if; 879 if (ifp->if_flags & IFF_UP) { 880 ifp->if_init(ifp); 881 if (ifp->if_flags & IFF_RUNNING) 882 ifp->if_start(ifp); 883 } 884 splx(s); 885 } 886 #endif 887 888 static bool 889 iwn_resume(device_t dv, const pmf_qual_t *qual) 890 { 891 return true; 892 } 893 894 static int 895 iwn_nic_lock(struct iwn_softc *sc) 896 { 897 int ntries; 898 899 /* Request exclusive access to NIC. */ 900 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 901 902 /* Spin until we actually get the lock. */ 903 for (ntries = 0; ntries < 1000; ntries++) { 904 if ((IWN_READ(sc, IWN_GP_CNTRL) & 905 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 906 IWN_GP_CNTRL_MAC_ACCESS_ENA) 907 return 0; 908 DELAY(10); 909 } 910 return ETIMEDOUT; 911 } 912 913 static __inline void 914 iwn_nic_unlock(struct iwn_softc *sc) 915 { 916 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 917 } 918 919 static __inline uint32_t 920 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 921 { 922 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 923 IWN_BARRIER_READ_WRITE(sc); 924 return IWN_READ(sc, IWN_PRPH_RDATA); 925 } 926 927 static __inline void 928 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 929 { 930 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 931 IWN_BARRIER_WRITE(sc); 932 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 933 } 934 935 static __inline void 936 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 937 { 938 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 939 } 940 941 static __inline void 942 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 943 { 944 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 945 } 946 947 static __inline void 948 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 949 const uint32_t *data, int count) 950 { 951 for (; count > 0; count--, data++, addr += 4) 952 iwn_prph_write(sc, addr, *data); 953 } 954 955 static __inline uint32_t 956 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 957 { 958 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 959 IWN_BARRIER_READ_WRITE(sc); 960 return IWN_READ(sc, IWN_MEM_RDATA); 961 } 962 963 static __inline void 964 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 965 { 966 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 967 IWN_BARRIER_WRITE(sc); 968 IWN_WRITE(sc, IWN_MEM_WDATA, data); 969 } 970 971 #ifndef IEEE80211_NO_HT 972 static __inline void 973 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 974 { 975 uint32_t tmp; 976 977 tmp = iwn_mem_read(sc, addr & ~3); 978 if (addr & 3) 979 tmp = (tmp & 0x0000ffff) | data << 16; 980 else 981 tmp = (tmp & 0xffff0000) | data; 982 iwn_mem_write(sc, addr & ~3, tmp); 983 } 984 #endif 985 986 static __inline void 987 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 988 int count) 989 { 990 for (; count > 0; count--, addr += 4) 991 *data++ = iwn_mem_read(sc, addr); 992 } 993 994 static __inline void 995 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 996 int count) 997 { 998 for (; count > 0; count--, addr += 4) 999 iwn_mem_write(sc, addr, val); 1000 } 1001 1002 static int 1003 iwn_eeprom_lock(struct iwn_softc *sc) 1004 { 1005 int i, ntries; 1006 1007 for (i = 0; i < 100; i++) { 1008 /* Request exclusive access to EEPROM. */ 1009 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1010 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1011 1012 /* Spin until we actually get the lock. */ 1013 for (ntries = 0; ntries < 100; ntries++) { 1014 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1015 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1016 return 0; 1017 DELAY(10); 1018 } 1019 } 1020 return ETIMEDOUT; 1021 } 1022 1023 static __inline void 1024 iwn_eeprom_unlock(struct iwn_softc *sc) 1025 { 1026 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1027 } 1028 1029 /* 1030 * Initialize access by host to One Time Programmable ROM. 1031 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1032 */ 1033 static int 1034 iwn_init_otprom(struct iwn_softc *sc) 1035 { 1036 uint16_t prev = 0, base, next; 1037 int count, error; 1038 1039 /* Wait for clock stabilization before accessing prph. */ 1040 if ((error = iwn_clock_wait(sc)) != 0) 1041 return error; 1042 1043 if ((error = iwn_nic_lock(sc)) != 0) 1044 return error; 1045 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1046 DELAY(5); 1047 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1048 iwn_nic_unlock(sc); 1049 1050 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1051 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1052 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1053 IWN_RESET_LINK_PWR_MGMT_DIS); 1054 } 1055 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1056 /* Clear ECC status. */ 1057 IWN_SETBITS(sc, IWN_OTP_GP, 1058 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1059 1060 /* 1061 * Find the block before last block (contains the EEPROM image) 1062 * for HW without OTP shadow RAM. 1063 */ 1064 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1065 /* Switch to absolute addressing mode. */ 1066 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1067 base = 0; 1068 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1069 error = iwn_read_prom_data(sc, base, &next, 2); 1070 if (error != 0) 1071 return error; 1072 if (next == 0) /* End of linked-list. */ 1073 break; 1074 prev = base; 1075 base = le16toh(next); 1076 } 1077 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1078 return EIO; 1079 /* Skip "next" word. */ 1080 sc->prom_base = prev + 1; 1081 } 1082 return 0; 1083 } 1084 1085 static int 1086 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1087 { 1088 uint8_t *out = data; 1089 uint32_t val, tmp; 1090 int ntries; 1091 1092 addr += sc->prom_base; 1093 for (; count > 0; count -= 2, addr++) { 1094 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1095 for (ntries = 0; ntries < 10; ntries++) { 1096 val = IWN_READ(sc, IWN_EEPROM); 1097 if (val & IWN_EEPROM_READ_VALID) 1098 break; 1099 DELAY(5); 1100 } 1101 if (ntries == 10) { 1102 aprint_error_dev(sc->sc_dev, 1103 "timeout reading ROM at 0x%x\n", addr); 1104 return ETIMEDOUT; 1105 } 1106 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1107 /* OTPROM, check for ECC errors. */ 1108 tmp = IWN_READ(sc, IWN_OTP_GP); 1109 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1110 aprint_error_dev(sc->sc_dev, 1111 "OTPROM ECC error at 0x%x\n", addr); 1112 return EIO; 1113 } 1114 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1115 /* Correctable ECC error, clear bit. */ 1116 IWN_SETBITS(sc, IWN_OTP_GP, 1117 IWN_OTP_GP_ECC_CORR_STTS); 1118 } 1119 } 1120 *out++ = val >> 16; 1121 if (count > 1) 1122 *out++ = val >> 24; 1123 } 1124 return 0; 1125 } 1126 1127 static int 1128 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1129 bus_size_t size, bus_size_t alignment) 1130 { 1131 int nsegs, error; 1132 1133 dma->tag = tag; 1134 dma->size = size; 1135 1136 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1137 &dma->map); 1138 if (error != 0) 1139 goto fail; 1140 1141 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1142 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1143 if (error != 0) 1144 goto fail; 1145 1146 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1147 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1148 if (error != 0) 1149 goto fail; 1150 1151 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1152 BUS_DMA_NOWAIT); 1153 if (error != 0) 1154 goto fail; 1155 1156 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1157 memset(dma->vaddr, 0, size); 1158 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1159 1160 dma->paddr = dma->map->dm_segs[0].ds_addr; 1161 if (kvap != NULL) 1162 *kvap = dma->vaddr; 1163 1164 return 0; 1165 1166 fail: iwn_dma_contig_free(dma); 1167 return error; 1168 } 1169 1170 static void 1171 iwn_dma_contig_free(struct iwn_dma_info *dma) 1172 { 1173 if (dma->map != NULL) { 1174 if (dma->vaddr != NULL) { 1175 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1176 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1177 bus_dmamap_unload(dma->tag, dma->map); 1178 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1179 bus_dmamem_free(dma->tag, &dma->seg, 1); 1180 dma->vaddr = NULL; 1181 } 1182 bus_dmamap_destroy(dma->tag, dma->map); 1183 dma->map = NULL; 1184 } 1185 } 1186 1187 static int 1188 iwn_alloc_sched(struct iwn_softc *sc) 1189 { 1190 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1191 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1192 (void **)&sc->sched, sc->schedsz, 1024); 1193 } 1194 1195 static void 1196 iwn_free_sched(struct iwn_softc *sc) 1197 { 1198 iwn_dma_contig_free(&sc->sched_dma); 1199 } 1200 1201 static int 1202 iwn_alloc_kw(struct iwn_softc *sc) 1203 { 1204 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1205 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1206 4096); 1207 } 1208 1209 static void 1210 iwn_free_kw(struct iwn_softc *sc) 1211 { 1212 iwn_dma_contig_free(&sc->kw_dma); 1213 } 1214 1215 static int 1216 iwn_alloc_ict(struct iwn_softc *sc) 1217 { 1218 /* ICT table must be aligned on a 4KB boundary. */ 1219 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1220 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1221 } 1222 1223 static void 1224 iwn_free_ict(struct iwn_softc *sc) 1225 { 1226 iwn_dma_contig_free(&sc->ict_dma); 1227 } 1228 1229 static int 1230 iwn_alloc_fwmem(struct iwn_softc *sc) 1231 { 1232 /* Must be aligned on a 16-byte boundary. */ 1233 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1234 sc->fwsz, 16); 1235 } 1236 1237 static void 1238 iwn_free_fwmem(struct iwn_softc *sc) 1239 { 1240 iwn_dma_contig_free(&sc->fw_dma); 1241 } 1242 1243 static int 1244 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1245 { 1246 bus_size_t size; 1247 int i, error; 1248 1249 ring->cur = 0; 1250 1251 /* Allocate RX descriptors (256-byte aligned). */ 1252 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1253 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1254 (void **)&ring->desc, size, 256); 1255 if (error != 0) { 1256 aprint_error_dev(sc->sc_dev, 1257 "could not allocate RX ring DMA memory\n"); 1258 goto fail; 1259 } 1260 1261 /* Allocate RX status area (16-byte aligned). */ 1262 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1263 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1264 if (error != 0) { 1265 aprint_error_dev(sc->sc_dev, 1266 "could not allocate RX status DMA memory\n"); 1267 goto fail; 1268 } 1269 1270 /* 1271 * Allocate and map RX buffers. 1272 */ 1273 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1274 struct iwn_rx_data *data = &ring->data[i]; 1275 1276 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1277 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1278 &data->map); 1279 if (error != 0) { 1280 aprint_error_dev(sc->sc_dev, 1281 "could not create RX buf DMA map\n"); 1282 goto fail; 1283 } 1284 1285 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1286 if (data->m == NULL) { 1287 aprint_error_dev(sc->sc_dev, 1288 "could not allocate RX mbuf\n"); 1289 error = ENOBUFS; 1290 goto fail; 1291 } 1292 1293 error = bus_dmamap_load(sc->sc_dmat, data->map, 1294 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1295 BUS_DMA_NOWAIT | BUS_DMA_READ); 1296 if (error != 0) { 1297 aprint_error_dev(sc->sc_dev, 1298 "can't not map mbuf (error %d)\n", error); 1299 goto fail; 1300 } 1301 1302 /* Set physical address of RX buffer (256-byte aligned). */ 1303 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1304 } 1305 1306 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1307 BUS_DMASYNC_PREWRITE); 1308 1309 return 0; 1310 1311 fail: iwn_free_rx_ring(sc, ring); 1312 return error; 1313 } 1314 1315 static void 1316 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1317 { 1318 int ntries; 1319 1320 if (iwn_nic_lock(sc) == 0) { 1321 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1322 for (ntries = 0; ntries < 1000; ntries++) { 1323 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1324 IWN_FH_RX_STATUS_IDLE) 1325 break; 1326 DELAY(10); 1327 } 1328 iwn_nic_unlock(sc); 1329 } 1330 ring->cur = 0; 1331 sc->last_rx_valid = 0; 1332 } 1333 1334 static void 1335 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1336 { 1337 int i; 1338 1339 iwn_dma_contig_free(&ring->desc_dma); 1340 iwn_dma_contig_free(&ring->stat_dma); 1341 1342 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1343 struct iwn_rx_data *data = &ring->data[i]; 1344 1345 if (data->m != NULL) { 1346 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1347 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1348 bus_dmamap_unload(sc->sc_dmat, data->map); 1349 m_freem(data->m); 1350 } 1351 if (data->map != NULL) 1352 bus_dmamap_destroy(sc->sc_dmat, data->map); 1353 } 1354 } 1355 1356 static int 1357 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1358 { 1359 bus_addr_t paddr; 1360 bus_size_t size; 1361 int i, error; 1362 1363 ring->qid = qid; 1364 ring->queued = 0; 1365 ring->cur = 0; 1366 1367 /* Allocate TX descriptors (256-byte aligned). */ 1368 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1369 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1370 (void **)&ring->desc, size, 256); 1371 if (error != 0) { 1372 aprint_error_dev(sc->sc_dev, 1373 "could not allocate TX ring DMA memory\n"); 1374 goto fail; 1375 } 1376 /* 1377 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1378 * to allocate commands space for other rings. 1379 * XXX Do we really need to allocate descriptors for other rings? 1380 */ 1381 if (qid > 4) 1382 return 0; 1383 1384 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1385 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1386 (void **)&ring->cmd, size, 4); 1387 if (error != 0) { 1388 aprint_error_dev(sc->sc_dev, 1389 "could not allocate TX cmd DMA memory\n"); 1390 goto fail; 1391 } 1392 1393 paddr = ring->cmd_dma.paddr; 1394 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1395 struct iwn_tx_data *data = &ring->data[i]; 1396 1397 data->cmd_paddr = paddr; 1398 data->scratch_paddr = paddr + 12; 1399 paddr += sizeof (struct iwn_tx_cmd); 1400 1401 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1402 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1403 &data->map); 1404 if (error != 0) { 1405 aprint_error_dev(sc->sc_dev, 1406 "could not create TX buf DMA map\n"); 1407 goto fail; 1408 } 1409 } 1410 return 0; 1411 1412 fail: iwn_free_tx_ring(sc, ring); 1413 return error; 1414 } 1415 1416 static void 1417 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1418 { 1419 int i; 1420 1421 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1422 struct iwn_tx_data *data = &ring->data[i]; 1423 1424 if (data->m != NULL) { 1425 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1426 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1427 bus_dmamap_unload(sc->sc_dmat, data->map); 1428 m_freem(data->m); 1429 data->m = NULL; 1430 } 1431 } 1432 /* Clear TX descriptors. */ 1433 memset(ring->desc, 0, ring->desc_dma.size); 1434 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1435 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1436 sc->qfullmsk &= ~(1 << ring->qid); 1437 ring->queued = 0; 1438 ring->cur = 0; 1439 } 1440 1441 static void 1442 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1443 { 1444 int i; 1445 1446 iwn_dma_contig_free(&ring->desc_dma); 1447 iwn_dma_contig_free(&ring->cmd_dma); 1448 1449 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1450 struct iwn_tx_data *data = &ring->data[i]; 1451 1452 if (data->m != NULL) { 1453 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1454 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1455 bus_dmamap_unload(sc->sc_dmat, data->map); 1456 m_freem(data->m); 1457 } 1458 if (data->map != NULL) 1459 bus_dmamap_destroy(sc->sc_dmat, data->map); 1460 } 1461 } 1462 1463 static void 1464 iwn5000_ict_reset(struct iwn_softc *sc) 1465 { 1466 /* Disable interrupts. */ 1467 IWN_WRITE(sc, IWN_INT_MASK, 0); 1468 1469 /* Reset ICT table. */ 1470 memset(sc->ict, 0, IWN_ICT_SIZE); 1471 sc->ict_cur = 0; 1472 1473 /* Set physical address of ICT table (4KB aligned). */ 1474 DPRINTF(("enabling ICT\n")); 1475 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1476 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1477 1478 /* Enable periodic RX interrupt. */ 1479 sc->int_mask |= IWN_INT_RX_PERIODIC; 1480 /* Switch to ICT interrupt mode in driver. */ 1481 sc->sc_flags |= IWN_FLAG_USE_ICT; 1482 1483 /* Re-enable interrupts. */ 1484 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1485 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1486 } 1487 1488 static int 1489 iwn_read_eeprom(struct iwn_softc *sc) 1490 { 1491 struct iwn_ops *ops = &sc->ops; 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 uint16_t val; 1494 int error; 1495 1496 /* Check whether adapter has an EEPROM or an OTPROM. */ 1497 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1498 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1499 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1500 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1501 "OTPROM" : "EEPROM")); 1502 1503 /* Adapter has to be powered on for EEPROM access to work. */ 1504 if ((error = iwn_apm_init(sc)) != 0) { 1505 aprint_error_dev(sc->sc_dev, 1506 "could not power ON adapter\n"); 1507 return error; 1508 } 1509 1510 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1511 aprint_error_dev(sc->sc_dev, 1512 "bad ROM signature\n"); 1513 return EIO; 1514 } 1515 if ((error = iwn_eeprom_lock(sc)) != 0) { 1516 aprint_error_dev(sc->sc_dev, 1517 "could not lock ROM (error=%d)\n", error); 1518 return error; 1519 } 1520 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1521 if ((error = iwn_init_otprom(sc)) != 0) { 1522 aprint_error_dev(sc->sc_dev, 1523 "could not initialize OTPROM\n"); 1524 return error; 1525 } 1526 } 1527 1528 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1529 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1530 /* Check if HT support is bonded out. */ 1531 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1532 sc->sc_flags |= IWN_FLAG_HAS_11N; 1533 1534 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1535 sc->rfcfg = le16toh(val); 1536 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1537 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1538 if (sc->txchainmask == 0) 1539 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1540 if (sc->rxchainmask == 0) 1541 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1542 1543 /* Read MAC address. */ 1544 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1545 1546 /* Read adapter-specific information from EEPROM. */ 1547 ops->read_eeprom(sc); 1548 1549 iwn_apm_stop(sc); /* Power OFF adapter. */ 1550 1551 iwn_eeprom_unlock(sc); 1552 return 0; 1553 } 1554 1555 static void 1556 iwn4965_read_eeprom(struct iwn_softc *sc) 1557 { 1558 uint32_t addr; 1559 uint16_t val; 1560 int i; 1561 1562 /* Read regulatory domain (4 ASCII characters). */ 1563 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1564 1565 /* Read the list of authorized channels (20MHz ones only). */ 1566 for (i = 0; i < 5; i++) { 1567 addr = iwn4965_regulatory_bands[i]; 1568 iwn_read_eeprom_channels(sc, i, addr); 1569 } 1570 1571 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1572 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1573 sc->maxpwr2GHz = val & 0xff; 1574 sc->maxpwr5GHz = val >> 8; 1575 /* Check that EEPROM values are within valid range. */ 1576 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1577 sc->maxpwr5GHz = 38; 1578 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1579 sc->maxpwr2GHz = 38; 1580 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1581 1582 /* Read samples for each TX power group. */ 1583 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1584 sizeof sc->bands); 1585 1586 /* Read voltage at which samples were taken. */ 1587 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1588 sc->eeprom_voltage = (int16_t)le16toh(val); 1589 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1590 1591 #ifdef IWN_DEBUG 1592 /* Print samples. */ 1593 if (iwn_debug > 0) { 1594 for (i = 0; i < IWN_NBANDS; i++) 1595 iwn4965_print_power_group(sc, i); 1596 } 1597 #endif 1598 } 1599 1600 #ifdef IWN_DEBUG 1601 static void 1602 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1603 { 1604 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1605 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1606 int j, c; 1607 1608 aprint_normal("===band %d===\n", i); 1609 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1610 aprint_normal("chan1 num=%d\n", chans[0].num); 1611 for (c = 0; c < 2; c++) { 1612 for (j = 0; j < IWN_NSAMPLES; j++) { 1613 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1614 "power=%d pa_det=%d\n", c, j, 1615 chans[0].samples[c][j].temp, 1616 chans[0].samples[c][j].gain, 1617 chans[0].samples[c][j].power, 1618 chans[0].samples[c][j].pa_det); 1619 } 1620 } 1621 aprint_normal("chan2 num=%d\n", chans[1].num); 1622 for (c = 0; c < 2; c++) { 1623 for (j = 0; j < IWN_NSAMPLES; j++) { 1624 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1625 "power=%d pa_det=%d\n", c, j, 1626 chans[1].samples[c][j].temp, 1627 chans[1].samples[c][j].gain, 1628 chans[1].samples[c][j].power, 1629 chans[1].samples[c][j].pa_det); 1630 } 1631 } 1632 } 1633 #endif 1634 1635 static void 1636 iwn5000_read_eeprom(struct iwn_softc *sc) 1637 { 1638 struct iwn5000_eeprom_calib_hdr hdr; 1639 int32_t volt; 1640 uint32_t base, addr; 1641 uint16_t val; 1642 int i; 1643 1644 /* Read regulatory domain (4 ASCII characters). */ 1645 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1646 base = le16toh(val); 1647 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1648 sc->eeprom_domain, 4); 1649 1650 /* Read the list of authorized channels (20MHz ones only). */ 1651 for (i = 0; i < 5; i++) { 1652 addr = base + iwn5000_regulatory_bands[i]; 1653 iwn_read_eeprom_channels(sc, i, addr); 1654 } 1655 1656 /* Read enhanced TX power information for 6000 Series. */ 1657 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1658 iwn_read_eeprom_enhinfo(sc); 1659 1660 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1661 base = le16toh(val); 1662 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1663 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1664 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1665 sc->calib_ver = hdr.version; 1666 1667 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1668 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1669 sc->hw_type == IWN_HW_REV_TYPE_135 || 1670 sc->hw_type == IWN_HW_REV_TYPE_105) { 1671 sc->eeprom_voltage = le16toh(hdr.volt); 1672 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1673 sc->eeprom_temp = le16toh(val); 1674 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1675 sc->eeprom_rawtemp = le16toh(val); 1676 } 1677 1678 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1679 /* Compute temperature offset. */ 1680 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1681 sc->eeprom_temp = le16toh(val); 1682 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1683 volt = le16toh(val); 1684 sc->temp_off = sc->eeprom_temp - (volt / -5); 1685 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1686 sc->eeprom_temp, volt, sc->temp_off)); 1687 } else { 1688 /* Read crystal calibration. */ 1689 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1690 &sc->eeprom_crystal, sizeof (uint32_t)); 1691 DPRINTF(("crystal calibration 0x%08x\n", 1692 le32toh(sc->eeprom_crystal))); 1693 } 1694 } 1695 1696 static void 1697 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1698 { 1699 struct ieee80211com *ic = &sc->sc_ic; 1700 const struct iwn_chan_band *band = &iwn_bands[n]; 1701 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1702 uint8_t chan; 1703 int i; 1704 1705 iwn_read_prom_data(sc, addr, channels, 1706 band->nchan * sizeof (struct iwn_eeprom_chan)); 1707 1708 for (i = 0; i < band->nchan; i++) { 1709 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1710 continue; 1711 1712 chan = band->chan[i]; 1713 1714 if (n == 0) { /* 2GHz band */ 1715 ic->ic_channels[chan].ic_freq = 1716 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1717 ic->ic_channels[chan].ic_flags = 1718 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1719 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1720 1721 } else { /* 5GHz band */ 1722 /* 1723 * Some adapters support channels 7, 8, 11 and 12 1724 * both in the 2GHz and 4.9GHz bands. 1725 * Because of limitations in our net80211 layer, 1726 * we don't support them in the 4.9GHz band. 1727 */ 1728 if (chan <= 14) 1729 continue; 1730 1731 ic->ic_channels[chan].ic_freq = 1732 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1733 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1734 /* We have at least one valid 5GHz channel. */ 1735 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1736 } 1737 1738 /* Is active scan allowed on this channel? */ 1739 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1740 ic->ic_channels[chan].ic_flags |= 1741 IEEE80211_CHAN_PASSIVE; 1742 } 1743 1744 /* Save maximum allowed TX power for this channel. */ 1745 sc->maxpwr[chan] = channels[i].maxpwr; 1746 1747 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1748 chan, channels[i].flags, sc->maxpwr[chan])); 1749 } 1750 } 1751 1752 static void 1753 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1754 { 1755 struct iwn_eeprom_enhinfo enhinfo[35]; 1756 uint16_t val, base; 1757 int8_t maxpwr; 1758 int i; 1759 1760 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1761 base = le16toh(val); 1762 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1763 enhinfo, sizeof enhinfo); 1764 1765 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1766 for (i = 0; i < __arraycount(enhinfo); i++) { 1767 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1768 continue; /* Skip invalid entries. */ 1769 1770 maxpwr = 0; 1771 if (sc->txchainmask & IWN_ANT_A) 1772 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1773 if (sc->txchainmask & IWN_ANT_B) 1774 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1775 if (sc->txchainmask & IWN_ANT_C) 1776 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1777 if (sc->ntxchains == 2) 1778 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1779 else if (sc->ntxchains == 3) 1780 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1781 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1782 1783 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1784 sc->enh_maxpwr[i] = maxpwr; 1785 } 1786 } 1787 1788 static struct ieee80211_node * 1789 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1790 { 1791 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1792 } 1793 1794 static void 1795 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1796 { 1797 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1798 struct iwn_node *wn = (void *)ni; 1799 uint8_t rate; 1800 int ridx, i; 1801 1802 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1803 /* Start at lowest available bit-rate, AMRR will raise. */ 1804 ni->ni_txrate = 0; 1805 1806 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1807 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1808 /* Map 802.11 rate to HW rate index. */ 1809 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1810 if (iwn_rates[ridx].rate == rate) 1811 break; 1812 wn->ridx[i] = ridx; 1813 } 1814 } 1815 1816 static int 1817 iwn_media_change(struct ifnet *ifp) 1818 { 1819 struct iwn_softc *sc = ifp->if_softc; 1820 struct ieee80211com *ic = &sc->sc_ic; 1821 uint8_t rate, ridx; 1822 int error; 1823 1824 error = ieee80211_media_change(ifp); 1825 if (error != ENETRESET) 1826 return error; 1827 1828 if (ic->ic_fixed_rate != -1) { 1829 rate = ic->ic_sup_rates[ic->ic_curmode]. 1830 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1831 /* Map 802.11 rate to HW rate index. */ 1832 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1833 if (iwn_rates[ridx].rate == rate) 1834 break; 1835 sc->fixed_ridx = ridx; 1836 } 1837 1838 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1839 (IFF_UP | IFF_RUNNING)) { 1840 iwn_stop(ifp, 0); 1841 error = iwn_init(ifp); 1842 } 1843 return error; 1844 } 1845 1846 static int 1847 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1848 { 1849 struct ifnet *ifp = ic->ic_ifp; 1850 struct iwn_softc *sc = ifp->if_softc; 1851 int error; 1852 1853 callout_stop(&sc->calib_to); 1854 1855 switch (nstate) { 1856 case IEEE80211_S_SCAN: 1857 /* XXX Do not abort a running scan. */ 1858 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1859 if (ic->ic_state != nstate) 1860 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1861 "while scanning(%d) ignored\n", nstate, 1862 ic->ic_state); 1863 break; 1864 } 1865 1866 /* XXX Not sure if call and flags are needed. */ 1867 ieee80211_node_table_reset(&ic->ic_scan); 1868 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1869 sc->sc_flags |= IWN_FLAG_SCANNING; 1870 1871 /* Make the link LED blink while we're scanning. */ 1872 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1873 1874 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1875 aprint_error_dev(sc->sc_dev, 1876 "could not initiate scan\n"); 1877 return error; 1878 } 1879 ic->ic_state = nstate; 1880 return 0; 1881 1882 case IEEE80211_S_ASSOC: 1883 if (ic->ic_state != IEEE80211_S_RUN) 1884 break; 1885 /* FALLTHROUGH */ 1886 case IEEE80211_S_AUTH: 1887 /* Reset state to handle reassociations correctly. */ 1888 sc->rxon.associd = 0; 1889 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1890 sc->calib.state = IWN_CALIB_STATE_INIT; 1891 1892 if ((error = iwn_auth(sc)) != 0) { 1893 aprint_error_dev(sc->sc_dev, 1894 "could not move to auth state\n"); 1895 return error; 1896 } 1897 break; 1898 1899 case IEEE80211_S_RUN: 1900 if ((error = iwn_run(sc)) != 0) { 1901 aprint_error_dev(sc->sc_dev, 1902 "could not move to run state\n"); 1903 return error; 1904 } 1905 break; 1906 1907 case IEEE80211_S_INIT: 1908 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1909 sc->calib.state = IWN_CALIB_STATE_INIT; 1910 break; 1911 } 1912 1913 return sc->sc_newstate(ic, nstate, arg); 1914 } 1915 1916 static void 1917 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1918 { 1919 struct iwn_softc *sc = arg; 1920 struct iwn_node *wn = (struct iwn_node *)ni; 1921 1922 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1923 } 1924 1925 static void 1926 iwn_calib_timeout(void *arg) 1927 { 1928 struct iwn_softc *sc = arg; 1929 struct ieee80211com *ic = &sc->sc_ic; 1930 int s; 1931 1932 s = splnet(); 1933 if (ic->ic_fixed_rate == -1) { 1934 if (ic->ic_opmode == IEEE80211_M_STA) 1935 iwn_iter_func(sc, ic->ic_bss); 1936 else 1937 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1938 } 1939 /* Force automatic TX power calibration every 60 secs. */ 1940 if (++sc->calib_cnt >= 120) { 1941 uint32_t flags = 0; 1942 1943 DPRINTF(("sending request for statistics\n")); 1944 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1945 sizeof flags, 1); 1946 sc->calib_cnt = 0; 1947 } 1948 splx(s); 1949 1950 /* Automatic rate control triggered every 500ms. */ 1951 callout_schedule(&sc->calib_to, hz/2); 1952 } 1953 1954 /* 1955 * Process an RX_PHY firmware notification. This is usually immediately 1956 * followed by an MPDU_RX_DONE notification. 1957 */ 1958 static void 1959 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1960 struct iwn_rx_data *data) 1961 { 1962 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1963 1964 DPRINTFN(2, ("received PHY stats\n")); 1965 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1966 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1967 1968 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1969 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1970 sc->last_rx_valid = 1; 1971 } 1972 1973 /* 1974 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1975 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1976 */ 1977 static void 1978 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1979 struct iwn_rx_data *data) 1980 { 1981 struct iwn_ops *ops = &sc->ops; 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 struct ifnet *ifp = ic->ic_ifp; 1984 struct iwn_rx_ring *ring = &sc->rxq; 1985 struct ieee80211_frame *wh; 1986 struct ieee80211_node *ni; 1987 struct mbuf *m, *m1; 1988 struct iwn_rx_stat *stat; 1989 char *head; 1990 uint32_t flags; 1991 int error, len, rssi; 1992 1993 if (desc->type == IWN_MPDU_RX_DONE) { 1994 /* Check for prior RX_PHY notification. */ 1995 if (!sc->last_rx_valid) { 1996 DPRINTF(("missing RX_PHY\n")); 1997 return; 1998 } 1999 sc->last_rx_valid = 0; 2000 stat = &sc->last_rx_stat; 2001 } else 2002 stat = (struct iwn_rx_stat *)(desc + 1); 2003 2004 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2005 BUS_DMASYNC_POSTREAD); 2006 2007 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2008 aprint_error_dev(sc->sc_dev, 2009 "invalid RX statistic header\n"); 2010 return; 2011 } 2012 if (desc->type == IWN_MPDU_RX_DONE) { 2013 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2014 head = (char *)(mpdu + 1); 2015 len = le16toh(mpdu->len); 2016 } else { 2017 head = (char *)(stat + 1) + stat->cfg_phy_len; 2018 len = le16toh(stat->len); 2019 } 2020 2021 flags = le32toh(*(uint32_t *)(head + len)); 2022 2023 /* Discard frames with a bad FCS early. */ 2024 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2025 DPRINTFN(2, ("RX flags error %x\n", flags)); 2026 ifp->if_ierrors++; 2027 return; 2028 } 2029 /* Discard frames that are too short. */ 2030 if (len < sizeof (*wh)) { 2031 DPRINTF(("frame too short: %d\n", len)); 2032 ic->ic_stats.is_rx_tooshort++; 2033 ifp->if_ierrors++; 2034 return; 2035 } 2036 2037 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2038 if (m1 == NULL) { 2039 ic->ic_stats.is_rx_nobuf++; 2040 ifp->if_ierrors++; 2041 return; 2042 } 2043 bus_dmamap_unload(sc->sc_dmat, data->map); 2044 2045 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2046 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2047 if (error != 0) { 2048 m_freem(m1); 2049 2050 /* Try to reload the old mbuf. */ 2051 error = bus_dmamap_load(sc->sc_dmat, data->map, 2052 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2053 BUS_DMA_NOWAIT | BUS_DMA_READ); 2054 if (error != 0) { 2055 panic("%s: could not load old RX mbuf", 2056 device_xname(sc->sc_dev)); 2057 } 2058 /* Physical address may have changed. */ 2059 ring->desc[ring->cur] = 2060 htole32(data->map->dm_segs[0].ds_addr >> 8); 2061 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2062 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2063 BUS_DMASYNC_PREWRITE); 2064 ifp->if_ierrors++; 2065 return; 2066 } 2067 2068 m = data->m; 2069 data->m = m1; 2070 /* Update RX descriptor. */ 2071 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2072 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2073 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2074 BUS_DMASYNC_PREWRITE); 2075 2076 /* Finalize mbuf. */ 2077 m->m_pkthdr.rcvif = ifp; 2078 m->m_data = head; 2079 m->m_pkthdr.len = m->m_len = len; 2080 2081 /* Grab a reference to the source node. */ 2082 wh = mtod(m, struct ieee80211_frame *); 2083 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2084 2085 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2086 /* NetBSD does decryption in ieee80211_input. */ 2087 2088 rssi = ops->get_rssi(stat); 2089 2090 /* XXX Added for NetBSD: scans never stop without it */ 2091 if (ic->ic_state == IEEE80211_S_SCAN) 2092 iwn_fix_channel(ic, m); 2093 2094 if (sc->sc_drvbpf != NULL) { 2095 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2096 2097 tap->wr_flags = 0; 2098 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2099 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2100 tap->wr_chan_freq = 2101 htole16(ic->ic_channels[stat->chan].ic_freq); 2102 tap->wr_chan_flags = 2103 htole16(ic->ic_channels[stat->chan].ic_flags); 2104 tap->wr_dbm_antsignal = (int8_t)rssi; 2105 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2106 tap->wr_tsft = stat->tstamp; 2107 switch (stat->rate) { 2108 /* CCK rates. */ 2109 case 10: tap->wr_rate = 2; break; 2110 case 20: tap->wr_rate = 4; break; 2111 case 55: tap->wr_rate = 11; break; 2112 case 110: tap->wr_rate = 22; break; 2113 /* OFDM rates. */ 2114 case 0xd: tap->wr_rate = 12; break; 2115 case 0xf: tap->wr_rate = 18; break; 2116 case 0x5: tap->wr_rate = 24; break; 2117 case 0x7: tap->wr_rate = 36; break; 2118 case 0x9: tap->wr_rate = 48; break; 2119 case 0xb: tap->wr_rate = 72; break; 2120 case 0x1: tap->wr_rate = 96; break; 2121 case 0x3: tap->wr_rate = 108; break; 2122 /* Unknown rate: should not happen. */ 2123 default: tap->wr_rate = 0; 2124 } 2125 2126 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2127 } 2128 2129 /* Send the frame to the 802.11 layer. */ 2130 ieee80211_input(ic, m, ni, rssi, 0); 2131 2132 /* Node is no longer needed. */ 2133 ieee80211_free_node(ni); 2134 } 2135 2136 #ifndef IEEE80211_NO_HT 2137 /* Process an incoming Compressed BlockAck. */ 2138 static void 2139 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2140 struct iwn_rx_data *data) 2141 { 2142 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2143 struct iwn_tx_ring *txq; 2144 2145 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2146 BUS_DMASYNC_POSTREAD); 2147 2148 txq = &sc->txq[le16toh(ba->qid)]; 2149 /* XXX TBD */ 2150 } 2151 #endif 2152 2153 /* 2154 * Process a CALIBRATION_RESULT notification sent by the initialization 2155 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2156 */ 2157 static void 2158 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2159 struct iwn_rx_data *data) 2160 { 2161 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2162 int len, idx = -1; 2163 2164 /* Runtime firmware should not send such a notification. */ 2165 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2166 return; 2167 2168 len = (le32toh(desc->len) & 0x3fff) - 4; 2169 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2170 BUS_DMASYNC_POSTREAD); 2171 2172 switch (calib->code) { 2173 case IWN5000_PHY_CALIB_DC: 2174 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2175 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2176 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2177 sc->hw_type == IWN_HW_REV_TYPE_135 || 2178 sc->hw_type == IWN_HW_REV_TYPE_105) 2179 idx = 0; 2180 break; 2181 case IWN5000_PHY_CALIB_LO: 2182 idx = 1; 2183 break; 2184 case IWN5000_PHY_CALIB_TX_IQ: 2185 idx = 2; 2186 break; 2187 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2188 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2189 sc->hw_type != IWN_HW_REV_TYPE_5150) 2190 idx = 3; 2191 break; 2192 case IWN5000_PHY_CALIB_BASE_BAND: 2193 idx = 4; 2194 break; 2195 } 2196 if (idx == -1) /* Ignore other results. */ 2197 return; 2198 2199 /* Save calibration result. */ 2200 if (sc->calibcmd[idx].buf != NULL) 2201 free(sc->calibcmd[idx].buf, M_DEVBUF); 2202 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2203 if (sc->calibcmd[idx].buf == NULL) { 2204 DPRINTF(("not enough memory for calibration result %d\n", 2205 calib->code)); 2206 return; 2207 } 2208 DPRINTF(("saving calibration result code=%d len=%d\n", 2209 calib->code, len)); 2210 sc->calibcmd[idx].len = len; 2211 memcpy(sc->calibcmd[idx].buf, calib, len); 2212 } 2213 2214 /* 2215 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2216 * The latter is sent by the firmware after each received beacon. 2217 */ 2218 static void 2219 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2220 struct iwn_rx_data *data) 2221 { 2222 struct iwn_ops *ops = &sc->ops; 2223 struct ieee80211com *ic = &sc->sc_ic; 2224 struct iwn_calib_state *calib = &sc->calib; 2225 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2226 int temp; 2227 2228 /* Ignore statistics received during a scan. */ 2229 if (ic->ic_state != IEEE80211_S_RUN) 2230 return; 2231 2232 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2233 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2234 2235 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2236 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2237 2238 /* Test if temperature has changed. */ 2239 if (stats->general.temp != sc->rawtemp) { 2240 /* Convert "raw" temperature to degC. */ 2241 sc->rawtemp = stats->general.temp; 2242 temp = ops->get_temperature(sc); 2243 DPRINTFN(2, ("temperature=%dC\n", temp)); 2244 2245 /* Update TX power if need be (4965AGN only). */ 2246 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2247 iwn4965_power_calibration(sc, temp); 2248 } 2249 2250 if (desc->type != IWN_BEACON_STATISTICS) 2251 return; /* Reply to a statistics request. */ 2252 2253 sc->noise = iwn_get_noise(&stats->rx.general); 2254 2255 /* Test that RSSI and noise are present in stats report. */ 2256 if (le32toh(stats->rx.general.flags) != 1) { 2257 DPRINTF(("received statistics without RSSI\n")); 2258 return; 2259 } 2260 2261 /* 2262 * XXX Differential gain calibration makes the 6005 firmware 2263 * crap out, so skip it for now. This effectively disables 2264 * sensitivity tuning as well. 2265 */ 2266 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2267 return; 2268 2269 if (calib->state == IWN_CALIB_STATE_ASSOC) 2270 iwn_collect_noise(sc, &stats->rx.general); 2271 else if (calib->state == IWN_CALIB_STATE_RUN) 2272 iwn_tune_sensitivity(sc, &stats->rx); 2273 } 2274 2275 /* 2276 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2277 * and 5000 adapters have different incompatible TX status formats. 2278 */ 2279 static void 2280 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2281 struct iwn_rx_data *data) 2282 { 2283 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2284 2285 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2286 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2287 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2288 } 2289 2290 static void 2291 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2292 struct iwn_rx_data *data) 2293 { 2294 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2295 2296 #ifdef notyet 2297 /* Reset TX scheduler slot. */ 2298 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2299 #endif 2300 2301 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2302 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2303 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2304 } 2305 2306 /* 2307 * Adapter-independent backend for TX_DONE firmware notifications. 2308 */ 2309 static void 2310 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2311 uint8_t status) 2312 { 2313 struct ieee80211com *ic = &sc->sc_ic; 2314 struct ifnet *ifp = ic->ic_ifp; 2315 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2316 struct iwn_tx_data *data = &ring->data[desc->idx]; 2317 struct iwn_node *wn = (struct iwn_node *)data->ni; 2318 2319 /* Update rate control statistics. */ 2320 wn->amn.amn_txcnt++; 2321 if (ackfailcnt > 0) 2322 wn->amn.amn_retrycnt++; 2323 2324 if (status != 1 && status != 2) 2325 ifp->if_oerrors++; 2326 else 2327 ifp->if_opackets++; 2328 2329 /* Unmap and free mbuf. */ 2330 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2331 BUS_DMASYNC_POSTWRITE); 2332 bus_dmamap_unload(sc->sc_dmat, data->map); 2333 m_freem(data->m); 2334 data->m = NULL; 2335 ieee80211_free_node(data->ni); 2336 data->ni = NULL; 2337 2338 sc->sc_tx_timer = 0; 2339 if (--ring->queued < IWN_TX_RING_LOMARK) { 2340 sc->qfullmsk &= ~(1 << ring->qid); 2341 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2342 ifp->if_flags &= ~IFF_OACTIVE; 2343 (*ifp->if_start)(ifp); 2344 } 2345 } 2346 } 2347 2348 /* 2349 * Process a "command done" firmware notification. This is where we wakeup 2350 * processes waiting for a synchronous command completion. 2351 */ 2352 static void 2353 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2354 { 2355 struct iwn_tx_ring *ring = &sc->txq[4]; 2356 struct iwn_tx_data *data; 2357 2358 if ((desc->qid & 0xf) != 4) 2359 return; /* Not a command ack. */ 2360 2361 data = &ring->data[desc->idx]; 2362 2363 /* If the command was mapped in an mbuf, free it. */ 2364 if (data->m != NULL) { 2365 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2366 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2367 bus_dmamap_unload(sc->sc_dmat, data->map); 2368 m_freem(data->m); 2369 data->m = NULL; 2370 } 2371 wakeup(&ring->desc[desc->idx]); 2372 } 2373 2374 /* 2375 * Process an INT_FH_RX or INT_SW_RX interrupt. 2376 */ 2377 static void 2378 iwn_notif_intr(struct iwn_softc *sc) 2379 { 2380 struct iwn_ops *ops = &sc->ops; 2381 struct ieee80211com *ic = &sc->sc_ic; 2382 struct ifnet *ifp = ic->ic_ifp; 2383 uint16_t hw; 2384 2385 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2386 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2387 2388 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2389 while (sc->rxq.cur != hw) { 2390 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2391 struct iwn_rx_desc *desc; 2392 2393 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2394 BUS_DMASYNC_POSTREAD); 2395 desc = mtod(data->m, struct iwn_rx_desc *); 2396 2397 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2398 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2399 2400 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2401 iwn_cmd_done(sc, desc); 2402 2403 switch (desc->type) { 2404 case IWN_RX_PHY: 2405 iwn_rx_phy(sc, desc, data); 2406 break; 2407 2408 case IWN_RX_DONE: /* 4965AGN only. */ 2409 case IWN_MPDU_RX_DONE: 2410 /* An 802.11 frame has been received. */ 2411 iwn_rx_done(sc, desc, data); 2412 break; 2413 #ifndef IEEE80211_NO_HT 2414 case IWN_RX_COMPRESSED_BA: 2415 /* A Compressed BlockAck has been received. */ 2416 iwn_rx_compressed_ba(sc, desc, data); 2417 break; 2418 #endif 2419 case IWN_TX_DONE: 2420 /* An 802.11 frame has been transmitted. */ 2421 ops->tx_done(sc, desc, data); 2422 break; 2423 2424 case IWN_RX_STATISTICS: 2425 case IWN_BEACON_STATISTICS: 2426 iwn_rx_statistics(sc, desc, data); 2427 break; 2428 2429 case IWN_BEACON_MISSED: 2430 { 2431 struct iwn_beacon_missed *miss = 2432 (struct iwn_beacon_missed *)(desc + 1); 2433 2434 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2435 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2436 /* 2437 * If more than 5 consecutive beacons are missed, 2438 * reinitialize the sensitivity state machine. 2439 */ 2440 DPRINTF(("beacons missed %d/%d\n", 2441 le32toh(miss->consecutive), le32toh(miss->total))); 2442 if (ic->ic_state == IEEE80211_S_RUN && 2443 le32toh(miss->consecutive) > 5) 2444 (void)iwn_init_sensitivity(sc); 2445 break; 2446 } 2447 case IWN_UC_READY: 2448 { 2449 struct iwn_ucode_info *uc = 2450 (struct iwn_ucode_info *)(desc + 1); 2451 2452 /* The microcontroller is ready. */ 2453 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2454 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2455 DPRINTF(("microcode alive notification version=%d.%d " 2456 "subtype=%x alive=%x\n", uc->major, uc->minor, 2457 uc->subtype, le32toh(uc->valid))); 2458 2459 if (le32toh(uc->valid) != 1) { 2460 aprint_error_dev(sc->sc_dev, 2461 "microcontroller initialization " 2462 "failed\n"); 2463 break; 2464 } 2465 if (uc->subtype == IWN_UCODE_INIT) { 2466 /* Save microcontroller report. */ 2467 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2468 } 2469 /* Save the address of the error log in SRAM. */ 2470 sc->errptr = le32toh(uc->errptr); 2471 break; 2472 } 2473 case IWN_STATE_CHANGED: 2474 { 2475 uint32_t *status = (uint32_t *)(desc + 1); 2476 2477 /* Enabled/disabled notification. */ 2478 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2479 sizeof (*status), BUS_DMASYNC_POSTREAD); 2480 DPRINTF(("state changed to %x\n", le32toh(*status))); 2481 2482 if (le32toh(*status) & 1) { 2483 /* The radio button has to be pushed. */ 2484 aprint_error_dev(sc->sc_dev, 2485 "Radio transmitter is off\n"); 2486 /* Turn the interface down. */ 2487 ifp->if_flags &= ~IFF_UP; 2488 iwn_stop(ifp, 1); 2489 return; /* No further processing. */ 2490 } 2491 break; 2492 } 2493 case IWN_START_SCAN: 2494 { 2495 struct iwn_start_scan *scan = 2496 (struct iwn_start_scan *)(desc + 1); 2497 2498 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2499 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2500 DPRINTFN(2, ("scanning channel %d status %x\n", 2501 scan->chan, le32toh(scan->status))); 2502 2503 /* Fix current channel. */ 2504 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2505 break; 2506 } 2507 case IWN_STOP_SCAN: 2508 { 2509 struct iwn_stop_scan *scan = 2510 (struct iwn_stop_scan *)(desc + 1); 2511 2512 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2513 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2514 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2515 scan->nchan, scan->status, scan->chan)); 2516 2517 if (scan->status == 1 && scan->chan <= 14 && 2518 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2519 /* 2520 * We just finished scanning 2GHz channels, 2521 * start scanning 5GHz ones. 2522 */ 2523 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2524 break; 2525 } 2526 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2527 ieee80211_end_scan(ic); 2528 break; 2529 } 2530 case IWN5000_CALIBRATION_RESULT: 2531 iwn5000_rx_calib_results(sc, desc, data); 2532 break; 2533 2534 case IWN5000_CALIBRATION_DONE: 2535 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2536 wakeup(sc); 2537 break; 2538 } 2539 2540 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2541 } 2542 2543 /* Tell the firmware what we have processed. */ 2544 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2545 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2546 } 2547 2548 /* 2549 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2550 * from power-down sleep mode. 2551 */ 2552 static void 2553 iwn_wakeup_intr(struct iwn_softc *sc) 2554 { 2555 int qid; 2556 2557 DPRINTF(("ucode wakeup from power-down sleep\n")); 2558 2559 /* Wakeup RX and TX rings. */ 2560 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2561 for (qid = 0; qid < sc->ntxqs; qid++) { 2562 struct iwn_tx_ring *ring = &sc->txq[qid]; 2563 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2564 } 2565 } 2566 2567 /* 2568 * Dump the error log of the firmware when a firmware panic occurs. Although 2569 * we can't debug the firmware because it is neither open source nor free, it 2570 * can help us to identify certain classes of problems. 2571 */ 2572 static void 2573 iwn_fatal_intr(struct iwn_softc *sc) 2574 { 2575 struct iwn_fw_dump dump; 2576 int i; 2577 2578 /* Force a complete recalibration on next init. */ 2579 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2580 2581 /* Check that the error log address is valid. */ 2582 if (sc->errptr < IWN_FW_DATA_BASE || 2583 sc->errptr + sizeof (dump) > 2584 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2585 aprint_error_dev(sc->sc_dev, 2586 "bad firmware error log address 0x%08x\n", sc->errptr); 2587 return; 2588 } 2589 if (iwn_nic_lock(sc) != 0) { 2590 aprint_error_dev(sc->sc_dev, 2591 "could not read firmware error log\n"); 2592 return; 2593 } 2594 /* Read firmware error log from SRAM. */ 2595 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2596 sizeof (dump) / sizeof (uint32_t)); 2597 iwn_nic_unlock(sc); 2598 2599 if (dump.valid == 0) { 2600 aprint_error_dev(sc->sc_dev, 2601 "firmware error log is empty\n"); 2602 return; 2603 } 2604 aprint_error("firmware error log:\n"); 2605 aprint_error(" error type = \"%s\" (0x%08X)\n", 2606 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2607 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2608 dump.id); 2609 aprint_error(" program counter = 0x%08X\n", dump.pc); 2610 aprint_error(" source line = 0x%08X\n", dump.src_line); 2611 aprint_error(" error data = 0x%08X%08X\n", 2612 dump.error_data[0], dump.error_data[1]); 2613 aprint_error(" branch link = 0x%08X%08X\n", 2614 dump.branch_link[0], dump.branch_link[1]); 2615 aprint_error(" interrupt link = 0x%08X%08X\n", 2616 dump.interrupt_link[0], dump.interrupt_link[1]); 2617 aprint_error(" time = %u\n", dump.time[0]); 2618 2619 /* Dump driver status (TX and RX rings) while we're here. */ 2620 aprint_error("driver status:\n"); 2621 for (i = 0; i < sc->ntxqs; i++) { 2622 struct iwn_tx_ring *ring = &sc->txq[i]; 2623 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2624 i, ring->qid, ring->cur, ring->queued); 2625 } 2626 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2627 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2628 } 2629 2630 static int 2631 iwn_intr(void *arg) 2632 { 2633 struct iwn_softc *sc = arg; 2634 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2635 uint32_t r1, r2, tmp; 2636 2637 /* Disable interrupts. */ 2638 IWN_WRITE(sc, IWN_INT_MASK, 0); 2639 2640 /* Read interrupts from ICT (fast) or from registers (slow). */ 2641 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2642 tmp = 0; 2643 while (sc->ict[sc->ict_cur] != 0) { 2644 tmp |= sc->ict[sc->ict_cur]; 2645 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2646 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2647 } 2648 tmp = le32toh(tmp); 2649 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2650 tmp = 0; 2651 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2652 tmp |= 0x8000; 2653 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2654 r2 = 0; /* Unused. */ 2655 } else { 2656 r1 = IWN_READ(sc, IWN_INT); 2657 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2658 return 0; /* Hardware gone! */ 2659 r2 = IWN_READ(sc, IWN_FH_INT); 2660 } 2661 if (r1 == 0 && r2 == 0) { 2662 if (ifp->if_flags & IFF_UP) 2663 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2664 return 0; /* Interrupt not for us. */ 2665 } 2666 2667 /* Acknowledge interrupts. */ 2668 IWN_WRITE(sc, IWN_INT, r1); 2669 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2670 IWN_WRITE(sc, IWN_FH_INT, r2); 2671 2672 if (r1 & IWN_INT_RF_TOGGLED) { 2673 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2674 aprint_error_dev(sc->sc_dev, 2675 "RF switch: radio %s\n", 2676 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2677 } 2678 if (r1 & IWN_INT_CT_REACHED) { 2679 aprint_error_dev(sc->sc_dev, 2680 "critical temperature reached!\n"); 2681 } 2682 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2683 aprint_error_dev(sc->sc_dev, 2684 "fatal firmware error\n"); 2685 /* Dump firmware error log and stop. */ 2686 iwn_fatal_intr(sc); 2687 ifp->if_flags &= ~IFF_UP; 2688 iwn_stop(ifp, 1); 2689 return 1; 2690 } 2691 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2692 (r2 & IWN_FH_INT_RX)) { 2693 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2694 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2695 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2696 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2697 IWN_INT_PERIODIC_DIS); 2698 iwn_notif_intr(sc); 2699 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2700 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2701 IWN_INT_PERIODIC_ENA); 2702 } 2703 } else 2704 iwn_notif_intr(sc); 2705 } 2706 2707 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2708 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2709 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2710 wakeup(sc); /* FH DMA transfer completed. */ 2711 } 2712 2713 if (r1 & IWN_INT_ALIVE) 2714 wakeup(sc); /* Firmware is alive. */ 2715 2716 if (r1 & IWN_INT_WAKEUP) 2717 iwn_wakeup_intr(sc); 2718 2719 /* Re-enable interrupts. */ 2720 if (ifp->if_flags & IFF_UP) 2721 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2722 2723 return 1; 2724 } 2725 2726 /* 2727 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2728 * 5000 adapters use a slightly different format). 2729 */ 2730 static void 2731 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2732 uint16_t len) 2733 { 2734 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2735 2736 *w = htole16(len + 8); 2737 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2738 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2739 sizeof (uint16_t), 2740 BUS_DMASYNC_PREWRITE); 2741 if (idx < IWN_SCHED_WINSZ) { 2742 *(w + IWN_TX_RING_COUNT) = *w; 2743 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2744 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2745 (char *)(void *)sc->sched_dma.vaddr, 2746 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2747 } 2748 } 2749 2750 static void 2751 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2752 uint16_t len) 2753 { 2754 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2755 2756 *w = htole16(id << 12 | (len + 8)); 2757 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2758 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2759 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2760 if (idx < IWN_SCHED_WINSZ) { 2761 *(w + IWN_TX_RING_COUNT) = *w; 2762 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2763 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2764 (char *)(void *)sc->sched_dma.vaddr, 2765 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2766 } 2767 } 2768 2769 #ifdef notyet 2770 static void 2771 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2772 { 2773 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2774 2775 *w = (*w & htole16(0xf000)) | htole16(1); 2776 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2777 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2778 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2779 if (idx < IWN_SCHED_WINSZ) { 2780 *(w + IWN_TX_RING_COUNT) = *w; 2781 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2782 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2783 (char *)(void *)sc->sched_dma.vaddr, 2784 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2785 } 2786 } 2787 #endif 2788 2789 static int 2790 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2791 { 2792 struct ieee80211com *ic = &sc->sc_ic; 2793 struct iwn_node *wn = (void *)ni; 2794 struct iwn_tx_ring *ring; 2795 struct iwn_tx_desc *desc; 2796 struct iwn_tx_data *data; 2797 struct iwn_tx_cmd *cmd; 2798 struct iwn_cmd_data *tx; 2799 const struct iwn_rate *rinfo; 2800 struct ieee80211_frame *wh; 2801 struct ieee80211_key *k = NULL; 2802 struct mbuf *m1; 2803 uint32_t flags; 2804 u_int hdrlen; 2805 bus_dma_segment_t *seg; 2806 uint8_t tid, ridx, txant, type; 2807 int i, totlen, error, pad; 2808 2809 const struct chanAccParams *cap; 2810 int noack; 2811 int hdrlen2; 2812 2813 wh = mtod(m, struct ieee80211_frame *); 2814 hdrlen = ieee80211_anyhdrsize(wh); 2815 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2816 2817 hdrlen2 = (ieee80211_has_qos(wh)) ? 2818 sizeof (struct ieee80211_qosframe) : 2819 sizeof (struct ieee80211_frame); 2820 2821 if (hdrlen != hdrlen2) 2822 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2823 hdrlen, hdrlen2); 2824 2825 /* XXX OpenBSD sets a different tid when using QOS */ 2826 tid = 0; 2827 if (ieee80211_has_qos(wh)) { 2828 cap = &ic->ic_wme.wme_chanParams; 2829 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2830 } 2831 else 2832 noack = 0; 2833 2834 ring = &sc->txq[ac]; 2835 desc = &ring->desc[ring->cur]; 2836 data = &ring->data[ring->cur]; 2837 2838 /* Choose a TX rate index. */ 2839 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2840 type != IEEE80211_FC0_TYPE_DATA) { 2841 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2842 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2843 } else if (ic->ic_fixed_rate != -1) { 2844 ridx = sc->fixed_ridx; 2845 } else 2846 ridx = wn->ridx[ni->ni_txrate]; 2847 rinfo = &iwn_rates[ridx]; 2848 2849 /* Encrypt the frame if need be. */ 2850 /* 2851 * XXX For now, NetBSD swaps the encryption and bpf sections 2852 * in order to match old code and other drivers. Tests with 2853 * tcpdump indicates that the order is irrelevant, however, 2854 * as bpf produces unencrypted data for both ordering choices. 2855 */ 2856 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2857 k = ieee80211_crypto_encap(ic, ni, m); 2858 if (k == NULL) { 2859 m_freem(m); 2860 return ENOBUFS; 2861 } 2862 /* Packet header may have moved, reset our local pointer. */ 2863 wh = mtod(m, struct ieee80211_frame *); 2864 } 2865 totlen = m->m_pkthdr.len; 2866 2867 if (sc->sc_drvbpf != NULL) { 2868 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2869 2870 tap->wt_flags = 0; 2871 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2872 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2873 tap->wt_rate = rinfo->rate; 2874 tap->wt_hwqueue = ac; 2875 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2876 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2877 2878 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2879 } 2880 2881 /* Prepare TX firmware command. */ 2882 cmd = &ring->cmd[ring->cur]; 2883 cmd->code = IWN_CMD_TX_DATA; 2884 cmd->flags = 0; 2885 cmd->qid = ring->qid; 2886 cmd->idx = ring->cur; 2887 2888 tx = (struct iwn_cmd_data *)cmd->data; 2889 /* NB: No need to clear tx, all fields are reinitialized here. */ 2890 tx->scratch = 0; /* clear "scratch" area */ 2891 2892 flags = 0; 2893 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2894 /* Unicast frame, check if an ACK is expected. */ 2895 if (!noack) 2896 flags |= IWN_TX_NEED_ACK; 2897 } 2898 2899 #ifdef notyet 2900 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2901 if ((wh->i_fc[0] & 2902 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2903 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2904 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2905 #endif 2906 2907 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2908 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2909 2910 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2911 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2912 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2913 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2914 flags |= IWN_TX_NEED_RTS; 2915 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2916 ridx >= IWN_RIDX_OFDM6) { 2917 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2918 flags |= IWN_TX_NEED_CTS; 2919 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2920 flags |= IWN_TX_NEED_RTS; 2921 } 2922 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2923 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2924 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2925 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2926 flags |= IWN_TX_NEED_PROTECTION; 2927 } else 2928 flags |= IWN_TX_FULL_TXOP; 2929 } 2930 } 2931 2932 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2933 type != IEEE80211_FC0_TYPE_DATA) 2934 tx->id = sc->broadcast_id; 2935 else 2936 tx->id = wn->id; 2937 2938 if (type == IEEE80211_FC0_TYPE_MGT) { 2939 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2940 2941 #ifndef IEEE80211_STA_ONLY 2942 /* Tell HW to set timestamp in probe responses. */ 2943 /* XXX NetBSD rev 1.11 added probe requests here but */ 2944 /* probe requests do not take timestamps (from Bergamini). */ 2945 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2946 flags |= IWN_TX_INSERT_TSTAMP; 2947 #endif 2948 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2949 /* changes here. These are not needed (from Bergamini). */ 2950 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2951 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2952 tx->timeout = htole16(3); 2953 else 2954 tx->timeout = htole16(2); 2955 } else 2956 tx->timeout = htole16(0); 2957 2958 if (hdrlen & 3) { 2959 /* First segment length must be a multiple of 4. */ 2960 flags |= IWN_TX_NEED_PADDING; 2961 pad = 4 - (hdrlen & 3); 2962 } else 2963 pad = 0; 2964 2965 tx->len = htole16(totlen); 2966 tx->tid = tid; 2967 tx->rts_ntries = 60; 2968 tx->data_ntries = 15; 2969 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2970 tx->plcp = rinfo->plcp; 2971 tx->rflags = rinfo->flags; 2972 if (tx->id == sc->broadcast_id) { 2973 /* Group or management frame. */ 2974 tx->linkq = 0; 2975 /* XXX Alternate between antenna A and B? */ 2976 txant = IWN_LSB(sc->txchainmask); 2977 tx->rflags |= IWN_RFLAG_ANT(txant); 2978 } else { 2979 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2980 flags |= IWN_TX_LINKQ; /* enable MRR */ 2981 } 2982 /* Set physical address of "scratch area". */ 2983 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2984 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2985 2986 /* Copy 802.11 header in TX command. */ 2987 /* XXX NetBSD changed this in rev 1.20 */ 2988 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2989 2990 /* Trim 802.11 header. */ 2991 m_adj(m, hdrlen); 2992 tx->security = 0; 2993 tx->flags = htole32(flags); 2994 2995 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2996 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2997 if (error != 0) { 2998 if (error != EFBIG) { 2999 aprint_error_dev(sc->sc_dev, 3000 "can't map mbuf (error %d)\n", error); 3001 m_freem(m); 3002 return error; 3003 } 3004 /* Too many DMA segments, linearize mbuf. */ 3005 MGETHDR(m1, M_DONTWAIT, MT_DATA); 3006 if (m1 == NULL) { 3007 m_freem(m); 3008 return ENOBUFS; 3009 } 3010 if (m->m_pkthdr.len > MHLEN) { 3011 MCLGET(m1, M_DONTWAIT); 3012 if (!(m1->m_flags & M_EXT)) { 3013 m_freem(m); 3014 m_freem(m1); 3015 return ENOBUFS; 3016 } 3017 } 3018 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 3019 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3020 m_freem(m); 3021 m = m1; 3022 3023 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3024 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3025 if (error != 0) { 3026 aprint_error_dev(sc->sc_dev, 3027 "can't map mbuf (error %d)\n", error); 3028 m_freem(m); 3029 return error; 3030 } 3031 } 3032 3033 data->m = m; 3034 data->ni = ni; 3035 3036 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3037 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3038 3039 /* Fill TX descriptor. */ 3040 desc->nsegs = 1 + data->map->dm_nsegs; 3041 /* First DMA segment is used by the TX command. */ 3042 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3043 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3044 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3045 /* Other DMA segments are for data payload. */ 3046 seg = data->map->dm_segs; 3047 for (i = 1; i <= data->map->dm_nsegs; i++) { 3048 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3049 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3050 seg->ds_len << 4); 3051 seg++; 3052 } 3053 3054 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3055 BUS_DMASYNC_PREWRITE); 3056 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3057 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3058 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3059 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3060 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3061 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3062 3063 #ifdef notyet 3064 /* Update TX scheduler. */ 3065 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3066 #endif 3067 3068 /* Kick TX ring. */ 3069 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3070 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3071 3072 /* Mark TX ring as full if we reach a certain threshold. */ 3073 if (++ring->queued > IWN_TX_RING_HIMARK) 3074 sc->qfullmsk |= 1 << ring->qid; 3075 3076 return 0; 3077 } 3078 3079 static void 3080 iwn_start(struct ifnet *ifp) 3081 { 3082 struct iwn_softc *sc = ifp->if_softc; 3083 struct ieee80211com *ic = &sc->sc_ic; 3084 struct ieee80211_node *ni; 3085 struct ether_header *eh; 3086 struct mbuf *m; 3087 int ac; 3088 3089 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3090 return; 3091 3092 for (;;) { 3093 if (sc->qfullmsk != 0) { 3094 ifp->if_flags |= IFF_OACTIVE; 3095 break; 3096 } 3097 /* Send pending management frames first. */ 3098 IF_DEQUEUE(&ic->ic_mgtq, m); 3099 if (m != NULL) { 3100 ni = (void *)m->m_pkthdr.rcvif; 3101 ac = 0; 3102 goto sendit; 3103 } 3104 if (ic->ic_state != IEEE80211_S_RUN) 3105 break; 3106 3107 /* Encapsulate and send data frames. */ 3108 IFQ_DEQUEUE(&ifp->if_snd, m); 3109 if (m == NULL) 3110 break; 3111 if (m->m_len < sizeof (*eh) && 3112 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3113 ifp->if_oerrors++; 3114 continue; 3115 } 3116 eh = mtod(m, struct ether_header *); 3117 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3118 if (ni == NULL) { 3119 m_freem(m); 3120 ifp->if_oerrors++; 3121 continue; 3122 } 3123 /* classify mbuf so we can find which tx ring to use */ 3124 if (ieee80211_classify(ic, m, ni) != 0) { 3125 m_freem(m); 3126 ieee80211_free_node(ni); 3127 ifp->if_oerrors++; 3128 continue; 3129 } 3130 3131 /* No QoS encapsulation for EAPOL frames. */ 3132 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3133 M_WME_GETAC(m) : WME_AC_BE; 3134 3135 bpf_mtap(ifp, m); 3136 3137 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3138 ieee80211_free_node(ni); 3139 ifp->if_oerrors++; 3140 continue; 3141 } 3142 sendit: 3143 bpf_mtap3(ic->ic_rawbpf, m); 3144 3145 if (iwn_tx(sc, m, ni, ac) != 0) { 3146 ieee80211_free_node(ni); 3147 ifp->if_oerrors++; 3148 continue; 3149 } 3150 3151 sc->sc_tx_timer = 5; 3152 ifp->if_timer = 1; 3153 } 3154 } 3155 3156 static void 3157 iwn_watchdog(struct ifnet *ifp) 3158 { 3159 struct iwn_softc *sc = ifp->if_softc; 3160 3161 ifp->if_timer = 0; 3162 3163 if (sc->sc_tx_timer > 0) { 3164 if (--sc->sc_tx_timer == 0) { 3165 aprint_error_dev(sc->sc_dev, 3166 "device timeout\n"); 3167 ifp->if_flags &= ~IFF_UP; 3168 iwn_stop(ifp, 1); 3169 ifp->if_oerrors++; 3170 return; 3171 } 3172 ifp->if_timer = 1; 3173 } 3174 3175 ieee80211_watchdog(&sc->sc_ic); 3176 } 3177 3178 static int 3179 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3180 { 3181 struct iwn_softc *sc = ifp->if_softc; 3182 struct ieee80211com *ic = &sc->sc_ic; 3183 const struct sockaddr *sa; 3184 int s, error = 0; 3185 3186 s = splnet(); 3187 3188 switch (cmd) { 3189 case SIOCSIFADDR: 3190 ifp->if_flags |= IFF_UP; 3191 #ifdef INET 3192 struct ifaddr *ifa = (struct ifaddr *)data; 3193 if (ifa->ifa_addr->sa_family == AF_INET) 3194 arp_ifinit(&ic->ic_ac, ifa); 3195 #endif 3196 /* FALLTHROUGH */ 3197 case SIOCSIFFLAGS: 3198 /* XXX Added as it is in every NetBSD driver */ 3199 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3200 break; 3201 if (ifp->if_flags & IFF_UP) { 3202 if (!(ifp->if_flags & IFF_RUNNING)) 3203 error = iwn_init(ifp); 3204 } else { 3205 if (ifp->if_flags & IFF_RUNNING) 3206 iwn_stop(ifp, 1); 3207 } 3208 break; 3209 3210 case SIOCADDMULTI: 3211 case SIOCDELMULTI: 3212 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3213 error = (cmd == SIOCADDMULTI) ? 3214 ether_addmulti(sa, &sc->sc_ec) : 3215 ether_delmulti(sa, &sc->sc_ec); 3216 3217 if (error == ENETRESET) 3218 error = 0; 3219 break; 3220 3221 default: 3222 error = ieee80211_ioctl(ic, cmd, data); 3223 } 3224 3225 if (error == ENETRESET) { 3226 error = 0; 3227 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3228 (IFF_UP | IFF_RUNNING)) { 3229 iwn_stop(ifp, 0); 3230 error = iwn_init(ifp); 3231 } 3232 } 3233 3234 splx(s); 3235 return error; 3236 } 3237 3238 /* 3239 * Send a command to the firmware. 3240 */ 3241 static int 3242 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3243 { 3244 struct iwn_tx_ring *ring = &sc->txq[4]; 3245 struct iwn_tx_desc *desc; 3246 struct iwn_tx_data *data; 3247 struct iwn_tx_cmd *cmd; 3248 struct mbuf *m; 3249 bus_addr_t paddr; 3250 int totlen, error; 3251 3252 desc = &ring->desc[ring->cur]; 3253 data = &ring->data[ring->cur]; 3254 totlen = 4 + size; 3255 3256 if (size > sizeof cmd->data) { 3257 /* Command is too large to fit in a descriptor. */ 3258 if (totlen > MCLBYTES) 3259 return EINVAL; 3260 MGETHDR(m, M_DONTWAIT, MT_DATA); 3261 if (m == NULL) 3262 return ENOMEM; 3263 if (totlen > MHLEN) { 3264 MCLGET(m, M_DONTWAIT); 3265 if (!(m->m_flags & M_EXT)) { 3266 m_freem(m); 3267 return ENOMEM; 3268 } 3269 } 3270 cmd = mtod(m, struct iwn_tx_cmd *); 3271 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3272 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3273 if (error != 0) { 3274 m_freem(m); 3275 return error; 3276 } 3277 data->m = m; 3278 paddr = data->map->dm_segs[0].ds_addr; 3279 } else { 3280 cmd = &ring->cmd[ring->cur]; 3281 paddr = data->cmd_paddr; 3282 } 3283 3284 cmd->code = code; 3285 cmd->flags = 0; 3286 cmd->qid = ring->qid; 3287 cmd->idx = ring->cur; 3288 memcpy(cmd->data, buf, size); 3289 3290 desc->nsegs = 1; 3291 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3292 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3293 3294 if (size > sizeof cmd->data) { 3295 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3296 BUS_DMASYNC_PREWRITE); 3297 } else { 3298 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3299 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3300 totlen, BUS_DMASYNC_PREWRITE); 3301 } 3302 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3303 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3304 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3305 3306 #ifdef notyet 3307 /* Update TX scheduler. */ 3308 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3309 #endif 3310 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3311 3312 /* Kick command ring. */ 3313 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3314 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3315 3316 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3317 } 3318 3319 static int 3320 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3321 { 3322 struct iwn4965_node_info hnode; 3323 char *src, *dst; 3324 3325 /* 3326 * We use the node structure for 5000 Series internally (it is 3327 * a superset of the one for 4965AGN). We thus copy the common 3328 * fields before sending the command. 3329 */ 3330 src = (char *)node; 3331 dst = (char *)&hnode; 3332 memcpy(dst, src, 48); 3333 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3334 memcpy(dst + 48, src + 72, 20); 3335 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3336 } 3337 3338 static int 3339 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3340 { 3341 /* Direct mapping. */ 3342 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3343 } 3344 3345 static int 3346 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3347 { 3348 struct iwn_node *wn = (void *)ni; 3349 struct ieee80211_rateset *rs = &ni->ni_rates; 3350 struct iwn_cmd_link_quality linkq; 3351 const struct iwn_rate *rinfo; 3352 uint8_t txant; 3353 int i, txrate; 3354 3355 /* Use the first valid TX antenna. */ 3356 txant = IWN_LSB(sc->txchainmask); 3357 3358 memset(&linkq, 0, sizeof linkq); 3359 linkq.id = wn->id; 3360 linkq.antmsk_1stream = txant; 3361 linkq.antmsk_2stream = IWN_ANT_AB; 3362 linkq.ampdu_max = 31; 3363 linkq.ampdu_threshold = 3; 3364 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3365 3366 /* Start at highest available bit-rate. */ 3367 txrate = rs->rs_nrates - 1; 3368 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3369 rinfo = &iwn_rates[wn->ridx[txrate]]; 3370 linkq.retry[i].plcp = rinfo->plcp; 3371 linkq.retry[i].rflags = rinfo->flags; 3372 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3373 /* Next retry at immediate lower bit-rate. */ 3374 if (txrate > 0) 3375 txrate--; 3376 } 3377 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3378 } 3379 3380 /* 3381 * Broadcast node is used to send group-addressed and management frames. 3382 */ 3383 static int 3384 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3385 { 3386 struct iwn_ops *ops = &sc->ops; 3387 struct iwn_node_info node; 3388 struct iwn_cmd_link_quality linkq; 3389 const struct iwn_rate *rinfo; 3390 uint8_t txant; 3391 int i, error; 3392 3393 memset(&node, 0, sizeof node); 3394 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3395 node.id = sc->broadcast_id; 3396 DPRINTF(("adding broadcast node\n")); 3397 if ((error = ops->add_node(sc, &node, async)) != 0) 3398 return error; 3399 3400 /* Use the first valid TX antenna. */ 3401 txant = IWN_LSB(sc->txchainmask); 3402 3403 memset(&linkq, 0, sizeof linkq); 3404 linkq.id = sc->broadcast_id; 3405 linkq.antmsk_1stream = txant; 3406 linkq.antmsk_2stream = IWN_ANT_AB; 3407 linkq.ampdu_max = 64; 3408 linkq.ampdu_threshold = 3; 3409 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3410 3411 /* Use lowest mandatory bit-rate. */ 3412 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3413 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3414 linkq.retry[0].plcp = rinfo->plcp; 3415 linkq.retry[0].rflags = rinfo->flags; 3416 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3417 /* Use same bit-rate for all TX retries. */ 3418 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3419 linkq.retry[i].plcp = linkq.retry[0].plcp; 3420 linkq.retry[i].rflags = linkq.retry[0].rflags; 3421 } 3422 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3423 } 3424 3425 static void 3426 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3427 { 3428 struct iwn_cmd_led led; 3429 3430 /* Clear microcode LED ownership. */ 3431 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3432 3433 led.which = which; 3434 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3435 led.off = off; 3436 led.on = on; 3437 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3438 } 3439 3440 /* 3441 * Set the critical temperature at which the firmware will stop the radio 3442 * and notify us. 3443 */ 3444 static int 3445 iwn_set_critical_temp(struct iwn_softc *sc) 3446 { 3447 struct iwn_critical_temp crit; 3448 int32_t temp; 3449 3450 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3451 3452 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3453 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3454 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3455 temp = IWN_CTOK(110); 3456 else 3457 temp = 110; 3458 memset(&crit, 0, sizeof crit); 3459 crit.tempR = htole32(temp); 3460 DPRINTF(("setting critical temperature to %d\n", temp)); 3461 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3462 } 3463 3464 static int 3465 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3466 { 3467 struct iwn_cmd_timing cmd; 3468 uint64_t val, mod; 3469 3470 memset(&cmd, 0, sizeof cmd); 3471 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3472 cmd.bintval = htole16(ni->ni_intval); 3473 cmd.lintval = htole16(10); 3474 3475 /* Compute remaining time until next beacon. */ 3476 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3477 mod = le64toh(cmd.tstamp) % val; 3478 cmd.binitval = htole32((uint32_t)(val - mod)); 3479 3480 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3481 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3482 3483 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3484 } 3485 3486 static void 3487 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3488 { 3489 /* Adjust TX power if need be (delta >= 3 degC). */ 3490 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3491 if (abs(temp - sc->temp) >= 3) { 3492 /* Record temperature of last calibration. */ 3493 sc->temp = temp; 3494 (void)iwn4965_set_txpower(sc, 1); 3495 } 3496 } 3497 3498 /* 3499 * Set TX power for current channel (each rate has its own power settings). 3500 * This function takes into account the regulatory information from EEPROM, 3501 * the current temperature and the current voltage. 3502 */ 3503 static int 3504 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3505 { 3506 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3507 #define fdivround(a, b, n) \ 3508 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3509 /* Linear interpolation. */ 3510 #define interpolate(x, x1, y1, x2, y2, n) \ 3511 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3512 3513 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3514 struct ieee80211com *ic = &sc->sc_ic; 3515 struct iwn_ucode_info *uc = &sc->ucode_info; 3516 struct ieee80211_channel *ch; 3517 struct iwn4965_cmd_txpower cmd; 3518 struct iwn4965_eeprom_chan_samples *chans; 3519 const uint8_t *rf_gain, *dsp_gain; 3520 int32_t vdiff, tdiff; 3521 int i, c, grp, maxpwr; 3522 uint8_t chan; 3523 3524 /* Retrieve current channel from last RXON. */ 3525 chan = sc->rxon.chan; 3526 DPRINTF(("setting TX power for channel %d\n", chan)); 3527 ch = &ic->ic_channels[chan]; 3528 3529 memset(&cmd, 0, sizeof cmd); 3530 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3531 cmd.chan = chan; 3532 3533 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3534 maxpwr = sc->maxpwr5GHz; 3535 rf_gain = iwn4965_rf_gain_5ghz; 3536 dsp_gain = iwn4965_dsp_gain_5ghz; 3537 } else { 3538 maxpwr = sc->maxpwr2GHz; 3539 rf_gain = iwn4965_rf_gain_2ghz; 3540 dsp_gain = iwn4965_dsp_gain_2ghz; 3541 } 3542 3543 /* Compute voltage compensation. */ 3544 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3545 if (vdiff > 0) 3546 vdiff *= 2; 3547 if (abs(vdiff) > 2) 3548 vdiff = 0; 3549 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3550 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3551 3552 /* Get channel attenuation group. */ 3553 if (chan <= 20) /* 1-20 */ 3554 grp = 4; 3555 else if (chan <= 43) /* 34-43 */ 3556 grp = 0; 3557 else if (chan <= 70) /* 44-70 */ 3558 grp = 1; 3559 else if (chan <= 124) /* 71-124 */ 3560 grp = 2; 3561 else /* 125-200 */ 3562 grp = 3; 3563 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3564 3565 /* Get channel sub-band. */ 3566 for (i = 0; i < IWN_NBANDS; i++) 3567 if (sc->bands[i].lo != 0 && 3568 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3569 break; 3570 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3571 return EINVAL; 3572 chans = sc->bands[i].chans; 3573 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3574 3575 for (c = 0; c < 2; c++) { 3576 uint8_t power, gain, temp; 3577 int maxchpwr, pwr, ridx, idx; 3578 3579 power = interpolate(chan, 3580 chans[0].num, chans[0].samples[c][1].power, 3581 chans[1].num, chans[1].samples[c][1].power, 1); 3582 gain = interpolate(chan, 3583 chans[0].num, chans[0].samples[c][1].gain, 3584 chans[1].num, chans[1].samples[c][1].gain, 1); 3585 temp = interpolate(chan, 3586 chans[0].num, chans[0].samples[c][1].temp, 3587 chans[1].num, chans[1].samples[c][1].temp, 1); 3588 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3589 c, power, gain, temp)); 3590 3591 /* Compute temperature compensation. */ 3592 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3593 DPRINTF(("temperature compensation=%d (current=%d, " 3594 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3595 3596 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3597 /* Convert dBm to half-dBm. */ 3598 maxchpwr = sc->maxpwr[chan] * 2; 3599 if ((ridx / 8) & 1) 3600 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3601 3602 pwr = maxpwr; 3603 3604 /* Adjust TX power based on rate. */ 3605 if ((ridx % 8) == 5) 3606 pwr -= 15; /* OFDM48: -7.5dB */ 3607 else if ((ridx % 8) == 6) 3608 pwr -= 17; /* OFDM54: -8.5dB */ 3609 else if ((ridx % 8) == 7) 3610 pwr -= 20; /* OFDM60: -10dB */ 3611 else 3612 pwr -= 10; /* Others: -5dB */ 3613 3614 /* Do not exceed channel max TX power. */ 3615 if (pwr > maxchpwr) 3616 pwr = maxchpwr; 3617 3618 idx = gain - (pwr - power) - tdiff - vdiff; 3619 if ((ridx / 8) & 1) /* MIMO */ 3620 idx += (int32_t)le32toh(uc->atten[grp][c]); 3621 3622 if (cmd.band == 0) 3623 idx += 9; /* 5GHz */ 3624 if (ridx == IWN_RIDX_MAX) 3625 idx += 5; /* CCK */ 3626 3627 /* Make sure idx stays in a valid range. */ 3628 if (idx < 0) 3629 idx = 0; 3630 else if (idx > IWN4965_MAX_PWR_INDEX) 3631 idx = IWN4965_MAX_PWR_INDEX; 3632 3633 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3634 c, ridx, idx)); 3635 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3636 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3637 } 3638 } 3639 3640 DPRINTF(("setting TX power for chan %d\n", chan)); 3641 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3642 3643 #undef interpolate 3644 #undef fdivround 3645 } 3646 3647 static int 3648 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3649 { 3650 struct iwn5000_cmd_txpower cmd; 3651 3652 /* 3653 * TX power calibration is handled automatically by the firmware 3654 * for 5000 Series. 3655 */ 3656 memset(&cmd, 0, sizeof cmd); 3657 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3658 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3659 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3660 DPRINTF(("setting TX power\n")); 3661 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3662 } 3663 3664 /* 3665 * Retrieve the maximum RSSI (in dBm) among receivers. 3666 */ 3667 static int 3668 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3669 { 3670 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3671 uint8_t mask, agc; 3672 int rssi; 3673 3674 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3675 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3676 3677 rssi = 0; 3678 if (mask & IWN_ANT_A) 3679 rssi = MAX(rssi, phy->rssi[0]); 3680 if (mask & IWN_ANT_B) 3681 rssi = MAX(rssi, phy->rssi[2]); 3682 if (mask & IWN_ANT_C) 3683 rssi = MAX(rssi, phy->rssi[4]); 3684 3685 return rssi - agc - IWN_RSSI_TO_DBM; 3686 } 3687 3688 static int 3689 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3690 { 3691 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3692 uint8_t agc; 3693 int rssi; 3694 3695 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3696 3697 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3698 le16toh(phy->rssi[1]) & 0xff); 3699 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3700 3701 return rssi - agc - IWN_RSSI_TO_DBM; 3702 } 3703 3704 /* 3705 * Retrieve the average noise (in dBm) among receivers. 3706 */ 3707 static int 3708 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3709 { 3710 int i, total, nbant, noise; 3711 3712 total = nbant = 0; 3713 for (i = 0; i < 3; i++) { 3714 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3715 continue; 3716 total += noise; 3717 nbant++; 3718 } 3719 /* There should be at least one antenna but check anyway. */ 3720 return (nbant == 0) ? -127 : (total / nbant) - 107; 3721 } 3722 3723 /* 3724 * Compute temperature (in degC) from last received statistics. 3725 */ 3726 static int 3727 iwn4965_get_temperature(struct iwn_softc *sc) 3728 { 3729 struct iwn_ucode_info *uc = &sc->ucode_info; 3730 int32_t r1, r2, r3, r4, temp; 3731 3732 r1 = le32toh(uc->temp[0].chan20MHz); 3733 r2 = le32toh(uc->temp[1].chan20MHz); 3734 r3 = le32toh(uc->temp[2].chan20MHz); 3735 r4 = le32toh(sc->rawtemp); 3736 3737 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3738 return 0; 3739 3740 /* Sign-extend 23-bit R4 value to 32-bit. */ 3741 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3742 /* Compute temperature in Kelvin. */ 3743 temp = (259 * (r4 - r2)) / (r3 - r1); 3744 temp = (temp * 97) / 100 + 8; 3745 3746 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3747 return IWN_KTOC(temp); 3748 } 3749 3750 static int 3751 iwn5000_get_temperature(struct iwn_softc *sc) 3752 { 3753 int32_t temp; 3754 3755 /* 3756 * Temperature is not used by the driver for 5000 Series because 3757 * TX power calibration is handled by firmware. We export it to 3758 * users through the sensor framework though. 3759 */ 3760 temp = le32toh(sc->rawtemp); 3761 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3762 temp = (temp / -5) + sc->temp_off; 3763 temp = IWN_KTOC(temp); 3764 } 3765 return temp; 3766 } 3767 3768 /* 3769 * Initialize sensitivity calibration state machine. 3770 */ 3771 static int 3772 iwn_init_sensitivity(struct iwn_softc *sc) 3773 { 3774 struct iwn_ops *ops = &sc->ops; 3775 struct iwn_calib_state *calib = &sc->calib; 3776 uint32_t flags; 3777 int error; 3778 3779 /* Reset calibration state machine. */ 3780 memset(calib, 0, sizeof (*calib)); 3781 calib->state = IWN_CALIB_STATE_INIT; 3782 calib->cck_state = IWN_CCK_STATE_HIFA; 3783 /* Set initial correlation values. */ 3784 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3785 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3786 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3787 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3788 calib->cck_x4 = 125; 3789 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3790 calib->energy_cck = sc->limits->energy_cck; 3791 3792 /* Write initial sensitivity. */ 3793 if ((error = iwn_send_sensitivity(sc)) != 0) 3794 return error; 3795 3796 /* Write initial gains. */ 3797 if ((error = ops->init_gains(sc)) != 0) 3798 return error; 3799 3800 /* Request statistics at each beacon interval. */ 3801 flags = 0; 3802 DPRINTF(("sending request for statistics\n")); 3803 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3804 } 3805 3806 /* 3807 * Collect noise and RSSI statistics for the first 20 beacons received 3808 * after association and use them to determine connected antennas and 3809 * to set differential gains. 3810 */ 3811 static void 3812 iwn_collect_noise(struct iwn_softc *sc, 3813 const struct iwn_rx_general_stats *stats) 3814 { 3815 struct iwn_ops *ops = &sc->ops; 3816 struct iwn_calib_state *calib = &sc->calib; 3817 uint32_t val; 3818 int i; 3819 3820 /* Accumulate RSSI and noise for all 3 antennas. */ 3821 for (i = 0; i < 3; i++) { 3822 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3823 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3824 } 3825 /* NB: We update differential gains only once after 20 beacons. */ 3826 if (++calib->nbeacons < 20) 3827 return; 3828 3829 /* Determine highest average RSSI. */ 3830 val = MAX(calib->rssi[0], calib->rssi[1]); 3831 val = MAX(calib->rssi[2], val); 3832 3833 /* Determine which antennas are connected. */ 3834 sc->chainmask = sc->rxchainmask; 3835 for (i = 0; i < 3; i++) 3836 if (val - calib->rssi[i] > 15 * 20) 3837 sc->chainmask &= ~(1 << i); 3838 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3839 sc->rxchainmask, sc->chainmask)); 3840 3841 /* If none of the TX antennas are connected, keep at least one. */ 3842 if ((sc->chainmask & sc->txchainmask) == 0) 3843 sc->chainmask |= IWN_LSB(sc->txchainmask); 3844 3845 (void)ops->set_gains(sc); 3846 calib->state = IWN_CALIB_STATE_RUN; 3847 3848 #ifdef notyet 3849 /* XXX Disable RX chains with no antennas connected. */ 3850 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3851 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3852 #endif 3853 3854 /* Enable power-saving mode if requested by user. */ 3855 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3856 (void)iwn_set_pslevel(sc, 0, 3, 1); 3857 } 3858 3859 static int 3860 iwn4965_init_gains(struct iwn_softc *sc) 3861 { 3862 struct iwn_phy_calib_gain cmd; 3863 3864 memset(&cmd, 0, sizeof cmd); 3865 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3866 /* Differential gains initially set to 0 for all 3 antennas. */ 3867 DPRINTF(("setting initial differential gains\n")); 3868 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3869 } 3870 3871 static int 3872 iwn5000_init_gains(struct iwn_softc *sc) 3873 { 3874 struct iwn_phy_calib cmd; 3875 3876 memset(&cmd, 0, sizeof cmd); 3877 cmd.code = sc->reset_noise_gain; 3878 cmd.ngroups = 1; 3879 cmd.isvalid = 1; 3880 DPRINTF(("setting initial differential gains\n")); 3881 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3882 } 3883 3884 static int 3885 iwn4965_set_gains(struct iwn_softc *sc) 3886 { 3887 struct iwn_calib_state *calib = &sc->calib; 3888 struct iwn_phy_calib_gain cmd; 3889 int i, delta, noise; 3890 3891 /* Get minimal noise among connected antennas. */ 3892 noise = INT_MAX; /* NB: There's at least one antenna. */ 3893 for (i = 0; i < 3; i++) 3894 if (sc->chainmask & (1 << i)) 3895 noise = MIN(calib->noise[i], noise); 3896 3897 memset(&cmd, 0, sizeof cmd); 3898 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3899 /* Set differential gains for connected antennas. */ 3900 for (i = 0; i < 3; i++) { 3901 if (sc->chainmask & (1 << i)) { 3902 /* Compute attenuation (in unit of 1.5dB). */ 3903 delta = (noise - (int32_t)calib->noise[i]) / 30; 3904 /* NB: delta <= 0 */ 3905 /* Limit to [-4.5dB,0]. */ 3906 cmd.gain[i] = MIN(abs(delta), 3); 3907 if (delta < 0) 3908 cmd.gain[i] |= 1 << 2; /* sign bit */ 3909 } 3910 } 3911 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3912 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3913 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3914 } 3915 3916 static int 3917 iwn5000_set_gains(struct iwn_softc *sc) 3918 { 3919 struct iwn_calib_state *calib = &sc->calib; 3920 struct iwn_phy_calib_gain cmd; 3921 int i, ant, div, delta; 3922 3923 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3924 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3925 3926 memset(&cmd, 0, sizeof cmd); 3927 cmd.code = sc->noise_gain; 3928 cmd.ngroups = 1; 3929 cmd.isvalid = 1; 3930 /* Get first available RX antenna as referential. */ 3931 ant = IWN_LSB(sc->rxchainmask); 3932 /* Set differential gains for other antennas. */ 3933 for (i = ant + 1; i < 3; i++) { 3934 if (sc->chainmask & (1 << i)) { 3935 /* The delta is relative to antenna "ant". */ 3936 delta = ((int32_t)calib->noise[ant] - 3937 (int32_t)calib->noise[i]) / div; 3938 /* Limit to [-4.5dB,+4.5dB]. */ 3939 cmd.gain[i - 1] = MIN(abs(delta), 3); 3940 if (delta < 0) 3941 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3942 } 3943 } 3944 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3945 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3946 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3947 } 3948 3949 /* 3950 * Tune RF RX sensitivity based on the number of false alarms detected 3951 * during the last beacon period. 3952 */ 3953 static void 3954 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3955 { 3956 #define inc(val, inc, max) \ 3957 if ((val) < (max)) { \ 3958 if ((val) < (max) - (inc)) \ 3959 (val) += (inc); \ 3960 else \ 3961 (val) = (max); \ 3962 needs_update = 1; \ 3963 } 3964 #define dec(val, dec, min) \ 3965 if ((val) > (min)) { \ 3966 if ((val) > (min) + (dec)) \ 3967 (val) -= (dec); \ 3968 else \ 3969 (val) = (min); \ 3970 needs_update = 1; \ 3971 } 3972 3973 const struct iwn_sensitivity_limits *limits = sc->limits; 3974 struct iwn_calib_state *calib = &sc->calib; 3975 uint32_t val, rxena, fa; 3976 uint32_t energy[3], energy_min; 3977 uint8_t noise[3], noise_ref; 3978 int i, needs_update = 0; 3979 3980 /* Check that we've been enabled long enough. */ 3981 if ((rxena = le32toh(stats->general.load)) == 0) 3982 return; 3983 3984 /* Compute number of false alarms since last call for OFDM. */ 3985 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3986 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3987 fa *= 200 * 1024; /* 200TU */ 3988 3989 /* Save counters values for next call. */ 3990 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3991 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3992 3993 if (fa > 50 * rxena) { 3994 /* High false alarm count, decrease sensitivity. */ 3995 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3996 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3997 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3998 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3999 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4000 4001 } else if (fa < 5 * rxena) { 4002 /* Low false alarm count, increase sensitivity. */ 4003 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4004 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4005 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4006 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4007 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4008 } 4009 4010 /* Compute maximum noise among 3 receivers. */ 4011 for (i = 0; i < 3; i++) 4012 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4013 val = MAX(noise[0], noise[1]); 4014 val = MAX(noise[2], val); 4015 /* Insert it into our samples table. */ 4016 calib->noise_samples[calib->cur_noise_sample] = val; 4017 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4018 4019 /* Compute maximum noise among last 20 samples. */ 4020 noise_ref = calib->noise_samples[0]; 4021 for (i = 1; i < 20; i++) 4022 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4023 4024 /* Compute maximum energy among 3 receivers. */ 4025 for (i = 0; i < 3; i++) 4026 energy[i] = le32toh(stats->general.energy[i]); 4027 val = MIN(energy[0], energy[1]); 4028 val = MIN(energy[2], val); 4029 /* Insert it into our samples table. */ 4030 calib->energy_samples[calib->cur_energy_sample] = val; 4031 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4032 4033 /* Compute minimum energy among last 10 samples. */ 4034 energy_min = calib->energy_samples[0]; 4035 for (i = 1; i < 10; i++) 4036 energy_min = MAX(energy_min, calib->energy_samples[i]); 4037 energy_min += 6; 4038 4039 /* Compute number of false alarms since last call for CCK. */ 4040 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4041 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4042 fa *= 200 * 1024; /* 200TU */ 4043 4044 /* Save counters values for next call. */ 4045 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4046 calib->fa_cck = le32toh(stats->cck.fa); 4047 4048 if (fa > 50 * rxena) { 4049 /* High false alarm count, decrease sensitivity. */ 4050 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4051 calib->cck_state = IWN_CCK_STATE_HIFA; 4052 calib->low_fa = 0; 4053 4054 if (calib->cck_x4 > 160) { 4055 calib->noise_ref = noise_ref; 4056 if (calib->energy_cck > 2) 4057 dec(calib->energy_cck, 2, energy_min); 4058 } 4059 if (calib->cck_x4 < 160) { 4060 calib->cck_x4 = 161; 4061 needs_update = 1; 4062 } else 4063 inc(calib->cck_x4, 3, limits->max_cck_x4); 4064 4065 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4066 4067 } else if (fa < 5 * rxena) { 4068 /* Low false alarm count, increase sensitivity. */ 4069 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4070 calib->cck_state = IWN_CCK_STATE_LOFA; 4071 calib->low_fa++; 4072 4073 if (calib->cck_state != IWN_CCK_STATE_INIT && 4074 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4075 calib->low_fa > 100)) { 4076 inc(calib->energy_cck, 2, limits->min_energy_cck); 4077 dec(calib->cck_x4, 3, limits->min_cck_x4); 4078 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4079 } 4080 } else { 4081 /* Not worth to increase or decrease sensitivity. */ 4082 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4083 calib->low_fa = 0; 4084 calib->noise_ref = noise_ref; 4085 4086 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4087 /* Previous interval had many false alarms. */ 4088 dec(calib->energy_cck, 8, energy_min); 4089 } 4090 calib->cck_state = IWN_CCK_STATE_INIT; 4091 } 4092 4093 if (needs_update) 4094 (void)iwn_send_sensitivity(sc); 4095 #undef dec 4096 #undef inc 4097 } 4098 4099 static int 4100 iwn_send_sensitivity(struct iwn_softc *sc) 4101 { 4102 struct iwn_calib_state *calib = &sc->calib; 4103 struct iwn_enhanced_sensitivity_cmd cmd; 4104 int len; 4105 4106 memset(&cmd, 0, sizeof cmd); 4107 len = sizeof (struct iwn_sensitivity_cmd); 4108 cmd.which = IWN_SENSITIVITY_WORKTBL; 4109 /* OFDM modulation. */ 4110 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4111 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4112 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4113 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4114 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4115 cmd.energy_ofdm_th = htole16(62); 4116 /* CCK modulation. */ 4117 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4118 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4119 cmd.energy_cck = htole16(calib->energy_cck); 4120 /* Barker modulation: use default values. */ 4121 cmd.corr_barker = htole16(190); 4122 cmd.corr_barker_mrc = htole16(390); 4123 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4124 goto send; 4125 /* Enhanced sensitivity settings. */ 4126 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4127 cmd.ofdm_det_slope_mrc = htole16(668); 4128 cmd.ofdm_det_icept_mrc = htole16(4); 4129 cmd.ofdm_det_slope = htole16(486); 4130 cmd.ofdm_det_icept = htole16(37); 4131 cmd.cck_det_slope_mrc = htole16(853); 4132 cmd.cck_det_icept_mrc = htole16(4); 4133 cmd.cck_det_slope = htole16(476); 4134 cmd.cck_det_icept = htole16(99); 4135 send: 4136 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4137 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4138 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4139 calib->energy_cck)); 4140 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4141 } 4142 4143 /* 4144 * Set STA mode power saving level (between 0 and 5). 4145 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4146 */ 4147 static int 4148 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4149 { 4150 struct iwn_pmgt_cmd cmd; 4151 const struct iwn_pmgt *pmgt; 4152 uint32_t maxp, skip_dtim; 4153 pcireg_t reg; 4154 int i; 4155 4156 /* Select which PS parameters to use. */ 4157 if (dtim <= 2) 4158 pmgt = &iwn_pmgt[0][level]; 4159 else if (dtim <= 10) 4160 pmgt = &iwn_pmgt[1][level]; 4161 else 4162 pmgt = &iwn_pmgt[2][level]; 4163 4164 memset(&cmd, 0, sizeof cmd); 4165 if (level != 0) /* not CAM */ 4166 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4167 if (level == 5) 4168 cmd.flags |= htole16(IWN_PS_FAST_PD); 4169 /* Retrieve PCIe Active State Power Management (ASPM). */ 4170 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4171 sc->sc_cap_off + PCIE_LCSR); 4172 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4173 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4174 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4175 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4176 4177 if (dtim == 0) { 4178 dtim = 1; 4179 skip_dtim = 0; 4180 } else 4181 skip_dtim = pmgt->skip_dtim; 4182 if (skip_dtim != 0) { 4183 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4184 maxp = pmgt->intval[4]; 4185 if (maxp == (uint32_t)-1) 4186 maxp = dtim * (skip_dtim + 1); 4187 else if (maxp > dtim) 4188 maxp = (maxp / dtim) * dtim; 4189 } else 4190 maxp = dtim; 4191 for (i = 0; i < 5; i++) 4192 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4193 4194 DPRINTF(("setting power saving level to %d\n", level)); 4195 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4196 } 4197 4198 int 4199 iwn5000_runtime_calib(struct iwn_softc *sc) 4200 { 4201 struct iwn5000_calib_config cmd; 4202 4203 memset(&cmd, 0, sizeof cmd); 4204 cmd.ucode.once.enable = 0xffffffff; 4205 cmd.ucode.once.start = IWN5000_CALIB_DC; 4206 DPRINTF(("configuring runtime calibration\n")); 4207 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4208 } 4209 4210 static int 4211 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc) 4212 { 4213 struct iwn_bluetooth bluetooth; 4214 4215 memset(&bluetooth, 0, sizeof bluetooth); 4216 bluetooth.flags = IWN_BT_COEX_ENABLE; 4217 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4218 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4219 4220 DPRINTF(("configuring bluetooth coexistence\n")); 4221 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4222 } 4223 4224 static int 4225 iwn_config_bt_coex_prio_table(struct iwn_softc *sc) 4226 { 4227 uint8_t prio_table[16]; 4228 4229 memset(&prio_table, 0, sizeof prio_table); 4230 prio_table[ 0] = 6; /* init calibration 1 */ 4231 prio_table[ 1] = 7; /* init calibration 2 */ 4232 prio_table[ 2] = 2; /* periodic calib low 1 */ 4233 prio_table[ 3] = 3; /* periodic calib low 2 */ 4234 prio_table[ 4] = 4; /* periodic calib high 1 */ 4235 prio_table[ 5] = 5; /* periodic calib high 2 */ 4236 prio_table[ 6] = 6; /* dtim */ 4237 prio_table[ 7] = 8; /* scan52 */ 4238 prio_table[ 8] = 10; /* scan24 */ 4239 4240 DPRINTF(("sending priority lookup table\n")); 4241 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE, 4242 &prio_table, sizeof prio_table, 0); 4243 } 4244 4245 static int 4246 iwn_config_bt_coex_adv_config(struct iwn_softc *sc, struct iwn_bt_basic *basic, 4247 size_t len) 4248 { 4249 struct iwn_btcoex_prot btprot; 4250 int error; 4251 4252 basic->bt.flags = IWN_BT_COEX_ENABLE; 4253 basic->bt.lead_time = IWN_BT_LEAD_TIME_DEF; 4254 basic->bt.max_kill = IWN_BT_MAX_KILL_DEF; 4255 basic->bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF; 4256 basic->bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF; 4257 basic->bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF; 4258 basic->bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF; 4259 basic->bt3_timer_t2_value = IWN_BT_BT3_T2_DEF; 4260 basic->bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */ 4261 basic->bt3_lookup_table[ 1] = htole32(0xaaaaaaaa); 4262 basic->bt3_lookup_table[ 2] = htole32(0xaeaaaaaa); 4263 basic->bt3_lookup_table[ 3] = htole32(0xaaaaaaaa); 4264 basic->bt3_lookup_table[ 4] = htole32(0xcc00ff28); 4265 basic->bt3_lookup_table[ 5] = htole32(0x0000aaaa); 4266 basic->bt3_lookup_table[ 6] = htole32(0xcc00aaaa); 4267 basic->bt3_lookup_table[ 7] = htole32(0x0000aaaa); 4268 basic->bt3_lookup_table[ 8] = htole32(0xc0004000); 4269 basic->bt3_lookup_table[ 9] = htole32(0x00004000); 4270 basic->bt3_lookup_table[10] = htole32(0xf0005000); 4271 basic->bt3_lookup_table[11] = htole32(0xf0005000); 4272 basic->reduce_txpower = 0; /* as not implemented */ 4273 basic->valid = IWN_BT_ALL_VALID_MASK; 4274 4275 DPRINTF(("configuring advanced bluetooth coexistence v1\n")); 4276 error = iwn_cmd(sc, IWN_CMD_BT_COEX, basic, len, 0); 4277 if (error != 0) { 4278 aprint_error_dev(sc->sc_dev, 4279 "could not configure advanced bluetooth coexistence\n"); 4280 return error; 4281 } 4282 4283 error = iwn_config_bt_coex_prio_table(sc); 4284 if (error != 0) { 4285 aprint_error_dev(sc->sc_dev, 4286 "could not configure send BT priority table\n"); 4287 return error; 4288 } 4289 4290 /* Force BT state machine change */ 4291 memset(&btprot, 0, sizeof btprot); 4292 btprot.open = 1; 4293 btprot.type = 1; 4294 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4295 if (error != 0) { 4296 aprint_error_dev(sc->sc_dev, "could not open BT protcol\n"); 4297 return error; 4298 } 4299 4300 btprot.open = 0; 4301 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4302 if (error != 0) { 4303 aprint_error_dev(sc->sc_dev, "could not close BT protcol\n"); 4304 return error; 4305 } 4306 return 0; 4307 } 4308 4309 static int 4310 iwn_config_bt_coex_adv1(struct iwn_softc *sc) 4311 { 4312 struct iwn_bt_adv1 d; 4313 4314 memset(&d, 0, sizeof d); 4315 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4316 d.tx_prio_boost = 0; 4317 d.rx_prio_boost = 0; 4318 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4319 } 4320 4321 static int 4322 iwn_config_bt_coex_adv2(struct iwn_softc *sc) 4323 { 4324 struct iwn_bt_adv2 d; 4325 4326 memset(&d, 0, sizeof d); 4327 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4328 d.tx_prio_boost = 0; 4329 d.rx_prio_boost = 0; 4330 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4331 } 4332 4333 static int 4334 iwn_config(struct iwn_softc *sc) 4335 { 4336 struct iwn_ops *ops = &sc->ops; 4337 struct ieee80211com *ic = &sc->sc_ic; 4338 struct ifnet *ifp = ic->ic_ifp; 4339 uint32_t txmask; 4340 uint16_t rxchain; 4341 int error; 4342 4343 error = ops->config_bt_coex(sc); 4344 if (error != 0) { 4345 aprint_error_dev(sc->sc_dev, 4346 "could not configure bluetooth coexistence\n"); 4347 return error; 4348 } 4349 4350 /* Set radio temperature sensor offset. */ 4351 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4352 error = iwn6000_temp_offset_calib(sc); 4353 if (error != 0) { 4354 aprint_error_dev(sc->sc_dev, 4355 "could not set temperature offset\n"); 4356 return error; 4357 } 4358 } 4359 4360 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4361 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4362 sc->hw_type == IWN_HW_REV_TYPE_135 || 4363 sc->hw_type == IWN_HW_REV_TYPE_105) { 4364 error = iwn2000_temp_offset_calib(sc); 4365 if (error != 0) { 4366 aprint_error_dev(sc->sc_dev, 4367 "could not set temperature offset\n"); 4368 return error; 4369 } 4370 } 4371 4372 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4373 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4374 /* Configure runtime DC calibration. */ 4375 error = iwn5000_runtime_calib(sc); 4376 if (error != 0) { 4377 aprint_error_dev(sc->sc_dev, 4378 "could not configure runtime calibration\n"); 4379 return error; 4380 } 4381 } 4382 4383 /* Configure valid TX chains for 5000 Series. */ 4384 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4385 txmask = htole32(sc->txchainmask); 4386 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4387 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4388 sizeof txmask, 0); 4389 if (error != 0) { 4390 aprint_error_dev(sc->sc_dev, 4391 "could not configure valid TX chains\n"); 4392 return error; 4393 } 4394 } 4395 4396 /* Set mode, channel, RX filter and enable RX. */ 4397 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4398 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4399 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4400 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4401 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4402 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4403 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4404 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4405 switch (ic->ic_opmode) { 4406 case IEEE80211_M_STA: 4407 sc->rxon.mode = IWN_MODE_STA; 4408 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4409 break; 4410 case IEEE80211_M_MONITOR: 4411 sc->rxon.mode = IWN_MODE_MONITOR; 4412 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4413 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4414 break; 4415 default: 4416 /* Should not get there. */ 4417 break; 4418 } 4419 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4420 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4421 sc->rxon.ht_single_mask = 0xff; 4422 sc->rxon.ht_dual_mask = 0xff; 4423 sc->rxon.ht_triple_mask = 0xff; 4424 rxchain = 4425 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4426 IWN_RXCHAIN_MIMO_COUNT(2) | 4427 IWN_RXCHAIN_IDLE_COUNT(2); 4428 sc->rxon.rxchain = htole16(rxchain); 4429 DPRINTF(("setting configuration\n")); 4430 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4431 if (error != 0) { 4432 aprint_error_dev(sc->sc_dev, 4433 "RXON command failed\n"); 4434 return error; 4435 } 4436 4437 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4438 aprint_error_dev(sc->sc_dev, 4439 "could not add broadcast node\n"); 4440 return error; 4441 } 4442 4443 /* Configuration has changed, set TX power accordingly. */ 4444 if ((error = ops->set_txpower(sc, 0)) != 0) { 4445 aprint_error_dev(sc->sc_dev, 4446 "could not set TX power\n"); 4447 return error; 4448 } 4449 4450 if ((error = iwn_set_critical_temp(sc)) != 0) { 4451 aprint_error_dev(sc->sc_dev, 4452 "could not set critical temperature\n"); 4453 return error; 4454 } 4455 4456 /* Set power saving level to CAM during initialization. */ 4457 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4458 aprint_error_dev(sc->sc_dev, 4459 "could not set power saving level\n"); 4460 return error; 4461 } 4462 return 0; 4463 } 4464 4465 static uint16_t 4466 iwn_get_active_dwell_time(struct iwn_softc *sc, uint16_t flags, 4467 uint8_t n_probes) 4468 { 4469 /* No channel? Default to 2GHz settings */ 4470 if (flags & IEEE80211_CHAN_2GHZ) 4471 return IWN_ACTIVE_DWELL_TIME_2GHZ + 4472 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1); 4473 4474 /* 5GHz dwell time */ 4475 return IWN_ACTIVE_DWELL_TIME_5GHZ + 4476 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1); 4477 } 4478 4479 /* 4480 * Limit the total dwell time to 85% of the beacon interval. 4481 * 4482 * Returns the dwell time in milliseconds. 4483 */ 4484 static uint16_t 4485 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 4486 { 4487 struct ieee80211com *ic = &sc->sc_ic; 4488 struct ieee80211_node *ni = ic->ic_bss; 4489 int bintval = 0; 4490 4491 /* bintval is in TU (1.024mS) */ 4492 if (ni != NULL) 4493 bintval = ni->ni_intval; 4494 4495 /* 4496 * If it's non-zero, we should calculate the minimum of 4497 * it and the DWELL_BASE. 4498 * 4499 * XXX Yes, the math should take into account that bintval 4500 * is 1.024mS, not 1mS.. 4501 */ 4502 if (bintval > 0) 4503 return MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)); 4504 4505 /* No association context? Default */ 4506 return IWN_PASSIVE_DWELL_BASE; 4507 } 4508 4509 static uint16_t 4510 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 4511 { 4512 uint16_t passive; 4513 if (flags & IEEE80211_CHAN_2GHZ) 4514 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 4515 else 4516 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 4517 4518 /* Clamp to the beacon interval if we're associated */ 4519 return iwn_limit_dwell(sc, passive); 4520 } 4521 4522 static int 4523 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4524 { 4525 struct ieee80211com *ic = &sc->sc_ic; 4526 struct iwn_scan_hdr *hdr; 4527 struct iwn_cmd_data *tx; 4528 struct iwn_scan_essid *essid; 4529 struct iwn_scan_chan *chan; 4530 struct ieee80211_frame *wh; 4531 struct ieee80211_rateset *rs; 4532 struct ieee80211_channel *c; 4533 uint8_t *buf, *frm; 4534 uint16_t rxchain, dwell_active, dwell_passive; 4535 uint8_t txant; 4536 int buflen, error, is_active; 4537 4538 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4539 if (buf == NULL) { 4540 aprint_error_dev(sc->sc_dev, 4541 "could not allocate buffer for scan command\n"); 4542 return ENOMEM; 4543 } 4544 hdr = (struct iwn_scan_hdr *)buf; 4545 /* 4546 * Move to the next channel if no frames are received within 10ms 4547 * after sending the probe request. 4548 */ 4549 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4550 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4551 4552 /* Select antennas for scanning. */ 4553 rxchain = 4554 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4555 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4556 IWN_RXCHAIN_DRIVER_FORCE; 4557 if ((flags & IEEE80211_CHAN_5GHZ) && 4558 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4559 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4560 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4561 } else /* Use all available RX antennas. */ 4562 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4563 hdr->rxchain = htole16(rxchain); 4564 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4565 4566 tx = (struct iwn_cmd_data *)(hdr + 1); 4567 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4568 tx->id = sc->broadcast_id; 4569 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4570 4571 if (flags & IEEE80211_CHAN_5GHZ) { 4572 hdr->crc_threshold = 0xffff; 4573 /* Send probe requests at 6Mbps. */ 4574 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4575 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4576 } else { 4577 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4578 /* Send probe requests at 1Mbps. */ 4579 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4580 tx->rflags = IWN_RFLAG_CCK; 4581 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4582 } 4583 /* Use the first valid TX antenna. */ 4584 txant = IWN_LSB(sc->txchainmask); 4585 tx->rflags |= IWN_RFLAG_ANT(txant); 4586 4587 /* 4588 * Only do active scanning if we're announcing a probe request 4589 * for a given SSID (or more, if we ever add it to the driver.) 4590 */ 4591 is_active = 0; 4592 4593 essid = (struct iwn_scan_essid *)(tx + 1); 4594 if (ic->ic_des_esslen != 0) { 4595 essid[0].id = IEEE80211_ELEMID_SSID; 4596 essid[0].len = ic->ic_des_esslen; 4597 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4598 4599 is_active = 1; 4600 } 4601 /* 4602 * Build a probe request frame. Most of the following code is a 4603 * copy & paste of what is done in net80211. 4604 */ 4605 wh = (struct ieee80211_frame *)(essid + 20); 4606 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4607 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4608 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4609 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4610 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4611 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4612 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4613 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4614 4615 frm = (uint8_t *)(wh + 1); 4616 frm = ieee80211_add_ssid(frm, NULL, 0); 4617 frm = ieee80211_add_rates(frm, rs); 4618 #ifndef IEEE80211_NO_HT 4619 if (ic->ic_flags & IEEE80211_F_HTON) 4620 frm = ieee80211_add_htcaps(frm, ic); 4621 #endif 4622 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4623 frm = ieee80211_add_xrates(frm, rs); 4624 4625 /* Set length of probe request. */ 4626 tx->len = htole16(frm - (uint8_t *)wh); 4627 4628 4629 /* 4630 * If active scanning is requested but a certain channel is 4631 * marked passive, we can do active scanning if we detect 4632 * transmissions. 4633 * 4634 * There is an issue with some firmware versions that triggers 4635 * a sysassert on a "good CRC threshold" of zero (== disabled), 4636 * on a radar channel even though this means that we should NOT 4637 * send probes. 4638 * 4639 * The "good CRC threshold" is the number of frames that we 4640 * need to receive during our dwell time on a channel before 4641 * sending out probes -- setting this to a huge value will 4642 * mean we never reach it, but at the same time work around 4643 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 4644 * here instead of IWN_GOOD_CRC_TH_DISABLED. 4645 * 4646 * This was fixed in later versions along with some other 4647 * scan changes, and the threshold behaves as a flag in those 4648 * versions. 4649 */ 4650 4651 /* 4652 * If we're doing active scanning, set the crc_threshold 4653 * to a suitable value. This is different to active veruss 4654 * passive scanning depending upon the channel flags; the 4655 * firmware will obey that particular check for us. 4656 */ 4657 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 4658 hdr->crc_threshold = is_active ? 4659 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 4660 else 4661 hdr->crc_threshold = is_active ? 4662 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 4663 4664 chan = (struct iwn_scan_chan *)frm; 4665 for (c = &ic->ic_channels[1]; 4666 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4667 if ((c->ic_flags & flags) != flags) 4668 continue; 4669 4670 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4671 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4672 chan->flags = 0; 4673 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4674 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4675 if (ic->ic_des_esslen != 0) 4676 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4677 4678 /* 4679 * Calculate the active/passive dwell times. 4680 */ 4681 4682 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 4683 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 4684 4685 /* Make sure they're valid */ 4686 if (dwell_passive <= dwell_active) 4687 dwell_passive = dwell_active + 1; 4688 4689 chan->active = htole16(dwell_active); 4690 chan->passive = htole16(dwell_passive); 4691 4692 chan->dsp_gain = 0x6e; 4693 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4694 chan->rf_gain = 0x3b; 4695 } else { 4696 chan->rf_gain = 0x28; 4697 } 4698 hdr->nchan++; 4699 chan++; 4700 } 4701 4702 buflen = (uint8_t *)chan - buf; 4703 hdr->len = htole16(buflen); 4704 4705 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4706 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4707 free(buf, M_DEVBUF); 4708 return error; 4709 } 4710 4711 static int 4712 iwn_auth(struct iwn_softc *sc) 4713 { 4714 struct iwn_ops *ops = &sc->ops; 4715 struct ieee80211com *ic = &sc->sc_ic; 4716 struct ieee80211_node *ni = ic->ic_bss; 4717 int error; 4718 4719 /* Update adapter configuration. */ 4720 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4721 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4722 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4723 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4724 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4725 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4726 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4727 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4728 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4729 switch (ic->ic_curmode) { 4730 case IEEE80211_MODE_11A: 4731 sc->rxon.cck_mask = 0; 4732 sc->rxon.ofdm_mask = 0x15; 4733 break; 4734 case IEEE80211_MODE_11B: 4735 sc->rxon.cck_mask = 0x03; 4736 sc->rxon.ofdm_mask = 0; 4737 break; 4738 default: /* Assume 802.11b/g. */ 4739 sc->rxon.cck_mask = 0x0f; 4740 sc->rxon.ofdm_mask = 0x15; 4741 } 4742 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4743 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4744 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4745 if (error != 0) { 4746 aprint_error_dev(sc->sc_dev, 4747 "RXON command failed\n"); 4748 return error; 4749 } 4750 4751 /* Configuration has changed, set TX power accordingly. */ 4752 if ((error = ops->set_txpower(sc, 1)) != 0) { 4753 aprint_error_dev(sc->sc_dev, 4754 "could not set TX power\n"); 4755 return error; 4756 } 4757 /* 4758 * Reconfiguring RXON clears the firmware nodes table so we must 4759 * add the broadcast node again. 4760 */ 4761 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4762 aprint_error_dev(sc->sc_dev, 4763 "could not add broadcast node\n"); 4764 return error; 4765 } 4766 return 0; 4767 } 4768 4769 static int 4770 iwn_run(struct iwn_softc *sc) 4771 { 4772 struct iwn_ops *ops = &sc->ops; 4773 struct ieee80211com *ic = &sc->sc_ic; 4774 struct ieee80211_node *ni = ic->ic_bss; 4775 struct iwn_node_info node; 4776 int error; 4777 4778 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4779 /* Link LED blinks while monitoring. */ 4780 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4781 return 0; 4782 } 4783 if ((error = iwn_set_timing(sc, ni)) != 0) { 4784 aprint_error_dev(sc->sc_dev, 4785 "could not set timing\n"); 4786 return error; 4787 } 4788 4789 /* Update adapter configuration. */ 4790 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4791 /* Short preamble and slot time are negotiated when associating. */ 4792 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4793 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4794 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4795 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4796 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4797 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4798 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4799 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4800 if (error != 0) { 4801 aprint_error_dev(sc->sc_dev, 4802 "could not update configuration\n"); 4803 return error; 4804 } 4805 4806 /* Configuration has changed, set TX power accordingly. */ 4807 if ((error = ops->set_txpower(sc, 1)) != 0) { 4808 aprint_error_dev(sc->sc_dev, 4809 "could not set TX power\n"); 4810 return error; 4811 } 4812 4813 /* Fake a join to initialize the TX rate. */ 4814 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4815 iwn_newassoc(ni, 1); 4816 4817 /* Add BSS node. */ 4818 memset(&node, 0, sizeof node); 4819 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4820 node.id = IWN_ID_BSS; 4821 #ifdef notyet 4822 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4823 IWN_AMDPU_DENSITY(5)); /* 2us */ 4824 #endif 4825 DPRINTF(("adding BSS node\n")); 4826 error = ops->add_node(sc, &node, 1); 4827 if (error != 0) { 4828 aprint_error_dev(sc->sc_dev, 4829 "could not add BSS node\n"); 4830 return error; 4831 } 4832 DPRINTF(("setting link quality for node %d\n", node.id)); 4833 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4834 aprint_error_dev(sc->sc_dev, 4835 "could not setup link quality for node %d\n", node.id); 4836 return error; 4837 } 4838 4839 if ((error = iwn_init_sensitivity(sc)) != 0) { 4840 aprint_error_dev(sc->sc_dev, 4841 "could not set sensitivity\n"); 4842 return error; 4843 } 4844 /* Start periodic calibration timer. */ 4845 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4846 sc->calib_cnt = 0; 4847 callout_schedule(&sc->calib_to, hz/2); 4848 4849 /* Link LED always on while associated. */ 4850 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4851 return 0; 4852 } 4853 4854 #ifdef IWN_HWCRYPTO 4855 /* 4856 * We support CCMP hardware encryption/decryption of unicast frames only. 4857 * HW support for TKIP really sucks. We should let TKIP die anyway. 4858 */ 4859 static int 4860 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4861 struct ieee80211_key *k) 4862 { 4863 struct iwn_softc *sc = ic->ic_softc; 4864 struct iwn_ops *ops = &sc->ops; 4865 struct iwn_node *wn = (void *)ni; 4866 struct iwn_node_info node; 4867 uint16_t kflags; 4868 4869 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4870 k->k_cipher != IEEE80211_CIPHER_CCMP) 4871 return ieee80211_set_key(ic, ni, k); 4872 4873 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4874 if (k->k_flags & IEEE80211_KEY_GROUP) 4875 kflags |= IWN_KFLAG_GROUP; 4876 4877 memset(&node, 0, sizeof node); 4878 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4879 sc->broadcast_id : wn->id; 4880 node.control = IWN_NODE_UPDATE; 4881 node.flags = IWN_FLAG_SET_KEY; 4882 node.kflags = htole16(kflags); 4883 node.kid = k->k_id; 4884 memcpy(node.key, k->k_key, k->k_len); 4885 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4886 return ops->add_node(sc, &node, 1); 4887 } 4888 4889 static void 4890 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4891 struct ieee80211_key *k) 4892 { 4893 struct iwn_softc *sc = ic->ic_softc; 4894 struct iwn_ops *ops = &sc->ops; 4895 struct iwn_node *wn = (void *)ni; 4896 struct iwn_node_info node; 4897 4898 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4899 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4900 /* See comment about other ciphers above. */ 4901 ieee80211_delete_key(ic, ni, k); 4902 return; 4903 } 4904 if (ic->ic_state != IEEE80211_S_RUN) 4905 return; /* Nothing to do. */ 4906 memset(&node, 0, sizeof node); 4907 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4908 sc->broadcast_id : wn->id; 4909 node.control = IWN_NODE_UPDATE; 4910 node.flags = IWN_FLAG_SET_KEY; 4911 node.kflags = htole16(IWN_KFLAG_INVALID); 4912 node.kid = 0xff; 4913 DPRINTF(("delete keys for node %d\n", node.id)); 4914 (void)ops->add_node(sc, &node, 1); 4915 } 4916 #endif 4917 4918 /* XXX Added for NetBSD (copied from rev 1.39). */ 4919 4920 static int 4921 iwn_wme_update(struct ieee80211com *ic) 4922 { 4923 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4924 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4925 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4926 const struct wmeParams *wmep; 4927 struct iwn_edca_params cmd; 4928 int ac; 4929 4930 /* don't override default WME values if WME is not actually enabled */ 4931 if (!(ic->ic_flags & IEEE80211_F_WME)) 4932 return 0; 4933 cmd.flags = 0; 4934 for (ac = 0; ac < WME_NUM_AC; ac++) { 4935 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4936 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4937 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4938 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4939 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4940 4941 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4942 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4943 cmd.ac[ac].cwmin, 4944 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4945 } 4946 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4947 #undef IWN_USEC 4948 #undef IWN_EXP2 4949 } 4950 4951 #ifndef IEEE80211_NO_HT 4952 /* 4953 * This function is called by upper layer when an ADDBA request is received 4954 * from another STA and before the ADDBA response is sent. 4955 */ 4956 static int 4957 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4958 uint8_t tid) 4959 { 4960 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4961 struct iwn_softc *sc = ic->ic_softc; 4962 struct iwn_ops *ops = &sc->ops; 4963 struct iwn_node *wn = (void *)ni; 4964 struct iwn_node_info node; 4965 4966 memset(&node, 0, sizeof node); 4967 node.id = wn->id; 4968 node.control = IWN_NODE_UPDATE; 4969 node.flags = IWN_FLAG_SET_ADDBA; 4970 node.addba_tid = tid; 4971 node.addba_ssn = htole16(ba->ba_winstart); 4972 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4973 ba->ba_winstart)); 4974 return ops->add_node(sc, &node, 1); 4975 } 4976 4977 /* 4978 * This function is called by upper layer on teardown of an HT-immediate 4979 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4980 */ 4981 static void 4982 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4983 uint8_t tid) 4984 { 4985 struct iwn_softc *sc = ic->ic_softc; 4986 struct iwn_ops *ops = &sc->ops; 4987 struct iwn_node *wn = (void *)ni; 4988 struct iwn_node_info node; 4989 4990 memset(&node, 0, sizeof node); 4991 node.id = wn->id; 4992 node.control = IWN_NODE_UPDATE; 4993 node.flags = IWN_FLAG_SET_DELBA; 4994 node.delba_tid = tid; 4995 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4996 (void)ops->add_node(sc, &node, 1); 4997 } 4998 4999 /* 5000 * This function is called by upper layer when an ADDBA response is received 5001 * from another STA. 5002 */ 5003 static int 5004 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5005 uint8_t tid) 5006 { 5007 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5008 struct iwn_softc *sc = ic->ic_softc; 5009 struct iwn_ops *ops = &sc->ops; 5010 struct iwn_node *wn = (void *)ni; 5011 struct iwn_node_info node; 5012 int error; 5013 5014 /* Enable TX for the specified RA/TID. */ 5015 wn->disable_tid &= ~(1 << tid); 5016 memset(&node, 0, sizeof node); 5017 node.id = wn->id; 5018 node.control = IWN_NODE_UPDATE; 5019 node.flags = IWN_FLAG_SET_DISABLE_TID; 5020 node.disable_tid = htole16(wn->disable_tid); 5021 error = ops->add_node(sc, &node, 1); 5022 if (error != 0) 5023 return error; 5024 5025 if ((error = iwn_nic_lock(sc)) != 0) 5026 return error; 5027 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5028 iwn_nic_unlock(sc); 5029 return 0; 5030 } 5031 5032 static void 5033 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5034 uint8_t tid) 5035 { 5036 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5037 struct iwn_softc *sc = ic->ic_softc; 5038 struct iwn_ops *ops = &sc->ops; 5039 5040 if (iwn_nic_lock(sc) != 0) 5041 return; 5042 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5043 iwn_nic_unlock(sc); 5044 } 5045 5046 static void 5047 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5048 uint8_t tid, uint16_t ssn) 5049 { 5050 struct iwn_node *wn = (void *)ni; 5051 int qid = 7 + tid; 5052 5053 /* Stop TX scheduler while we're changing its configuration. */ 5054 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5055 IWN4965_TXQ_STATUS_CHGACT); 5056 5057 /* Assign RA/TID translation to the queue. */ 5058 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5059 wn->id << 4 | tid); 5060 5061 /* Enable chain-building mode for the queue. */ 5062 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5063 5064 /* Set starting sequence number from the ADDBA request. */ 5065 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5066 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5067 5068 /* Set scheduler window size. */ 5069 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5070 IWN_SCHED_WINSZ); 5071 /* Set scheduler frame limit. */ 5072 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5073 IWN_SCHED_LIMIT << 16); 5074 5075 /* Enable interrupts for the queue. */ 5076 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5077 5078 /* Mark the queue as active. */ 5079 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5080 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5081 iwn_tid2fifo[tid] << 1); 5082 } 5083 5084 static void 5085 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5086 { 5087 int qid = 7 + tid; 5088 5089 /* Stop TX scheduler while we're changing its configuration. */ 5090 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5091 IWN4965_TXQ_STATUS_CHGACT); 5092 5093 /* Set starting sequence number from the ADDBA request. */ 5094 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5095 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5096 5097 /* Disable interrupts for the queue. */ 5098 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5099 5100 /* Mark the queue as inactive. */ 5101 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5102 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5103 } 5104 5105 static void 5106 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5107 uint8_t tid, uint16_t ssn) 5108 { 5109 struct iwn_node *wn = (void *)ni; 5110 int qid = 10 + tid; 5111 5112 /* Stop TX scheduler while we're changing its configuration. */ 5113 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5114 IWN5000_TXQ_STATUS_CHGACT); 5115 5116 /* Assign RA/TID translation to the queue. */ 5117 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5118 wn->id << 4 | tid); 5119 5120 /* Enable chain-building mode for the queue. */ 5121 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5122 5123 /* Enable aggregation for the queue. */ 5124 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5125 5126 /* Set starting sequence number from the ADDBA request. */ 5127 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5128 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5129 5130 /* Set scheduler window size and frame limit. */ 5131 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5132 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5133 5134 /* Enable interrupts for the queue. */ 5135 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5136 5137 /* Mark the queue as active. */ 5138 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5139 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5140 } 5141 5142 static void 5143 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5144 { 5145 int qid = 10 + tid; 5146 5147 /* Stop TX scheduler while we're changing its configuration. */ 5148 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5149 IWN5000_TXQ_STATUS_CHGACT); 5150 5151 /* Disable aggregation for the queue. */ 5152 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5153 5154 /* Set starting sequence number from the ADDBA request. */ 5155 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5156 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5157 5158 /* Disable interrupts for the queue. */ 5159 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5160 5161 /* Mark the queue as inactive. */ 5162 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5163 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5164 } 5165 #endif /* !IEEE80211_NO_HT */ 5166 5167 /* 5168 * Query calibration tables from the initialization firmware. We do this 5169 * only once at first boot. Called from a process context. 5170 */ 5171 static int 5172 iwn5000_query_calibration(struct iwn_softc *sc) 5173 { 5174 struct iwn5000_calib_config cmd; 5175 int error; 5176 5177 memset(&cmd, 0, sizeof cmd); 5178 cmd.ucode.once.enable = 0xffffffff; 5179 cmd.ucode.once.start = 0xffffffff; 5180 cmd.ucode.once.send = 0xffffffff; 5181 cmd.ucode.flags = 0xffffffff; 5182 DPRINTF(("sending calibration query\n")); 5183 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5184 if (error != 0) 5185 return error; 5186 5187 /* Wait at most two seconds for calibration to complete. */ 5188 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5189 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 5190 return error; 5191 } 5192 5193 /* 5194 * Send calibration results to the runtime firmware. These results were 5195 * obtained on first boot from the initialization firmware. 5196 */ 5197 static int 5198 iwn5000_send_calibration(struct iwn_softc *sc) 5199 { 5200 int idx, error; 5201 5202 for (idx = 0; idx < 5; idx++) { 5203 if (sc->calibcmd[idx].buf == NULL) 5204 continue; /* No results available. */ 5205 DPRINTF(("send calibration result idx=%d len=%d\n", 5206 idx, sc->calibcmd[idx].len)); 5207 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5208 sc->calibcmd[idx].len, 0); 5209 if (error != 0) { 5210 aprint_error_dev(sc->sc_dev, 5211 "could not send calibration result\n"); 5212 return error; 5213 } 5214 } 5215 return 0; 5216 } 5217 5218 static int 5219 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5220 { 5221 struct iwn5000_wimax_coex wimax; 5222 5223 #ifdef notyet 5224 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5225 /* Enable WiMAX coexistence for combo adapters. */ 5226 wimax.flags = 5227 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5228 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5229 IWN_WIMAX_COEX_STA_TABLE_VALID | 5230 IWN_WIMAX_COEX_ENABLE; 5231 memcpy(wimax.events, iwn6050_wimax_events, 5232 sizeof iwn6050_wimax_events); 5233 } else 5234 #endif 5235 { 5236 /* Disable WiMAX coexistence. */ 5237 wimax.flags = 0; 5238 memset(wimax.events, 0, sizeof wimax.events); 5239 } 5240 DPRINTF(("Configuring WiMAX coexistence\n")); 5241 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5242 } 5243 5244 static int 5245 iwn6000_temp_offset_calib(struct iwn_softc *sc) 5246 { 5247 struct iwn6000_phy_calib_temp_offset cmd; 5248 5249 memset(&cmd, 0, sizeof cmd); 5250 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 5251 cmd.ngroups = 1; 5252 cmd.isvalid = 1; 5253 if (sc->eeprom_temp != 0) 5254 cmd.offset = htole16(sc->eeprom_temp); 5255 else 5256 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5257 DPRINTF(("setting radio sensor offset to %d\n", le16toh(cmd.offset))); 5258 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5259 } 5260 5261 static int 5262 iwn2000_temp_offset_calib(struct iwn_softc *sc) 5263 { 5264 struct iwn2000_phy_calib_temp_offset cmd; 5265 5266 memset(&cmd, 0, sizeof cmd); 5267 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 5268 cmd.ngroups = 1; 5269 cmd.isvalid = 1; 5270 if (sc->eeprom_rawtemp != 0) { 5271 cmd.offset_low = htole16(sc->eeprom_rawtemp); 5272 cmd.offset_high = htole16(sc->eeprom_temp); 5273 } else { 5274 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 5275 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 5276 } 5277 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 5278 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 5279 le16toh(cmd.offset_low), le16toh(cmd.offset_high), 5280 le16toh(cmd.burnt_voltage_ref))); 5281 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5282 } 5283 5284 /* 5285 * This function is called after the runtime firmware notifies us of its 5286 * readiness (called in a process context). 5287 */ 5288 static int 5289 iwn4965_post_alive(struct iwn_softc *sc) 5290 { 5291 int error, qid; 5292 5293 if ((error = iwn_nic_lock(sc)) != 0) 5294 return error; 5295 5296 /* Clear TX scheduler state in SRAM. */ 5297 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5298 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5299 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5300 5301 /* Set physical address of TX scheduler rings (1KB aligned). */ 5302 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5303 5304 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5305 5306 /* Disable chain mode for all our 16 queues. */ 5307 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5308 5309 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5310 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5311 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5312 5313 /* Set scheduler window size. */ 5314 iwn_mem_write(sc, sc->sched_base + 5315 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5316 /* Set scheduler frame limit. */ 5317 iwn_mem_write(sc, sc->sched_base + 5318 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5319 IWN_SCHED_LIMIT << 16); 5320 } 5321 5322 /* Enable interrupts for all our 16 queues. */ 5323 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5324 /* Identify TX FIFO rings (0-7). */ 5325 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5326 5327 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5328 for (qid = 0; qid < 7; qid++) { 5329 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5330 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5331 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5332 } 5333 iwn_nic_unlock(sc); 5334 return 0; 5335 } 5336 5337 /* 5338 * This function is called after the initialization or runtime firmware 5339 * notifies us of its readiness (called in a process context). 5340 */ 5341 static int 5342 iwn5000_post_alive(struct iwn_softc *sc) 5343 { 5344 int error, qid; 5345 5346 /* Switch to using ICT interrupt mode. */ 5347 iwn5000_ict_reset(sc); 5348 5349 if ((error = iwn_nic_lock(sc)) != 0) 5350 return error; 5351 5352 /* Clear TX scheduler state in SRAM. */ 5353 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5354 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5355 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5356 5357 /* Set physical address of TX scheduler rings (1KB aligned). */ 5358 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5359 5360 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5361 5362 /* Enable chain mode for all queues, except command queue. */ 5363 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5364 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5365 5366 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5367 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5368 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5369 5370 iwn_mem_write(sc, sc->sched_base + 5371 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5372 /* Set scheduler window size and frame limit. */ 5373 iwn_mem_write(sc, sc->sched_base + 5374 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5375 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5376 } 5377 5378 /* Enable interrupts for all our 20 queues. */ 5379 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5380 /* Identify TX FIFO rings (0-7). */ 5381 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5382 5383 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5384 for (qid = 0; qid < 7; qid++) { 5385 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5386 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5387 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5388 } 5389 iwn_nic_unlock(sc); 5390 5391 /* Configure WiMAX coexistence for combo adapters. */ 5392 error = iwn5000_send_wimax_coex(sc); 5393 if (error != 0) { 5394 aprint_error_dev(sc->sc_dev, 5395 "could not configure WiMAX coexistence\n"); 5396 return error; 5397 } 5398 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5399 struct iwn5000_phy_calib_crystal cmd; 5400 5401 /* Perform crystal calibration. */ 5402 memset(&cmd, 0, sizeof cmd); 5403 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5404 cmd.ngroups = 1; 5405 cmd.isvalid = 1; 5406 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5407 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5408 DPRINTF(("sending crystal calibration %d, %d\n", 5409 cmd.cap_pin[0], cmd.cap_pin[1])); 5410 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5411 if (error != 0) { 5412 aprint_error_dev(sc->sc_dev, 5413 "crystal calibration failed\n"); 5414 return error; 5415 } 5416 } 5417 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5418 /* Query calibration from the initialization firmware. */ 5419 if ((error = iwn5000_query_calibration(sc)) != 0) { 5420 aprint_error_dev(sc->sc_dev, 5421 "could not query calibration\n"); 5422 return error; 5423 } 5424 /* 5425 * We have the calibration results now, reboot with the 5426 * runtime firmware (call ourselves recursively!) 5427 */ 5428 iwn_hw_stop(sc); 5429 error = iwn_hw_init(sc); 5430 } else { 5431 /* Send calibration results to runtime firmware. */ 5432 error = iwn5000_send_calibration(sc); 5433 } 5434 return error; 5435 } 5436 5437 /* 5438 * The firmware boot code is small and is intended to be copied directly into 5439 * the NIC internal memory (no DMA transfer). 5440 */ 5441 static int 5442 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5443 { 5444 int error, ntries; 5445 5446 size /= sizeof (uint32_t); 5447 5448 if ((error = iwn_nic_lock(sc)) != 0) 5449 return error; 5450 5451 /* Copy microcode image into NIC memory. */ 5452 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5453 (const uint32_t *)ucode, size); 5454 5455 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5456 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5457 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5458 5459 /* Start boot load now. */ 5460 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5461 5462 /* Wait for transfer to complete. */ 5463 for (ntries = 0; ntries < 1000; ntries++) { 5464 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5465 IWN_BSM_WR_CTRL_START)) 5466 break; 5467 DELAY(10); 5468 } 5469 if (ntries == 1000) { 5470 aprint_error_dev(sc->sc_dev, 5471 "could not load boot firmware\n"); 5472 iwn_nic_unlock(sc); 5473 return ETIMEDOUT; 5474 } 5475 5476 /* Enable boot after power up. */ 5477 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5478 5479 iwn_nic_unlock(sc); 5480 return 0; 5481 } 5482 5483 static int 5484 iwn4965_load_firmware(struct iwn_softc *sc) 5485 { 5486 struct iwn_fw_info *fw = &sc->fw; 5487 struct iwn_dma_info *dma = &sc->fw_dma; 5488 int error; 5489 5490 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5491 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5492 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5493 BUS_DMASYNC_PREWRITE); 5494 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5495 fw->init.text, fw->init.textsz); 5496 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5497 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5498 5499 /* Tell adapter where to find initialization sections. */ 5500 if ((error = iwn_nic_lock(sc)) != 0) 5501 return error; 5502 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5503 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5504 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5505 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5506 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5507 iwn_nic_unlock(sc); 5508 5509 /* Load firmware boot code. */ 5510 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5511 if (error != 0) { 5512 aprint_error_dev(sc->sc_dev, 5513 "could not load boot firmware\n"); 5514 return error; 5515 } 5516 /* Now press "execute". */ 5517 IWN_WRITE(sc, IWN_RESET, 0); 5518 5519 /* Wait at most one second for first alive notification. */ 5520 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5521 aprint_error_dev(sc->sc_dev, 5522 "timeout waiting for adapter to initialize\n"); 5523 return error; 5524 } 5525 5526 /* Retrieve current temperature for initial TX power calibration. */ 5527 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5528 sc->temp = iwn4965_get_temperature(sc); 5529 5530 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5531 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5532 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5533 BUS_DMASYNC_PREWRITE); 5534 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5535 fw->main.text, fw->main.textsz); 5536 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5537 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5538 5539 /* Tell adapter where to find runtime sections. */ 5540 if ((error = iwn_nic_lock(sc)) != 0) 5541 return error; 5542 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5543 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5544 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5545 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5546 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5547 IWN_FW_UPDATED | fw->main.textsz); 5548 iwn_nic_unlock(sc); 5549 5550 return 0; 5551 } 5552 5553 static int 5554 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5555 const uint8_t *section, int size) 5556 { 5557 struct iwn_dma_info *dma = &sc->fw_dma; 5558 int error; 5559 5560 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5561 memcpy(dma->vaddr, section, size); 5562 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5563 5564 if ((error = iwn_nic_lock(sc)) != 0) 5565 return error; 5566 5567 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5568 IWN_FH_TX_CONFIG_DMA_PAUSE); 5569 5570 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5571 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5572 IWN_LOADDR(dma->paddr)); 5573 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5574 IWN_HIADDR(dma->paddr) << 28 | size); 5575 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5576 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5577 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5578 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5579 5580 /* Kick Flow Handler to start DMA transfer. */ 5581 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5582 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5583 5584 iwn_nic_unlock(sc); 5585 5586 /* Wait at most five seconds for FH DMA transfer to complete. */ 5587 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5588 } 5589 5590 static int 5591 iwn5000_load_firmware(struct iwn_softc *sc) 5592 { 5593 struct iwn_fw_part *fw; 5594 int error; 5595 5596 /* Load the initialization firmware on first boot only. */ 5597 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5598 &sc->fw.main : &sc->fw.init; 5599 5600 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5601 fw->text, fw->textsz); 5602 if (error != 0) { 5603 aprint_error_dev(sc->sc_dev, 5604 "could not load firmware %s section\n", ".text"); 5605 return error; 5606 } 5607 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5608 fw->data, fw->datasz); 5609 if (error != 0) { 5610 aprint_error_dev(sc->sc_dev, 5611 "could not load firmware %s section\n", ".data"); 5612 return error; 5613 } 5614 5615 /* Now press "execute". */ 5616 IWN_WRITE(sc, IWN_RESET, 0); 5617 return 0; 5618 } 5619 5620 /* 5621 * Extract text and data sections from a legacy firmware image. 5622 */ 5623 static int 5624 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5625 { 5626 const uint32_t *ptr; 5627 size_t hdrlen = 24; 5628 uint32_t rev; 5629 5630 ptr = (const uint32_t *)fw->data; 5631 rev = le32toh(*ptr++); 5632 5633 /* Check firmware API version. */ 5634 if (IWN_FW_API(rev) <= 1) { 5635 aprint_error_dev(sc->sc_dev, 5636 "bad firmware, need API version >=2\n"); 5637 return EINVAL; 5638 } 5639 if (IWN_FW_API(rev) >= 3) { 5640 /* Skip build number (version 2 header). */ 5641 hdrlen += 4; 5642 ptr++; 5643 } 5644 if (fw->size < hdrlen) { 5645 aprint_error_dev(sc->sc_dev, 5646 "firmware too short: %zd bytes\n", fw->size); 5647 return EINVAL; 5648 } 5649 fw->main.textsz = le32toh(*ptr++); 5650 fw->main.datasz = le32toh(*ptr++); 5651 fw->init.textsz = le32toh(*ptr++); 5652 fw->init.datasz = le32toh(*ptr++); 5653 fw->boot.textsz = le32toh(*ptr++); 5654 5655 /* Check that all firmware sections fit. */ 5656 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5657 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5658 aprint_error_dev(sc->sc_dev, 5659 "firmware too short: %zd bytes\n", fw->size); 5660 return EINVAL; 5661 } 5662 5663 /* Get pointers to firmware sections. */ 5664 fw->main.text = (const uint8_t *)ptr; 5665 fw->main.data = fw->main.text + fw->main.textsz; 5666 fw->init.text = fw->main.data + fw->main.datasz; 5667 fw->init.data = fw->init.text + fw->init.textsz; 5668 fw->boot.text = fw->init.data + fw->init.datasz; 5669 return 0; 5670 } 5671 5672 /* 5673 * Extract text and data sections from a TLV firmware image. 5674 */ 5675 static int 5676 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5677 uint16_t alt) 5678 { 5679 const struct iwn_fw_tlv_hdr *hdr; 5680 const struct iwn_fw_tlv *tlv; 5681 const uint8_t *ptr, *end; 5682 uint64_t altmask; 5683 uint32_t len; 5684 5685 if (fw->size < sizeof (*hdr)) { 5686 aprint_error_dev(sc->sc_dev, 5687 "firmware too short: %zd bytes\n", fw->size); 5688 return EINVAL; 5689 } 5690 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5691 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5692 aprint_error_dev(sc->sc_dev, 5693 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5694 return EINVAL; 5695 } 5696 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5697 le32toh(hdr->build))); 5698 5699 /* 5700 * Select the closest supported alternative that is less than 5701 * or equal to the specified one. 5702 */ 5703 altmask = le64toh(hdr->altmask); 5704 while (alt > 0 && !(altmask & (1ULL << alt))) 5705 alt--; /* Downgrade. */ 5706 DPRINTF(("using alternative %d\n", alt)); 5707 5708 ptr = (const uint8_t *)(hdr + 1); 5709 end = (const uint8_t *)(fw->data + fw->size); 5710 5711 /* Parse type-length-value fields. */ 5712 while (ptr + sizeof (*tlv) <= end) { 5713 tlv = (const struct iwn_fw_tlv *)ptr; 5714 len = le32toh(tlv->len); 5715 5716 ptr += sizeof (*tlv); 5717 if (ptr + len > end) { 5718 aprint_error_dev(sc->sc_dev, 5719 "firmware too short: %zd bytes\n", fw->size); 5720 return EINVAL; 5721 } 5722 /* Skip other alternatives. */ 5723 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5724 goto next; 5725 5726 switch (le16toh(tlv->type)) { 5727 case IWN_FW_TLV_MAIN_TEXT: 5728 fw->main.text = ptr; 5729 fw->main.textsz = len; 5730 break; 5731 case IWN_FW_TLV_MAIN_DATA: 5732 fw->main.data = ptr; 5733 fw->main.datasz = len; 5734 break; 5735 case IWN_FW_TLV_INIT_TEXT: 5736 fw->init.text = ptr; 5737 fw->init.textsz = len; 5738 break; 5739 case IWN_FW_TLV_INIT_DATA: 5740 fw->init.data = ptr; 5741 fw->init.datasz = len; 5742 break; 5743 case IWN_FW_TLV_BOOT_TEXT: 5744 fw->boot.text = ptr; 5745 fw->boot.textsz = len; 5746 break; 5747 case IWN_FW_TLV_ENH_SENS: 5748 if (len != 0) { 5749 aprint_error_dev(sc->sc_dev, 5750 "TLV type %d has invalid size %u\n", 5751 le16toh(tlv->type), len); 5752 goto next; 5753 } 5754 sc->sc_flags |= IWN_FLAG_ENH_SENS; 5755 break; 5756 case IWN_FW_TLV_PHY_CALIB: 5757 if (len != sizeof(uint32_t)) { 5758 aprint_error_dev(sc->sc_dev, 5759 "TLV type %d has invalid size %u\n", 5760 le16toh(tlv->type), len); 5761 goto next; 5762 } 5763 if (le32toh(*ptr) <= IWN5000_PHY_CALIB_MAX) { 5764 sc->reset_noise_gain = le32toh(*ptr); 5765 sc->noise_gain = le32toh(*ptr) + 1; 5766 } 5767 break; 5768 case IWN_FW_TLV_FLAGS: 5769 if (len < sizeof(uint32_t)) 5770 break; 5771 if (len % sizeof(uint32_t)) 5772 break; 5773 sc->tlv_feature_flags = le32toh(*ptr); 5774 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 5775 break; 5776 default: 5777 DPRINTF(("TLV type %d not handled\n", 5778 le16toh(tlv->type))); 5779 break; 5780 } 5781 next: /* TLV fields are 32-bit aligned. */ 5782 ptr += (len + 3) & ~3; 5783 } 5784 return 0; 5785 } 5786 5787 static int 5788 iwn_read_firmware(struct iwn_softc *sc) 5789 { 5790 struct iwn_fw_info *fw = &sc->fw; 5791 firmware_handle_t fwh; 5792 int error; 5793 5794 /* 5795 * Some PHY calibration commands are firmware-dependent; these 5796 * are the default values that will be overridden if 5797 * necessary. 5798 */ 5799 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 5800 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 5801 5802 /* Initialize for error returns */ 5803 fw->data = NULL; 5804 fw->size = 0; 5805 5806 /* Open firmware image. */ 5807 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5808 aprint_error_dev(sc->sc_dev, 5809 "could not get firmware handle %s\n", sc->fwname); 5810 return error; 5811 } 5812 fw->size = firmware_get_size(fwh); 5813 if (fw->size < sizeof (uint32_t)) { 5814 aprint_error_dev(sc->sc_dev, 5815 "firmware too short: %zd bytes\n", fw->size); 5816 firmware_close(fwh); 5817 return EINVAL; 5818 } 5819 5820 /* Read the firmware. */ 5821 fw->data = firmware_malloc(fw->size); 5822 if (fw->data == NULL) { 5823 aprint_error_dev(sc->sc_dev, 5824 "not enough memory to stock firmware %s\n", sc->fwname); 5825 firmware_close(fwh); 5826 return ENOMEM; 5827 } 5828 error = firmware_read(fwh, 0, fw->data, fw->size); 5829 firmware_close(fwh); 5830 if (error != 0) { 5831 aprint_error_dev(sc->sc_dev, 5832 "could not read firmware %s\n", sc->fwname); 5833 goto out; 5834 } 5835 5836 /* Retrieve text and data sections. */ 5837 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5838 error = iwn_read_firmware_leg(sc, fw); 5839 else 5840 error = iwn_read_firmware_tlv(sc, fw, 1); 5841 if (error != 0) { 5842 aprint_error_dev(sc->sc_dev, 5843 "could not read firmware sections\n"); 5844 goto out; 5845 } 5846 5847 /* Make sure text and data sections fit in hardware memory. */ 5848 if (fw->main.textsz > sc->fw_text_maxsz || 5849 fw->main.datasz > sc->fw_data_maxsz || 5850 fw->init.textsz > sc->fw_text_maxsz || 5851 fw->init.datasz > sc->fw_data_maxsz || 5852 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5853 (fw->boot.textsz & 3) != 0) { 5854 aprint_error_dev(sc->sc_dev, 5855 "firmware sections too large\n"); 5856 goto out; 5857 } 5858 5859 /* We can proceed with loading the firmware. */ 5860 return 0; 5861 out: 5862 firmware_free(fw->data, fw->size); 5863 fw->data = NULL; 5864 fw->size = 0; 5865 return error ? error : EINVAL; 5866 } 5867 5868 static int 5869 iwn_clock_wait(struct iwn_softc *sc) 5870 { 5871 int ntries; 5872 5873 /* Set "initialization complete" bit. */ 5874 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5875 5876 /* Wait for clock stabilization. */ 5877 for (ntries = 0; ntries < 2500; ntries++) { 5878 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5879 return 0; 5880 DELAY(10); 5881 } 5882 aprint_error_dev(sc->sc_dev, 5883 "timeout waiting for clock stabilization\n"); 5884 return ETIMEDOUT; 5885 } 5886 5887 static int 5888 iwn_apm_init(struct iwn_softc *sc) 5889 { 5890 pcireg_t reg; 5891 int error; 5892 5893 /* Disable L0s exit timer (NMI bug workaround). */ 5894 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5895 /* Don't wait for ICH L0s (ICH bug workaround). */ 5896 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5897 5898 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5899 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5900 5901 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5902 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5903 5904 /* Retrieve PCIe Active State Power Management (ASPM). */ 5905 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5906 sc->sc_cap_off + PCIE_LCSR); 5907 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5908 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5909 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5910 else 5911 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5912 5913 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5914 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5915 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5916 5917 /* Wait for clock stabilization before accessing prph. */ 5918 if ((error = iwn_clock_wait(sc)) != 0) 5919 return error; 5920 5921 if ((error = iwn_nic_lock(sc)) != 0) 5922 return error; 5923 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5924 /* Enable DMA and BSM (Bootstrap State Machine). */ 5925 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5926 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5927 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5928 } else { 5929 /* Enable DMA. */ 5930 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5931 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5932 } 5933 DELAY(20); 5934 /* Disable L1-Active. */ 5935 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5936 iwn_nic_unlock(sc); 5937 5938 return 0; 5939 } 5940 5941 static void 5942 iwn_apm_stop_master(struct iwn_softc *sc) 5943 { 5944 int ntries; 5945 5946 /* Stop busmaster DMA activity. */ 5947 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5948 for (ntries = 0; ntries < 100; ntries++) { 5949 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5950 return; 5951 DELAY(10); 5952 } 5953 aprint_error_dev(sc->sc_dev, 5954 "timeout waiting for master\n"); 5955 } 5956 5957 static void 5958 iwn_apm_stop(struct iwn_softc *sc) 5959 { 5960 iwn_apm_stop_master(sc); 5961 5962 /* Reset the entire device. */ 5963 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5964 DELAY(10); 5965 /* Clear "initialization complete" bit. */ 5966 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5967 } 5968 5969 static int 5970 iwn4965_nic_config(struct iwn_softc *sc) 5971 { 5972 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5973 /* 5974 * I don't believe this to be correct but this is what the 5975 * vendor driver is doing. Probably the bits should not be 5976 * shifted in IWN_RFCFG_*. 5977 */ 5978 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5979 IWN_RFCFG_TYPE(sc->rfcfg) | 5980 IWN_RFCFG_STEP(sc->rfcfg) | 5981 IWN_RFCFG_DASH(sc->rfcfg)); 5982 } 5983 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5984 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5985 return 0; 5986 } 5987 5988 static int 5989 iwn5000_nic_config(struct iwn_softc *sc) 5990 { 5991 uint32_t tmp; 5992 int error; 5993 5994 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5995 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5996 IWN_RFCFG_TYPE(sc->rfcfg) | 5997 IWN_RFCFG_STEP(sc->rfcfg) | 5998 IWN_RFCFG_DASH(sc->rfcfg)); 5999 } 6000 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6001 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6002 6003 if ((error = iwn_nic_lock(sc)) != 0) 6004 return error; 6005 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6006 6007 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6008 /* 6009 * Select first Switching Voltage Regulator (1.32V) to 6010 * solve a stability issue related to noisy DC2DC line 6011 * in the silicon of 1000 Series. 6012 */ 6013 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6014 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6015 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6016 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6017 } 6018 iwn_nic_unlock(sc); 6019 6020 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6021 /* Use internal power amplifier only. */ 6022 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6023 } 6024 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6025 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6026 /* Indicate that ROM calibration version is >=6. */ 6027 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6028 } 6029 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6030 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6031 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6032 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6033 sc->hw_type == IWN_HW_REV_TYPE_135 || 6034 sc->hw_type == IWN_HW_REV_TYPE_105) 6035 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6036 return 0; 6037 } 6038 6039 /* 6040 * Take NIC ownership over Intel Active Management Technology (AMT). 6041 */ 6042 static int 6043 iwn_hw_prepare(struct iwn_softc *sc) 6044 { 6045 int ntries; 6046 6047 /* Check if hardware is ready. */ 6048 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6049 for (ntries = 0; ntries < 5; ntries++) { 6050 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6051 IWN_HW_IF_CONFIG_NIC_READY) 6052 return 0; 6053 DELAY(10); 6054 } 6055 6056 /* Hardware not ready, force into ready state. */ 6057 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6058 for (ntries = 0; ntries < 15000; ntries++) { 6059 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6060 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6061 break; 6062 DELAY(10); 6063 } 6064 if (ntries == 15000) 6065 return ETIMEDOUT; 6066 6067 /* Hardware should be ready now. */ 6068 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6069 for (ntries = 0; ntries < 5; ntries++) { 6070 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6071 IWN_HW_IF_CONFIG_NIC_READY) 6072 return 0; 6073 DELAY(10); 6074 } 6075 return ETIMEDOUT; 6076 } 6077 6078 static int 6079 iwn_hw_init(struct iwn_softc *sc) 6080 { 6081 struct iwn_ops *ops = &sc->ops; 6082 int error, chnl, qid; 6083 6084 /* Clear pending interrupts. */ 6085 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6086 6087 if ((error = iwn_apm_init(sc)) != 0) { 6088 aprint_error_dev(sc->sc_dev, 6089 "could not power ON adapter\n"); 6090 return error; 6091 } 6092 6093 /* Select VMAIN power source. */ 6094 if ((error = iwn_nic_lock(sc)) != 0) 6095 return error; 6096 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6097 iwn_nic_unlock(sc); 6098 6099 /* Perform adapter-specific initialization. */ 6100 if ((error = ops->nic_config(sc)) != 0) 6101 return error; 6102 6103 /* Initialize RX ring. */ 6104 if ((error = iwn_nic_lock(sc)) != 0) 6105 return error; 6106 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6107 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6108 /* Set physical address of RX ring (256-byte aligned). */ 6109 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6110 /* Set physical address of RX status (16-byte aligned). */ 6111 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6112 /* Enable RX. */ 6113 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6114 IWN_FH_RX_CONFIG_ENA | 6115 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6116 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6117 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6118 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6119 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6120 iwn_nic_unlock(sc); 6121 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6122 6123 if ((error = iwn_nic_lock(sc)) != 0) 6124 return error; 6125 6126 /* Initialize TX scheduler. */ 6127 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6128 6129 /* Set physical address of "keep warm" page (16-byte aligned). */ 6130 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6131 6132 /* Initialize TX rings. */ 6133 for (qid = 0; qid < sc->ntxqs; qid++) { 6134 struct iwn_tx_ring *txq = &sc->txq[qid]; 6135 6136 /* Set physical address of TX ring (256-byte aligned). */ 6137 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6138 txq->desc_dma.paddr >> 8); 6139 } 6140 iwn_nic_unlock(sc); 6141 6142 /* Enable DMA channels. */ 6143 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6144 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6145 IWN_FH_TX_CONFIG_DMA_ENA | 6146 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6147 } 6148 6149 /* Clear "radio off" and "commands blocked" bits. */ 6150 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6151 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6152 6153 /* Clear pending interrupts. */ 6154 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6155 /* Enable interrupt coalescing. */ 6156 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6157 /* Enable interrupts. */ 6158 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6159 6160 /* _Really_ make sure "radio off" bit is cleared! */ 6161 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6162 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6163 6164 /* Enable shadow registers. */ 6165 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6166 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6167 6168 if ((error = ops->load_firmware(sc)) != 0) { 6169 aprint_error_dev(sc->sc_dev, 6170 "could not load firmware\n"); 6171 return error; 6172 } 6173 /* Wait at most one second for firmware alive notification. */ 6174 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 6175 aprint_error_dev(sc->sc_dev, 6176 "timeout waiting for adapter to initialize\n"); 6177 return error; 6178 } 6179 /* Do post-firmware initialization. */ 6180 return ops->post_alive(sc); 6181 } 6182 6183 static void 6184 iwn_hw_stop(struct iwn_softc *sc) 6185 { 6186 int chnl, qid, ntries; 6187 6188 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6189 6190 /* Disable interrupts. */ 6191 IWN_WRITE(sc, IWN_INT_MASK, 0); 6192 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6193 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6194 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6195 6196 /* Make sure we no longer hold the NIC lock. */ 6197 iwn_nic_unlock(sc); 6198 6199 /* Stop TX scheduler. */ 6200 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6201 6202 /* Stop all DMA channels. */ 6203 if (iwn_nic_lock(sc) == 0) { 6204 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6205 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6206 for (ntries = 0; ntries < 200; ntries++) { 6207 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6208 IWN_FH_TX_STATUS_IDLE(chnl)) 6209 break; 6210 DELAY(10); 6211 } 6212 } 6213 iwn_nic_unlock(sc); 6214 } 6215 6216 /* Stop RX ring. */ 6217 iwn_reset_rx_ring(sc, &sc->rxq); 6218 6219 /* Reset all TX rings. */ 6220 for (qid = 0; qid < sc->ntxqs; qid++) 6221 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6222 6223 if (iwn_nic_lock(sc) == 0) { 6224 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6225 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6226 iwn_nic_unlock(sc); 6227 } 6228 DELAY(5); 6229 /* Power OFF adapter. */ 6230 iwn_apm_stop(sc); 6231 } 6232 6233 static int 6234 iwn_init(struct ifnet *ifp) 6235 { 6236 struct iwn_softc *sc = ifp->if_softc; 6237 struct ieee80211com *ic = &sc->sc_ic; 6238 int error; 6239 6240 mutex_enter(&sc->sc_mtx); 6241 if (sc->sc_flags & IWN_FLAG_HW_INITED) 6242 goto out; 6243 if ((error = iwn_hw_prepare(sc)) != 0) { 6244 aprint_error_dev(sc->sc_dev, 6245 "hardware not ready\n"); 6246 goto fail; 6247 } 6248 6249 /* Check that the radio is not disabled by hardware switch. */ 6250 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6251 aprint_error_dev(sc->sc_dev, 6252 "radio is disabled by hardware switch\n"); 6253 error = EPERM; /* :-) */ 6254 goto fail; 6255 } 6256 6257 /* Read firmware images from the filesystem. */ 6258 if ((error = iwn_read_firmware(sc)) != 0) { 6259 aprint_error_dev(sc->sc_dev, 6260 "could not read firmware\n"); 6261 goto fail; 6262 } 6263 6264 /* Initialize interrupt mask to default value. */ 6265 sc->int_mask = IWN_INT_MASK_DEF; 6266 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6267 6268 /* Initialize hardware and upload firmware. */ 6269 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 6270 error = iwn_hw_init(sc); 6271 firmware_free(sc->fw.data, sc->fw.size); 6272 sc->fw.data = NULL; 6273 sc->fw.size = 0; 6274 if (error != 0) { 6275 aprint_error_dev(sc->sc_dev, 6276 "could not initialize hardware\n"); 6277 goto fail; 6278 } 6279 6280 /* Configure adapter now that it is ready. */ 6281 if ((error = iwn_config(sc)) != 0) { 6282 aprint_error_dev(sc->sc_dev, 6283 "could not configure device\n"); 6284 goto fail; 6285 } 6286 6287 ifp->if_flags &= ~IFF_OACTIVE; 6288 ifp->if_flags |= IFF_RUNNING; 6289 6290 if (ic->ic_opmode != IEEE80211_M_MONITOR) 6291 ieee80211_begin_scan(ic, 0); 6292 else 6293 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 6294 6295 sc->sc_flags |= IWN_FLAG_HW_INITED; 6296 out: 6297 mutex_exit(&sc->sc_mtx); 6298 return 0; 6299 6300 fail: mutex_exit(&sc->sc_mtx); 6301 iwn_stop(ifp, 1); 6302 return error; 6303 } 6304 6305 static void 6306 iwn_stop(struct ifnet *ifp, int disable) 6307 { 6308 struct iwn_softc *sc = ifp->if_softc; 6309 struct ieee80211com *ic = &sc->sc_ic; 6310 6311 if (!disable) 6312 mutex_enter(&sc->sc_mtx); 6313 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 6314 ifp->if_timer = sc->sc_tx_timer = 0; 6315 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6316 6317 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6318 6319 /* Power OFF hardware. */ 6320 iwn_hw_stop(sc); 6321 6322 if (!disable) 6323 mutex_exit(&sc->sc_mtx); 6324 } 6325 6326 /* 6327 * XXX MCLGETI alternative 6328 * 6329 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 6330 * as long as there are available free buffers then it uses MEXTMALLOC., 6331 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 6332 * The MCLGET4K code is used for testing an alternative mbuf cache. 6333 */ 6334 6335 static struct mbuf * 6336 MCLGETIalt(struct iwn_softc *sc, int how, 6337 struct ifnet *ifp __unused, u_int size) 6338 { 6339 struct mbuf *m; 6340 #ifdef IWN_USE_RBUF 6341 struct iwn_rbuf *rbuf; 6342 #endif 6343 6344 MGETHDR(m, how, MT_DATA); 6345 if (m == NULL) 6346 return NULL; 6347 6348 #ifdef IWN_USE_RBUF 6349 if (sc->rxq.nb_free_entries > 0 && 6350 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 6351 /* Attach buffer to mbuf header. */ 6352 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 6353 m->m_flags |= M_EXT_RW; 6354 } 6355 else { 6356 MEXTMALLOC(m, size, how); 6357 if ((m->m_flags & M_EXT) == 0) { 6358 m_freem(m); 6359 return NULL; 6360 } 6361 } 6362 6363 #else 6364 #ifdef MCLGET4K 6365 if (size == 4096) 6366 MCLGET4K(m, how); 6367 else 6368 panic("size must be 4k"); 6369 #else 6370 MEXTMALLOC(m, size, how); 6371 #endif 6372 if ((m->m_flags & M_EXT) == 0) { 6373 m_freem(m); 6374 return NULL; 6375 } 6376 #endif 6377 6378 return m; 6379 } 6380 6381 #ifdef IWN_USE_RBUF 6382 static struct iwn_rbuf * 6383 iwn_alloc_rbuf(struct iwn_softc *sc) 6384 { 6385 struct iwn_rbuf *rbuf; 6386 mutex_enter(&sc->rxq.freelist_mtx); 6387 6388 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6389 if (rbuf != NULL) { 6390 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6391 sc->rxq.nb_free_entries --; 6392 } 6393 mutex_exit(&sc->rxq.freelist_mtx); 6394 return rbuf; 6395 } 6396 6397 /* 6398 * This is called automatically by the network stack when the mbuf to which 6399 * our RX buffer is attached is freed. 6400 */ 6401 static void 6402 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6403 { 6404 struct iwn_rbuf *rbuf = arg; 6405 struct iwn_softc *sc = rbuf->sc; 6406 6407 /* Put the RX buffer back in the free list. */ 6408 mutex_enter(&sc->rxq.freelist_mtx); 6409 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6410 mutex_exit(&sc->rxq.freelist_mtx); 6411 6412 sc->rxq.nb_free_entries ++; 6413 if (__predict_true(m != NULL)) 6414 pool_cache_put(mb_cache, m); 6415 } 6416 6417 static int 6418 iwn_alloc_rpool(struct iwn_softc *sc) 6419 { 6420 struct iwn_rx_ring *ring = &sc->rxq; 6421 struct iwn_rbuf *rbuf; 6422 int i, error; 6423 6424 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6425 6426 /* Allocate a big chunk of DMA'able memory... */ 6427 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6428 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6429 if (error != 0) { 6430 aprint_error_dev(sc->sc_dev, 6431 "could not allocate RX buffers DMA memory\n"); 6432 return error; 6433 } 6434 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6435 SLIST_INIT(&ring->freelist); 6436 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6437 rbuf = &ring->rbuf[i]; 6438 6439 rbuf->sc = sc; /* Backpointer for callbacks. */ 6440 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6441 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6442 6443 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6444 } 6445 ring->nb_free_entries = IWN_RBUF_COUNT; 6446 return 0; 6447 } 6448 6449 static void 6450 iwn_free_rpool(struct iwn_softc *sc) 6451 { 6452 iwn_dma_contig_free(&sc->rxq.buf_dma); 6453 } 6454 #endif 6455 6456 /* 6457 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6458 * Copyright (c) 2001 Atsushi Onoe 6459 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6460 * Copyright (c) 2007-2009 Damien Bergamini 6461 * All rights reserved. 6462 */ 6463 6464 /* 6465 * Add an SSID element to a frame (see 7.3.2.1). 6466 */ 6467 static u_int8_t * 6468 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6469 { 6470 *frm++ = IEEE80211_ELEMID_SSID; 6471 *frm++ = len; 6472 memcpy(frm, ssid, len); 6473 return frm + len; 6474 } 6475 6476 /* 6477 * Add a supported rates element to a frame (see 7.3.2.2). 6478 */ 6479 static u_int8_t * 6480 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6481 { 6482 int nrates; 6483 6484 *frm++ = IEEE80211_ELEMID_RATES; 6485 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6486 *frm++ = nrates; 6487 memcpy(frm, rs->rs_rates, nrates); 6488 return frm + nrates; 6489 } 6490 6491 /* 6492 * Add an extended supported rates element to a frame (see 7.3.2.14). 6493 */ 6494 static u_int8_t * 6495 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6496 { 6497 int nrates; 6498 6499 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6500 6501 *frm++ = IEEE80211_ELEMID_XRATES; 6502 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6503 *frm++ = nrates; 6504 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6505 return frm + nrates; 6506 } 6507 6508 /* 6509 * XXX: Hack to set the current channel to the value advertised in beacons or 6510 * probe responses. Only used during AP detection. 6511 * XXX: Duplicated from if_iwi.c 6512 */ 6513 static void 6514 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6515 { 6516 struct ieee80211_frame *wh; 6517 uint8_t subtype; 6518 uint8_t *frm, *efrm; 6519 6520 wh = mtod(m, struct ieee80211_frame *); 6521 6522 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6523 return; 6524 6525 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6526 6527 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6528 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6529 return; 6530 6531 frm = (uint8_t *)(wh + 1); 6532 efrm = mtod(m, uint8_t *) + m->m_len; 6533 6534 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6535 while (frm < efrm) { 6536 if (*frm == IEEE80211_ELEMID_DSPARMS) 6537 #if IEEE80211_CHAN_MAX < 255 6538 if (frm[2] <= IEEE80211_CHAN_MAX) 6539 #endif 6540 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6541 6542 frm += frm[1] + 2; 6543 } 6544 } 6545 6546 #ifdef notyetMODULE 6547 6548 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci"); 6549 6550 #ifdef _MODULE 6551 #include "ioconf.c" 6552 #endif 6553 6554 static int 6555 if_iwn_modcmd(modcmd_t cmd, void *data) 6556 { 6557 int error = 0; 6558 6559 switch (cmd) { 6560 case MODULE_CMD_INIT: 6561 #ifdef _MODULE 6562 error = config_init_component(cfdriver_ioconf_if_iwn, 6563 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6564 #endif 6565 return error; 6566 case MODULE_CMD_FINI: 6567 #ifdef _MODULE 6568 error = config_fini_component(cfdriver_ioconf_if_iwn, 6569 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6570 #endif 6571 return error; 6572 case MODULE_CMD_AUTOUNLOAD: 6573 #ifdef _MODULE 6574 /* XXX This is not optional! */ 6575 #endif 6576 return error; 6577 default: 6578 return ENOTTY; 6579 } 6580 } 6581 #endif 6582
Indexes created Mon Sep 29 03:10:08 GMT 2025