if_iwn.c revision 1.74.2.8
1 /* $NetBSD: if_iwn.c,v 1.74.2.8 2017/08/28 17:52:05 skrll Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.74.2.8 2017/08/28 17:52:05 skrll Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #ifdef notyetMODULE 39 #include <sys/module.h> 40 #endif 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <sys/bus.h> 49 #include <machine/endian.h> 50 #include <sys/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2, 107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1, 108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2, 109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1, 110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2, 111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1, 112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2, 113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1, 114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2, 115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1, 116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2, 117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1, 118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2, 119 }; 120 121 /* 122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 123 */ 124 static const struct ieee80211_rateset iwn_rateset_11a = 125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 126 127 static const struct ieee80211_rateset iwn_rateset_11b = 128 { 4, { 2, 4, 11, 22 } }; 129 130 static const struct ieee80211_rateset iwn_rateset_11g = 131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 132 133 static int iwn_match(device_t , struct cfdata *, void *); 134 static void iwn_attach(device_t , device_t , void *); 135 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 136 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static int iwn_detach(device_t , int); 139 #if 0 140 static void iwn_power(int, void *); 141 #endif 142 static bool iwn_resume(device_t, const pmf_qual_t *); 143 static int iwn_nic_lock(struct iwn_softc *); 144 static int iwn_eeprom_lock(struct iwn_softc *); 145 static int iwn_init_otprom(struct iwn_softc *); 146 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 147 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 148 void **, bus_size_t, bus_size_t); 149 static void iwn_dma_contig_free(struct iwn_dma_info *); 150 static int iwn_alloc_sched(struct iwn_softc *); 151 static void iwn_free_sched(struct iwn_softc *); 152 static int iwn_alloc_kw(struct iwn_softc *); 153 static void iwn_free_kw(struct iwn_softc *); 154 static int iwn_alloc_ict(struct iwn_softc *); 155 static void iwn_free_ict(struct iwn_softc *); 156 static int iwn_alloc_fwmem(struct iwn_softc *); 157 static void iwn_free_fwmem(struct iwn_softc *); 158 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 159 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 160 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 161 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 162 int); 163 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 164 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 165 static void iwn5000_ict_reset(struct iwn_softc *); 166 static int iwn_read_eeprom(struct iwn_softc *); 167 static void iwn4965_read_eeprom(struct iwn_softc *); 168 169 #ifdef IWN_DEBUG 170 static void iwn4965_print_power_group(struct iwn_softc *, int); 171 #endif 172 static void iwn5000_read_eeprom(struct iwn_softc *); 173 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 174 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 175 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 176 static void iwn_newassoc(struct ieee80211_node *, int); 177 static int iwn_media_change(struct ifnet *); 178 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 179 static void iwn_iter_func(void *, struct ieee80211_node *); 180 static void iwn_calib_timeout(void *); 181 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 #ifndef IEEE80211_NO_HT 186 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 187 struct iwn_rx_data *); 188 #endif 189 static void iwn5000_rx_calib_results(struct iwn_softc *, 190 struct iwn_rx_desc *, struct iwn_rx_data *); 191 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 192 struct iwn_rx_data *); 193 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 194 struct iwn_rx_data *); 195 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 196 struct iwn_rx_data *); 197 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 198 uint8_t); 199 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 200 static void iwn_notif_intr(struct iwn_softc *); 201 static void iwn_wakeup_intr(struct iwn_softc *); 202 static void iwn_fatal_intr(struct iwn_softc *); 203 static int iwn_intr(void *); 204 static void iwn_softintr(void *); 205 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 206 uint16_t); 207 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 208 uint16_t); 209 #ifdef notyet 210 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 211 #endif 212 static int iwn_tx(struct iwn_softc *, struct mbuf *, 213 struct ieee80211_node *, int); 214 static void iwn_start(struct ifnet *); 215 static void iwn_watchdog(struct ifnet *); 216 static int iwn_ioctl(struct ifnet *, u_long, void *); 217 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 218 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 219 int); 220 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 221 int); 222 static int iwn_set_link_quality(struct iwn_softc *, 223 struct ieee80211_node *); 224 static int iwn_add_broadcast_node(struct iwn_softc *, int); 225 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 226 static int iwn_set_critical_temp(struct iwn_softc *); 227 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 228 static void iwn4965_power_calibration(struct iwn_softc *, int); 229 static int iwn4965_set_txpower(struct iwn_softc *, int); 230 static int iwn5000_set_txpower(struct iwn_softc *, int); 231 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 232 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 233 static int iwn_get_noise(const struct iwn_rx_general_stats *); 234 static int iwn4965_get_temperature(struct iwn_softc *); 235 static int iwn5000_get_temperature(struct iwn_softc *); 236 static int iwn_init_sensitivity(struct iwn_softc *); 237 static void iwn_collect_noise(struct iwn_softc *, 238 const struct iwn_rx_general_stats *); 239 static int iwn4965_init_gains(struct iwn_softc *); 240 static int iwn5000_init_gains(struct iwn_softc *); 241 static int iwn4965_set_gains(struct iwn_softc *); 242 static int iwn5000_set_gains(struct iwn_softc *); 243 static void iwn_tune_sensitivity(struct iwn_softc *, 244 const struct iwn_rx_stats *); 245 static int iwn_send_sensitivity(struct iwn_softc *); 246 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 247 static int iwn5000_runtime_calib(struct iwn_softc *); 248 249 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 250 static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 251 static int iwn_config_bt_coex_adv1(struct iwn_softc *); 252 static int iwn_config_bt_coex_adv2(struct iwn_softc *); 253 254 static int iwn_config(struct iwn_softc *); 255 static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, 256 uint8_t); 257 static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 258 static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 259 static int iwn_scan(struct iwn_softc *, uint16_t); 260 static int iwn_auth(struct iwn_softc *); 261 static int iwn_run(struct iwn_softc *); 262 #ifdef IWN_HWCRYPTO 263 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 264 struct ieee80211_key *); 265 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 266 struct ieee80211_key *); 267 #endif 268 static int iwn_wme_update(struct ieee80211com *); 269 #ifndef IEEE80211_NO_HT 270 static int iwn_ampdu_rx_start(struct ieee80211com *, 271 struct ieee80211_node *, uint8_t); 272 static void iwn_ampdu_rx_stop(struct ieee80211com *, 273 struct ieee80211_node *, uint8_t); 274 static int iwn_ampdu_tx_start(struct ieee80211com *, 275 struct ieee80211_node *, uint8_t); 276 static void iwn_ampdu_tx_stop(struct ieee80211com *, 277 struct ieee80211_node *, uint8_t); 278 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 279 struct ieee80211_node *, uint8_t, uint16_t); 280 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 281 uint8_t, uint16_t); 282 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 283 struct ieee80211_node *, uint8_t, uint16_t); 284 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 285 uint8_t, uint16_t); 286 #endif 287 static int iwn5000_query_calibration(struct iwn_softc *); 288 static int iwn5000_send_calibration(struct iwn_softc *); 289 static int iwn5000_send_wimax_coex(struct iwn_softc *); 290 static int iwn6000_temp_offset_calib(struct iwn_softc *); 291 static int iwn2000_temp_offset_calib(struct iwn_softc *); 292 static int iwn4965_post_alive(struct iwn_softc *); 293 static int iwn5000_post_alive(struct iwn_softc *); 294 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 295 int); 296 static int iwn4965_load_firmware(struct iwn_softc *); 297 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 298 const uint8_t *, int); 299 static int iwn5000_load_firmware(struct iwn_softc *); 300 static int iwn_read_firmware_leg(struct iwn_softc *, 301 struct iwn_fw_info *); 302 static int iwn_read_firmware_tlv(struct iwn_softc *, 303 struct iwn_fw_info *, uint16_t); 304 static int iwn_read_firmware(struct iwn_softc *); 305 static int iwn_clock_wait(struct iwn_softc *); 306 static int iwn_apm_init(struct iwn_softc *); 307 static void iwn_apm_stop_master(struct iwn_softc *); 308 static void iwn_apm_stop(struct iwn_softc *); 309 static int iwn4965_nic_config(struct iwn_softc *); 310 static int iwn5000_nic_config(struct iwn_softc *); 311 static int iwn_hw_prepare(struct iwn_softc *); 312 static int iwn_hw_init(struct iwn_softc *); 313 static void iwn_hw_stop(struct iwn_softc *); 314 static int iwn_init(struct ifnet *); 315 static void iwn_stop(struct ifnet *, int); 316 317 /* XXX MCLGETI alternative */ 318 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 319 struct ifnet *, u_int); 320 #ifdef IWN_USE_RBUF 321 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 322 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 323 static int iwn_alloc_rpool(struct iwn_softc *); 324 static void iwn_free_rpool(struct iwn_softc *); 325 #endif 326 327 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *, 328 struct iwn_rx_stat *); 329 330 #ifdef IWN_DEBUG 331 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 332 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 333 int iwn_debug = 0; 334 #else 335 #define DPRINTF(x) 336 #define DPRINTFN(n, x) 337 #endif 338 339 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 340 iwn_detach, NULL); 341 342 static int 343 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 344 { 345 struct pci_attach_args *pa = aux; 346 size_t i; 347 348 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 349 return 0; 350 351 for (i = 0; i < __arraycount(iwn_devices); i++) 352 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 353 return 1; 354 355 return 0; 356 } 357 358 static void 359 iwn_attach(device_t parent __unused, device_t self, void *aux) 360 { 361 struct iwn_softc *sc = device_private(self); 362 struct ieee80211com *ic = &sc->sc_ic; 363 struct ifnet *ifp = &sc->sc_ec.ec_if; 364 struct pci_attach_args *pa = aux; 365 const char *intrstr; 366 pcireg_t memtype, reg; 367 int i, error; 368 char intrbuf[PCI_INTRSTR_LEN]; 369 370 sc->sc_dev = self; 371 sc->sc_pct = pa->pa_pc; 372 sc->sc_pcitag = pa->pa_tag; 373 sc->sc_dmat = pa->pa_dmat; 374 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 375 376 callout_init(&sc->calib_to, 0); 377 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 378 379 pci_aprint_devinfo(pa, NULL); 380 381 /* 382 * Get the offset of the PCI Express Capability Structure in PCI 383 * Configuration Space. 384 */ 385 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 386 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 387 if (error == 0) { 388 aprint_error_dev(self, 389 "PCIe capability structure not found!\n"); 390 return; 391 } 392 393 /* Clear device-specific "PCI retry timeout" register (41h). */ 394 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 395 if (reg & 0xff00) 396 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 397 398 /* Enable bus-mastering. */ 399 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 400 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 401 reg |= PCI_COMMAND_MASTER_ENABLE; 402 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 403 404 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 405 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 406 &sc->sc_sh, NULL, &sc->sc_sz); 407 if (error != 0) { 408 aprint_error_dev(self, "can't map mem space\n"); 409 return; 410 } 411 412 sc->sc_soft_ih = softint_establish(SOFTINT_NET, iwn_softintr, sc); 413 if (sc->sc_soft_ih == NULL) { 414 aprint_error_dev(self, "can't establish soft interrupt\n"); 415 goto unmap; 416 } 417 418 /* Install interrupt handler. */ 419 error = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0); 420 if (error) { 421 aprint_error_dev(self, "can't allocate interrupt\n"); 422 goto failsi; 423 } 424 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 425 if (pci_intr_type(sc->sc_pct, sc->sc_pihp[0]) == PCI_INTR_TYPE_INTX) 426 CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE); 427 else 428 SET(reg, PCI_COMMAND_INTERRUPT_DISABLE); 429 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 430 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf, 431 sizeof(intrbuf)); 432 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, sc->sc_pihp[0], 433 IPL_NET, iwn_intr, sc, device_xname(self)); 434 if (sc->sc_ih == NULL) { 435 aprint_error_dev(self, "can't establish interrupt"); 436 if (intrstr != NULL) 437 aprint_error(" at %s", intrstr); 438 aprint_error("\n"); 439 goto failia; 440 } 441 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 442 443 /* Read hardware revision and attach. */ 444 sc->hw_type = 445 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK) 446 >> IWN_HW_REV_TYPE_SHIFT; 447 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 448 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 449 else 450 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 451 if (error != 0) { 452 aprint_error_dev(self, "could not attach device\n"); 453 goto failih; 454 } 455 456 if ((error = iwn_hw_prepare(sc)) != 0) { 457 aprint_error_dev(self, "hardware not ready\n"); 458 goto failih; 459 } 460 461 /* Read MAC address, channels, etc from EEPROM. */ 462 if ((error = iwn_read_eeprom(sc)) != 0) { 463 aprint_error_dev(self, "could not read EEPROM\n"); 464 goto failih; 465 } 466 467 /* Allocate DMA memory for firmware transfers. */ 468 if ((error = iwn_alloc_fwmem(sc)) != 0) { 469 aprint_error_dev(self, 470 "could not allocate memory for firmware\n"); 471 goto failih; 472 } 473 474 /* Allocate "Keep Warm" page. */ 475 if ((error = iwn_alloc_kw(sc)) != 0) { 476 aprint_error_dev(self, "could not allocate keep warm page\n"); 477 goto fail1; 478 } 479 480 /* Allocate ICT table for 5000 Series. */ 481 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 482 (error = iwn_alloc_ict(sc)) != 0) { 483 aprint_error_dev(self, "could not allocate ICT table\n"); 484 goto fail2; 485 } 486 487 /* Allocate TX scheduler "rings". */ 488 if ((error = iwn_alloc_sched(sc)) != 0) { 489 aprint_error_dev(self, 490 "could not allocate TX scheduler rings\n"); 491 goto fail3; 492 } 493 494 #ifdef IWN_USE_RBUF 495 /* Allocate RX buffers. */ 496 if ((error = iwn_alloc_rpool(sc)) != 0) { 497 aprint_error_dev(self, "could not allocate RX buffers\n"); 498 goto fail3; 499 } 500 #endif 501 502 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 503 for (i = 0; i < sc->ntxqs; i++) { 504 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 505 aprint_error_dev(self, 506 "could not allocate TX ring %d\n", i); 507 goto fail4; 508 } 509 } 510 511 /* Allocate RX ring. */ 512 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 513 aprint_error_dev(self, "could not allocate RX ring\n"); 514 goto fail4; 515 } 516 517 /* Clear pending interrupts. */ 518 IWN_WRITE(sc, IWN_INT, 0xffffffff); 519 520 /* Count the number of available chains. */ 521 sc->ntxchains = 522 ((sc->txchainmask >> 2) & 1) + 523 ((sc->txchainmask >> 1) & 1) + 524 ((sc->txchainmask >> 0) & 1); 525 sc->nrxchains = 526 ((sc->rxchainmask >> 2) & 1) + 527 ((sc->rxchainmask >> 1) & 1) + 528 ((sc->rxchainmask >> 0) & 1); 529 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 530 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 531 ether_sprintf(ic->ic_myaddr)); 532 533 ic->ic_ifp = ifp; 534 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 535 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 536 ic->ic_state = IEEE80211_S_INIT; 537 538 /* Set device capabilities. */ 539 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 540 * and IEEE80211_C_PMGT too. */ 541 ic->ic_caps = 542 IEEE80211_C_IBSS | /* IBSS mode support */ 543 IEEE80211_C_WPA | /* 802.11i */ 544 IEEE80211_C_MONITOR | /* monitor mode supported */ 545 IEEE80211_C_TXPMGT | /* tx power management */ 546 IEEE80211_C_SHSLOT | /* short slot time supported */ 547 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 548 IEEE80211_C_WME; /* 802.11e */ 549 550 #ifndef IEEE80211_NO_HT 551 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 552 /* Set HT capabilities. */ 553 ic->ic_htcaps = 554 #if IWN_RBUF_SIZE == 8192 555 IEEE80211_HTCAP_AMSDU7935 | 556 #endif 557 IEEE80211_HTCAP_CBW20_40 | 558 IEEE80211_HTCAP_SGI20 | 559 IEEE80211_HTCAP_SGI40; 560 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 561 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 562 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 563 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 564 else 565 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 566 } 567 #endif /* !IEEE80211_NO_HT */ 568 569 /* Set supported legacy rates. */ 570 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 571 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 572 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 573 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 574 } 575 #ifndef IEEE80211_NO_HT 576 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 577 /* Set supported HT rates. */ 578 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 579 if (sc->nrxchains > 1) 580 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 581 if (sc->nrxchains > 2) 582 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 583 } 584 #endif 585 586 /* IBSS channel undefined for now. */ 587 ic->ic_ibss_chan = &ic->ic_channels[0]; 588 589 ifp->if_softc = sc; 590 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 591 ifp->if_init = iwn_init; 592 ifp->if_ioctl = iwn_ioctl; 593 ifp->if_start = iwn_start; 594 ifp->if_stop = iwn_stop; 595 ifp->if_watchdog = iwn_watchdog; 596 IFQ_SET_READY(&ifp->if_snd); 597 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 598 599 if_initialize(ifp); 600 ieee80211_ifattach(ic); 601 /* Use common softint-based if_input */ 602 ifp->if_percpuq = if_percpuq_create(ifp); 603 if_register(ifp); 604 605 ic->ic_node_alloc = iwn_node_alloc; 606 ic->ic_newassoc = iwn_newassoc; 607 #ifdef IWN_HWCRYPTO 608 ic->ic_crypto.cs_key_set = iwn_set_key; 609 ic->ic_crypto.cs_key_delete = iwn_delete_key; 610 #endif 611 ic->ic_wme.wme_update = iwn_wme_update; 612 #ifndef IEEE80211_NO_HT 613 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 614 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 615 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 616 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 617 #endif 618 619 /* Override 802.11 state transition machine. */ 620 sc->sc_newstate = ic->ic_newstate; 621 ic->ic_newstate = iwn_newstate; 622 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 623 624 sc->amrr.amrr_min_success_threshold = 1; 625 sc->amrr.amrr_max_success_threshold = 15; 626 627 iwn_radiotap_attach(sc); 628 629 /* 630 * XXX for NetBSD, OpenBSD timeout_set replaced by 631 * callout_init and callout_setfunc, above. 632 */ 633 634 if (pmf_device_register(self, NULL, iwn_resume)) 635 pmf_class_network_register(self, ifp); 636 else 637 aprint_error_dev(self, "couldn't establish power handler\n"); 638 639 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 640 ieee80211_announce(ic); 641 642 sc->sc_flags |= IWN_FLAG_ATTACHED; 643 return; 644 645 /* Free allocated memory if something failed during attachment. */ 646 fail4: while (--i >= 0) 647 iwn_free_tx_ring(sc, &sc->txq[i]); 648 #ifdef IWN_USE_RBUF 649 iwn_free_rpool(sc); 650 #endif 651 iwn_free_sched(sc); 652 fail3: if (sc->ict != NULL) 653 iwn_free_ict(sc); 654 fail2: iwn_free_kw(sc); 655 fail1: iwn_free_fwmem(sc); 656 failih: pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 657 sc->sc_ih = NULL; 658 failia: pci_intr_release(sc->sc_pct, sc->sc_pihp, 1); 659 sc->sc_pihp = NULL; 660 failsi: softint_disestablish(sc->sc_soft_ih); 661 sc->sc_soft_ih = NULL; 662 unmap: bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 663 } 664 665 int 666 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 667 { 668 struct iwn_ops *ops = &sc->ops; 669 670 ops->load_firmware = iwn4965_load_firmware; 671 ops->read_eeprom = iwn4965_read_eeprom; 672 ops->post_alive = iwn4965_post_alive; 673 ops->nic_config = iwn4965_nic_config; 674 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 675 ops->update_sched = iwn4965_update_sched; 676 ops->get_temperature = iwn4965_get_temperature; 677 ops->get_rssi = iwn4965_get_rssi; 678 ops->set_txpower = iwn4965_set_txpower; 679 ops->init_gains = iwn4965_init_gains; 680 ops->set_gains = iwn4965_set_gains; 681 ops->add_node = iwn4965_add_node; 682 ops->tx_done = iwn4965_tx_done; 683 #ifndef IEEE80211_NO_HT 684 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 685 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 686 #endif 687 sc->ntxqs = IWN4965_NTXQUEUES; 688 sc->ndmachnls = IWN4965_NDMACHNLS; 689 sc->broadcast_id = IWN4965_ID_BROADCAST; 690 sc->rxonsz = IWN4965_RXONSZ; 691 sc->schedsz = IWN4965_SCHEDSZ; 692 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 693 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 694 sc->fwsz = IWN4965_FWSZ; 695 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 696 sc->limits = &iwn4965_sensitivity_limits; 697 sc->fwname = "iwlwifi-4965-2.ucode"; 698 /* Override chains masks, ROM is known to be broken. */ 699 sc->txchainmask = IWN_ANT_AB; 700 sc->rxchainmask = IWN_ANT_ABC; 701 702 return 0; 703 } 704 705 int 706 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 707 { 708 struct iwn_ops *ops = &sc->ops; 709 710 ops->load_firmware = iwn5000_load_firmware; 711 ops->read_eeprom = iwn5000_read_eeprom; 712 ops->post_alive = iwn5000_post_alive; 713 ops->nic_config = iwn5000_nic_config; 714 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 715 ops->update_sched = iwn5000_update_sched; 716 ops->get_temperature = iwn5000_get_temperature; 717 ops->get_rssi = iwn5000_get_rssi; 718 ops->set_txpower = iwn5000_set_txpower; 719 ops->init_gains = iwn5000_init_gains; 720 ops->set_gains = iwn5000_set_gains; 721 ops->add_node = iwn5000_add_node; 722 ops->tx_done = iwn5000_tx_done; 723 #ifndef IEEE80211_NO_HT 724 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 725 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 726 #endif 727 sc->ntxqs = IWN5000_NTXQUEUES; 728 sc->ndmachnls = IWN5000_NDMACHNLS; 729 sc->broadcast_id = IWN5000_ID_BROADCAST; 730 sc->rxonsz = IWN5000_RXONSZ; 731 sc->schedsz = IWN5000_SCHEDSZ; 732 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 733 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 734 sc->fwsz = IWN5000_FWSZ; 735 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 736 737 switch (sc->hw_type) { 738 case IWN_HW_REV_TYPE_5100: 739 sc->limits = &iwn5000_sensitivity_limits; 740 sc->fwname = "iwlwifi-5000-2.ucode"; 741 /* Override chains masks, ROM is known to be broken. */ 742 sc->txchainmask = IWN_ANT_B; 743 sc->rxchainmask = IWN_ANT_AB; 744 break; 745 case IWN_HW_REV_TYPE_5150: 746 sc->limits = &iwn5150_sensitivity_limits; 747 sc->fwname = "iwlwifi-5150-2.ucode"; 748 break; 749 case IWN_HW_REV_TYPE_5300: 750 case IWN_HW_REV_TYPE_5350: 751 sc->limits = &iwn5000_sensitivity_limits; 752 sc->fwname = "iwlwifi-5000-2.ucode"; 753 break; 754 case IWN_HW_REV_TYPE_1000: 755 sc->limits = &iwn1000_sensitivity_limits; 756 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 || 757 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2) 758 sc->fwname = "iwlwifi-100-5.ucode"; 759 else 760 sc->fwname = "iwlwifi-1000-3.ucode"; 761 break; 762 case IWN_HW_REV_TYPE_6000: 763 sc->limits = &iwn6000_sensitivity_limits; 764 sc->fwname = "iwlwifi-6000-4.ucode"; 765 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 766 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 767 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 768 /* Override chains masks, ROM is known to be broken. */ 769 sc->txchainmask = IWN_ANT_BC; 770 sc->rxchainmask = IWN_ANT_BC; 771 } 772 break; 773 case IWN_HW_REV_TYPE_6050: 774 sc->limits = &iwn6000_sensitivity_limits; 775 sc->fwname = "iwlwifi-6050-5.ucode"; 776 break; 777 case IWN_HW_REV_TYPE_6005: 778 sc->limits = &iwn6000_sensitivity_limits; 779 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 780 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 781 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 782 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 783 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 784 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 || 785 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) { 786 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 787 ops->config_bt_coex = iwn_config_bt_coex_adv1; 788 } 789 else 790 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 791 break; 792 case IWN_HW_REV_TYPE_2030: 793 sc->limits = &iwn2030_sensitivity_limits; 794 sc->fwname = "iwlwifi-2030-6.ucode"; 795 ops->config_bt_coex = iwn_config_bt_coex_adv2; 796 break; 797 case IWN_HW_REV_TYPE_2000: 798 sc->limits = &iwn2000_sensitivity_limits; 799 sc->fwname = "iwlwifi-2000-6.ucode"; 800 break; 801 case IWN_HW_REV_TYPE_135: 802 sc->limits = &iwn2000_sensitivity_limits; 803 sc->fwname = "iwlwifi-135-6.ucode"; 804 ops->config_bt_coex = iwn_config_bt_coex_adv2; 805 break; 806 case IWN_HW_REV_TYPE_105: 807 sc->limits = &iwn2000_sensitivity_limits; 808 sc->fwname = "iwlwifi-105-6.ucode"; 809 break; 810 default: 811 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 812 return ENOTSUP; 813 } 814 return 0; 815 } 816 817 /* 818 * Attach the interface to 802.11 radiotap. 819 */ 820 static void 821 iwn_radiotap_attach(struct iwn_softc *sc) 822 { 823 struct ifnet *ifp = sc->sc_ic.ic_ifp; 824 825 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 826 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 827 &sc->sc_drvbpf); 828 829 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 830 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 831 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 832 833 sc->sc_txtap_len = sizeof sc->sc_txtapu; 834 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 835 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 836 } 837 838 static int 839 iwn_detach(device_t self, int flags __unused) 840 { 841 struct iwn_softc *sc = device_private(self); 842 struct ifnet *ifp = sc->sc_ic.ic_ifp; 843 int qid; 844 845 if (!(sc->sc_flags & IWN_FLAG_ATTACHED)) 846 return 0; 847 848 callout_stop(&sc->calib_to); 849 850 /* Uninstall interrupt handler. */ 851 if (sc->sc_ih != NULL) 852 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 853 if (sc->sc_pihp != NULL) 854 pci_intr_release(sc->sc_pct, sc->sc_pihp, 1); 855 if (sc->sc_soft_ih != NULL) 856 softint_disestablish(sc->sc_soft_ih); 857 858 /* Free DMA resources. */ 859 iwn_free_rx_ring(sc, &sc->rxq); 860 for (qid = 0; qid < sc->ntxqs; qid++) 861 iwn_free_tx_ring(sc, &sc->txq[qid]); 862 #ifdef IWN_USE_RBUF 863 iwn_free_rpool(sc); 864 #endif 865 iwn_free_sched(sc); 866 iwn_free_kw(sc); 867 if (sc->ict != NULL) 868 iwn_free_ict(sc); 869 iwn_free_fwmem(sc); 870 871 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 872 873 ieee80211_ifdetach(&sc->sc_ic); 874 if_detach(ifp); 875 876 return 0; 877 } 878 879 #if 0 880 /* 881 * XXX Investigate if clearing the PCI retry timeout could eliminate 882 * the repeated scan calls. Also the calls to if_init and if_start 883 * are similar to the effect of adding the call to ifioctl_common . 884 */ 885 static void 886 iwn_power(int why, void *arg) 887 { 888 struct iwn_softc *sc = arg; 889 struct ifnet *ifp; 890 pcireg_t reg; 891 int s; 892 893 if (why != PWR_RESUME) 894 return; 895 896 /* Clear device-specific "PCI retry timeout" register (41h). */ 897 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 898 if (reg & 0xff00) 899 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 900 901 s = splnet(); 902 ifp = &sc->sc_ic.ic_if; 903 if (ifp->if_flags & IFF_UP) { 904 ifp->if_init(ifp); 905 if (ifp->if_flags & IFF_RUNNING) 906 ifp->if_start(ifp); 907 } 908 splx(s); 909 } 910 #endif 911 912 static bool 913 iwn_resume(device_t dv, const pmf_qual_t *qual) 914 { 915 return true; 916 } 917 918 static int 919 iwn_nic_lock(struct iwn_softc *sc) 920 { 921 int ntries; 922 923 /* Request exclusive access to NIC. */ 924 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 925 926 /* Spin until we actually get the lock. */ 927 for (ntries = 0; ntries < 1000; ntries++) { 928 if ((IWN_READ(sc, IWN_GP_CNTRL) & 929 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 930 IWN_GP_CNTRL_MAC_ACCESS_ENA) 931 return 0; 932 DELAY(10); 933 } 934 return ETIMEDOUT; 935 } 936 937 static __inline void 938 iwn_nic_unlock(struct iwn_softc *sc) 939 { 940 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 941 } 942 943 static __inline uint32_t 944 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 945 { 946 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 947 IWN_BARRIER_READ_WRITE(sc); 948 return IWN_READ(sc, IWN_PRPH_RDATA); 949 } 950 951 static __inline void 952 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 953 { 954 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 955 IWN_BARRIER_WRITE(sc); 956 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 957 } 958 959 static __inline void 960 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 961 { 962 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 963 } 964 965 static __inline void 966 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 967 { 968 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 969 } 970 971 static __inline void 972 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 973 const uint32_t *data, int count) 974 { 975 for (; count > 0; count--, data++, addr += 4) 976 iwn_prph_write(sc, addr, *data); 977 } 978 979 static __inline uint32_t 980 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 981 { 982 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 983 IWN_BARRIER_READ_WRITE(sc); 984 return IWN_READ(sc, IWN_MEM_RDATA); 985 } 986 987 static __inline void 988 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 989 { 990 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 991 IWN_BARRIER_WRITE(sc); 992 IWN_WRITE(sc, IWN_MEM_WDATA, data); 993 } 994 995 #ifndef IEEE80211_NO_HT 996 static __inline void 997 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 998 { 999 uint32_t tmp; 1000 1001 tmp = iwn_mem_read(sc, addr & ~3); 1002 if (addr & 3) 1003 tmp = (tmp & 0x0000ffff) | data << 16; 1004 else 1005 tmp = (tmp & 0xffff0000) | data; 1006 iwn_mem_write(sc, addr & ~3, tmp); 1007 } 1008 #endif 1009 1010 static __inline void 1011 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1012 int count) 1013 { 1014 for (; count > 0; count--, addr += 4) 1015 *data++ = iwn_mem_read(sc, addr); 1016 } 1017 1018 static __inline void 1019 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1020 int count) 1021 { 1022 for (; count > 0; count--, addr += 4) 1023 iwn_mem_write(sc, addr, val); 1024 } 1025 1026 static int 1027 iwn_eeprom_lock(struct iwn_softc *sc) 1028 { 1029 int i, ntries; 1030 1031 for (i = 0; i < 100; i++) { 1032 /* Request exclusive access to EEPROM. */ 1033 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1034 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1035 1036 /* Spin until we actually get the lock. */ 1037 for (ntries = 0; ntries < 100; ntries++) { 1038 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1039 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1040 return 0; 1041 DELAY(10); 1042 } 1043 } 1044 return ETIMEDOUT; 1045 } 1046 1047 static __inline void 1048 iwn_eeprom_unlock(struct iwn_softc *sc) 1049 { 1050 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1051 } 1052 1053 /* 1054 * Initialize access by host to One Time Programmable ROM. 1055 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1056 */ 1057 static int 1058 iwn_init_otprom(struct iwn_softc *sc) 1059 { 1060 uint16_t prev = 0, base, next; 1061 int count, error; 1062 1063 /* Wait for clock stabilization before accessing prph. */ 1064 if ((error = iwn_clock_wait(sc)) != 0) 1065 return error; 1066 1067 if ((error = iwn_nic_lock(sc)) != 0) 1068 return error; 1069 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1070 DELAY(5); 1071 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1072 iwn_nic_unlock(sc); 1073 1074 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1075 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1076 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1077 IWN_RESET_LINK_PWR_MGMT_DIS); 1078 } 1079 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1080 /* Clear ECC status. */ 1081 IWN_SETBITS(sc, IWN_OTP_GP, 1082 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1083 1084 /* 1085 * Find the block before last block (contains the EEPROM image) 1086 * for HW without OTP shadow RAM. 1087 */ 1088 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1089 /* Switch to absolute addressing mode. */ 1090 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1091 base = 0; 1092 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1093 error = iwn_read_prom_data(sc, base, &next, 2); 1094 if (error != 0) 1095 return error; 1096 if (next == 0) /* End of linked-list. */ 1097 break; 1098 prev = base; 1099 base = le16toh(next); 1100 } 1101 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1102 return EIO; 1103 /* Skip "next" word. */ 1104 sc->prom_base = prev + 1; 1105 } 1106 return 0; 1107 } 1108 1109 static int 1110 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1111 { 1112 uint8_t *out = data; 1113 uint32_t val, tmp; 1114 int ntries; 1115 1116 addr += sc->prom_base; 1117 for (; count > 0; count -= 2, addr++) { 1118 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1119 for (ntries = 0; ntries < 10; ntries++) { 1120 val = IWN_READ(sc, IWN_EEPROM); 1121 if (val & IWN_EEPROM_READ_VALID) 1122 break; 1123 DELAY(5); 1124 } 1125 if (ntries == 10) { 1126 aprint_error_dev(sc->sc_dev, 1127 "timeout reading ROM at 0x%x\n", addr); 1128 return ETIMEDOUT; 1129 } 1130 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1131 /* OTPROM, check for ECC errors. */ 1132 tmp = IWN_READ(sc, IWN_OTP_GP); 1133 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1134 aprint_error_dev(sc->sc_dev, 1135 "OTPROM ECC error at 0x%x\n", addr); 1136 return EIO; 1137 } 1138 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1139 /* Correctable ECC error, clear bit. */ 1140 IWN_SETBITS(sc, IWN_OTP_GP, 1141 IWN_OTP_GP_ECC_CORR_STTS); 1142 } 1143 } 1144 *out++ = val >> 16; 1145 if (count > 1) 1146 *out++ = val >> 24; 1147 } 1148 return 0; 1149 } 1150 1151 static int 1152 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1153 bus_size_t size, bus_size_t alignment) 1154 { 1155 int nsegs, error; 1156 1157 dma->tag = tag; 1158 dma->size = size; 1159 1160 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1161 &dma->map); 1162 if (error != 0) 1163 goto fail; 1164 1165 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1166 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1167 if (error != 0) 1168 goto fail; 1169 1170 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1171 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1172 if (error != 0) 1173 goto fail; 1174 1175 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1176 BUS_DMA_NOWAIT); 1177 if (error != 0) 1178 goto fail; 1179 1180 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1181 memset(dma->vaddr, 0, size); 1182 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1183 1184 dma->paddr = dma->map->dm_segs[0].ds_addr; 1185 if (kvap != NULL) 1186 *kvap = dma->vaddr; 1187 1188 return 0; 1189 1190 fail: iwn_dma_contig_free(dma); 1191 return error; 1192 } 1193 1194 static void 1195 iwn_dma_contig_free(struct iwn_dma_info *dma) 1196 { 1197 if (dma->map != NULL) { 1198 if (dma->vaddr != NULL) { 1199 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1200 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1201 bus_dmamap_unload(dma->tag, dma->map); 1202 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1203 bus_dmamem_free(dma->tag, &dma->seg, 1); 1204 dma->vaddr = NULL; 1205 } 1206 bus_dmamap_destroy(dma->tag, dma->map); 1207 dma->map = NULL; 1208 } 1209 } 1210 1211 static int 1212 iwn_alloc_sched(struct iwn_softc *sc) 1213 { 1214 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1215 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1216 (void **)&sc->sched, sc->schedsz, 1024); 1217 } 1218 1219 static void 1220 iwn_free_sched(struct iwn_softc *sc) 1221 { 1222 iwn_dma_contig_free(&sc->sched_dma); 1223 } 1224 1225 static int 1226 iwn_alloc_kw(struct iwn_softc *sc) 1227 { 1228 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1229 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1230 4096); 1231 } 1232 1233 static void 1234 iwn_free_kw(struct iwn_softc *sc) 1235 { 1236 iwn_dma_contig_free(&sc->kw_dma); 1237 } 1238 1239 static int 1240 iwn_alloc_ict(struct iwn_softc *sc) 1241 { 1242 /* ICT table must be aligned on a 4KB boundary. */ 1243 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1244 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1245 } 1246 1247 static void 1248 iwn_free_ict(struct iwn_softc *sc) 1249 { 1250 iwn_dma_contig_free(&sc->ict_dma); 1251 } 1252 1253 static int 1254 iwn_alloc_fwmem(struct iwn_softc *sc) 1255 { 1256 /* Must be aligned on a 16-byte boundary. */ 1257 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1258 sc->fwsz, 16); 1259 } 1260 1261 static void 1262 iwn_free_fwmem(struct iwn_softc *sc) 1263 { 1264 iwn_dma_contig_free(&sc->fw_dma); 1265 } 1266 1267 static int 1268 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1269 { 1270 bus_size_t size; 1271 int i, error; 1272 1273 ring->cur = 0; 1274 1275 /* Allocate RX descriptors (256-byte aligned). */ 1276 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1277 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1278 (void **)&ring->desc, size, 256); 1279 if (error != 0) { 1280 aprint_error_dev(sc->sc_dev, 1281 "could not allocate RX ring DMA memory\n"); 1282 goto fail; 1283 } 1284 1285 /* Allocate RX status area (16-byte aligned). */ 1286 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1287 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1288 if (error != 0) { 1289 aprint_error_dev(sc->sc_dev, 1290 "could not allocate RX status DMA memory\n"); 1291 goto fail; 1292 } 1293 1294 /* 1295 * Allocate and map RX buffers. 1296 */ 1297 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1298 struct iwn_rx_data *data = &ring->data[i]; 1299 1300 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1301 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1302 &data->map); 1303 if (error != 0) { 1304 aprint_error_dev(sc->sc_dev, 1305 "could not create RX buf DMA map\n"); 1306 goto fail; 1307 } 1308 1309 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1310 if (data->m == NULL) { 1311 aprint_error_dev(sc->sc_dev, 1312 "could not allocate RX mbuf\n"); 1313 error = ENOBUFS; 1314 goto fail; 1315 } 1316 1317 error = bus_dmamap_load(sc->sc_dmat, data->map, 1318 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1319 BUS_DMA_NOWAIT | BUS_DMA_READ); 1320 if (error != 0) { 1321 aprint_error_dev(sc->sc_dev, 1322 "can't not map mbuf (error %d)\n", error); 1323 goto fail; 1324 } 1325 1326 /* Set physical address of RX buffer (256-byte aligned). */ 1327 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1328 } 1329 1330 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1331 BUS_DMASYNC_PREWRITE); 1332 1333 return 0; 1334 1335 fail: iwn_free_rx_ring(sc, ring); 1336 return error; 1337 } 1338 1339 static void 1340 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1341 { 1342 int ntries; 1343 1344 if (iwn_nic_lock(sc) == 0) { 1345 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1346 for (ntries = 0; ntries < 1000; ntries++) { 1347 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1348 IWN_FH_RX_STATUS_IDLE) 1349 break; 1350 DELAY(10); 1351 } 1352 iwn_nic_unlock(sc); 1353 } 1354 ring->cur = 0; 1355 sc->last_rx_valid = 0; 1356 } 1357 1358 static void 1359 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1360 { 1361 int i; 1362 1363 iwn_dma_contig_free(&ring->desc_dma); 1364 iwn_dma_contig_free(&ring->stat_dma); 1365 1366 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1367 struct iwn_rx_data *data = &ring->data[i]; 1368 1369 if (data->m != NULL) { 1370 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1371 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1372 bus_dmamap_unload(sc->sc_dmat, data->map); 1373 m_freem(data->m); 1374 } 1375 if (data->map != NULL) 1376 bus_dmamap_destroy(sc->sc_dmat, data->map); 1377 } 1378 } 1379 1380 static int 1381 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1382 { 1383 bus_addr_t paddr; 1384 bus_size_t size; 1385 int i, error; 1386 1387 ring->qid = qid; 1388 ring->queued = 0; 1389 ring->cur = 0; 1390 1391 /* Allocate TX descriptors (256-byte aligned). */ 1392 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1393 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1394 (void **)&ring->desc, size, 256); 1395 if (error != 0) { 1396 aprint_error_dev(sc->sc_dev, 1397 "could not allocate TX ring DMA memory\n"); 1398 goto fail; 1399 } 1400 /* 1401 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1402 * to allocate commands space for other rings. 1403 * XXX Do we really need to allocate descriptors for other rings? 1404 */ 1405 if (qid > 4) 1406 return 0; 1407 1408 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1409 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1410 (void **)&ring->cmd, size, 4); 1411 if (error != 0) { 1412 aprint_error_dev(sc->sc_dev, 1413 "could not allocate TX cmd DMA memory\n"); 1414 goto fail; 1415 } 1416 1417 paddr = ring->cmd_dma.paddr; 1418 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1419 struct iwn_tx_data *data = &ring->data[i]; 1420 1421 data->cmd_paddr = paddr; 1422 data->scratch_paddr = paddr + 12; 1423 paddr += sizeof (struct iwn_tx_cmd); 1424 1425 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1426 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1427 &data->map); 1428 if (error != 0) { 1429 aprint_error_dev(sc->sc_dev, 1430 "could not create TX buf DMA map\n"); 1431 goto fail; 1432 } 1433 } 1434 return 0; 1435 1436 fail: iwn_free_tx_ring(sc, ring); 1437 return error; 1438 } 1439 1440 static void 1441 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1442 { 1443 int i; 1444 1445 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1446 struct iwn_tx_data *data = &ring->data[i]; 1447 1448 if (data->m != NULL) { 1449 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1450 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1451 bus_dmamap_unload(sc->sc_dmat, data->map); 1452 m_freem(data->m); 1453 data->m = NULL; 1454 } 1455 } 1456 /* Clear TX descriptors. */ 1457 memset(ring->desc, 0, ring->desc_dma.size); 1458 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1459 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1460 sc->qfullmsk &= ~(1 << ring->qid); 1461 ring->queued = 0; 1462 ring->cur = 0; 1463 } 1464 1465 static void 1466 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1467 { 1468 int i; 1469 1470 iwn_dma_contig_free(&ring->desc_dma); 1471 iwn_dma_contig_free(&ring->cmd_dma); 1472 1473 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1474 struct iwn_tx_data *data = &ring->data[i]; 1475 1476 if (data->m != NULL) { 1477 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1478 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1479 bus_dmamap_unload(sc->sc_dmat, data->map); 1480 m_freem(data->m); 1481 } 1482 if (data->map != NULL) 1483 bus_dmamap_destroy(sc->sc_dmat, data->map); 1484 } 1485 } 1486 1487 static void 1488 iwn5000_ict_reset(struct iwn_softc *sc) 1489 { 1490 /* Disable interrupts. */ 1491 IWN_WRITE(sc, IWN_INT_MASK, 0); 1492 1493 /* Reset ICT table. */ 1494 memset(sc->ict, 0, IWN_ICT_SIZE); 1495 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, IWN_ICT_SIZE, 1496 BUS_DMASYNC_PREWRITE); 1497 sc->ict_cur = 0; 1498 1499 /* Set physical address of ICT table (4KB aligned). */ 1500 DPRINTF(("enabling ICT\n")); 1501 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1502 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1503 1504 /* Enable periodic RX interrupt. */ 1505 sc->int_mask |= IWN_INT_RX_PERIODIC; 1506 /* Switch to ICT interrupt mode in driver. */ 1507 sc->sc_flags |= IWN_FLAG_USE_ICT; 1508 1509 /* Re-enable interrupts. */ 1510 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1511 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1512 } 1513 1514 static int 1515 iwn_read_eeprom(struct iwn_softc *sc) 1516 { 1517 struct iwn_ops *ops = &sc->ops; 1518 struct ieee80211com *ic = &sc->sc_ic; 1519 uint16_t val; 1520 int error; 1521 1522 /* Check whether adapter has an EEPROM or an OTPROM. */ 1523 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1524 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1525 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1526 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1527 "OTPROM" : "EEPROM")); 1528 1529 /* Adapter has to be powered on for EEPROM access to work. */ 1530 if ((error = iwn_apm_init(sc)) != 0) { 1531 aprint_error_dev(sc->sc_dev, 1532 "could not power ON adapter\n"); 1533 return error; 1534 } 1535 1536 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1537 aprint_error_dev(sc->sc_dev, 1538 "bad ROM signature\n"); 1539 return EIO; 1540 } 1541 if ((error = iwn_eeprom_lock(sc)) != 0) { 1542 aprint_error_dev(sc->sc_dev, 1543 "could not lock ROM (error=%d)\n", error); 1544 return error; 1545 } 1546 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1547 if ((error = iwn_init_otprom(sc)) != 0) { 1548 aprint_error_dev(sc->sc_dev, 1549 "could not initialize OTPROM\n"); 1550 return error; 1551 } 1552 } 1553 1554 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1555 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1556 /* Check if HT support is bonded out. */ 1557 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1558 sc->sc_flags |= IWN_FLAG_HAS_11N; 1559 1560 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1561 sc->rfcfg = le16toh(val); 1562 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1563 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1564 if (sc->txchainmask == 0) 1565 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1566 if (sc->rxchainmask == 0) 1567 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1568 1569 /* Read MAC address. */ 1570 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1571 1572 /* Read adapter-specific information from EEPROM. */ 1573 ops->read_eeprom(sc); 1574 1575 iwn_apm_stop(sc); /* Power OFF adapter. */ 1576 1577 iwn_eeprom_unlock(sc); 1578 return 0; 1579 } 1580 1581 static void 1582 iwn4965_read_eeprom(struct iwn_softc *sc) 1583 { 1584 uint32_t addr; 1585 uint16_t val; 1586 int i; 1587 1588 /* Read regulatory domain (4 ASCII characters). */ 1589 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1590 1591 /* Read the list of authorized channels (20MHz ones only). */ 1592 for (i = 0; i < 5; i++) { 1593 addr = iwn4965_regulatory_bands[i]; 1594 iwn_read_eeprom_channels(sc, i, addr); 1595 } 1596 1597 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1598 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1599 sc->maxpwr2GHz = val & 0xff; 1600 sc->maxpwr5GHz = val >> 8; 1601 /* Check that EEPROM values are within valid range. */ 1602 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1603 sc->maxpwr5GHz = 38; 1604 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1605 sc->maxpwr2GHz = 38; 1606 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1607 1608 /* Read samples for each TX power group. */ 1609 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1610 sizeof sc->bands); 1611 1612 /* Read voltage at which samples were taken. */ 1613 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1614 sc->eeprom_voltage = (int16_t)le16toh(val); 1615 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1616 1617 #ifdef IWN_DEBUG 1618 /* Print samples. */ 1619 if (iwn_debug > 0) { 1620 for (i = 0; i < IWN_NBANDS; i++) 1621 iwn4965_print_power_group(sc, i); 1622 } 1623 #endif 1624 } 1625 1626 #ifdef IWN_DEBUG 1627 static void 1628 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1629 { 1630 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1631 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1632 int j, c; 1633 1634 aprint_normal("===band %d===\n", i); 1635 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1636 aprint_normal("chan1 num=%d\n", chans[0].num); 1637 for (c = 0; c < 2; c++) { 1638 for (j = 0; j < IWN_NSAMPLES; j++) { 1639 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1640 "power=%d pa_det=%d\n", c, j, 1641 chans[0].samples[c][j].temp, 1642 chans[0].samples[c][j].gain, 1643 chans[0].samples[c][j].power, 1644 chans[0].samples[c][j].pa_det); 1645 } 1646 } 1647 aprint_normal("chan2 num=%d\n", chans[1].num); 1648 for (c = 0; c < 2; c++) { 1649 for (j = 0; j < IWN_NSAMPLES; j++) { 1650 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1651 "power=%d pa_det=%d\n", c, j, 1652 chans[1].samples[c][j].temp, 1653 chans[1].samples[c][j].gain, 1654 chans[1].samples[c][j].power, 1655 chans[1].samples[c][j].pa_det); 1656 } 1657 } 1658 } 1659 #endif 1660 1661 static void 1662 iwn5000_read_eeprom(struct iwn_softc *sc) 1663 { 1664 struct iwn5000_eeprom_calib_hdr hdr; 1665 int32_t volt; 1666 uint32_t base, addr; 1667 uint16_t val; 1668 int i; 1669 1670 /* Read regulatory domain (4 ASCII characters). */ 1671 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1672 base = le16toh(val); 1673 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1674 sc->eeprom_domain, 4); 1675 1676 /* Read the list of authorized channels (20MHz ones only). */ 1677 for (i = 0; i < 5; i++) { 1678 addr = base + iwn5000_regulatory_bands[i]; 1679 iwn_read_eeprom_channels(sc, i, addr); 1680 } 1681 1682 /* Read enhanced TX power information for 6000 Series. */ 1683 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1684 iwn_read_eeprom_enhinfo(sc); 1685 1686 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1687 base = le16toh(val); 1688 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1689 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1690 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1691 sc->calib_ver = hdr.version; 1692 1693 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1694 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1695 sc->hw_type == IWN_HW_REV_TYPE_135 || 1696 sc->hw_type == IWN_HW_REV_TYPE_105) { 1697 sc->eeprom_voltage = le16toh(hdr.volt); 1698 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1699 sc->eeprom_temp = le16toh(val); 1700 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1701 sc->eeprom_rawtemp = le16toh(val); 1702 } 1703 1704 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1705 /* Compute temperature offset. */ 1706 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1707 sc->eeprom_temp = le16toh(val); 1708 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1709 volt = le16toh(val); 1710 sc->temp_off = sc->eeprom_temp - (volt / -5); 1711 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1712 sc->eeprom_temp, volt, sc->temp_off)); 1713 } else { 1714 /* Read crystal calibration. */ 1715 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1716 &sc->eeprom_crystal, sizeof (uint32_t)); 1717 DPRINTF(("crystal calibration 0x%08x\n", 1718 le32toh(sc->eeprom_crystal))); 1719 } 1720 } 1721 1722 static void 1723 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1724 { 1725 struct ieee80211com *ic = &sc->sc_ic; 1726 const struct iwn_chan_band *band = &iwn_bands[n]; 1727 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1728 uint8_t chan; 1729 int i; 1730 1731 iwn_read_prom_data(sc, addr, channels, 1732 band->nchan * sizeof (struct iwn_eeprom_chan)); 1733 1734 for (i = 0; i < band->nchan; i++) { 1735 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1736 continue; 1737 1738 chan = band->chan[i]; 1739 1740 if (n == 0) { /* 2GHz band */ 1741 ic->ic_channels[chan].ic_freq = 1742 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1743 ic->ic_channels[chan].ic_flags = 1744 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1745 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1746 1747 } else { /* 5GHz band */ 1748 /* 1749 * Some adapters support channels 7, 8, 11 and 12 1750 * both in the 2GHz and 4.9GHz bands. 1751 * Because of limitations in our net80211 layer, 1752 * we don't support them in the 4.9GHz band. 1753 */ 1754 if (chan <= 14) 1755 continue; 1756 1757 ic->ic_channels[chan].ic_freq = 1758 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1759 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1760 /* We have at least one valid 5GHz channel. */ 1761 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1762 } 1763 1764 /* Is active scan allowed on this channel? */ 1765 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1766 ic->ic_channels[chan].ic_flags |= 1767 IEEE80211_CHAN_PASSIVE; 1768 } 1769 1770 /* Save maximum allowed TX power for this channel. */ 1771 sc->maxpwr[chan] = channels[i].maxpwr; 1772 1773 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1774 chan, channels[i].flags, sc->maxpwr[chan])); 1775 } 1776 } 1777 1778 static void 1779 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1780 { 1781 struct iwn_eeprom_enhinfo enhinfo[35]; 1782 uint16_t val, base; 1783 int8_t maxpwr; 1784 uint8_t flags; 1785 int i; 1786 1787 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1788 base = le16toh(val); 1789 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1790 enhinfo, sizeof enhinfo); 1791 1792 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1793 for (i = 0; i < __arraycount(enhinfo); i++) { 1794 flags = enhinfo[i].flags; 1795 if (!(flags & IWN_ENHINFO_VALID)) 1796 continue; /* Skip invalid entries. */ 1797 1798 maxpwr = 0; 1799 if (sc->txchainmask & IWN_ANT_A) 1800 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1801 if (sc->txchainmask & IWN_ANT_B) 1802 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1803 if (sc->txchainmask & IWN_ANT_C) 1804 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1805 if (sc->ntxchains == 2) 1806 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1807 else if (sc->ntxchains == 3) 1808 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1809 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1810 1811 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1812 sc->enh_maxpwr[i] = maxpwr; 1813 } 1814 } 1815 1816 static struct ieee80211_node * 1817 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1818 { 1819 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1820 } 1821 1822 static void 1823 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1824 { 1825 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1826 struct iwn_node *wn = (void *)ni; 1827 uint8_t rate; 1828 int ridx, i; 1829 1830 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1831 /* Start at lowest available bit-rate, AMRR will raise. */ 1832 ni->ni_txrate = 0; 1833 1834 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1835 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1836 /* Map 802.11 rate to HW rate index. */ 1837 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1838 if (iwn_rates[ridx].rate == rate) 1839 break; 1840 wn->ridx[i] = ridx; 1841 } 1842 } 1843 1844 static int 1845 iwn_media_change(struct ifnet *ifp) 1846 { 1847 struct iwn_softc *sc = ifp->if_softc; 1848 struct ieee80211com *ic = &sc->sc_ic; 1849 uint8_t rate, ridx; 1850 int error; 1851 1852 error = ieee80211_media_change(ifp); 1853 if (error != ENETRESET) 1854 return error; 1855 1856 if (ic->ic_fixed_rate != -1) { 1857 rate = ic->ic_sup_rates[ic->ic_curmode]. 1858 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1859 /* Map 802.11 rate to HW rate index. */ 1860 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1861 if (iwn_rates[ridx].rate == rate) 1862 break; 1863 sc->fixed_ridx = ridx; 1864 } 1865 1866 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1867 (IFF_UP | IFF_RUNNING)) { 1868 iwn_stop(ifp, 0); 1869 error = iwn_init(ifp); 1870 } 1871 return error; 1872 } 1873 1874 static int 1875 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1876 { 1877 struct ifnet *ifp = ic->ic_ifp; 1878 struct iwn_softc *sc = ifp->if_softc; 1879 int error; 1880 1881 callout_stop(&sc->calib_to); 1882 1883 switch (nstate) { 1884 case IEEE80211_S_SCAN: 1885 /* XXX Do not abort a running scan. */ 1886 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1887 if (ic->ic_state != nstate) 1888 aprint_debug_dev(sc->sc_dev, "scan request(%d) " 1889 "while scanning(%d) ignored\n", nstate, 1890 ic->ic_state); 1891 break; 1892 } 1893 1894 /* XXX Not sure if call and flags are needed. */ 1895 ieee80211_node_table_reset(&ic->ic_scan); 1896 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1897 sc->sc_flags |= IWN_FLAG_SCANNING_2GHZ; 1898 1899 /* Make the link LED blink while we're scanning. */ 1900 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1901 1902 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1903 aprint_error_dev(sc->sc_dev, 1904 "could not initiate scan\n"); 1905 return error; 1906 } 1907 ic->ic_state = nstate; 1908 return 0; 1909 1910 case IEEE80211_S_ASSOC: 1911 if (ic->ic_state != IEEE80211_S_RUN) 1912 break; 1913 /* FALLTHROUGH */ 1914 case IEEE80211_S_AUTH: 1915 /* Reset state to handle reassociations correctly. */ 1916 sc->rxon.associd = 0; 1917 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1918 sc->calib.state = IWN_CALIB_STATE_INIT; 1919 1920 /* Wait until we hear a beacon before we transmit */ 1921 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 1922 sc->sc_beacon_wait = 1; 1923 1924 if ((error = iwn_auth(sc)) != 0) { 1925 aprint_error_dev(sc->sc_dev, 1926 "could not move to auth state\n"); 1927 return error; 1928 } 1929 break; 1930 1931 case IEEE80211_S_RUN: 1932 /* 1933 * RUN -> RUN transition; Just restart timers. 1934 */ 1935 if (ic->ic_state == IEEE80211_S_RUN) { 1936 sc->calib_cnt = 0; 1937 break; 1938 } 1939 1940 /* Wait until we hear a beacon before we transmit */ 1941 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 1942 sc->sc_beacon_wait = 1; 1943 1944 if ((error = iwn_run(sc)) != 0) { 1945 aprint_error_dev(sc->sc_dev, 1946 "could not move to run state\n"); 1947 return error; 1948 } 1949 break; 1950 1951 case IEEE80211_S_INIT: 1952 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1953 sc->calib.state = IWN_CALIB_STATE_INIT; 1954 /* 1955 * Purge the xmit queue so we don't have old frames 1956 * during a new association attempt. 1957 */ 1958 sc->sc_beacon_wait = 0; 1959 ifp->if_flags &= ~IFF_OACTIVE; 1960 iwn_start(ifp); 1961 break; 1962 } 1963 1964 return sc->sc_newstate(ic, nstate, arg); 1965 } 1966 1967 static void 1968 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1969 { 1970 struct iwn_softc *sc = arg; 1971 struct iwn_node *wn = (struct iwn_node *)ni; 1972 1973 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1974 } 1975 1976 static void 1977 iwn_calib_timeout(void *arg) 1978 { 1979 struct iwn_softc *sc = arg; 1980 struct ieee80211com *ic = &sc->sc_ic; 1981 int s; 1982 1983 s = splnet(); 1984 if (ic->ic_fixed_rate == -1) { 1985 if (ic->ic_opmode == IEEE80211_M_STA) 1986 iwn_iter_func(sc, ic->ic_bss); 1987 else 1988 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1989 } 1990 /* Force automatic TX power calibration every 60 secs. */ 1991 if (++sc->calib_cnt >= 120) { 1992 uint32_t flags = 0; 1993 1994 DPRINTF(("sending request for statistics\n")); 1995 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1996 sizeof flags, 1); 1997 sc->calib_cnt = 0; 1998 } 1999 splx(s); 2000 2001 /* Automatic rate control triggered every 500ms. */ 2002 callout_schedule(&sc->calib_to, mstohz(500)); 2003 } 2004 2005 /* 2006 * Process an RX_PHY firmware notification. This is usually immediately 2007 * followed by an MPDU_RX_DONE notification. 2008 */ 2009 static void 2010 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2011 struct iwn_rx_data *data) 2012 { 2013 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2014 2015 DPRINTFN(2, ("received PHY stats\n")); 2016 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2017 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2018 2019 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2020 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2021 sc->last_rx_valid = 1; 2022 } 2023 2024 /* 2025 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2026 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2027 */ 2028 static void 2029 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2030 struct iwn_rx_data *data) 2031 { 2032 struct iwn_ops *ops = &sc->ops; 2033 struct ieee80211com *ic = &sc->sc_ic; 2034 struct ifnet *ifp = ic->ic_ifp; 2035 struct iwn_rx_ring *ring = &sc->rxq; 2036 struct ieee80211_frame *wh; 2037 struct ieee80211_node *ni; 2038 struct mbuf *m, *m1; 2039 struct iwn_rx_stat *stat; 2040 char *head; 2041 uint32_t flags; 2042 int error, len, rssi, s; 2043 2044 if (desc->type == IWN_MPDU_RX_DONE) { 2045 /* Check for prior RX_PHY notification. */ 2046 if (!sc->last_rx_valid) { 2047 DPRINTF(("missing RX_PHY\n")); 2048 return; 2049 } 2050 sc->last_rx_valid = 0; 2051 stat = &sc->last_rx_stat; 2052 } else 2053 stat = (struct iwn_rx_stat *)(desc + 1); 2054 2055 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2056 BUS_DMASYNC_POSTREAD); 2057 2058 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2059 aprint_error_dev(sc->sc_dev, 2060 "invalid RX statistic header\n"); 2061 return; 2062 } 2063 if (desc->type == IWN_MPDU_RX_DONE) { 2064 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2065 head = (char *)(mpdu + 1); 2066 len = le16toh(mpdu->len); 2067 } else { 2068 head = (char *)(stat + 1) + stat->cfg_phy_len; 2069 len = le16toh(stat->len); 2070 } 2071 2072 flags = le32toh(*(uint32_t *)(head + len)); 2073 2074 /* Discard frames with a bad FCS early. */ 2075 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2076 DPRINTFN(2, ("RX flags error %x\n", flags)); 2077 ifp->if_ierrors++; 2078 return; 2079 } 2080 /* Discard frames that are too short. */ 2081 if (len < sizeof (*wh)) { 2082 DPRINTF(("frame too short: %d\n", len)); 2083 ic->ic_stats.is_rx_tooshort++; 2084 ifp->if_ierrors++; 2085 return; 2086 } 2087 2088 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2089 if (m1 == NULL) { 2090 ic->ic_stats.is_rx_nobuf++; 2091 ifp->if_ierrors++; 2092 return; 2093 } 2094 bus_dmamap_unload(sc->sc_dmat, data->map); 2095 2096 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2097 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2098 if (error != 0) { 2099 m_freem(m1); 2100 2101 /* Try to reload the old mbuf. */ 2102 error = bus_dmamap_load(sc->sc_dmat, data->map, 2103 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2104 BUS_DMA_NOWAIT | BUS_DMA_READ); 2105 if (error != 0) { 2106 panic("%s: could not load old RX mbuf", 2107 device_xname(sc->sc_dev)); 2108 } 2109 /* Physical address may have changed. */ 2110 ring->desc[ring->cur] = 2111 htole32(data->map->dm_segs[0].ds_addr >> 8); 2112 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2113 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2114 BUS_DMASYNC_PREWRITE); 2115 ifp->if_ierrors++; 2116 return; 2117 } 2118 2119 m = data->m; 2120 data->m = m1; 2121 /* Update RX descriptor. */ 2122 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2123 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2124 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2125 BUS_DMASYNC_PREWRITE); 2126 2127 /* Finalize mbuf. */ 2128 m_set_rcvif(m, ifp); 2129 m->m_data = head; 2130 m->m_pkthdr.len = m->m_len = len; 2131 2132 s = splnet(); 2133 2134 /* Grab a reference to the source node. */ 2135 wh = mtod(m, struct ieee80211_frame *); 2136 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2137 2138 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2139 /* NetBSD does decryption in ieee80211_input. */ 2140 2141 rssi = ops->get_rssi(stat); 2142 2143 /* XXX Added for NetBSD: scans never stop without it */ 2144 if (ic->ic_state == IEEE80211_S_SCAN) 2145 iwn_fix_channel(ic, m, stat); 2146 2147 if (sc->sc_drvbpf != NULL) { 2148 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2149 2150 tap->wr_flags = 0; 2151 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2152 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2153 tap->wr_chan_freq = 2154 htole16(ic->ic_channels[stat->chan].ic_freq); 2155 tap->wr_chan_flags = 2156 htole16(ic->ic_channels[stat->chan].ic_flags); 2157 tap->wr_dbm_antsignal = (int8_t)rssi; 2158 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2159 tap->wr_tsft = stat->tstamp; 2160 switch (stat->rate) { 2161 /* CCK rates. */ 2162 case 10: tap->wr_rate = 2; break; 2163 case 20: tap->wr_rate = 4; break; 2164 case 55: tap->wr_rate = 11; break; 2165 case 110: tap->wr_rate = 22; break; 2166 /* OFDM rates. */ 2167 case 0xd: tap->wr_rate = 12; break; 2168 case 0xf: tap->wr_rate = 18; break; 2169 case 0x5: tap->wr_rate = 24; break; 2170 case 0x7: tap->wr_rate = 36; break; 2171 case 0x9: tap->wr_rate = 48; break; 2172 case 0xb: tap->wr_rate = 72; break; 2173 case 0x1: tap->wr_rate = 96; break; 2174 case 0x3: tap->wr_rate = 108; break; 2175 /* Unknown rate: should not happen. */ 2176 default: tap->wr_rate = 0; 2177 } 2178 2179 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2180 } 2181 2182 /* 2183 * If it's a beacon and we're waiting, then do the wakeup. 2184 */ 2185 if (sc->sc_beacon_wait) { 2186 uint8_t type, subtype; 2187 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2188 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2189 /* 2190 * This assumes at this point we've received our own 2191 * beacon. 2192 */ 2193 if (type == IEEE80211_FC0_TYPE_MGT && 2194 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 2195 sc->sc_beacon_wait = 0; 2196 ifp->if_flags &= ~IFF_OACTIVE; 2197 iwn_start(ifp); 2198 } 2199 } 2200 2201 /* Send the frame to the 802.11 layer. */ 2202 ieee80211_input(ic, m, ni, rssi, 0); 2203 2204 /* Node is no longer needed. */ 2205 ieee80211_free_node(ni); 2206 2207 splx(s); 2208 } 2209 2210 #ifndef IEEE80211_NO_HT 2211 /* Process an incoming Compressed BlockAck. */ 2212 static void 2213 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2214 struct iwn_rx_data *data) 2215 { 2216 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2217 struct iwn_tx_ring *txq; 2218 2219 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2220 BUS_DMASYNC_POSTREAD); 2221 2222 txq = &sc->txq[le16toh(ba->qid)]; 2223 /* XXX TBD */ 2224 } 2225 #endif 2226 2227 /* 2228 * Process a CALIBRATION_RESULT notification sent by the initialization 2229 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2230 */ 2231 static void 2232 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2233 struct iwn_rx_data *data) 2234 { 2235 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2236 int len, idx = -1; 2237 2238 /* Runtime firmware should not send such a notification. */ 2239 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2240 return; 2241 2242 len = (le32toh(desc->len) & 0x3fff) - 4; 2243 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2244 BUS_DMASYNC_POSTREAD); 2245 2246 switch (calib->code) { 2247 case IWN5000_PHY_CALIB_DC: 2248 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2249 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2250 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2251 sc->hw_type == IWN_HW_REV_TYPE_135 || 2252 sc->hw_type == IWN_HW_REV_TYPE_105) 2253 idx = 0; 2254 break; 2255 case IWN5000_PHY_CALIB_LO: 2256 idx = 1; 2257 break; 2258 case IWN5000_PHY_CALIB_TX_IQ: 2259 idx = 2; 2260 break; 2261 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2262 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2263 sc->hw_type != IWN_HW_REV_TYPE_5150) 2264 idx = 3; 2265 break; 2266 case IWN5000_PHY_CALIB_BASE_BAND: 2267 idx = 4; 2268 break; 2269 } 2270 if (idx == -1) /* Ignore other results. */ 2271 return; 2272 2273 /* Save calibration result. */ 2274 if (sc->calibcmd[idx].buf != NULL) 2275 free(sc->calibcmd[idx].buf, M_DEVBUF); 2276 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2277 if (sc->calibcmd[idx].buf == NULL) { 2278 DPRINTF(("not enough memory for calibration result %d\n", 2279 calib->code)); 2280 return; 2281 } 2282 DPRINTF(("saving calibration result code=%d len=%d\n", 2283 calib->code, len)); 2284 sc->calibcmd[idx].len = len; 2285 memcpy(sc->calibcmd[idx].buf, calib, len); 2286 } 2287 2288 /* 2289 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2290 * The latter is sent by the firmware after each received beacon. 2291 */ 2292 static void 2293 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2294 struct iwn_rx_data *data) 2295 { 2296 struct iwn_ops *ops = &sc->ops; 2297 struct ieee80211com *ic = &sc->sc_ic; 2298 struct iwn_calib_state *calib = &sc->calib; 2299 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2300 int temp; 2301 2302 /* Ignore statistics received during a scan. */ 2303 if (ic->ic_state != IEEE80211_S_RUN) 2304 return; 2305 2306 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2307 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2308 2309 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2310 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2311 2312 /* Test if temperature has changed. */ 2313 if (stats->general.temp != sc->rawtemp) { 2314 /* Convert "raw" temperature to degC. */ 2315 sc->rawtemp = stats->general.temp; 2316 temp = ops->get_temperature(sc); 2317 DPRINTFN(2, ("temperature=%dC\n", temp)); 2318 2319 /* Update TX power if need be (4965AGN only). */ 2320 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2321 iwn4965_power_calibration(sc, temp); 2322 } 2323 2324 if (desc->type != IWN_BEACON_STATISTICS) 2325 return; /* Reply to a statistics request. */ 2326 2327 sc->noise = iwn_get_noise(&stats->rx.general); 2328 2329 /* Test that RSSI and noise are present in stats report. */ 2330 if (le32toh(stats->rx.general.flags) != 1) { 2331 DPRINTF(("received statistics without RSSI\n")); 2332 return; 2333 } 2334 2335 /* 2336 * XXX Differential gain calibration makes the 6005 firmware 2337 * crap out, so skip it for now. This effectively disables 2338 * sensitivity tuning as well. 2339 */ 2340 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2341 return; 2342 2343 if (calib->state == IWN_CALIB_STATE_ASSOC) 2344 iwn_collect_noise(sc, &stats->rx.general); 2345 else if (calib->state == IWN_CALIB_STATE_RUN) 2346 iwn_tune_sensitivity(sc, &stats->rx); 2347 } 2348 2349 /* 2350 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2351 * and 5000 adapters have different incompatible TX status formats. 2352 */ 2353 static void 2354 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2355 struct iwn_rx_data *data) 2356 { 2357 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2358 2359 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2360 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2361 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2362 } 2363 2364 static void 2365 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2366 struct iwn_rx_data *data) 2367 { 2368 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2369 2370 #ifdef notyet 2371 /* Reset TX scheduler slot. */ 2372 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2373 #endif 2374 2375 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2376 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2377 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2378 } 2379 2380 /* 2381 * Adapter-independent backend for TX_DONE firmware notifications. 2382 */ 2383 static void 2384 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2385 uint8_t status) 2386 { 2387 struct ieee80211com *ic = &sc->sc_ic; 2388 struct ifnet *ifp = ic->ic_ifp; 2389 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2390 struct iwn_tx_data *data = &ring->data[desc->idx]; 2391 struct iwn_node *wn = (struct iwn_node *)data->ni; 2392 int s; 2393 2394 s = splnet(); 2395 2396 /* Update rate control statistics. */ 2397 wn->amn.amn_txcnt++; 2398 if (ackfailcnt > 0) 2399 wn->amn.amn_retrycnt++; 2400 2401 if (status != 1 && status != 2) 2402 ifp->if_oerrors++; 2403 else 2404 ifp->if_opackets++; 2405 2406 /* Unmap and free mbuf. */ 2407 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2408 BUS_DMASYNC_POSTWRITE); 2409 bus_dmamap_unload(sc->sc_dmat, data->map); 2410 m_freem(data->m); 2411 data->m = NULL; 2412 ieee80211_free_node(data->ni); 2413 data->ni = NULL; 2414 2415 sc->sc_tx_timer = 0; 2416 if (--ring->queued < IWN_TX_RING_LOMARK) { 2417 sc->qfullmsk &= ~(1 << ring->qid); 2418 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2419 ifp->if_flags &= ~IFF_OACTIVE; 2420 iwn_start(ifp); 2421 } 2422 } 2423 2424 splx(s); 2425 } 2426 2427 /* 2428 * Process a "command done" firmware notification. This is where we wakeup 2429 * processes waiting for a synchronous command completion. 2430 */ 2431 static void 2432 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2433 { 2434 struct iwn_tx_ring *ring = &sc->txq[4]; 2435 struct iwn_tx_data *data; 2436 2437 if ((desc->qid & 0xf) != 4) 2438 return; /* Not a command ack. */ 2439 2440 data = &ring->data[desc->idx]; 2441 2442 /* If the command was mapped in an mbuf, free it. */ 2443 if (data->m != NULL) { 2444 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2445 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2446 bus_dmamap_unload(sc->sc_dmat, data->map); 2447 m_freem(data->m); 2448 data->m = NULL; 2449 } 2450 wakeup(&ring->desc[desc->idx]); 2451 } 2452 2453 /* 2454 * Process an INT_FH_RX or INT_SW_RX interrupt. 2455 */ 2456 static void 2457 iwn_notif_intr(struct iwn_softc *sc) 2458 { 2459 struct iwn_ops *ops = &sc->ops; 2460 struct ieee80211com *ic = &sc->sc_ic; 2461 struct ifnet *ifp = ic->ic_ifp; 2462 uint16_t hw; 2463 int s; 2464 2465 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2466 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2467 2468 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2469 while (sc->rxq.cur != hw) { 2470 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2471 struct iwn_rx_desc *desc; 2472 2473 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2474 BUS_DMASYNC_POSTREAD); 2475 desc = mtod(data->m, struct iwn_rx_desc *); 2476 2477 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2478 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2479 2480 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2481 iwn_cmd_done(sc, desc); 2482 2483 switch (desc->type) { 2484 case IWN_RX_PHY: 2485 iwn_rx_phy(sc, desc, data); 2486 break; 2487 2488 case IWN_RX_DONE: /* 4965AGN only. */ 2489 case IWN_MPDU_RX_DONE: 2490 /* An 802.11 frame has been received. */ 2491 iwn_rx_done(sc, desc, data); 2492 break; 2493 #ifndef IEEE80211_NO_HT 2494 case IWN_RX_COMPRESSED_BA: 2495 /* A Compressed BlockAck has been received. */ 2496 iwn_rx_compressed_ba(sc, desc, data); 2497 break; 2498 #endif 2499 case IWN_TX_DONE: 2500 /* An 802.11 frame has been transmitted. */ 2501 ops->tx_done(sc, desc, data); 2502 break; 2503 2504 case IWN_RX_STATISTICS: 2505 case IWN_BEACON_STATISTICS: 2506 iwn_rx_statistics(sc, desc, data); 2507 break; 2508 2509 case IWN_BEACON_MISSED: 2510 { 2511 struct iwn_beacon_missed *miss = 2512 (struct iwn_beacon_missed *)(desc + 1); 2513 2514 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2515 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2516 /* 2517 * If more than 5 consecutive beacons are missed, 2518 * reinitialize the sensitivity state machine. 2519 */ 2520 DPRINTF(("beacons missed %d/%d\n", 2521 le32toh(miss->consecutive), le32toh(miss->total))); 2522 if (ic->ic_state == IEEE80211_S_RUN && 2523 le32toh(miss->consecutive) > 5) 2524 (void)iwn_init_sensitivity(sc); 2525 break; 2526 } 2527 case IWN_UC_READY: 2528 { 2529 struct iwn_ucode_info *uc = 2530 (struct iwn_ucode_info *)(desc + 1); 2531 2532 /* The microcontroller is ready. */ 2533 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2534 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2535 DPRINTF(("microcode alive notification version=%d.%d " 2536 "subtype=%x alive=%x\n", uc->major, uc->minor, 2537 uc->subtype, le32toh(uc->valid))); 2538 2539 if (le32toh(uc->valid) != 1) { 2540 aprint_error_dev(sc->sc_dev, 2541 "microcontroller initialization " 2542 "failed\n"); 2543 break; 2544 } 2545 if (uc->subtype == IWN_UCODE_INIT) { 2546 /* Save microcontroller report. */ 2547 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2548 } 2549 /* Save the address of the error log in SRAM. */ 2550 sc->errptr = le32toh(uc->errptr); 2551 break; 2552 } 2553 case IWN_STATE_CHANGED: 2554 { 2555 uint32_t *status = (uint32_t *)(desc + 1); 2556 2557 /* Enabled/disabled notification. */ 2558 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2559 sizeof (*status), BUS_DMASYNC_POSTREAD); 2560 DPRINTF(("state changed to %x\n", le32toh(*status))); 2561 2562 if (le32toh(*status) & 1) { 2563 /* The radio button has to be pushed. */ 2564 aprint_error_dev(sc->sc_dev, 2565 "Radio transmitter is off\n"); 2566 /* Turn the interface down. */ 2567 s = splnet(); 2568 ifp->if_flags &= ~IFF_UP; 2569 iwn_stop(ifp, 1); 2570 splx(s); 2571 return; /* No further processing. */ 2572 } 2573 break; 2574 } 2575 case IWN_START_SCAN: 2576 { 2577 struct iwn_start_scan *scan = 2578 (struct iwn_start_scan *)(desc + 1); 2579 2580 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2581 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2582 DPRINTFN(2, ("scanning channel %d status %x\n", 2583 scan->chan, le32toh(scan->status))); 2584 2585 /* Fix current channel. */ 2586 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2587 break; 2588 } 2589 case IWN_STOP_SCAN: 2590 { 2591 struct iwn_stop_scan *scan = 2592 (struct iwn_stop_scan *)(desc + 1); 2593 2594 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2595 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2596 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2597 scan->nchan, scan->status, scan->chan)); 2598 2599 if (scan->status == 1 && scan->chan <= 14 && 2600 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2601 /* 2602 * We just finished scanning 2GHz channels, 2603 * start scanning 5GHz ones. 2604 */ 2605 sc->sc_flags &= ~IWN_FLAG_SCANNING_2GHZ; 2606 sc->sc_flags |= IWN_FLAG_SCANNING_5GHZ; 2607 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2608 break; 2609 } 2610 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2611 ieee80211_end_scan(ic); 2612 break; 2613 } 2614 case IWN5000_CALIBRATION_RESULT: 2615 iwn5000_rx_calib_results(sc, desc, data); 2616 break; 2617 2618 case IWN5000_CALIBRATION_DONE: 2619 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2620 wakeup(sc); 2621 break; 2622 } 2623 2624 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2625 } 2626 2627 /* Tell the firmware what we have processed. */ 2628 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2629 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2630 } 2631 2632 /* 2633 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2634 * from power-down sleep mode. 2635 */ 2636 static void 2637 iwn_wakeup_intr(struct iwn_softc *sc) 2638 { 2639 int qid; 2640 2641 DPRINTF(("ucode wakeup from power-down sleep\n")); 2642 2643 /* Wakeup RX and TX rings. */ 2644 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2645 for (qid = 0; qid < sc->ntxqs; qid++) { 2646 struct iwn_tx_ring *ring = &sc->txq[qid]; 2647 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2648 } 2649 } 2650 2651 /* 2652 * Dump the error log of the firmware when a firmware panic occurs. Although 2653 * we can't debug the firmware because it is neither open source nor free, it 2654 * can help us to identify certain classes of problems. 2655 */ 2656 static void 2657 iwn_fatal_intr(struct iwn_softc *sc) 2658 { 2659 struct iwn_fw_dump dump; 2660 int i; 2661 2662 /* Force a complete recalibration on next init. */ 2663 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2664 2665 /* Check that the error log address is valid. */ 2666 if (sc->errptr < IWN_FW_DATA_BASE || 2667 sc->errptr + sizeof (dump) > 2668 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2669 aprint_error_dev(sc->sc_dev, 2670 "bad firmware error log address 0x%08x\n", sc->errptr); 2671 return; 2672 } 2673 if (iwn_nic_lock(sc) != 0) { 2674 aprint_error_dev(sc->sc_dev, 2675 "could not read firmware error log\n"); 2676 return; 2677 } 2678 /* Read firmware error log from SRAM. */ 2679 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2680 sizeof (dump) / sizeof (uint32_t)); 2681 iwn_nic_unlock(sc); 2682 2683 if (dump.valid == 0) { 2684 aprint_error_dev(sc->sc_dev, 2685 "firmware error log is empty\n"); 2686 return; 2687 } 2688 aprint_error("firmware error log:\n"); 2689 aprint_error(" error type = \"%s\" (0x%08X)\n", 2690 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2691 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2692 dump.id); 2693 aprint_error(" program counter = 0x%08X\n", dump.pc); 2694 aprint_error(" source line = 0x%08X\n", dump.src_line); 2695 aprint_error(" error data = 0x%08X%08X\n", 2696 dump.error_data[0], dump.error_data[1]); 2697 aprint_error(" branch link = 0x%08X%08X\n", 2698 dump.branch_link[0], dump.branch_link[1]); 2699 aprint_error(" interrupt link = 0x%08X%08X\n", 2700 dump.interrupt_link[0], dump.interrupt_link[1]); 2701 aprint_error(" time = %u\n", dump.time[0]); 2702 2703 /* Dump driver status (TX and RX rings) while we're here. */ 2704 aprint_error("driver status:\n"); 2705 for (i = 0; i < sc->ntxqs; i++) { 2706 struct iwn_tx_ring *ring = &sc->txq[i]; 2707 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2708 i, ring->qid, ring->cur, ring->queued); 2709 } 2710 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2711 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2712 } 2713 2714 static int 2715 iwn_intr(void *arg) 2716 { 2717 struct iwn_softc *sc = arg; 2718 2719 /* Disable interrupts. */ 2720 IWN_WRITE(sc, IWN_INT_MASK, 0); 2721 2722 softint_schedule(sc->sc_soft_ih); 2723 return 1; 2724 } 2725 2726 static void 2727 iwn_softintr(void *arg) 2728 { 2729 struct iwn_softc *sc = arg; 2730 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2731 uint32_t r1, r2, tmp; 2732 int s; 2733 2734 /* Read interrupts from ICT (fast) or from registers (slow). */ 2735 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2736 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, 2737 IWN_ICT_SIZE, BUS_DMASYNC_POSTREAD); 2738 tmp = 0; 2739 while (sc->ict[sc->ict_cur] != 0) { 2740 tmp |= sc->ict[sc->ict_cur]; 2741 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2742 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2743 } 2744 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, 2745 IWN_ICT_SIZE, BUS_DMASYNC_PREWRITE); 2746 tmp = le32toh(tmp); 2747 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2748 tmp = 0; 2749 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2750 tmp |= 0x8000; 2751 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2752 r2 = 0; /* Unused. */ 2753 } else { 2754 r1 = IWN_READ(sc, IWN_INT); 2755 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2756 return; /* Hardware gone! */ 2757 r2 = IWN_READ(sc, IWN_FH_INT); 2758 } 2759 if (r1 == 0 && r2 == 0) { 2760 goto out; /* Interrupt not for us. */ 2761 } 2762 2763 /* Acknowledge interrupts. */ 2764 IWN_WRITE(sc, IWN_INT, r1); 2765 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2766 IWN_WRITE(sc, IWN_FH_INT, r2); 2767 2768 if (r1 & IWN_INT_RF_TOGGLED) { 2769 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2770 aprint_error_dev(sc->sc_dev, 2771 "RF switch: radio %s\n", 2772 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2773 } 2774 if (r1 & IWN_INT_CT_REACHED) { 2775 aprint_error_dev(sc->sc_dev, 2776 "critical temperature reached!\n"); 2777 } 2778 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2779 aprint_error_dev(sc->sc_dev, 2780 "fatal firmware error\n"); 2781 /* Dump firmware error log and stop. */ 2782 iwn_fatal_intr(sc); 2783 s = splnet(); 2784 ifp->if_flags &= ~IFF_UP; 2785 iwn_stop(ifp, 1); 2786 splx(s); 2787 return; 2788 } 2789 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2790 (r2 & IWN_FH_INT_RX)) { 2791 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2792 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2793 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2794 IWN_WRITE_1(sc, IWN_INT_PERIODIC, IWN_INT_PERIODIC_DIS); 2795 iwn_notif_intr(sc); 2796 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2797 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2798 IWN_INT_PERIODIC_ENA); 2799 } 2800 } else 2801 iwn_notif_intr(sc); 2802 } 2803 2804 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2805 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2806 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2807 wakeup(sc); /* FH DMA transfer completed. */ 2808 } 2809 2810 if (r1 & IWN_INT_ALIVE) 2811 wakeup(sc); /* Firmware is alive. */ 2812 2813 if (r1 & IWN_INT_WAKEUP) 2814 iwn_wakeup_intr(sc); 2815 2816 out: 2817 /* Re-enable interrupts. */ 2818 if (ifp->if_flags & IFF_UP) 2819 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2820 } 2821 2822 /* 2823 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2824 * 5000 adapters use a slightly different format). 2825 */ 2826 static void 2827 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2828 uint16_t len) 2829 { 2830 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2831 2832 *w = htole16(len + 8); 2833 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2834 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2835 sizeof (uint16_t), 2836 BUS_DMASYNC_PREWRITE); 2837 if (idx < IWN_SCHED_WINSZ) { 2838 *(w + IWN_TX_RING_COUNT) = *w; 2839 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2840 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2841 (char *)(void *)sc->sched_dma.vaddr, 2842 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2843 } 2844 } 2845 2846 static void 2847 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2848 uint16_t len) 2849 { 2850 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2851 2852 *w = htole16(id << 12 | (len + 8)); 2853 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2854 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2855 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2856 if (idx < IWN_SCHED_WINSZ) { 2857 *(w + IWN_TX_RING_COUNT) = *w; 2858 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2859 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2860 (char *)(void *)sc->sched_dma.vaddr, 2861 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2862 } 2863 } 2864 2865 #ifdef notyet 2866 static void 2867 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2868 { 2869 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2870 2871 *w = (*w & htole16(0xf000)) | htole16(1); 2872 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2873 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2874 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2875 if (idx < IWN_SCHED_WINSZ) { 2876 *(w + IWN_TX_RING_COUNT) = *w; 2877 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2878 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2879 (char *)(void *)sc->sched_dma.vaddr, 2880 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2881 } 2882 } 2883 #endif 2884 2885 static int 2886 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2887 { 2888 struct ieee80211com *ic = &sc->sc_ic; 2889 struct iwn_node *wn = (void *)ni; 2890 struct iwn_tx_ring *ring; 2891 struct iwn_tx_desc *desc; 2892 struct iwn_tx_data *data; 2893 struct iwn_tx_cmd *cmd; 2894 struct iwn_cmd_data *tx; 2895 const struct iwn_rate *rinfo; 2896 struct ieee80211_frame *wh; 2897 struct ieee80211_key *k = NULL; 2898 struct mbuf *m1; 2899 uint32_t flags; 2900 u_int hdrlen; 2901 bus_dma_segment_t *seg; 2902 uint8_t tid, ridx, txant, type; 2903 int i, totlen, error, pad; 2904 2905 const struct chanAccParams *cap; 2906 int noack; 2907 int hdrlen2; 2908 2909 wh = mtod(m, struct ieee80211_frame *); 2910 hdrlen = ieee80211_anyhdrsize(wh); 2911 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2912 2913 hdrlen2 = (ieee80211_has_qos(wh)) ? 2914 sizeof (struct ieee80211_qosframe) : 2915 sizeof (struct ieee80211_frame); 2916 2917 if (hdrlen != hdrlen2) 2918 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2919 hdrlen, hdrlen2); 2920 2921 /* XXX OpenBSD sets a different tid when using QOS */ 2922 tid = 0; 2923 if (ieee80211_has_qos(wh)) { 2924 cap = &ic->ic_wme.wme_chanParams; 2925 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2926 } 2927 else 2928 noack = 0; 2929 2930 ring = &sc->txq[ac]; 2931 desc = &ring->desc[ring->cur]; 2932 data = &ring->data[ring->cur]; 2933 2934 /* Choose a TX rate index. */ 2935 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2936 type != IEEE80211_FC0_TYPE_DATA) { 2937 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2938 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2939 } else if (ic->ic_fixed_rate != -1) { 2940 ridx = sc->fixed_ridx; 2941 } else 2942 ridx = wn->ridx[ni->ni_txrate]; 2943 rinfo = &iwn_rates[ridx]; 2944 2945 /* Encrypt the frame if need be. */ 2946 /* 2947 * XXX For now, NetBSD swaps the encryption and bpf sections 2948 * in order to match old code and other drivers. Tests with 2949 * tcpdump indicates that the order is irrelevant, however, 2950 * as bpf produces unencrypted data for both ordering choices. 2951 */ 2952 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2953 k = ieee80211_crypto_encap(ic, ni, m); 2954 if (k == NULL) { 2955 m_freem(m); 2956 return ENOBUFS; 2957 } 2958 /* Packet header may have moved, reset our local pointer. */ 2959 wh = mtod(m, struct ieee80211_frame *); 2960 } 2961 totlen = m->m_pkthdr.len; 2962 2963 if (sc->sc_drvbpf != NULL) { 2964 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2965 2966 tap->wt_flags = 0; 2967 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2968 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2969 tap->wt_rate = rinfo->rate; 2970 tap->wt_hwqueue = ac; 2971 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2972 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2973 2974 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2975 } 2976 2977 /* Prepare TX firmware command. */ 2978 cmd = &ring->cmd[ring->cur]; 2979 cmd->code = IWN_CMD_TX_DATA; 2980 cmd->flags = 0; 2981 cmd->qid = ring->qid; 2982 cmd->idx = ring->cur; 2983 2984 tx = (struct iwn_cmd_data *)cmd->data; 2985 /* NB: No need to clear tx, all fields are reinitialized here. */ 2986 tx->scratch = 0; /* clear "scratch" area */ 2987 2988 flags = 0; 2989 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2990 /* Unicast frame, check if an ACK is expected. */ 2991 if (!noack) 2992 flags |= IWN_TX_NEED_ACK; 2993 } 2994 2995 #ifdef notyet 2996 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2997 if ((wh->i_fc[0] & 2998 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2999 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3000 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3001 #endif 3002 3003 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3004 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3005 3006 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3007 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3008 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3009 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 3010 flags |= IWN_TX_NEED_RTS; 3011 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3012 ridx >= IWN_RIDX_OFDM6) { 3013 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3014 flags |= IWN_TX_NEED_CTS; 3015 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3016 flags |= IWN_TX_NEED_RTS; 3017 } 3018 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3019 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3020 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3021 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3022 flags |= IWN_TX_NEED_PROTECTION; 3023 } else 3024 flags |= IWN_TX_FULL_TXOP; 3025 } 3026 } 3027 3028 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3029 type != IEEE80211_FC0_TYPE_DATA) 3030 tx->id = sc->broadcast_id; 3031 else 3032 tx->id = wn->id; 3033 3034 if (type == IEEE80211_FC0_TYPE_MGT) { 3035 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3036 3037 #ifndef IEEE80211_STA_ONLY 3038 /* Tell HW to set timestamp in probe responses. */ 3039 /* XXX NetBSD rev 1.11 added probe requests here but */ 3040 /* probe requests do not take timestamps (from Bergamini). */ 3041 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3042 flags |= IWN_TX_INSERT_TSTAMP; 3043 #endif 3044 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 3045 /* changes here. These are not needed (from Bergamini). */ 3046 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3047 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3048 tx->timeout = htole16(3); 3049 else 3050 tx->timeout = htole16(2); 3051 } else 3052 tx->timeout = htole16(0); 3053 3054 if (hdrlen & 3) { 3055 /* First segment length must be a multiple of 4. */ 3056 flags |= IWN_TX_NEED_PADDING; 3057 pad = 4 - (hdrlen & 3); 3058 } else 3059 pad = 0; 3060 3061 tx->len = htole16(totlen); 3062 tx->tid = tid; 3063 tx->rts_ntries = 60; 3064 tx->data_ntries = 15; 3065 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3066 tx->plcp = rinfo->plcp; 3067 tx->rflags = rinfo->flags; 3068 if (tx->id == sc->broadcast_id) { 3069 /* Group or management frame. */ 3070 tx->linkq = 0; 3071 /* XXX Alternate between antenna A and B? */ 3072 txant = IWN_LSB(sc->txchainmask); 3073 tx->rflags |= IWN_RFLAG_ANT(txant); 3074 } else { 3075 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 3076 flags |= IWN_TX_LINKQ; /* enable MRR */ 3077 } 3078 /* Set physical address of "scratch area". */ 3079 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3080 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3081 3082 /* Copy 802.11 header in TX command. */ 3083 /* XXX NetBSD changed this in rev 1.20 */ 3084 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 3085 3086 /* Trim 802.11 header. */ 3087 m_adj(m, hdrlen); 3088 tx->security = 0; 3089 tx->flags = htole32(flags); 3090 3091 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3092 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3093 if (error != 0) { 3094 if (error != EFBIG) { 3095 aprint_error_dev(sc->sc_dev, 3096 "can't map mbuf (error %d)\n", error); 3097 m_freem(m); 3098 return error; 3099 } 3100 /* Too many DMA segments, linearize mbuf. */ 3101 MGETHDR(m1, M_DONTWAIT, MT_DATA); 3102 if (m1 == NULL) { 3103 m_freem(m); 3104 return ENOBUFS; 3105 } 3106 if (m->m_pkthdr.len > MHLEN) { 3107 MCLGET(m1, M_DONTWAIT); 3108 if (!(m1->m_flags & M_EXT)) { 3109 m_freem(m); 3110 m_freem(m1); 3111 return ENOBUFS; 3112 } 3113 } 3114 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 3115 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3116 m_freem(m); 3117 m = m1; 3118 3119 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3120 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3121 if (error != 0) { 3122 aprint_error_dev(sc->sc_dev, 3123 "can't map mbuf (error %d)\n", error); 3124 m_freem(m); 3125 return error; 3126 } 3127 } 3128 3129 data->m = m; 3130 data->ni = ni; 3131 3132 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3133 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3134 3135 /* Fill TX descriptor. */ 3136 desc->nsegs = 1 + data->map->dm_nsegs; 3137 /* First DMA segment is used by the TX command. */ 3138 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3139 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3140 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3141 /* Other DMA segments are for data payload. */ 3142 seg = data->map->dm_segs; 3143 for (i = 1; i <= data->map->dm_nsegs; i++) { 3144 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3145 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3146 seg->ds_len << 4); 3147 seg++; 3148 } 3149 3150 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3151 BUS_DMASYNC_PREWRITE); 3152 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3153 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3154 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3155 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3156 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3157 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3158 3159 #ifdef notyet 3160 /* Update TX scheduler. */ 3161 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3162 #endif 3163 3164 /* Kick TX ring. */ 3165 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3166 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3167 3168 /* Mark TX ring as full if we reach a certain threshold. */ 3169 if (++ring->queued > IWN_TX_RING_HIMARK) 3170 sc->qfullmsk |= 1 << ring->qid; 3171 3172 return 0; 3173 } 3174 3175 static void 3176 iwn_start(struct ifnet *ifp) 3177 { 3178 struct iwn_softc *sc = ifp->if_softc; 3179 struct ieee80211com *ic = &sc->sc_ic; 3180 struct ieee80211_node *ni; 3181 struct ether_header *eh; 3182 struct mbuf *m; 3183 int ac; 3184 3185 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3186 return; 3187 3188 for (;;) { 3189 if (sc->sc_beacon_wait == 1) { 3190 ifp->if_flags |= IFF_OACTIVE; 3191 break; 3192 } 3193 3194 if (sc->qfullmsk != 0) { 3195 ifp->if_flags |= IFF_OACTIVE; 3196 break; 3197 } 3198 /* Send pending management frames first. */ 3199 IF_DEQUEUE(&ic->ic_mgtq, m); 3200 if (m != NULL) { 3201 ni = M_GETCTX(m, struct ieee80211_node *); 3202 ac = 0; 3203 goto sendit; 3204 } 3205 if (ic->ic_state != IEEE80211_S_RUN) 3206 break; 3207 3208 /* Encapsulate and send data frames. */ 3209 IFQ_DEQUEUE(&ifp->if_snd, m); 3210 if (m == NULL) 3211 break; 3212 if (m->m_len < sizeof (*eh) && 3213 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3214 ifp->if_oerrors++; 3215 continue; 3216 } 3217 eh = mtod(m, struct ether_header *); 3218 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3219 if (ni == NULL) { 3220 m_freem(m); 3221 ifp->if_oerrors++; 3222 continue; 3223 } 3224 /* classify mbuf so we can find which tx ring to use */ 3225 if (ieee80211_classify(ic, m, ni) != 0) { 3226 m_freem(m); 3227 ieee80211_free_node(ni); 3228 ifp->if_oerrors++; 3229 continue; 3230 } 3231 3232 /* No QoS encapsulation for EAPOL frames. */ 3233 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3234 M_WME_GETAC(m) : WME_AC_BE; 3235 3236 if (sc->sc_beacon_wait == 0) 3237 bpf_mtap(ifp, m); 3238 3239 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3240 ieee80211_free_node(ni); 3241 ifp->if_oerrors++; 3242 continue; 3243 } 3244 sendit: 3245 if (sc->sc_beacon_wait) 3246 continue; 3247 3248 bpf_mtap3(ic->ic_rawbpf, m); 3249 3250 if (iwn_tx(sc, m, ni, ac) != 0) { 3251 ieee80211_free_node(ni); 3252 ifp->if_oerrors++; 3253 continue; 3254 } 3255 3256 sc->sc_tx_timer = 5; 3257 ifp->if_timer = 1; 3258 } 3259 3260 if (sc->sc_beacon_wait > 1) 3261 sc->sc_beacon_wait = 0; 3262 } 3263 3264 static void 3265 iwn_watchdog(struct ifnet *ifp) 3266 { 3267 struct iwn_softc *sc = ifp->if_softc; 3268 3269 ifp->if_timer = 0; 3270 3271 if (sc->sc_tx_timer > 0) { 3272 if (--sc->sc_tx_timer == 0) { 3273 aprint_error_dev(sc->sc_dev, 3274 "device timeout\n"); 3275 ifp->if_flags &= ~IFF_UP; 3276 iwn_stop(ifp, 1); 3277 ifp->if_oerrors++; 3278 return; 3279 } 3280 ifp->if_timer = 1; 3281 } 3282 3283 ieee80211_watchdog(&sc->sc_ic); 3284 } 3285 3286 static int 3287 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3288 { 3289 struct iwn_softc *sc = ifp->if_softc; 3290 struct ieee80211com *ic = &sc->sc_ic; 3291 const struct sockaddr *sa; 3292 int s, error = 0; 3293 3294 s = splnet(); 3295 3296 switch (cmd) { 3297 case SIOCSIFADDR: 3298 ifp->if_flags |= IFF_UP; 3299 /* FALLTHROUGH */ 3300 case SIOCSIFFLAGS: 3301 /* XXX Added as it is in every NetBSD driver */ 3302 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3303 break; 3304 if (ifp->if_flags & IFF_UP) { 3305 if (!(ifp->if_flags & IFF_RUNNING)) 3306 error = iwn_init(ifp); 3307 } else { 3308 if (ifp->if_flags & IFF_RUNNING) 3309 iwn_stop(ifp, 1); 3310 } 3311 break; 3312 3313 case SIOCADDMULTI: 3314 case SIOCDELMULTI: 3315 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3316 error = (cmd == SIOCADDMULTI) ? 3317 ether_addmulti(sa, &sc->sc_ec) : 3318 ether_delmulti(sa, &sc->sc_ec); 3319 3320 if (error == ENETRESET) 3321 error = 0; 3322 break; 3323 3324 default: 3325 error = ieee80211_ioctl(ic, cmd, data); 3326 } 3327 3328 if (error == ENETRESET) { 3329 error = 0; 3330 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3331 (IFF_UP | IFF_RUNNING)) { 3332 iwn_stop(ifp, 0); 3333 error = iwn_init(ifp); 3334 } 3335 } 3336 3337 splx(s); 3338 return error; 3339 } 3340 3341 /* 3342 * Send a command to the firmware. 3343 */ 3344 static int 3345 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3346 { 3347 struct iwn_tx_ring *ring = &sc->txq[4]; 3348 struct iwn_tx_desc *desc; 3349 struct iwn_tx_data *data; 3350 struct iwn_tx_cmd *cmd; 3351 struct mbuf *m; 3352 bus_addr_t paddr; 3353 int totlen, error; 3354 3355 desc = &ring->desc[ring->cur]; 3356 data = &ring->data[ring->cur]; 3357 totlen = 4 + size; 3358 3359 if (size > sizeof cmd->data) { 3360 /* Command is too large to fit in a descriptor. */ 3361 if (totlen > MCLBYTES) 3362 return EINVAL; 3363 MGETHDR(m, M_DONTWAIT, MT_DATA); 3364 if (m == NULL) 3365 return ENOMEM; 3366 if (totlen > MHLEN) { 3367 MCLGET(m, M_DONTWAIT); 3368 if (!(m->m_flags & M_EXT)) { 3369 m_freem(m); 3370 return ENOMEM; 3371 } 3372 } 3373 cmd = mtod(m, struct iwn_tx_cmd *); 3374 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3375 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3376 if (error != 0) { 3377 m_freem(m); 3378 return error; 3379 } 3380 data->m = m; 3381 paddr = data->map->dm_segs[0].ds_addr; 3382 } else { 3383 cmd = &ring->cmd[ring->cur]; 3384 paddr = data->cmd_paddr; 3385 } 3386 3387 cmd->code = code; 3388 cmd->flags = 0; 3389 cmd->qid = ring->qid; 3390 cmd->idx = ring->cur; 3391 memcpy(cmd->data, buf, size); 3392 3393 desc->nsegs = 1; 3394 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3395 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3396 3397 if (size > sizeof cmd->data) { 3398 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3399 BUS_DMASYNC_PREWRITE); 3400 } else { 3401 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3402 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3403 totlen, BUS_DMASYNC_PREWRITE); 3404 } 3405 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3406 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3407 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3408 3409 #ifdef notyet 3410 /* Update TX scheduler. */ 3411 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3412 #endif 3413 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3414 3415 /* Kick command ring. */ 3416 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3417 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3418 3419 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3420 } 3421 3422 static int 3423 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3424 { 3425 struct iwn4965_node_info hnode; 3426 char *src, *dst; 3427 3428 /* 3429 * We use the node structure for 5000 Series internally (it is 3430 * a superset of the one for 4965AGN). We thus copy the common 3431 * fields before sending the command. 3432 */ 3433 src = (char *)node; 3434 dst = (char *)&hnode; 3435 memcpy(dst, src, 48); 3436 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3437 memcpy(dst + 48, src + 72, 20); 3438 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3439 } 3440 3441 static int 3442 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3443 { 3444 /* Direct mapping. */ 3445 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3446 } 3447 3448 static int 3449 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3450 { 3451 struct iwn_node *wn = (void *)ni; 3452 struct ieee80211_rateset *rs = &ni->ni_rates; 3453 struct iwn_cmd_link_quality linkq; 3454 const struct iwn_rate *rinfo; 3455 uint8_t txant; 3456 int i, txrate; 3457 3458 /* Use the first valid TX antenna. */ 3459 txant = IWN_LSB(sc->txchainmask); 3460 3461 memset(&linkq, 0, sizeof linkq); 3462 linkq.id = wn->id; 3463 linkq.antmsk_1stream = txant; 3464 linkq.antmsk_2stream = IWN_ANT_AB; 3465 linkq.ampdu_max = 31; 3466 linkq.ampdu_threshold = 3; 3467 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3468 3469 /* Start at highest available bit-rate. */ 3470 txrate = rs->rs_nrates - 1; 3471 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3472 rinfo = &iwn_rates[wn->ridx[txrate]]; 3473 linkq.retry[i].plcp = rinfo->plcp; 3474 linkq.retry[i].rflags = rinfo->flags; 3475 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3476 /* Next retry at immediate lower bit-rate. */ 3477 if (txrate > 0) 3478 txrate--; 3479 } 3480 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3481 } 3482 3483 /* 3484 * Broadcast node is used to send group-addressed and management frames. 3485 */ 3486 static int 3487 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3488 { 3489 struct iwn_ops *ops = &sc->ops; 3490 struct iwn_node_info node; 3491 struct iwn_cmd_link_quality linkq; 3492 const struct iwn_rate *rinfo; 3493 uint8_t txant; 3494 int i, error; 3495 3496 memset(&node, 0, sizeof node); 3497 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3498 node.id = sc->broadcast_id; 3499 DPRINTF(("adding broadcast node\n")); 3500 if ((error = ops->add_node(sc, &node, async)) != 0) 3501 return error; 3502 3503 /* Use the first valid TX antenna. */ 3504 txant = IWN_LSB(sc->txchainmask); 3505 3506 memset(&linkq, 0, sizeof linkq); 3507 linkq.id = sc->broadcast_id; 3508 linkq.antmsk_1stream = txant; 3509 linkq.antmsk_2stream = IWN_ANT_AB; 3510 linkq.ampdu_max = 64; 3511 linkq.ampdu_threshold = 3; 3512 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3513 3514 /* Use lowest mandatory bit-rate. */ 3515 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3516 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3517 linkq.retry[0].plcp = rinfo->plcp; 3518 linkq.retry[0].rflags = rinfo->flags; 3519 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3520 /* Use same bit-rate for all TX retries. */ 3521 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3522 linkq.retry[i].plcp = linkq.retry[0].plcp; 3523 linkq.retry[i].rflags = linkq.retry[0].rflags; 3524 } 3525 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3526 } 3527 3528 static void 3529 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3530 { 3531 struct iwn_cmd_led led; 3532 3533 /* Clear microcode LED ownership. */ 3534 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3535 3536 led.which = which; 3537 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3538 led.off = off; 3539 led.on = on; 3540 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3541 } 3542 3543 /* 3544 * Set the critical temperature at which the firmware will stop the radio 3545 * and notify us. 3546 */ 3547 static int 3548 iwn_set_critical_temp(struct iwn_softc *sc) 3549 { 3550 struct iwn_critical_temp crit; 3551 int32_t temp; 3552 3553 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3554 3555 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3556 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3557 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3558 temp = IWN_CTOK(110); 3559 else 3560 temp = 110; 3561 memset(&crit, 0, sizeof crit); 3562 crit.tempR = htole32(temp); 3563 DPRINTF(("setting critical temperature to %d\n", temp)); 3564 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3565 } 3566 3567 static int 3568 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3569 { 3570 struct iwn_cmd_timing cmd; 3571 uint64_t val, mod; 3572 3573 memset(&cmd, 0, sizeof cmd); 3574 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3575 cmd.bintval = htole16(ni->ni_intval); 3576 cmd.lintval = htole16(10); 3577 3578 /* Compute remaining time until next beacon. */ 3579 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3580 mod = le64toh(cmd.tstamp) % val; 3581 cmd.binitval = htole32((uint32_t)(val - mod)); 3582 3583 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3584 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3585 3586 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3587 } 3588 3589 static void 3590 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3591 { 3592 /* Adjust TX power if need be (delta >= 3 degC). */ 3593 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3594 if (abs(temp - sc->temp) >= 3) { 3595 /* Record temperature of last calibration. */ 3596 sc->temp = temp; 3597 (void)iwn4965_set_txpower(sc, 1); 3598 } 3599 } 3600 3601 /* 3602 * Set TX power for current channel (each rate has its own power settings). 3603 * This function takes into account the regulatory information from EEPROM, 3604 * the current temperature and the current voltage. 3605 */ 3606 static int 3607 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3608 { 3609 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3610 #define fdivround(a, b, n) \ 3611 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3612 /* Linear interpolation. */ 3613 #define interpolate(x, x1, y1, x2, y2, n) \ 3614 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3615 3616 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3617 struct ieee80211com *ic = &sc->sc_ic; 3618 struct iwn_ucode_info *uc = &sc->ucode_info; 3619 struct ieee80211_channel *ch; 3620 struct iwn4965_cmd_txpower cmd; 3621 struct iwn4965_eeprom_chan_samples *chans; 3622 const uint8_t *rf_gain, *dsp_gain; 3623 int32_t vdiff, tdiff; 3624 int i, c, grp, maxpwr; 3625 uint8_t chan; 3626 3627 /* Retrieve current channel from last RXON. */ 3628 chan = sc->rxon.chan; 3629 DPRINTF(("setting TX power for channel %d\n", chan)); 3630 ch = &ic->ic_channels[chan]; 3631 3632 memset(&cmd, 0, sizeof cmd); 3633 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3634 cmd.chan = chan; 3635 3636 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3637 maxpwr = sc->maxpwr5GHz; 3638 rf_gain = iwn4965_rf_gain_5ghz; 3639 dsp_gain = iwn4965_dsp_gain_5ghz; 3640 } else { 3641 maxpwr = sc->maxpwr2GHz; 3642 rf_gain = iwn4965_rf_gain_2ghz; 3643 dsp_gain = iwn4965_dsp_gain_2ghz; 3644 } 3645 3646 /* Compute voltage compensation. */ 3647 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3648 if (vdiff > 0) 3649 vdiff *= 2; 3650 if (abs(vdiff) > 2) 3651 vdiff = 0; 3652 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3653 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3654 3655 /* Get channel attenuation group. */ 3656 if (chan <= 20) /* 1-20 */ 3657 grp = 4; 3658 else if (chan <= 43) /* 34-43 */ 3659 grp = 0; 3660 else if (chan <= 70) /* 44-70 */ 3661 grp = 1; 3662 else if (chan <= 124) /* 71-124 */ 3663 grp = 2; 3664 else /* 125-200 */ 3665 grp = 3; 3666 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3667 3668 /* Get channel sub-band. */ 3669 for (i = 0; i < IWN_NBANDS; i++) 3670 if (sc->bands[i].lo != 0 && 3671 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3672 break; 3673 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3674 return EINVAL; 3675 chans = sc->bands[i].chans; 3676 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3677 3678 for (c = 0; c < 2; c++) { 3679 uint8_t power, gain, temp; 3680 int maxchpwr, pwr, ridx, idx; 3681 3682 power = interpolate(chan, 3683 chans[0].num, chans[0].samples[c][1].power, 3684 chans[1].num, chans[1].samples[c][1].power, 1); 3685 gain = interpolate(chan, 3686 chans[0].num, chans[0].samples[c][1].gain, 3687 chans[1].num, chans[1].samples[c][1].gain, 1); 3688 temp = interpolate(chan, 3689 chans[0].num, chans[0].samples[c][1].temp, 3690 chans[1].num, chans[1].samples[c][1].temp, 1); 3691 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3692 c, power, gain, temp)); 3693 3694 /* Compute temperature compensation. */ 3695 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3696 DPRINTF(("temperature compensation=%d (current=%d, " 3697 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3698 3699 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3700 /* Convert dBm to half-dBm. */ 3701 maxchpwr = sc->maxpwr[chan] * 2; 3702 if ((ridx / 8) & 1) 3703 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3704 3705 pwr = maxpwr; 3706 3707 /* Adjust TX power based on rate. */ 3708 if ((ridx % 8) == 5) 3709 pwr -= 15; /* OFDM48: -7.5dB */ 3710 else if ((ridx % 8) == 6) 3711 pwr -= 17; /* OFDM54: -8.5dB */ 3712 else if ((ridx % 8) == 7) 3713 pwr -= 20; /* OFDM60: -10dB */ 3714 else 3715 pwr -= 10; /* Others: -5dB */ 3716 3717 /* Do not exceed channel max TX power. */ 3718 if (pwr > maxchpwr) 3719 pwr = maxchpwr; 3720 3721 idx = gain - (pwr - power) - tdiff - vdiff; 3722 if ((ridx / 8) & 1) /* MIMO */ 3723 idx += (int32_t)le32toh(uc->atten[grp][c]); 3724 3725 if (cmd.band == 0) 3726 idx += 9; /* 5GHz */ 3727 if (ridx == IWN_RIDX_MAX) 3728 idx += 5; /* CCK */ 3729 3730 /* Make sure idx stays in a valid range. */ 3731 if (idx < 0) 3732 idx = 0; 3733 else if (idx > IWN4965_MAX_PWR_INDEX) 3734 idx = IWN4965_MAX_PWR_INDEX; 3735 3736 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3737 c, ridx, idx)); 3738 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3739 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3740 } 3741 } 3742 3743 DPRINTF(("setting TX power for chan %d\n", chan)); 3744 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3745 3746 #undef interpolate 3747 #undef fdivround 3748 } 3749 3750 static int 3751 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3752 { 3753 struct iwn5000_cmd_txpower cmd; 3754 int cmdid; 3755 3756 /* 3757 * TX power calibration is handled automatically by the firmware 3758 * for 5000 Series. 3759 */ 3760 memset(&cmd, 0, sizeof cmd); 3761 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3762 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3763 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3764 DPRINTF(("setting TX power\n")); 3765 if (IWN_UCODE_API(sc->ucode_rev) == 1) 3766 cmdid = IWN_CMD_TXPOWER_DBM_V1; 3767 else 3768 cmdid = IWN_CMD_TXPOWER_DBM; 3769 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 3770 } 3771 3772 /* 3773 * Retrieve the maximum RSSI (in dBm) among receivers. 3774 */ 3775 static int 3776 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3777 { 3778 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3779 uint8_t mask, agc; 3780 int rssi; 3781 3782 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3783 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3784 3785 rssi = 0; 3786 if (mask & IWN_ANT_A) 3787 rssi = MAX(rssi, phy->rssi[0]); 3788 if (mask & IWN_ANT_B) 3789 rssi = MAX(rssi, phy->rssi[2]); 3790 if (mask & IWN_ANT_C) 3791 rssi = MAX(rssi, phy->rssi[4]); 3792 3793 return rssi - agc - IWN_RSSI_TO_DBM; 3794 } 3795 3796 static int 3797 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3798 { 3799 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3800 uint8_t agc; 3801 int rssi; 3802 3803 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3804 3805 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3806 le16toh(phy->rssi[1]) & 0xff); 3807 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3808 3809 return rssi - agc - IWN_RSSI_TO_DBM; 3810 } 3811 3812 /* 3813 * Retrieve the average noise (in dBm) among receivers. 3814 */ 3815 static int 3816 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3817 { 3818 int i, total, nbant, noise; 3819 3820 total = nbant = 0; 3821 for (i = 0; i < 3; i++) { 3822 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3823 continue; 3824 total += noise; 3825 nbant++; 3826 } 3827 /* There should be at least one antenna but check anyway. */ 3828 return (nbant == 0) ? -127 : (total / nbant) - 107; 3829 } 3830 3831 /* 3832 * Compute temperature (in degC) from last received statistics. 3833 */ 3834 static int 3835 iwn4965_get_temperature(struct iwn_softc *sc) 3836 { 3837 struct iwn_ucode_info *uc = &sc->ucode_info; 3838 int32_t r1, r2, r3, r4, temp; 3839 3840 r1 = le32toh(uc->temp[0].chan20MHz); 3841 r2 = le32toh(uc->temp[1].chan20MHz); 3842 r3 = le32toh(uc->temp[2].chan20MHz); 3843 r4 = le32toh(sc->rawtemp); 3844 3845 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3846 return 0; 3847 3848 /* Sign-extend 23-bit R4 value to 32-bit. */ 3849 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3850 /* Compute temperature in Kelvin. */ 3851 temp = (259 * (r4 - r2)) / (r3 - r1); 3852 temp = (temp * 97) / 100 + 8; 3853 3854 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3855 return IWN_KTOC(temp); 3856 } 3857 3858 static int 3859 iwn5000_get_temperature(struct iwn_softc *sc) 3860 { 3861 int32_t temp; 3862 3863 /* 3864 * Temperature is not used by the driver for 5000 Series because 3865 * TX power calibration is handled by firmware. We export it to 3866 * users through the sensor framework though. 3867 */ 3868 temp = le32toh(sc->rawtemp); 3869 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3870 temp = (temp / -5) + sc->temp_off; 3871 temp = IWN_KTOC(temp); 3872 } 3873 return temp; 3874 } 3875 3876 /* 3877 * Initialize sensitivity calibration state machine. 3878 */ 3879 static int 3880 iwn_init_sensitivity(struct iwn_softc *sc) 3881 { 3882 struct iwn_ops *ops = &sc->ops; 3883 struct iwn_calib_state *calib = &sc->calib; 3884 uint32_t flags; 3885 int error; 3886 3887 /* Reset calibration state machine. */ 3888 memset(calib, 0, sizeof (*calib)); 3889 calib->state = IWN_CALIB_STATE_INIT; 3890 calib->cck_state = IWN_CCK_STATE_HIFA; 3891 /* Set initial correlation values. */ 3892 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3893 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3894 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3895 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3896 calib->cck_x4 = 125; 3897 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3898 calib->energy_cck = sc->limits->energy_cck; 3899 3900 /* Write initial sensitivity. */ 3901 if ((error = iwn_send_sensitivity(sc)) != 0) 3902 return error; 3903 3904 /* Write initial gains. */ 3905 if ((error = ops->init_gains(sc)) != 0) 3906 return error; 3907 3908 /* Request statistics at each beacon interval. */ 3909 flags = 0; 3910 DPRINTF(("sending request for statistics\n")); 3911 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3912 } 3913 3914 /* 3915 * Collect noise and RSSI statistics for the first 20 beacons received 3916 * after association and use them to determine connected antennas and 3917 * to set differential gains. 3918 */ 3919 static void 3920 iwn_collect_noise(struct iwn_softc *sc, 3921 const struct iwn_rx_general_stats *stats) 3922 { 3923 struct iwn_ops *ops = &sc->ops; 3924 struct iwn_calib_state *calib = &sc->calib; 3925 uint32_t val; 3926 int i; 3927 3928 /* Accumulate RSSI and noise for all 3 antennas. */ 3929 for (i = 0; i < 3; i++) { 3930 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3931 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3932 } 3933 /* NB: We update differential gains only once after 20 beacons. */ 3934 if (++calib->nbeacons < 20) 3935 return; 3936 3937 /* Determine highest average RSSI. */ 3938 val = MAX(calib->rssi[0], calib->rssi[1]); 3939 val = MAX(calib->rssi[2], val); 3940 3941 /* Determine which antennas are connected. */ 3942 sc->chainmask = sc->rxchainmask; 3943 for (i = 0; i < 3; i++) 3944 if (val - calib->rssi[i] > 15 * 20) 3945 sc->chainmask &= ~(1 << i); 3946 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3947 sc->rxchainmask, sc->chainmask)); 3948 3949 /* If none of the TX antennas are connected, keep at least one. */ 3950 if ((sc->chainmask & sc->txchainmask) == 0) 3951 sc->chainmask |= IWN_LSB(sc->txchainmask); 3952 3953 (void)ops->set_gains(sc); 3954 calib->state = IWN_CALIB_STATE_RUN; 3955 3956 #ifdef notyet 3957 /* XXX Disable RX chains with no antennas connected. */ 3958 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3959 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3960 #endif 3961 3962 /* Enable power-saving mode if requested by user. */ 3963 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3964 (void)iwn_set_pslevel(sc, 0, 3, 1); 3965 } 3966 3967 static int 3968 iwn4965_init_gains(struct iwn_softc *sc) 3969 { 3970 struct iwn_phy_calib_gain cmd; 3971 3972 memset(&cmd, 0, sizeof cmd); 3973 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3974 /* Differential gains initially set to 0 for all 3 antennas. */ 3975 DPRINTF(("setting initial differential gains\n")); 3976 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3977 } 3978 3979 static int 3980 iwn5000_init_gains(struct iwn_softc *sc) 3981 { 3982 struct iwn_phy_calib cmd; 3983 3984 memset(&cmd, 0, sizeof cmd); 3985 cmd.code = sc->reset_noise_gain; 3986 cmd.ngroups = 1; 3987 cmd.isvalid = 1; 3988 DPRINTF(("setting initial differential gains\n")); 3989 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3990 } 3991 3992 static int 3993 iwn4965_set_gains(struct iwn_softc *sc) 3994 { 3995 struct iwn_calib_state *calib = &sc->calib; 3996 struct iwn_phy_calib_gain cmd; 3997 int i, delta, noise; 3998 3999 /* Get minimal noise among connected antennas. */ 4000 noise = INT_MAX; /* NB: There's at least one antenna. */ 4001 for (i = 0; i < 3; i++) 4002 if (sc->chainmask & (1 << i)) 4003 noise = MIN(calib->noise[i], noise); 4004 4005 memset(&cmd, 0, sizeof cmd); 4006 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4007 /* Set differential gains for connected antennas. */ 4008 for (i = 0; i < 3; i++) { 4009 if (sc->chainmask & (1 << i)) { 4010 /* Compute attenuation (in unit of 1.5dB). */ 4011 delta = (noise - (int32_t)calib->noise[i]) / 30; 4012 /* NB: delta <= 0 */ 4013 /* Limit to [-4.5dB,0]. */ 4014 cmd.gain[i] = MIN(abs(delta), 3); 4015 if (delta < 0) 4016 cmd.gain[i] |= 1 << 2; /* sign bit */ 4017 } 4018 } 4019 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4020 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 4021 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4022 } 4023 4024 static int 4025 iwn5000_set_gains(struct iwn_softc *sc) 4026 { 4027 struct iwn_calib_state *calib = &sc->calib; 4028 struct iwn_phy_calib_gain cmd; 4029 int i, ant, div, delta; 4030 4031 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4032 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4033 4034 memset(&cmd, 0, sizeof cmd); 4035 cmd.code = sc->noise_gain; 4036 cmd.ngroups = 1; 4037 cmd.isvalid = 1; 4038 /* Get first available RX antenna as referential. */ 4039 ant = IWN_LSB(sc->rxchainmask); 4040 /* Set differential gains for other antennas. */ 4041 for (i = ant + 1; i < 3; i++) { 4042 if (sc->chainmask & (1 << i)) { 4043 /* The delta is relative to antenna "ant". */ 4044 delta = ((int32_t)calib->noise[ant] - 4045 (int32_t)calib->noise[i]) / div; 4046 /* Limit to [-4.5dB,+4.5dB]. */ 4047 cmd.gain[i - 1] = MIN(abs(delta), 3); 4048 if (delta < 0) 4049 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4050 } 4051 } 4052 DPRINTF(("setting differential gains: %x/%x (%x)\n", 4053 cmd.gain[0], cmd.gain[1], sc->chainmask)); 4054 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4055 } 4056 4057 /* 4058 * Tune RF RX sensitivity based on the number of false alarms detected 4059 * during the last beacon period. 4060 */ 4061 static void 4062 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4063 { 4064 #define inc(val, inc, max) \ 4065 if ((val) < (max)) { \ 4066 if ((val) < (max) - (inc)) \ 4067 (val) += (inc); \ 4068 else \ 4069 (val) = (max); \ 4070 needs_update = 1; \ 4071 } 4072 #define dec(val, dec, min) \ 4073 if ((val) > (min)) { \ 4074 if ((val) > (min) + (dec)) \ 4075 (val) -= (dec); \ 4076 else \ 4077 (val) = (min); \ 4078 needs_update = 1; \ 4079 } 4080 4081 const struct iwn_sensitivity_limits *limits = sc->limits; 4082 struct iwn_calib_state *calib = &sc->calib; 4083 uint32_t val, rxena, fa; 4084 uint32_t energy[3], energy_min; 4085 uint8_t noise[3], noise_ref; 4086 int i, needs_update = 0; 4087 4088 /* Check that we've been enabled long enough. */ 4089 if ((rxena = le32toh(stats->general.load)) == 0) 4090 return; 4091 4092 /* Compute number of false alarms since last call for OFDM. */ 4093 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4094 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4095 fa *= 200 * 1024; /* 200TU */ 4096 4097 /* Save counters values for next call. */ 4098 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4099 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4100 4101 if (fa > 50 * rxena) { 4102 /* High false alarm count, decrease sensitivity. */ 4103 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4104 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4105 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4106 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4107 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4108 4109 } else if (fa < 5 * rxena) { 4110 /* Low false alarm count, increase sensitivity. */ 4111 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4112 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4113 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4114 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4115 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4116 } 4117 4118 /* Compute maximum noise among 3 receivers. */ 4119 for (i = 0; i < 3; i++) 4120 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4121 val = MAX(noise[0], noise[1]); 4122 val = MAX(noise[2], val); 4123 /* Insert it into our samples table. */ 4124 calib->noise_samples[calib->cur_noise_sample] = val; 4125 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4126 4127 /* Compute maximum noise among last 20 samples. */ 4128 noise_ref = calib->noise_samples[0]; 4129 for (i = 1; i < 20; i++) 4130 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4131 4132 /* Compute maximum energy among 3 receivers. */ 4133 for (i = 0; i < 3; i++) 4134 energy[i] = le32toh(stats->general.energy[i]); 4135 val = MIN(energy[0], energy[1]); 4136 val = MIN(energy[2], val); 4137 /* Insert it into our samples table. */ 4138 calib->energy_samples[calib->cur_energy_sample] = val; 4139 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4140 4141 /* Compute minimum energy among last 10 samples. */ 4142 energy_min = calib->energy_samples[0]; 4143 for (i = 1; i < 10; i++) 4144 energy_min = MAX(energy_min, calib->energy_samples[i]); 4145 energy_min += 6; 4146 4147 /* Compute number of false alarms since last call for CCK. */ 4148 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4149 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4150 fa *= 200 * 1024; /* 200TU */ 4151 4152 /* Save counters values for next call. */ 4153 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4154 calib->fa_cck = le32toh(stats->cck.fa); 4155 4156 if (fa > 50 * rxena) { 4157 /* High false alarm count, decrease sensitivity. */ 4158 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4159 calib->cck_state = IWN_CCK_STATE_HIFA; 4160 calib->low_fa = 0; 4161 4162 if (calib->cck_x4 > 160) { 4163 calib->noise_ref = noise_ref; 4164 if (calib->energy_cck > 2) 4165 dec(calib->energy_cck, 2, energy_min); 4166 } 4167 if (calib->cck_x4 < 160) { 4168 calib->cck_x4 = 161; 4169 needs_update = 1; 4170 } else 4171 inc(calib->cck_x4, 3, limits->max_cck_x4); 4172 4173 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4174 4175 } else if (fa < 5 * rxena) { 4176 /* Low false alarm count, increase sensitivity. */ 4177 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4178 calib->cck_state = IWN_CCK_STATE_LOFA; 4179 calib->low_fa++; 4180 4181 if (calib->cck_state != IWN_CCK_STATE_INIT && 4182 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4183 calib->low_fa > 100)) { 4184 inc(calib->energy_cck, 2, limits->min_energy_cck); 4185 dec(calib->cck_x4, 3, limits->min_cck_x4); 4186 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4187 } 4188 } else { 4189 /* Not worth to increase or decrease sensitivity. */ 4190 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4191 calib->low_fa = 0; 4192 calib->noise_ref = noise_ref; 4193 4194 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4195 /* Previous interval had many false alarms. */ 4196 dec(calib->energy_cck, 8, energy_min); 4197 } 4198 calib->cck_state = IWN_CCK_STATE_INIT; 4199 } 4200 4201 if (needs_update) 4202 (void)iwn_send_sensitivity(sc); 4203 #undef dec 4204 #undef inc 4205 } 4206 4207 static int 4208 iwn_send_sensitivity(struct iwn_softc *sc) 4209 { 4210 struct iwn_calib_state *calib = &sc->calib; 4211 struct iwn_enhanced_sensitivity_cmd cmd; 4212 int len; 4213 4214 memset(&cmd, 0, sizeof cmd); 4215 len = sizeof (struct iwn_sensitivity_cmd); 4216 cmd.which = IWN_SENSITIVITY_WORKTBL; 4217 /* OFDM modulation. */ 4218 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4219 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4220 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4221 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4222 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4223 cmd.energy_ofdm_th = htole16(62); 4224 /* CCK modulation. */ 4225 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4226 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4227 cmd.energy_cck = htole16(calib->energy_cck); 4228 /* Barker modulation: use default values. */ 4229 cmd.corr_barker = htole16(190); 4230 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 4231 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4232 goto send; 4233 /* Enhanced sensitivity settings. */ 4234 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4235 cmd.ofdm_det_slope_mrc = htole16(668); 4236 cmd.ofdm_det_icept_mrc = htole16(4); 4237 cmd.ofdm_det_slope = htole16(486); 4238 cmd.ofdm_det_icept = htole16(37); 4239 cmd.cck_det_slope_mrc = htole16(853); 4240 cmd.cck_det_icept_mrc = htole16(4); 4241 cmd.cck_det_slope = htole16(476); 4242 cmd.cck_det_icept = htole16(99); 4243 send: 4244 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4245 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4246 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4247 calib->energy_cck)); 4248 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4249 } 4250 4251 /* 4252 * Set STA mode power saving level (between 0 and 5). 4253 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4254 */ 4255 static int 4256 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4257 { 4258 struct iwn_pmgt_cmd cmd; 4259 const struct iwn_pmgt *pmgt; 4260 uint32_t maxp, skip_dtim; 4261 pcireg_t reg; 4262 int i; 4263 4264 /* Select which PS parameters to use. */ 4265 if (dtim <= 2) 4266 pmgt = &iwn_pmgt[0][level]; 4267 else if (dtim <= 10) 4268 pmgt = &iwn_pmgt[1][level]; 4269 else 4270 pmgt = &iwn_pmgt[2][level]; 4271 4272 memset(&cmd, 0, sizeof cmd); 4273 if (level != 0) /* not CAM */ 4274 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4275 if (level == 5) 4276 cmd.flags |= htole16(IWN_PS_FAST_PD); 4277 /* Retrieve PCIe Active State Power Management (ASPM). */ 4278 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4279 sc->sc_cap_off + PCIE_LCSR); 4280 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4281 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4282 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4283 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4284 4285 if (dtim == 0) { 4286 dtim = 1; 4287 skip_dtim = 0; 4288 } else 4289 skip_dtim = pmgt->skip_dtim; 4290 if (skip_dtim != 0) { 4291 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4292 maxp = pmgt->intval[4]; 4293 if (maxp == (uint32_t)-1) 4294 maxp = dtim * (skip_dtim + 1); 4295 else if (maxp > dtim) 4296 maxp = (maxp / dtim) * dtim; 4297 } else 4298 maxp = dtim; 4299 for (i = 0; i < 5; i++) 4300 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4301 4302 DPRINTF(("setting power saving level to %d\n", level)); 4303 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4304 } 4305 4306 int 4307 iwn5000_runtime_calib(struct iwn_softc *sc) 4308 { 4309 struct iwn5000_calib_config cmd; 4310 4311 memset(&cmd, 0, sizeof cmd); 4312 cmd.ucode.once.enable = 0xffffffff; 4313 cmd.ucode.once.start = IWN5000_CALIB_DC; 4314 DPRINTF(("configuring runtime calibration\n")); 4315 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4316 } 4317 4318 static int 4319 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc) 4320 { 4321 struct iwn_bluetooth bluetooth; 4322 4323 memset(&bluetooth, 0, sizeof bluetooth); 4324 bluetooth.flags = IWN_BT_COEX_ENABLE; 4325 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4326 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4327 4328 DPRINTF(("configuring bluetooth coexistence\n")); 4329 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4330 } 4331 4332 static int 4333 iwn_config_bt_coex_prio_table(struct iwn_softc *sc) 4334 { 4335 uint8_t prio_table[16]; 4336 4337 memset(&prio_table, 0, sizeof prio_table); 4338 prio_table[ 0] = 6; /* init calibration 1 */ 4339 prio_table[ 1] = 7; /* init calibration 2 */ 4340 prio_table[ 2] = 2; /* periodic calib low 1 */ 4341 prio_table[ 3] = 3; /* periodic calib low 2 */ 4342 prio_table[ 4] = 4; /* periodic calib high 1 */ 4343 prio_table[ 5] = 5; /* periodic calib high 2 */ 4344 prio_table[ 6] = 6; /* dtim */ 4345 prio_table[ 7] = 8; /* scan52 */ 4346 prio_table[ 8] = 10; /* scan24 */ 4347 4348 DPRINTF(("sending priority lookup table\n")); 4349 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE, 4350 &prio_table, sizeof prio_table, 0); 4351 } 4352 4353 static int 4354 iwn_config_bt_coex_adv_config(struct iwn_softc *sc, struct iwn_bt_basic *basic, 4355 size_t len) 4356 { 4357 struct iwn_btcoex_prot btprot; 4358 int error; 4359 4360 basic->bt.flags = IWN_BT_COEX_ENABLE; 4361 basic->bt.lead_time = IWN_BT_LEAD_TIME_DEF; 4362 basic->bt.max_kill = IWN_BT_MAX_KILL_DEF; 4363 basic->bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF; 4364 basic->bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF; 4365 basic->bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF; 4366 basic->bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF; 4367 basic->bt3_timer_t2_value = IWN_BT_BT3_T2_DEF; 4368 basic->bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */ 4369 basic->bt3_lookup_table[ 1] = htole32(0xaaaaaaaa); 4370 basic->bt3_lookup_table[ 2] = htole32(0xaeaaaaaa); 4371 basic->bt3_lookup_table[ 3] = htole32(0xaaaaaaaa); 4372 basic->bt3_lookup_table[ 4] = htole32(0xcc00ff28); 4373 basic->bt3_lookup_table[ 5] = htole32(0x0000aaaa); 4374 basic->bt3_lookup_table[ 6] = htole32(0xcc00aaaa); 4375 basic->bt3_lookup_table[ 7] = htole32(0x0000aaaa); 4376 basic->bt3_lookup_table[ 8] = htole32(0xc0004000); 4377 basic->bt3_lookup_table[ 9] = htole32(0x00004000); 4378 basic->bt3_lookup_table[10] = htole32(0xf0005000); 4379 basic->bt3_lookup_table[11] = htole32(0xf0005000); 4380 basic->reduce_txpower = 0; /* as not implemented */ 4381 basic->valid = IWN_BT_ALL_VALID_MASK; 4382 4383 DPRINTF(("configuring advanced bluetooth coexistence v1\n")); 4384 error = iwn_cmd(sc, IWN_CMD_BT_COEX, basic, len, 0); 4385 if (error != 0) { 4386 aprint_error_dev(sc->sc_dev, 4387 "could not configure advanced bluetooth coexistence\n"); 4388 return error; 4389 } 4390 4391 error = iwn_config_bt_coex_prio_table(sc); 4392 if (error != 0) { 4393 aprint_error_dev(sc->sc_dev, 4394 "could not configure send BT priority table\n"); 4395 return error; 4396 } 4397 4398 /* Force BT state machine change */ 4399 memset(&btprot, 0, sizeof btprot); 4400 btprot.open = 1; 4401 btprot.type = 1; 4402 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4403 if (error != 0) { 4404 aprint_error_dev(sc->sc_dev, "could not open BT protcol\n"); 4405 return error; 4406 } 4407 4408 btprot.open = 0; 4409 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4410 if (error != 0) { 4411 aprint_error_dev(sc->sc_dev, "could not close BT protcol\n"); 4412 return error; 4413 } 4414 return 0; 4415 } 4416 4417 static int 4418 iwn_config_bt_coex_adv1(struct iwn_softc *sc) 4419 { 4420 struct iwn_bt_adv1 d; 4421 4422 memset(&d, 0, sizeof d); 4423 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4424 d.tx_prio_boost = 0; 4425 d.rx_prio_boost = 0; 4426 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4427 } 4428 4429 static int 4430 iwn_config_bt_coex_adv2(struct iwn_softc *sc) 4431 { 4432 struct iwn_bt_adv2 d; 4433 4434 memset(&d, 0, sizeof d); 4435 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4436 d.tx_prio_boost = 0; 4437 d.rx_prio_boost = 0; 4438 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4439 } 4440 4441 static int 4442 iwn_config(struct iwn_softc *sc) 4443 { 4444 struct iwn_ops *ops = &sc->ops; 4445 struct ieee80211com *ic = &sc->sc_ic; 4446 struct ifnet *ifp = ic->ic_ifp; 4447 uint32_t txmask; 4448 uint16_t rxchain; 4449 int error; 4450 4451 error = ops->config_bt_coex(sc); 4452 if (error != 0) { 4453 aprint_error_dev(sc->sc_dev, 4454 "could not configure bluetooth coexistence\n"); 4455 return error; 4456 } 4457 4458 /* Set radio temperature sensor offset. */ 4459 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4460 error = iwn6000_temp_offset_calib(sc); 4461 if (error != 0) { 4462 aprint_error_dev(sc->sc_dev, 4463 "could not set temperature offset\n"); 4464 return error; 4465 } 4466 } 4467 4468 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4469 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4470 sc->hw_type == IWN_HW_REV_TYPE_135 || 4471 sc->hw_type == IWN_HW_REV_TYPE_105) { 4472 error = iwn2000_temp_offset_calib(sc); 4473 if (error != 0) { 4474 aprint_error_dev(sc->sc_dev, 4475 "could not set temperature offset\n"); 4476 return error; 4477 } 4478 } 4479 4480 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4481 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4482 /* Configure runtime DC calibration. */ 4483 error = iwn5000_runtime_calib(sc); 4484 if (error != 0) { 4485 aprint_error_dev(sc->sc_dev, 4486 "could not configure runtime calibration\n"); 4487 return error; 4488 } 4489 } 4490 4491 /* Configure valid TX chains for 5000 Series. */ 4492 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4493 txmask = htole32(sc->txchainmask); 4494 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4495 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4496 sizeof txmask, 0); 4497 if (error != 0) { 4498 aprint_error_dev(sc->sc_dev, 4499 "could not configure valid TX chains\n"); 4500 return error; 4501 } 4502 } 4503 4504 /* Set mode, channel, RX filter and enable RX. */ 4505 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4506 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4507 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4508 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4509 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4510 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4511 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4512 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4513 switch (ic->ic_opmode) { 4514 case IEEE80211_M_STA: 4515 sc->rxon.mode = IWN_MODE_STA; 4516 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4517 break; 4518 case IEEE80211_M_MONITOR: 4519 sc->rxon.mode = IWN_MODE_MONITOR; 4520 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4521 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4522 break; 4523 default: 4524 /* Should not get there. */ 4525 break; 4526 } 4527 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4528 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4529 sc->rxon.ht_single_mask = 0xff; 4530 sc->rxon.ht_dual_mask = 0xff; 4531 sc->rxon.ht_triple_mask = 0xff; 4532 rxchain = 4533 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4534 IWN_RXCHAIN_MIMO_COUNT(2) | 4535 IWN_RXCHAIN_IDLE_COUNT(2); 4536 sc->rxon.rxchain = htole16(rxchain); 4537 DPRINTF(("setting configuration\n")); 4538 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4539 if (error != 0) { 4540 aprint_error_dev(sc->sc_dev, 4541 "RXON command failed\n"); 4542 return error; 4543 } 4544 4545 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4546 aprint_error_dev(sc->sc_dev, 4547 "could not add broadcast node\n"); 4548 return error; 4549 } 4550 4551 /* Configuration has changed, set TX power accordingly. */ 4552 if ((error = ops->set_txpower(sc, 0)) != 0) { 4553 aprint_error_dev(sc->sc_dev, 4554 "could not set TX power\n"); 4555 return error; 4556 } 4557 4558 if ((error = iwn_set_critical_temp(sc)) != 0) { 4559 aprint_error_dev(sc->sc_dev, 4560 "could not set critical temperature\n"); 4561 return error; 4562 } 4563 4564 /* Set power saving level to CAM during initialization. */ 4565 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4566 aprint_error_dev(sc->sc_dev, 4567 "could not set power saving level\n"); 4568 return error; 4569 } 4570 return 0; 4571 } 4572 4573 static uint16_t 4574 iwn_get_active_dwell_time(struct iwn_softc *sc, uint16_t flags, 4575 uint8_t n_probes) 4576 { 4577 /* No channel? Default to 2GHz settings */ 4578 if (flags & IEEE80211_CHAN_2GHZ) 4579 return IWN_ACTIVE_DWELL_TIME_2GHZ + 4580 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1); 4581 4582 /* 5GHz dwell time */ 4583 return IWN_ACTIVE_DWELL_TIME_5GHZ + 4584 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1); 4585 } 4586 4587 /* 4588 * Limit the total dwell time to 85% of the beacon interval. 4589 * 4590 * Returns the dwell time in milliseconds. 4591 */ 4592 static uint16_t 4593 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 4594 { 4595 struct ieee80211com *ic = &sc->sc_ic; 4596 struct ieee80211_node *ni = ic->ic_bss; 4597 int bintval = 0; 4598 4599 /* bintval is in TU (1.024mS) */ 4600 if (ni != NULL) 4601 bintval = ni->ni_intval; 4602 4603 /* 4604 * If it's non-zero, we should calculate the minimum of 4605 * it and the DWELL_BASE. 4606 * 4607 * XXX Yes, the math should take into account that bintval 4608 * is 1.024mS, not 1mS.. 4609 */ 4610 if (bintval > 0) 4611 return MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)); 4612 4613 /* No association context? Default */ 4614 return IWN_PASSIVE_DWELL_BASE; 4615 } 4616 4617 static uint16_t 4618 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 4619 { 4620 uint16_t passive; 4621 if (flags & IEEE80211_CHAN_2GHZ) 4622 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 4623 else 4624 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 4625 4626 /* Clamp to the beacon interval if we're associated */ 4627 return iwn_limit_dwell(sc, passive); 4628 } 4629 4630 static int 4631 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4632 { 4633 struct ieee80211com *ic = &sc->sc_ic; 4634 struct iwn_scan_hdr *hdr; 4635 struct iwn_cmd_data *tx; 4636 struct iwn_scan_essid *essid; 4637 struct iwn_scan_chan *chan; 4638 struct ieee80211_frame *wh; 4639 struct ieee80211_rateset *rs; 4640 struct ieee80211_channel *c; 4641 uint8_t *buf, *frm; 4642 uint16_t rxchain, dwell_active, dwell_passive; 4643 uint8_t txant; 4644 int buflen, error, is_active; 4645 4646 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4647 if (buf == NULL) { 4648 aprint_error_dev(sc->sc_dev, 4649 "could not allocate buffer for scan command\n"); 4650 return ENOMEM; 4651 } 4652 hdr = (struct iwn_scan_hdr *)buf; 4653 /* 4654 * Move to the next channel if no frames are received within 10ms 4655 * after sending the probe request. 4656 */ 4657 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4658 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4659 4660 /* Select antennas for scanning. */ 4661 rxchain = 4662 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4663 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4664 IWN_RXCHAIN_DRIVER_FORCE; 4665 if ((flags & IEEE80211_CHAN_5GHZ) && 4666 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4667 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4668 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4669 } else /* Use all available RX antennas. */ 4670 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4671 hdr->rxchain = htole16(rxchain); 4672 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4673 4674 tx = (struct iwn_cmd_data *)(hdr + 1); 4675 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4676 tx->id = sc->broadcast_id; 4677 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4678 4679 if (flags & IEEE80211_CHAN_5GHZ) { 4680 hdr->crc_threshold = 0xffff; 4681 /* Send probe requests at 6Mbps. */ 4682 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4683 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4684 } else { 4685 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4686 /* Send probe requests at 1Mbps. */ 4687 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4688 tx->rflags = IWN_RFLAG_CCK; 4689 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4690 } 4691 /* Use the first valid TX antenna. */ 4692 txant = IWN_LSB(sc->txchainmask); 4693 tx->rflags |= IWN_RFLAG_ANT(txant); 4694 4695 /* 4696 * Only do active scanning if we're announcing a probe request 4697 * for a given SSID (or more, if we ever add it to the driver.) 4698 */ 4699 is_active = 0; 4700 4701 essid = (struct iwn_scan_essid *)(tx + 1); 4702 if (ic->ic_des_esslen != 0) { 4703 essid[0].id = IEEE80211_ELEMID_SSID; 4704 essid[0].len = ic->ic_des_esslen; 4705 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4706 4707 is_active = 1; 4708 } 4709 /* 4710 * Build a probe request frame. Most of the following code is a 4711 * copy & paste of what is done in net80211. 4712 */ 4713 wh = (struct ieee80211_frame *)(essid + 20); 4714 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4715 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4716 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4717 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4718 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4719 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4720 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4721 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4722 4723 frm = (uint8_t *)(wh + 1); 4724 frm = ieee80211_add_ssid(frm, NULL, 0); 4725 frm = ieee80211_add_rates(frm, rs); 4726 #ifndef IEEE80211_NO_HT 4727 if (ic->ic_flags & IEEE80211_F_HTON) 4728 frm = ieee80211_add_htcaps(frm, ic); 4729 #endif 4730 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4731 frm = ieee80211_add_xrates(frm, rs); 4732 4733 /* Set length of probe request. */ 4734 tx->len = htole16(frm - (uint8_t *)wh); 4735 4736 4737 /* 4738 * If active scanning is requested but a certain channel is 4739 * marked passive, we can do active scanning if we detect 4740 * transmissions. 4741 * 4742 * There is an issue with some firmware versions that triggers 4743 * a sysassert on a "good CRC threshold" of zero (== disabled), 4744 * on a radar channel even though this means that we should NOT 4745 * send probes. 4746 * 4747 * The "good CRC threshold" is the number of frames that we 4748 * need to receive during our dwell time on a channel before 4749 * sending out probes -- setting this to a huge value will 4750 * mean we never reach it, but at the same time work around 4751 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 4752 * here instead of IWN_GOOD_CRC_TH_DISABLED. 4753 * 4754 * This was fixed in later versions along with some other 4755 * scan changes, and the threshold behaves as a flag in those 4756 * versions. 4757 */ 4758 4759 /* 4760 * If we're doing active scanning, set the crc_threshold 4761 * to a suitable value. This is different to active veruss 4762 * passive scanning depending upon the channel flags; the 4763 * firmware will obey that particular check for us. 4764 */ 4765 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 4766 hdr->crc_threshold = is_active ? 4767 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 4768 else 4769 hdr->crc_threshold = is_active ? 4770 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 4771 4772 chan = (struct iwn_scan_chan *)frm; 4773 for (c = &ic->ic_channels[1]; 4774 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4775 if ((c->ic_flags & flags) != flags) 4776 continue; 4777 4778 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4779 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4780 chan->flags = 0; 4781 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4782 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4783 if (ic->ic_des_esslen != 0) 4784 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4785 4786 /* 4787 * Calculate the active/passive dwell times. 4788 */ 4789 4790 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 4791 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 4792 4793 /* Make sure they're valid */ 4794 if (dwell_passive <= dwell_active) 4795 dwell_passive = dwell_active + 1; 4796 4797 chan->active = htole16(dwell_active); 4798 chan->passive = htole16(dwell_passive); 4799 4800 chan->dsp_gain = 0x6e; 4801 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4802 chan->rf_gain = 0x3b; 4803 } else { 4804 chan->rf_gain = 0x28; 4805 } 4806 hdr->nchan++; 4807 chan++; 4808 } 4809 4810 buflen = (uint8_t *)chan - buf; 4811 hdr->len = htole16(buflen); 4812 4813 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4814 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4815 free(buf, M_DEVBUF); 4816 return error; 4817 } 4818 4819 static int 4820 iwn_auth(struct iwn_softc *sc) 4821 { 4822 struct iwn_ops *ops = &sc->ops; 4823 struct ieee80211com *ic = &sc->sc_ic; 4824 struct ieee80211_node *ni = ic->ic_bss; 4825 int error; 4826 4827 /* Update adapter configuration. */ 4828 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4829 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4830 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4831 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4832 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4833 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4834 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4835 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4836 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4837 switch (ic->ic_curmode) { 4838 case IEEE80211_MODE_11A: 4839 sc->rxon.cck_mask = 0; 4840 sc->rxon.ofdm_mask = 0x15; 4841 break; 4842 case IEEE80211_MODE_11B: 4843 sc->rxon.cck_mask = 0x03; 4844 sc->rxon.ofdm_mask = 0; 4845 break; 4846 default: /* Assume 802.11b/g. */ 4847 sc->rxon.cck_mask = 0x0f; 4848 sc->rxon.ofdm_mask = 0x15; 4849 } 4850 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4851 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4852 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4853 if (error != 0) { 4854 aprint_error_dev(sc->sc_dev, 4855 "RXON command failed\n"); 4856 return error; 4857 } 4858 4859 /* Configuration has changed, set TX power accordingly. */ 4860 if ((error = ops->set_txpower(sc, 1)) != 0) { 4861 aprint_error_dev(sc->sc_dev, 4862 "could not set TX power\n"); 4863 return error; 4864 } 4865 /* 4866 * Reconfiguring RXON clears the firmware nodes table so we must 4867 * add the broadcast node again. 4868 */ 4869 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4870 aprint_error_dev(sc->sc_dev, 4871 "could not add broadcast node\n"); 4872 return error; 4873 } 4874 return 0; 4875 } 4876 4877 static int 4878 iwn_run(struct iwn_softc *sc) 4879 { 4880 struct iwn_ops *ops = &sc->ops; 4881 struct ieee80211com *ic = &sc->sc_ic; 4882 struct ieee80211_node *ni = ic->ic_bss; 4883 struct iwn_node_info node; 4884 int error; 4885 4886 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4887 /* Link LED blinks while monitoring. */ 4888 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4889 return 0; 4890 } 4891 if ((error = iwn_set_timing(sc, ni)) != 0) { 4892 aprint_error_dev(sc->sc_dev, 4893 "could not set timing\n"); 4894 return error; 4895 } 4896 4897 /* Update adapter configuration. */ 4898 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4899 /* Short preamble and slot time are negotiated when associating. */ 4900 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4901 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4902 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4903 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4904 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4905 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4906 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4907 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4908 if (error != 0) { 4909 aprint_error_dev(sc->sc_dev, 4910 "could not update configuration\n"); 4911 return error; 4912 } 4913 4914 /* Configuration has changed, set TX power accordingly. */ 4915 if ((error = ops->set_txpower(sc, 1)) != 0) { 4916 aprint_error_dev(sc->sc_dev, 4917 "could not set TX power\n"); 4918 return error; 4919 } 4920 4921 /* Fake a join to initialize the TX rate. */ 4922 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4923 iwn_newassoc(ni, 1); 4924 4925 /* Add BSS node. */ 4926 memset(&node, 0, sizeof node); 4927 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4928 node.id = IWN_ID_BSS; 4929 #ifdef notyet 4930 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4931 IWN_AMDPU_DENSITY(5)); /* 2us */ 4932 #endif 4933 DPRINTF(("adding BSS node\n")); 4934 error = ops->add_node(sc, &node, 1); 4935 if (error != 0) { 4936 aprint_error_dev(sc->sc_dev, 4937 "could not add BSS node\n"); 4938 return error; 4939 } 4940 DPRINTF(("setting link quality for node %d\n", node.id)); 4941 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4942 aprint_error_dev(sc->sc_dev, 4943 "could not setup link quality for node %d\n", node.id); 4944 return error; 4945 } 4946 4947 if ((error = iwn_init_sensitivity(sc)) != 0) { 4948 aprint_error_dev(sc->sc_dev, 4949 "could not set sensitivity\n"); 4950 return error; 4951 } 4952 /* Start periodic calibration timer. */ 4953 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4954 sc->calib_cnt = 0; 4955 callout_schedule(&sc->calib_to, hz/2); 4956 4957 /* Link LED always on while associated. */ 4958 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4959 return 0; 4960 } 4961 4962 #ifdef IWN_HWCRYPTO 4963 /* 4964 * We support CCMP hardware encryption/decryption of unicast frames only. 4965 * HW support for TKIP really sucks. We should let TKIP die anyway. 4966 */ 4967 static int 4968 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4969 struct ieee80211_key *k) 4970 { 4971 struct iwn_softc *sc = ic->ic_softc; 4972 struct iwn_ops *ops = &sc->ops; 4973 struct iwn_node *wn = (void *)ni; 4974 struct iwn_node_info node; 4975 uint16_t kflags; 4976 4977 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4978 k->k_cipher != IEEE80211_CIPHER_CCMP) 4979 return ieee80211_set_key(ic, ni, k); 4980 4981 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4982 if (k->k_flags & IEEE80211_KEY_GROUP) 4983 kflags |= IWN_KFLAG_GROUP; 4984 4985 memset(&node, 0, sizeof node); 4986 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4987 sc->broadcast_id : wn->id; 4988 node.control = IWN_NODE_UPDATE; 4989 node.flags = IWN_FLAG_SET_KEY; 4990 node.kflags = htole16(kflags); 4991 node.kid = k->k_id; 4992 memcpy(node.key, k->k_key, k->k_len); 4993 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4994 return ops->add_node(sc, &node, 1); 4995 } 4996 4997 static void 4998 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4999 struct ieee80211_key *k) 5000 { 5001 struct iwn_softc *sc = ic->ic_softc; 5002 struct iwn_ops *ops = &sc->ops; 5003 struct iwn_node *wn = (void *)ni; 5004 struct iwn_node_info node; 5005 5006 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5007 k->k_cipher != IEEE80211_CIPHER_CCMP) { 5008 /* See comment about other ciphers above. */ 5009 ieee80211_delete_key(ic, ni, k); 5010 return; 5011 } 5012 if (ic->ic_state != IEEE80211_S_RUN) 5013 return; /* Nothing to do. */ 5014 memset(&node, 0, sizeof node); 5015 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5016 sc->broadcast_id : wn->id; 5017 node.control = IWN_NODE_UPDATE; 5018 node.flags = IWN_FLAG_SET_KEY; 5019 node.kflags = htole16(IWN_KFLAG_INVALID); 5020 node.kid = 0xff; 5021 DPRINTF(("delete keys for node %d\n", node.id)); 5022 (void)ops->add_node(sc, &node, 1); 5023 } 5024 #endif 5025 5026 /* XXX Added for NetBSD (copied from rev 1.39). */ 5027 5028 static int 5029 iwn_wme_update(struct ieee80211com *ic) 5030 { 5031 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 5032 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 5033 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5034 const struct wmeParams *wmep; 5035 struct iwn_edca_params cmd; 5036 int ac; 5037 5038 /* don't override default WME values if WME is not actually enabled */ 5039 if (!(ic->ic_flags & IEEE80211_F_WME)) 5040 return 0; 5041 cmd.flags = 0; 5042 for (ac = 0; ac < WME_NUM_AC; ac++) { 5043 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 5044 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 5045 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 5046 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 5047 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 5048 5049 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 5050 "txop=%d\n", ac, cmd.ac[ac].aifsn, 5051 cmd.ac[ac].cwmin, 5052 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 5053 } 5054 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5055 #undef IWN_USEC 5056 #undef IWN_EXP2 5057 } 5058 5059 #ifndef IEEE80211_NO_HT 5060 /* 5061 * This function is called by upper layer when an ADDBA request is received 5062 * from another STA and before the ADDBA response is sent. 5063 */ 5064 static int 5065 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5066 uint8_t tid) 5067 { 5068 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5069 struct iwn_softc *sc = ic->ic_softc; 5070 struct iwn_ops *ops = &sc->ops; 5071 struct iwn_node *wn = (void *)ni; 5072 struct iwn_node_info node; 5073 5074 memset(&node, 0, sizeof node); 5075 node.id = wn->id; 5076 node.control = IWN_NODE_UPDATE; 5077 node.flags = IWN_FLAG_SET_ADDBA; 5078 node.addba_tid = tid; 5079 node.addba_ssn = htole16(ba->ba_winstart); 5080 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 5081 ba->ba_winstart)); 5082 return ops->add_node(sc, &node, 1); 5083 } 5084 5085 /* 5086 * This function is called by upper layer on teardown of an HT-immediate 5087 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5088 */ 5089 static void 5090 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5091 uint8_t tid) 5092 { 5093 struct iwn_softc *sc = ic->ic_softc; 5094 struct iwn_ops *ops = &sc->ops; 5095 struct iwn_node *wn = (void *)ni; 5096 struct iwn_node_info node; 5097 5098 memset(&node, 0, sizeof node); 5099 node.id = wn->id; 5100 node.control = IWN_NODE_UPDATE; 5101 node.flags = IWN_FLAG_SET_DELBA; 5102 node.delba_tid = tid; 5103 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 5104 (void)ops->add_node(sc, &node, 1); 5105 } 5106 5107 /* 5108 * This function is called by upper layer when an ADDBA response is received 5109 * from another STA. 5110 */ 5111 static int 5112 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5113 uint8_t tid) 5114 { 5115 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5116 struct iwn_softc *sc = ic->ic_softc; 5117 struct iwn_ops *ops = &sc->ops; 5118 struct iwn_node *wn = (void *)ni; 5119 struct iwn_node_info node; 5120 int error; 5121 5122 /* Enable TX for the specified RA/TID. */ 5123 wn->disable_tid &= ~(1 << tid); 5124 memset(&node, 0, sizeof node); 5125 node.id = wn->id; 5126 node.control = IWN_NODE_UPDATE; 5127 node.flags = IWN_FLAG_SET_DISABLE_TID; 5128 node.disable_tid = htole16(wn->disable_tid); 5129 error = ops->add_node(sc, &node, 1); 5130 if (error != 0) 5131 return error; 5132 5133 if ((error = iwn_nic_lock(sc)) != 0) 5134 return error; 5135 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5136 iwn_nic_unlock(sc); 5137 return 0; 5138 } 5139 5140 static void 5141 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5142 uint8_t tid) 5143 { 5144 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5145 struct iwn_softc *sc = ic->ic_softc; 5146 struct iwn_ops *ops = &sc->ops; 5147 5148 if (iwn_nic_lock(sc) != 0) 5149 return; 5150 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5151 iwn_nic_unlock(sc); 5152 } 5153 5154 static void 5155 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5156 uint8_t tid, uint16_t ssn) 5157 { 5158 struct iwn_node *wn = (void *)ni; 5159 int qid = 7 + tid; 5160 5161 /* Stop TX scheduler while we're changing its configuration. */ 5162 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5163 IWN4965_TXQ_STATUS_CHGACT); 5164 5165 /* Assign RA/TID translation to the queue. */ 5166 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5167 wn->id << 4 | tid); 5168 5169 /* Enable chain-building mode for the queue. */ 5170 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5171 5172 /* Set starting sequence number from the ADDBA request. */ 5173 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5174 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5175 5176 /* Set scheduler window size. */ 5177 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5178 IWN_SCHED_WINSZ); 5179 /* Set scheduler frame limit. */ 5180 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5181 IWN_SCHED_LIMIT << 16); 5182 5183 /* Enable interrupts for the queue. */ 5184 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5185 5186 /* Mark the queue as active. */ 5187 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5188 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5189 iwn_tid2fifo[tid] << 1); 5190 } 5191 5192 static void 5193 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5194 { 5195 int qid = 7 + tid; 5196 5197 /* Stop TX scheduler while we're changing its configuration. */ 5198 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5199 IWN4965_TXQ_STATUS_CHGACT); 5200 5201 /* Set starting sequence number from the ADDBA request. */ 5202 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5203 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5204 5205 /* Disable interrupts for the queue. */ 5206 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5207 5208 /* Mark the queue as inactive. */ 5209 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5210 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5211 } 5212 5213 static void 5214 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5215 uint8_t tid, uint16_t ssn) 5216 { 5217 struct iwn_node *wn = (void *)ni; 5218 int qid = 10 + tid; 5219 5220 /* Stop TX scheduler while we're changing its configuration. */ 5221 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5222 IWN5000_TXQ_STATUS_CHGACT); 5223 5224 /* Assign RA/TID translation to the queue. */ 5225 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5226 wn->id << 4 | tid); 5227 5228 /* Enable chain-building mode for the queue. */ 5229 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5230 5231 /* Enable aggregation for the queue. */ 5232 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5233 5234 /* Set starting sequence number from the ADDBA request. */ 5235 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5236 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5237 5238 /* Set scheduler window size and frame limit. */ 5239 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5240 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5241 5242 /* Enable interrupts for the queue. */ 5243 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5244 5245 /* Mark the queue as active. */ 5246 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5247 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5248 } 5249 5250 static void 5251 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5252 { 5253 int qid = 10 + tid; 5254 5255 /* Stop TX scheduler while we're changing its configuration. */ 5256 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5257 IWN5000_TXQ_STATUS_CHGACT); 5258 5259 /* Disable aggregation for the queue. */ 5260 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5261 5262 /* Set starting sequence number from the ADDBA request. */ 5263 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5264 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5265 5266 /* Disable interrupts for the queue. */ 5267 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5268 5269 /* Mark the queue as inactive. */ 5270 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5271 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5272 } 5273 #endif /* !IEEE80211_NO_HT */ 5274 5275 /* 5276 * Query calibration tables from the initialization firmware. We do this 5277 * only once at first boot. Called from a process context. 5278 */ 5279 static int 5280 iwn5000_query_calibration(struct iwn_softc *sc) 5281 { 5282 struct iwn5000_calib_config cmd; 5283 int error; 5284 5285 memset(&cmd, 0, sizeof cmd); 5286 cmd.ucode.once.enable = 0xffffffff; 5287 cmd.ucode.once.start = 0xffffffff; 5288 cmd.ucode.once.send = 0xffffffff; 5289 cmd.ucode.flags = 0xffffffff; 5290 DPRINTF(("sending calibration query\n")); 5291 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5292 if (error != 0) 5293 return error; 5294 5295 /* Wait at most two seconds for calibration to complete. */ 5296 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5297 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 5298 return error; 5299 } 5300 5301 /* 5302 * Send calibration results to the runtime firmware. These results were 5303 * obtained on first boot from the initialization firmware. 5304 */ 5305 static int 5306 iwn5000_send_calibration(struct iwn_softc *sc) 5307 { 5308 int idx, error; 5309 5310 for (idx = 0; idx < 5; idx++) { 5311 if (sc->calibcmd[idx].buf == NULL) 5312 continue; /* No results available. */ 5313 DPRINTF(("send calibration result idx=%d len=%d\n", 5314 idx, sc->calibcmd[idx].len)); 5315 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5316 sc->calibcmd[idx].len, 0); 5317 if (error != 0) { 5318 aprint_error_dev(sc->sc_dev, 5319 "could not send calibration result\n"); 5320 return error; 5321 } 5322 } 5323 return 0; 5324 } 5325 5326 static int 5327 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5328 { 5329 struct iwn5000_wimax_coex wimax; 5330 5331 #ifdef notyet 5332 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5333 /* Enable WiMAX coexistence for combo adapters. */ 5334 wimax.flags = 5335 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5336 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5337 IWN_WIMAX_COEX_STA_TABLE_VALID | 5338 IWN_WIMAX_COEX_ENABLE; 5339 memcpy(wimax.events, iwn6050_wimax_events, 5340 sizeof iwn6050_wimax_events); 5341 } else 5342 #endif 5343 { 5344 /* Disable WiMAX coexistence. */ 5345 wimax.flags = 0; 5346 memset(wimax.events, 0, sizeof wimax.events); 5347 } 5348 DPRINTF(("Configuring WiMAX coexistence\n")); 5349 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5350 } 5351 5352 static int 5353 iwn6000_temp_offset_calib(struct iwn_softc *sc) 5354 { 5355 struct iwn6000_phy_calib_temp_offset cmd; 5356 5357 memset(&cmd, 0, sizeof cmd); 5358 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 5359 cmd.ngroups = 1; 5360 cmd.isvalid = 1; 5361 if (sc->eeprom_temp != 0) 5362 cmd.offset = htole16(sc->eeprom_temp); 5363 else 5364 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5365 DPRINTF(("setting radio sensor offset to %d\n", le16toh(cmd.offset))); 5366 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5367 } 5368 5369 static int 5370 iwn2000_temp_offset_calib(struct iwn_softc *sc) 5371 { 5372 struct iwn2000_phy_calib_temp_offset cmd; 5373 5374 memset(&cmd, 0, sizeof cmd); 5375 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 5376 cmd.ngroups = 1; 5377 cmd.isvalid = 1; 5378 if (sc->eeprom_rawtemp != 0) { 5379 cmd.offset_low = htole16(sc->eeprom_rawtemp); 5380 cmd.offset_high = htole16(sc->eeprom_temp); 5381 } else { 5382 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 5383 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 5384 } 5385 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 5386 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 5387 le16toh(cmd.offset_low), le16toh(cmd.offset_high), 5388 le16toh(cmd.burnt_voltage_ref))); 5389 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5390 } 5391 5392 /* 5393 * This function is called after the runtime firmware notifies us of its 5394 * readiness (called in a process context). 5395 */ 5396 static int 5397 iwn4965_post_alive(struct iwn_softc *sc) 5398 { 5399 int error, qid; 5400 5401 if ((error = iwn_nic_lock(sc)) != 0) 5402 return error; 5403 5404 /* Clear TX scheduler state in SRAM. */ 5405 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5406 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5407 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5408 5409 /* Set physical address of TX scheduler rings (1KB aligned). */ 5410 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5411 5412 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5413 5414 /* Disable chain mode for all our 16 queues. */ 5415 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5416 5417 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5418 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5419 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5420 5421 /* Set scheduler window size. */ 5422 iwn_mem_write(sc, sc->sched_base + 5423 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5424 /* Set scheduler frame limit. */ 5425 iwn_mem_write(sc, sc->sched_base + 5426 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5427 IWN_SCHED_LIMIT << 16); 5428 } 5429 5430 /* Enable interrupts for all our 16 queues. */ 5431 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5432 /* Identify TX FIFO rings (0-7). */ 5433 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5434 5435 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5436 for (qid = 0; qid < 7; qid++) { 5437 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5438 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5439 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5440 } 5441 iwn_nic_unlock(sc); 5442 return 0; 5443 } 5444 5445 /* 5446 * This function is called after the initialization or runtime firmware 5447 * notifies us of its readiness (called in a process context). 5448 */ 5449 static int 5450 iwn5000_post_alive(struct iwn_softc *sc) 5451 { 5452 int error, qid; 5453 5454 /* Switch to using ICT interrupt mode. */ 5455 iwn5000_ict_reset(sc); 5456 5457 if ((error = iwn_nic_lock(sc)) != 0) 5458 return error; 5459 5460 /* Clear TX scheduler state in SRAM. */ 5461 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5462 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5463 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5464 5465 /* Set physical address of TX scheduler rings (1KB aligned). */ 5466 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5467 5468 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5469 5470 /* Enable chain mode for all queues, except command queue. */ 5471 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5472 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5473 5474 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5475 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5476 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5477 5478 iwn_mem_write(sc, sc->sched_base + 5479 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5480 /* Set scheduler window size and frame limit. */ 5481 iwn_mem_write(sc, sc->sched_base + 5482 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5483 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5484 } 5485 5486 /* Enable interrupts for all our 20 queues. */ 5487 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5488 /* Identify TX FIFO rings (0-7). */ 5489 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5490 5491 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5492 for (qid = 0; qid < 7; qid++) { 5493 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5494 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5495 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5496 } 5497 iwn_nic_unlock(sc); 5498 5499 /* Configure WiMAX coexistence for combo adapters. */ 5500 error = iwn5000_send_wimax_coex(sc); 5501 if (error != 0) { 5502 aprint_error_dev(sc->sc_dev, 5503 "could not configure WiMAX coexistence\n"); 5504 return error; 5505 } 5506 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5507 struct iwn5000_phy_calib_crystal cmd; 5508 5509 /* Perform crystal calibration. */ 5510 memset(&cmd, 0, sizeof cmd); 5511 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5512 cmd.ngroups = 1; 5513 cmd.isvalid = 1; 5514 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5515 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5516 DPRINTF(("sending crystal calibration %d, %d\n", 5517 cmd.cap_pin[0], cmd.cap_pin[1])); 5518 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5519 if (error != 0) { 5520 aprint_error_dev(sc->sc_dev, 5521 "crystal calibration failed\n"); 5522 return error; 5523 } 5524 } 5525 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5526 /* Query calibration from the initialization firmware. */ 5527 if ((error = iwn5000_query_calibration(sc)) != 0) { 5528 aprint_error_dev(sc->sc_dev, 5529 "could not query calibration\n"); 5530 return error; 5531 } 5532 /* 5533 * We have the calibration results now, reboot with the 5534 * runtime firmware (call ourselves recursively!) 5535 */ 5536 iwn_hw_stop(sc); 5537 error = iwn_hw_init(sc); 5538 } else { 5539 /* Send calibration results to runtime firmware. */ 5540 error = iwn5000_send_calibration(sc); 5541 } 5542 return error; 5543 } 5544 5545 /* 5546 * The firmware boot code is small and is intended to be copied directly into 5547 * the NIC internal memory (no DMA transfer). 5548 */ 5549 static int 5550 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5551 { 5552 int error, ntries; 5553 5554 size /= sizeof (uint32_t); 5555 5556 if ((error = iwn_nic_lock(sc)) != 0) 5557 return error; 5558 5559 /* Copy microcode image into NIC memory. */ 5560 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5561 (const uint32_t *)ucode, size); 5562 5563 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5564 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5565 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5566 5567 /* Start boot load now. */ 5568 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5569 5570 /* Wait for transfer to complete. */ 5571 for (ntries = 0; ntries < 1000; ntries++) { 5572 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5573 IWN_BSM_WR_CTRL_START)) 5574 break; 5575 DELAY(10); 5576 } 5577 if (ntries == 1000) { 5578 aprint_error_dev(sc->sc_dev, 5579 "could not load boot firmware\n"); 5580 iwn_nic_unlock(sc); 5581 return ETIMEDOUT; 5582 } 5583 5584 /* Enable boot after power up. */ 5585 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5586 5587 iwn_nic_unlock(sc); 5588 return 0; 5589 } 5590 5591 static int 5592 iwn4965_load_firmware(struct iwn_softc *sc) 5593 { 5594 struct iwn_fw_info *fw = &sc->fw; 5595 struct iwn_dma_info *dma = &sc->fw_dma; 5596 int error; 5597 5598 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5599 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5600 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5601 BUS_DMASYNC_PREWRITE); 5602 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5603 fw->init.text, fw->init.textsz); 5604 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5605 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5606 5607 /* Tell adapter where to find initialization sections. */ 5608 if ((error = iwn_nic_lock(sc)) != 0) 5609 return error; 5610 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5611 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5612 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5613 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5614 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5615 iwn_nic_unlock(sc); 5616 5617 /* Load firmware boot code. */ 5618 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5619 if (error != 0) { 5620 aprint_error_dev(sc->sc_dev, 5621 "could not load boot firmware\n"); 5622 return error; 5623 } 5624 /* Now press "execute". */ 5625 IWN_WRITE(sc, IWN_RESET, 0); 5626 5627 /* Wait at most one second for first alive notification. */ 5628 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5629 aprint_error_dev(sc->sc_dev, 5630 "timeout waiting for adapter to initialize\n"); 5631 return error; 5632 } 5633 5634 /* Retrieve current temperature for initial TX power calibration. */ 5635 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5636 sc->temp = iwn4965_get_temperature(sc); 5637 5638 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5639 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5640 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5641 BUS_DMASYNC_PREWRITE); 5642 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5643 fw->main.text, fw->main.textsz); 5644 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5645 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5646 5647 /* Tell adapter where to find runtime sections. */ 5648 if ((error = iwn_nic_lock(sc)) != 0) 5649 return error; 5650 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5651 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5652 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5653 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5654 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5655 IWN_FW_UPDATED | fw->main.textsz); 5656 iwn_nic_unlock(sc); 5657 5658 return 0; 5659 } 5660 5661 static int 5662 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5663 const uint8_t *section, int size) 5664 { 5665 struct iwn_dma_info *dma = &sc->fw_dma; 5666 int error; 5667 5668 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5669 memcpy(dma->vaddr, section, size); 5670 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5671 5672 if ((error = iwn_nic_lock(sc)) != 0) 5673 return error; 5674 5675 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5676 IWN_FH_TX_CONFIG_DMA_PAUSE); 5677 5678 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5679 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5680 IWN_LOADDR(dma->paddr)); 5681 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5682 IWN_HIADDR(dma->paddr) << 28 | size); 5683 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5684 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5685 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5686 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5687 5688 /* Kick Flow Handler to start DMA transfer. */ 5689 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5690 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5691 5692 iwn_nic_unlock(sc); 5693 5694 /* Wait at most five seconds for FH DMA transfer to complete. */ 5695 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5696 } 5697 5698 static int 5699 iwn5000_load_firmware(struct iwn_softc *sc) 5700 { 5701 struct iwn_fw_part *fw; 5702 int error; 5703 5704 /* Load the initialization firmware on first boot only. */ 5705 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5706 &sc->fw.main : &sc->fw.init; 5707 5708 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5709 fw->text, fw->textsz); 5710 if (error != 0) { 5711 aprint_error_dev(sc->sc_dev, 5712 "could not load firmware %s section\n", ".text"); 5713 return error; 5714 } 5715 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5716 fw->data, fw->datasz); 5717 if (error != 0) { 5718 aprint_error_dev(sc->sc_dev, 5719 "could not load firmware %s section\n", ".data"); 5720 return error; 5721 } 5722 5723 /* Now press "execute". */ 5724 IWN_WRITE(sc, IWN_RESET, 0); 5725 return 0; 5726 } 5727 5728 /* 5729 * Extract text and data sections from a legacy firmware image. 5730 */ 5731 static int 5732 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5733 { 5734 const uint32_t *ptr; 5735 size_t hdrlen = 24; 5736 uint32_t rev; 5737 5738 ptr = (const uint32_t *)fw->data; 5739 rev = le32toh(*ptr++); 5740 5741 sc->ucode_rev = rev; 5742 5743 /* Check firmware API version. */ 5744 if (IWN_FW_API(rev) <= 1) { 5745 aprint_error_dev(sc->sc_dev, 5746 "bad firmware, need API version >=2\n"); 5747 return EINVAL; 5748 } 5749 if (IWN_FW_API(rev) >= 3) { 5750 /* Skip build number (version 2 header). */ 5751 hdrlen += 4; 5752 ptr++; 5753 } 5754 if (fw->size < hdrlen) { 5755 aprint_error_dev(sc->sc_dev, 5756 "firmware too short: %zd bytes\n", fw->size); 5757 return EINVAL; 5758 } 5759 fw->main.textsz = le32toh(*ptr++); 5760 fw->main.datasz = le32toh(*ptr++); 5761 fw->init.textsz = le32toh(*ptr++); 5762 fw->init.datasz = le32toh(*ptr++); 5763 fw->boot.textsz = le32toh(*ptr++); 5764 5765 /* Check that all firmware sections fit. */ 5766 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5767 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5768 aprint_error_dev(sc->sc_dev, 5769 "firmware too short: %zd bytes\n", fw->size); 5770 return EINVAL; 5771 } 5772 5773 /* Get pointers to firmware sections. */ 5774 fw->main.text = (const uint8_t *)ptr; 5775 fw->main.data = fw->main.text + fw->main.textsz; 5776 fw->init.text = fw->main.data + fw->main.datasz; 5777 fw->init.data = fw->init.text + fw->init.textsz; 5778 fw->boot.text = fw->init.data + fw->init.datasz; 5779 return 0; 5780 } 5781 5782 /* 5783 * Extract text and data sections from a TLV firmware image. 5784 */ 5785 static int 5786 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5787 uint16_t alt) 5788 { 5789 const struct iwn_fw_tlv_hdr *hdr; 5790 const struct iwn_fw_tlv *tlv; 5791 const uint8_t *ptr, *end; 5792 uint64_t altmask; 5793 uint32_t len; 5794 5795 if (fw->size < sizeof (*hdr)) { 5796 aprint_error_dev(sc->sc_dev, 5797 "firmware too short: %zd bytes\n", fw->size); 5798 return EINVAL; 5799 } 5800 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5801 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5802 aprint_error_dev(sc->sc_dev, 5803 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5804 return EINVAL; 5805 } 5806 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5807 le32toh(hdr->build))); 5808 sc->ucode_rev = le32toh(hdr->rev); 5809 5810 /* 5811 * Select the closest supported alternative that is less than 5812 * or equal to the specified one. 5813 */ 5814 altmask = le64toh(hdr->altmask); 5815 while (alt > 0 && !(altmask & (1ULL << alt))) 5816 alt--; /* Downgrade. */ 5817 DPRINTF(("using alternative %d\n", alt)); 5818 5819 ptr = (const uint8_t *)(hdr + 1); 5820 end = (const uint8_t *)(fw->data + fw->size); 5821 5822 /* Parse type-length-value fields. */ 5823 while (ptr + sizeof (*tlv) <= end) { 5824 tlv = (const struct iwn_fw_tlv *)ptr; 5825 len = le32toh(tlv->len); 5826 5827 ptr += sizeof (*tlv); 5828 if (ptr + len > end) { 5829 aprint_error_dev(sc->sc_dev, 5830 "firmware too short: %zd bytes\n", fw->size); 5831 return EINVAL; 5832 } 5833 /* Skip other alternatives. */ 5834 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5835 goto next; 5836 5837 switch (le16toh(tlv->type)) { 5838 case IWN_FW_TLV_MAIN_TEXT: 5839 fw->main.text = ptr; 5840 fw->main.textsz = len; 5841 break; 5842 case IWN_FW_TLV_MAIN_DATA: 5843 fw->main.data = ptr; 5844 fw->main.datasz = len; 5845 break; 5846 case IWN_FW_TLV_INIT_TEXT: 5847 fw->init.text = ptr; 5848 fw->init.textsz = len; 5849 break; 5850 case IWN_FW_TLV_INIT_DATA: 5851 fw->init.data = ptr; 5852 fw->init.datasz = len; 5853 break; 5854 case IWN_FW_TLV_BOOT_TEXT: 5855 fw->boot.text = ptr; 5856 fw->boot.textsz = len; 5857 break; 5858 case IWN_FW_TLV_ENH_SENS: 5859 if (len != 0) { 5860 aprint_error_dev(sc->sc_dev, 5861 "TLV type %d has invalid size %u\n", 5862 le16toh(tlv->type), len); 5863 goto next; 5864 } 5865 sc->sc_flags |= IWN_FLAG_ENH_SENS; 5866 break; 5867 case IWN_FW_TLV_PHY_CALIB: 5868 if (len != sizeof(uint32_t)) { 5869 aprint_error_dev(sc->sc_dev, 5870 "TLV type %d has invalid size %u\n", 5871 le16toh(tlv->type), len); 5872 goto next; 5873 } 5874 if (le32toh(*ptr) <= IWN5000_PHY_CALIB_MAX) { 5875 sc->reset_noise_gain = le32toh(*ptr); 5876 sc->noise_gain = le32toh(*ptr) + 1; 5877 } 5878 break; 5879 case IWN_FW_TLV_FLAGS: 5880 if (len < sizeof(uint32_t)) 5881 break; 5882 if (len % sizeof(uint32_t)) 5883 break; 5884 sc->tlv_feature_flags = le32toh(*ptr); 5885 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 5886 break; 5887 default: 5888 DPRINTF(("TLV type %d not handled\n", 5889 le16toh(tlv->type))); 5890 break; 5891 } 5892 next: /* TLV fields are 32-bit aligned. */ 5893 ptr += (len + 3) & ~3; 5894 } 5895 return 0; 5896 } 5897 5898 static int 5899 iwn_read_firmware(struct iwn_softc *sc) 5900 { 5901 struct iwn_fw_info *fw = &sc->fw; 5902 firmware_handle_t fwh; 5903 int error; 5904 5905 /* 5906 * Some PHY calibration commands are firmware-dependent; these 5907 * are the default values that will be overridden if 5908 * necessary. 5909 */ 5910 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 5911 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 5912 5913 /* Initialize for error returns */ 5914 fw->data = NULL; 5915 fw->size = 0; 5916 5917 /* Open firmware image. */ 5918 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5919 aprint_error_dev(sc->sc_dev, 5920 "could not get firmware handle %s\n", sc->fwname); 5921 return error; 5922 } 5923 fw->size = firmware_get_size(fwh); 5924 if (fw->size < sizeof (uint32_t)) { 5925 aprint_error_dev(sc->sc_dev, 5926 "firmware too short: %zd bytes\n", fw->size); 5927 firmware_close(fwh); 5928 return EINVAL; 5929 } 5930 5931 /* Read the firmware. */ 5932 fw->data = firmware_malloc(fw->size); 5933 if (fw->data == NULL) { 5934 aprint_error_dev(sc->sc_dev, 5935 "not enough memory to stock firmware %s\n", sc->fwname); 5936 firmware_close(fwh); 5937 return ENOMEM; 5938 } 5939 error = firmware_read(fwh, 0, fw->data, fw->size); 5940 firmware_close(fwh); 5941 if (error != 0) { 5942 aprint_error_dev(sc->sc_dev, 5943 "could not read firmware %s\n", sc->fwname); 5944 goto out; 5945 } 5946 5947 /* Retrieve text and data sections. */ 5948 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5949 error = iwn_read_firmware_leg(sc, fw); 5950 else 5951 error = iwn_read_firmware_tlv(sc, fw, 1); 5952 if (error != 0) { 5953 aprint_error_dev(sc->sc_dev, 5954 "could not read firmware sections\n"); 5955 goto out; 5956 } 5957 5958 /* Make sure text and data sections fit in hardware memory. */ 5959 if (fw->main.textsz > sc->fw_text_maxsz || 5960 fw->main.datasz > sc->fw_data_maxsz || 5961 fw->init.textsz > sc->fw_text_maxsz || 5962 fw->init.datasz > sc->fw_data_maxsz || 5963 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5964 (fw->boot.textsz & 3) != 0) { 5965 aprint_error_dev(sc->sc_dev, 5966 "firmware sections too large\n"); 5967 goto out; 5968 } 5969 5970 /* We can proceed with loading the firmware. */ 5971 return 0; 5972 out: 5973 firmware_free(fw->data, fw->size); 5974 fw->data = NULL; 5975 fw->size = 0; 5976 return error ? error : EINVAL; 5977 } 5978 5979 static int 5980 iwn_clock_wait(struct iwn_softc *sc) 5981 { 5982 int ntries; 5983 5984 /* Set "initialization complete" bit. */ 5985 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5986 5987 /* Wait for clock stabilization. */ 5988 for (ntries = 0; ntries < 2500; ntries++) { 5989 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5990 return 0; 5991 DELAY(10); 5992 } 5993 aprint_error_dev(sc->sc_dev, 5994 "timeout waiting for clock stabilization\n"); 5995 return ETIMEDOUT; 5996 } 5997 5998 static int 5999 iwn_apm_init(struct iwn_softc *sc) 6000 { 6001 pcireg_t reg; 6002 int error; 6003 6004 /* Disable L0s exit timer (NMI bug workaround). */ 6005 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6006 /* Don't wait for ICH L0s (ICH bug workaround). */ 6007 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6008 6009 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6010 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6011 6012 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6013 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6014 6015 /* Retrieve PCIe Active State Power Management (ASPM). */ 6016 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 6017 sc->sc_cap_off + PCIE_LCSR); 6018 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6019 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 6020 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6021 else 6022 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6023 6024 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6025 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6026 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6027 6028 /* Wait for clock stabilization before accessing prph. */ 6029 if ((error = iwn_clock_wait(sc)) != 0) 6030 return error; 6031 6032 if ((error = iwn_nic_lock(sc)) != 0) 6033 return error; 6034 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6035 /* Enable DMA and BSM (Bootstrap State Machine). */ 6036 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6037 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6038 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6039 } else { 6040 /* Enable DMA. */ 6041 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6042 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6043 } 6044 DELAY(20); 6045 /* Disable L1-Active. */ 6046 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6047 iwn_nic_unlock(sc); 6048 6049 return 0; 6050 } 6051 6052 static void 6053 iwn_apm_stop_master(struct iwn_softc *sc) 6054 { 6055 int ntries; 6056 6057 /* Stop busmaster DMA activity. */ 6058 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6059 for (ntries = 0; ntries < 100; ntries++) { 6060 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6061 return; 6062 DELAY(10); 6063 } 6064 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 6065 } 6066 6067 static void 6068 iwn_apm_stop(struct iwn_softc *sc) 6069 { 6070 iwn_apm_stop_master(sc); 6071 6072 /* Reset the entire device. */ 6073 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6074 DELAY(10); 6075 /* Clear "initialization complete" bit. */ 6076 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6077 } 6078 6079 static int 6080 iwn4965_nic_config(struct iwn_softc *sc) 6081 { 6082 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6083 /* 6084 * I don't believe this to be correct but this is what the 6085 * vendor driver is doing. Probably the bits should not be 6086 * shifted in IWN_RFCFG_*. 6087 */ 6088 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6089 IWN_RFCFG_TYPE(sc->rfcfg) | 6090 IWN_RFCFG_STEP(sc->rfcfg) | 6091 IWN_RFCFG_DASH(sc->rfcfg)); 6092 } 6093 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6094 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6095 return 0; 6096 } 6097 6098 static int 6099 iwn5000_nic_config(struct iwn_softc *sc) 6100 { 6101 uint32_t tmp; 6102 int error; 6103 6104 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6105 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6106 IWN_RFCFG_TYPE(sc->rfcfg) | 6107 IWN_RFCFG_STEP(sc->rfcfg) | 6108 IWN_RFCFG_DASH(sc->rfcfg)); 6109 } 6110 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6111 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6112 6113 if ((error = iwn_nic_lock(sc)) != 0) 6114 return error; 6115 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6116 6117 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6118 /* 6119 * Select first Switching Voltage Regulator (1.32V) to 6120 * solve a stability issue related to noisy DC2DC line 6121 * in the silicon of 1000 Series. 6122 */ 6123 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6124 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6125 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6126 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6127 } 6128 iwn_nic_unlock(sc); 6129 6130 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6131 /* Use internal power amplifier only. */ 6132 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6133 } 6134 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6135 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6136 /* Indicate that ROM calibration version is >=6. */ 6137 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6138 } 6139 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6140 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6141 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6142 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6143 sc->hw_type == IWN_HW_REV_TYPE_135 || 6144 sc->hw_type == IWN_HW_REV_TYPE_105) 6145 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6146 return 0; 6147 } 6148 6149 /* 6150 * Take NIC ownership over Intel Active Management Technology (AMT). 6151 */ 6152 static int 6153 iwn_hw_prepare(struct iwn_softc *sc) 6154 { 6155 int ntries; 6156 6157 /* Check if hardware is ready. */ 6158 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6159 for (ntries = 0; ntries < 5; ntries++) { 6160 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6161 IWN_HW_IF_CONFIG_NIC_READY) 6162 return 0; 6163 DELAY(10); 6164 } 6165 6166 /* Hardware not ready, force into ready state. */ 6167 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6168 for (ntries = 0; ntries < 15000; ntries++) { 6169 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6170 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6171 break; 6172 DELAY(10); 6173 } 6174 if (ntries == 15000) 6175 return ETIMEDOUT; 6176 6177 /* Hardware should be ready now. */ 6178 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6179 for (ntries = 0; ntries < 5; ntries++) { 6180 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6181 IWN_HW_IF_CONFIG_NIC_READY) 6182 return 0; 6183 DELAY(10); 6184 } 6185 return ETIMEDOUT; 6186 } 6187 6188 static int 6189 iwn_hw_init(struct iwn_softc *sc) 6190 { 6191 struct iwn_ops *ops = &sc->ops; 6192 int error, chnl, qid; 6193 6194 /* Clear pending interrupts. */ 6195 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6196 6197 if ((error = iwn_apm_init(sc)) != 0) { 6198 aprint_error_dev(sc->sc_dev, 6199 "could not power ON adapter\n"); 6200 return error; 6201 } 6202 6203 /* Select VMAIN power source. */ 6204 if ((error = iwn_nic_lock(sc)) != 0) 6205 return error; 6206 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6207 iwn_nic_unlock(sc); 6208 6209 /* Perform adapter-specific initialization. */ 6210 if ((error = ops->nic_config(sc)) != 0) 6211 return error; 6212 6213 /* Initialize RX ring. */ 6214 if ((error = iwn_nic_lock(sc)) != 0) 6215 return error; 6216 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6217 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6218 /* Set physical address of RX ring (256-byte aligned). */ 6219 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6220 /* Set physical address of RX status (16-byte aligned). */ 6221 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6222 /* Enable RX. */ 6223 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6224 IWN_FH_RX_CONFIG_ENA | 6225 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6226 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6227 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6228 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6229 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6230 iwn_nic_unlock(sc); 6231 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6232 6233 if ((error = iwn_nic_lock(sc)) != 0) 6234 return error; 6235 6236 /* Initialize TX scheduler. */ 6237 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6238 6239 /* Set physical address of "keep warm" page (16-byte aligned). */ 6240 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6241 6242 /* Initialize TX rings. */ 6243 for (qid = 0; qid < sc->ntxqs; qid++) { 6244 struct iwn_tx_ring *txq = &sc->txq[qid]; 6245 6246 /* Set physical address of TX ring (256-byte aligned). */ 6247 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6248 txq->desc_dma.paddr >> 8); 6249 } 6250 iwn_nic_unlock(sc); 6251 6252 /* Enable DMA channels. */ 6253 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6254 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6255 IWN_FH_TX_CONFIG_DMA_ENA | 6256 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6257 } 6258 6259 /* Clear "radio off" and "commands blocked" bits. */ 6260 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6261 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6262 6263 /* Clear pending interrupts. */ 6264 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6265 /* Enable interrupt coalescing. */ 6266 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6267 /* Enable interrupts. */ 6268 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6269 6270 /* _Really_ make sure "radio off" bit is cleared! */ 6271 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6272 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6273 6274 /* Enable shadow registers. */ 6275 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6276 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6277 6278 if ((error = ops->load_firmware(sc)) != 0) { 6279 aprint_error_dev(sc->sc_dev, 6280 "could not load firmware\n"); 6281 return error; 6282 } 6283 /* Wait at most one second for firmware alive notification. */ 6284 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 6285 aprint_error_dev(sc->sc_dev, 6286 "timeout waiting for adapter to initialize\n"); 6287 return error; 6288 } 6289 /* Do post-firmware initialization. */ 6290 return ops->post_alive(sc); 6291 } 6292 6293 static void 6294 iwn_hw_stop(struct iwn_softc *sc) 6295 { 6296 int chnl, qid, ntries; 6297 6298 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6299 6300 /* Disable interrupts. */ 6301 IWN_WRITE(sc, IWN_INT_MASK, 0); 6302 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6303 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6304 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6305 6306 /* Make sure we no longer hold the NIC lock. */ 6307 iwn_nic_unlock(sc); 6308 6309 /* Stop TX scheduler. */ 6310 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6311 6312 /* Stop all DMA channels. */ 6313 if (iwn_nic_lock(sc) == 0) { 6314 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6315 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6316 for (ntries = 0; ntries < 200; ntries++) { 6317 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6318 IWN_FH_TX_STATUS_IDLE(chnl)) 6319 break; 6320 DELAY(10); 6321 } 6322 } 6323 iwn_nic_unlock(sc); 6324 } 6325 6326 /* Stop RX ring. */ 6327 iwn_reset_rx_ring(sc, &sc->rxq); 6328 6329 /* Reset all TX rings. */ 6330 for (qid = 0; qid < sc->ntxqs; qid++) 6331 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6332 6333 if (iwn_nic_lock(sc) == 0) { 6334 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6335 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6336 iwn_nic_unlock(sc); 6337 } 6338 DELAY(5); 6339 /* Power OFF adapter. */ 6340 iwn_apm_stop(sc); 6341 } 6342 6343 static int 6344 iwn_init(struct ifnet *ifp) 6345 { 6346 struct iwn_softc *sc = ifp->if_softc; 6347 struct ieee80211com *ic = &sc->sc_ic; 6348 int error; 6349 6350 mutex_enter(&sc->sc_mtx); 6351 if (sc->sc_flags & IWN_FLAG_HW_INITED) 6352 goto out; 6353 if ((error = iwn_hw_prepare(sc)) != 0) { 6354 aprint_error_dev(sc->sc_dev, 6355 "hardware not ready\n"); 6356 goto fail; 6357 } 6358 6359 /* Check that the radio is not disabled by hardware switch. */ 6360 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6361 aprint_error_dev(sc->sc_dev, 6362 "radio is disabled by hardware switch\n"); 6363 error = EPERM; /* :-) */ 6364 goto fail; 6365 } 6366 6367 /* Read firmware images from the filesystem. */ 6368 if ((error = iwn_read_firmware(sc)) != 0) { 6369 aprint_error_dev(sc->sc_dev, 6370 "could not read firmware\n"); 6371 goto fail; 6372 } 6373 6374 /* Initialize interrupt mask to default value. */ 6375 sc->int_mask = IWN_INT_MASK_DEF; 6376 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6377 6378 /* Initialize hardware and upload firmware. */ 6379 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 6380 error = iwn_hw_init(sc); 6381 firmware_free(sc->fw.data, sc->fw.size); 6382 sc->fw.data = NULL; 6383 sc->fw.size = 0; 6384 if (error != 0) { 6385 aprint_error_dev(sc->sc_dev, 6386 "could not initialize hardware\n"); 6387 goto fail; 6388 } 6389 6390 /* Configure adapter now that it is ready. */ 6391 if ((error = iwn_config(sc)) != 0) { 6392 aprint_error_dev(sc->sc_dev, 6393 "could not configure device\n"); 6394 goto fail; 6395 } 6396 6397 sc->sc_beacon_wait = 0; 6398 6399 ifp->if_flags &= ~IFF_OACTIVE; 6400 ifp->if_flags |= IFF_RUNNING; 6401 6402 if (ic->ic_opmode != IEEE80211_M_MONITOR) 6403 ieee80211_begin_scan(ic, 0); 6404 else 6405 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 6406 6407 sc->sc_flags |= IWN_FLAG_HW_INITED; 6408 out: 6409 mutex_exit(&sc->sc_mtx); 6410 return 0; 6411 6412 fail: mutex_exit(&sc->sc_mtx); 6413 iwn_stop(ifp, 1); 6414 return error; 6415 } 6416 6417 static void 6418 iwn_stop(struct ifnet *ifp, int disable) 6419 { 6420 struct iwn_softc *sc = ifp->if_softc; 6421 struct ieee80211com *ic = &sc->sc_ic; 6422 6423 if (!disable) 6424 mutex_enter(&sc->sc_mtx); 6425 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 6426 ifp->if_timer = sc->sc_tx_timer = 0; 6427 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6428 6429 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6430 6431 /* Power OFF hardware. */ 6432 iwn_hw_stop(sc); 6433 6434 if (!disable) 6435 mutex_exit(&sc->sc_mtx); 6436 } 6437 6438 /* 6439 * XXX MCLGETI alternative 6440 * 6441 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 6442 * as long as there are available free buffers then it uses MEXTMALLOC., 6443 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 6444 * The MCLGET4K code is used for testing an alternative mbuf cache. 6445 */ 6446 6447 static struct mbuf * 6448 MCLGETIalt(struct iwn_softc *sc, int how, 6449 struct ifnet *ifp __unused, u_int size) 6450 { 6451 struct mbuf *m; 6452 #ifdef IWN_USE_RBUF 6453 struct iwn_rbuf *rbuf; 6454 #endif 6455 6456 MGETHDR(m, how, MT_DATA); 6457 if (m == NULL) 6458 return NULL; 6459 6460 #ifdef IWN_USE_RBUF 6461 if (sc->rxq.nb_free_entries > 0 && 6462 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 6463 /* Attach buffer to mbuf header. */ 6464 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 6465 m->m_flags |= M_EXT_RW; 6466 } 6467 else { 6468 MEXTMALLOC(m, size, how); 6469 if ((m->m_flags & M_EXT) == 0) { 6470 m_freem(m); 6471 return NULL; 6472 } 6473 } 6474 6475 #else 6476 #ifdef MCLGET4K 6477 if (size == 4096) 6478 MCLGET4K(m, how); 6479 else 6480 panic("size must be 4k"); 6481 #else 6482 MEXTMALLOC(m, size, how); 6483 #endif 6484 if ((m->m_flags & M_EXT) == 0) { 6485 m_freem(m); 6486 return NULL; 6487 } 6488 #endif 6489 6490 return m; 6491 } 6492 6493 #ifdef IWN_USE_RBUF 6494 static struct iwn_rbuf * 6495 iwn_alloc_rbuf(struct iwn_softc *sc) 6496 { 6497 struct iwn_rbuf *rbuf; 6498 mutex_enter(&sc->rxq.freelist_mtx); 6499 6500 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6501 if (rbuf != NULL) { 6502 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6503 sc->rxq.nb_free_entries --; 6504 } 6505 mutex_exit(&sc->rxq.freelist_mtx); 6506 return rbuf; 6507 } 6508 6509 /* 6510 * This is called automatically by the network stack when the mbuf to which 6511 * our RX buffer is attached is freed. 6512 */ 6513 static void 6514 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6515 { 6516 struct iwn_rbuf *rbuf = arg; 6517 struct iwn_softc *sc = rbuf->sc; 6518 6519 /* Put the RX buffer back in the free list. */ 6520 mutex_enter(&sc->rxq.freelist_mtx); 6521 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6522 mutex_exit(&sc->rxq.freelist_mtx); 6523 6524 sc->rxq.nb_free_entries ++; 6525 if (__predict_true(m != NULL)) 6526 pool_cache_put(mb_cache, m); 6527 } 6528 6529 static int 6530 iwn_alloc_rpool(struct iwn_softc *sc) 6531 { 6532 struct iwn_rx_ring *ring = &sc->rxq; 6533 struct iwn_rbuf *rbuf; 6534 int i, error; 6535 6536 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6537 6538 /* Allocate a big chunk of DMA'able memory... */ 6539 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6540 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6541 if (error != 0) { 6542 aprint_error_dev(sc->sc_dev, 6543 "could not allocate RX buffers DMA memory\n"); 6544 return error; 6545 } 6546 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6547 SLIST_INIT(&ring->freelist); 6548 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6549 rbuf = &ring->rbuf[i]; 6550 6551 rbuf->sc = sc; /* Backpointer for callbacks. */ 6552 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6553 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6554 6555 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6556 } 6557 ring->nb_free_entries = IWN_RBUF_COUNT; 6558 return 0; 6559 } 6560 6561 static void 6562 iwn_free_rpool(struct iwn_softc *sc) 6563 { 6564 iwn_dma_contig_free(&sc->rxq.buf_dma); 6565 } 6566 #endif 6567 6568 /* 6569 * XXX: Hack to set the current channel to the value advertised in beacons or 6570 * probe responses. Only used during AP detection. 6571 * XXX: Duplicated from if_iwi.c 6572 */ 6573 static void 6574 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m, 6575 struct iwn_rx_stat *stat) 6576 { 6577 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6578 struct ieee80211_frame *wh; 6579 uint8_t subtype; 6580 uint8_t *frm, *efrm; 6581 6582 wh = mtod(m, struct ieee80211_frame *); 6583 6584 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6585 return; 6586 6587 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6588 6589 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6590 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6591 return; 6592 6593 if (sc->sc_flags & IWN_FLAG_SCANNING_5GHZ) { 6594 int chan = le16toh(stat->chan); 6595 if (chan < __arraycount(ic->ic_channels)) 6596 ic->ic_curchan = &ic->ic_channels[chan]; 6597 return; 6598 } 6599 6600 frm = (uint8_t *)(wh + 1); 6601 efrm = mtod(m, uint8_t *) + m->m_len; 6602 6603 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6604 while (frm < efrm) { 6605 if (*frm == IEEE80211_ELEMID_DSPARMS) 6606 #if IEEE80211_CHAN_MAX < 255 6607 if (frm[2] <= IEEE80211_CHAN_MAX) 6608 #endif 6609 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6610 6611 frm += frm[1] + 2; 6612 } 6613 } 6614 6615 #ifdef notyetMODULE 6616 6617 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci"); 6618 6619 #ifdef _MODULE 6620 #include "ioconf.c" 6621 #endif 6622 6623 static int 6624 if_iwn_modcmd(modcmd_t cmd, void *data) 6625 { 6626 int error = 0; 6627 6628 switch (cmd) { 6629 case MODULE_CMD_INIT: 6630 #ifdef _MODULE 6631 error = config_init_component(cfdriver_ioconf_if_iwn, 6632 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6633 #endif 6634 return error; 6635 case MODULE_CMD_FINI: 6636 #ifdef _MODULE 6637 error = config_fini_component(cfdriver_ioconf_if_iwn, 6638 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6639 #endif 6640 return error; 6641 case MODULE_CMD_AUTOUNLOAD: 6642 #ifdef _MODULE 6643 /* XXX This is not optional! */ 6644 #endif 6645 return error; 6646 default: 6647 return ENOTTY; 6648 } 6649 } 6650 #endif 6651
Indexes created Thu Oct 02 14:10:14 GMT 2025