if_iwn.c revision 1.75
1 /* $NetBSD: if_iwn.c,v 1.75 2015/08/24 23:52:18 pooka Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.75 2015/08/24 23:52:18 pooka Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #ifdef notyetMODULE 39 #include <sys/module.h> 40 #endif 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <sys/bus.h> 49 #include <machine/endian.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2, 107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1, 108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2, 109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1, 110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2, 111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1, 112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2, 113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1, 114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2, 115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1, 116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2, 117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1, 118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2, 119 }; 120 121 /* 122 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 123 */ 124 static const struct ieee80211_rateset iwn_rateset_11a = 125 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 126 127 static const struct ieee80211_rateset iwn_rateset_11b = 128 { 4, { 2, 4, 11, 22 } }; 129 130 static const struct ieee80211_rateset iwn_rateset_11g = 131 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 132 133 static int iwn_match(device_t , struct cfdata *, void *); 134 static void iwn_attach(device_t , device_t , void *); 135 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 136 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 137 static void iwn_radiotap_attach(struct iwn_softc *); 138 static int iwn_detach(device_t , int); 139 #if 0 140 static void iwn_power(int, void *); 141 #endif 142 static bool iwn_resume(device_t, const pmf_qual_t *); 143 static int iwn_nic_lock(struct iwn_softc *); 144 static int iwn_eeprom_lock(struct iwn_softc *); 145 static int iwn_init_otprom(struct iwn_softc *); 146 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 147 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 148 void **, bus_size_t, bus_size_t); 149 static void iwn_dma_contig_free(struct iwn_dma_info *); 150 static int iwn_alloc_sched(struct iwn_softc *); 151 static void iwn_free_sched(struct iwn_softc *); 152 static int iwn_alloc_kw(struct iwn_softc *); 153 static void iwn_free_kw(struct iwn_softc *); 154 static int iwn_alloc_ict(struct iwn_softc *); 155 static void iwn_free_ict(struct iwn_softc *); 156 static int iwn_alloc_fwmem(struct iwn_softc *); 157 static void iwn_free_fwmem(struct iwn_softc *); 158 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 159 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 160 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 161 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 162 int); 163 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 164 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 165 static void iwn5000_ict_reset(struct iwn_softc *); 166 static int iwn_read_eeprom(struct iwn_softc *); 167 static void iwn4965_read_eeprom(struct iwn_softc *); 168 169 #ifdef IWN_DEBUG 170 static void iwn4965_print_power_group(struct iwn_softc *, int); 171 #endif 172 static void iwn5000_read_eeprom(struct iwn_softc *); 173 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 174 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 175 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 176 static void iwn_newassoc(struct ieee80211_node *, int); 177 static int iwn_media_change(struct ifnet *); 178 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 179 static void iwn_iter_func(void *, struct ieee80211_node *); 180 static void iwn_calib_timeout(void *); 181 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 #ifndef IEEE80211_NO_HT 186 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 187 struct iwn_rx_data *); 188 #endif 189 static void iwn5000_rx_calib_results(struct iwn_softc *, 190 struct iwn_rx_desc *, struct iwn_rx_data *); 191 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 192 struct iwn_rx_data *); 193 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 194 struct iwn_rx_data *); 195 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 196 struct iwn_rx_data *); 197 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 198 uint8_t); 199 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 200 static void iwn_notif_intr(struct iwn_softc *); 201 static void iwn_wakeup_intr(struct iwn_softc *); 202 static void iwn_fatal_intr(struct iwn_softc *); 203 static int iwn_intr(void *); 204 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 205 uint16_t); 206 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 207 uint16_t); 208 #ifdef notyet 209 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 210 #endif 211 static int iwn_tx(struct iwn_softc *, struct mbuf *, 212 struct ieee80211_node *, int); 213 static void iwn_start(struct ifnet *); 214 static void iwn_watchdog(struct ifnet *); 215 static int iwn_ioctl(struct ifnet *, u_long, void *); 216 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 217 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 218 int); 219 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 220 int); 221 static int iwn_set_link_quality(struct iwn_softc *, 222 struct ieee80211_node *); 223 static int iwn_add_broadcast_node(struct iwn_softc *, int); 224 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 225 static int iwn_set_critical_temp(struct iwn_softc *); 226 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 227 static void iwn4965_power_calibration(struct iwn_softc *, int); 228 static int iwn4965_set_txpower(struct iwn_softc *, int); 229 static int iwn5000_set_txpower(struct iwn_softc *, int); 230 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 231 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 232 static int iwn_get_noise(const struct iwn_rx_general_stats *); 233 static int iwn4965_get_temperature(struct iwn_softc *); 234 static int iwn5000_get_temperature(struct iwn_softc *); 235 static int iwn_init_sensitivity(struct iwn_softc *); 236 static void iwn_collect_noise(struct iwn_softc *, 237 const struct iwn_rx_general_stats *); 238 static int iwn4965_init_gains(struct iwn_softc *); 239 static int iwn5000_init_gains(struct iwn_softc *); 240 static int iwn4965_set_gains(struct iwn_softc *); 241 static int iwn5000_set_gains(struct iwn_softc *); 242 static void iwn_tune_sensitivity(struct iwn_softc *, 243 const struct iwn_rx_stats *); 244 static int iwn_send_sensitivity(struct iwn_softc *); 245 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 246 static int iwn5000_runtime_calib(struct iwn_softc *); 247 248 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 249 static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 250 static int iwn_config_bt_coex_adv1(struct iwn_softc *); 251 static int iwn_config_bt_coex_adv2(struct iwn_softc *); 252 253 static int iwn_config(struct iwn_softc *); 254 static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, 255 uint8_t); 256 static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 257 static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 258 static int iwn_scan(struct iwn_softc *, uint16_t); 259 static int iwn_auth(struct iwn_softc *); 260 static int iwn_run(struct iwn_softc *); 261 #ifdef IWN_HWCRYPTO 262 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 263 struct ieee80211_key *); 264 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 265 struct ieee80211_key *); 266 #endif 267 static int iwn_wme_update(struct ieee80211com *); 268 #ifndef IEEE80211_NO_HT 269 static int iwn_ampdu_rx_start(struct ieee80211com *, 270 struct ieee80211_node *, uint8_t); 271 static void iwn_ampdu_rx_stop(struct ieee80211com *, 272 struct ieee80211_node *, uint8_t); 273 static int iwn_ampdu_tx_start(struct ieee80211com *, 274 struct ieee80211_node *, uint8_t); 275 static void iwn_ampdu_tx_stop(struct ieee80211com *, 276 struct ieee80211_node *, uint8_t); 277 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 278 struct ieee80211_node *, uint8_t, uint16_t); 279 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 280 uint8_t, uint16_t); 281 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 282 struct ieee80211_node *, uint8_t, uint16_t); 283 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 284 uint8_t, uint16_t); 285 #endif 286 static int iwn5000_query_calibration(struct iwn_softc *); 287 static int iwn5000_send_calibration(struct iwn_softc *); 288 static int iwn5000_send_wimax_coex(struct iwn_softc *); 289 static int iwn6000_temp_offset_calib(struct iwn_softc *); 290 static int iwn2000_temp_offset_calib(struct iwn_softc *); 291 static int iwn4965_post_alive(struct iwn_softc *); 292 static int iwn5000_post_alive(struct iwn_softc *); 293 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 294 int); 295 static int iwn4965_load_firmware(struct iwn_softc *); 296 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 297 const uint8_t *, int); 298 static int iwn5000_load_firmware(struct iwn_softc *); 299 static int iwn_read_firmware_leg(struct iwn_softc *, 300 struct iwn_fw_info *); 301 static int iwn_read_firmware_tlv(struct iwn_softc *, 302 struct iwn_fw_info *, uint16_t); 303 static int iwn_read_firmware(struct iwn_softc *); 304 static int iwn_clock_wait(struct iwn_softc *); 305 static int iwn_apm_init(struct iwn_softc *); 306 static void iwn_apm_stop_master(struct iwn_softc *); 307 static void iwn_apm_stop(struct iwn_softc *); 308 static int iwn4965_nic_config(struct iwn_softc *); 309 static int iwn5000_nic_config(struct iwn_softc *); 310 static int iwn_hw_prepare(struct iwn_softc *); 311 static int iwn_hw_init(struct iwn_softc *); 312 static void iwn_hw_stop(struct iwn_softc *); 313 static int iwn_init(struct ifnet *); 314 static void iwn_stop(struct ifnet *, int); 315 316 /* XXX MCLGETI alternative */ 317 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 318 struct ifnet *, u_int); 319 #ifdef IWN_USE_RBUF 320 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 321 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 322 static int iwn_alloc_rpool(struct iwn_softc *); 323 static void iwn_free_rpool(struct iwn_softc *); 324 #endif 325 326 /* XXX needed by iwn_scan */ 327 static u_int8_t *ieee80211_add_ssid(u_int8_t *, const u_int8_t *, u_int); 328 static u_int8_t *ieee80211_add_rates(u_int8_t *, 329 const struct ieee80211_rateset *); 330 static u_int8_t *ieee80211_add_xrates(u_int8_t *, 331 const struct ieee80211_rateset *); 332 333 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *); 334 335 #ifdef IWN_DEBUG 336 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 337 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 338 int iwn_debug = 0; 339 #else 340 #define DPRINTF(x) 341 #define DPRINTFN(n, x) 342 #endif 343 344 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 345 iwn_detach, NULL); 346 347 static int 348 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 349 { 350 struct pci_attach_args *pa = aux; 351 size_t i; 352 353 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 354 return 0; 355 356 for (i = 0; i < __arraycount(iwn_devices); i++) 357 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 358 return 1; 359 360 return 0; 361 } 362 363 static void 364 iwn_attach(device_t parent __unused, device_t self, void *aux) 365 { 366 struct iwn_softc *sc = device_private(self); 367 struct ieee80211com *ic = &sc->sc_ic; 368 struct ifnet *ifp = &sc->sc_ec.ec_if; 369 struct pci_attach_args *pa = aux; 370 const char *intrstr; 371 pci_intr_handle_t ih; 372 pcireg_t memtype, reg; 373 int i, error; 374 char intrbuf[PCI_INTRSTR_LEN]; 375 376 sc->sc_dev = self; 377 sc->sc_pct = pa->pa_pc; 378 sc->sc_pcitag = pa->pa_tag; 379 sc->sc_dmat = pa->pa_dmat; 380 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 381 382 callout_init(&sc->calib_to, 0); 383 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 384 385 pci_aprint_devinfo(pa, NULL); 386 387 /* 388 * Get the offset of the PCI Express Capability Structure in PCI 389 * Configuration Space. 390 */ 391 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 392 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 393 if (error == 0) { 394 aprint_error_dev(self, 395 "PCIe capability structure not found!\n"); 396 return; 397 } 398 399 /* Clear device-specific "PCI retry timeout" register (41h). */ 400 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 401 if (reg & 0xff00) 402 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 403 404 /* Enable bus-mastering and hardware bug workaround. */ 405 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 406 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 407 reg |= PCI_COMMAND_MASTER_ENABLE; 408 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 409 DPRINTF(("PCIe INTx Disable set\n")); 410 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 411 } 412 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 413 414 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 415 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 416 &sc->sc_sh, NULL, &sc->sc_sz); 417 if (error != 0) { 418 aprint_error_dev(self, "can't map mem space\n"); 419 return; 420 } 421 422 /* Install interrupt handler. */ 423 if (pci_intr_map(pa, &ih) != 0) { 424 aprint_error_dev(self, "can't map interrupt\n"); 425 return; 426 } 427 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 428 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc); 429 if (sc->sc_ih == NULL) { 430 aprint_error_dev(self, "can't establish interrupt"); 431 if (intrstr != NULL) 432 aprint_error(" at %s", intrstr); 433 aprint_error("\n"); 434 return; 435 } 436 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 437 438 /* Read hardware revision and attach. */ 439 sc->hw_type = 440 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK) 441 >> IWN_HW_REV_TYPE_SHIFT; 442 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 443 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 444 else 445 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 446 if (error != 0) { 447 aprint_error_dev(self, "could not attach device\n"); 448 return; 449 } 450 451 if ((error = iwn_hw_prepare(sc)) != 0) { 452 aprint_error_dev(self, "hardware not ready\n"); 453 return; 454 } 455 456 /* Read MAC address, channels, etc from EEPROM. */ 457 if ((error = iwn_read_eeprom(sc)) != 0) { 458 aprint_error_dev(self, "could not read EEPROM\n"); 459 return; 460 } 461 462 /* Allocate DMA memory for firmware transfers. */ 463 if ((error = iwn_alloc_fwmem(sc)) != 0) { 464 aprint_error_dev(self, 465 "could not allocate memory for firmware\n"); 466 return; 467 } 468 469 /* Allocate "Keep Warm" page. */ 470 if ((error = iwn_alloc_kw(sc)) != 0) { 471 aprint_error_dev(self, "could not allocate keep warm page\n"); 472 goto fail1; 473 } 474 475 /* Allocate ICT table for 5000 Series. */ 476 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 477 (error = iwn_alloc_ict(sc)) != 0) { 478 aprint_error_dev(self, "could not allocate ICT table\n"); 479 goto fail2; 480 } 481 482 /* Allocate TX scheduler "rings". */ 483 if ((error = iwn_alloc_sched(sc)) != 0) { 484 aprint_error_dev(self, 485 "could not allocate TX scheduler rings\n"); 486 goto fail3; 487 } 488 489 #ifdef IWN_USE_RBUF 490 /* Allocate RX buffers. */ 491 if ((error = iwn_alloc_rpool(sc)) != 0) { 492 aprint_error_dev(self, "could not allocate RX buffers\n"); 493 goto fail3; 494 } 495 #endif 496 497 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 498 for (i = 0; i < sc->ntxqs; i++) { 499 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 500 aprint_error_dev(self, 501 "could not allocate TX ring %d\n", i); 502 goto fail4; 503 } 504 } 505 506 /* Allocate RX ring. */ 507 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 508 aprint_error_dev(self, "could not allocate RX ring\n"); 509 goto fail4; 510 } 511 512 /* Clear pending interrupts. */ 513 IWN_WRITE(sc, IWN_INT, 0xffffffff); 514 515 /* Count the number of available chains. */ 516 sc->ntxchains = 517 ((sc->txchainmask >> 2) & 1) + 518 ((sc->txchainmask >> 1) & 1) + 519 ((sc->txchainmask >> 0) & 1); 520 sc->nrxchains = 521 ((sc->rxchainmask >> 2) & 1) + 522 ((sc->rxchainmask >> 1) & 1) + 523 ((sc->rxchainmask >> 0) & 1); 524 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 525 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 526 ether_sprintf(ic->ic_myaddr)); 527 528 ic->ic_ifp = ifp; 529 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 530 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 531 ic->ic_state = IEEE80211_S_INIT; 532 533 /* Set device capabilities. */ 534 /* XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, 535 * and IEEE80211_C_PMGT too. */ 536 ic->ic_caps = 537 IEEE80211_C_IBSS | /* IBSS mode support */ 538 IEEE80211_C_WPA | /* 802.11i */ 539 IEEE80211_C_MONITOR | /* monitor mode supported */ 540 IEEE80211_C_TXPMGT | /* tx power management */ 541 IEEE80211_C_SHSLOT | /* short slot time supported */ 542 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 543 IEEE80211_C_WME; /* 802.11e */ 544 545 #ifndef IEEE80211_NO_HT 546 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 547 /* Set HT capabilities. */ 548 ic->ic_htcaps = 549 #if IWN_RBUF_SIZE == 8192 550 IEEE80211_HTCAP_AMSDU7935 | 551 #endif 552 IEEE80211_HTCAP_CBW20_40 | 553 IEEE80211_HTCAP_SGI20 | 554 IEEE80211_HTCAP_SGI40; 555 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 556 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 557 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 558 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 559 else 560 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 561 } 562 #endif /* !IEEE80211_NO_HT */ 563 564 /* Set supported legacy rates. */ 565 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwn_rateset_11b; 566 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwn_rateset_11g; 567 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 568 ic->ic_sup_rates[IEEE80211_MODE_11A] = iwn_rateset_11a; 569 } 570 #ifndef IEEE80211_NO_HT 571 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 572 /* Set supported HT rates. */ 573 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 574 if (sc->nrxchains > 1) 575 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 576 if (sc->nrxchains > 2) 577 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 578 } 579 #endif 580 581 /* IBSS channel undefined for now. */ 582 ic->ic_ibss_chan = &ic->ic_channels[0]; 583 584 ifp->if_softc = sc; 585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 586 ifp->if_init = iwn_init; 587 ifp->if_ioctl = iwn_ioctl; 588 ifp->if_start = iwn_start; 589 ifp->if_stop = iwn_stop; 590 ifp->if_watchdog = iwn_watchdog; 591 IFQ_SET_READY(&ifp->if_snd); 592 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 593 594 if_attach(ifp); 595 ieee80211_ifattach(ic); 596 ic->ic_node_alloc = iwn_node_alloc; 597 ic->ic_newassoc = iwn_newassoc; 598 #ifdef IWN_HWCRYPTO 599 ic->ic_crypto.cs_key_set = iwn_set_key; 600 ic->ic_crypto.cs_key_delete = iwn_delete_key; 601 #endif 602 ic->ic_wme.wme_update = iwn_wme_update; 603 #ifndef IEEE80211_NO_HT 604 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 605 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 606 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 607 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 608 #endif 609 610 /* Override 802.11 state transition machine. */ 611 sc->sc_newstate = ic->ic_newstate; 612 ic->ic_newstate = iwn_newstate; 613 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 614 615 sc->amrr.amrr_min_success_threshold = 1; 616 sc->amrr.amrr_max_success_threshold = 15; 617 618 iwn_radiotap_attach(sc); 619 620 /* 621 * XXX for NetBSD, OpenBSD timeout_set replaced by 622 * callout_init and callout_setfunc, above. 623 */ 624 625 if (pmf_device_register(self, NULL, iwn_resume)) 626 pmf_class_network_register(self, ifp); 627 else 628 aprint_error_dev(self, "couldn't establish power handler\n"); 629 630 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 631 ieee80211_announce(ic); 632 633 return; 634 635 /* Free allocated memory if something failed during attachment. */ 636 fail4: while (--i >= 0) 637 iwn_free_tx_ring(sc, &sc->txq[i]); 638 #ifdef IWN_USE_RBUF 639 iwn_free_rpool(sc); 640 #endif 641 iwn_free_sched(sc); 642 fail3: if (sc->ict != NULL) 643 iwn_free_ict(sc); 644 fail2: iwn_free_kw(sc); 645 fail1: iwn_free_fwmem(sc); 646 } 647 648 int 649 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 650 { 651 struct iwn_ops *ops = &sc->ops; 652 653 ops->load_firmware = iwn4965_load_firmware; 654 ops->read_eeprom = iwn4965_read_eeprom; 655 ops->post_alive = iwn4965_post_alive; 656 ops->nic_config = iwn4965_nic_config; 657 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 658 ops->update_sched = iwn4965_update_sched; 659 ops->get_temperature = iwn4965_get_temperature; 660 ops->get_rssi = iwn4965_get_rssi; 661 ops->set_txpower = iwn4965_set_txpower; 662 ops->init_gains = iwn4965_init_gains; 663 ops->set_gains = iwn4965_set_gains; 664 ops->add_node = iwn4965_add_node; 665 ops->tx_done = iwn4965_tx_done; 666 #ifndef IEEE80211_NO_HT 667 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 668 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 669 #endif 670 sc->ntxqs = IWN4965_NTXQUEUES; 671 sc->ndmachnls = IWN4965_NDMACHNLS; 672 sc->broadcast_id = IWN4965_ID_BROADCAST; 673 sc->rxonsz = IWN4965_RXONSZ; 674 sc->schedsz = IWN4965_SCHEDSZ; 675 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 676 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 677 sc->fwsz = IWN4965_FWSZ; 678 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 679 sc->limits = &iwn4965_sensitivity_limits; 680 sc->fwname = "iwlwifi-4965-2.ucode"; 681 /* Override chains masks, ROM is known to be broken. */ 682 sc->txchainmask = IWN_ANT_AB; 683 sc->rxchainmask = IWN_ANT_ABC; 684 685 return 0; 686 } 687 688 int 689 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 690 { 691 struct iwn_ops *ops = &sc->ops; 692 693 ops->load_firmware = iwn5000_load_firmware; 694 ops->read_eeprom = iwn5000_read_eeprom; 695 ops->post_alive = iwn5000_post_alive; 696 ops->nic_config = iwn5000_nic_config; 697 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 698 ops->update_sched = iwn5000_update_sched; 699 ops->get_temperature = iwn5000_get_temperature; 700 ops->get_rssi = iwn5000_get_rssi; 701 ops->set_txpower = iwn5000_set_txpower; 702 ops->init_gains = iwn5000_init_gains; 703 ops->set_gains = iwn5000_set_gains; 704 ops->add_node = iwn5000_add_node; 705 ops->tx_done = iwn5000_tx_done; 706 #ifndef IEEE80211_NO_HT 707 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 708 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 709 #endif 710 sc->ntxqs = IWN5000_NTXQUEUES; 711 sc->ndmachnls = IWN5000_NDMACHNLS; 712 sc->broadcast_id = IWN5000_ID_BROADCAST; 713 sc->rxonsz = IWN5000_RXONSZ; 714 sc->schedsz = IWN5000_SCHEDSZ; 715 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 716 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 717 sc->fwsz = IWN5000_FWSZ; 718 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 719 720 switch (sc->hw_type) { 721 case IWN_HW_REV_TYPE_5100: 722 sc->limits = &iwn5000_sensitivity_limits; 723 sc->fwname = "iwlwifi-5000-2.ucode"; 724 /* Override chains masks, ROM is known to be broken. */ 725 sc->txchainmask = IWN_ANT_B; 726 sc->rxchainmask = IWN_ANT_AB; 727 break; 728 case IWN_HW_REV_TYPE_5150: 729 sc->limits = &iwn5150_sensitivity_limits; 730 sc->fwname = "iwlwifi-5150-2.ucode"; 731 break; 732 case IWN_HW_REV_TYPE_5300: 733 case IWN_HW_REV_TYPE_5350: 734 sc->limits = &iwn5000_sensitivity_limits; 735 sc->fwname = "iwlwifi-5000-2.ucode"; 736 break; 737 case IWN_HW_REV_TYPE_1000: 738 sc->limits = &iwn1000_sensitivity_limits; 739 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 || 740 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2) 741 sc->fwname = "iwlwifi-100-5.ucode"; 742 else 743 sc->fwname = "iwlwifi-1000-3.ucode"; 744 break; 745 case IWN_HW_REV_TYPE_6000: 746 sc->limits = &iwn6000_sensitivity_limits; 747 sc->fwname = "iwlwifi-6000-4.ucode"; 748 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 749 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 750 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 751 /* Override chains masks, ROM is known to be broken. */ 752 sc->txchainmask = IWN_ANT_BC; 753 sc->rxchainmask = IWN_ANT_BC; 754 } 755 break; 756 case IWN_HW_REV_TYPE_6050: 757 sc->limits = &iwn6000_sensitivity_limits; 758 sc->fwname = "iwlwifi-6050-5.ucode"; 759 break; 760 case IWN_HW_REV_TYPE_6005: 761 sc->limits = &iwn6000_sensitivity_limits; 762 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 763 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 764 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 765 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 766 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 767 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 || 768 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) { 769 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 770 ops->config_bt_coex = iwn_config_bt_coex_adv1; 771 } 772 else 773 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 774 break; 775 case IWN_HW_REV_TYPE_2030: 776 sc->limits = &iwn2000_sensitivity_limits; 777 sc->fwname = "iwlwifi-2030-6.ucode"; 778 ops->config_bt_coex = iwn_config_bt_coex_adv2; 779 break; 780 case IWN_HW_REV_TYPE_2000: 781 sc->limits = &iwn2000_sensitivity_limits; 782 sc->fwname = "iwlwifi-2000-6.ucode"; 783 break; 784 case IWN_HW_REV_TYPE_135: 785 sc->limits = &iwn2000_sensitivity_limits; 786 sc->fwname = "iwlwifi-135-6.ucode"; 787 ops->config_bt_coex = iwn_config_bt_coex_adv2; 788 break; 789 case IWN_HW_REV_TYPE_105: 790 sc->limits = &iwn2000_sensitivity_limits; 791 sc->fwname = "iwlwifi-105-6.ucode"; 792 break; 793 default: 794 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 795 return ENOTSUP; 796 } 797 return 0; 798 } 799 800 /* 801 * Attach the interface to 802.11 radiotap. 802 */ 803 static void 804 iwn_radiotap_attach(struct iwn_softc *sc) 805 { 806 struct ifnet *ifp = sc->sc_ic.ic_ifp; 807 808 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 809 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 810 &sc->sc_drvbpf); 811 812 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 813 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 814 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 815 816 sc->sc_txtap_len = sizeof sc->sc_txtapu; 817 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 818 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 819 } 820 821 static int 822 iwn_detach(device_t self, int flags __unused) 823 { 824 struct iwn_softc *sc = device_private(self); 825 struct ifnet *ifp = sc->sc_ic.ic_ifp; 826 int qid; 827 828 callout_stop(&sc->calib_to); 829 830 /* Uninstall interrupt handler. */ 831 if (sc->sc_ih != NULL) 832 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 833 834 /* Free DMA resources. */ 835 iwn_free_rx_ring(sc, &sc->rxq); 836 for (qid = 0; qid < sc->ntxqs; qid++) 837 iwn_free_tx_ring(sc, &sc->txq[qid]); 838 #ifdef IWN_USE_RBUF 839 iwn_free_rpool(sc); 840 #endif 841 iwn_free_sched(sc); 842 iwn_free_kw(sc); 843 if (sc->ict != NULL) 844 iwn_free_ict(sc); 845 iwn_free_fwmem(sc); 846 847 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 848 849 ieee80211_ifdetach(&sc->sc_ic); 850 if_detach(ifp); 851 852 return 0; 853 } 854 855 #if 0 856 /* 857 * XXX Investigate if clearing the PCI retry timeout could eliminate 858 * the repeated scan calls. Also the calls to if_init and if_start 859 * are similar to the effect of adding the call to ifioctl_common . 860 */ 861 static void 862 iwn_power(int why, void *arg) 863 { 864 struct iwn_softc *sc = arg; 865 struct ifnet *ifp; 866 pcireg_t reg; 867 int s; 868 869 if (why != PWR_RESUME) 870 return; 871 872 /* Clear device-specific "PCI retry timeout" register (41h). */ 873 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 874 if (reg & 0xff00) 875 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 876 877 s = splnet(); 878 ifp = &sc->sc_ic.ic_if; 879 if (ifp->if_flags & IFF_UP) { 880 ifp->if_init(ifp); 881 if (ifp->if_flags & IFF_RUNNING) 882 ifp->if_start(ifp); 883 } 884 splx(s); 885 } 886 #endif 887 888 static bool 889 iwn_resume(device_t dv, const pmf_qual_t *qual) 890 { 891 return true; 892 } 893 894 static int 895 iwn_nic_lock(struct iwn_softc *sc) 896 { 897 int ntries; 898 899 /* Request exclusive access to NIC. */ 900 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 901 902 /* Spin until we actually get the lock. */ 903 for (ntries = 0; ntries < 1000; ntries++) { 904 if ((IWN_READ(sc, IWN_GP_CNTRL) & 905 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 906 IWN_GP_CNTRL_MAC_ACCESS_ENA) 907 return 0; 908 DELAY(10); 909 } 910 return ETIMEDOUT; 911 } 912 913 static __inline void 914 iwn_nic_unlock(struct iwn_softc *sc) 915 { 916 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 917 } 918 919 static __inline uint32_t 920 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 921 { 922 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 923 IWN_BARRIER_READ_WRITE(sc); 924 return IWN_READ(sc, IWN_PRPH_RDATA); 925 } 926 927 static __inline void 928 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 929 { 930 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 931 IWN_BARRIER_WRITE(sc); 932 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 933 } 934 935 static __inline void 936 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 937 { 938 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 939 } 940 941 static __inline void 942 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 943 { 944 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 945 } 946 947 static __inline void 948 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 949 const uint32_t *data, int count) 950 { 951 for (; count > 0; count--, data++, addr += 4) 952 iwn_prph_write(sc, addr, *data); 953 } 954 955 static __inline uint32_t 956 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 957 { 958 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 959 IWN_BARRIER_READ_WRITE(sc); 960 return IWN_READ(sc, IWN_MEM_RDATA); 961 } 962 963 static __inline void 964 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 965 { 966 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 967 IWN_BARRIER_WRITE(sc); 968 IWN_WRITE(sc, IWN_MEM_WDATA, data); 969 } 970 971 #ifndef IEEE80211_NO_HT 972 static __inline void 973 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 974 { 975 uint32_t tmp; 976 977 tmp = iwn_mem_read(sc, addr & ~3); 978 if (addr & 3) 979 tmp = (tmp & 0x0000ffff) | data << 16; 980 else 981 tmp = (tmp & 0xffff0000) | data; 982 iwn_mem_write(sc, addr & ~3, tmp); 983 } 984 #endif 985 986 static __inline void 987 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 988 int count) 989 { 990 for (; count > 0; count--, addr += 4) 991 *data++ = iwn_mem_read(sc, addr); 992 } 993 994 static __inline void 995 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 996 int count) 997 { 998 for (; count > 0; count--, addr += 4) 999 iwn_mem_write(sc, addr, val); 1000 } 1001 1002 static int 1003 iwn_eeprom_lock(struct iwn_softc *sc) 1004 { 1005 int i, ntries; 1006 1007 for (i = 0; i < 100; i++) { 1008 /* Request exclusive access to EEPROM. */ 1009 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1010 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1011 1012 /* Spin until we actually get the lock. */ 1013 for (ntries = 0; ntries < 100; ntries++) { 1014 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1015 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1016 return 0; 1017 DELAY(10); 1018 } 1019 } 1020 return ETIMEDOUT; 1021 } 1022 1023 static __inline void 1024 iwn_eeprom_unlock(struct iwn_softc *sc) 1025 { 1026 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1027 } 1028 1029 /* 1030 * Initialize access by host to One Time Programmable ROM. 1031 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1032 */ 1033 static int 1034 iwn_init_otprom(struct iwn_softc *sc) 1035 { 1036 uint16_t prev = 0, base, next; 1037 int count, error; 1038 1039 /* Wait for clock stabilization before accessing prph. */ 1040 if ((error = iwn_clock_wait(sc)) != 0) 1041 return error; 1042 1043 if ((error = iwn_nic_lock(sc)) != 0) 1044 return error; 1045 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1046 DELAY(5); 1047 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1048 iwn_nic_unlock(sc); 1049 1050 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1051 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1052 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1053 IWN_RESET_LINK_PWR_MGMT_DIS); 1054 } 1055 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1056 /* Clear ECC status. */ 1057 IWN_SETBITS(sc, IWN_OTP_GP, 1058 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1059 1060 /* 1061 * Find the block before last block (contains the EEPROM image) 1062 * for HW without OTP shadow RAM. 1063 */ 1064 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1065 /* Switch to absolute addressing mode. */ 1066 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1067 base = 0; 1068 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1069 error = iwn_read_prom_data(sc, base, &next, 2); 1070 if (error != 0) 1071 return error; 1072 if (next == 0) /* End of linked-list. */ 1073 break; 1074 prev = base; 1075 base = le16toh(next); 1076 } 1077 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1078 return EIO; 1079 /* Skip "next" word. */ 1080 sc->prom_base = prev + 1; 1081 } 1082 return 0; 1083 } 1084 1085 static int 1086 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1087 { 1088 uint8_t *out = data; 1089 uint32_t val, tmp; 1090 int ntries; 1091 1092 addr += sc->prom_base; 1093 for (; count > 0; count -= 2, addr++) { 1094 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1095 for (ntries = 0; ntries < 10; ntries++) { 1096 val = IWN_READ(sc, IWN_EEPROM); 1097 if (val & IWN_EEPROM_READ_VALID) 1098 break; 1099 DELAY(5); 1100 } 1101 if (ntries == 10) { 1102 aprint_error_dev(sc->sc_dev, 1103 "timeout reading ROM at 0x%x\n", addr); 1104 return ETIMEDOUT; 1105 } 1106 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1107 /* OTPROM, check for ECC errors. */ 1108 tmp = IWN_READ(sc, IWN_OTP_GP); 1109 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1110 aprint_error_dev(sc->sc_dev, 1111 "OTPROM ECC error at 0x%x\n", addr); 1112 return EIO; 1113 } 1114 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1115 /* Correctable ECC error, clear bit. */ 1116 IWN_SETBITS(sc, IWN_OTP_GP, 1117 IWN_OTP_GP_ECC_CORR_STTS); 1118 } 1119 } 1120 *out++ = val >> 16; 1121 if (count > 1) 1122 *out++ = val >> 24; 1123 } 1124 return 0; 1125 } 1126 1127 static int 1128 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1129 bus_size_t size, bus_size_t alignment) 1130 { 1131 int nsegs, error; 1132 1133 dma->tag = tag; 1134 dma->size = size; 1135 1136 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1137 &dma->map); 1138 if (error != 0) 1139 goto fail; 1140 1141 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1142 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1143 if (error != 0) 1144 goto fail; 1145 1146 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1147 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1148 if (error != 0) 1149 goto fail; 1150 1151 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1152 BUS_DMA_NOWAIT); 1153 if (error != 0) 1154 goto fail; 1155 1156 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1157 memset(dma->vaddr, 0, size); 1158 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1159 1160 dma->paddr = dma->map->dm_segs[0].ds_addr; 1161 if (kvap != NULL) 1162 *kvap = dma->vaddr; 1163 1164 return 0; 1165 1166 fail: iwn_dma_contig_free(dma); 1167 return error; 1168 } 1169 1170 static void 1171 iwn_dma_contig_free(struct iwn_dma_info *dma) 1172 { 1173 if (dma->map != NULL) { 1174 if (dma->vaddr != NULL) { 1175 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1176 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1177 bus_dmamap_unload(dma->tag, dma->map); 1178 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1179 bus_dmamem_free(dma->tag, &dma->seg, 1); 1180 dma->vaddr = NULL; 1181 } 1182 bus_dmamap_destroy(dma->tag, dma->map); 1183 dma->map = NULL; 1184 } 1185 } 1186 1187 static int 1188 iwn_alloc_sched(struct iwn_softc *sc) 1189 { 1190 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1191 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1192 (void **)&sc->sched, sc->schedsz, 1024); 1193 } 1194 1195 static void 1196 iwn_free_sched(struct iwn_softc *sc) 1197 { 1198 iwn_dma_contig_free(&sc->sched_dma); 1199 } 1200 1201 static int 1202 iwn_alloc_kw(struct iwn_softc *sc) 1203 { 1204 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1205 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1206 4096); 1207 } 1208 1209 static void 1210 iwn_free_kw(struct iwn_softc *sc) 1211 { 1212 iwn_dma_contig_free(&sc->kw_dma); 1213 } 1214 1215 static int 1216 iwn_alloc_ict(struct iwn_softc *sc) 1217 { 1218 /* ICT table must be aligned on a 4KB boundary. */ 1219 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1220 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1221 } 1222 1223 static void 1224 iwn_free_ict(struct iwn_softc *sc) 1225 { 1226 iwn_dma_contig_free(&sc->ict_dma); 1227 } 1228 1229 static int 1230 iwn_alloc_fwmem(struct iwn_softc *sc) 1231 { 1232 /* Must be aligned on a 16-byte boundary. */ 1233 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1234 sc->fwsz, 16); 1235 } 1236 1237 static void 1238 iwn_free_fwmem(struct iwn_softc *sc) 1239 { 1240 iwn_dma_contig_free(&sc->fw_dma); 1241 } 1242 1243 static int 1244 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1245 { 1246 bus_size_t size; 1247 int i, error; 1248 1249 ring->cur = 0; 1250 1251 /* Allocate RX descriptors (256-byte aligned). */ 1252 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1253 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1254 (void **)&ring->desc, size, 256); 1255 if (error != 0) { 1256 aprint_error_dev(sc->sc_dev, 1257 "could not allocate RX ring DMA memory\n"); 1258 goto fail; 1259 } 1260 1261 /* Allocate RX status area (16-byte aligned). */ 1262 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1263 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1264 if (error != 0) { 1265 aprint_error_dev(sc->sc_dev, 1266 "could not allocate RX status DMA memory\n"); 1267 goto fail; 1268 } 1269 1270 /* 1271 * Allocate and map RX buffers. 1272 */ 1273 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1274 struct iwn_rx_data *data = &ring->data[i]; 1275 1276 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1277 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1278 &data->map); 1279 if (error != 0) { 1280 aprint_error_dev(sc->sc_dev, 1281 "could not create RX buf DMA map\n"); 1282 goto fail; 1283 } 1284 1285 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1286 if (data->m == NULL) { 1287 aprint_error_dev(sc->sc_dev, 1288 "could not allocate RX mbuf\n"); 1289 error = ENOBUFS; 1290 goto fail; 1291 } 1292 1293 error = bus_dmamap_load(sc->sc_dmat, data->map, 1294 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1295 BUS_DMA_NOWAIT | BUS_DMA_READ); 1296 if (error != 0) { 1297 aprint_error_dev(sc->sc_dev, 1298 "can't not map mbuf (error %d)\n", error); 1299 goto fail; 1300 } 1301 1302 /* Set physical address of RX buffer (256-byte aligned). */ 1303 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1304 } 1305 1306 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1307 BUS_DMASYNC_PREWRITE); 1308 1309 return 0; 1310 1311 fail: iwn_free_rx_ring(sc, ring); 1312 return error; 1313 } 1314 1315 static void 1316 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1317 { 1318 int ntries; 1319 1320 if (iwn_nic_lock(sc) == 0) { 1321 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1322 for (ntries = 0; ntries < 1000; ntries++) { 1323 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1324 IWN_FH_RX_STATUS_IDLE) 1325 break; 1326 DELAY(10); 1327 } 1328 iwn_nic_unlock(sc); 1329 } 1330 ring->cur = 0; 1331 sc->last_rx_valid = 0; 1332 } 1333 1334 static void 1335 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1336 { 1337 int i; 1338 1339 iwn_dma_contig_free(&ring->desc_dma); 1340 iwn_dma_contig_free(&ring->stat_dma); 1341 1342 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1343 struct iwn_rx_data *data = &ring->data[i]; 1344 1345 if (data->m != NULL) { 1346 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1347 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1348 bus_dmamap_unload(sc->sc_dmat, data->map); 1349 m_freem(data->m); 1350 } 1351 if (data->map != NULL) 1352 bus_dmamap_destroy(sc->sc_dmat, data->map); 1353 } 1354 } 1355 1356 static int 1357 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1358 { 1359 bus_addr_t paddr; 1360 bus_size_t size; 1361 int i, error; 1362 1363 ring->qid = qid; 1364 ring->queued = 0; 1365 ring->cur = 0; 1366 1367 /* Allocate TX descriptors (256-byte aligned). */ 1368 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1369 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1370 (void **)&ring->desc, size, 256); 1371 if (error != 0) { 1372 aprint_error_dev(sc->sc_dev, 1373 "could not allocate TX ring DMA memory\n"); 1374 goto fail; 1375 } 1376 /* 1377 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1378 * to allocate commands space for other rings. 1379 * XXX Do we really need to allocate descriptors for other rings? 1380 */ 1381 if (qid > 4) 1382 return 0; 1383 1384 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1385 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1386 (void **)&ring->cmd, size, 4); 1387 if (error != 0) { 1388 aprint_error_dev(sc->sc_dev, 1389 "could not allocate TX cmd DMA memory\n"); 1390 goto fail; 1391 } 1392 1393 paddr = ring->cmd_dma.paddr; 1394 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1395 struct iwn_tx_data *data = &ring->data[i]; 1396 1397 data->cmd_paddr = paddr; 1398 data->scratch_paddr = paddr + 12; 1399 paddr += sizeof (struct iwn_tx_cmd); 1400 1401 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1402 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1403 &data->map); 1404 if (error != 0) { 1405 aprint_error_dev(sc->sc_dev, 1406 "could not create TX buf DMA map\n"); 1407 goto fail; 1408 } 1409 } 1410 return 0; 1411 1412 fail: iwn_free_tx_ring(sc, ring); 1413 return error; 1414 } 1415 1416 static void 1417 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1418 { 1419 int i; 1420 1421 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1422 struct iwn_tx_data *data = &ring->data[i]; 1423 1424 if (data->m != NULL) { 1425 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1426 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1427 bus_dmamap_unload(sc->sc_dmat, data->map); 1428 m_freem(data->m); 1429 data->m = NULL; 1430 } 1431 } 1432 /* Clear TX descriptors. */ 1433 memset(ring->desc, 0, ring->desc_dma.size); 1434 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1435 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1436 sc->qfullmsk &= ~(1 << ring->qid); 1437 ring->queued = 0; 1438 ring->cur = 0; 1439 } 1440 1441 static void 1442 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1443 { 1444 int i; 1445 1446 iwn_dma_contig_free(&ring->desc_dma); 1447 iwn_dma_contig_free(&ring->cmd_dma); 1448 1449 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1450 struct iwn_tx_data *data = &ring->data[i]; 1451 1452 if (data->m != NULL) { 1453 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1454 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1455 bus_dmamap_unload(sc->sc_dmat, data->map); 1456 m_freem(data->m); 1457 } 1458 if (data->map != NULL) 1459 bus_dmamap_destroy(sc->sc_dmat, data->map); 1460 } 1461 } 1462 1463 static void 1464 iwn5000_ict_reset(struct iwn_softc *sc) 1465 { 1466 /* Disable interrupts. */ 1467 IWN_WRITE(sc, IWN_INT_MASK, 0); 1468 1469 /* Reset ICT table. */ 1470 memset(sc->ict, 0, IWN_ICT_SIZE); 1471 sc->ict_cur = 0; 1472 1473 /* Set physical address of ICT table (4KB aligned). */ 1474 DPRINTF(("enabling ICT\n")); 1475 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1476 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1477 1478 /* Enable periodic RX interrupt. */ 1479 sc->int_mask |= IWN_INT_RX_PERIODIC; 1480 /* Switch to ICT interrupt mode in driver. */ 1481 sc->sc_flags |= IWN_FLAG_USE_ICT; 1482 1483 /* Re-enable interrupts. */ 1484 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1485 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1486 } 1487 1488 static int 1489 iwn_read_eeprom(struct iwn_softc *sc) 1490 { 1491 struct iwn_ops *ops = &sc->ops; 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 uint16_t val; 1494 int error; 1495 1496 /* Check whether adapter has an EEPROM or an OTPROM. */ 1497 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1498 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1499 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1500 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1501 "OTPROM" : "EEPROM")); 1502 1503 /* Adapter has to be powered on for EEPROM access to work. */ 1504 if ((error = iwn_apm_init(sc)) != 0) { 1505 aprint_error_dev(sc->sc_dev, 1506 "could not power ON adapter\n"); 1507 return error; 1508 } 1509 1510 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1511 aprint_error_dev(sc->sc_dev, 1512 "bad ROM signature\n"); 1513 return EIO; 1514 } 1515 if ((error = iwn_eeprom_lock(sc)) != 0) { 1516 aprint_error_dev(sc->sc_dev, 1517 "could not lock ROM (error=%d)\n", error); 1518 return error; 1519 } 1520 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1521 if ((error = iwn_init_otprom(sc)) != 0) { 1522 aprint_error_dev(sc->sc_dev, 1523 "could not initialize OTPROM\n"); 1524 return error; 1525 } 1526 } 1527 1528 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1529 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1530 /* Check if HT support is bonded out. */ 1531 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1532 sc->sc_flags |= IWN_FLAG_HAS_11N; 1533 1534 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1535 sc->rfcfg = le16toh(val); 1536 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1537 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1538 if (sc->txchainmask == 0) 1539 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1540 if (sc->rxchainmask == 0) 1541 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1542 1543 /* Read MAC address. */ 1544 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1545 1546 /* Read adapter-specific information from EEPROM. */ 1547 ops->read_eeprom(sc); 1548 1549 iwn_apm_stop(sc); /* Power OFF adapter. */ 1550 1551 iwn_eeprom_unlock(sc); 1552 return 0; 1553 } 1554 1555 static void 1556 iwn4965_read_eeprom(struct iwn_softc *sc) 1557 { 1558 uint32_t addr; 1559 uint16_t val; 1560 int i; 1561 1562 /* Read regulatory domain (4 ASCII characters). */ 1563 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1564 1565 /* Read the list of authorized channels (20MHz ones only). */ 1566 for (i = 0; i < 5; i++) { 1567 addr = iwn4965_regulatory_bands[i]; 1568 iwn_read_eeprom_channels(sc, i, addr); 1569 } 1570 1571 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1572 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1573 sc->maxpwr2GHz = val & 0xff; 1574 sc->maxpwr5GHz = val >> 8; 1575 /* Check that EEPROM values are within valid range. */ 1576 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1577 sc->maxpwr5GHz = 38; 1578 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1579 sc->maxpwr2GHz = 38; 1580 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1581 1582 /* Read samples for each TX power group. */ 1583 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1584 sizeof sc->bands); 1585 1586 /* Read voltage at which samples were taken. */ 1587 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1588 sc->eeprom_voltage = (int16_t)le16toh(val); 1589 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1590 1591 #ifdef IWN_DEBUG 1592 /* Print samples. */ 1593 if (iwn_debug > 0) { 1594 for (i = 0; i < IWN_NBANDS; i++) 1595 iwn4965_print_power_group(sc, i); 1596 } 1597 #endif 1598 } 1599 1600 #ifdef IWN_DEBUG 1601 static void 1602 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1603 { 1604 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1605 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1606 int j, c; 1607 1608 aprint_normal("===band %d===\n", i); 1609 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1610 aprint_normal("chan1 num=%d\n", chans[0].num); 1611 for (c = 0; c < 2; c++) { 1612 for (j = 0; j < IWN_NSAMPLES; j++) { 1613 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1614 "power=%d pa_det=%d\n", c, j, 1615 chans[0].samples[c][j].temp, 1616 chans[0].samples[c][j].gain, 1617 chans[0].samples[c][j].power, 1618 chans[0].samples[c][j].pa_det); 1619 } 1620 } 1621 aprint_normal("chan2 num=%d\n", chans[1].num); 1622 for (c = 0; c < 2; c++) { 1623 for (j = 0; j < IWN_NSAMPLES; j++) { 1624 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1625 "power=%d pa_det=%d\n", c, j, 1626 chans[1].samples[c][j].temp, 1627 chans[1].samples[c][j].gain, 1628 chans[1].samples[c][j].power, 1629 chans[1].samples[c][j].pa_det); 1630 } 1631 } 1632 } 1633 #endif 1634 1635 static void 1636 iwn5000_read_eeprom(struct iwn_softc *sc) 1637 { 1638 struct iwn5000_eeprom_calib_hdr hdr; 1639 int32_t volt; 1640 uint32_t base, addr; 1641 uint16_t val; 1642 int i; 1643 1644 /* Read regulatory domain (4 ASCII characters). */ 1645 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1646 base = le16toh(val); 1647 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1648 sc->eeprom_domain, 4); 1649 1650 /* Read the list of authorized channels (20MHz ones only). */ 1651 for (i = 0; i < 5; i++) { 1652 addr = base + iwn5000_regulatory_bands[i]; 1653 iwn_read_eeprom_channels(sc, i, addr); 1654 } 1655 1656 /* Read enhanced TX power information for 6000 Series. */ 1657 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1658 iwn_read_eeprom_enhinfo(sc); 1659 1660 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1661 base = le16toh(val); 1662 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1663 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1664 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1665 sc->calib_ver = hdr.version; 1666 1667 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1668 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1669 sc->hw_type == IWN_HW_REV_TYPE_135 || 1670 sc->hw_type == IWN_HW_REV_TYPE_105) { 1671 sc->eeprom_voltage = le16toh(hdr.volt); 1672 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1673 sc->eeprom_temp = le16toh(val); 1674 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1675 sc->eeprom_rawtemp = le16toh(val); 1676 } 1677 1678 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1679 /* Compute temperature offset. */ 1680 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1681 sc->eeprom_temp = le16toh(val); 1682 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1683 volt = le16toh(val); 1684 sc->temp_off = sc->eeprom_temp - (volt / -5); 1685 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1686 sc->eeprom_temp, volt, sc->temp_off)); 1687 } else { 1688 /* Read crystal calibration. */ 1689 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1690 &sc->eeprom_crystal, sizeof (uint32_t)); 1691 DPRINTF(("crystal calibration 0x%08x\n", 1692 le32toh(sc->eeprom_crystal))); 1693 } 1694 } 1695 1696 static void 1697 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1698 { 1699 struct ieee80211com *ic = &sc->sc_ic; 1700 const struct iwn_chan_band *band = &iwn_bands[n]; 1701 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1702 uint8_t chan; 1703 int i; 1704 1705 iwn_read_prom_data(sc, addr, channels, 1706 band->nchan * sizeof (struct iwn_eeprom_chan)); 1707 1708 for (i = 0; i < band->nchan; i++) { 1709 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1710 continue; 1711 1712 chan = band->chan[i]; 1713 1714 if (n == 0) { /* 2GHz band */ 1715 ic->ic_channels[chan].ic_freq = 1716 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1717 ic->ic_channels[chan].ic_flags = 1718 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1719 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1720 1721 } else { /* 5GHz band */ 1722 /* 1723 * Some adapters support channels 7, 8, 11 and 12 1724 * both in the 2GHz and 4.9GHz bands. 1725 * Because of limitations in our net80211 layer, 1726 * we don't support them in the 4.9GHz band. 1727 */ 1728 if (chan <= 14) 1729 continue; 1730 1731 ic->ic_channels[chan].ic_freq = 1732 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1733 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1734 /* We have at least one valid 5GHz channel. */ 1735 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1736 } 1737 1738 /* Is active scan allowed on this channel? */ 1739 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1740 ic->ic_channels[chan].ic_flags |= 1741 IEEE80211_CHAN_PASSIVE; 1742 } 1743 1744 /* Save maximum allowed TX power for this channel. */ 1745 sc->maxpwr[chan] = channels[i].maxpwr; 1746 1747 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1748 chan, channels[i].flags, sc->maxpwr[chan])); 1749 } 1750 } 1751 1752 static void 1753 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1754 { 1755 struct iwn_eeprom_enhinfo enhinfo[35]; 1756 uint16_t val, base; 1757 int8_t maxpwr; 1758 int i; 1759 1760 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1761 base = le16toh(val); 1762 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1763 enhinfo, sizeof enhinfo); 1764 1765 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1766 for (i = 0; i < __arraycount(enhinfo); i++) { 1767 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1768 continue; /* Skip invalid entries. */ 1769 1770 maxpwr = 0; 1771 if (sc->txchainmask & IWN_ANT_A) 1772 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1773 if (sc->txchainmask & IWN_ANT_B) 1774 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1775 if (sc->txchainmask & IWN_ANT_C) 1776 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1777 if (sc->ntxchains == 2) 1778 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1779 else if (sc->ntxchains == 3) 1780 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1781 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1782 1783 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1784 sc->enh_maxpwr[i] = maxpwr; 1785 } 1786 } 1787 1788 static struct ieee80211_node * 1789 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1790 { 1791 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1792 } 1793 1794 static void 1795 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1796 { 1797 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1798 struct iwn_node *wn = (void *)ni; 1799 uint8_t rate; 1800 int ridx, i; 1801 1802 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1803 /* Start at lowest available bit-rate, AMRR will raise. */ 1804 ni->ni_txrate = 0; 1805 1806 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1807 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1808 /* Map 802.11 rate to HW rate index. */ 1809 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1810 if (iwn_rates[ridx].rate == rate) 1811 break; 1812 wn->ridx[i] = ridx; 1813 } 1814 } 1815 1816 static int 1817 iwn_media_change(struct ifnet *ifp) 1818 { 1819 struct iwn_softc *sc = ifp->if_softc; 1820 struct ieee80211com *ic = &sc->sc_ic; 1821 uint8_t rate, ridx; 1822 int error; 1823 1824 error = ieee80211_media_change(ifp); 1825 if (error != ENETRESET) 1826 return error; 1827 1828 if (ic->ic_fixed_rate != -1) { 1829 rate = ic->ic_sup_rates[ic->ic_curmode]. 1830 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1831 /* Map 802.11 rate to HW rate index. */ 1832 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1833 if (iwn_rates[ridx].rate == rate) 1834 break; 1835 sc->fixed_ridx = ridx; 1836 } 1837 1838 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1839 (IFF_UP | IFF_RUNNING)) { 1840 iwn_stop(ifp, 0); 1841 error = iwn_init(ifp); 1842 } 1843 return error; 1844 } 1845 1846 static int 1847 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1848 { 1849 struct ifnet *ifp = ic->ic_ifp; 1850 struct iwn_softc *sc = ifp->if_softc; 1851 int error; 1852 1853 callout_stop(&sc->calib_to); 1854 1855 switch (nstate) { 1856 case IEEE80211_S_SCAN: 1857 /* XXX Do not abort a running scan. */ 1858 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1859 if (ic->ic_state != nstate) 1860 aprint_error_dev(sc->sc_dev, "scan request(%d) " 1861 "while scanning(%d) ignored\n", nstate, 1862 ic->ic_state); 1863 break; 1864 } 1865 1866 /* XXX Not sure if call and flags are needed. */ 1867 ieee80211_node_table_reset(&ic->ic_scan); 1868 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1869 sc->sc_flags |= IWN_FLAG_SCANNING; 1870 1871 /* Make the link LED blink while we're scanning. */ 1872 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1873 1874 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1875 aprint_error_dev(sc->sc_dev, 1876 "could not initiate scan\n"); 1877 return error; 1878 } 1879 ic->ic_state = nstate; 1880 return 0; 1881 1882 case IEEE80211_S_ASSOC: 1883 if (ic->ic_state != IEEE80211_S_RUN) 1884 break; 1885 /* FALLTHROUGH */ 1886 case IEEE80211_S_AUTH: 1887 /* Reset state to handle reassociations correctly. */ 1888 sc->rxon.associd = 0; 1889 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1890 sc->calib.state = IWN_CALIB_STATE_INIT; 1891 1892 if ((error = iwn_auth(sc)) != 0) { 1893 aprint_error_dev(sc->sc_dev, 1894 "could not move to auth state\n"); 1895 return error; 1896 } 1897 break; 1898 1899 case IEEE80211_S_RUN: 1900 if ((error = iwn_run(sc)) != 0) { 1901 aprint_error_dev(sc->sc_dev, 1902 "could not move to run state\n"); 1903 return error; 1904 } 1905 break; 1906 1907 case IEEE80211_S_INIT: 1908 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1909 sc->calib.state = IWN_CALIB_STATE_INIT; 1910 break; 1911 } 1912 1913 return sc->sc_newstate(ic, nstate, arg); 1914 } 1915 1916 static void 1917 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1918 { 1919 struct iwn_softc *sc = arg; 1920 struct iwn_node *wn = (struct iwn_node *)ni; 1921 1922 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1923 } 1924 1925 static void 1926 iwn_calib_timeout(void *arg) 1927 { 1928 struct iwn_softc *sc = arg; 1929 struct ieee80211com *ic = &sc->sc_ic; 1930 int s; 1931 1932 s = splnet(); 1933 if (ic->ic_fixed_rate == -1) { 1934 if (ic->ic_opmode == IEEE80211_M_STA) 1935 iwn_iter_func(sc, ic->ic_bss); 1936 else 1937 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1938 } 1939 /* Force automatic TX power calibration every 60 secs. */ 1940 if (++sc->calib_cnt >= 120) { 1941 uint32_t flags = 0; 1942 1943 DPRINTF(("sending request for statistics\n")); 1944 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1945 sizeof flags, 1); 1946 sc->calib_cnt = 0; 1947 } 1948 splx(s); 1949 1950 /* Automatic rate control triggered every 500ms. */ 1951 callout_schedule(&sc->calib_to, hz/2); 1952 } 1953 1954 /* 1955 * Process an RX_PHY firmware notification. This is usually immediately 1956 * followed by an MPDU_RX_DONE notification. 1957 */ 1958 static void 1959 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1960 struct iwn_rx_data *data) 1961 { 1962 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1963 1964 DPRINTFN(2, ("received PHY stats\n")); 1965 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1966 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1967 1968 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1969 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1970 sc->last_rx_valid = 1; 1971 } 1972 1973 /* 1974 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1975 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1976 */ 1977 static void 1978 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1979 struct iwn_rx_data *data) 1980 { 1981 struct iwn_ops *ops = &sc->ops; 1982 struct ieee80211com *ic = &sc->sc_ic; 1983 struct ifnet *ifp = ic->ic_ifp; 1984 struct iwn_rx_ring *ring = &sc->rxq; 1985 struct ieee80211_frame *wh; 1986 struct ieee80211_node *ni; 1987 struct mbuf *m, *m1; 1988 struct iwn_rx_stat *stat; 1989 char *head; 1990 uint32_t flags; 1991 int error, len, rssi; 1992 1993 if (desc->type == IWN_MPDU_RX_DONE) { 1994 /* Check for prior RX_PHY notification. */ 1995 if (!sc->last_rx_valid) { 1996 DPRINTF(("missing RX_PHY\n")); 1997 return; 1998 } 1999 sc->last_rx_valid = 0; 2000 stat = &sc->last_rx_stat; 2001 } else 2002 stat = (struct iwn_rx_stat *)(desc + 1); 2003 2004 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2005 BUS_DMASYNC_POSTREAD); 2006 2007 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2008 aprint_error_dev(sc->sc_dev, 2009 "invalid RX statistic header\n"); 2010 return; 2011 } 2012 if (desc->type == IWN_MPDU_RX_DONE) { 2013 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2014 head = (char *)(mpdu + 1); 2015 len = le16toh(mpdu->len); 2016 } else { 2017 head = (char *)(stat + 1) + stat->cfg_phy_len; 2018 len = le16toh(stat->len); 2019 } 2020 2021 flags = le32toh(*(uint32_t *)(head + len)); 2022 2023 /* Discard frames with a bad FCS early. */ 2024 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2025 DPRINTFN(2, ("RX flags error %x\n", flags)); 2026 ifp->if_ierrors++; 2027 return; 2028 } 2029 /* Discard frames that are too short. */ 2030 if (len < sizeof (*wh)) { 2031 DPRINTF(("frame too short: %d\n", len)); 2032 ic->ic_stats.is_rx_tooshort++; 2033 ifp->if_ierrors++; 2034 return; 2035 } 2036 2037 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2038 if (m1 == NULL) { 2039 ic->ic_stats.is_rx_nobuf++; 2040 ifp->if_ierrors++; 2041 return; 2042 } 2043 bus_dmamap_unload(sc->sc_dmat, data->map); 2044 2045 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2046 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2047 if (error != 0) { 2048 m_freem(m1); 2049 2050 /* Try to reload the old mbuf. */ 2051 error = bus_dmamap_load(sc->sc_dmat, data->map, 2052 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2053 BUS_DMA_NOWAIT | BUS_DMA_READ); 2054 if (error != 0) { 2055 panic("%s: could not load old RX mbuf", 2056 device_xname(sc->sc_dev)); 2057 } 2058 /* Physical address may have changed. */ 2059 ring->desc[ring->cur] = 2060 htole32(data->map->dm_segs[0].ds_addr >> 8); 2061 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2062 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2063 BUS_DMASYNC_PREWRITE); 2064 ifp->if_ierrors++; 2065 return; 2066 } 2067 2068 m = data->m; 2069 data->m = m1; 2070 /* Update RX descriptor. */ 2071 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2072 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2073 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2074 BUS_DMASYNC_PREWRITE); 2075 2076 /* Finalize mbuf. */ 2077 m->m_pkthdr.rcvif = ifp; 2078 m->m_data = head; 2079 m->m_pkthdr.len = m->m_len = len; 2080 2081 /* Grab a reference to the source node. */ 2082 wh = mtod(m, struct ieee80211_frame *); 2083 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2084 2085 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2086 /* NetBSD does decryption in ieee80211_input. */ 2087 2088 rssi = ops->get_rssi(stat); 2089 2090 /* XXX Added for NetBSD: scans never stop without it */ 2091 if (ic->ic_state == IEEE80211_S_SCAN) 2092 iwn_fix_channel(ic, m); 2093 2094 if (sc->sc_drvbpf != NULL) { 2095 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2096 2097 tap->wr_flags = 0; 2098 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2099 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2100 tap->wr_chan_freq = 2101 htole16(ic->ic_channels[stat->chan].ic_freq); 2102 tap->wr_chan_flags = 2103 htole16(ic->ic_channels[stat->chan].ic_flags); 2104 tap->wr_dbm_antsignal = (int8_t)rssi; 2105 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2106 tap->wr_tsft = stat->tstamp; 2107 switch (stat->rate) { 2108 /* CCK rates. */ 2109 case 10: tap->wr_rate = 2; break; 2110 case 20: tap->wr_rate = 4; break; 2111 case 55: tap->wr_rate = 11; break; 2112 case 110: tap->wr_rate = 22; break; 2113 /* OFDM rates. */ 2114 case 0xd: tap->wr_rate = 12; break; 2115 case 0xf: tap->wr_rate = 18; break; 2116 case 0x5: tap->wr_rate = 24; break; 2117 case 0x7: tap->wr_rate = 36; break; 2118 case 0x9: tap->wr_rate = 48; break; 2119 case 0xb: tap->wr_rate = 72; break; 2120 case 0x1: tap->wr_rate = 96; break; 2121 case 0x3: tap->wr_rate = 108; break; 2122 /* Unknown rate: should not happen. */ 2123 default: tap->wr_rate = 0; 2124 } 2125 2126 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2127 } 2128 2129 /* Send the frame to the 802.11 layer. */ 2130 ieee80211_input(ic, m, ni, rssi, 0); 2131 2132 /* Node is no longer needed. */ 2133 ieee80211_free_node(ni); 2134 } 2135 2136 #ifndef IEEE80211_NO_HT 2137 /* Process an incoming Compressed BlockAck. */ 2138 static void 2139 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2140 struct iwn_rx_data *data) 2141 { 2142 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2143 struct iwn_tx_ring *txq; 2144 2145 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2146 BUS_DMASYNC_POSTREAD); 2147 2148 txq = &sc->txq[le16toh(ba->qid)]; 2149 /* XXX TBD */ 2150 } 2151 #endif 2152 2153 /* 2154 * Process a CALIBRATION_RESULT notification sent by the initialization 2155 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2156 */ 2157 static void 2158 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2159 struct iwn_rx_data *data) 2160 { 2161 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2162 int len, idx = -1; 2163 2164 /* Runtime firmware should not send such a notification. */ 2165 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2166 return; 2167 2168 len = (le32toh(desc->len) & 0x3fff) - 4; 2169 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2170 BUS_DMASYNC_POSTREAD); 2171 2172 switch (calib->code) { 2173 case IWN5000_PHY_CALIB_DC: 2174 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2175 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2176 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2177 sc->hw_type == IWN_HW_REV_TYPE_135 || 2178 sc->hw_type == IWN_HW_REV_TYPE_105) 2179 idx = 0; 2180 break; 2181 case IWN5000_PHY_CALIB_LO: 2182 idx = 1; 2183 break; 2184 case IWN5000_PHY_CALIB_TX_IQ: 2185 idx = 2; 2186 break; 2187 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2188 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2189 sc->hw_type != IWN_HW_REV_TYPE_5150) 2190 idx = 3; 2191 break; 2192 case IWN5000_PHY_CALIB_BASE_BAND: 2193 idx = 4; 2194 break; 2195 } 2196 if (idx == -1) /* Ignore other results. */ 2197 return; 2198 2199 /* Save calibration result. */ 2200 if (sc->calibcmd[idx].buf != NULL) 2201 free(sc->calibcmd[idx].buf, M_DEVBUF); 2202 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2203 if (sc->calibcmd[idx].buf == NULL) { 2204 DPRINTF(("not enough memory for calibration result %d\n", 2205 calib->code)); 2206 return; 2207 } 2208 DPRINTF(("saving calibration result code=%d len=%d\n", 2209 calib->code, len)); 2210 sc->calibcmd[idx].len = len; 2211 memcpy(sc->calibcmd[idx].buf, calib, len); 2212 } 2213 2214 /* 2215 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2216 * The latter is sent by the firmware after each received beacon. 2217 */ 2218 static void 2219 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2220 struct iwn_rx_data *data) 2221 { 2222 struct iwn_ops *ops = &sc->ops; 2223 struct ieee80211com *ic = &sc->sc_ic; 2224 struct iwn_calib_state *calib = &sc->calib; 2225 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2226 int temp; 2227 2228 /* Ignore statistics received during a scan. */ 2229 if (ic->ic_state != IEEE80211_S_RUN) 2230 return; 2231 2232 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2233 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2234 2235 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2236 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2237 2238 /* Test if temperature has changed. */ 2239 if (stats->general.temp != sc->rawtemp) { 2240 /* Convert "raw" temperature to degC. */ 2241 sc->rawtemp = stats->general.temp; 2242 temp = ops->get_temperature(sc); 2243 DPRINTFN(2, ("temperature=%dC\n", temp)); 2244 2245 /* Update TX power if need be (4965AGN only). */ 2246 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2247 iwn4965_power_calibration(sc, temp); 2248 } 2249 2250 if (desc->type != IWN_BEACON_STATISTICS) 2251 return; /* Reply to a statistics request. */ 2252 2253 sc->noise = iwn_get_noise(&stats->rx.general); 2254 2255 /* Test that RSSI and noise are present in stats report. */ 2256 if (le32toh(stats->rx.general.flags) != 1) { 2257 DPRINTF(("received statistics without RSSI\n")); 2258 return; 2259 } 2260 2261 /* 2262 * XXX Differential gain calibration makes the 6005 firmware 2263 * crap out, so skip it for now. This effectively disables 2264 * sensitivity tuning as well. 2265 */ 2266 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2267 return; 2268 2269 if (calib->state == IWN_CALIB_STATE_ASSOC) 2270 iwn_collect_noise(sc, &stats->rx.general); 2271 else if (calib->state == IWN_CALIB_STATE_RUN) 2272 iwn_tune_sensitivity(sc, &stats->rx); 2273 } 2274 2275 /* 2276 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2277 * and 5000 adapters have different incompatible TX status formats. 2278 */ 2279 static void 2280 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2281 struct iwn_rx_data *data) 2282 { 2283 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2284 2285 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2286 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2287 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2288 } 2289 2290 static void 2291 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2292 struct iwn_rx_data *data) 2293 { 2294 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2295 2296 #ifdef notyet 2297 /* Reset TX scheduler slot. */ 2298 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2299 #endif 2300 2301 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2302 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2303 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2304 } 2305 2306 /* 2307 * Adapter-independent backend for TX_DONE firmware notifications. 2308 */ 2309 static void 2310 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2311 uint8_t status) 2312 { 2313 struct ieee80211com *ic = &sc->sc_ic; 2314 struct ifnet *ifp = ic->ic_ifp; 2315 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2316 struct iwn_tx_data *data = &ring->data[desc->idx]; 2317 struct iwn_node *wn = (struct iwn_node *)data->ni; 2318 2319 /* Update rate control statistics. */ 2320 wn->amn.amn_txcnt++; 2321 if (ackfailcnt > 0) 2322 wn->amn.amn_retrycnt++; 2323 2324 if (status != 1 && status != 2) 2325 ifp->if_oerrors++; 2326 else 2327 ifp->if_opackets++; 2328 2329 /* Unmap and free mbuf. */ 2330 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2331 BUS_DMASYNC_POSTWRITE); 2332 bus_dmamap_unload(sc->sc_dmat, data->map); 2333 m_freem(data->m); 2334 data->m = NULL; 2335 ieee80211_free_node(data->ni); 2336 data->ni = NULL; 2337 2338 sc->sc_tx_timer = 0; 2339 if (--ring->queued < IWN_TX_RING_LOMARK) { 2340 sc->qfullmsk &= ~(1 << ring->qid); 2341 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2342 ifp->if_flags &= ~IFF_OACTIVE; 2343 (*ifp->if_start)(ifp); 2344 } 2345 } 2346 } 2347 2348 /* 2349 * Process a "command done" firmware notification. This is where we wakeup 2350 * processes waiting for a synchronous command completion. 2351 */ 2352 static void 2353 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2354 { 2355 struct iwn_tx_ring *ring = &sc->txq[4]; 2356 struct iwn_tx_data *data; 2357 2358 if ((desc->qid & 0xf) != 4) 2359 return; /* Not a command ack. */ 2360 2361 data = &ring->data[desc->idx]; 2362 2363 /* If the command was mapped in an mbuf, free it. */ 2364 if (data->m != NULL) { 2365 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2366 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2367 bus_dmamap_unload(sc->sc_dmat, data->map); 2368 m_freem(data->m); 2369 data->m = NULL; 2370 } 2371 wakeup(&ring->desc[desc->idx]); 2372 } 2373 2374 /* 2375 * Process an INT_FH_RX or INT_SW_RX interrupt. 2376 */ 2377 static void 2378 iwn_notif_intr(struct iwn_softc *sc) 2379 { 2380 struct iwn_ops *ops = &sc->ops; 2381 struct ieee80211com *ic = &sc->sc_ic; 2382 struct ifnet *ifp = ic->ic_ifp; 2383 uint16_t hw; 2384 2385 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2386 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2387 2388 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2389 while (sc->rxq.cur != hw) { 2390 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2391 struct iwn_rx_desc *desc; 2392 2393 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2394 BUS_DMASYNC_POSTREAD); 2395 desc = mtod(data->m, struct iwn_rx_desc *); 2396 2397 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2398 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2399 2400 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2401 iwn_cmd_done(sc, desc); 2402 2403 switch (desc->type) { 2404 case IWN_RX_PHY: 2405 iwn_rx_phy(sc, desc, data); 2406 break; 2407 2408 case IWN_RX_DONE: /* 4965AGN only. */ 2409 case IWN_MPDU_RX_DONE: 2410 /* An 802.11 frame has been received. */ 2411 iwn_rx_done(sc, desc, data); 2412 break; 2413 #ifndef IEEE80211_NO_HT 2414 case IWN_RX_COMPRESSED_BA: 2415 /* A Compressed BlockAck has been received. */ 2416 iwn_rx_compressed_ba(sc, desc, data); 2417 break; 2418 #endif 2419 case IWN_TX_DONE: 2420 /* An 802.11 frame has been transmitted. */ 2421 ops->tx_done(sc, desc, data); 2422 break; 2423 2424 case IWN_RX_STATISTICS: 2425 case IWN_BEACON_STATISTICS: 2426 iwn_rx_statistics(sc, desc, data); 2427 break; 2428 2429 case IWN_BEACON_MISSED: 2430 { 2431 struct iwn_beacon_missed *miss = 2432 (struct iwn_beacon_missed *)(desc + 1); 2433 2434 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2435 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2436 /* 2437 * If more than 5 consecutive beacons are missed, 2438 * reinitialize the sensitivity state machine. 2439 */ 2440 DPRINTF(("beacons missed %d/%d\n", 2441 le32toh(miss->consecutive), le32toh(miss->total))); 2442 if (ic->ic_state == IEEE80211_S_RUN && 2443 le32toh(miss->consecutive) > 5) 2444 (void)iwn_init_sensitivity(sc); 2445 break; 2446 } 2447 case IWN_UC_READY: 2448 { 2449 struct iwn_ucode_info *uc = 2450 (struct iwn_ucode_info *)(desc + 1); 2451 2452 /* The microcontroller is ready. */ 2453 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2454 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2455 DPRINTF(("microcode alive notification version=%d.%d " 2456 "subtype=%x alive=%x\n", uc->major, uc->minor, 2457 uc->subtype, le32toh(uc->valid))); 2458 2459 if (le32toh(uc->valid) != 1) { 2460 aprint_error_dev(sc->sc_dev, 2461 "microcontroller initialization " 2462 "failed\n"); 2463 break; 2464 } 2465 if (uc->subtype == IWN_UCODE_INIT) { 2466 /* Save microcontroller report. */ 2467 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2468 } 2469 /* Save the address of the error log in SRAM. */ 2470 sc->errptr = le32toh(uc->errptr); 2471 break; 2472 } 2473 case IWN_STATE_CHANGED: 2474 { 2475 uint32_t *status = (uint32_t *)(desc + 1); 2476 2477 /* Enabled/disabled notification. */ 2478 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2479 sizeof (*status), BUS_DMASYNC_POSTREAD); 2480 DPRINTF(("state changed to %x\n", le32toh(*status))); 2481 2482 if (le32toh(*status) & 1) { 2483 /* The radio button has to be pushed. */ 2484 aprint_error_dev(sc->sc_dev, 2485 "Radio transmitter is off\n"); 2486 /* Turn the interface down. */ 2487 ifp->if_flags &= ~IFF_UP; 2488 iwn_stop(ifp, 1); 2489 return; /* No further processing. */ 2490 } 2491 break; 2492 } 2493 case IWN_START_SCAN: 2494 { 2495 struct iwn_start_scan *scan = 2496 (struct iwn_start_scan *)(desc + 1); 2497 2498 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2499 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2500 DPRINTFN(2, ("scanning channel %d status %x\n", 2501 scan->chan, le32toh(scan->status))); 2502 2503 /* Fix current channel. */ 2504 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2505 break; 2506 } 2507 case IWN_STOP_SCAN: 2508 { 2509 struct iwn_stop_scan *scan = 2510 (struct iwn_stop_scan *)(desc + 1); 2511 2512 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2513 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2514 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2515 scan->nchan, scan->status, scan->chan)); 2516 2517 if (scan->status == 1 && scan->chan <= 14 && 2518 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2519 /* 2520 * We just finished scanning 2GHz channels, 2521 * start scanning 5GHz ones. 2522 */ 2523 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2524 break; 2525 } 2526 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2527 ieee80211_end_scan(ic); 2528 break; 2529 } 2530 case IWN5000_CALIBRATION_RESULT: 2531 iwn5000_rx_calib_results(sc, desc, data); 2532 break; 2533 2534 case IWN5000_CALIBRATION_DONE: 2535 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2536 wakeup(sc); 2537 break; 2538 } 2539 2540 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2541 } 2542 2543 /* Tell the firmware what we have processed. */ 2544 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2545 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2546 } 2547 2548 /* 2549 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2550 * from power-down sleep mode. 2551 */ 2552 static void 2553 iwn_wakeup_intr(struct iwn_softc *sc) 2554 { 2555 int qid; 2556 2557 DPRINTF(("ucode wakeup from power-down sleep\n")); 2558 2559 /* Wakeup RX and TX rings. */ 2560 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2561 for (qid = 0; qid < sc->ntxqs; qid++) { 2562 struct iwn_tx_ring *ring = &sc->txq[qid]; 2563 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2564 } 2565 } 2566 2567 /* 2568 * Dump the error log of the firmware when a firmware panic occurs. Although 2569 * we can't debug the firmware because it is neither open source nor free, it 2570 * can help us to identify certain classes of problems. 2571 */ 2572 static void 2573 iwn_fatal_intr(struct iwn_softc *sc) 2574 { 2575 struct iwn_fw_dump dump; 2576 int i; 2577 2578 /* Force a complete recalibration on next init. */ 2579 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2580 2581 /* Check that the error log address is valid. */ 2582 if (sc->errptr < IWN_FW_DATA_BASE || 2583 sc->errptr + sizeof (dump) > 2584 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2585 aprint_error_dev(sc->sc_dev, 2586 "bad firmware error log address 0x%08x\n", sc->errptr); 2587 return; 2588 } 2589 if (iwn_nic_lock(sc) != 0) { 2590 aprint_error_dev(sc->sc_dev, 2591 "could not read firmware error log\n"); 2592 return; 2593 } 2594 /* Read firmware error log from SRAM. */ 2595 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2596 sizeof (dump) / sizeof (uint32_t)); 2597 iwn_nic_unlock(sc); 2598 2599 if (dump.valid == 0) { 2600 aprint_error_dev(sc->sc_dev, 2601 "firmware error log is empty\n"); 2602 return; 2603 } 2604 aprint_error("firmware error log:\n"); 2605 aprint_error(" error type = \"%s\" (0x%08X)\n", 2606 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2607 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2608 dump.id); 2609 aprint_error(" program counter = 0x%08X\n", dump.pc); 2610 aprint_error(" source line = 0x%08X\n", dump.src_line); 2611 aprint_error(" error data = 0x%08X%08X\n", 2612 dump.error_data[0], dump.error_data[1]); 2613 aprint_error(" branch link = 0x%08X%08X\n", 2614 dump.branch_link[0], dump.branch_link[1]); 2615 aprint_error(" interrupt link = 0x%08X%08X\n", 2616 dump.interrupt_link[0], dump.interrupt_link[1]); 2617 aprint_error(" time = %u\n", dump.time[0]); 2618 2619 /* Dump driver status (TX and RX rings) while we're here. */ 2620 aprint_error("driver status:\n"); 2621 for (i = 0; i < sc->ntxqs; i++) { 2622 struct iwn_tx_ring *ring = &sc->txq[i]; 2623 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2624 i, ring->qid, ring->cur, ring->queued); 2625 } 2626 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2627 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2628 } 2629 2630 static int 2631 iwn_intr(void *arg) 2632 { 2633 struct iwn_softc *sc = arg; 2634 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2635 uint32_t r1, r2, tmp; 2636 2637 /* Disable interrupts. */ 2638 IWN_WRITE(sc, IWN_INT_MASK, 0); 2639 2640 /* Read interrupts from ICT (fast) or from registers (slow). */ 2641 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2642 tmp = 0; 2643 while (sc->ict[sc->ict_cur] != 0) { 2644 tmp |= sc->ict[sc->ict_cur]; 2645 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2646 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2647 } 2648 tmp = le32toh(tmp); 2649 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2650 tmp = 0; 2651 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2652 tmp |= 0x8000; 2653 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2654 r2 = 0; /* Unused. */ 2655 } else { 2656 r1 = IWN_READ(sc, IWN_INT); 2657 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2658 return 0; /* Hardware gone! */ 2659 r2 = IWN_READ(sc, IWN_FH_INT); 2660 } 2661 if (r1 == 0 && r2 == 0) { 2662 if (ifp->if_flags & IFF_UP) 2663 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2664 return 0; /* Interrupt not for us. */ 2665 } 2666 2667 /* Acknowledge interrupts. */ 2668 IWN_WRITE(sc, IWN_INT, r1); 2669 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2670 IWN_WRITE(sc, IWN_FH_INT, r2); 2671 2672 if (r1 & IWN_INT_RF_TOGGLED) { 2673 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2674 aprint_error_dev(sc->sc_dev, 2675 "RF switch: radio %s\n", 2676 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2677 } 2678 if (r1 & IWN_INT_CT_REACHED) { 2679 aprint_error_dev(sc->sc_dev, 2680 "critical temperature reached!\n"); 2681 } 2682 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2683 aprint_error_dev(sc->sc_dev, 2684 "fatal firmware error\n"); 2685 /* Dump firmware error log and stop. */ 2686 iwn_fatal_intr(sc); 2687 ifp->if_flags &= ~IFF_UP; 2688 iwn_stop(ifp, 1); 2689 return 1; 2690 } 2691 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2692 (r2 & IWN_FH_INT_RX)) { 2693 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2694 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2695 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2696 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2697 IWN_INT_PERIODIC_DIS); 2698 iwn_notif_intr(sc); 2699 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2700 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2701 IWN_INT_PERIODIC_ENA); 2702 } 2703 } else 2704 iwn_notif_intr(sc); 2705 } 2706 2707 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2708 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2709 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2710 wakeup(sc); /* FH DMA transfer completed. */ 2711 } 2712 2713 if (r1 & IWN_INT_ALIVE) 2714 wakeup(sc); /* Firmware is alive. */ 2715 2716 if (r1 & IWN_INT_WAKEUP) 2717 iwn_wakeup_intr(sc); 2718 2719 /* Re-enable interrupts. */ 2720 if (ifp->if_flags & IFF_UP) 2721 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2722 2723 return 1; 2724 } 2725 2726 /* 2727 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2728 * 5000 adapters use a slightly different format). 2729 */ 2730 static void 2731 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2732 uint16_t len) 2733 { 2734 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2735 2736 *w = htole16(len + 8); 2737 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2738 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2739 sizeof (uint16_t), 2740 BUS_DMASYNC_PREWRITE); 2741 if (idx < IWN_SCHED_WINSZ) { 2742 *(w + IWN_TX_RING_COUNT) = *w; 2743 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2744 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2745 (char *)(void *)sc->sched_dma.vaddr, 2746 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2747 } 2748 } 2749 2750 static void 2751 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2752 uint16_t len) 2753 { 2754 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2755 2756 *w = htole16(id << 12 | (len + 8)); 2757 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2758 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2759 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2760 if (idx < IWN_SCHED_WINSZ) { 2761 *(w + IWN_TX_RING_COUNT) = *w; 2762 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2763 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2764 (char *)(void *)sc->sched_dma.vaddr, 2765 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2766 } 2767 } 2768 2769 #ifdef notyet 2770 static void 2771 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2772 { 2773 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2774 2775 *w = (*w & htole16(0xf000)) | htole16(1); 2776 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2777 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2778 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2779 if (idx < IWN_SCHED_WINSZ) { 2780 *(w + IWN_TX_RING_COUNT) = *w; 2781 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2782 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2783 (char *)(void *)sc->sched_dma.vaddr, 2784 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2785 } 2786 } 2787 #endif 2788 2789 static int 2790 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2791 { 2792 struct ieee80211com *ic = &sc->sc_ic; 2793 struct iwn_node *wn = (void *)ni; 2794 struct iwn_tx_ring *ring; 2795 struct iwn_tx_desc *desc; 2796 struct iwn_tx_data *data; 2797 struct iwn_tx_cmd *cmd; 2798 struct iwn_cmd_data *tx; 2799 const struct iwn_rate *rinfo; 2800 struct ieee80211_frame *wh; 2801 struct ieee80211_key *k = NULL; 2802 struct mbuf *m1; 2803 uint32_t flags; 2804 u_int hdrlen; 2805 bus_dma_segment_t *seg; 2806 uint8_t tid, ridx, txant, type; 2807 int i, totlen, error, pad; 2808 2809 const struct chanAccParams *cap; 2810 int noack; 2811 int hdrlen2; 2812 2813 wh = mtod(m, struct ieee80211_frame *); 2814 hdrlen = ieee80211_anyhdrsize(wh); 2815 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2816 2817 hdrlen2 = (ieee80211_has_qos(wh)) ? 2818 sizeof (struct ieee80211_qosframe) : 2819 sizeof (struct ieee80211_frame); 2820 2821 if (hdrlen != hdrlen2) 2822 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2823 hdrlen, hdrlen2); 2824 2825 /* XXX OpenBSD sets a different tid when using QOS */ 2826 tid = 0; 2827 if (ieee80211_has_qos(wh)) { 2828 cap = &ic->ic_wme.wme_chanParams; 2829 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2830 } 2831 else 2832 noack = 0; 2833 2834 ring = &sc->txq[ac]; 2835 desc = &ring->desc[ring->cur]; 2836 data = &ring->data[ring->cur]; 2837 2838 /* Choose a TX rate index. */ 2839 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2840 type != IEEE80211_FC0_TYPE_DATA) { 2841 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2842 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2843 } else if (ic->ic_fixed_rate != -1) { 2844 ridx = sc->fixed_ridx; 2845 } else 2846 ridx = wn->ridx[ni->ni_txrate]; 2847 rinfo = &iwn_rates[ridx]; 2848 2849 /* Encrypt the frame if need be. */ 2850 /* 2851 * XXX For now, NetBSD swaps the encryption and bpf sections 2852 * in order to match old code and other drivers. Tests with 2853 * tcpdump indicates that the order is irrelevant, however, 2854 * as bpf produces unencrypted data for both ordering choices. 2855 */ 2856 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2857 k = ieee80211_crypto_encap(ic, ni, m); 2858 if (k == NULL) { 2859 m_freem(m); 2860 return ENOBUFS; 2861 } 2862 /* Packet header may have moved, reset our local pointer. */ 2863 wh = mtod(m, struct ieee80211_frame *); 2864 } 2865 totlen = m->m_pkthdr.len; 2866 2867 if (sc->sc_drvbpf != NULL) { 2868 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2869 2870 tap->wt_flags = 0; 2871 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2872 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2873 tap->wt_rate = rinfo->rate; 2874 tap->wt_hwqueue = ac; 2875 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2876 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2877 2878 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2879 } 2880 2881 /* Prepare TX firmware command. */ 2882 cmd = &ring->cmd[ring->cur]; 2883 cmd->code = IWN_CMD_TX_DATA; 2884 cmd->flags = 0; 2885 cmd->qid = ring->qid; 2886 cmd->idx = ring->cur; 2887 2888 tx = (struct iwn_cmd_data *)cmd->data; 2889 /* NB: No need to clear tx, all fields are reinitialized here. */ 2890 tx->scratch = 0; /* clear "scratch" area */ 2891 2892 flags = 0; 2893 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2894 /* Unicast frame, check if an ACK is expected. */ 2895 if (!noack) 2896 flags |= IWN_TX_NEED_ACK; 2897 } 2898 2899 #ifdef notyet 2900 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 2901 if ((wh->i_fc[0] & 2902 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2903 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 2904 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 2905 #endif 2906 2907 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2908 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 2909 2910 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 2911 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2912 /* NB: Group frames are sent using CCK in 802.11b/g. */ 2913 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 2914 flags |= IWN_TX_NEED_RTS; 2915 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 2916 ridx >= IWN_RIDX_OFDM6) { 2917 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2918 flags |= IWN_TX_NEED_CTS; 2919 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2920 flags |= IWN_TX_NEED_RTS; 2921 } 2922 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 2923 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 2924 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 2925 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 2926 flags |= IWN_TX_NEED_PROTECTION; 2927 } else 2928 flags |= IWN_TX_FULL_TXOP; 2929 } 2930 } 2931 2932 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2933 type != IEEE80211_FC0_TYPE_DATA) 2934 tx->id = sc->broadcast_id; 2935 else 2936 tx->id = wn->id; 2937 2938 if (type == IEEE80211_FC0_TYPE_MGT) { 2939 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2940 2941 #ifndef IEEE80211_STA_ONLY 2942 /* Tell HW to set timestamp in probe responses. */ 2943 /* XXX NetBSD rev 1.11 added probe requests here but */ 2944 /* probe requests do not take timestamps (from Bergamini). */ 2945 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2946 flags |= IWN_TX_INSERT_TSTAMP; 2947 #endif 2948 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 2949 /* changes here. These are not needed (from Bergamini). */ 2950 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 2951 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 2952 tx->timeout = htole16(3); 2953 else 2954 tx->timeout = htole16(2); 2955 } else 2956 tx->timeout = htole16(0); 2957 2958 if (hdrlen & 3) { 2959 /* First segment length must be a multiple of 4. */ 2960 flags |= IWN_TX_NEED_PADDING; 2961 pad = 4 - (hdrlen & 3); 2962 } else 2963 pad = 0; 2964 2965 tx->len = htole16(totlen); 2966 tx->tid = tid; 2967 tx->rts_ntries = 60; 2968 tx->data_ntries = 15; 2969 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 2970 tx->plcp = rinfo->plcp; 2971 tx->rflags = rinfo->flags; 2972 if (tx->id == sc->broadcast_id) { 2973 /* Group or management frame. */ 2974 tx->linkq = 0; 2975 /* XXX Alternate between antenna A and B? */ 2976 txant = IWN_LSB(sc->txchainmask); 2977 tx->rflags |= IWN_RFLAG_ANT(txant); 2978 } else { 2979 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 2980 flags |= IWN_TX_LINKQ; /* enable MRR */ 2981 } 2982 /* Set physical address of "scratch area". */ 2983 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 2984 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 2985 2986 /* Copy 802.11 header in TX command. */ 2987 /* XXX NetBSD changed this in rev 1.20 */ 2988 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 2989 2990 /* Trim 802.11 header. */ 2991 m_adj(m, hdrlen); 2992 tx->security = 0; 2993 tx->flags = htole32(flags); 2994 2995 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 2996 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 2997 if (error != 0) { 2998 if (error != EFBIG) { 2999 aprint_error_dev(sc->sc_dev, 3000 "can't map mbuf (error %d)\n", error); 3001 m_freem(m); 3002 return error; 3003 } 3004 /* Too many DMA segments, linearize mbuf. */ 3005 MGETHDR(m1, M_DONTWAIT, MT_DATA); 3006 if (m1 == NULL) { 3007 m_freem(m); 3008 return ENOBUFS; 3009 } 3010 if (m->m_pkthdr.len > MHLEN) { 3011 MCLGET(m1, M_DONTWAIT); 3012 if (!(m1->m_flags & M_EXT)) { 3013 m_freem(m); 3014 m_freem(m1); 3015 return ENOBUFS; 3016 } 3017 } 3018 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 3019 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3020 m_freem(m); 3021 m = m1; 3022 3023 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3024 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3025 if (error != 0) { 3026 aprint_error_dev(sc->sc_dev, 3027 "can't map mbuf (error %d)\n", error); 3028 m_freem(m); 3029 return error; 3030 } 3031 } 3032 3033 data->m = m; 3034 data->ni = ni; 3035 3036 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3037 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3038 3039 /* Fill TX descriptor. */ 3040 desc->nsegs = 1 + data->map->dm_nsegs; 3041 /* First DMA segment is used by the TX command. */ 3042 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3043 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3044 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3045 /* Other DMA segments are for data payload. */ 3046 seg = data->map->dm_segs; 3047 for (i = 1; i <= data->map->dm_nsegs; i++) { 3048 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3049 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3050 seg->ds_len << 4); 3051 seg++; 3052 } 3053 3054 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3055 BUS_DMASYNC_PREWRITE); 3056 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3057 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3058 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3059 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3060 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3061 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3062 3063 #ifdef notyet 3064 /* Update TX scheduler. */ 3065 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3066 #endif 3067 3068 /* Kick TX ring. */ 3069 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3070 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3071 3072 /* Mark TX ring as full if we reach a certain threshold. */ 3073 if (++ring->queued > IWN_TX_RING_HIMARK) 3074 sc->qfullmsk |= 1 << ring->qid; 3075 3076 return 0; 3077 } 3078 3079 static void 3080 iwn_start(struct ifnet *ifp) 3081 { 3082 struct iwn_softc *sc = ifp->if_softc; 3083 struct ieee80211com *ic = &sc->sc_ic; 3084 struct ieee80211_node *ni; 3085 struct ether_header *eh; 3086 struct mbuf *m; 3087 int ac; 3088 3089 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3090 return; 3091 3092 for (;;) { 3093 if (sc->qfullmsk != 0) { 3094 ifp->if_flags |= IFF_OACTIVE; 3095 break; 3096 } 3097 /* Send pending management frames first. */ 3098 IF_DEQUEUE(&ic->ic_mgtq, m); 3099 if (m != NULL) { 3100 ni = (void *)m->m_pkthdr.rcvif; 3101 ac = 0; 3102 goto sendit; 3103 } 3104 if (ic->ic_state != IEEE80211_S_RUN) 3105 break; 3106 3107 /* Encapsulate and send data frames. */ 3108 IFQ_DEQUEUE(&ifp->if_snd, m); 3109 if (m == NULL) 3110 break; 3111 if (m->m_len < sizeof (*eh) && 3112 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3113 ifp->if_oerrors++; 3114 continue; 3115 } 3116 eh = mtod(m, struct ether_header *); 3117 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3118 if (ni == NULL) { 3119 m_freem(m); 3120 ifp->if_oerrors++; 3121 continue; 3122 } 3123 /* classify mbuf so we can find which tx ring to use */ 3124 if (ieee80211_classify(ic, m, ni) != 0) { 3125 m_freem(m); 3126 ieee80211_free_node(ni); 3127 ifp->if_oerrors++; 3128 continue; 3129 } 3130 3131 /* No QoS encapsulation for EAPOL frames. */ 3132 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3133 M_WME_GETAC(m) : WME_AC_BE; 3134 3135 bpf_mtap(ifp, m); 3136 3137 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3138 ieee80211_free_node(ni); 3139 ifp->if_oerrors++; 3140 continue; 3141 } 3142 sendit: 3143 bpf_mtap3(ic->ic_rawbpf, m); 3144 3145 if (iwn_tx(sc, m, ni, ac) != 0) { 3146 ieee80211_free_node(ni); 3147 ifp->if_oerrors++; 3148 continue; 3149 } 3150 3151 sc->sc_tx_timer = 5; 3152 ifp->if_timer = 1; 3153 } 3154 } 3155 3156 static void 3157 iwn_watchdog(struct ifnet *ifp) 3158 { 3159 struct iwn_softc *sc = ifp->if_softc; 3160 3161 ifp->if_timer = 0; 3162 3163 if (sc->sc_tx_timer > 0) { 3164 if (--sc->sc_tx_timer == 0) { 3165 aprint_error_dev(sc->sc_dev, 3166 "device timeout\n"); 3167 ifp->if_flags &= ~IFF_UP; 3168 iwn_stop(ifp, 1); 3169 ifp->if_oerrors++; 3170 return; 3171 } 3172 ifp->if_timer = 1; 3173 } 3174 3175 ieee80211_watchdog(&sc->sc_ic); 3176 } 3177 3178 static int 3179 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3180 { 3181 struct iwn_softc *sc = ifp->if_softc; 3182 struct ieee80211com *ic = &sc->sc_ic; 3183 const struct sockaddr *sa; 3184 int s, error = 0; 3185 3186 s = splnet(); 3187 3188 switch (cmd) { 3189 case SIOCSIFADDR: 3190 ifp->if_flags |= IFF_UP; 3191 /* FALLTHROUGH */ 3192 case SIOCSIFFLAGS: 3193 /* XXX Added as it is in every NetBSD driver */ 3194 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3195 break; 3196 if (ifp->if_flags & IFF_UP) { 3197 if (!(ifp->if_flags & IFF_RUNNING)) 3198 error = iwn_init(ifp); 3199 } else { 3200 if (ifp->if_flags & IFF_RUNNING) 3201 iwn_stop(ifp, 1); 3202 } 3203 break; 3204 3205 case SIOCADDMULTI: 3206 case SIOCDELMULTI: 3207 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3208 error = (cmd == SIOCADDMULTI) ? 3209 ether_addmulti(sa, &sc->sc_ec) : 3210 ether_delmulti(sa, &sc->sc_ec); 3211 3212 if (error == ENETRESET) 3213 error = 0; 3214 break; 3215 3216 default: 3217 error = ieee80211_ioctl(ic, cmd, data); 3218 } 3219 3220 if (error == ENETRESET) { 3221 error = 0; 3222 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3223 (IFF_UP | IFF_RUNNING)) { 3224 iwn_stop(ifp, 0); 3225 error = iwn_init(ifp); 3226 } 3227 } 3228 3229 splx(s); 3230 return error; 3231 } 3232 3233 /* 3234 * Send a command to the firmware. 3235 */ 3236 static int 3237 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3238 { 3239 struct iwn_tx_ring *ring = &sc->txq[4]; 3240 struct iwn_tx_desc *desc; 3241 struct iwn_tx_data *data; 3242 struct iwn_tx_cmd *cmd; 3243 struct mbuf *m; 3244 bus_addr_t paddr; 3245 int totlen, error; 3246 3247 desc = &ring->desc[ring->cur]; 3248 data = &ring->data[ring->cur]; 3249 totlen = 4 + size; 3250 3251 if (size > sizeof cmd->data) { 3252 /* Command is too large to fit in a descriptor. */ 3253 if (totlen > MCLBYTES) 3254 return EINVAL; 3255 MGETHDR(m, M_DONTWAIT, MT_DATA); 3256 if (m == NULL) 3257 return ENOMEM; 3258 if (totlen > MHLEN) { 3259 MCLGET(m, M_DONTWAIT); 3260 if (!(m->m_flags & M_EXT)) { 3261 m_freem(m); 3262 return ENOMEM; 3263 } 3264 } 3265 cmd = mtod(m, struct iwn_tx_cmd *); 3266 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3267 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3268 if (error != 0) { 3269 m_freem(m); 3270 return error; 3271 } 3272 data->m = m; 3273 paddr = data->map->dm_segs[0].ds_addr; 3274 } else { 3275 cmd = &ring->cmd[ring->cur]; 3276 paddr = data->cmd_paddr; 3277 } 3278 3279 cmd->code = code; 3280 cmd->flags = 0; 3281 cmd->qid = ring->qid; 3282 cmd->idx = ring->cur; 3283 memcpy(cmd->data, buf, size); 3284 3285 desc->nsegs = 1; 3286 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3287 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3288 3289 if (size > sizeof cmd->data) { 3290 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3291 BUS_DMASYNC_PREWRITE); 3292 } else { 3293 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3294 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3295 totlen, BUS_DMASYNC_PREWRITE); 3296 } 3297 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3298 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3299 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3300 3301 #ifdef notyet 3302 /* Update TX scheduler. */ 3303 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3304 #endif 3305 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3306 3307 /* Kick command ring. */ 3308 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3309 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3310 3311 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3312 } 3313 3314 static int 3315 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3316 { 3317 struct iwn4965_node_info hnode; 3318 char *src, *dst; 3319 3320 /* 3321 * We use the node structure for 5000 Series internally (it is 3322 * a superset of the one for 4965AGN). We thus copy the common 3323 * fields before sending the command. 3324 */ 3325 src = (char *)node; 3326 dst = (char *)&hnode; 3327 memcpy(dst, src, 48); 3328 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3329 memcpy(dst + 48, src + 72, 20); 3330 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3331 } 3332 3333 static int 3334 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3335 { 3336 /* Direct mapping. */ 3337 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3338 } 3339 3340 static int 3341 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3342 { 3343 struct iwn_node *wn = (void *)ni; 3344 struct ieee80211_rateset *rs = &ni->ni_rates; 3345 struct iwn_cmd_link_quality linkq; 3346 const struct iwn_rate *rinfo; 3347 uint8_t txant; 3348 int i, txrate; 3349 3350 /* Use the first valid TX antenna. */ 3351 txant = IWN_LSB(sc->txchainmask); 3352 3353 memset(&linkq, 0, sizeof linkq); 3354 linkq.id = wn->id; 3355 linkq.antmsk_1stream = txant; 3356 linkq.antmsk_2stream = IWN_ANT_AB; 3357 linkq.ampdu_max = 31; 3358 linkq.ampdu_threshold = 3; 3359 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3360 3361 /* Start at highest available bit-rate. */ 3362 txrate = rs->rs_nrates - 1; 3363 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3364 rinfo = &iwn_rates[wn->ridx[txrate]]; 3365 linkq.retry[i].plcp = rinfo->plcp; 3366 linkq.retry[i].rflags = rinfo->flags; 3367 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3368 /* Next retry at immediate lower bit-rate. */ 3369 if (txrate > 0) 3370 txrate--; 3371 } 3372 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3373 } 3374 3375 /* 3376 * Broadcast node is used to send group-addressed and management frames. 3377 */ 3378 static int 3379 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3380 { 3381 struct iwn_ops *ops = &sc->ops; 3382 struct iwn_node_info node; 3383 struct iwn_cmd_link_quality linkq; 3384 const struct iwn_rate *rinfo; 3385 uint8_t txant; 3386 int i, error; 3387 3388 memset(&node, 0, sizeof node); 3389 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3390 node.id = sc->broadcast_id; 3391 DPRINTF(("adding broadcast node\n")); 3392 if ((error = ops->add_node(sc, &node, async)) != 0) 3393 return error; 3394 3395 /* Use the first valid TX antenna. */ 3396 txant = IWN_LSB(sc->txchainmask); 3397 3398 memset(&linkq, 0, sizeof linkq); 3399 linkq.id = sc->broadcast_id; 3400 linkq.antmsk_1stream = txant; 3401 linkq.antmsk_2stream = IWN_ANT_AB; 3402 linkq.ampdu_max = 64; 3403 linkq.ampdu_threshold = 3; 3404 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3405 3406 /* Use lowest mandatory bit-rate. */ 3407 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3408 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3409 linkq.retry[0].plcp = rinfo->plcp; 3410 linkq.retry[0].rflags = rinfo->flags; 3411 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3412 /* Use same bit-rate for all TX retries. */ 3413 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3414 linkq.retry[i].plcp = linkq.retry[0].plcp; 3415 linkq.retry[i].rflags = linkq.retry[0].rflags; 3416 } 3417 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3418 } 3419 3420 static void 3421 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3422 { 3423 struct iwn_cmd_led led; 3424 3425 /* Clear microcode LED ownership. */ 3426 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3427 3428 led.which = which; 3429 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3430 led.off = off; 3431 led.on = on; 3432 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3433 } 3434 3435 /* 3436 * Set the critical temperature at which the firmware will stop the radio 3437 * and notify us. 3438 */ 3439 static int 3440 iwn_set_critical_temp(struct iwn_softc *sc) 3441 { 3442 struct iwn_critical_temp crit; 3443 int32_t temp; 3444 3445 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3446 3447 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3448 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3449 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3450 temp = IWN_CTOK(110); 3451 else 3452 temp = 110; 3453 memset(&crit, 0, sizeof crit); 3454 crit.tempR = htole32(temp); 3455 DPRINTF(("setting critical temperature to %d\n", temp)); 3456 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3457 } 3458 3459 static int 3460 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3461 { 3462 struct iwn_cmd_timing cmd; 3463 uint64_t val, mod; 3464 3465 memset(&cmd, 0, sizeof cmd); 3466 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3467 cmd.bintval = htole16(ni->ni_intval); 3468 cmd.lintval = htole16(10); 3469 3470 /* Compute remaining time until next beacon. */ 3471 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3472 mod = le64toh(cmd.tstamp) % val; 3473 cmd.binitval = htole32((uint32_t)(val - mod)); 3474 3475 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3476 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3477 3478 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3479 } 3480 3481 static void 3482 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3483 { 3484 /* Adjust TX power if need be (delta >= 3 degC). */ 3485 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3486 if (abs(temp - sc->temp) >= 3) { 3487 /* Record temperature of last calibration. */ 3488 sc->temp = temp; 3489 (void)iwn4965_set_txpower(sc, 1); 3490 } 3491 } 3492 3493 /* 3494 * Set TX power for current channel (each rate has its own power settings). 3495 * This function takes into account the regulatory information from EEPROM, 3496 * the current temperature and the current voltage. 3497 */ 3498 static int 3499 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3500 { 3501 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3502 #define fdivround(a, b, n) \ 3503 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3504 /* Linear interpolation. */ 3505 #define interpolate(x, x1, y1, x2, y2, n) \ 3506 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3507 3508 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3509 struct ieee80211com *ic = &sc->sc_ic; 3510 struct iwn_ucode_info *uc = &sc->ucode_info; 3511 struct ieee80211_channel *ch; 3512 struct iwn4965_cmd_txpower cmd; 3513 struct iwn4965_eeprom_chan_samples *chans; 3514 const uint8_t *rf_gain, *dsp_gain; 3515 int32_t vdiff, tdiff; 3516 int i, c, grp, maxpwr; 3517 uint8_t chan; 3518 3519 /* Retrieve current channel from last RXON. */ 3520 chan = sc->rxon.chan; 3521 DPRINTF(("setting TX power for channel %d\n", chan)); 3522 ch = &ic->ic_channels[chan]; 3523 3524 memset(&cmd, 0, sizeof cmd); 3525 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3526 cmd.chan = chan; 3527 3528 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3529 maxpwr = sc->maxpwr5GHz; 3530 rf_gain = iwn4965_rf_gain_5ghz; 3531 dsp_gain = iwn4965_dsp_gain_5ghz; 3532 } else { 3533 maxpwr = sc->maxpwr2GHz; 3534 rf_gain = iwn4965_rf_gain_2ghz; 3535 dsp_gain = iwn4965_dsp_gain_2ghz; 3536 } 3537 3538 /* Compute voltage compensation. */ 3539 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3540 if (vdiff > 0) 3541 vdiff *= 2; 3542 if (abs(vdiff) > 2) 3543 vdiff = 0; 3544 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3545 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3546 3547 /* Get channel attenuation group. */ 3548 if (chan <= 20) /* 1-20 */ 3549 grp = 4; 3550 else if (chan <= 43) /* 34-43 */ 3551 grp = 0; 3552 else if (chan <= 70) /* 44-70 */ 3553 grp = 1; 3554 else if (chan <= 124) /* 71-124 */ 3555 grp = 2; 3556 else /* 125-200 */ 3557 grp = 3; 3558 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3559 3560 /* Get channel sub-band. */ 3561 for (i = 0; i < IWN_NBANDS; i++) 3562 if (sc->bands[i].lo != 0 && 3563 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3564 break; 3565 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3566 return EINVAL; 3567 chans = sc->bands[i].chans; 3568 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3569 3570 for (c = 0; c < 2; c++) { 3571 uint8_t power, gain, temp; 3572 int maxchpwr, pwr, ridx, idx; 3573 3574 power = interpolate(chan, 3575 chans[0].num, chans[0].samples[c][1].power, 3576 chans[1].num, chans[1].samples[c][1].power, 1); 3577 gain = interpolate(chan, 3578 chans[0].num, chans[0].samples[c][1].gain, 3579 chans[1].num, chans[1].samples[c][1].gain, 1); 3580 temp = interpolate(chan, 3581 chans[0].num, chans[0].samples[c][1].temp, 3582 chans[1].num, chans[1].samples[c][1].temp, 1); 3583 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3584 c, power, gain, temp)); 3585 3586 /* Compute temperature compensation. */ 3587 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3588 DPRINTF(("temperature compensation=%d (current=%d, " 3589 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3590 3591 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3592 /* Convert dBm to half-dBm. */ 3593 maxchpwr = sc->maxpwr[chan] * 2; 3594 if ((ridx / 8) & 1) 3595 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3596 3597 pwr = maxpwr; 3598 3599 /* Adjust TX power based on rate. */ 3600 if ((ridx % 8) == 5) 3601 pwr -= 15; /* OFDM48: -7.5dB */ 3602 else if ((ridx % 8) == 6) 3603 pwr -= 17; /* OFDM54: -8.5dB */ 3604 else if ((ridx % 8) == 7) 3605 pwr -= 20; /* OFDM60: -10dB */ 3606 else 3607 pwr -= 10; /* Others: -5dB */ 3608 3609 /* Do not exceed channel max TX power. */ 3610 if (pwr > maxchpwr) 3611 pwr = maxchpwr; 3612 3613 idx = gain - (pwr - power) - tdiff - vdiff; 3614 if ((ridx / 8) & 1) /* MIMO */ 3615 idx += (int32_t)le32toh(uc->atten[grp][c]); 3616 3617 if (cmd.band == 0) 3618 idx += 9; /* 5GHz */ 3619 if (ridx == IWN_RIDX_MAX) 3620 idx += 5; /* CCK */ 3621 3622 /* Make sure idx stays in a valid range. */ 3623 if (idx < 0) 3624 idx = 0; 3625 else if (idx > IWN4965_MAX_PWR_INDEX) 3626 idx = IWN4965_MAX_PWR_INDEX; 3627 3628 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3629 c, ridx, idx)); 3630 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3631 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3632 } 3633 } 3634 3635 DPRINTF(("setting TX power for chan %d\n", chan)); 3636 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3637 3638 #undef interpolate 3639 #undef fdivround 3640 } 3641 3642 static int 3643 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3644 { 3645 struct iwn5000_cmd_txpower cmd; 3646 3647 /* 3648 * TX power calibration is handled automatically by the firmware 3649 * for 5000 Series. 3650 */ 3651 memset(&cmd, 0, sizeof cmd); 3652 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3653 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3654 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3655 DPRINTF(("setting TX power\n")); 3656 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 3657 } 3658 3659 /* 3660 * Retrieve the maximum RSSI (in dBm) among receivers. 3661 */ 3662 static int 3663 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3664 { 3665 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3666 uint8_t mask, agc; 3667 int rssi; 3668 3669 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3670 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3671 3672 rssi = 0; 3673 if (mask & IWN_ANT_A) 3674 rssi = MAX(rssi, phy->rssi[0]); 3675 if (mask & IWN_ANT_B) 3676 rssi = MAX(rssi, phy->rssi[2]); 3677 if (mask & IWN_ANT_C) 3678 rssi = MAX(rssi, phy->rssi[4]); 3679 3680 return rssi - agc - IWN_RSSI_TO_DBM; 3681 } 3682 3683 static int 3684 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3685 { 3686 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3687 uint8_t agc; 3688 int rssi; 3689 3690 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3691 3692 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3693 le16toh(phy->rssi[1]) & 0xff); 3694 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3695 3696 return rssi - agc - IWN_RSSI_TO_DBM; 3697 } 3698 3699 /* 3700 * Retrieve the average noise (in dBm) among receivers. 3701 */ 3702 static int 3703 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3704 { 3705 int i, total, nbant, noise; 3706 3707 total = nbant = 0; 3708 for (i = 0; i < 3; i++) { 3709 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3710 continue; 3711 total += noise; 3712 nbant++; 3713 } 3714 /* There should be at least one antenna but check anyway. */ 3715 return (nbant == 0) ? -127 : (total / nbant) - 107; 3716 } 3717 3718 /* 3719 * Compute temperature (in degC) from last received statistics. 3720 */ 3721 static int 3722 iwn4965_get_temperature(struct iwn_softc *sc) 3723 { 3724 struct iwn_ucode_info *uc = &sc->ucode_info; 3725 int32_t r1, r2, r3, r4, temp; 3726 3727 r1 = le32toh(uc->temp[0].chan20MHz); 3728 r2 = le32toh(uc->temp[1].chan20MHz); 3729 r3 = le32toh(uc->temp[2].chan20MHz); 3730 r4 = le32toh(sc->rawtemp); 3731 3732 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3733 return 0; 3734 3735 /* Sign-extend 23-bit R4 value to 32-bit. */ 3736 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3737 /* Compute temperature in Kelvin. */ 3738 temp = (259 * (r4 - r2)) / (r3 - r1); 3739 temp = (temp * 97) / 100 + 8; 3740 3741 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3742 return IWN_KTOC(temp); 3743 } 3744 3745 static int 3746 iwn5000_get_temperature(struct iwn_softc *sc) 3747 { 3748 int32_t temp; 3749 3750 /* 3751 * Temperature is not used by the driver for 5000 Series because 3752 * TX power calibration is handled by firmware. We export it to 3753 * users through the sensor framework though. 3754 */ 3755 temp = le32toh(sc->rawtemp); 3756 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3757 temp = (temp / -5) + sc->temp_off; 3758 temp = IWN_KTOC(temp); 3759 } 3760 return temp; 3761 } 3762 3763 /* 3764 * Initialize sensitivity calibration state machine. 3765 */ 3766 static int 3767 iwn_init_sensitivity(struct iwn_softc *sc) 3768 { 3769 struct iwn_ops *ops = &sc->ops; 3770 struct iwn_calib_state *calib = &sc->calib; 3771 uint32_t flags; 3772 int error; 3773 3774 /* Reset calibration state machine. */ 3775 memset(calib, 0, sizeof (*calib)); 3776 calib->state = IWN_CALIB_STATE_INIT; 3777 calib->cck_state = IWN_CCK_STATE_HIFA; 3778 /* Set initial correlation values. */ 3779 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3780 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3781 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3782 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3783 calib->cck_x4 = 125; 3784 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3785 calib->energy_cck = sc->limits->energy_cck; 3786 3787 /* Write initial sensitivity. */ 3788 if ((error = iwn_send_sensitivity(sc)) != 0) 3789 return error; 3790 3791 /* Write initial gains. */ 3792 if ((error = ops->init_gains(sc)) != 0) 3793 return error; 3794 3795 /* Request statistics at each beacon interval. */ 3796 flags = 0; 3797 DPRINTF(("sending request for statistics\n")); 3798 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3799 } 3800 3801 /* 3802 * Collect noise and RSSI statistics for the first 20 beacons received 3803 * after association and use them to determine connected antennas and 3804 * to set differential gains. 3805 */ 3806 static void 3807 iwn_collect_noise(struct iwn_softc *sc, 3808 const struct iwn_rx_general_stats *stats) 3809 { 3810 struct iwn_ops *ops = &sc->ops; 3811 struct iwn_calib_state *calib = &sc->calib; 3812 uint32_t val; 3813 int i; 3814 3815 /* Accumulate RSSI and noise for all 3 antennas. */ 3816 for (i = 0; i < 3; i++) { 3817 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3818 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3819 } 3820 /* NB: We update differential gains only once after 20 beacons. */ 3821 if (++calib->nbeacons < 20) 3822 return; 3823 3824 /* Determine highest average RSSI. */ 3825 val = MAX(calib->rssi[0], calib->rssi[1]); 3826 val = MAX(calib->rssi[2], val); 3827 3828 /* Determine which antennas are connected. */ 3829 sc->chainmask = sc->rxchainmask; 3830 for (i = 0; i < 3; i++) 3831 if (val - calib->rssi[i] > 15 * 20) 3832 sc->chainmask &= ~(1 << i); 3833 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3834 sc->rxchainmask, sc->chainmask)); 3835 3836 /* If none of the TX antennas are connected, keep at least one. */ 3837 if ((sc->chainmask & sc->txchainmask) == 0) 3838 sc->chainmask |= IWN_LSB(sc->txchainmask); 3839 3840 (void)ops->set_gains(sc); 3841 calib->state = IWN_CALIB_STATE_RUN; 3842 3843 #ifdef notyet 3844 /* XXX Disable RX chains with no antennas connected. */ 3845 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3846 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3847 #endif 3848 3849 /* Enable power-saving mode if requested by user. */ 3850 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3851 (void)iwn_set_pslevel(sc, 0, 3, 1); 3852 } 3853 3854 static int 3855 iwn4965_init_gains(struct iwn_softc *sc) 3856 { 3857 struct iwn_phy_calib_gain cmd; 3858 3859 memset(&cmd, 0, sizeof cmd); 3860 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3861 /* Differential gains initially set to 0 for all 3 antennas. */ 3862 DPRINTF(("setting initial differential gains\n")); 3863 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3864 } 3865 3866 static int 3867 iwn5000_init_gains(struct iwn_softc *sc) 3868 { 3869 struct iwn_phy_calib cmd; 3870 3871 memset(&cmd, 0, sizeof cmd); 3872 cmd.code = sc->reset_noise_gain; 3873 cmd.ngroups = 1; 3874 cmd.isvalid = 1; 3875 DPRINTF(("setting initial differential gains\n")); 3876 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3877 } 3878 3879 static int 3880 iwn4965_set_gains(struct iwn_softc *sc) 3881 { 3882 struct iwn_calib_state *calib = &sc->calib; 3883 struct iwn_phy_calib_gain cmd; 3884 int i, delta, noise; 3885 3886 /* Get minimal noise among connected antennas. */ 3887 noise = INT_MAX; /* NB: There's at least one antenna. */ 3888 for (i = 0; i < 3; i++) 3889 if (sc->chainmask & (1 << i)) 3890 noise = MIN(calib->noise[i], noise); 3891 3892 memset(&cmd, 0, sizeof cmd); 3893 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3894 /* Set differential gains for connected antennas. */ 3895 for (i = 0; i < 3; i++) { 3896 if (sc->chainmask & (1 << i)) { 3897 /* Compute attenuation (in unit of 1.5dB). */ 3898 delta = (noise - (int32_t)calib->noise[i]) / 30; 3899 /* NB: delta <= 0 */ 3900 /* Limit to [-4.5dB,0]. */ 3901 cmd.gain[i] = MIN(abs(delta), 3); 3902 if (delta < 0) 3903 cmd.gain[i] |= 1 << 2; /* sign bit */ 3904 } 3905 } 3906 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 3907 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 3908 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3909 } 3910 3911 static int 3912 iwn5000_set_gains(struct iwn_softc *sc) 3913 { 3914 struct iwn_calib_state *calib = &sc->calib; 3915 struct iwn_phy_calib_gain cmd; 3916 int i, ant, div, delta; 3917 3918 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 3919 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 3920 3921 memset(&cmd, 0, sizeof cmd); 3922 cmd.code = sc->noise_gain; 3923 cmd.ngroups = 1; 3924 cmd.isvalid = 1; 3925 /* Get first available RX antenna as referential. */ 3926 ant = IWN_LSB(sc->rxchainmask); 3927 /* Set differential gains for other antennas. */ 3928 for (i = ant + 1; i < 3; i++) { 3929 if (sc->chainmask & (1 << i)) { 3930 /* The delta is relative to antenna "ant". */ 3931 delta = ((int32_t)calib->noise[ant] - 3932 (int32_t)calib->noise[i]) / div; 3933 /* Limit to [-4.5dB,+4.5dB]. */ 3934 cmd.gain[i - 1] = MIN(abs(delta), 3); 3935 if (delta < 0) 3936 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 3937 } 3938 } 3939 DPRINTF(("setting differential gains: %x/%x (%x)\n", 3940 cmd.gain[0], cmd.gain[1], sc->chainmask)); 3941 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3942 } 3943 3944 /* 3945 * Tune RF RX sensitivity based on the number of false alarms detected 3946 * during the last beacon period. 3947 */ 3948 static void 3949 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 3950 { 3951 #define inc(val, inc, max) \ 3952 if ((val) < (max)) { \ 3953 if ((val) < (max) - (inc)) \ 3954 (val) += (inc); \ 3955 else \ 3956 (val) = (max); \ 3957 needs_update = 1; \ 3958 } 3959 #define dec(val, dec, min) \ 3960 if ((val) > (min)) { \ 3961 if ((val) > (min) + (dec)) \ 3962 (val) -= (dec); \ 3963 else \ 3964 (val) = (min); \ 3965 needs_update = 1; \ 3966 } 3967 3968 const struct iwn_sensitivity_limits *limits = sc->limits; 3969 struct iwn_calib_state *calib = &sc->calib; 3970 uint32_t val, rxena, fa; 3971 uint32_t energy[3], energy_min; 3972 uint8_t noise[3], noise_ref; 3973 int i, needs_update = 0; 3974 3975 /* Check that we've been enabled long enough. */ 3976 if ((rxena = le32toh(stats->general.load)) == 0) 3977 return; 3978 3979 /* Compute number of false alarms since last call for OFDM. */ 3980 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 3981 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 3982 fa *= 200 * 1024; /* 200TU */ 3983 3984 /* Save counters values for next call. */ 3985 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 3986 calib->fa_ofdm = le32toh(stats->ofdm.fa); 3987 3988 if (fa > 50 * rxena) { 3989 /* High false alarm count, decrease sensitivity. */ 3990 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 3991 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 3992 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 3993 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 3994 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 3995 3996 } else if (fa < 5 * rxena) { 3997 /* Low false alarm count, increase sensitivity. */ 3998 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 3999 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4000 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4001 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4002 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4003 } 4004 4005 /* Compute maximum noise among 3 receivers. */ 4006 for (i = 0; i < 3; i++) 4007 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4008 val = MAX(noise[0], noise[1]); 4009 val = MAX(noise[2], val); 4010 /* Insert it into our samples table. */ 4011 calib->noise_samples[calib->cur_noise_sample] = val; 4012 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4013 4014 /* Compute maximum noise among last 20 samples. */ 4015 noise_ref = calib->noise_samples[0]; 4016 for (i = 1; i < 20; i++) 4017 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4018 4019 /* Compute maximum energy among 3 receivers. */ 4020 for (i = 0; i < 3; i++) 4021 energy[i] = le32toh(stats->general.energy[i]); 4022 val = MIN(energy[0], energy[1]); 4023 val = MIN(energy[2], val); 4024 /* Insert it into our samples table. */ 4025 calib->energy_samples[calib->cur_energy_sample] = val; 4026 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4027 4028 /* Compute minimum energy among last 10 samples. */ 4029 energy_min = calib->energy_samples[0]; 4030 for (i = 1; i < 10; i++) 4031 energy_min = MAX(energy_min, calib->energy_samples[i]); 4032 energy_min += 6; 4033 4034 /* Compute number of false alarms since last call for CCK. */ 4035 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4036 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4037 fa *= 200 * 1024; /* 200TU */ 4038 4039 /* Save counters values for next call. */ 4040 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4041 calib->fa_cck = le32toh(stats->cck.fa); 4042 4043 if (fa > 50 * rxena) { 4044 /* High false alarm count, decrease sensitivity. */ 4045 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4046 calib->cck_state = IWN_CCK_STATE_HIFA; 4047 calib->low_fa = 0; 4048 4049 if (calib->cck_x4 > 160) { 4050 calib->noise_ref = noise_ref; 4051 if (calib->energy_cck > 2) 4052 dec(calib->energy_cck, 2, energy_min); 4053 } 4054 if (calib->cck_x4 < 160) { 4055 calib->cck_x4 = 161; 4056 needs_update = 1; 4057 } else 4058 inc(calib->cck_x4, 3, limits->max_cck_x4); 4059 4060 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4061 4062 } else if (fa < 5 * rxena) { 4063 /* Low false alarm count, increase sensitivity. */ 4064 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4065 calib->cck_state = IWN_CCK_STATE_LOFA; 4066 calib->low_fa++; 4067 4068 if (calib->cck_state != IWN_CCK_STATE_INIT && 4069 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4070 calib->low_fa > 100)) { 4071 inc(calib->energy_cck, 2, limits->min_energy_cck); 4072 dec(calib->cck_x4, 3, limits->min_cck_x4); 4073 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4074 } 4075 } else { 4076 /* Not worth to increase or decrease sensitivity. */ 4077 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4078 calib->low_fa = 0; 4079 calib->noise_ref = noise_ref; 4080 4081 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4082 /* Previous interval had many false alarms. */ 4083 dec(calib->energy_cck, 8, energy_min); 4084 } 4085 calib->cck_state = IWN_CCK_STATE_INIT; 4086 } 4087 4088 if (needs_update) 4089 (void)iwn_send_sensitivity(sc); 4090 #undef dec 4091 #undef inc 4092 } 4093 4094 static int 4095 iwn_send_sensitivity(struct iwn_softc *sc) 4096 { 4097 struct iwn_calib_state *calib = &sc->calib; 4098 struct iwn_enhanced_sensitivity_cmd cmd; 4099 int len; 4100 4101 memset(&cmd, 0, sizeof cmd); 4102 len = sizeof (struct iwn_sensitivity_cmd); 4103 cmd.which = IWN_SENSITIVITY_WORKTBL; 4104 /* OFDM modulation. */ 4105 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4106 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4107 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4108 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4109 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4110 cmd.energy_ofdm_th = htole16(62); 4111 /* CCK modulation. */ 4112 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4113 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4114 cmd.energy_cck = htole16(calib->energy_cck); 4115 /* Barker modulation: use default values. */ 4116 cmd.corr_barker = htole16(190); 4117 cmd.corr_barker_mrc = htole16(390); 4118 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4119 goto send; 4120 /* Enhanced sensitivity settings. */ 4121 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4122 cmd.ofdm_det_slope_mrc = htole16(668); 4123 cmd.ofdm_det_icept_mrc = htole16(4); 4124 cmd.ofdm_det_slope = htole16(486); 4125 cmd.ofdm_det_icept = htole16(37); 4126 cmd.cck_det_slope_mrc = htole16(853); 4127 cmd.cck_det_icept_mrc = htole16(4); 4128 cmd.cck_det_slope = htole16(476); 4129 cmd.cck_det_icept = htole16(99); 4130 send: 4131 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4132 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4133 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4134 calib->energy_cck)); 4135 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4136 } 4137 4138 /* 4139 * Set STA mode power saving level (between 0 and 5). 4140 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4141 */ 4142 static int 4143 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4144 { 4145 struct iwn_pmgt_cmd cmd; 4146 const struct iwn_pmgt *pmgt; 4147 uint32_t maxp, skip_dtim; 4148 pcireg_t reg; 4149 int i; 4150 4151 /* Select which PS parameters to use. */ 4152 if (dtim <= 2) 4153 pmgt = &iwn_pmgt[0][level]; 4154 else if (dtim <= 10) 4155 pmgt = &iwn_pmgt[1][level]; 4156 else 4157 pmgt = &iwn_pmgt[2][level]; 4158 4159 memset(&cmd, 0, sizeof cmd); 4160 if (level != 0) /* not CAM */ 4161 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4162 if (level == 5) 4163 cmd.flags |= htole16(IWN_PS_FAST_PD); 4164 /* Retrieve PCIe Active State Power Management (ASPM). */ 4165 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4166 sc->sc_cap_off + PCIE_LCSR); 4167 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4168 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4169 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4170 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4171 4172 if (dtim == 0) { 4173 dtim = 1; 4174 skip_dtim = 0; 4175 } else 4176 skip_dtim = pmgt->skip_dtim; 4177 if (skip_dtim != 0) { 4178 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4179 maxp = pmgt->intval[4]; 4180 if (maxp == (uint32_t)-1) 4181 maxp = dtim * (skip_dtim + 1); 4182 else if (maxp > dtim) 4183 maxp = (maxp / dtim) * dtim; 4184 } else 4185 maxp = dtim; 4186 for (i = 0; i < 5; i++) 4187 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4188 4189 DPRINTF(("setting power saving level to %d\n", level)); 4190 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4191 } 4192 4193 int 4194 iwn5000_runtime_calib(struct iwn_softc *sc) 4195 { 4196 struct iwn5000_calib_config cmd; 4197 4198 memset(&cmd, 0, sizeof cmd); 4199 cmd.ucode.once.enable = 0xffffffff; 4200 cmd.ucode.once.start = IWN5000_CALIB_DC; 4201 DPRINTF(("configuring runtime calibration\n")); 4202 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4203 } 4204 4205 static int 4206 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc) 4207 { 4208 struct iwn_bluetooth bluetooth; 4209 4210 memset(&bluetooth, 0, sizeof bluetooth); 4211 bluetooth.flags = IWN_BT_COEX_ENABLE; 4212 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4213 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4214 4215 DPRINTF(("configuring bluetooth coexistence\n")); 4216 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4217 } 4218 4219 static int 4220 iwn_config_bt_coex_prio_table(struct iwn_softc *sc) 4221 { 4222 uint8_t prio_table[16]; 4223 4224 memset(&prio_table, 0, sizeof prio_table); 4225 prio_table[ 0] = 6; /* init calibration 1 */ 4226 prio_table[ 1] = 7; /* init calibration 2 */ 4227 prio_table[ 2] = 2; /* periodic calib low 1 */ 4228 prio_table[ 3] = 3; /* periodic calib low 2 */ 4229 prio_table[ 4] = 4; /* periodic calib high 1 */ 4230 prio_table[ 5] = 5; /* periodic calib high 2 */ 4231 prio_table[ 6] = 6; /* dtim */ 4232 prio_table[ 7] = 8; /* scan52 */ 4233 prio_table[ 8] = 10; /* scan24 */ 4234 4235 DPRINTF(("sending priority lookup table\n")); 4236 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE, 4237 &prio_table, sizeof prio_table, 0); 4238 } 4239 4240 static int 4241 iwn_config_bt_coex_adv_config(struct iwn_softc *sc, struct iwn_bt_basic *basic, 4242 size_t len) 4243 { 4244 struct iwn_btcoex_prot btprot; 4245 int error; 4246 4247 basic->bt.flags = IWN_BT_COEX_ENABLE; 4248 basic->bt.lead_time = IWN_BT_LEAD_TIME_DEF; 4249 basic->bt.max_kill = IWN_BT_MAX_KILL_DEF; 4250 basic->bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF; 4251 basic->bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF; 4252 basic->bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF; 4253 basic->bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF; 4254 basic->bt3_timer_t2_value = IWN_BT_BT3_T2_DEF; 4255 basic->bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */ 4256 basic->bt3_lookup_table[ 1] = htole32(0xaaaaaaaa); 4257 basic->bt3_lookup_table[ 2] = htole32(0xaeaaaaaa); 4258 basic->bt3_lookup_table[ 3] = htole32(0xaaaaaaaa); 4259 basic->bt3_lookup_table[ 4] = htole32(0xcc00ff28); 4260 basic->bt3_lookup_table[ 5] = htole32(0x0000aaaa); 4261 basic->bt3_lookup_table[ 6] = htole32(0xcc00aaaa); 4262 basic->bt3_lookup_table[ 7] = htole32(0x0000aaaa); 4263 basic->bt3_lookup_table[ 8] = htole32(0xc0004000); 4264 basic->bt3_lookup_table[ 9] = htole32(0x00004000); 4265 basic->bt3_lookup_table[10] = htole32(0xf0005000); 4266 basic->bt3_lookup_table[11] = htole32(0xf0005000); 4267 basic->reduce_txpower = 0; /* as not implemented */ 4268 basic->valid = IWN_BT_ALL_VALID_MASK; 4269 4270 DPRINTF(("configuring advanced bluetooth coexistence v1\n")); 4271 error = iwn_cmd(sc, IWN_CMD_BT_COEX, basic, len, 0); 4272 if (error != 0) { 4273 aprint_error_dev(sc->sc_dev, 4274 "could not configure advanced bluetooth coexistence\n"); 4275 return error; 4276 } 4277 4278 error = iwn_config_bt_coex_prio_table(sc); 4279 if (error != 0) { 4280 aprint_error_dev(sc->sc_dev, 4281 "could not configure send BT priority table\n"); 4282 return error; 4283 } 4284 4285 /* Force BT state machine change */ 4286 memset(&btprot, 0, sizeof btprot); 4287 btprot.open = 1; 4288 btprot.type = 1; 4289 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4290 if (error != 0) { 4291 aprint_error_dev(sc->sc_dev, "could not open BT protcol\n"); 4292 return error; 4293 } 4294 4295 btprot.open = 0; 4296 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4297 if (error != 0) { 4298 aprint_error_dev(sc->sc_dev, "could not close BT protcol\n"); 4299 return error; 4300 } 4301 return 0; 4302 } 4303 4304 static int 4305 iwn_config_bt_coex_adv1(struct iwn_softc *sc) 4306 { 4307 struct iwn_bt_adv1 d; 4308 4309 memset(&d, 0, sizeof d); 4310 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4311 d.tx_prio_boost = 0; 4312 d.rx_prio_boost = 0; 4313 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4314 } 4315 4316 static int 4317 iwn_config_bt_coex_adv2(struct iwn_softc *sc) 4318 { 4319 struct iwn_bt_adv2 d; 4320 4321 memset(&d, 0, sizeof d); 4322 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4323 d.tx_prio_boost = 0; 4324 d.rx_prio_boost = 0; 4325 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4326 } 4327 4328 static int 4329 iwn_config(struct iwn_softc *sc) 4330 { 4331 struct iwn_ops *ops = &sc->ops; 4332 struct ieee80211com *ic = &sc->sc_ic; 4333 struct ifnet *ifp = ic->ic_ifp; 4334 uint32_t txmask; 4335 uint16_t rxchain; 4336 int error; 4337 4338 error = ops->config_bt_coex(sc); 4339 if (error != 0) { 4340 aprint_error_dev(sc->sc_dev, 4341 "could not configure bluetooth coexistence\n"); 4342 return error; 4343 } 4344 4345 /* Set radio temperature sensor offset. */ 4346 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4347 error = iwn6000_temp_offset_calib(sc); 4348 if (error != 0) { 4349 aprint_error_dev(sc->sc_dev, 4350 "could not set temperature offset\n"); 4351 return error; 4352 } 4353 } 4354 4355 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4356 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4357 sc->hw_type == IWN_HW_REV_TYPE_135 || 4358 sc->hw_type == IWN_HW_REV_TYPE_105) { 4359 error = iwn2000_temp_offset_calib(sc); 4360 if (error != 0) { 4361 aprint_error_dev(sc->sc_dev, 4362 "could not set temperature offset\n"); 4363 return error; 4364 } 4365 } 4366 4367 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4368 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4369 /* Configure runtime DC calibration. */ 4370 error = iwn5000_runtime_calib(sc); 4371 if (error != 0) { 4372 aprint_error_dev(sc->sc_dev, 4373 "could not configure runtime calibration\n"); 4374 return error; 4375 } 4376 } 4377 4378 /* Configure valid TX chains for 5000 Series. */ 4379 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4380 txmask = htole32(sc->txchainmask); 4381 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4382 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4383 sizeof txmask, 0); 4384 if (error != 0) { 4385 aprint_error_dev(sc->sc_dev, 4386 "could not configure valid TX chains\n"); 4387 return error; 4388 } 4389 } 4390 4391 /* Set mode, channel, RX filter and enable RX. */ 4392 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4393 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4394 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4395 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4396 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4397 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4398 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4399 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4400 switch (ic->ic_opmode) { 4401 case IEEE80211_M_STA: 4402 sc->rxon.mode = IWN_MODE_STA; 4403 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4404 break; 4405 case IEEE80211_M_MONITOR: 4406 sc->rxon.mode = IWN_MODE_MONITOR; 4407 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4408 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4409 break; 4410 default: 4411 /* Should not get there. */ 4412 break; 4413 } 4414 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4415 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4416 sc->rxon.ht_single_mask = 0xff; 4417 sc->rxon.ht_dual_mask = 0xff; 4418 sc->rxon.ht_triple_mask = 0xff; 4419 rxchain = 4420 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4421 IWN_RXCHAIN_MIMO_COUNT(2) | 4422 IWN_RXCHAIN_IDLE_COUNT(2); 4423 sc->rxon.rxchain = htole16(rxchain); 4424 DPRINTF(("setting configuration\n")); 4425 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4426 if (error != 0) { 4427 aprint_error_dev(sc->sc_dev, 4428 "RXON command failed\n"); 4429 return error; 4430 } 4431 4432 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4433 aprint_error_dev(sc->sc_dev, 4434 "could not add broadcast node\n"); 4435 return error; 4436 } 4437 4438 /* Configuration has changed, set TX power accordingly. */ 4439 if ((error = ops->set_txpower(sc, 0)) != 0) { 4440 aprint_error_dev(sc->sc_dev, 4441 "could not set TX power\n"); 4442 return error; 4443 } 4444 4445 if ((error = iwn_set_critical_temp(sc)) != 0) { 4446 aprint_error_dev(sc->sc_dev, 4447 "could not set critical temperature\n"); 4448 return error; 4449 } 4450 4451 /* Set power saving level to CAM during initialization. */ 4452 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4453 aprint_error_dev(sc->sc_dev, 4454 "could not set power saving level\n"); 4455 return error; 4456 } 4457 return 0; 4458 } 4459 4460 static uint16_t 4461 iwn_get_active_dwell_time(struct iwn_softc *sc, uint16_t flags, 4462 uint8_t n_probes) 4463 { 4464 /* No channel? Default to 2GHz settings */ 4465 if (flags & IEEE80211_CHAN_2GHZ) 4466 return IWN_ACTIVE_DWELL_TIME_2GHZ + 4467 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1); 4468 4469 /* 5GHz dwell time */ 4470 return IWN_ACTIVE_DWELL_TIME_5GHZ + 4471 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1); 4472 } 4473 4474 /* 4475 * Limit the total dwell time to 85% of the beacon interval. 4476 * 4477 * Returns the dwell time in milliseconds. 4478 */ 4479 static uint16_t 4480 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 4481 { 4482 struct ieee80211com *ic = &sc->sc_ic; 4483 struct ieee80211_node *ni = ic->ic_bss; 4484 int bintval = 0; 4485 4486 /* bintval is in TU (1.024mS) */ 4487 if (ni != NULL) 4488 bintval = ni->ni_intval; 4489 4490 /* 4491 * If it's non-zero, we should calculate the minimum of 4492 * it and the DWELL_BASE. 4493 * 4494 * XXX Yes, the math should take into account that bintval 4495 * is 1.024mS, not 1mS.. 4496 */ 4497 if (bintval > 0) 4498 return MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)); 4499 4500 /* No association context? Default */ 4501 return IWN_PASSIVE_DWELL_BASE; 4502 } 4503 4504 static uint16_t 4505 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 4506 { 4507 uint16_t passive; 4508 if (flags & IEEE80211_CHAN_2GHZ) 4509 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 4510 else 4511 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 4512 4513 /* Clamp to the beacon interval if we're associated */ 4514 return iwn_limit_dwell(sc, passive); 4515 } 4516 4517 static int 4518 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4519 { 4520 struct ieee80211com *ic = &sc->sc_ic; 4521 struct iwn_scan_hdr *hdr; 4522 struct iwn_cmd_data *tx; 4523 struct iwn_scan_essid *essid; 4524 struct iwn_scan_chan *chan; 4525 struct ieee80211_frame *wh; 4526 struct ieee80211_rateset *rs; 4527 struct ieee80211_channel *c; 4528 uint8_t *buf, *frm; 4529 uint16_t rxchain, dwell_active, dwell_passive; 4530 uint8_t txant; 4531 int buflen, error, is_active; 4532 4533 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4534 if (buf == NULL) { 4535 aprint_error_dev(sc->sc_dev, 4536 "could not allocate buffer for scan command\n"); 4537 return ENOMEM; 4538 } 4539 hdr = (struct iwn_scan_hdr *)buf; 4540 /* 4541 * Move to the next channel if no frames are received within 10ms 4542 * after sending the probe request. 4543 */ 4544 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4545 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4546 4547 /* Select antennas for scanning. */ 4548 rxchain = 4549 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4550 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4551 IWN_RXCHAIN_DRIVER_FORCE; 4552 if ((flags & IEEE80211_CHAN_5GHZ) && 4553 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4554 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4555 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4556 } else /* Use all available RX antennas. */ 4557 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4558 hdr->rxchain = htole16(rxchain); 4559 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4560 4561 tx = (struct iwn_cmd_data *)(hdr + 1); 4562 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4563 tx->id = sc->broadcast_id; 4564 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4565 4566 if (flags & IEEE80211_CHAN_5GHZ) { 4567 hdr->crc_threshold = 0xffff; 4568 /* Send probe requests at 6Mbps. */ 4569 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4570 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4571 } else { 4572 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4573 /* Send probe requests at 1Mbps. */ 4574 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4575 tx->rflags = IWN_RFLAG_CCK; 4576 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4577 } 4578 /* Use the first valid TX antenna. */ 4579 txant = IWN_LSB(sc->txchainmask); 4580 tx->rflags |= IWN_RFLAG_ANT(txant); 4581 4582 /* 4583 * Only do active scanning if we're announcing a probe request 4584 * for a given SSID (or more, if we ever add it to the driver.) 4585 */ 4586 is_active = 0; 4587 4588 essid = (struct iwn_scan_essid *)(tx + 1); 4589 if (ic->ic_des_esslen != 0) { 4590 essid[0].id = IEEE80211_ELEMID_SSID; 4591 essid[0].len = ic->ic_des_esslen; 4592 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4593 4594 is_active = 1; 4595 } 4596 /* 4597 * Build a probe request frame. Most of the following code is a 4598 * copy & paste of what is done in net80211. 4599 */ 4600 wh = (struct ieee80211_frame *)(essid + 20); 4601 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4602 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4603 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4604 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4605 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4606 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4607 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4608 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4609 4610 frm = (uint8_t *)(wh + 1); 4611 frm = ieee80211_add_ssid(frm, NULL, 0); 4612 frm = ieee80211_add_rates(frm, rs); 4613 #ifndef IEEE80211_NO_HT 4614 if (ic->ic_flags & IEEE80211_F_HTON) 4615 frm = ieee80211_add_htcaps(frm, ic); 4616 #endif 4617 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4618 frm = ieee80211_add_xrates(frm, rs); 4619 4620 /* Set length of probe request. */ 4621 tx->len = htole16(frm - (uint8_t *)wh); 4622 4623 4624 /* 4625 * If active scanning is requested but a certain channel is 4626 * marked passive, we can do active scanning if we detect 4627 * transmissions. 4628 * 4629 * There is an issue with some firmware versions that triggers 4630 * a sysassert on a "good CRC threshold" of zero (== disabled), 4631 * on a radar channel even though this means that we should NOT 4632 * send probes. 4633 * 4634 * The "good CRC threshold" is the number of frames that we 4635 * need to receive during our dwell time on a channel before 4636 * sending out probes -- setting this to a huge value will 4637 * mean we never reach it, but at the same time work around 4638 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 4639 * here instead of IWN_GOOD_CRC_TH_DISABLED. 4640 * 4641 * This was fixed in later versions along with some other 4642 * scan changes, and the threshold behaves as a flag in those 4643 * versions. 4644 */ 4645 4646 /* 4647 * If we're doing active scanning, set the crc_threshold 4648 * to a suitable value. This is different to active veruss 4649 * passive scanning depending upon the channel flags; the 4650 * firmware will obey that particular check for us. 4651 */ 4652 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 4653 hdr->crc_threshold = is_active ? 4654 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 4655 else 4656 hdr->crc_threshold = is_active ? 4657 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 4658 4659 chan = (struct iwn_scan_chan *)frm; 4660 for (c = &ic->ic_channels[1]; 4661 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4662 if ((c->ic_flags & flags) != flags) 4663 continue; 4664 4665 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4666 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4667 chan->flags = 0; 4668 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4669 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4670 if (ic->ic_des_esslen != 0) 4671 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4672 4673 /* 4674 * Calculate the active/passive dwell times. 4675 */ 4676 4677 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 4678 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 4679 4680 /* Make sure they're valid */ 4681 if (dwell_passive <= dwell_active) 4682 dwell_passive = dwell_active + 1; 4683 4684 chan->active = htole16(dwell_active); 4685 chan->passive = htole16(dwell_passive); 4686 4687 chan->dsp_gain = 0x6e; 4688 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4689 chan->rf_gain = 0x3b; 4690 } else { 4691 chan->rf_gain = 0x28; 4692 } 4693 hdr->nchan++; 4694 chan++; 4695 } 4696 4697 buflen = (uint8_t *)chan - buf; 4698 hdr->len = htole16(buflen); 4699 4700 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4701 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4702 free(buf, M_DEVBUF); 4703 return error; 4704 } 4705 4706 static int 4707 iwn_auth(struct iwn_softc *sc) 4708 { 4709 struct iwn_ops *ops = &sc->ops; 4710 struct ieee80211com *ic = &sc->sc_ic; 4711 struct ieee80211_node *ni = ic->ic_bss; 4712 int error; 4713 4714 /* Update adapter configuration. */ 4715 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4716 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4717 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4718 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4719 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4720 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4721 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4722 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4723 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4724 switch (ic->ic_curmode) { 4725 case IEEE80211_MODE_11A: 4726 sc->rxon.cck_mask = 0; 4727 sc->rxon.ofdm_mask = 0x15; 4728 break; 4729 case IEEE80211_MODE_11B: 4730 sc->rxon.cck_mask = 0x03; 4731 sc->rxon.ofdm_mask = 0; 4732 break; 4733 default: /* Assume 802.11b/g. */ 4734 sc->rxon.cck_mask = 0x0f; 4735 sc->rxon.ofdm_mask = 0x15; 4736 } 4737 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4738 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4739 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4740 if (error != 0) { 4741 aprint_error_dev(sc->sc_dev, 4742 "RXON command failed\n"); 4743 return error; 4744 } 4745 4746 /* Configuration has changed, set TX power accordingly. */ 4747 if ((error = ops->set_txpower(sc, 1)) != 0) { 4748 aprint_error_dev(sc->sc_dev, 4749 "could not set TX power\n"); 4750 return error; 4751 } 4752 /* 4753 * Reconfiguring RXON clears the firmware nodes table so we must 4754 * add the broadcast node again. 4755 */ 4756 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4757 aprint_error_dev(sc->sc_dev, 4758 "could not add broadcast node\n"); 4759 return error; 4760 } 4761 return 0; 4762 } 4763 4764 static int 4765 iwn_run(struct iwn_softc *sc) 4766 { 4767 struct iwn_ops *ops = &sc->ops; 4768 struct ieee80211com *ic = &sc->sc_ic; 4769 struct ieee80211_node *ni = ic->ic_bss; 4770 struct iwn_node_info node; 4771 int error; 4772 4773 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4774 /* Link LED blinks while monitoring. */ 4775 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4776 return 0; 4777 } 4778 if ((error = iwn_set_timing(sc, ni)) != 0) { 4779 aprint_error_dev(sc->sc_dev, 4780 "could not set timing\n"); 4781 return error; 4782 } 4783 4784 /* Update adapter configuration. */ 4785 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4786 /* Short preamble and slot time are negotiated when associating. */ 4787 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4788 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4789 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4790 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4791 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4792 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4793 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4794 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4795 if (error != 0) { 4796 aprint_error_dev(sc->sc_dev, 4797 "could not update configuration\n"); 4798 return error; 4799 } 4800 4801 /* Configuration has changed, set TX power accordingly. */ 4802 if ((error = ops->set_txpower(sc, 1)) != 0) { 4803 aprint_error_dev(sc->sc_dev, 4804 "could not set TX power\n"); 4805 return error; 4806 } 4807 4808 /* Fake a join to initialize the TX rate. */ 4809 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4810 iwn_newassoc(ni, 1); 4811 4812 /* Add BSS node. */ 4813 memset(&node, 0, sizeof node); 4814 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4815 node.id = IWN_ID_BSS; 4816 #ifdef notyet 4817 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4818 IWN_AMDPU_DENSITY(5)); /* 2us */ 4819 #endif 4820 DPRINTF(("adding BSS node\n")); 4821 error = ops->add_node(sc, &node, 1); 4822 if (error != 0) { 4823 aprint_error_dev(sc->sc_dev, 4824 "could not add BSS node\n"); 4825 return error; 4826 } 4827 DPRINTF(("setting link quality for node %d\n", node.id)); 4828 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4829 aprint_error_dev(sc->sc_dev, 4830 "could not setup link quality for node %d\n", node.id); 4831 return error; 4832 } 4833 4834 if ((error = iwn_init_sensitivity(sc)) != 0) { 4835 aprint_error_dev(sc->sc_dev, 4836 "could not set sensitivity\n"); 4837 return error; 4838 } 4839 /* Start periodic calibration timer. */ 4840 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4841 sc->calib_cnt = 0; 4842 callout_schedule(&sc->calib_to, hz/2); 4843 4844 /* Link LED always on while associated. */ 4845 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4846 return 0; 4847 } 4848 4849 #ifdef IWN_HWCRYPTO 4850 /* 4851 * We support CCMP hardware encryption/decryption of unicast frames only. 4852 * HW support for TKIP really sucks. We should let TKIP die anyway. 4853 */ 4854 static int 4855 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4856 struct ieee80211_key *k) 4857 { 4858 struct iwn_softc *sc = ic->ic_softc; 4859 struct iwn_ops *ops = &sc->ops; 4860 struct iwn_node *wn = (void *)ni; 4861 struct iwn_node_info node; 4862 uint16_t kflags; 4863 4864 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4865 k->k_cipher != IEEE80211_CIPHER_CCMP) 4866 return ieee80211_set_key(ic, ni, k); 4867 4868 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4869 if (k->k_flags & IEEE80211_KEY_GROUP) 4870 kflags |= IWN_KFLAG_GROUP; 4871 4872 memset(&node, 0, sizeof node); 4873 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4874 sc->broadcast_id : wn->id; 4875 node.control = IWN_NODE_UPDATE; 4876 node.flags = IWN_FLAG_SET_KEY; 4877 node.kflags = htole16(kflags); 4878 node.kid = k->k_id; 4879 memcpy(node.key, k->k_key, k->k_len); 4880 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 4881 return ops->add_node(sc, &node, 1); 4882 } 4883 4884 static void 4885 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4886 struct ieee80211_key *k) 4887 { 4888 struct iwn_softc *sc = ic->ic_softc; 4889 struct iwn_ops *ops = &sc->ops; 4890 struct iwn_node *wn = (void *)ni; 4891 struct iwn_node_info node; 4892 4893 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4894 k->k_cipher != IEEE80211_CIPHER_CCMP) { 4895 /* See comment about other ciphers above. */ 4896 ieee80211_delete_key(ic, ni, k); 4897 return; 4898 } 4899 if (ic->ic_state != IEEE80211_S_RUN) 4900 return; /* Nothing to do. */ 4901 memset(&node, 0, sizeof node); 4902 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4903 sc->broadcast_id : wn->id; 4904 node.control = IWN_NODE_UPDATE; 4905 node.flags = IWN_FLAG_SET_KEY; 4906 node.kflags = htole16(IWN_KFLAG_INVALID); 4907 node.kid = 0xff; 4908 DPRINTF(("delete keys for node %d\n", node.id)); 4909 (void)ops->add_node(sc, &node, 1); 4910 } 4911 #endif 4912 4913 /* XXX Added for NetBSD (copied from rev 1.39). */ 4914 4915 static int 4916 iwn_wme_update(struct ieee80211com *ic) 4917 { 4918 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 4919 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 4920 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4921 const struct wmeParams *wmep; 4922 struct iwn_edca_params cmd; 4923 int ac; 4924 4925 /* don't override default WME values if WME is not actually enabled */ 4926 if (!(ic->ic_flags & IEEE80211_F_WME)) 4927 return 0; 4928 cmd.flags = 0; 4929 for (ac = 0; ac < WME_NUM_AC; ac++) { 4930 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4931 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 4932 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 4933 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 4934 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 4935 4936 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 4937 "txop=%d\n", ac, cmd.ac[ac].aifsn, 4938 cmd.ac[ac].cwmin, 4939 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 4940 } 4941 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4942 #undef IWN_USEC 4943 #undef IWN_EXP2 4944 } 4945 4946 #ifndef IEEE80211_NO_HT 4947 /* 4948 * This function is called by upper layer when an ADDBA request is received 4949 * from another STA and before the ADDBA response is sent. 4950 */ 4951 static int 4952 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 4953 uint8_t tid) 4954 { 4955 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 4956 struct iwn_softc *sc = ic->ic_softc; 4957 struct iwn_ops *ops = &sc->ops; 4958 struct iwn_node *wn = (void *)ni; 4959 struct iwn_node_info node; 4960 4961 memset(&node, 0, sizeof node); 4962 node.id = wn->id; 4963 node.control = IWN_NODE_UPDATE; 4964 node.flags = IWN_FLAG_SET_ADDBA; 4965 node.addba_tid = tid; 4966 node.addba_ssn = htole16(ba->ba_winstart); 4967 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 4968 ba->ba_winstart)); 4969 return ops->add_node(sc, &node, 1); 4970 } 4971 4972 /* 4973 * This function is called by upper layer on teardown of an HT-immediate 4974 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 4975 */ 4976 static void 4977 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 4978 uint8_t tid) 4979 { 4980 struct iwn_softc *sc = ic->ic_softc; 4981 struct iwn_ops *ops = &sc->ops; 4982 struct iwn_node *wn = (void *)ni; 4983 struct iwn_node_info node; 4984 4985 memset(&node, 0, sizeof node); 4986 node.id = wn->id; 4987 node.control = IWN_NODE_UPDATE; 4988 node.flags = IWN_FLAG_SET_DELBA; 4989 node.delba_tid = tid; 4990 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 4991 (void)ops->add_node(sc, &node, 1); 4992 } 4993 4994 /* 4995 * This function is called by upper layer when an ADDBA response is received 4996 * from another STA. 4997 */ 4998 static int 4999 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5000 uint8_t tid) 5001 { 5002 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5003 struct iwn_softc *sc = ic->ic_softc; 5004 struct iwn_ops *ops = &sc->ops; 5005 struct iwn_node *wn = (void *)ni; 5006 struct iwn_node_info node; 5007 int error; 5008 5009 /* Enable TX for the specified RA/TID. */ 5010 wn->disable_tid &= ~(1 << tid); 5011 memset(&node, 0, sizeof node); 5012 node.id = wn->id; 5013 node.control = IWN_NODE_UPDATE; 5014 node.flags = IWN_FLAG_SET_DISABLE_TID; 5015 node.disable_tid = htole16(wn->disable_tid); 5016 error = ops->add_node(sc, &node, 1); 5017 if (error != 0) 5018 return error; 5019 5020 if ((error = iwn_nic_lock(sc)) != 0) 5021 return error; 5022 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5023 iwn_nic_unlock(sc); 5024 return 0; 5025 } 5026 5027 static void 5028 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5029 uint8_t tid) 5030 { 5031 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5032 struct iwn_softc *sc = ic->ic_softc; 5033 struct iwn_ops *ops = &sc->ops; 5034 5035 if (iwn_nic_lock(sc) != 0) 5036 return; 5037 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5038 iwn_nic_unlock(sc); 5039 } 5040 5041 static void 5042 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5043 uint8_t tid, uint16_t ssn) 5044 { 5045 struct iwn_node *wn = (void *)ni; 5046 int qid = 7 + tid; 5047 5048 /* Stop TX scheduler while we're changing its configuration. */ 5049 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5050 IWN4965_TXQ_STATUS_CHGACT); 5051 5052 /* Assign RA/TID translation to the queue. */ 5053 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5054 wn->id << 4 | tid); 5055 5056 /* Enable chain-building mode for the queue. */ 5057 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5058 5059 /* Set starting sequence number from the ADDBA request. */ 5060 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5061 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5062 5063 /* Set scheduler window size. */ 5064 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5065 IWN_SCHED_WINSZ); 5066 /* Set scheduler frame limit. */ 5067 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5068 IWN_SCHED_LIMIT << 16); 5069 5070 /* Enable interrupts for the queue. */ 5071 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5072 5073 /* Mark the queue as active. */ 5074 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5075 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5076 iwn_tid2fifo[tid] << 1); 5077 } 5078 5079 static void 5080 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5081 { 5082 int qid = 7 + tid; 5083 5084 /* Stop TX scheduler while we're changing its configuration. */ 5085 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5086 IWN4965_TXQ_STATUS_CHGACT); 5087 5088 /* Set starting sequence number from the ADDBA request. */ 5089 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5090 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5091 5092 /* Disable interrupts for the queue. */ 5093 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5094 5095 /* Mark the queue as inactive. */ 5096 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5097 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5098 } 5099 5100 static void 5101 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5102 uint8_t tid, uint16_t ssn) 5103 { 5104 struct iwn_node *wn = (void *)ni; 5105 int qid = 10 + tid; 5106 5107 /* Stop TX scheduler while we're changing its configuration. */ 5108 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5109 IWN5000_TXQ_STATUS_CHGACT); 5110 5111 /* Assign RA/TID translation to the queue. */ 5112 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5113 wn->id << 4 | tid); 5114 5115 /* Enable chain-building mode for the queue. */ 5116 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5117 5118 /* Enable aggregation for the queue. */ 5119 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5120 5121 /* Set starting sequence number from the ADDBA request. */ 5122 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5123 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5124 5125 /* Set scheduler window size and frame limit. */ 5126 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5127 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5128 5129 /* Enable interrupts for the queue. */ 5130 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5131 5132 /* Mark the queue as active. */ 5133 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5134 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5135 } 5136 5137 static void 5138 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5139 { 5140 int qid = 10 + tid; 5141 5142 /* Stop TX scheduler while we're changing its configuration. */ 5143 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5144 IWN5000_TXQ_STATUS_CHGACT); 5145 5146 /* Disable aggregation for the queue. */ 5147 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5148 5149 /* Set starting sequence number from the ADDBA request. */ 5150 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5151 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5152 5153 /* Disable interrupts for the queue. */ 5154 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5155 5156 /* Mark the queue as inactive. */ 5157 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5158 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5159 } 5160 #endif /* !IEEE80211_NO_HT */ 5161 5162 /* 5163 * Query calibration tables from the initialization firmware. We do this 5164 * only once at first boot. Called from a process context. 5165 */ 5166 static int 5167 iwn5000_query_calibration(struct iwn_softc *sc) 5168 { 5169 struct iwn5000_calib_config cmd; 5170 int error; 5171 5172 memset(&cmd, 0, sizeof cmd); 5173 cmd.ucode.once.enable = 0xffffffff; 5174 cmd.ucode.once.start = 0xffffffff; 5175 cmd.ucode.once.send = 0xffffffff; 5176 cmd.ucode.flags = 0xffffffff; 5177 DPRINTF(("sending calibration query\n")); 5178 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5179 if (error != 0) 5180 return error; 5181 5182 /* Wait at most two seconds for calibration to complete. */ 5183 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5184 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 5185 return error; 5186 } 5187 5188 /* 5189 * Send calibration results to the runtime firmware. These results were 5190 * obtained on first boot from the initialization firmware. 5191 */ 5192 static int 5193 iwn5000_send_calibration(struct iwn_softc *sc) 5194 { 5195 int idx, error; 5196 5197 for (idx = 0; idx < 5; idx++) { 5198 if (sc->calibcmd[idx].buf == NULL) 5199 continue; /* No results available. */ 5200 DPRINTF(("send calibration result idx=%d len=%d\n", 5201 idx, sc->calibcmd[idx].len)); 5202 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5203 sc->calibcmd[idx].len, 0); 5204 if (error != 0) { 5205 aprint_error_dev(sc->sc_dev, 5206 "could not send calibration result\n"); 5207 return error; 5208 } 5209 } 5210 return 0; 5211 } 5212 5213 static int 5214 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5215 { 5216 struct iwn5000_wimax_coex wimax; 5217 5218 #ifdef notyet 5219 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5220 /* Enable WiMAX coexistence for combo adapters. */ 5221 wimax.flags = 5222 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5223 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5224 IWN_WIMAX_COEX_STA_TABLE_VALID | 5225 IWN_WIMAX_COEX_ENABLE; 5226 memcpy(wimax.events, iwn6050_wimax_events, 5227 sizeof iwn6050_wimax_events); 5228 } else 5229 #endif 5230 { 5231 /* Disable WiMAX coexistence. */ 5232 wimax.flags = 0; 5233 memset(wimax.events, 0, sizeof wimax.events); 5234 } 5235 DPRINTF(("Configuring WiMAX coexistence\n")); 5236 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5237 } 5238 5239 static int 5240 iwn6000_temp_offset_calib(struct iwn_softc *sc) 5241 { 5242 struct iwn6000_phy_calib_temp_offset cmd; 5243 5244 memset(&cmd, 0, sizeof cmd); 5245 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 5246 cmd.ngroups = 1; 5247 cmd.isvalid = 1; 5248 if (sc->eeprom_temp != 0) 5249 cmd.offset = htole16(sc->eeprom_temp); 5250 else 5251 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5252 DPRINTF(("setting radio sensor offset to %d\n", le16toh(cmd.offset))); 5253 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5254 } 5255 5256 static int 5257 iwn2000_temp_offset_calib(struct iwn_softc *sc) 5258 { 5259 struct iwn2000_phy_calib_temp_offset cmd; 5260 5261 memset(&cmd, 0, sizeof cmd); 5262 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 5263 cmd.ngroups = 1; 5264 cmd.isvalid = 1; 5265 if (sc->eeprom_rawtemp != 0) { 5266 cmd.offset_low = htole16(sc->eeprom_rawtemp); 5267 cmd.offset_high = htole16(sc->eeprom_temp); 5268 } else { 5269 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 5270 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 5271 } 5272 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 5273 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 5274 le16toh(cmd.offset_low), le16toh(cmd.offset_high), 5275 le16toh(cmd.burnt_voltage_ref))); 5276 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5277 } 5278 5279 /* 5280 * This function is called after the runtime firmware notifies us of its 5281 * readiness (called in a process context). 5282 */ 5283 static int 5284 iwn4965_post_alive(struct iwn_softc *sc) 5285 { 5286 int error, qid; 5287 5288 if ((error = iwn_nic_lock(sc)) != 0) 5289 return error; 5290 5291 /* Clear TX scheduler state in SRAM. */ 5292 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5293 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5294 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5295 5296 /* Set physical address of TX scheduler rings (1KB aligned). */ 5297 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5298 5299 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5300 5301 /* Disable chain mode for all our 16 queues. */ 5302 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5303 5304 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5305 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5306 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5307 5308 /* Set scheduler window size. */ 5309 iwn_mem_write(sc, sc->sched_base + 5310 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5311 /* Set scheduler frame limit. */ 5312 iwn_mem_write(sc, sc->sched_base + 5313 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5314 IWN_SCHED_LIMIT << 16); 5315 } 5316 5317 /* Enable interrupts for all our 16 queues. */ 5318 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5319 /* Identify TX FIFO rings (0-7). */ 5320 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5321 5322 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5323 for (qid = 0; qid < 7; qid++) { 5324 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5325 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5326 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5327 } 5328 iwn_nic_unlock(sc); 5329 return 0; 5330 } 5331 5332 /* 5333 * This function is called after the initialization or runtime firmware 5334 * notifies us of its readiness (called in a process context). 5335 */ 5336 static int 5337 iwn5000_post_alive(struct iwn_softc *sc) 5338 { 5339 int error, qid; 5340 5341 /* Switch to using ICT interrupt mode. */ 5342 iwn5000_ict_reset(sc); 5343 5344 if ((error = iwn_nic_lock(sc)) != 0) 5345 return error; 5346 5347 /* Clear TX scheduler state in SRAM. */ 5348 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5349 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5350 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5351 5352 /* Set physical address of TX scheduler rings (1KB aligned). */ 5353 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5354 5355 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5356 5357 /* Enable chain mode for all queues, except command queue. */ 5358 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5359 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5360 5361 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5362 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5363 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5364 5365 iwn_mem_write(sc, sc->sched_base + 5366 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5367 /* Set scheduler window size and frame limit. */ 5368 iwn_mem_write(sc, sc->sched_base + 5369 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5370 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5371 } 5372 5373 /* Enable interrupts for all our 20 queues. */ 5374 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5375 /* Identify TX FIFO rings (0-7). */ 5376 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5377 5378 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5379 for (qid = 0; qid < 7; qid++) { 5380 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5381 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5382 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5383 } 5384 iwn_nic_unlock(sc); 5385 5386 /* Configure WiMAX coexistence for combo adapters. */ 5387 error = iwn5000_send_wimax_coex(sc); 5388 if (error != 0) { 5389 aprint_error_dev(sc->sc_dev, 5390 "could not configure WiMAX coexistence\n"); 5391 return error; 5392 } 5393 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5394 struct iwn5000_phy_calib_crystal cmd; 5395 5396 /* Perform crystal calibration. */ 5397 memset(&cmd, 0, sizeof cmd); 5398 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5399 cmd.ngroups = 1; 5400 cmd.isvalid = 1; 5401 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5402 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5403 DPRINTF(("sending crystal calibration %d, %d\n", 5404 cmd.cap_pin[0], cmd.cap_pin[1])); 5405 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5406 if (error != 0) { 5407 aprint_error_dev(sc->sc_dev, 5408 "crystal calibration failed\n"); 5409 return error; 5410 } 5411 } 5412 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5413 /* Query calibration from the initialization firmware. */ 5414 if ((error = iwn5000_query_calibration(sc)) != 0) { 5415 aprint_error_dev(sc->sc_dev, 5416 "could not query calibration\n"); 5417 return error; 5418 } 5419 /* 5420 * We have the calibration results now, reboot with the 5421 * runtime firmware (call ourselves recursively!) 5422 */ 5423 iwn_hw_stop(sc); 5424 error = iwn_hw_init(sc); 5425 } else { 5426 /* Send calibration results to runtime firmware. */ 5427 error = iwn5000_send_calibration(sc); 5428 } 5429 return error; 5430 } 5431 5432 /* 5433 * The firmware boot code is small and is intended to be copied directly into 5434 * the NIC internal memory (no DMA transfer). 5435 */ 5436 static int 5437 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5438 { 5439 int error, ntries; 5440 5441 size /= sizeof (uint32_t); 5442 5443 if ((error = iwn_nic_lock(sc)) != 0) 5444 return error; 5445 5446 /* Copy microcode image into NIC memory. */ 5447 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5448 (const uint32_t *)ucode, size); 5449 5450 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5451 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5452 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5453 5454 /* Start boot load now. */ 5455 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5456 5457 /* Wait for transfer to complete. */ 5458 for (ntries = 0; ntries < 1000; ntries++) { 5459 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5460 IWN_BSM_WR_CTRL_START)) 5461 break; 5462 DELAY(10); 5463 } 5464 if (ntries == 1000) { 5465 aprint_error_dev(sc->sc_dev, 5466 "could not load boot firmware\n"); 5467 iwn_nic_unlock(sc); 5468 return ETIMEDOUT; 5469 } 5470 5471 /* Enable boot after power up. */ 5472 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5473 5474 iwn_nic_unlock(sc); 5475 return 0; 5476 } 5477 5478 static int 5479 iwn4965_load_firmware(struct iwn_softc *sc) 5480 { 5481 struct iwn_fw_info *fw = &sc->fw; 5482 struct iwn_dma_info *dma = &sc->fw_dma; 5483 int error; 5484 5485 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5486 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5487 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5488 BUS_DMASYNC_PREWRITE); 5489 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5490 fw->init.text, fw->init.textsz); 5491 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5492 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5493 5494 /* Tell adapter where to find initialization sections. */ 5495 if ((error = iwn_nic_lock(sc)) != 0) 5496 return error; 5497 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5498 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5499 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5500 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5501 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5502 iwn_nic_unlock(sc); 5503 5504 /* Load firmware boot code. */ 5505 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5506 if (error != 0) { 5507 aprint_error_dev(sc->sc_dev, 5508 "could not load boot firmware\n"); 5509 return error; 5510 } 5511 /* Now press "execute". */ 5512 IWN_WRITE(sc, IWN_RESET, 0); 5513 5514 /* Wait at most one second for first alive notification. */ 5515 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5516 aprint_error_dev(sc->sc_dev, 5517 "timeout waiting for adapter to initialize\n"); 5518 return error; 5519 } 5520 5521 /* Retrieve current temperature for initial TX power calibration. */ 5522 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5523 sc->temp = iwn4965_get_temperature(sc); 5524 5525 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5526 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5527 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5528 BUS_DMASYNC_PREWRITE); 5529 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5530 fw->main.text, fw->main.textsz); 5531 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5532 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5533 5534 /* Tell adapter where to find runtime sections. */ 5535 if ((error = iwn_nic_lock(sc)) != 0) 5536 return error; 5537 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5538 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5539 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5540 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5541 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5542 IWN_FW_UPDATED | fw->main.textsz); 5543 iwn_nic_unlock(sc); 5544 5545 return 0; 5546 } 5547 5548 static int 5549 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5550 const uint8_t *section, int size) 5551 { 5552 struct iwn_dma_info *dma = &sc->fw_dma; 5553 int error; 5554 5555 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5556 memcpy(dma->vaddr, section, size); 5557 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5558 5559 if ((error = iwn_nic_lock(sc)) != 0) 5560 return error; 5561 5562 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5563 IWN_FH_TX_CONFIG_DMA_PAUSE); 5564 5565 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5566 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5567 IWN_LOADDR(dma->paddr)); 5568 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5569 IWN_HIADDR(dma->paddr) << 28 | size); 5570 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5571 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5572 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5573 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5574 5575 /* Kick Flow Handler to start DMA transfer. */ 5576 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5577 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5578 5579 iwn_nic_unlock(sc); 5580 5581 /* Wait at most five seconds for FH DMA transfer to complete. */ 5582 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5583 } 5584 5585 static int 5586 iwn5000_load_firmware(struct iwn_softc *sc) 5587 { 5588 struct iwn_fw_part *fw; 5589 int error; 5590 5591 /* Load the initialization firmware on first boot only. */ 5592 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5593 &sc->fw.main : &sc->fw.init; 5594 5595 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5596 fw->text, fw->textsz); 5597 if (error != 0) { 5598 aprint_error_dev(sc->sc_dev, 5599 "could not load firmware %s section\n", ".text"); 5600 return error; 5601 } 5602 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5603 fw->data, fw->datasz); 5604 if (error != 0) { 5605 aprint_error_dev(sc->sc_dev, 5606 "could not load firmware %s section\n", ".data"); 5607 return error; 5608 } 5609 5610 /* Now press "execute". */ 5611 IWN_WRITE(sc, IWN_RESET, 0); 5612 return 0; 5613 } 5614 5615 /* 5616 * Extract text and data sections from a legacy firmware image. 5617 */ 5618 static int 5619 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5620 { 5621 const uint32_t *ptr; 5622 size_t hdrlen = 24; 5623 uint32_t rev; 5624 5625 ptr = (const uint32_t *)fw->data; 5626 rev = le32toh(*ptr++); 5627 5628 /* Check firmware API version. */ 5629 if (IWN_FW_API(rev) <= 1) { 5630 aprint_error_dev(sc->sc_dev, 5631 "bad firmware, need API version >=2\n"); 5632 return EINVAL; 5633 } 5634 if (IWN_FW_API(rev) >= 3) { 5635 /* Skip build number (version 2 header). */ 5636 hdrlen += 4; 5637 ptr++; 5638 } 5639 if (fw->size < hdrlen) { 5640 aprint_error_dev(sc->sc_dev, 5641 "firmware too short: %zd bytes\n", fw->size); 5642 return EINVAL; 5643 } 5644 fw->main.textsz = le32toh(*ptr++); 5645 fw->main.datasz = le32toh(*ptr++); 5646 fw->init.textsz = le32toh(*ptr++); 5647 fw->init.datasz = le32toh(*ptr++); 5648 fw->boot.textsz = le32toh(*ptr++); 5649 5650 /* Check that all firmware sections fit. */ 5651 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5652 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5653 aprint_error_dev(sc->sc_dev, 5654 "firmware too short: %zd bytes\n", fw->size); 5655 return EINVAL; 5656 } 5657 5658 /* Get pointers to firmware sections. */ 5659 fw->main.text = (const uint8_t *)ptr; 5660 fw->main.data = fw->main.text + fw->main.textsz; 5661 fw->init.text = fw->main.data + fw->main.datasz; 5662 fw->init.data = fw->init.text + fw->init.textsz; 5663 fw->boot.text = fw->init.data + fw->init.datasz; 5664 return 0; 5665 } 5666 5667 /* 5668 * Extract text and data sections from a TLV firmware image. 5669 */ 5670 static int 5671 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5672 uint16_t alt) 5673 { 5674 const struct iwn_fw_tlv_hdr *hdr; 5675 const struct iwn_fw_tlv *tlv; 5676 const uint8_t *ptr, *end; 5677 uint64_t altmask; 5678 uint32_t len; 5679 5680 if (fw->size < sizeof (*hdr)) { 5681 aprint_error_dev(sc->sc_dev, 5682 "firmware too short: %zd bytes\n", fw->size); 5683 return EINVAL; 5684 } 5685 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5686 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5687 aprint_error_dev(sc->sc_dev, 5688 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5689 return EINVAL; 5690 } 5691 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5692 le32toh(hdr->build))); 5693 5694 /* 5695 * Select the closest supported alternative that is less than 5696 * or equal to the specified one. 5697 */ 5698 altmask = le64toh(hdr->altmask); 5699 while (alt > 0 && !(altmask & (1ULL << alt))) 5700 alt--; /* Downgrade. */ 5701 DPRINTF(("using alternative %d\n", alt)); 5702 5703 ptr = (const uint8_t *)(hdr + 1); 5704 end = (const uint8_t *)(fw->data + fw->size); 5705 5706 /* Parse type-length-value fields. */ 5707 while (ptr + sizeof (*tlv) <= end) { 5708 tlv = (const struct iwn_fw_tlv *)ptr; 5709 len = le32toh(tlv->len); 5710 5711 ptr += sizeof (*tlv); 5712 if (ptr + len > end) { 5713 aprint_error_dev(sc->sc_dev, 5714 "firmware too short: %zd bytes\n", fw->size); 5715 return EINVAL; 5716 } 5717 /* Skip other alternatives. */ 5718 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5719 goto next; 5720 5721 switch (le16toh(tlv->type)) { 5722 case IWN_FW_TLV_MAIN_TEXT: 5723 fw->main.text = ptr; 5724 fw->main.textsz = len; 5725 break; 5726 case IWN_FW_TLV_MAIN_DATA: 5727 fw->main.data = ptr; 5728 fw->main.datasz = len; 5729 break; 5730 case IWN_FW_TLV_INIT_TEXT: 5731 fw->init.text = ptr; 5732 fw->init.textsz = len; 5733 break; 5734 case IWN_FW_TLV_INIT_DATA: 5735 fw->init.data = ptr; 5736 fw->init.datasz = len; 5737 break; 5738 case IWN_FW_TLV_BOOT_TEXT: 5739 fw->boot.text = ptr; 5740 fw->boot.textsz = len; 5741 break; 5742 case IWN_FW_TLV_ENH_SENS: 5743 if (len != 0) { 5744 aprint_error_dev(sc->sc_dev, 5745 "TLV type %d has invalid size %u\n", 5746 le16toh(tlv->type), len); 5747 goto next; 5748 } 5749 sc->sc_flags |= IWN_FLAG_ENH_SENS; 5750 break; 5751 case IWN_FW_TLV_PHY_CALIB: 5752 if (len != sizeof(uint32_t)) { 5753 aprint_error_dev(sc->sc_dev, 5754 "TLV type %d has invalid size %u\n", 5755 le16toh(tlv->type), len); 5756 goto next; 5757 } 5758 if (le32toh(*ptr) <= IWN5000_PHY_CALIB_MAX) { 5759 sc->reset_noise_gain = le32toh(*ptr); 5760 sc->noise_gain = le32toh(*ptr) + 1; 5761 } 5762 break; 5763 case IWN_FW_TLV_FLAGS: 5764 if (len < sizeof(uint32_t)) 5765 break; 5766 if (len % sizeof(uint32_t)) 5767 break; 5768 sc->tlv_feature_flags = le32toh(*ptr); 5769 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 5770 break; 5771 default: 5772 DPRINTF(("TLV type %d not handled\n", 5773 le16toh(tlv->type))); 5774 break; 5775 } 5776 next: /* TLV fields are 32-bit aligned. */ 5777 ptr += (len + 3) & ~3; 5778 } 5779 return 0; 5780 } 5781 5782 static int 5783 iwn_read_firmware(struct iwn_softc *sc) 5784 { 5785 struct iwn_fw_info *fw = &sc->fw; 5786 firmware_handle_t fwh; 5787 int error; 5788 5789 /* 5790 * Some PHY calibration commands are firmware-dependent; these 5791 * are the default values that will be overridden if 5792 * necessary. 5793 */ 5794 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 5795 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 5796 5797 /* Initialize for error returns */ 5798 fw->data = NULL; 5799 fw->size = 0; 5800 5801 /* Open firmware image. */ 5802 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5803 aprint_error_dev(sc->sc_dev, 5804 "could not get firmware handle %s\n", sc->fwname); 5805 return error; 5806 } 5807 fw->size = firmware_get_size(fwh); 5808 if (fw->size < sizeof (uint32_t)) { 5809 aprint_error_dev(sc->sc_dev, 5810 "firmware too short: %zd bytes\n", fw->size); 5811 firmware_close(fwh); 5812 return EINVAL; 5813 } 5814 5815 /* Read the firmware. */ 5816 fw->data = firmware_malloc(fw->size); 5817 if (fw->data == NULL) { 5818 aprint_error_dev(sc->sc_dev, 5819 "not enough memory to stock firmware %s\n", sc->fwname); 5820 firmware_close(fwh); 5821 return ENOMEM; 5822 } 5823 error = firmware_read(fwh, 0, fw->data, fw->size); 5824 firmware_close(fwh); 5825 if (error != 0) { 5826 aprint_error_dev(sc->sc_dev, 5827 "could not read firmware %s\n", sc->fwname); 5828 goto out; 5829 } 5830 5831 /* Retrieve text and data sections. */ 5832 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5833 error = iwn_read_firmware_leg(sc, fw); 5834 else 5835 error = iwn_read_firmware_tlv(sc, fw, 1); 5836 if (error != 0) { 5837 aprint_error_dev(sc->sc_dev, 5838 "could not read firmware sections\n"); 5839 goto out; 5840 } 5841 5842 /* Make sure text and data sections fit in hardware memory. */ 5843 if (fw->main.textsz > sc->fw_text_maxsz || 5844 fw->main.datasz > sc->fw_data_maxsz || 5845 fw->init.textsz > sc->fw_text_maxsz || 5846 fw->init.datasz > sc->fw_data_maxsz || 5847 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5848 (fw->boot.textsz & 3) != 0) { 5849 aprint_error_dev(sc->sc_dev, 5850 "firmware sections too large\n"); 5851 goto out; 5852 } 5853 5854 /* We can proceed with loading the firmware. */ 5855 return 0; 5856 out: 5857 firmware_free(fw->data, fw->size); 5858 fw->data = NULL; 5859 fw->size = 0; 5860 return error ? error : EINVAL; 5861 } 5862 5863 static int 5864 iwn_clock_wait(struct iwn_softc *sc) 5865 { 5866 int ntries; 5867 5868 /* Set "initialization complete" bit. */ 5869 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5870 5871 /* Wait for clock stabilization. */ 5872 for (ntries = 0; ntries < 2500; ntries++) { 5873 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5874 return 0; 5875 DELAY(10); 5876 } 5877 aprint_error_dev(sc->sc_dev, 5878 "timeout waiting for clock stabilization\n"); 5879 return ETIMEDOUT; 5880 } 5881 5882 static int 5883 iwn_apm_init(struct iwn_softc *sc) 5884 { 5885 pcireg_t reg; 5886 int error; 5887 5888 /* Disable L0s exit timer (NMI bug workaround). */ 5889 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 5890 /* Don't wait for ICH L0s (ICH bug workaround). */ 5891 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 5892 5893 /* Set FH wait threshold to max (HW bug under stress workaround). */ 5894 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 5895 5896 /* Enable HAP INTA to move adapter from L1a to L0s. */ 5897 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 5898 5899 /* Retrieve PCIe Active State Power Management (ASPM). */ 5900 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 5901 sc->sc_cap_off + PCIE_LCSR); 5902 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 5903 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 5904 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5905 else 5906 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 5907 5908 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 5909 sc->hw_type <= IWN_HW_REV_TYPE_1000) 5910 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 5911 5912 /* Wait for clock stabilization before accessing prph. */ 5913 if ((error = iwn_clock_wait(sc)) != 0) 5914 return error; 5915 5916 if ((error = iwn_nic_lock(sc)) != 0) 5917 return error; 5918 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 5919 /* Enable DMA and BSM (Bootstrap State Machine). */ 5920 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5921 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 5922 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 5923 } else { 5924 /* Enable DMA. */ 5925 iwn_prph_write(sc, IWN_APMG_CLK_EN, 5926 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 5927 } 5928 DELAY(20); 5929 /* Disable L1-Active. */ 5930 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 5931 iwn_nic_unlock(sc); 5932 5933 return 0; 5934 } 5935 5936 static void 5937 iwn_apm_stop_master(struct iwn_softc *sc) 5938 { 5939 int ntries; 5940 5941 /* Stop busmaster DMA activity. */ 5942 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 5943 for (ntries = 0; ntries < 100; ntries++) { 5944 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 5945 return; 5946 DELAY(10); 5947 } 5948 aprint_error_dev(sc->sc_dev, 5949 "timeout waiting for master\n"); 5950 } 5951 5952 static void 5953 iwn_apm_stop(struct iwn_softc *sc) 5954 { 5955 iwn_apm_stop_master(sc); 5956 5957 /* Reset the entire device. */ 5958 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 5959 DELAY(10); 5960 /* Clear "initialization complete" bit. */ 5961 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5962 } 5963 5964 static int 5965 iwn4965_nic_config(struct iwn_softc *sc) 5966 { 5967 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 5968 /* 5969 * I don't believe this to be correct but this is what the 5970 * vendor driver is doing. Probably the bits should not be 5971 * shifted in IWN_RFCFG_*. 5972 */ 5973 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5974 IWN_RFCFG_TYPE(sc->rfcfg) | 5975 IWN_RFCFG_STEP(sc->rfcfg) | 5976 IWN_RFCFG_DASH(sc->rfcfg)); 5977 } 5978 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5979 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5980 return 0; 5981 } 5982 5983 static int 5984 iwn5000_nic_config(struct iwn_softc *sc) 5985 { 5986 uint32_t tmp; 5987 int error; 5988 5989 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 5990 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5991 IWN_RFCFG_TYPE(sc->rfcfg) | 5992 IWN_RFCFG_STEP(sc->rfcfg) | 5993 IWN_RFCFG_DASH(sc->rfcfg)); 5994 } 5995 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 5996 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 5997 5998 if ((error = iwn_nic_lock(sc)) != 0) 5999 return error; 6000 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6001 6002 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6003 /* 6004 * Select first Switching Voltage Regulator (1.32V) to 6005 * solve a stability issue related to noisy DC2DC line 6006 * in the silicon of 1000 Series. 6007 */ 6008 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6009 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6010 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6011 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6012 } 6013 iwn_nic_unlock(sc); 6014 6015 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6016 /* Use internal power amplifier only. */ 6017 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6018 } 6019 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6020 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6021 /* Indicate that ROM calibration version is >=6. */ 6022 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6023 } 6024 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6025 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6026 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6027 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6028 sc->hw_type == IWN_HW_REV_TYPE_135 || 6029 sc->hw_type == IWN_HW_REV_TYPE_105) 6030 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6031 return 0; 6032 } 6033 6034 /* 6035 * Take NIC ownership over Intel Active Management Technology (AMT). 6036 */ 6037 static int 6038 iwn_hw_prepare(struct iwn_softc *sc) 6039 { 6040 int ntries; 6041 6042 /* Check if hardware is ready. */ 6043 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6044 for (ntries = 0; ntries < 5; ntries++) { 6045 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6046 IWN_HW_IF_CONFIG_NIC_READY) 6047 return 0; 6048 DELAY(10); 6049 } 6050 6051 /* Hardware not ready, force into ready state. */ 6052 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6053 for (ntries = 0; ntries < 15000; ntries++) { 6054 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6055 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6056 break; 6057 DELAY(10); 6058 } 6059 if (ntries == 15000) 6060 return ETIMEDOUT; 6061 6062 /* Hardware should be ready now. */ 6063 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6064 for (ntries = 0; ntries < 5; ntries++) { 6065 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6066 IWN_HW_IF_CONFIG_NIC_READY) 6067 return 0; 6068 DELAY(10); 6069 } 6070 return ETIMEDOUT; 6071 } 6072 6073 static int 6074 iwn_hw_init(struct iwn_softc *sc) 6075 { 6076 struct iwn_ops *ops = &sc->ops; 6077 int error, chnl, qid; 6078 6079 /* Clear pending interrupts. */ 6080 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6081 6082 if ((error = iwn_apm_init(sc)) != 0) { 6083 aprint_error_dev(sc->sc_dev, 6084 "could not power ON adapter\n"); 6085 return error; 6086 } 6087 6088 /* Select VMAIN power source. */ 6089 if ((error = iwn_nic_lock(sc)) != 0) 6090 return error; 6091 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6092 iwn_nic_unlock(sc); 6093 6094 /* Perform adapter-specific initialization. */ 6095 if ((error = ops->nic_config(sc)) != 0) 6096 return error; 6097 6098 /* Initialize RX ring. */ 6099 if ((error = iwn_nic_lock(sc)) != 0) 6100 return error; 6101 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6102 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6103 /* Set physical address of RX ring (256-byte aligned). */ 6104 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6105 /* Set physical address of RX status (16-byte aligned). */ 6106 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6107 /* Enable RX. */ 6108 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6109 IWN_FH_RX_CONFIG_ENA | 6110 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6111 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6112 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6113 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6114 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6115 iwn_nic_unlock(sc); 6116 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6117 6118 if ((error = iwn_nic_lock(sc)) != 0) 6119 return error; 6120 6121 /* Initialize TX scheduler. */ 6122 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6123 6124 /* Set physical address of "keep warm" page (16-byte aligned). */ 6125 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6126 6127 /* Initialize TX rings. */ 6128 for (qid = 0; qid < sc->ntxqs; qid++) { 6129 struct iwn_tx_ring *txq = &sc->txq[qid]; 6130 6131 /* Set physical address of TX ring (256-byte aligned). */ 6132 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6133 txq->desc_dma.paddr >> 8); 6134 } 6135 iwn_nic_unlock(sc); 6136 6137 /* Enable DMA channels. */ 6138 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6139 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6140 IWN_FH_TX_CONFIG_DMA_ENA | 6141 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6142 } 6143 6144 /* Clear "radio off" and "commands blocked" bits. */ 6145 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6146 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6147 6148 /* Clear pending interrupts. */ 6149 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6150 /* Enable interrupt coalescing. */ 6151 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6152 /* Enable interrupts. */ 6153 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6154 6155 /* _Really_ make sure "radio off" bit is cleared! */ 6156 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6157 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6158 6159 /* Enable shadow registers. */ 6160 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6161 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6162 6163 if ((error = ops->load_firmware(sc)) != 0) { 6164 aprint_error_dev(sc->sc_dev, 6165 "could not load firmware\n"); 6166 return error; 6167 } 6168 /* Wait at most one second for firmware alive notification. */ 6169 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 6170 aprint_error_dev(sc->sc_dev, 6171 "timeout waiting for adapter to initialize\n"); 6172 return error; 6173 } 6174 /* Do post-firmware initialization. */ 6175 return ops->post_alive(sc); 6176 } 6177 6178 static void 6179 iwn_hw_stop(struct iwn_softc *sc) 6180 { 6181 int chnl, qid, ntries; 6182 6183 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6184 6185 /* Disable interrupts. */ 6186 IWN_WRITE(sc, IWN_INT_MASK, 0); 6187 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6188 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6189 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6190 6191 /* Make sure we no longer hold the NIC lock. */ 6192 iwn_nic_unlock(sc); 6193 6194 /* Stop TX scheduler. */ 6195 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6196 6197 /* Stop all DMA channels. */ 6198 if (iwn_nic_lock(sc) == 0) { 6199 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6200 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6201 for (ntries = 0; ntries < 200; ntries++) { 6202 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6203 IWN_FH_TX_STATUS_IDLE(chnl)) 6204 break; 6205 DELAY(10); 6206 } 6207 } 6208 iwn_nic_unlock(sc); 6209 } 6210 6211 /* Stop RX ring. */ 6212 iwn_reset_rx_ring(sc, &sc->rxq); 6213 6214 /* Reset all TX rings. */ 6215 for (qid = 0; qid < sc->ntxqs; qid++) 6216 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6217 6218 if (iwn_nic_lock(sc) == 0) { 6219 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6220 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6221 iwn_nic_unlock(sc); 6222 } 6223 DELAY(5); 6224 /* Power OFF adapter. */ 6225 iwn_apm_stop(sc); 6226 } 6227 6228 static int 6229 iwn_init(struct ifnet *ifp) 6230 { 6231 struct iwn_softc *sc = ifp->if_softc; 6232 struct ieee80211com *ic = &sc->sc_ic; 6233 int error; 6234 6235 mutex_enter(&sc->sc_mtx); 6236 if (sc->sc_flags & IWN_FLAG_HW_INITED) 6237 goto out; 6238 if ((error = iwn_hw_prepare(sc)) != 0) { 6239 aprint_error_dev(sc->sc_dev, 6240 "hardware not ready\n"); 6241 goto fail; 6242 } 6243 6244 /* Check that the radio is not disabled by hardware switch. */ 6245 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6246 aprint_error_dev(sc->sc_dev, 6247 "radio is disabled by hardware switch\n"); 6248 error = EPERM; /* :-) */ 6249 goto fail; 6250 } 6251 6252 /* Read firmware images from the filesystem. */ 6253 if ((error = iwn_read_firmware(sc)) != 0) { 6254 aprint_error_dev(sc->sc_dev, 6255 "could not read firmware\n"); 6256 goto fail; 6257 } 6258 6259 /* Initialize interrupt mask to default value. */ 6260 sc->int_mask = IWN_INT_MASK_DEF; 6261 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6262 6263 /* Initialize hardware and upload firmware. */ 6264 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 6265 error = iwn_hw_init(sc); 6266 firmware_free(sc->fw.data, sc->fw.size); 6267 sc->fw.data = NULL; 6268 sc->fw.size = 0; 6269 if (error != 0) { 6270 aprint_error_dev(sc->sc_dev, 6271 "could not initialize hardware\n"); 6272 goto fail; 6273 } 6274 6275 /* Configure adapter now that it is ready. */ 6276 if ((error = iwn_config(sc)) != 0) { 6277 aprint_error_dev(sc->sc_dev, 6278 "could not configure device\n"); 6279 goto fail; 6280 } 6281 6282 ifp->if_flags &= ~IFF_OACTIVE; 6283 ifp->if_flags |= IFF_RUNNING; 6284 6285 if (ic->ic_opmode != IEEE80211_M_MONITOR) 6286 ieee80211_begin_scan(ic, 0); 6287 else 6288 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 6289 6290 sc->sc_flags |= IWN_FLAG_HW_INITED; 6291 out: 6292 mutex_exit(&sc->sc_mtx); 6293 return 0; 6294 6295 fail: mutex_exit(&sc->sc_mtx); 6296 iwn_stop(ifp, 1); 6297 return error; 6298 } 6299 6300 static void 6301 iwn_stop(struct ifnet *ifp, int disable) 6302 { 6303 struct iwn_softc *sc = ifp->if_softc; 6304 struct ieee80211com *ic = &sc->sc_ic; 6305 6306 if (!disable) 6307 mutex_enter(&sc->sc_mtx); 6308 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 6309 ifp->if_timer = sc->sc_tx_timer = 0; 6310 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6311 6312 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6313 6314 /* Power OFF hardware. */ 6315 iwn_hw_stop(sc); 6316 6317 if (!disable) 6318 mutex_exit(&sc->sc_mtx); 6319 } 6320 6321 /* 6322 * XXX MCLGETI alternative 6323 * 6324 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 6325 * as long as there are available free buffers then it uses MEXTMALLOC., 6326 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 6327 * The MCLGET4K code is used for testing an alternative mbuf cache. 6328 */ 6329 6330 static struct mbuf * 6331 MCLGETIalt(struct iwn_softc *sc, int how, 6332 struct ifnet *ifp __unused, u_int size) 6333 { 6334 struct mbuf *m; 6335 #ifdef IWN_USE_RBUF 6336 struct iwn_rbuf *rbuf; 6337 #endif 6338 6339 MGETHDR(m, how, MT_DATA); 6340 if (m == NULL) 6341 return NULL; 6342 6343 #ifdef IWN_USE_RBUF 6344 if (sc->rxq.nb_free_entries > 0 && 6345 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 6346 /* Attach buffer to mbuf header. */ 6347 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 6348 m->m_flags |= M_EXT_RW; 6349 } 6350 else { 6351 MEXTMALLOC(m, size, how); 6352 if ((m->m_flags & M_EXT) == 0) { 6353 m_freem(m); 6354 return NULL; 6355 } 6356 } 6357 6358 #else 6359 #ifdef MCLGET4K 6360 if (size == 4096) 6361 MCLGET4K(m, how); 6362 else 6363 panic("size must be 4k"); 6364 #else 6365 MEXTMALLOC(m, size, how); 6366 #endif 6367 if ((m->m_flags & M_EXT) == 0) { 6368 m_freem(m); 6369 return NULL; 6370 } 6371 #endif 6372 6373 return m; 6374 } 6375 6376 #ifdef IWN_USE_RBUF 6377 static struct iwn_rbuf * 6378 iwn_alloc_rbuf(struct iwn_softc *sc) 6379 { 6380 struct iwn_rbuf *rbuf; 6381 mutex_enter(&sc->rxq.freelist_mtx); 6382 6383 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6384 if (rbuf != NULL) { 6385 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6386 sc->rxq.nb_free_entries --; 6387 } 6388 mutex_exit(&sc->rxq.freelist_mtx); 6389 return rbuf; 6390 } 6391 6392 /* 6393 * This is called automatically by the network stack when the mbuf to which 6394 * our RX buffer is attached is freed. 6395 */ 6396 static void 6397 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6398 { 6399 struct iwn_rbuf *rbuf = arg; 6400 struct iwn_softc *sc = rbuf->sc; 6401 6402 /* Put the RX buffer back in the free list. */ 6403 mutex_enter(&sc->rxq.freelist_mtx); 6404 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6405 mutex_exit(&sc->rxq.freelist_mtx); 6406 6407 sc->rxq.nb_free_entries ++; 6408 if (__predict_true(m != NULL)) 6409 pool_cache_put(mb_cache, m); 6410 } 6411 6412 static int 6413 iwn_alloc_rpool(struct iwn_softc *sc) 6414 { 6415 struct iwn_rx_ring *ring = &sc->rxq; 6416 struct iwn_rbuf *rbuf; 6417 int i, error; 6418 6419 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6420 6421 /* Allocate a big chunk of DMA'able memory... */ 6422 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6423 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6424 if (error != 0) { 6425 aprint_error_dev(sc->sc_dev, 6426 "could not allocate RX buffers DMA memory\n"); 6427 return error; 6428 } 6429 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6430 SLIST_INIT(&ring->freelist); 6431 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6432 rbuf = &ring->rbuf[i]; 6433 6434 rbuf->sc = sc; /* Backpointer for callbacks. */ 6435 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6436 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6437 6438 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6439 } 6440 ring->nb_free_entries = IWN_RBUF_COUNT; 6441 return 0; 6442 } 6443 6444 static void 6445 iwn_free_rpool(struct iwn_softc *sc) 6446 { 6447 iwn_dma_contig_free(&sc->rxq.buf_dma); 6448 } 6449 #endif 6450 6451 /* 6452 * XXX code from OpenBSD src/sys/net80211/ieee80211_output.c 6453 * Copyright (c) 2001 Atsushi Onoe 6454 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 6455 * Copyright (c) 2007-2009 Damien Bergamini 6456 * All rights reserved. 6457 */ 6458 6459 /* 6460 * Add an SSID element to a frame (see 7.3.2.1). 6461 */ 6462 static u_int8_t * 6463 ieee80211_add_ssid(u_int8_t *frm, const u_int8_t *ssid, u_int len) 6464 { 6465 *frm++ = IEEE80211_ELEMID_SSID; 6466 *frm++ = len; 6467 memcpy(frm, ssid, len); 6468 return frm + len; 6469 } 6470 6471 /* 6472 * Add a supported rates element to a frame (see 7.3.2.2). 6473 */ 6474 static u_int8_t * 6475 ieee80211_add_rates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6476 { 6477 int nrates; 6478 6479 *frm++ = IEEE80211_ELEMID_RATES; 6480 nrates = min(rs->rs_nrates, IEEE80211_RATE_SIZE); 6481 *frm++ = nrates; 6482 memcpy(frm, rs->rs_rates, nrates); 6483 return frm + nrates; 6484 } 6485 6486 /* 6487 * Add an extended supported rates element to a frame (see 7.3.2.14). 6488 */ 6489 static u_int8_t * 6490 ieee80211_add_xrates(u_int8_t *frm, const struct ieee80211_rateset *rs) 6491 { 6492 int nrates; 6493 6494 KASSERT(rs->rs_nrates > IEEE80211_RATE_SIZE); 6495 6496 *frm++ = IEEE80211_ELEMID_XRATES; 6497 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE; 6498 *frm++ = nrates; 6499 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates); 6500 return frm + nrates; 6501 } 6502 6503 /* 6504 * XXX: Hack to set the current channel to the value advertised in beacons or 6505 * probe responses. Only used during AP detection. 6506 * XXX: Duplicated from if_iwi.c 6507 */ 6508 static void 6509 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m) 6510 { 6511 struct ieee80211_frame *wh; 6512 uint8_t subtype; 6513 uint8_t *frm, *efrm; 6514 6515 wh = mtod(m, struct ieee80211_frame *); 6516 6517 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6518 return; 6519 6520 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6521 6522 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6523 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6524 return; 6525 6526 frm = (uint8_t *)(wh + 1); 6527 efrm = mtod(m, uint8_t *) + m->m_len; 6528 6529 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6530 while (frm < efrm) { 6531 if (*frm == IEEE80211_ELEMID_DSPARMS) 6532 #if IEEE80211_CHAN_MAX < 255 6533 if (frm[2] <= IEEE80211_CHAN_MAX) 6534 #endif 6535 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6536 6537 frm += frm[1] + 2; 6538 } 6539 } 6540 6541 #ifdef notyetMODULE 6542 6543 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci"); 6544 6545 #ifdef _MODULE 6546 #include "ioconf.c" 6547 #endif 6548 6549 static int 6550 if_iwn_modcmd(modcmd_t cmd, void *data) 6551 { 6552 int error = 0; 6553 6554 switch (cmd) { 6555 case MODULE_CMD_INIT: 6556 #ifdef _MODULE 6557 error = config_init_component(cfdriver_ioconf_if_iwn, 6558 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6559 #endif 6560 return error; 6561 case MODULE_CMD_FINI: 6562 #ifdef _MODULE 6563 error = config_fini_component(cfdriver_ioconf_if_iwn, 6564 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6565 #endif 6566 return error; 6567 case MODULE_CMD_AUTOUNLOAD: 6568 #ifdef _MODULE 6569 /* XXX This is not optional! */ 6570 #endif 6571 return error; 6572 default: 6573 return ENOTTY; 6574 } 6575 } 6576 #endif 6577
Indexes created Thu Oct 02 14:10:14 GMT 2025