if_iwn.c revision 1.91.4.1
1 /* $NetBSD: if_iwn.c,v 1.91.4.1 2024/04/17 16:24:26 martin Exp $ */ 2 /* $OpenBSD: if_iwn.c,v 1.135 2014/09/10 07:22:09 dcoppa Exp $ */ 3 4 /*- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 22 * adapters. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: if_iwn.c,v 1.91.4.1 2024/04/17 16:24:26 martin Exp $"); 26 27 #define IWN_USE_RBUF /* Use local storage for RX */ 28 #undef IWN_HWCRYPTO /* XXX does not even compile yet */ 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/proc.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #ifdef notyetMODULE 39 #include <sys/module.h> 40 #endif 41 #include <sys/mutex.h> 42 #include <sys/conf.h> 43 #include <sys/kauth.h> 44 #include <sys/callout.h> 45 46 #include <dev/sysmon/sysmonvar.h> 47 48 #include <sys/bus.h> 49 #include <machine/endian.h> 50 #include <sys/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <net/if_ether.h> 67 #include <netinet/ip.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_amrr.h> 71 #include <net80211/ieee80211_radiotap.h> 72 73 #include <dev/firmload.h> 74 75 #include <dev/pci/if_iwnreg.h> 76 #include <dev/pci/if_iwnvar.h> 77 78 static const pci_product_id_t iwn_devices[] = { 79 PCI_PRODUCT_INTEL_WIFI_LINK_1030_1, 80 PCI_PRODUCT_INTEL_WIFI_LINK_1030_2, 81 PCI_PRODUCT_INTEL_WIFI_LINK_4965_1, 82 PCI_PRODUCT_INTEL_WIFI_LINK_4965_2, 83 PCI_PRODUCT_INTEL_WIFI_LINK_4965_3, 84 PCI_PRODUCT_INTEL_WIFI_LINK_4965_4, 85 PCI_PRODUCT_INTEL_WIFI_LINK_5100_1, 86 PCI_PRODUCT_INTEL_WIFI_LINK_5100_2, 87 PCI_PRODUCT_INTEL_WIFI_LINK_5150_1, 88 PCI_PRODUCT_INTEL_WIFI_LINK_5150_2, 89 PCI_PRODUCT_INTEL_WIFI_LINK_5300_1, 90 PCI_PRODUCT_INTEL_WIFI_LINK_5300_2, 91 PCI_PRODUCT_INTEL_WIFI_LINK_5350_1, 92 PCI_PRODUCT_INTEL_WIFI_LINK_5350_2, 93 PCI_PRODUCT_INTEL_WIFI_LINK_1000_1, 94 PCI_PRODUCT_INTEL_WIFI_LINK_1000_2, 95 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_1, 96 PCI_PRODUCT_INTEL_WIFI_LINK_6000_3X3_2, 97 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1, 98 PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2, 99 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_1, 100 PCI_PRODUCT_INTEL_WIFI_LINK_6050_2X2_2, 101 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1, 102 PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2, 103 PCI_PRODUCT_INTEL_WIFI_LINK_6230_1, 104 PCI_PRODUCT_INTEL_WIFI_LINK_6230_2, 105 PCI_PRODUCT_INTEL_WIFI_LINK_6235, 106 PCI_PRODUCT_INTEL_WIFI_LINK_6235_2, 107 PCI_PRODUCT_INTEL_WIFI_LINK_100_1, 108 PCI_PRODUCT_INTEL_WIFI_LINK_100_2, 109 PCI_PRODUCT_INTEL_WIFI_LINK_130_1, 110 PCI_PRODUCT_INTEL_WIFI_LINK_130_2, 111 PCI_PRODUCT_INTEL_WIFI_LINK_2230_1, 112 PCI_PRODUCT_INTEL_WIFI_LINK_2230_2, 113 PCI_PRODUCT_INTEL_WIFI_LINK_2200_1, 114 PCI_PRODUCT_INTEL_WIFI_LINK_2200_2, 115 PCI_PRODUCT_INTEL_WIFI_LINK_135_1, 116 PCI_PRODUCT_INTEL_WIFI_LINK_135_2, 117 PCI_PRODUCT_INTEL_WIFI_LINK_105_1, 118 PCI_PRODUCT_INTEL_WIFI_LINK_105_2, 119 }; 120 121 static int iwn_match(device_t , struct cfdata *, void *); 122 static void iwn_attach(device_t , device_t , void *); 123 static int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 124 static int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 125 static void iwn_radiotap_attach(struct iwn_softc *); 126 static int iwn_detach(device_t , int); 127 #if 0 128 static void iwn_power(int, void *); 129 #endif 130 static bool iwn_resume(device_t, const pmf_qual_t *); 131 static int iwn_nic_lock(struct iwn_softc *); 132 static int iwn_eeprom_lock(struct iwn_softc *); 133 static int iwn_init_otprom(struct iwn_softc *); 134 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 135 static int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 136 void **, bus_size_t, bus_size_t); 137 static void iwn_dma_contig_free(struct iwn_dma_info *); 138 static int iwn_alloc_sched(struct iwn_softc *); 139 static void iwn_free_sched(struct iwn_softc *); 140 static int iwn_alloc_kw(struct iwn_softc *); 141 static void iwn_free_kw(struct iwn_softc *); 142 static int iwn_alloc_ict(struct iwn_softc *); 143 static void iwn_free_ict(struct iwn_softc *); 144 static int iwn_alloc_fwmem(struct iwn_softc *); 145 static void iwn_free_fwmem(struct iwn_softc *); 146 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 147 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 148 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 149 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 150 int); 151 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 152 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 153 static void iwn5000_ict_reset(struct iwn_softc *); 154 static int iwn_read_eeprom(struct iwn_softc *); 155 static void iwn4965_read_eeprom(struct iwn_softc *); 156 157 #ifdef IWN_DEBUG 158 static void iwn4965_print_power_group(struct iwn_softc *, int); 159 #endif 160 static void iwn5000_read_eeprom(struct iwn_softc *); 161 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 162 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 163 static struct ieee80211_node *iwn_node_alloc(struct ieee80211_node_table *); 164 static void iwn_newassoc(struct ieee80211_node *, int); 165 static int iwn_media_change(struct ifnet *); 166 static int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 167 static void iwn_iter_func(void *, struct ieee80211_node *); 168 static void iwn_calib_timeout(void *); 169 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 170 struct iwn_rx_data *); 171 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 172 struct iwn_rx_data *); 173 #ifndef IEEE80211_NO_HT 174 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 #endif 177 static void iwn5000_rx_calib_results(struct iwn_softc *, 178 struct iwn_rx_desc *, struct iwn_rx_data *); 179 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 180 struct iwn_rx_data *); 181 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 184 struct iwn_rx_data *); 185 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 186 uint8_t); 187 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 188 static void iwn_notif_intr(struct iwn_softc *); 189 static void iwn_wakeup_intr(struct iwn_softc *); 190 static void iwn_fatal_intr(struct iwn_softc *); 191 static int iwn_intr(void *); 192 static void iwn_softintr(void *); 193 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 194 uint16_t); 195 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 196 uint16_t); 197 #ifdef notyet 198 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 199 #endif 200 static int iwn_tx(struct iwn_softc *, struct mbuf *, 201 struct ieee80211_node *, int); 202 static void iwn_start(struct ifnet *); 203 static void iwn_watchdog(struct ifnet *); 204 static int iwn_ioctl(struct ifnet *, u_long, void *); 205 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 206 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 207 int); 208 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 209 int); 210 static int iwn_set_link_quality(struct iwn_softc *, 211 struct ieee80211_node *); 212 static int iwn_add_broadcast_node(struct iwn_softc *, int); 213 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 214 static int iwn_set_critical_temp(struct iwn_softc *); 215 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 216 static void iwn4965_power_calibration(struct iwn_softc *, int); 217 static int iwn4965_set_txpower(struct iwn_softc *, int); 218 static int iwn5000_set_txpower(struct iwn_softc *, int); 219 static int iwn4965_get_rssi(const struct iwn_rx_stat *); 220 static int iwn5000_get_rssi(const struct iwn_rx_stat *); 221 static int iwn_get_noise(const struct iwn_rx_general_stats *); 222 static int iwn4965_get_temperature(struct iwn_softc *); 223 static int iwn5000_get_temperature(struct iwn_softc *); 224 static int iwn_init_sensitivity(struct iwn_softc *); 225 static void iwn_collect_noise(struct iwn_softc *, 226 const struct iwn_rx_general_stats *); 227 static int iwn4965_init_gains(struct iwn_softc *); 228 static int iwn5000_init_gains(struct iwn_softc *); 229 static int iwn4965_set_gains(struct iwn_softc *); 230 static int iwn5000_set_gains(struct iwn_softc *); 231 static void iwn_tune_sensitivity(struct iwn_softc *, 232 const struct iwn_rx_stats *); 233 static int iwn_send_sensitivity(struct iwn_softc *); 234 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 235 static int iwn5000_runtime_calib(struct iwn_softc *); 236 237 static int iwn_config_bt_coex_bluetooth(struct iwn_softc *); 238 static int iwn_config_bt_coex_prio_table(struct iwn_softc *); 239 static int iwn_config_bt_coex_adv1(struct iwn_softc *); 240 static int iwn_config_bt_coex_adv2(struct iwn_softc *); 241 242 static int iwn_config(struct iwn_softc *); 243 static uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, 244 uint8_t); 245 static uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 246 static uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 247 static int iwn_scan(struct iwn_softc *, uint16_t); 248 static int iwn_auth(struct iwn_softc *); 249 static int iwn_run(struct iwn_softc *); 250 #ifdef IWN_HWCRYPTO 251 static int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 252 struct ieee80211_key *); 253 static void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 254 struct ieee80211_key *); 255 #endif 256 static int iwn_wme_update(struct ieee80211com *); 257 #ifndef IEEE80211_NO_HT 258 static int iwn_ampdu_rx_start(struct ieee80211com *, 259 struct ieee80211_node *, uint8_t); 260 static void iwn_ampdu_rx_stop(struct ieee80211com *, 261 struct ieee80211_node *, uint8_t); 262 static int iwn_ampdu_tx_start(struct ieee80211com *, 263 struct ieee80211_node *, uint8_t); 264 static void iwn_ampdu_tx_stop(struct ieee80211com *, 265 struct ieee80211_node *, uint8_t); 266 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 267 struct ieee80211_node *, uint8_t, uint16_t); 268 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, 269 uint8_t, uint16_t); 270 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 271 struct ieee80211_node *, uint8_t, uint16_t); 272 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, 273 uint8_t, uint16_t); 274 #endif 275 static int iwn5000_query_calibration(struct iwn_softc *); 276 static int iwn5000_send_calibration(struct iwn_softc *); 277 static int iwn5000_send_wimax_coex(struct iwn_softc *); 278 static int iwn6000_temp_offset_calib(struct iwn_softc *); 279 static int iwn2000_temp_offset_calib(struct iwn_softc *); 280 static int iwn4965_post_alive(struct iwn_softc *); 281 static int iwn5000_post_alive(struct iwn_softc *); 282 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 283 int); 284 static int iwn4965_load_firmware(struct iwn_softc *); 285 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 286 const uint8_t *, int); 287 static int iwn5000_load_firmware(struct iwn_softc *); 288 static int iwn_read_firmware_leg(struct iwn_softc *, 289 struct iwn_fw_info *); 290 static int iwn_read_firmware_tlv(struct iwn_softc *, 291 struct iwn_fw_info *, uint16_t); 292 static int iwn_read_firmware(struct iwn_softc *); 293 static int iwn_clock_wait(struct iwn_softc *); 294 static int iwn_apm_init(struct iwn_softc *); 295 static void iwn_apm_stop_master(struct iwn_softc *); 296 static void iwn_apm_stop(struct iwn_softc *); 297 static int iwn4965_nic_config(struct iwn_softc *); 298 static int iwn5000_nic_config(struct iwn_softc *); 299 static int iwn_hw_prepare(struct iwn_softc *); 300 static int iwn_hw_init(struct iwn_softc *); 301 static void iwn_hw_stop(struct iwn_softc *); 302 static int iwn_init(struct ifnet *); 303 static void iwn_stop(struct ifnet *, int); 304 305 /* XXX MCLGETI alternative */ 306 static struct mbuf *MCLGETIalt(struct iwn_softc *, int, 307 struct ifnet *, u_int); 308 #ifdef IWN_USE_RBUF 309 static struct iwn_rbuf *iwn_alloc_rbuf(struct iwn_softc *); 310 static void iwn_free_rbuf(struct mbuf *, void *, size_t, void *); 311 static int iwn_alloc_rpool(struct iwn_softc *); 312 static void iwn_free_rpool(struct iwn_softc *); 313 #endif 314 315 static void iwn_fix_channel(struct ieee80211com *, struct mbuf *, 316 struct iwn_rx_stat *); 317 318 #ifdef IWN_DEBUG 319 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 320 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 321 int iwn_debug = 0; 322 #else 323 #define DPRINTF(x) 324 #define DPRINTFN(n, x) 325 #endif 326 327 CFATTACH_DECL_NEW(iwn, sizeof(struct iwn_softc), iwn_match, iwn_attach, 328 iwn_detach, NULL); 329 330 static int 331 iwn_match(device_t parent, cfdata_t match __unused, void *aux) 332 { 333 struct pci_attach_args *pa = aux; 334 size_t i; 335 336 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 337 return 0; 338 339 for (i = 0; i < __arraycount(iwn_devices); i++) 340 if (PCI_PRODUCT(pa->pa_id) == iwn_devices[i]) 341 return 1; 342 343 return 0; 344 } 345 346 static void 347 iwn_attach(device_t parent __unused, device_t self, void *aux) 348 { 349 struct iwn_softc *sc = device_private(self); 350 struct ieee80211com *ic = &sc->sc_ic; 351 struct ifnet *ifp = &sc->sc_ec.ec_if; 352 struct pci_attach_args *pa = aux; 353 const char *intrstr; 354 pcireg_t memtype, reg; 355 int i, error; 356 char intrbuf[PCI_INTRSTR_LEN]; 357 358 sc->sc_dev = self; 359 sc->sc_pct = pa->pa_pc; 360 sc->sc_pcitag = pa->pa_tag; 361 sc->sc_dmat = pa->pa_dmat; 362 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE); 363 364 callout_init(&sc->calib_to, 0); 365 callout_setfunc(&sc->calib_to, iwn_calib_timeout, sc); 366 367 pci_aprint_devinfo(pa, NULL); 368 369 /* 370 * Get the offset of the PCI Express Capability Structure in PCI 371 * Configuration Space. 372 */ 373 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 374 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 375 if (error == 0) { 376 aprint_error_dev(self, 377 "PCIe capability structure not found!\n"); 378 return; 379 } 380 381 /* Clear device-specific "PCI retry timeout" register (41h). */ 382 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 383 if (reg & 0xff00) 384 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 385 386 /* Enable bus-mastering. */ 387 /* XXX verify the bus-mastering is really needed (not in OpenBSD) */ 388 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 389 reg |= PCI_COMMAND_MASTER_ENABLE; 390 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 391 392 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 393 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 394 &sc->sc_sh, NULL, &sc->sc_sz); 395 if (error != 0) { 396 aprint_error_dev(self, "can't map mem space\n"); 397 return; 398 } 399 400 sc->sc_soft_ih = softint_establish(SOFTINT_NET, iwn_softintr, sc); 401 if (sc->sc_soft_ih == NULL) { 402 aprint_error_dev(self, "can't establish soft interrupt\n"); 403 goto unmap; 404 } 405 406 /* Install interrupt handler. */ 407 error = pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0); 408 if (error) { 409 aprint_error_dev(self, "can't allocate interrupt\n"); 410 goto failsi; 411 } 412 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 413 if (pci_intr_type(sc->sc_pct, sc->sc_pihp[0]) == PCI_INTR_TYPE_INTX) 414 CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE); 415 else 416 SET(reg, PCI_COMMAND_INTERRUPT_DISABLE); 417 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 418 intrstr = pci_intr_string(sc->sc_pct, sc->sc_pihp[0], intrbuf, 419 sizeof(intrbuf)); 420 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, sc->sc_pihp[0], 421 IPL_NET, iwn_intr, sc, device_xname(self)); 422 if (sc->sc_ih == NULL) { 423 aprint_error_dev(self, "can't establish interrupt"); 424 if (intrstr != NULL) 425 aprint_error(" at %s", intrstr); 426 aprint_error("\n"); 427 goto failia; 428 } 429 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 430 431 /* Read hardware revision and attach. */ 432 sc->hw_type = 433 (IWN_READ(sc, IWN_HW_REV) & IWN_HW_REV_TYPE_MASK) 434 >> IWN_HW_REV_TYPE_SHIFT; 435 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 436 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 437 else 438 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 439 if (error != 0) { 440 aprint_error_dev(self, "could not attach device\n"); 441 goto failih; 442 } 443 444 if ((error = iwn_hw_prepare(sc)) != 0) { 445 aprint_error_dev(self, "hardware not ready\n"); 446 goto failih; 447 } 448 449 /* Read MAC address, channels, etc from EEPROM. */ 450 if ((error = iwn_read_eeprom(sc)) != 0) { 451 aprint_error_dev(self, "could not read EEPROM\n"); 452 goto failih; 453 } 454 455 /* Allocate DMA memory for firmware transfers. */ 456 if ((error = iwn_alloc_fwmem(sc)) != 0) { 457 aprint_error_dev(self, 458 "could not allocate memory for firmware\n"); 459 goto failih; 460 } 461 462 /* Allocate "Keep Warm" page. */ 463 if ((error = iwn_alloc_kw(sc)) != 0) { 464 aprint_error_dev(self, "could not allocate keep warm page\n"); 465 goto fail1; 466 } 467 468 /* Allocate ICT table for 5000 Series. */ 469 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 470 (error = iwn_alloc_ict(sc)) != 0) { 471 aprint_error_dev(self, "could not allocate ICT table\n"); 472 goto fail2; 473 } 474 475 /* Allocate TX scheduler "rings". */ 476 if ((error = iwn_alloc_sched(sc)) != 0) { 477 aprint_error_dev(self, 478 "could not allocate TX scheduler rings\n"); 479 goto fail3; 480 } 481 482 #ifdef IWN_USE_RBUF 483 /* Allocate RX buffers. */ 484 if ((error = iwn_alloc_rpool(sc)) != 0) { 485 aprint_error_dev(self, "could not allocate RX buffers\n"); 486 goto fail3; 487 } 488 #endif 489 490 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 491 for (i = 0; i < sc->ntxqs; i++) { 492 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 493 aprint_error_dev(self, 494 "could not allocate TX ring %d\n", i); 495 goto fail4; 496 } 497 } 498 499 /* Allocate RX ring. */ 500 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 501 aprint_error_dev(self, "could not allocate RX ring\n"); 502 goto fail4; 503 } 504 505 /* Clear pending interrupts. */ 506 IWN_WRITE(sc, IWN_INT, 0xffffffff); 507 508 /* Count the number of available chains. */ 509 sc->ntxchains = 510 ((sc->txchainmask >> 2) & 1) + 511 ((sc->txchainmask >> 1) & 1) + 512 ((sc->txchainmask >> 0) & 1); 513 sc->nrxchains = 514 ((sc->rxchainmask >> 2) & 1) + 515 ((sc->rxchainmask >> 1) & 1) + 516 ((sc->rxchainmask >> 0) & 1); 517 aprint_normal_dev(self, "MIMO %dT%dR, %.4s, address %s\n", 518 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 519 ether_sprintf(ic->ic_myaddr)); 520 521 ic->ic_ifp = ifp; 522 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 523 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 524 ic->ic_state = IEEE80211_S_INIT; 525 526 /* 527 * Set device capabilities. 528 * XXX OpenBSD has IEEE80211_C_WEP, IEEE80211_C_RSN, and 529 * IEEE80211_C_PMGT too. 530 */ 531 ic->ic_caps = 532 IEEE80211_C_IBSS | /* IBSS mode support */ 533 IEEE80211_C_WPA | /* 802.11i */ 534 IEEE80211_C_MONITOR | /* monitor mode supported */ 535 IEEE80211_C_TXPMGT | /* tx power management */ 536 IEEE80211_C_SHSLOT | /* short slot time supported */ 537 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 538 IEEE80211_C_WME; /* 802.11e */ 539 540 #ifndef IEEE80211_NO_HT 541 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 542 /* Set HT capabilities. */ 543 ic->ic_htcaps = 544 #if IWN_RBUF_SIZE == 8192 545 IEEE80211_HTCAP_AMSDU7935 | 546 #endif 547 IEEE80211_HTCAP_CBW20_40 | 548 IEEE80211_HTCAP_SGI20 | 549 IEEE80211_HTCAP_SGI40; 550 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 551 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 552 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 553 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 554 else 555 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 556 } 557 #endif /* !IEEE80211_NO_HT */ 558 559 /* Set supported legacy rates. */ 560 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 561 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 562 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 563 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a; 564 } 565 #ifndef IEEE80211_NO_HT 566 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 567 /* Set supported HT rates. */ 568 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 569 if (sc->nrxchains > 1) 570 ic->ic_sup_mcs[1] = 0xff; /* MCS 7-15 */ 571 if (sc->nrxchains > 2) 572 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 573 } 574 #endif 575 576 /* IBSS channel undefined for now. */ 577 ic->ic_ibss_chan = &ic->ic_channels[0]; 578 579 ifp->if_softc = sc; 580 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 581 ifp->if_init = iwn_init; 582 ifp->if_ioctl = iwn_ioctl; 583 ifp->if_start = iwn_start; 584 ifp->if_stop = iwn_stop; 585 ifp->if_watchdog = iwn_watchdog; 586 IFQ_SET_READY(&ifp->if_snd); 587 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 588 589 error = if_initialize(ifp); 590 if (error != 0) { 591 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 592 error); 593 goto fail5; 594 } 595 ieee80211_ifattach(ic); 596 /* Use common softint-based if_input */ 597 ifp->if_percpuq = if_percpuq_create(ifp); 598 if_register(ifp); 599 600 ic->ic_node_alloc = iwn_node_alloc; 601 ic->ic_newassoc = iwn_newassoc; 602 #ifdef IWN_HWCRYPTO 603 ic->ic_crypto.cs_key_set = iwn_set_key; 604 ic->ic_crypto.cs_key_delete = iwn_delete_key; 605 #endif 606 ic->ic_wme.wme_update = iwn_wme_update; 607 #ifndef IEEE80211_NO_HT 608 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 609 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 610 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 611 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 612 #endif 613 614 /* Override 802.11 state transition machine. */ 615 sc->sc_newstate = ic->ic_newstate; 616 ic->ic_newstate = iwn_newstate; 617 ieee80211_media_init(ic, iwn_media_change, ieee80211_media_status); 618 619 sc->amrr.amrr_min_success_threshold = 1; 620 sc->amrr.amrr_max_success_threshold = 15; 621 622 iwn_radiotap_attach(sc); 623 624 /* 625 * XXX for NetBSD, OpenBSD timeout_set replaced by 626 * callout_init and callout_setfunc, above. 627 */ 628 629 if (pmf_device_register(self, NULL, iwn_resume)) 630 pmf_class_network_register(self, ifp); 631 else 632 aprint_error_dev(self, "couldn't establish power handler\n"); 633 634 /* XXX NetBSD add call to ieee80211_announce for dmesg. */ 635 ieee80211_announce(ic); 636 637 sc->sc_flags |= IWN_FLAG_ATTACHED; 638 return; 639 640 /* Free allocated memory if something failed during attachment. */ 641 fail5: iwn_free_rx_ring(sc, &sc->rxq); 642 fail4: while (--i >= 0) 643 iwn_free_tx_ring(sc, &sc->txq[i]); 644 #ifdef IWN_USE_RBUF 645 iwn_free_rpool(sc); 646 #endif 647 iwn_free_sched(sc); 648 fail3: if (sc->ict != NULL) 649 iwn_free_ict(sc); 650 fail2: iwn_free_kw(sc); 651 fail1: iwn_free_fwmem(sc); 652 failih: pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 653 sc->sc_ih = NULL; 654 failia: pci_intr_release(sc->sc_pct, sc->sc_pihp, 1); 655 sc->sc_pihp = NULL; 656 failsi: softint_disestablish(sc->sc_soft_ih); 657 sc->sc_soft_ih = NULL; 658 unmap: bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 659 } 660 661 int 662 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 663 { 664 struct iwn_ops *ops = &sc->ops; 665 666 ops->load_firmware = iwn4965_load_firmware; 667 ops->read_eeprom = iwn4965_read_eeprom; 668 ops->post_alive = iwn4965_post_alive; 669 ops->nic_config = iwn4965_nic_config; 670 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 671 ops->update_sched = iwn4965_update_sched; 672 ops->get_temperature = iwn4965_get_temperature; 673 ops->get_rssi = iwn4965_get_rssi; 674 ops->set_txpower = iwn4965_set_txpower; 675 ops->init_gains = iwn4965_init_gains; 676 ops->set_gains = iwn4965_set_gains; 677 ops->add_node = iwn4965_add_node; 678 ops->tx_done = iwn4965_tx_done; 679 #ifndef IEEE80211_NO_HT 680 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 681 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 682 #endif 683 sc->ntxqs = IWN4965_NTXQUEUES; 684 sc->ndmachnls = IWN4965_NDMACHNLS; 685 sc->broadcast_id = IWN4965_ID_BROADCAST; 686 sc->rxonsz = IWN4965_RXONSZ; 687 sc->schedsz = IWN4965_SCHEDSZ; 688 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 689 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 690 sc->fwsz = IWN4965_FWSZ; 691 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 692 sc->limits = &iwn4965_sensitivity_limits; 693 sc->fwname = "iwlwifi-4965-2.ucode"; 694 /* Override chains masks, ROM is known to be broken. */ 695 sc->txchainmask = IWN_ANT_AB; 696 sc->rxchainmask = IWN_ANT_ABC; 697 698 return 0; 699 } 700 701 int 702 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 703 { 704 struct iwn_ops *ops = &sc->ops; 705 706 ops->load_firmware = iwn5000_load_firmware; 707 ops->read_eeprom = iwn5000_read_eeprom; 708 ops->post_alive = iwn5000_post_alive; 709 ops->nic_config = iwn5000_nic_config; 710 ops->config_bt_coex = iwn_config_bt_coex_bluetooth; 711 ops->update_sched = iwn5000_update_sched; 712 ops->get_temperature = iwn5000_get_temperature; 713 ops->get_rssi = iwn5000_get_rssi; 714 ops->set_txpower = iwn5000_set_txpower; 715 ops->init_gains = iwn5000_init_gains; 716 ops->set_gains = iwn5000_set_gains; 717 ops->add_node = iwn5000_add_node; 718 ops->tx_done = iwn5000_tx_done; 719 #ifndef IEEE80211_NO_HT 720 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 721 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 722 #endif 723 sc->ntxqs = IWN5000_NTXQUEUES; 724 sc->ndmachnls = IWN5000_NDMACHNLS; 725 sc->broadcast_id = IWN5000_ID_BROADCAST; 726 sc->rxonsz = IWN5000_RXONSZ; 727 sc->schedsz = IWN5000_SCHEDSZ; 728 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 729 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 730 sc->fwsz = IWN5000_FWSZ; 731 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 732 733 switch (sc->hw_type) { 734 case IWN_HW_REV_TYPE_5100: 735 sc->limits = &iwn5000_sensitivity_limits; 736 sc->fwname = "iwlwifi-5000-2.ucode"; 737 /* Override chains masks, ROM is known to be broken. */ 738 sc->txchainmask = IWN_ANT_B; 739 sc->rxchainmask = IWN_ANT_AB; 740 break; 741 case IWN_HW_REV_TYPE_5150: 742 sc->limits = &iwn5150_sensitivity_limits; 743 sc->fwname = "iwlwifi-5150-2.ucode"; 744 break; 745 case IWN_HW_REV_TYPE_5300: 746 case IWN_HW_REV_TYPE_5350: 747 sc->limits = &iwn5000_sensitivity_limits; 748 sc->fwname = "iwlwifi-5000-2.ucode"; 749 break; 750 case IWN_HW_REV_TYPE_1000: 751 sc->limits = &iwn1000_sensitivity_limits; 752 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_1 || 753 pid == PCI_PRODUCT_INTEL_WIFI_LINK_100_2) 754 sc->fwname = "iwlwifi-100-5.ucode"; 755 else 756 sc->fwname = "iwlwifi-1000-3.ucode"; 757 break; 758 case IWN_HW_REV_TYPE_6000: 759 sc->limits = &iwn6000_sensitivity_limits; 760 sc->fwname = "iwlwifi-6000-4.ucode"; 761 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_1 || 762 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6000_IPA_2) { 763 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 764 /* Override chains masks, ROM is known to be broken. */ 765 sc->txchainmask = IWN_ANT_BC; 766 sc->rxchainmask = IWN_ANT_BC; 767 } 768 break; 769 case IWN_HW_REV_TYPE_6050: 770 sc->limits = &iwn6000_sensitivity_limits; 771 sc->fwname = "iwlwifi-6050-5.ucode"; 772 break; 773 case IWN_HW_REV_TYPE_6005: 774 sc->limits = &iwn6000_sensitivity_limits; 775 /* Type 6030 cards return IWN_HW_REV_TYPE_6005 */ 776 if (pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_1 || 777 pid == PCI_PRODUCT_INTEL_WIFI_LINK_1030_2 || 778 pid == PCI_PRODUCT_INTEL_WIFI_LINK_130_1 || 779 pid == PCI_PRODUCT_INTEL_WIFI_LINK_130_2 || 780 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_1 || 781 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6230_2 || 782 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235 || 783 pid == PCI_PRODUCT_INTEL_WIFI_LINK_6235_2) { 784 sc->fwname = "iwlwifi-6000g2b-6.ucode"; 785 ops->config_bt_coex = iwn_config_bt_coex_adv1; 786 } 787 /* 788 * This covers: 789 * PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_1 790 * PCI_PRODUCT_INTEL_WIFI_LINK_6005_2X2_2 791 */ 792 else 793 sc->fwname = "iwlwifi-6000g2a-5.ucode"; 794 break; 795 case IWN_HW_REV_TYPE_2030: 796 sc->limits = &iwn2030_sensitivity_limits; 797 sc->fwname = "iwlwifi-2030-6.ucode"; 798 ops->config_bt_coex = iwn_config_bt_coex_adv2; 799 break; 800 case IWN_HW_REV_TYPE_2000: 801 sc->limits = &iwn2000_sensitivity_limits; 802 sc->fwname = "iwlwifi-2000-6.ucode"; 803 break; 804 case IWN_HW_REV_TYPE_135: 805 sc->limits = &iwn2000_sensitivity_limits; 806 sc->fwname = "iwlwifi-135-6.ucode"; 807 ops->config_bt_coex = iwn_config_bt_coex_adv2; 808 break; 809 case IWN_HW_REV_TYPE_105: 810 sc->limits = &iwn2000_sensitivity_limits; 811 sc->fwname = "iwlwifi-105-6.ucode"; 812 break; 813 default: 814 aprint_normal(": adapter type %d not supported\n", sc->hw_type); 815 return ENOTSUP; 816 } 817 return 0; 818 } 819 820 /* 821 * Attach the interface to 802.11 radiotap. 822 */ 823 static void 824 iwn_radiotap_attach(struct iwn_softc *sc) 825 { 826 struct ifnet *ifp = sc->sc_ic.ic_ifp; 827 828 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 829 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 830 &sc->sc_drvbpf); 831 832 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 833 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 834 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 835 836 sc->sc_txtap_len = sizeof sc->sc_txtapu; 837 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 838 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 839 } 840 841 static int 842 iwn_detach(device_t self, int flags __unused) 843 { 844 struct iwn_softc *sc = device_private(self); 845 struct ifnet *ifp = sc->sc_ic.ic_ifp; 846 int qid; 847 848 if (!(sc->sc_flags & IWN_FLAG_ATTACHED)) 849 return 0; 850 851 callout_stop(&sc->calib_to); 852 853 /* Uninstall interrupt handler. */ 854 if (sc->sc_ih != NULL) 855 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 856 if (sc->sc_pihp != NULL) 857 pci_intr_release(sc->sc_pct, sc->sc_pihp, 1); 858 if (sc->sc_soft_ih != NULL) 859 softint_disestablish(sc->sc_soft_ih); 860 861 /* Free DMA resources. */ 862 iwn_free_rx_ring(sc, &sc->rxq); 863 for (qid = 0; qid < sc->ntxqs; qid++) 864 iwn_free_tx_ring(sc, &sc->txq[qid]); 865 #ifdef IWN_USE_RBUF 866 iwn_free_rpool(sc); 867 #endif 868 iwn_free_sched(sc); 869 iwn_free_kw(sc); 870 if (sc->ict != NULL) 871 iwn_free_ict(sc); 872 iwn_free_fwmem(sc); 873 874 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 875 876 ieee80211_ifdetach(&sc->sc_ic); 877 if_detach(ifp); 878 879 return 0; 880 } 881 882 #if 0 883 /* 884 * XXX Investigate if clearing the PCI retry timeout could eliminate 885 * the repeated scan calls. Also the calls to if_init and if_start 886 * are similar to the effect of adding the call to ifioctl_common . 887 */ 888 static void 889 iwn_power(int why, void *arg) 890 { 891 struct iwn_softc *sc = arg; 892 struct ifnet *ifp; 893 pcireg_t reg; 894 int s; 895 896 if (why != PWR_RESUME) 897 return; 898 899 /* Clear device-specific "PCI retry timeout" register (41h). */ 900 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 901 if (reg & 0xff00) 902 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 903 904 s = splnet(); 905 ifp = &sc->sc_ic.ic_if; 906 if (ifp->if_flags & IFF_UP) { 907 ifp->if_init(ifp); 908 if (ifp->if_flags & IFF_RUNNING) 909 ifp->if_start(ifp); 910 } 911 splx(s); 912 } 913 #endif 914 915 static bool 916 iwn_resume(device_t dv, const pmf_qual_t *qual) 917 { 918 return true; 919 } 920 921 static int 922 iwn_nic_lock(struct iwn_softc *sc) 923 { 924 int ntries; 925 926 /* Request exclusive access to NIC. */ 927 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 928 929 /* Spin until we actually get the lock. */ 930 for (ntries = 0; ntries < 1000; ntries++) { 931 if ((IWN_READ(sc, IWN_GP_CNTRL) & 932 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 933 IWN_GP_CNTRL_MAC_ACCESS_ENA) 934 return 0; 935 DELAY(10); 936 } 937 return ETIMEDOUT; 938 } 939 940 static __inline void 941 iwn_nic_unlock(struct iwn_softc *sc) 942 { 943 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 944 } 945 946 static __inline uint32_t 947 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 948 { 949 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 950 IWN_BARRIER_READ_WRITE(sc); 951 return IWN_READ(sc, IWN_PRPH_RDATA); 952 } 953 954 static __inline void 955 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 956 { 957 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 958 IWN_BARRIER_WRITE(sc); 959 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 960 } 961 962 static __inline void 963 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 964 { 965 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 966 } 967 968 static __inline void 969 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 970 { 971 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 972 } 973 974 static __inline void 975 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 976 const uint32_t *data, int count) 977 { 978 for (; count > 0; count--, data++, addr += 4) 979 iwn_prph_write(sc, addr, *data); 980 } 981 982 static __inline uint32_t 983 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 984 { 985 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 986 IWN_BARRIER_READ_WRITE(sc); 987 return IWN_READ(sc, IWN_MEM_RDATA); 988 } 989 990 static __inline void 991 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 992 { 993 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 994 IWN_BARRIER_WRITE(sc); 995 IWN_WRITE(sc, IWN_MEM_WDATA, data); 996 } 997 998 #ifndef IEEE80211_NO_HT 999 static __inline void 1000 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1001 { 1002 uint32_t tmp; 1003 1004 tmp = iwn_mem_read(sc, addr & ~3); 1005 if (addr & 3) 1006 tmp = (tmp & 0x0000ffff) | data << 16; 1007 else 1008 tmp = (tmp & 0xffff0000) | data; 1009 iwn_mem_write(sc, addr & ~3, tmp); 1010 } 1011 #endif 1012 1013 static __inline void 1014 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1015 int count) 1016 { 1017 for (; count > 0; count--, addr += 4) 1018 *data++ = iwn_mem_read(sc, addr); 1019 } 1020 1021 static __inline void 1022 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1023 int count) 1024 { 1025 for (; count > 0; count--, addr += 4) 1026 iwn_mem_write(sc, addr, val); 1027 } 1028 1029 static int 1030 iwn_eeprom_lock(struct iwn_softc *sc) 1031 { 1032 int i, ntries; 1033 1034 for (i = 0; i < 100; i++) { 1035 /* Request exclusive access to EEPROM. */ 1036 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1037 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1038 1039 /* Spin until we actually get the lock. */ 1040 for (ntries = 0; ntries < 100; ntries++) { 1041 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1042 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1043 return 0; 1044 DELAY(10); 1045 } 1046 } 1047 return ETIMEDOUT; 1048 } 1049 1050 static __inline void 1051 iwn_eeprom_unlock(struct iwn_softc *sc) 1052 { 1053 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1054 } 1055 1056 /* 1057 * Initialize access by host to One Time Programmable ROM. 1058 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1059 */ 1060 static int 1061 iwn_init_otprom(struct iwn_softc *sc) 1062 { 1063 uint16_t prev = 0, base, next; 1064 int count, error; 1065 1066 /* Wait for clock stabilization before accessing prph. */ 1067 if ((error = iwn_clock_wait(sc)) != 0) 1068 return error; 1069 1070 if ((error = iwn_nic_lock(sc)) != 0) 1071 return error; 1072 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1073 DELAY(5); 1074 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1075 iwn_nic_unlock(sc); 1076 1077 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1078 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1079 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1080 IWN_RESET_LINK_PWR_MGMT_DIS); 1081 } 1082 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1083 /* Clear ECC status. */ 1084 IWN_SETBITS(sc, IWN_OTP_GP, 1085 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1086 1087 /* 1088 * Find the block before last block (contains the EEPROM image) 1089 * for HW without OTP shadow RAM. 1090 */ 1091 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1092 /* Switch to absolute addressing mode. */ 1093 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1094 base = 0; 1095 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1096 error = iwn_read_prom_data(sc, base, &next, 2); 1097 if (error != 0) 1098 return error; 1099 if (next == 0) /* End of linked-list. */ 1100 break; 1101 prev = base; 1102 base = le16toh(next); 1103 } 1104 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1105 return EIO; 1106 /* Skip "next" word. */ 1107 sc->prom_base = prev + 1; 1108 } 1109 return 0; 1110 } 1111 1112 static int 1113 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1114 { 1115 uint8_t *out = data; 1116 uint32_t val, tmp; 1117 int ntries; 1118 1119 addr += sc->prom_base; 1120 for (; count > 0; count -= 2, addr++) { 1121 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1122 for (ntries = 0; ntries < 10; ntries++) { 1123 val = IWN_READ(sc, IWN_EEPROM); 1124 if (val & IWN_EEPROM_READ_VALID) 1125 break; 1126 DELAY(5); 1127 } 1128 if (ntries == 10) { 1129 aprint_error_dev(sc->sc_dev, 1130 "timeout reading ROM at 0x%x\n", addr); 1131 return ETIMEDOUT; 1132 } 1133 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1134 /* OTPROM, check for ECC errors. */ 1135 tmp = IWN_READ(sc, IWN_OTP_GP); 1136 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1137 aprint_error_dev(sc->sc_dev, 1138 "OTPROM ECC error at 0x%x\n", addr); 1139 return EIO; 1140 } 1141 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1142 /* Correctable ECC error, clear bit. */ 1143 IWN_SETBITS(sc, IWN_OTP_GP, 1144 IWN_OTP_GP_ECC_CORR_STTS); 1145 } 1146 } 1147 *out++ = val >> 16; 1148 if (count > 1) 1149 *out++ = val >> 24; 1150 } 1151 return 0; 1152 } 1153 1154 static int 1155 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1156 bus_size_t size, bus_size_t alignment) 1157 { 1158 int nsegs, error; 1159 1160 dma->tag = tag; 1161 dma->size = size; 1162 1163 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1164 &dma->map); 1165 if (error != 0) 1166 goto fail; 1167 1168 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1169 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */ 1170 if (error != 0) 1171 goto fail; 1172 1173 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1174 BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */ 1175 if (error != 0) 1176 goto fail; 1177 1178 error = bus_dmamap_load(tag, dma->map, dma->vaddr, size, NULL, 1179 BUS_DMA_NOWAIT); 1180 if (error != 0) 1181 goto fail; 1182 1183 /* XXX Presumably needed because of missing BUS_DMA_ZERO, above. */ 1184 memset(dma->vaddr, 0, size); 1185 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1186 1187 dma->paddr = dma->map->dm_segs[0].ds_addr; 1188 if (kvap != NULL) 1189 *kvap = dma->vaddr; 1190 1191 return 0; 1192 1193 fail: iwn_dma_contig_free(dma); 1194 return error; 1195 } 1196 1197 static void 1198 iwn_dma_contig_free(struct iwn_dma_info *dma) 1199 { 1200 if (dma->map != NULL) { 1201 if (dma->vaddr != NULL) { 1202 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1203 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1204 bus_dmamap_unload(dma->tag, dma->map); 1205 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1206 bus_dmamem_free(dma->tag, &dma->seg, 1); 1207 dma->vaddr = NULL; 1208 } 1209 bus_dmamap_destroy(dma->tag, dma->map); 1210 dma->map = NULL; 1211 } 1212 } 1213 1214 static int 1215 iwn_alloc_sched(struct iwn_softc *sc) 1216 { 1217 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1218 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1219 (void **)&sc->sched, sc->schedsz, 1024); 1220 } 1221 1222 static void 1223 iwn_free_sched(struct iwn_softc *sc) 1224 { 1225 iwn_dma_contig_free(&sc->sched_dma); 1226 } 1227 1228 static int 1229 iwn_alloc_kw(struct iwn_softc *sc) 1230 { 1231 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1232 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1233 4096); 1234 } 1235 1236 static void 1237 iwn_free_kw(struct iwn_softc *sc) 1238 { 1239 iwn_dma_contig_free(&sc->kw_dma); 1240 } 1241 1242 static int 1243 iwn_alloc_ict(struct iwn_softc *sc) 1244 { 1245 /* ICT table must be aligned on a 4KB boundary. */ 1246 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1247 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1248 } 1249 1250 static void 1251 iwn_free_ict(struct iwn_softc *sc) 1252 { 1253 iwn_dma_contig_free(&sc->ict_dma); 1254 } 1255 1256 static int 1257 iwn_alloc_fwmem(struct iwn_softc *sc) 1258 { 1259 /* Must be aligned on a 16-byte boundary. */ 1260 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1261 sc->fwsz, 16); 1262 } 1263 1264 static void 1265 iwn_free_fwmem(struct iwn_softc *sc) 1266 { 1267 iwn_dma_contig_free(&sc->fw_dma); 1268 } 1269 1270 static int 1271 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1272 { 1273 bus_size_t size; 1274 int i, error; 1275 1276 ring->cur = 0; 1277 1278 /* Allocate RX descriptors (256-byte aligned). */ 1279 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1280 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1281 (void **)&ring->desc, size, 256); 1282 if (error != 0) { 1283 aprint_error_dev(sc->sc_dev, 1284 "could not allocate RX ring DMA memory\n"); 1285 goto fail; 1286 } 1287 1288 /* Allocate RX status area (16-byte aligned). */ 1289 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1290 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1291 if (error != 0) { 1292 aprint_error_dev(sc->sc_dev, 1293 "could not allocate RX status DMA memory\n"); 1294 goto fail; 1295 } 1296 1297 /* 1298 * Allocate and map RX buffers. 1299 */ 1300 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1301 struct iwn_rx_data *data = &ring->data[i]; 1302 1303 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1304 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1305 &data->map); 1306 if (error != 0) { 1307 aprint_error_dev(sc->sc_dev, 1308 "could not create RX buf DMA map\n"); 1309 goto fail; 1310 } 1311 1312 data->m = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1313 if (data->m == NULL) { 1314 aprint_error_dev(sc->sc_dev, 1315 "could not allocate RX mbuf\n"); 1316 error = ENOBUFS; 1317 goto fail; 1318 } 1319 1320 error = bus_dmamap_load(sc->sc_dmat, data->map, 1321 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1322 BUS_DMA_NOWAIT | BUS_DMA_READ); 1323 if (error != 0) { 1324 aprint_error_dev(sc->sc_dev, 1325 "can't not map mbuf (error %d)\n", error); 1326 goto fail; 1327 } 1328 1329 /* Set physical address of RX buffer (256-byte aligned). */ 1330 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1331 } 1332 1333 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1334 BUS_DMASYNC_PREWRITE); 1335 1336 return 0; 1337 1338 fail: iwn_free_rx_ring(sc, ring); 1339 return error; 1340 } 1341 1342 static void 1343 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1344 { 1345 int ntries; 1346 1347 if (iwn_nic_lock(sc) == 0) { 1348 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1349 for (ntries = 0; ntries < 1000; ntries++) { 1350 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1351 IWN_FH_RX_STATUS_IDLE) 1352 break; 1353 DELAY(10); 1354 } 1355 iwn_nic_unlock(sc); 1356 } 1357 ring->cur = 0; 1358 sc->last_rx_valid = 0; 1359 } 1360 1361 static void 1362 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1363 { 1364 int i; 1365 1366 iwn_dma_contig_free(&ring->desc_dma); 1367 iwn_dma_contig_free(&ring->stat_dma); 1368 1369 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1370 struct iwn_rx_data *data = &ring->data[i]; 1371 1372 if (data->m != NULL) { 1373 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1374 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1375 bus_dmamap_unload(sc->sc_dmat, data->map); 1376 m_freem(data->m); 1377 } 1378 if (data->map != NULL) 1379 bus_dmamap_destroy(sc->sc_dmat, data->map); 1380 } 1381 } 1382 1383 static int 1384 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1385 { 1386 bus_addr_t paddr; 1387 bus_size_t size; 1388 int i, error; 1389 1390 ring->qid = qid; 1391 ring->queued = 0; 1392 ring->cur = 0; 1393 1394 /* Allocate TX descriptors (256-byte aligned). */ 1395 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1396 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1397 (void **)&ring->desc, size, 256); 1398 if (error != 0) { 1399 aprint_error_dev(sc->sc_dev, 1400 "could not allocate TX ring DMA memory\n"); 1401 goto fail; 1402 } 1403 /* 1404 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need 1405 * to allocate commands space for other rings. 1406 * XXX Do we really need to allocate descriptors for other rings? 1407 */ 1408 if (qid > 4) 1409 return 0; 1410 1411 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1412 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1413 (void **)&ring->cmd, size, 4); 1414 if (error != 0) { 1415 aprint_error_dev(sc->sc_dev, 1416 "could not allocate TX cmd DMA memory\n"); 1417 goto fail; 1418 } 1419 1420 paddr = ring->cmd_dma.paddr; 1421 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1422 struct iwn_tx_data *data = &ring->data[i]; 1423 1424 data->cmd_paddr = paddr; 1425 data->scratch_paddr = paddr + 12; 1426 paddr += sizeof (struct iwn_tx_cmd); 1427 1428 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1429 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1430 &data->map); 1431 if (error != 0) { 1432 aprint_error_dev(sc->sc_dev, 1433 "could not create TX buf DMA map\n"); 1434 goto fail; 1435 } 1436 } 1437 return 0; 1438 1439 fail: iwn_free_tx_ring(sc, ring); 1440 return error; 1441 } 1442 1443 static void 1444 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1445 { 1446 int i; 1447 1448 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1449 struct iwn_tx_data *data = &ring->data[i]; 1450 1451 if (data->m != NULL) { 1452 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1453 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1454 bus_dmamap_unload(sc->sc_dmat, data->map); 1455 m_freem(data->m); 1456 data->m = NULL; 1457 } 1458 } 1459 /* Clear TX descriptors. */ 1460 memset(ring->desc, 0, ring->desc_dma.size); 1461 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1462 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1463 sc->qfullmsk &= ~(1 << ring->qid); 1464 ring->queued = 0; 1465 ring->cur = 0; 1466 } 1467 1468 static void 1469 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1470 { 1471 int i; 1472 1473 iwn_dma_contig_free(&ring->desc_dma); 1474 iwn_dma_contig_free(&ring->cmd_dma); 1475 1476 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1477 struct iwn_tx_data *data = &ring->data[i]; 1478 1479 if (data->m != NULL) { 1480 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1481 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1482 bus_dmamap_unload(sc->sc_dmat, data->map); 1483 m_freem(data->m); 1484 } 1485 if (data->map != NULL) 1486 bus_dmamap_destroy(sc->sc_dmat, data->map); 1487 } 1488 } 1489 1490 static void 1491 iwn5000_ict_reset(struct iwn_softc *sc) 1492 { 1493 /* Disable interrupts. */ 1494 IWN_WRITE(sc, IWN_INT_MASK, 0); 1495 1496 /* Reset ICT table. */ 1497 memset(sc->ict, 0, IWN_ICT_SIZE); 1498 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, IWN_ICT_SIZE, 1499 BUS_DMASYNC_PREWRITE); 1500 sc->ict_cur = 0; 1501 1502 /* Set physical address of ICT table (4KB aligned). */ 1503 DPRINTF(("enabling ICT\n")); 1504 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1505 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1506 1507 /* Enable periodic RX interrupt. */ 1508 sc->int_mask |= IWN_INT_RX_PERIODIC; 1509 /* Switch to ICT interrupt mode in driver. */ 1510 sc->sc_flags |= IWN_FLAG_USE_ICT; 1511 1512 /* Re-enable interrupts. */ 1513 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1514 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1515 } 1516 1517 static int 1518 iwn_read_eeprom(struct iwn_softc *sc) 1519 { 1520 struct iwn_ops *ops = &sc->ops; 1521 struct ieee80211com *ic = &sc->sc_ic; 1522 uint16_t val; 1523 int error; 1524 1525 /* Check whether adapter has an EEPROM or an OTPROM. */ 1526 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1527 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1528 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1529 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1530 "OTPROM" : "EEPROM")); 1531 1532 /* Adapter has to be powered on for EEPROM access to work. */ 1533 if ((error = iwn_apm_init(sc)) != 0) { 1534 aprint_error_dev(sc->sc_dev, 1535 "could not power ON adapter\n"); 1536 return error; 1537 } 1538 1539 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1540 aprint_error_dev(sc->sc_dev, 1541 "bad ROM signature\n"); 1542 return EIO; 1543 } 1544 if ((error = iwn_eeprom_lock(sc)) != 0) { 1545 aprint_error_dev(sc->sc_dev, 1546 "could not lock ROM (error=%d)\n", error); 1547 return error; 1548 } 1549 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1550 if ((error = iwn_init_otprom(sc)) != 0) { 1551 aprint_error_dev(sc->sc_dev, 1552 "could not initialize OTPROM\n"); 1553 return error; 1554 } 1555 } 1556 1557 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1558 DPRINTF(("SKU capabilities=0x%04x\n", le16toh(val))); 1559 /* Check if HT support is bonded out. */ 1560 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1561 sc->sc_flags |= IWN_FLAG_HAS_11N; 1562 1563 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1564 sc->rfcfg = le16toh(val); 1565 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1566 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1567 if (sc->txchainmask == 0) 1568 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1569 if (sc->rxchainmask == 0) 1570 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1571 1572 /* Read MAC address. */ 1573 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1574 1575 /* Read adapter-specific information from EEPROM. */ 1576 ops->read_eeprom(sc); 1577 1578 iwn_apm_stop(sc); /* Power OFF adapter. */ 1579 1580 iwn_eeprom_unlock(sc); 1581 return 0; 1582 } 1583 1584 static void 1585 iwn4965_read_eeprom(struct iwn_softc *sc) 1586 { 1587 uint32_t addr; 1588 uint16_t val; 1589 int i; 1590 1591 /* Read regulatory domain (4 ASCII characters). */ 1592 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1593 1594 /* Read the list of authorized channels (20MHz ones only). */ 1595 for (i = 0; i < 5; i++) { 1596 addr = iwn4965_regulatory_bands[i]; 1597 iwn_read_eeprom_channels(sc, i, addr); 1598 } 1599 1600 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1601 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1602 sc->maxpwr2GHz = val & 0xff; 1603 sc->maxpwr5GHz = val >> 8; 1604 /* Check that EEPROM values are within valid range. */ 1605 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1606 sc->maxpwr5GHz = 38; 1607 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1608 sc->maxpwr2GHz = 38; 1609 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1610 1611 /* Read samples for each TX power group. */ 1612 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1613 sizeof sc->bands); 1614 1615 /* Read voltage at which samples were taken. */ 1616 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1617 sc->eeprom_voltage = (int16_t)le16toh(val); 1618 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1619 1620 #ifdef IWN_DEBUG 1621 /* Print samples. */ 1622 if (iwn_debug > 0) { 1623 for (i = 0; i < IWN_NBANDS; i++) 1624 iwn4965_print_power_group(sc, i); 1625 } 1626 #endif 1627 } 1628 1629 #ifdef IWN_DEBUG 1630 static void 1631 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1632 { 1633 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1634 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1635 int j, c; 1636 1637 aprint_normal("===band %d===\n", i); 1638 aprint_normal("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1639 aprint_normal("chan1 num=%d\n", chans[0].num); 1640 for (c = 0; c < 2; c++) { 1641 for (j = 0; j < IWN_NSAMPLES; j++) { 1642 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1643 "power=%d pa_det=%d\n", c, j, 1644 chans[0].samples[c][j].temp, 1645 chans[0].samples[c][j].gain, 1646 chans[0].samples[c][j].power, 1647 chans[0].samples[c][j].pa_det); 1648 } 1649 } 1650 aprint_normal("chan2 num=%d\n", chans[1].num); 1651 for (c = 0; c < 2; c++) { 1652 for (j = 0; j < IWN_NSAMPLES; j++) { 1653 aprint_normal("chain %d, sample %d: temp=%d gain=%d " 1654 "power=%d pa_det=%d\n", c, j, 1655 chans[1].samples[c][j].temp, 1656 chans[1].samples[c][j].gain, 1657 chans[1].samples[c][j].power, 1658 chans[1].samples[c][j].pa_det); 1659 } 1660 } 1661 } 1662 #endif 1663 1664 static void 1665 iwn5000_read_eeprom(struct iwn_softc *sc) 1666 { 1667 struct iwn5000_eeprom_calib_hdr hdr; 1668 int32_t volt; 1669 uint32_t base, addr; 1670 uint16_t val; 1671 int i; 1672 1673 /* Read regulatory domain (4 ASCII characters). */ 1674 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1675 base = le16toh(val); 1676 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1677 sc->eeprom_domain, 4); 1678 1679 /* Read the list of authorized channels (20MHz ones only). */ 1680 for (i = 0; i < 5; i++) { 1681 addr = base + iwn5000_regulatory_bands[i]; 1682 iwn_read_eeprom_channels(sc, i, addr); 1683 } 1684 1685 /* Read enhanced TX power information for 6000 Series. */ 1686 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1687 iwn_read_eeprom_enhinfo(sc); 1688 1689 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1690 base = le16toh(val); 1691 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1692 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1693 hdr.version, hdr.pa_type, le16toh(hdr.volt))); 1694 sc->calib_ver = hdr.version; 1695 1696 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1697 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1698 sc->hw_type == IWN_HW_REV_TYPE_135 || 1699 sc->hw_type == IWN_HW_REV_TYPE_105) { 1700 sc->eeprom_voltage = le16toh(hdr.volt); 1701 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1702 sc->eeprom_temp = le16toh(val); 1703 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1704 sc->eeprom_rawtemp = le16toh(val); 1705 } 1706 1707 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1708 /* Compute temperature offset. */ 1709 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1710 sc->eeprom_temp = le16toh(val); 1711 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1712 volt = le16toh(val); 1713 sc->temp_off = sc->eeprom_temp - (volt / -5); 1714 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1715 sc->eeprom_temp, volt, sc->temp_off)); 1716 } else { 1717 /* Read crystal calibration. */ 1718 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1719 &sc->eeprom_crystal, sizeof (uint32_t)); 1720 DPRINTF(("crystal calibration 0x%08x\n", 1721 le32toh(sc->eeprom_crystal))); 1722 } 1723 } 1724 1725 static void 1726 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1727 { 1728 struct ieee80211com *ic = &sc->sc_ic; 1729 const struct iwn_chan_band *band = &iwn_bands[n]; 1730 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1731 uint8_t chan; 1732 int i; 1733 1734 iwn_read_prom_data(sc, addr, channels, 1735 band->nchan * sizeof (struct iwn_eeprom_chan)); 1736 1737 for (i = 0; i < band->nchan; i++) { 1738 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1739 continue; 1740 1741 chan = band->chan[i]; 1742 1743 if (n == 0) { /* 2GHz band */ 1744 ic->ic_channels[chan].ic_freq = 1745 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1746 ic->ic_channels[chan].ic_flags = 1747 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1748 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1749 1750 } else { /* 5GHz band */ 1751 /* 1752 * Some adapters support channels 7, 8, 11 and 12 1753 * both in the 2GHz and 4.9GHz bands. 1754 * Because of limitations in our net80211 layer, 1755 * we don't support them in the 4.9GHz band. 1756 */ 1757 if (chan <= 14) 1758 continue; 1759 1760 ic->ic_channels[chan].ic_freq = 1761 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1762 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1763 /* We have at least one valid 5GHz channel. */ 1764 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1765 } 1766 1767 /* Is active scan allowed on this channel? */ 1768 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1769 ic->ic_channels[chan].ic_flags |= 1770 IEEE80211_CHAN_PASSIVE; 1771 } 1772 1773 /* Save maximum allowed TX power for this channel. */ 1774 sc->maxpwr[chan] = channels[i].maxpwr; 1775 1776 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1777 chan, channels[i].flags, sc->maxpwr[chan])); 1778 } 1779 } 1780 1781 static void 1782 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1783 { 1784 struct iwn_eeprom_enhinfo enhinfo[35]; 1785 uint16_t val, base; 1786 int8_t maxpwr; 1787 uint8_t flags; 1788 int i; 1789 1790 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1791 base = le16toh(val); 1792 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1793 enhinfo, sizeof enhinfo); 1794 1795 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1796 for (i = 0; i < __arraycount(enhinfo); i++) { 1797 flags = enhinfo[i].flags; 1798 if (!(flags & IWN_ENHINFO_VALID)) 1799 continue; /* Skip invalid entries. */ 1800 1801 maxpwr = 0; 1802 if (sc->txchainmask & IWN_ANT_A) 1803 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1804 if (sc->txchainmask & IWN_ANT_B) 1805 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1806 if (sc->txchainmask & IWN_ANT_C) 1807 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1808 if (sc->ntxchains == 2) 1809 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1810 else if (sc->ntxchains == 3) 1811 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1812 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1813 1814 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1815 sc->enh_maxpwr[i] = maxpwr; 1816 } 1817 } 1818 1819 static struct ieee80211_node * 1820 iwn_node_alloc(struct ieee80211_node_table *ic __unused) 1821 { 1822 return malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1823 } 1824 1825 static void 1826 iwn_newassoc(struct ieee80211_node *ni, int isnew) 1827 { 1828 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 1829 struct iwn_node *wn = (void *)ni; 1830 uint8_t rate; 1831 int ridx, i; 1832 1833 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1834 /* Start at lowest available bit-rate, AMRR will raise. */ 1835 ni->ni_txrate = 0; 1836 1837 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1838 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1839 /* Map 802.11 rate to HW rate index. */ 1840 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1841 if (iwn_rates[ridx].rate == rate) 1842 break; 1843 wn->ridx[i] = ridx; 1844 } 1845 } 1846 1847 static int 1848 iwn_media_change(struct ifnet *ifp) 1849 { 1850 struct iwn_softc *sc = ifp->if_softc; 1851 struct ieee80211com *ic = &sc->sc_ic; 1852 uint8_t rate, ridx; 1853 int error; 1854 1855 error = ieee80211_media_change(ifp); 1856 if (error != ENETRESET) 1857 return error; 1858 1859 if (ic->ic_fixed_rate != -1) { 1860 rate = ic->ic_sup_rates[ic->ic_curmode]. 1861 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1862 /* Map 802.11 rate to HW rate index. */ 1863 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1864 if (iwn_rates[ridx].rate == rate) 1865 break; 1866 sc->fixed_ridx = ridx; 1867 } 1868 1869 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1870 (IFF_UP | IFF_RUNNING)) { 1871 iwn_stop(ifp, 0); 1872 error = iwn_init(ifp); 1873 } 1874 return error; 1875 } 1876 1877 static int 1878 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1879 { 1880 struct ifnet *ifp = ic->ic_ifp; 1881 struct iwn_softc *sc = ifp->if_softc; 1882 int error; 1883 1884 callout_stop(&sc->calib_to); 1885 1886 switch (nstate) { 1887 case IEEE80211_S_SCAN: 1888 /* XXX Do not abort a running scan. */ 1889 if (sc->sc_flags & IWN_FLAG_SCANNING) { 1890 if (ic->ic_state != nstate) 1891 aprint_debug_dev(sc->sc_dev, "scan request(%d) " 1892 "while scanning(%d) ignored\n", nstate, 1893 ic->ic_state); 1894 break; 1895 } 1896 1897 /* XXX Not sure if call and flags are needed. */ 1898 ieee80211_node_table_reset(&ic->ic_scan); 1899 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 1900 sc->sc_flags |= IWN_FLAG_SCANNING_2GHZ; 1901 1902 /* Make the link LED blink while we're scanning. */ 1903 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1904 1905 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ)) != 0) { 1906 aprint_error_dev(sc->sc_dev, 1907 "could not initiate scan\n"); 1908 return error; 1909 } 1910 ic->ic_state = nstate; 1911 return 0; 1912 1913 case IEEE80211_S_ASSOC: 1914 if (ic->ic_state != IEEE80211_S_RUN) 1915 break; 1916 /* FALLTHROUGH */ 1917 case IEEE80211_S_AUTH: 1918 /* Reset state to handle reassociations correctly. */ 1919 sc->rxon.associd = 0; 1920 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1921 sc->calib.state = IWN_CALIB_STATE_INIT; 1922 1923 /* Wait until we hear a beacon before we transmit */ 1924 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 1925 sc->sc_beacon_wait = 1; 1926 1927 if ((error = iwn_auth(sc)) != 0) { 1928 aprint_error_dev(sc->sc_dev, 1929 "could not move to auth state\n"); 1930 return error; 1931 } 1932 break; 1933 1934 case IEEE80211_S_RUN: 1935 /* 1936 * RUN -> RUN transition; Just restart timers. 1937 */ 1938 if (ic->ic_state == IEEE80211_S_RUN) { 1939 sc->calib_cnt = 0; 1940 break; 1941 } 1942 1943 /* Wait until we hear a beacon before we transmit */ 1944 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 1945 sc->sc_beacon_wait = 1; 1946 1947 if ((error = iwn_run(sc)) != 0) { 1948 aprint_error_dev(sc->sc_dev, 1949 "could not move to run state\n"); 1950 return error; 1951 } 1952 break; 1953 1954 case IEEE80211_S_INIT: 1955 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1956 sc->calib.state = IWN_CALIB_STATE_INIT; 1957 /* 1958 * Purge the xmit queue so we don't have old frames 1959 * during a new association attempt. 1960 */ 1961 sc->sc_beacon_wait = 0; 1962 ifp->if_flags &= ~IFF_OACTIVE; 1963 iwn_start(ifp); 1964 break; 1965 } 1966 1967 return sc->sc_newstate(ic, nstate, arg); 1968 } 1969 1970 static void 1971 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1972 { 1973 struct iwn_softc *sc = arg; 1974 struct iwn_node *wn = (struct iwn_node *)ni; 1975 1976 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1977 } 1978 1979 static void 1980 iwn_calib_timeout(void *arg) 1981 { 1982 struct iwn_softc *sc = arg; 1983 struct ieee80211com *ic = &sc->sc_ic; 1984 int s; 1985 1986 s = splnet(); 1987 if (ic->ic_fixed_rate == -1) { 1988 if (ic->ic_opmode == IEEE80211_M_STA) 1989 iwn_iter_func(sc, ic->ic_bss); 1990 else 1991 ieee80211_iterate_nodes(&ic->ic_sta, iwn_iter_func, sc); 1992 } 1993 /* Force automatic TX power calibration every 60 secs. */ 1994 if (++sc->calib_cnt >= 120) { 1995 uint32_t flags = 0; 1996 1997 DPRINTF(("sending request for statistics\n")); 1998 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1999 sizeof flags, 1); 2000 sc->calib_cnt = 0; 2001 } 2002 splx(s); 2003 2004 /* Automatic rate control triggered every 500ms. */ 2005 callout_schedule(&sc->calib_to, mstohz(500)); 2006 } 2007 2008 /* 2009 * Process an RX_PHY firmware notification. This is usually immediately 2010 * followed by an MPDU_RX_DONE notification. 2011 */ 2012 static void 2013 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2014 struct iwn_rx_data *data) 2015 { 2016 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2017 2018 DPRINTFN(2, ("received PHY stats\n")); 2019 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2020 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2021 2022 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2023 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2024 sc->last_rx_valid = 1; 2025 } 2026 2027 /* 2028 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2029 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2030 */ 2031 static void 2032 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2033 struct iwn_rx_data *data) 2034 { 2035 struct iwn_ops *ops = &sc->ops; 2036 struct ieee80211com *ic = &sc->sc_ic; 2037 struct ifnet *ifp = ic->ic_ifp; 2038 struct iwn_rx_ring *ring = &sc->rxq; 2039 struct ieee80211_frame *wh; 2040 struct ieee80211_node *ni; 2041 struct mbuf *m, *m1; 2042 struct iwn_rx_stat *stat; 2043 char *head; 2044 uint32_t flags; 2045 int error, len, rssi, s; 2046 2047 if (desc->type == IWN_MPDU_RX_DONE) { 2048 /* Check for prior RX_PHY notification. */ 2049 if (!sc->last_rx_valid) { 2050 DPRINTF(("missing RX_PHY\n")); 2051 return; 2052 } 2053 sc->last_rx_valid = 0; 2054 stat = &sc->last_rx_stat; 2055 } else 2056 stat = (struct iwn_rx_stat *)(desc + 1); 2057 2058 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2059 BUS_DMASYNC_POSTREAD); 2060 2061 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2062 aprint_error_dev(sc->sc_dev, 2063 "invalid RX statistic header\n"); 2064 return; 2065 } 2066 if (desc->type == IWN_MPDU_RX_DONE) { 2067 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2068 head = (char *)(mpdu + 1); 2069 len = le16toh(mpdu->len); 2070 } else { 2071 head = (char *)(stat + 1) + stat->cfg_phy_len; 2072 len = le16toh(stat->len); 2073 } 2074 2075 flags = le32toh(*(uint32_t *)(head + len)); 2076 2077 /* Discard frames with a bad FCS early. */ 2078 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2079 DPRINTFN(2, ("RX flags error %x\n", flags)); 2080 ifp->if_ierrors++; 2081 return; 2082 } 2083 /* Discard frames that are too short. */ 2084 if (len < sizeof (*wh)) { 2085 DPRINTF(("frame too short: %d\n", len)); 2086 ic->ic_stats.is_rx_tooshort++; 2087 ifp->if_ierrors++; 2088 return; 2089 } 2090 2091 m1 = MCLGETIalt(sc, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2092 if (m1 == NULL) { 2093 ic->ic_stats.is_rx_nobuf++; 2094 ifp->if_ierrors++; 2095 return; 2096 } 2097 bus_dmamap_unload(sc->sc_dmat, data->map); 2098 2099 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2100 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2101 if (error != 0) { 2102 m_freem(m1); 2103 2104 /* Try to reload the old mbuf. */ 2105 error = bus_dmamap_load(sc->sc_dmat, data->map, 2106 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2107 BUS_DMA_NOWAIT | BUS_DMA_READ); 2108 if (error != 0) { 2109 panic("%s: could not load old RX mbuf", 2110 device_xname(sc->sc_dev)); 2111 } 2112 /* Physical address may have changed. */ 2113 ring->desc[ring->cur] = 2114 htole32(data->map->dm_segs[0].ds_addr >> 8); 2115 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2116 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2117 BUS_DMASYNC_PREWRITE); 2118 ifp->if_ierrors++; 2119 return; 2120 } 2121 2122 m = data->m; 2123 data->m = m1; 2124 /* Update RX descriptor. */ 2125 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2126 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2127 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2128 BUS_DMASYNC_PREWRITE); 2129 2130 /* Finalize mbuf. */ 2131 m_set_rcvif(m, ifp); 2132 m->m_data = head; 2133 m->m_pkthdr.len = m->m_len = len; 2134 2135 s = splnet(); 2136 2137 /* Grab a reference to the source node. */ 2138 wh = mtod(m, struct ieee80211_frame *); 2139 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2140 2141 /* XXX OpenBSD adds decryption here (see also comments in iwn_tx). */ 2142 /* NetBSD does decryption in ieee80211_input. */ 2143 2144 rssi = ops->get_rssi(stat); 2145 2146 /* XXX Added for NetBSD: scans never stop without it */ 2147 if (ic->ic_state == IEEE80211_S_SCAN) 2148 iwn_fix_channel(ic, m, stat); 2149 2150 if (sc->sc_drvbpf != NULL) { 2151 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2152 2153 tap->wr_flags = 0; 2154 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2155 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2156 tap->wr_chan_freq = 2157 htole16(ic->ic_channels[stat->chan].ic_freq); 2158 tap->wr_chan_flags = 2159 htole16(ic->ic_channels[stat->chan].ic_flags); 2160 tap->wr_dbm_antsignal = (int8_t)rssi; 2161 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2162 tap->wr_tsft = stat->tstamp; 2163 switch (stat->rate) { 2164 /* CCK rates. */ 2165 case 10: tap->wr_rate = 2; break; 2166 case 20: tap->wr_rate = 4; break; 2167 case 55: tap->wr_rate = 11; break; 2168 case 110: tap->wr_rate = 22; break; 2169 /* OFDM rates. */ 2170 case 0xd: tap->wr_rate = 12; break; 2171 case 0xf: tap->wr_rate = 18; break; 2172 case 0x5: tap->wr_rate = 24; break; 2173 case 0x7: tap->wr_rate = 36; break; 2174 case 0x9: tap->wr_rate = 48; break; 2175 case 0xb: tap->wr_rate = 72; break; 2176 case 0x1: tap->wr_rate = 96; break; 2177 case 0x3: tap->wr_rate = 108; break; 2178 /* Unknown rate: should not happen. */ 2179 default: tap->wr_rate = 0; 2180 } 2181 2182 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2183 } 2184 2185 /* 2186 * If it's a beacon and we're waiting, then do the wakeup. 2187 */ 2188 if (sc->sc_beacon_wait) { 2189 uint8_t type, subtype; 2190 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2191 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2192 /* 2193 * This assumes at this point we've received our own 2194 * beacon. 2195 */ 2196 if (type == IEEE80211_FC0_TYPE_MGT && 2197 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 2198 sc->sc_beacon_wait = 0; 2199 ifp->if_flags &= ~IFF_OACTIVE; 2200 iwn_start(ifp); 2201 } 2202 } 2203 2204 /* Send the frame to the 802.11 layer. */ 2205 ieee80211_input(ic, m, ni, rssi, 0); 2206 2207 /* Node is no longer needed. */ 2208 ieee80211_free_node(ni); 2209 2210 splx(s); 2211 } 2212 2213 #ifndef IEEE80211_NO_HT 2214 /* Process an incoming Compressed BlockAck. */ 2215 static void 2216 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2217 struct iwn_rx_data *data) 2218 { 2219 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2220 struct iwn_tx_ring *txq; 2221 2222 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*ba), 2223 BUS_DMASYNC_POSTREAD); 2224 2225 txq = &sc->txq[le16toh(ba->qid)]; 2226 /* XXX TBD */ 2227 } 2228 #endif 2229 2230 /* 2231 * Process a CALIBRATION_RESULT notification sent by the initialization 2232 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2233 */ 2234 static void 2235 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2236 struct iwn_rx_data *data) 2237 { 2238 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2239 int len, idx = -1; 2240 2241 /* Runtime firmware should not send such a notification. */ 2242 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2243 return; 2244 2245 len = (le32toh(desc->len) & 0x3fff) - 4; 2246 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2247 BUS_DMASYNC_POSTREAD); 2248 2249 switch (calib->code) { 2250 case IWN5000_PHY_CALIB_DC: 2251 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2252 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2253 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2254 sc->hw_type == IWN_HW_REV_TYPE_135 || 2255 sc->hw_type == IWN_HW_REV_TYPE_105) 2256 idx = 0; 2257 break; 2258 case IWN5000_PHY_CALIB_LO: 2259 idx = 1; 2260 break; 2261 case IWN5000_PHY_CALIB_TX_IQ: 2262 idx = 2; 2263 break; 2264 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2265 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2266 sc->hw_type != IWN_HW_REV_TYPE_5150) 2267 idx = 3; 2268 break; 2269 case IWN5000_PHY_CALIB_BASE_BAND: 2270 idx = 4; 2271 break; 2272 } 2273 if (idx == -1) /* Ignore other results. */ 2274 return; 2275 2276 /* Save calibration result. */ 2277 if (sc->calibcmd[idx].buf != NULL) 2278 free(sc->calibcmd[idx].buf, M_DEVBUF); 2279 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2280 if (sc->calibcmd[idx].buf == NULL) { 2281 DPRINTF(("not enough memory for calibration result %d\n", 2282 calib->code)); 2283 return; 2284 } 2285 DPRINTF(("saving calibration result code=%d len=%d\n", 2286 calib->code, len)); 2287 sc->calibcmd[idx].len = len; 2288 memcpy(sc->calibcmd[idx].buf, calib, len); 2289 } 2290 2291 /* 2292 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2293 * The latter is sent by the firmware after each received beacon. 2294 */ 2295 static void 2296 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2297 struct iwn_rx_data *data) 2298 { 2299 struct iwn_ops *ops = &sc->ops; 2300 struct ieee80211com *ic = &sc->sc_ic; 2301 struct iwn_calib_state *calib = &sc->calib; 2302 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2303 int temp; 2304 2305 /* Ignore statistics received during a scan. */ 2306 if (ic->ic_state != IEEE80211_S_RUN) 2307 return; 2308 2309 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2310 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2311 2312 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2313 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2314 2315 /* Test if temperature has changed. */ 2316 if (stats->general.temp != sc->rawtemp) { 2317 /* Convert "raw" temperature to degC. */ 2318 sc->rawtemp = stats->general.temp; 2319 temp = ops->get_temperature(sc); 2320 DPRINTFN(2, ("temperature=%dC\n", temp)); 2321 2322 /* Update TX power if need be (4965AGN only). */ 2323 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2324 iwn4965_power_calibration(sc, temp); 2325 } 2326 2327 if (desc->type != IWN_BEACON_STATISTICS) 2328 return; /* Reply to a statistics request. */ 2329 2330 sc->noise = iwn_get_noise(&stats->rx.general); 2331 2332 /* Test that RSSI and noise are present in stats report. */ 2333 if (le32toh(stats->rx.general.flags) != 1) { 2334 DPRINTF(("received statistics without RSSI\n")); 2335 return; 2336 } 2337 2338 /* 2339 * XXX Differential gain calibration makes the 6005 firmware 2340 * crap out, so skip it for now. This effectively disables 2341 * sensitivity tuning as well. 2342 */ 2343 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2344 return; 2345 2346 if (calib->state == IWN_CALIB_STATE_ASSOC) 2347 iwn_collect_noise(sc, &stats->rx.general); 2348 else if (calib->state == IWN_CALIB_STATE_RUN) 2349 iwn_tune_sensitivity(sc, &stats->rx); 2350 } 2351 2352 /* 2353 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2354 * and 5000 adapters have different incompatible TX status formats. 2355 */ 2356 static void 2357 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2358 struct iwn_rx_data *data) 2359 { 2360 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2361 2362 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2363 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2364 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff); 2365 } 2366 2367 static void 2368 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2369 struct iwn_rx_data *data) 2370 { 2371 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2372 2373 #ifdef notyet 2374 /* Reset TX scheduler slot. */ 2375 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2376 #endif 2377 2378 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2379 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2380 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff); 2381 } 2382 2383 /* 2384 * Adapter-independent backend for TX_DONE firmware notifications. 2385 */ 2386 static void 2387 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2388 uint8_t status) 2389 { 2390 struct ieee80211com *ic = &sc->sc_ic; 2391 struct ifnet *ifp = ic->ic_ifp; 2392 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2393 struct iwn_tx_data *data = &ring->data[desc->idx]; 2394 struct iwn_node *wn = (struct iwn_node *)data->ni; 2395 int s; 2396 2397 s = splnet(); 2398 2399 /* Update rate control statistics. */ 2400 wn->amn.amn_txcnt++; 2401 if (ackfailcnt > 0) 2402 wn->amn.amn_retrycnt++; 2403 2404 if (status != 1 && status != 2) 2405 ifp->if_oerrors++; 2406 else 2407 ifp->if_opackets++; 2408 2409 /* Unmap and free mbuf. */ 2410 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2411 BUS_DMASYNC_POSTWRITE); 2412 bus_dmamap_unload(sc->sc_dmat, data->map); 2413 m_freem(data->m); 2414 data->m = NULL; 2415 ieee80211_free_node(data->ni); 2416 data->ni = NULL; 2417 2418 sc->sc_tx_timer = 0; 2419 if (--ring->queued < IWN_TX_RING_LOMARK) { 2420 sc->qfullmsk &= ~(1 << ring->qid); 2421 if (sc->qfullmsk == 0 && (ifp->if_flags & IFF_OACTIVE)) { 2422 ifp->if_flags &= ~IFF_OACTIVE; 2423 iwn_start(ifp); 2424 } 2425 } 2426 2427 splx(s); 2428 } 2429 2430 /* 2431 * Process a "command done" firmware notification. This is where we wakeup 2432 * processes waiting for a synchronous command completion. 2433 */ 2434 static void 2435 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2436 { 2437 struct iwn_tx_ring *ring = &sc->txq[4]; 2438 struct iwn_tx_data *data; 2439 2440 if ((desc->qid & 0xf) != 4) 2441 return; /* Not a command ack. */ 2442 2443 data = &ring->data[desc->idx]; 2444 2445 /* If the command was mapped in an mbuf, free it. */ 2446 if (data->m != NULL) { 2447 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2448 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2449 bus_dmamap_unload(sc->sc_dmat, data->map); 2450 m_freem(data->m); 2451 data->m = NULL; 2452 } 2453 wakeup(&ring->desc[desc->idx]); 2454 } 2455 2456 /* 2457 * Process an INT_FH_RX or INT_SW_RX interrupt. 2458 */ 2459 static void 2460 iwn_notif_intr(struct iwn_softc *sc) 2461 { 2462 struct iwn_ops *ops = &sc->ops; 2463 struct ieee80211com *ic = &sc->sc_ic; 2464 struct ifnet *ifp = ic->ic_ifp; 2465 uint16_t hw; 2466 int s; 2467 2468 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2469 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2470 2471 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2472 while (sc->rxq.cur != hw) { 2473 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2474 struct iwn_rx_desc *desc; 2475 2476 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2477 BUS_DMASYNC_POSTREAD); 2478 desc = mtod(data->m, struct iwn_rx_desc *); 2479 2480 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2481 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2482 2483 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2484 iwn_cmd_done(sc, desc); 2485 2486 switch (desc->type) { 2487 case IWN_RX_PHY: 2488 iwn_rx_phy(sc, desc, data); 2489 break; 2490 2491 case IWN_RX_DONE: /* 4965AGN only. */ 2492 case IWN_MPDU_RX_DONE: 2493 /* An 802.11 frame has been received. */ 2494 iwn_rx_done(sc, desc, data); 2495 break; 2496 #ifndef IEEE80211_NO_HT 2497 case IWN_RX_COMPRESSED_BA: 2498 /* A Compressed BlockAck has been received. */ 2499 iwn_rx_compressed_ba(sc, desc, data); 2500 break; 2501 #endif 2502 case IWN_TX_DONE: 2503 /* An 802.11 frame has been transmitted. */ 2504 ops->tx_done(sc, desc, data); 2505 break; 2506 2507 case IWN_RX_STATISTICS: 2508 case IWN_BEACON_STATISTICS: 2509 iwn_rx_statistics(sc, desc, data); 2510 break; 2511 2512 case IWN_BEACON_MISSED: 2513 { 2514 struct iwn_beacon_missed *miss = 2515 (struct iwn_beacon_missed *)(desc + 1); 2516 2517 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2518 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2519 /* 2520 * If more than 5 consecutive beacons are missed, 2521 * reinitialize the sensitivity state machine. 2522 */ 2523 DPRINTF(("beacons missed %d/%d\n", 2524 le32toh(miss->consecutive), le32toh(miss->total))); 2525 if (ic->ic_state == IEEE80211_S_RUN && 2526 le32toh(miss->consecutive) > 5) 2527 (void)iwn_init_sensitivity(sc); 2528 break; 2529 } 2530 case IWN_UC_READY: 2531 { 2532 struct iwn_ucode_info *uc = 2533 (struct iwn_ucode_info *)(desc + 1); 2534 2535 /* The microcontroller is ready. */ 2536 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2537 sizeof (*uc), BUS_DMASYNC_POSTREAD); 2538 DPRINTF(("microcode alive notification version=%d.%d " 2539 "subtype=%x alive=%x\n", uc->major, uc->minor, 2540 uc->subtype, le32toh(uc->valid))); 2541 2542 if (le32toh(uc->valid) != 1) { 2543 aprint_error_dev(sc->sc_dev, 2544 "microcontroller initialization " 2545 "failed\n"); 2546 break; 2547 } 2548 if (uc->subtype == IWN_UCODE_INIT) { 2549 /* Save microcontroller report. */ 2550 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 2551 } 2552 /* Save the address of the error log in SRAM. */ 2553 sc->errptr = le32toh(uc->errptr); 2554 break; 2555 } 2556 case IWN_STATE_CHANGED: 2557 { 2558 uint32_t *status = (uint32_t *)(desc + 1); 2559 2560 /* Enabled/disabled notification. */ 2561 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2562 sizeof (*status), BUS_DMASYNC_POSTREAD); 2563 DPRINTF(("state changed to %x\n", le32toh(*status))); 2564 2565 if (le32toh(*status) & 1) { 2566 /* The radio button has to be pushed. */ 2567 aprint_error_dev(sc->sc_dev, 2568 "Radio transmitter is off\n"); 2569 /* Turn the interface down. */ 2570 s = splnet(); 2571 ifp->if_flags &= ~IFF_UP; 2572 iwn_stop(ifp, 1); 2573 splx(s); 2574 return; /* No further processing. */ 2575 } 2576 break; 2577 } 2578 case IWN_START_SCAN: 2579 { 2580 struct iwn_start_scan *scan = 2581 (struct iwn_start_scan *)(desc + 1); 2582 2583 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2584 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2585 DPRINTFN(2, ("scanning channel %d status %x\n", 2586 scan->chan, le32toh(scan->status))); 2587 2588 /* Fix current channel. */ 2589 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 2590 break; 2591 } 2592 case IWN_STOP_SCAN: 2593 { 2594 struct iwn_stop_scan *scan = 2595 (struct iwn_stop_scan *)(desc + 1); 2596 2597 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2598 sizeof (*scan), BUS_DMASYNC_POSTREAD); 2599 DPRINTF(("scan finished nchan=%d status=%d chan=%d\n", 2600 scan->nchan, scan->status, scan->chan)); 2601 2602 if (scan->status == 1 && scan->chan <= 14 && 2603 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 2604 /* 2605 * We just finished scanning 2GHz channels, 2606 * start scanning 5GHz ones. 2607 */ 2608 sc->sc_flags &= ~IWN_FLAG_SCANNING_2GHZ; 2609 sc->sc_flags |= IWN_FLAG_SCANNING_5GHZ; 2610 if (iwn_scan(sc, IEEE80211_CHAN_5GHZ) == 0) 2611 break; 2612 } 2613 sc->sc_flags &= ~IWN_FLAG_SCANNING; 2614 ieee80211_end_scan(ic); 2615 break; 2616 } 2617 case IWN5000_CALIBRATION_RESULT: 2618 iwn5000_rx_calib_results(sc, desc, data); 2619 break; 2620 2621 case IWN5000_CALIBRATION_DONE: 2622 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 2623 wakeup(sc); 2624 break; 2625 } 2626 2627 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 2628 } 2629 2630 /* Tell the firmware what we have processed. */ 2631 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 2632 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 2633 } 2634 2635 /* 2636 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 2637 * from power-down sleep mode. 2638 */ 2639 static void 2640 iwn_wakeup_intr(struct iwn_softc *sc) 2641 { 2642 int qid; 2643 2644 DPRINTF(("ucode wakeup from power-down sleep\n")); 2645 2646 /* Wakeup RX and TX rings. */ 2647 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 2648 for (qid = 0; qid < sc->ntxqs; qid++) { 2649 struct iwn_tx_ring *ring = &sc->txq[qid]; 2650 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 2651 } 2652 } 2653 2654 /* 2655 * Dump the error log of the firmware when a firmware panic occurs. Although 2656 * we can't debug the firmware because it is neither open source nor free, it 2657 * can help us to identify certain classes of problems. 2658 */ 2659 static void 2660 iwn_fatal_intr(struct iwn_softc *sc) 2661 { 2662 struct iwn_fw_dump dump; 2663 int i; 2664 2665 /* Force a complete recalibration on next init. */ 2666 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 2667 2668 /* Check that the error log address is valid. */ 2669 if (sc->errptr < IWN_FW_DATA_BASE || 2670 sc->errptr + sizeof (dump) > 2671 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 2672 aprint_error_dev(sc->sc_dev, 2673 "bad firmware error log address 0x%08x\n", sc->errptr); 2674 return; 2675 } 2676 if (iwn_nic_lock(sc) != 0) { 2677 aprint_error_dev(sc->sc_dev, 2678 "could not read firmware error log\n"); 2679 return; 2680 } 2681 /* Read firmware error log from SRAM. */ 2682 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 2683 sizeof (dump) / sizeof (uint32_t)); 2684 iwn_nic_unlock(sc); 2685 2686 if (dump.valid == 0) { 2687 aprint_error_dev(sc->sc_dev, 2688 "firmware error log is empty\n"); 2689 return; 2690 } 2691 aprint_error("firmware error log:\n"); 2692 aprint_error(" error type = \"%s\" (0x%08X)\n", 2693 (dump.id < __arraycount(iwn_fw_errmsg)) ? 2694 iwn_fw_errmsg[dump.id] : "UNKNOWN", 2695 dump.id); 2696 aprint_error(" program counter = 0x%08X\n", dump.pc); 2697 aprint_error(" source line = 0x%08X\n", dump.src_line); 2698 aprint_error(" error data = 0x%08X%08X\n", 2699 dump.error_data[0], dump.error_data[1]); 2700 aprint_error(" branch link = 0x%08X%08X\n", 2701 dump.branch_link[0], dump.branch_link[1]); 2702 aprint_error(" interrupt link = 0x%08X%08X\n", 2703 dump.interrupt_link[0], dump.interrupt_link[1]); 2704 aprint_error(" time = %u\n", dump.time[0]); 2705 2706 /* Dump driver status (TX and RX rings) while we're here. */ 2707 aprint_error("driver status:\n"); 2708 for (i = 0; i < sc->ntxqs; i++) { 2709 struct iwn_tx_ring *ring = &sc->txq[i]; 2710 aprint_error(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 2711 i, ring->qid, ring->cur, ring->queued); 2712 } 2713 aprint_error(" rx ring: cur=%d\n", sc->rxq.cur); 2714 aprint_error(" 802.11 state %d\n", sc->sc_ic.ic_state); 2715 } 2716 2717 static int 2718 iwn_intr(void *arg) 2719 { 2720 struct iwn_softc *sc = arg; 2721 2722 /* Disable interrupts. */ 2723 IWN_WRITE(sc, IWN_INT_MASK, 0); 2724 2725 softint_schedule(sc->sc_soft_ih); 2726 return 1; 2727 } 2728 2729 static void 2730 iwn_softintr(void *arg) 2731 { 2732 struct iwn_softc *sc = arg; 2733 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2734 uint32_t r1, r2, tmp; 2735 int s; 2736 2737 /* Read interrupts from ICT (fast) or from registers (slow). */ 2738 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2739 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, 2740 IWN_ICT_SIZE, BUS_DMASYNC_POSTREAD); 2741 tmp = 0; 2742 while (sc->ict[sc->ict_cur] != 0) { 2743 tmp |= sc->ict[sc->ict_cur]; 2744 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 2745 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 2746 } 2747 bus_dmamap_sync(sc->sc_dmat, sc->ict_dma.map, 0, 2748 IWN_ICT_SIZE, BUS_DMASYNC_PREWRITE); 2749 tmp = le32toh(tmp); 2750 if (tmp == 0xffffffff) /* Shouldn't happen. */ 2751 tmp = 0; 2752 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 2753 tmp |= 0x8000; 2754 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 2755 r2 = 0; /* Unused. */ 2756 } else { 2757 r1 = IWN_READ(sc, IWN_INT); 2758 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 2759 return; /* Hardware gone! */ 2760 r2 = IWN_READ(sc, IWN_FH_INT); 2761 } 2762 if (r1 == 0 && r2 == 0) { 2763 goto out; /* Interrupt not for us. */ 2764 } 2765 2766 /* Acknowledge interrupts. */ 2767 IWN_WRITE(sc, IWN_INT, r1); 2768 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 2769 IWN_WRITE(sc, IWN_FH_INT, r2); 2770 2771 if (r1 & IWN_INT_RF_TOGGLED) { 2772 tmp = IWN_READ(sc, IWN_GP_CNTRL); 2773 aprint_error_dev(sc->sc_dev, 2774 "RF switch: radio %s\n", 2775 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 2776 } 2777 if (r1 & IWN_INT_CT_REACHED) { 2778 aprint_error_dev(sc->sc_dev, 2779 "critical temperature reached!\n"); 2780 } 2781 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 2782 aprint_error_dev(sc->sc_dev, 2783 "fatal firmware error\n"); 2784 /* Dump firmware error log and stop. */ 2785 iwn_fatal_intr(sc); 2786 s = splnet(); 2787 ifp->if_flags &= ~IFF_UP; 2788 iwn_stop(ifp, 1); 2789 splx(s); 2790 return; 2791 } 2792 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 2793 (r2 & IWN_FH_INT_RX)) { 2794 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 2795 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 2796 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 2797 IWN_WRITE_1(sc, IWN_INT_PERIODIC, IWN_INT_PERIODIC_DIS); 2798 iwn_notif_intr(sc); 2799 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 2800 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 2801 IWN_INT_PERIODIC_ENA); 2802 } 2803 } else 2804 iwn_notif_intr(sc); 2805 } 2806 2807 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 2808 if (sc->sc_flags & IWN_FLAG_USE_ICT) 2809 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 2810 wakeup(sc); /* FH DMA transfer completed. */ 2811 } 2812 2813 if (r1 & IWN_INT_ALIVE) 2814 wakeup(sc); /* Firmware is alive. */ 2815 2816 if (r1 & IWN_INT_WAKEUP) 2817 iwn_wakeup_intr(sc); 2818 2819 out: 2820 /* Re-enable interrupts. */ 2821 if (ifp->if_flags & IFF_UP) 2822 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2823 } 2824 2825 /* 2826 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 2827 * 5000 adapters use a slightly different format). 2828 */ 2829 static void 2830 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2831 uint16_t len) 2832 { 2833 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 2834 2835 *w = htole16(len + 8); 2836 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2837 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2838 sizeof (uint16_t), 2839 BUS_DMASYNC_PREWRITE); 2840 if (idx < IWN_SCHED_WINSZ) { 2841 *(w + IWN_TX_RING_COUNT) = *w; 2842 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2843 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2844 (char *)(void *)sc->sched_dma.vaddr, 2845 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2846 } 2847 } 2848 2849 static void 2850 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 2851 uint16_t len) 2852 { 2853 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2854 2855 *w = htole16(id << 12 | (len + 8)); 2856 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2857 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2858 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2859 if (idx < IWN_SCHED_WINSZ) { 2860 *(w + IWN_TX_RING_COUNT) = *w; 2861 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2862 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2863 (char *)(void *)sc->sched_dma.vaddr, 2864 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2865 } 2866 } 2867 2868 #ifdef notyet 2869 static void 2870 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 2871 { 2872 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 2873 2874 *w = (*w & htole16(0xf000)) | htole16(1); 2875 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2876 (char *)(void *)w - (char *)(void *)sc->sched_dma.vaddr, 2877 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2878 if (idx < IWN_SCHED_WINSZ) { 2879 *(w + IWN_TX_RING_COUNT) = *w; 2880 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 2881 (char *)(void *)(w + IWN_TX_RING_COUNT) - 2882 (char *)(void *)sc->sched_dma.vaddr, 2883 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 2884 } 2885 } 2886 #endif 2887 2888 static int 2889 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 2890 { 2891 struct ieee80211com *ic = &sc->sc_ic; 2892 struct iwn_node *wn = (void *)ni; 2893 struct iwn_tx_ring *ring; 2894 struct iwn_tx_desc *desc; 2895 struct iwn_tx_data *data; 2896 struct iwn_tx_cmd *cmd; 2897 struct iwn_cmd_data *tx; 2898 const struct iwn_rate *rinfo; 2899 struct ieee80211_frame *wh; 2900 struct ieee80211_key *k = NULL; 2901 struct mbuf *m1; 2902 uint32_t flags; 2903 u_int hdrlen; 2904 bus_dma_segment_t *seg; 2905 uint8_t tid, ridx, txant, type; 2906 int i, totlen, error, pad; 2907 2908 const struct chanAccParams *cap; 2909 int noack; 2910 int hdrlen2; 2911 2912 wh = mtod(m, struct ieee80211_frame *); 2913 hdrlen = ieee80211_anyhdrsize(wh); 2914 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2915 2916 hdrlen2 = (ieee80211_has_qos(wh)) ? 2917 sizeof (struct ieee80211_qosframe) : 2918 sizeof (struct ieee80211_frame); 2919 2920 if (hdrlen != hdrlen2) 2921 aprint_error_dev(sc->sc_dev, "hdrlen error (%d != %d)\n", 2922 hdrlen, hdrlen2); 2923 2924 /* XXX OpenBSD sets a different tid when using QOS */ 2925 tid = 0; 2926 if (ieee80211_has_qos(wh)) { 2927 cap = &ic->ic_wme.wme_chanParams; 2928 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 2929 } 2930 else 2931 noack = 0; 2932 2933 ring = &sc->txq[ac]; 2934 desc = &ring->desc[ring->cur]; 2935 data = &ring->data[ring->cur]; 2936 2937 /* Choose a TX rate index. */ 2938 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2939 type != IEEE80211_FC0_TYPE_DATA) { 2940 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2941 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 2942 } else if (ic->ic_fixed_rate != -1) { 2943 ridx = sc->fixed_ridx; 2944 } else 2945 ridx = wn->ridx[ni->ni_txrate]; 2946 rinfo = &iwn_rates[ridx]; 2947 2948 /* Encrypt the frame if need be. */ 2949 /* 2950 * XXX For now, NetBSD swaps the encryption and bpf sections 2951 * in order to match old code and other drivers. Tests with 2952 * tcpdump indicates that the order is irrelevant, however, 2953 * as bpf produces unencrypted data for both ordering choices. 2954 */ 2955 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2956 k = ieee80211_crypto_encap(ic, ni, m); 2957 if (k == NULL) { 2958 m_freem(m); 2959 return ENOBUFS; 2960 } 2961 /* Packet header may have moved, reset our local pointer. */ 2962 wh = mtod(m, struct ieee80211_frame *); 2963 } 2964 totlen = m->m_pkthdr.len; 2965 2966 if (sc->sc_drvbpf != NULL) { 2967 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 2968 2969 tap->wt_flags = 0; 2970 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 2971 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 2972 tap->wt_rate = rinfo->rate; 2973 tap->wt_hwqueue = ac; 2974 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2975 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2976 2977 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2978 } 2979 2980 /* Prepare TX firmware command. */ 2981 cmd = &ring->cmd[ring->cur]; 2982 cmd->code = IWN_CMD_TX_DATA; 2983 cmd->flags = 0; 2984 cmd->qid = ring->qid; 2985 cmd->idx = ring->cur; 2986 2987 tx = (struct iwn_cmd_data *)cmd->data; 2988 /* NB: No need to clear tx, all fields are reinitialized here. */ 2989 tx->scratch = 0; /* clear "scratch" area */ 2990 2991 flags = 0; 2992 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2993 /* Unicast frame, check if an ACK is expected. */ 2994 if (!noack) 2995 flags |= IWN_TX_NEED_ACK; 2996 } 2997 2998 #ifdef notyet 2999 /* XXX NetBSD does not define IEEE80211_FC0_SUBTYPE_BAR */ 3000 if ((wh->i_fc[0] & 3001 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 3002 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3003 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3004 #endif 3005 3006 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3007 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3008 3009 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3010 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3011 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3012 if (totlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 3013 flags |= IWN_TX_NEED_RTS; 3014 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3015 ridx >= IWN_RIDX_OFDM6) { 3016 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3017 flags |= IWN_TX_NEED_CTS; 3018 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3019 flags |= IWN_TX_NEED_RTS; 3020 } 3021 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3022 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3023 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3024 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3025 flags |= IWN_TX_NEED_PROTECTION; 3026 } else 3027 flags |= IWN_TX_FULL_TXOP; 3028 } 3029 } 3030 3031 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3032 type != IEEE80211_FC0_TYPE_DATA) 3033 tx->id = sc->broadcast_id; 3034 else 3035 tx->id = wn->id; 3036 3037 if (type == IEEE80211_FC0_TYPE_MGT) { 3038 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3039 3040 #ifndef IEEE80211_STA_ONLY 3041 /* Tell HW to set timestamp in probe responses. */ 3042 /* XXX NetBSD rev 1.11 added probe requests here but */ 3043 /* probe requests do not take timestamps (from Bergamini). */ 3044 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3045 flags |= IWN_TX_INSERT_TSTAMP; 3046 #endif 3047 /* XXX NetBSD rev 1.11 and 1.20 added AUTH/DAUTH and RTS/CTS */ 3048 /* changes here. These are not needed (from Bergamini). */ 3049 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3050 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3051 tx->timeout = htole16(3); 3052 else 3053 tx->timeout = htole16(2); 3054 } else 3055 tx->timeout = htole16(0); 3056 3057 if (hdrlen & 3) { 3058 /* First segment length must be a multiple of 4. */ 3059 flags |= IWN_TX_NEED_PADDING; 3060 pad = 4 - (hdrlen & 3); 3061 } else 3062 pad = 0; 3063 3064 tx->len = htole16(totlen); 3065 tx->tid = tid; 3066 tx->rts_ntries = 60; 3067 tx->data_ntries = 15; 3068 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3069 tx->plcp = rinfo->plcp; 3070 tx->rflags = rinfo->flags; 3071 if (tx->id == sc->broadcast_id) { 3072 /* Group or management frame. */ 3073 tx->linkq = 0; 3074 /* XXX Alternate between antenna A and B? */ 3075 txant = IWN_LSB(sc->txchainmask); 3076 tx->rflags |= IWN_RFLAG_ANT(txant); 3077 } else { 3078 tx->linkq = ni->ni_rates.rs_nrates - ni->ni_txrate - 1; 3079 flags |= IWN_TX_LINKQ; /* enable MRR */ 3080 } 3081 /* Set physical address of "scratch area". */ 3082 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3083 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3084 3085 /* Copy 802.11 header in TX command. */ 3086 /* XXX NetBSD changed this in rev 1.20 */ 3087 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 3088 3089 /* Trim 802.11 header. */ 3090 m_adj(m, hdrlen); 3091 tx->security = 0; 3092 tx->flags = htole32(flags); 3093 3094 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3095 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3096 if (error != 0) { 3097 if (error != EFBIG) { 3098 aprint_error_dev(sc->sc_dev, 3099 "can't map mbuf (error %d)\n", error); 3100 m_freem(m); 3101 return error; 3102 } 3103 /* Too many DMA segments, linearize mbuf. */ 3104 MGETHDR(m1, M_DONTWAIT, MT_DATA); 3105 if (m1 == NULL) { 3106 m_freem(m); 3107 return ENOBUFS; 3108 } 3109 if (m->m_pkthdr.len > MHLEN) { 3110 MCLGET(m1, M_DONTWAIT); 3111 if (!(m1->m_flags & M_EXT)) { 3112 m_freem(m); 3113 m_freem(m1); 3114 return ENOBUFS; 3115 } 3116 } 3117 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 3118 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 3119 m_freem(m); 3120 m = m1; 3121 3122 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3123 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3124 if (error != 0) { 3125 aprint_error_dev(sc->sc_dev, 3126 "can't map mbuf (error %d)\n", error); 3127 m_freem(m); 3128 return error; 3129 } 3130 } 3131 3132 data->m = m; 3133 data->ni = ni; 3134 3135 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3136 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3137 3138 /* Fill TX descriptor. */ 3139 desc->nsegs = 1 + data->map->dm_nsegs; 3140 /* First DMA segment is used by the TX command. */ 3141 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3142 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3143 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3144 /* Other DMA segments are for data payload. */ 3145 seg = data->map->dm_segs; 3146 for (i = 1; i <= data->map->dm_nsegs; i++) { 3147 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3148 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3149 seg->ds_len << 4); 3150 seg++; 3151 } 3152 3153 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3154 BUS_DMASYNC_PREWRITE); 3155 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3156 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3157 sizeof (*cmd), BUS_DMASYNC_PREWRITE); 3158 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3159 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3160 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3161 3162 #ifdef notyet 3163 /* Update TX scheduler. */ 3164 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3165 #endif 3166 3167 /* Kick TX ring. */ 3168 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3169 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3170 3171 /* Mark TX ring as full if we reach a certain threshold. */ 3172 if (++ring->queued > IWN_TX_RING_HIMARK) 3173 sc->qfullmsk |= 1 << ring->qid; 3174 3175 return 0; 3176 } 3177 3178 static void 3179 iwn_start(struct ifnet *ifp) 3180 { 3181 struct iwn_softc *sc = ifp->if_softc; 3182 struct ieee80211com *ic = &sc->sc_ic; 3183 struct ieee80211_node *ni; 3184 struct ether_header *eh; 3185 struct mbuf *m; 3186 int ac; 3187 3188 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3189 return; 3190 3191 for (;;) { 3192 if (sc->sc_beacon_wait == 1) { 3193 ifp->if_flags |= IFF_OACTIVE; 3194 break; 3195 } 3196 3197 if (sc->qfullmsk != 0) { 3198 ifp->if_flags |= IFF_OACTIVE; 3199 break; 3200 } 3201 /* Send pending management frames first. */ 3202 IF_DEQUEUE(&ic->ic_mgtq, m); 3203 if (m != NULL) { 3204 ni = M_GETCTX(m, struct ieee80211_node *); 3205 ac = 0; 3206 goto sendit; 3207 } 3208 if (ic->ic_state != IEEE80211_S_RUN) 3209 break; 3210 3211 /* Encapsulate and send data frames. */ 3212 IFQ_DEQUEUE(&ifp->if_snd, m); 3213 if (m == NULL) 3214 break; 3215 if (m->m_len < sizeof (*eh) && 3216 (m = m_pullup(m, sizeof (*eh))) == NULL) { 3217 ifp->if_oerrors++; 3218 continue; 3219 } 3220 eh = mtod(m, struct ether_header *); 3221 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 3222 if (ni == NULL) { 3223 m_freem(m); 3224 ifp->if_oerrors++; 3225 continue; 3226 } 3227 /* classify mbuf so we can find which tx ring to use */ 3228 if (ieee80211_classify(ic, m, ni) != 0) { 3229 m_freem(m); 3230 ieee80211_free_node(ni); 3231 ifp->if_oerrors++; 3232 continue; 3233 } 3234 3235 /* No QoS encapsulation for EAPOL frames. */ 3236 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 3237 M_WME_GETAC(m) : WME_AC_BE; 3238 3239 if (sc->sc_beacon_wait == 0) 3240 bpf_mtap(ifp, m, BPF_D_OUT); 3241 3242 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3243 ieee80211_free_node(ni); 3244 ifp->if_oerrors++; 3245 continue; 3246 } 3247 sendit: 3248 if (sc->sc_beacon_wait) 3249 continue; 3250 3251 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 3252 3253 if (iwn_tx(sc, m, ni, ac) != 0) { 3254 ieee80211_free_node(ni); 3255 ifp->if_oerrors++; 3256 continue; 3257 } 3258 3259 sc->sc_tx_timer = 5; 3260 ifp->if_timer = 1; 3261 } 3262 3263 if (sc->sc_beacon_wait > 1) 3264 sc->sc_beacon_wait = 0; 3265 } 3266 3267 static void 3268 iwn_watchdog(struct ifnet *ifp) 3269 { 3270 struct iwn_softc *sc = ifp->if_softc; 3271 3272 ifp->if_timer = 0; 3273 3274 if (sc->sc_tx_timer > 0) { 3275 if (--sc->sc_tx_timer == 0) { 3276 aprint_error_dev(sc->sc_dev, 3277 "device timeout\n"); 3278 ifp->if_flags &= ~IFF_UP; 3279 iwn_stop(ifp, 1); 3280 ifp->if_oerrors++; 3281 return; 3282 } 3283 ifp->if_timer = 1; 3284 } 3285 3286 ieee80211_watchdog(&sc->sc_ic); 3287 } 3288 3289 static int 3290 iwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3291 { 3292 struct iwn_softc *sc = ifp->if_softc; 3293 struct ieee80211com *ic = &sc->sc_ic; 3294 const struct sockaddr *sa; 3295 int s, error = 0; 3296 3297 s = splnet(); 3298 3299 switch (cmd) { 3300 case SIOCSIFADDR: 3301 ifp->if_flags |= IFF_UP; 3302 /* FALLTHROUGH */ 3303 case SIOCSIFFLAGS: 3304 /* XXX Added as it is in every NetBSD driver */ 3305 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3306 break; 3307 if (ifp->if_flags & IFF_UP) { 3308 if (!(ifp->if_flags & IFF_RUNNING)) 3309 error = iwn_init(ifp); 3310 } else { 3311 if (ifp->if_flags & IFF_RUNNING) 3312 iwn_stop(ifp, 1); 3313 } 3314 break; 3315 3316 case SIOCADDMULTI: 3317 case SIOCDELMULTI: 3318 sa = ifreq_getaddr(SIOCADDMULTI, (struct ifreq *)data); 3319 error = (cmd == SIOCADDMULTI) ? 3320 ether_addmulti(sa, &sc->sc_ec) : 3321 ether_delmulti(sa, &sc->sc_ec); 3322 3323 if (error == ENETRESET) 3324 error = 0; 3325 break; 3326 3327 default: 3328 error = ieee80211_ioctl(ic, cmd, data); 3329 } 3330 3331 if (error == ENETRESET) { 3332 error = 0; 3333 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3334 (IFF_UP | IFF_RUNNING)) { 3335 iwn_stop(ifp, 0); 3336 error = iwn_init(ifp); 3337 } 3338 } 3339 3340 splx(s); 3341 return error; 3342 } 3343 3344 /* 3345 * Send a command to the firmware. 3346 */ 3347 static int 3348 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3349 { 3350 struct iwn_tx_ring *ring = &sc->txq[4]; 3351 struct iwn_tx_desc *desc; 3352 struct iwn_tx_data *data; 3353 struct iwn_tx_cmd *cmd; 3354 struct mbuf *m; 3355 bus_addr_t paddr; 3356 int totlen, error; 3357 3358 desc = &ring->desc[ring->cur]; 3359 data = &ring->data[ring->cur]; 3360 totlen = 4 + size; 3361 3362 if (size > sizeof cmd->data) { 3363 /* Command is too large to fit in a descriptor. */ 3364 if (totlen > MCLBYTES) 3365 return EINVAL; 3366 MGETHDR(m, M_DONTWAIT, MT_DATA); 3367 if (m == NULL) 3368 return ENOMEM; 3369 if (totlen > MHLEN) { 3370 MCLGET(m, M_DONTWAIT); 3371 if (!(m->m_flags & M_EXT)) { 3372 m_freem(m); 3373 return ENOMEM; 3374 } 3375 } 3376 cmd = mtod(m, struct iwn_tx_cmd *); 3377 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3378 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3379 if (error != 0) { 3380 m_freem(m); 3381 return error; 3382 } 3383 data->m = m; 3384 paddr = data->map->dm_segs[0].ds_addr; 3385 } else { 3386 cmd = &ring->cmd[ring->cur]; 3387 paddr = data->cmd_paddr; 3388 } 3389 3390 cmd->code = code; 3391 cmd->flags = 0; 3392 cmd->qid = ring->qid; 3393 cmd->idx = ring->cur; 3394 /* 3395 * Coverity:[OUT_OF_BOUNDS] 3396 * false positive since, allocated in mbuf if it does not fit 3397 */ 3398 memcpy(cmd->data, buf, size); 3399 3400 desc->nsegs = 1; 3401 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3402 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3403 3404 if (size > sizeof cmd->data) { 3405 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3406 BUS_DMASYNC_PREWRITE); 3407 } else { 3408 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3409 (char *)(void *)cmd - (char *)(void *)ring->cmd_dma.vaddr, 3410 totlen, BUS_DMASYNC_PREWRITE); 3411 } 3412 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3413 (char *)(void *)desc - (char *)(void *)ring->desc_dma.vaddr, 3414 sizeof (*desc), BUS_DMASYNC_PREWRITE); 3415 3416 #ifdef notyet 3417 /* Update TX scheduler. */ 3418 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3419 #endif 3420 DPRINTFN(4, ("iwn_cmd %d size=%d %s\n", code, size, async ? " (async)" : "")); 3421 3422 /* Kick command ring. */ 3423 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3424 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3425 3426 return async ? 0 : tsleep(desc, PCATCH, "iwncmd", hz); 3427 } 3428 3429 static int 3430 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3431 { 3432 struct iwn4965_node_info hnode; 3433 char *src, *dst; 3434 3435 /* 3436 * We use the node structure for 5000 Series internally (it is 3437 * a superset of the one for 4965AGN). We thus copy the common 3438 * fields before sending the command. 3439 */ 3440 src = (char *)node; 3441 dst = (char *)&hnode; 3442 memcpy(dst, src, 48); 3443 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3444 memcpy(dst + 48, src + 72, 20); 3445 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3446 } 3447 3448 static int 3449 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3450 { 3451 /* Direct mapping. */ 3452 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3453 } 3454 3455 static int 3456 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3457 { 3458 struct iwn_node *wn = (void *)ni; 3459 struct ieee80211_rateset *rs = &ni->ni_rates; 3460 struct iwn_cmd_link_quality linkq; 3461 const struct iwn_rate *rinfo; 3462 uint8_t txant; 3463 int i, txrate; 3464 3465 /* Use the first valid TX antenna. */ 3466 txant = IWN_LSB(sc->txchainmask); 3467 3468 memset(&linkq, 0, sizeof linkq); 3469 linkq.id = wn->id; 3470 linkq.antmsk_1stream = txant; 3471 linkq.antmsk_2stream = IWN_ANT_AB; 3472 linkq.ampdu_max = 31; 3473 linkq.ampdu_threshold = 3; 3474 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3475 3476 /* Start at highest available bit-rate. */ 3477 txrate = rs->rs_nrates - 1; 3478 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 3479 rinfo = &iwn_rates[wn->ridx[txrate]]; 3480 linkq.retry[i].plcp = rinfo->plcp; 3481 linkq.retry[i].rflags = rinfo->flags; 3482 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 3483 /* Next retry at immediate lower bit-rate. */ 3484 if (txrate > 0) 3485 txrate--; 3486 } 3487 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 3488 } 3489 3490 /* 3491 * Broadcast node is used to send group-addressed and management frames. 3492 */ 3493 static int 3494 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 3495 { 3496 struct iwn_ops *ops = &sc->ops; 3497 struct iwn_node_info node; 3498 struct iwn_cmd_link_quality linkq; 3499 const struct iwn_rate *rinfo; 3500 uint8_t txant; 3501 int i, error; 3502 3503 memset(&node, 0, sizeof node); 3504 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 3505 node.id = sc->broadcast_id; 3506 DPRINTF(("adding broadcast node\n")); 3507 if ((error = ops->add_node(sc, &node, async)) != 0) 3508 return error; 3509 3510 /* Use the first valid TX antenna. */ 3511 txant = IWN_LSB(sc->txchainmask); 3512 3513 memset(&linkq, 0, sizeof linkq); 3514 linkq.id = sc->broadcast_id; 3515 linkq.antmsk_1stream = txant; 3516 linkq.antmsk_2stream = IWN_ANT_AB; 3517 linkq.ampdu_max = 64; 3518 linkq.ampdu_threshold = 3; 3519 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3520 3521 /* Use lowest mandatory bit-rate. */ 3522 rinfo = (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) ? 3523 &iwn_rates[IWN_RIDX_CCK1] : &iwn_rates[IWN_RIDX_OFDM6]; 3524 linkq.retry[0].plcp = rinfo->plcp; 3525 linkq.retry[0].rflags = rinfo->flags; 3526 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 3527 /* Use same bit-rate for all TX retries. */ 3528 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 3529 linkq.retry[i].plcp = linkq.retry[0].plcp; 3530 linkq.retry[i].rflags = linkq.retry[0].rflags; 3531 } 3532 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 3533 } 3534 3535 static void 3536 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 3537 { 3538 struct iwn_cmd_led led; 3539 3540 /* Clear microcode LED ownership. */ 3541 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 3542 3543 led.which = which; 3544 led.unit = htole32(10000); /* on/off in unit of 100ms */ 3545 led.off = off; 3546 led.on = on; 3547 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 3548 } 3549 3550 /* 3551 * Set the critical temperature at which the firmware will stop the radio 3552 * and notify us. 3553 */ 3554 static int 3555 iwn_set_critical_temp(struct iwn_softc *sc) 3556 { 3557 struct iwn_critical_temp crit; 3558 int32_t temp; 3559 3560 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 3561 3562 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 3563 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 3564 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3565 temp = IWN_CTOK(110); 3566 else 3567 temp = 110; 3568 memset(&crit, 0, sizeof crit); 3569 crit.tempR = htole32(temp); 3570 DPRINTF(("setting critical temperature to %d\n", temp)); 3571 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 3572 } 3573 3574 static int 3575 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 3576 { 3577 struct iwn_cmd_timing cmd; 3578 uint64_t val, mod; 3579 3580 memset(&cmd, 0, sizeof cmd); 3581 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 3582 cmd.bintval = htole16(ni->ni_intval); 3583 cmd.lintval = htole16(10); 3584 3585 /* Compute remaining time until next beacon. */ 3586 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */ 3587 mod = le64toh(cmd.tstamp) % val; 3588 cmd.binitval = htole32((uint32_t)(val - mod)); 3589 3590 DPRINTF(("timing bintval=%u, tstamp=%" PRIu64 ", init=%" PRIu32 "\n", 3591 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod))); 3592 3593 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 3594 } 3595 3596 static void 3597 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 3598 { 3599 /* Adjust TX power if need be (delta >= 3 degC). */ 3600 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 3601 if (abs(temp - sc->temp) >= 3) { 3602 /* Record temperature of last calibration. */ 3603 sc->temp = temp; 3604 (void)iwn4965_set_txpower(sc, 1); 3605 } 3606 } 3607 3608 /* 3609 * Set TX power for current channel (each rate has its own power settings). 3610 * This function takes into account the regulatory information from EEPROM, 3611 * the current temperature and the current voltage. 3612 */ 3613 static int 3614 iwn4965_set_txpower(struct iwn_softc *sc, int async) 3615 { 3616 /* Fixed-point arithmetic division using a n-bit fractional part. */ 3617 #define fdivround(a, b, n) \ 3618 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 3619 /* Linear interpolation. */ 3620 #define interpolate(x, x1, y1, x2, y2, n) \ 3621 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 3622 3623 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 3624 struct ieee80211com *ic = &sc->sc_ic; 3625 struct iwn_ucode_info *uc = &sc->ucode_info; 3626 struct ieee80211_channel *ch; 3627 struct iwn4965_cmd_txpower cmd; 3628 struct iwn4965_eeprom_chan_samples *chans; 3629 const uint8_t *rf_gain, *dsp_gain; 3630 int32_t vdiff, tdiff; 3631 int i, c, grp, maxpwr; 3632 uint8_t chan; 3633 3634 /* Retrieve current channel from last RXON. */ 3635 chan = sc->rxon.chan; 3636 DPRINTF(("setting TX power for channel %d\n", chan)); 3637 ch = &ic->ic_channels[chan]; 3638 3639 memset(&cmd, 0, sizeof cmd); 3640 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 3641 cmd.chan = chan; 3642 3643 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 3644 maxpwr = sc->maxpwr5GHz; 3645 rf_gain = iwn4965_rf_gain_5ghz; 3646 dsp_gain = iwn4965_dsp_gain_5ghz; 3647 } else { 3648 maxpwr = sc->maxpwr2GHz; 3649 rf_gain = iwn4965_rf_gain_2ghz; 3650 dsp_gain = iwn4965_dsp_gain_2ghz; 3651 } 3652 3653 /* Compute voltage compensation. */ 3654 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 3655 if (vdiff > 0) 3656 vdiff *= 2; 3657 if (abs(vdiff) > 2) 3658 vdiff = 0; 3659 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 3660 vdiff, le32toh(uc->volt), sc->eeprom_voltage)); 3661 3662 /* Get channel attenuation group. */ 3663 if (chan <= 20) /* 1-20 */ 3664 grp = 4; 3665 else if (chan <= 43) /* 34-43 */ 3666 grp = 0; 3667 else if (chan <= 70) /* 44-70 */ 3668 grp = 1; 3669 else if (chan <= 124) /* 71-124 */ 3670 grp = 2; 3671 else /* 125-200 */ 3672 grp = 3; 3673 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 3674 3675 /* Get channel sub-band. */ 3676 for (i = 0; i < IWN_NBANDS; i++) 3677 if (sc->bands[i].lo != 0 && 3678 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 3679 break; 3680 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 3681 return EINVAL; 3682 chans = sc->bands[i].chans; 3683 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 3684 3685 for (c = 0; c < 2; c++) { 3686 uint8_t power, gain, temp; 3687 int maxchpwr, pwr, ridx, idx; 3688 3689 power = interpolate(chan, 3690 chans[0].num, chans[0].samples[c][1].power, 3691 chans[1].num, chans[1].samples[c][1].power, 1); 3692 gain = interpolate(chan, 3693 chans[0].num, chans[0].samples[c][1].gain, 3694 chans[1].num, chans[1].samples[c][1].gain, 1); 3695 temp = interpolate(chan, 3696 chans[0].num, chans[0].samples[c][1].temp, 3697 chans[1].num, chans[1].samples[c][1].temp, 1); 3698 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 3699 c, power, gain, temp)); 3700 3701 /* Compute temperature compensation. */ 3702 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 3703 DPRINTF(("temperature compensation=%d (current=%d, " 3704 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 3705 3706 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 3707 /* Convert dBm to half-dBm. */ 3708 maxchpwr = sc->maxpwr[chan] * 2; 3709 if ((ridx / 8) & 1) 3710 maxchpwr -= 6; /* MIMO 2T: -3dB */ 3711 3712 pwr = maxpwr; 3713 3714 /* Adjust TX power based on rate. */ 3715 if ((ridx % 8) == 5) 3716 pwr -= 15; /* OFDM48: -7.5dB */ 3717 else if ((ridx % 8) == 6) 3718 pwr -= 17; /* OFDM54: -8.5dB */ 3719 else if ((ridx % 8) == 7) 3720 pwr -= 20; /* OFDM60: -10dB */ 3721 else 3722 pwr -= 10; /* Others: -5dB */ 3723 3724 /* Do not exceed channel max TX power. */ 3725 if (pwr > maxchpwr) 3726 pwr = maxchpwr; 3727 3728 idx = gain - (pwr - power) - tdiff - vdiff; 3729 if ((ridx / 8) & 1) /* MIMO */ 3730 idx += (int32_t)le32toh(uc->atten[grp][c]); 3731 3732 if (cmd.band == 0) 3733 idx += 9; /* 5GHz */ 3734 if (ridx == IWN_RIDX_MAX) 3735 idx += 5; /* CCK */ 3736 3737 /* Make sure idx stays in a valid range. */ 3738 if (idx < 0) 3739 idx = 0; 3740 else if (idx > IWN4965_MAX_PWR_INDEX) 3741 idx = IWN4965_MAX_PWR_INDEX; 3742 3743 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 3744 c, ridx, idx)); 3745 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 3746 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 3747 } 3748 } 3749 3750 DPRINTF(("setting TX power for chan %d\n", chan)); 3751 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 3752 3753 #undef interpolate 3754 #undef fdivround 3755 } 3756 3757 static int 3758 iwn5000_set_txpower(struct iwn_softc *sc, int async) 3759 { 3760 struct iwn5000_cmd_txpower cmd; 3761 int cmdid; 3762 3763 /* 3764 * TX power calibration is handled automatically by the firmware 3765 * for 5000 Series. 3766 */ 3767 memset(&cmd, 0, sizeof cmd); 3768 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 3769 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 3770 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 3771 DPRINTF(("setting TX power\n")); 3772 if (IWN_UCODE_API(sc->ucode_rev) == 1) 3773 cmdid = IWN_CMD_TXPOWER_DBM_V1; 3774 else 3775 cmdid = IWN_CMD_TXPOWER_DBM; 3776 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 3777 } 3778 3779 /* 3780 * Retrieve the maximum RSSI (in dBm) among receivers. 3781 */ 3782 static int 3783 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 3784 { 3785 const struct iwn4965_rx_phystat *phy = (const void *)stat->phybuf; 3786 uint8_t mask, agc; 3787 int rssi; 3788 3789 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 3790 agc = (le16toh(phy->agc) >> 7) & 0x7f; 3791 3792 rssi = 0; 3793 if (mask & IWN_ANT_A) 3794 rssi = MAX(rssi, phy->rssi[0]); 3795 if (mask & IWN_ANT_B) 3796 rssi = MAX(rssi, phy->rssi[2]); 3797 if (mask & IWN_ANT_C) 3798 rssi = MAX(rssi, phy->rssi[4]); 3799 3800 return rssi - agc - IWN_RSSI_TO_DBM; 3801 } 3802 3803 static int 3804 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 3805 { 3806 const struct iwn5000_rx_phystat *phy = (const void *)stat->phybuf; 3807 uint8_t agc; 3808 int rssi; 3809 3810 agc = (le32toh(phy->agc) >> 9) & 0x7f; 3811 3812 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 3813 le16toh(phy->rssi[1]) & 0xff); 3814 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 3815 3816 return rssi - agc - IWN_RSSI_TO_DBM; 3817 } 3818 3819 /* 3820 * Retrieve the average noise (in dBm) among receivers. 3821 */ 3822 static int 3823 iwn_get_noise(const struct iwn_rx_general_stats *stats) 3824 { 3825 int i, total, nbant, noise; 3826 3827 total = nbant = 0; 3828 for (i = 0; i < 3; i++) { 3829 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 3830 continue; 3831 total += noise; 3832 nbant++; 3833 } 3834 /* There should be at least one antenna but check anyway. */ 3835 return (nbant == 0) ? -127 : (total / nbant) - 107; 3836 } 3837 3838 /* 3839 * Compute temperature (in degC) from last received statistics. 3840 */ 3841 static int 3842 iwn4965_get_temperature(struct iwn_softc *sc) 3843 { 3844 struct iwn_ucode_info *uc = &sc->ucode_info; 3845 int32_t r1, r2, r3, r4, temp; 3846 3847 r1 = le32toh(uc->temp[0].chan20MHz); 3848 r2 = le32toh(uc->temp[1].chan20MHz); 3849 r3 = le32toh(uc->temp[2].chan20MHz); 3850 r4 = le32toh(sc->rawtemp); 3851 3852 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 3853 return 0; 3854 3855 /* Sign-extend 23-bit R4 value to 32-bit. */ 3856 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 3857 /* Compute temperature in Kelvin. */ 3858 temp = (259 * (r4 - r2)) / (r3 - r1); 3859 temp = (temp * 97) / 100 + 8; 3860 3861 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 3862 return IWN_KTOC(temp); 3863 } 3864 3865 static int 3866 iwn5000_get_temperature(struct iwn_softc *sc) 3867 { 3868 int32_t temp; 3869 3870 /* 3871 * Temperature is not used by the driver for 5000 Series because 3872 * TX power calibration is handled by firmware. We export it to 3873 * users through the sensor framework though. 3874 */ 3875 temp = le32toh(sc->rawtemp); 3876 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 3877 temp = (temp / -5) + sc->temp_off; 3878 temp = IWN_KTOC(temp); 3879 } 3880 return temp; 3881 } 3882 3883 /* 3884 * Initialize sensitivity calibration state machine. 3885 */ 3886 static int 3887 iwn_init_sensitivity(struct iwn_softc *sc) 3888 { 3889 struct iwn_ops *ops = &sc->ops; 3890 struct iwn_calib_state *calib = &sc->calib; 3891 uint32_t flags; 3892 int error; 3893 3894 /* Reset calibration state machine. */ 3895 memset(calib, 0, sizeof (*calib)); 3896 calib->state = IWN_CALIB_STATE_INIT; 3897 calib->cck_state = IWN_CCK_STATE_HIFA; 3898 /* Set initial correlation values. */ 3899 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 3900 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 3901 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 3902 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 3903 calib->cck_x4 = 125; 3904 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 3905 calib->energy_cck = sc->limits->energy_cck; 3906 3907 /* Write initial sensitivity. */ 3908 if ((error = iwn_send_sensitivity(sc)) != 0) 3909 return error; 3910 3911 /* Write initial gains. */ 3912 if ((error = ops->init_gains(sc)) != 0) 3913 return error; 3914 3915 /* Request statistics at each beacon interval. */ 3916 flags = 0; 3917 DPRINTF(("sending request for statistics\n")); 3918 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 3919 } 3920 3921 /* 3922 * Collect noise and RSSI statistics for the first 20 beacons received 3923 * after association and use them to determine connected antennas and 3924 * to set differential gains. 3925 */ 3926 static void 3927 iwn_collect_noise(struct iwn_softc *sc, 3928 const struct iwn_rx_general_stats *stats) 3929 { 3930 struct iwn_ops *ops = &sc->ops; 3931 struct iwn_calib_state *calib = &sc->calib; 3932 uint32_t val; 3933 int i; 3934 3935 /* Accumulate RSSI and noise for all 3 antennas. */ 3936 for (i = 0; i < 3; i++) { 3937 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 3938 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 3939 } 3940 /* NB: We update differential gains only once after 20 beacons. */ 3941 if (++calib->nbeacons < 20) 3942 return; 3943 3944 /* Determine highest average RSSI. */ 3945 val = MAX(calib->rssi[0], calib->rssi[1]); 3946 val = MAX(calib->rssi[2], val); 3947 3948 /* Determine which antennas are connected. */ 3949 sc->chainmask = sc->rxchainmask; 3950 for (i = 0; i < 3; i++) 3951 if (val - calib->rssi[i] > 15 * 20) 3952 sc->chainmask &= ~(1 << i); 3953 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 3954 sc->rxchainmask, sc->chainmask)); 3955 3956 /* If none of the TX antennas are connected, keep at least one. */ 3957 if ((sc->chainmask & sc->txchainmask) == 0) 3958 sc->chainmask |= IWN_LSB(sc->txchainmask); 3959 3960 (void)ops->set_gains(sc); 3961 calib->state = IWN_CALIB_STATE_RUN; 3962 3963 #ifdef notyet 3964 /* XXX Disable RX chains with no antennas connected. */ 3965 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 3966 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 3967 #endif 3968 3969 /* Enable power-saving mode if requested by user. */ 3970 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 3971 (void)iwn_set_pslevel(sc, 0, 3, 1); 3972 } 3973 3974 static int 3975 iwn4965_init_gains(struct iwn_softc *sc) 3976 { 3977 struct iwn_phy_calib_gain cmd; 3978 3979 memset(&cmd, 0, sizeof cmd); 3980 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 3981 /* Differential gains initially set to 0 for all 3 antennas. */ 3982 DPRINTF(("setting initial differential gains\n")); 3983 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3984 } 3985 3986 static int 3987 iwn5000_init_gains(struct iwn_softc *sc) 3988 { 3989 struct iwn_phy_calib cmd; 3990 3991 memset(&cmd, 0, sizeof cmd); 3992 cmd.code = sc->reset_noise_gain; 3993 cmd.ngroups = 1; 3994 cmd.isvalid = 1; 3995 DPRINTF(("setting initial differential gains\n")); 3996 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 3997 } 3998 3999 static int 4000 iwn4965_set_gains(struct iwn_softc *sc) 4001 { 4002 struct iwn_calib_state *calib = &sc->calib; 4003 struct iwn_phy_calib_gain cmd; 4004 int i, delta, noise; 4005 4006 /* Get minimal noise among connected antennas. */ 4007 noise = INT_MAX; /* NB: There's at least one antenna. */ 4008 for (i = 0; i < 3; i++) 4009 if (sc->chainmask & (1 << i)) 4010 noise = MIN(calib->noise[i], noise); 4011 4012 memset(&cmd, 0, sizeof cmd); 4013 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4014 /* Set differential gains for connected antennas. */ 4015 for (i = 0; i < 3; i++) { 4016 if (sc->chainmask & (1 << i)) { 4017 /* Compute attenuation (in unit of 1.5dB). */ 4018 delta = (noise - (int32_t)calib->noise[i]) / 30; 4019 /* NB: delta <= 0 */ 4020 /* Limit to [-4.5dB,0]. */ 4021 cmd.gain[i] = MIN(abs(delta), 3); 4022 if (delta < 0) 4023 cmd.gain[i] |= 1 << 2; /* sign bit */ 4024 } 4025 } 4026 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4027 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 4028 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4029 } 4030 4031 static int 4032 iwn5000_set_gains(struct iwn_softc *sc) 4033 { 4034 struct iwn_calib_state *calib = &sc->calib; 4035 struct iwn_phy_calib_gain cmd; 4036 int i, ant, div, delta; 4037 4038 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4039 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4040 4041 memset(&cmd, 0, sizeof cmd); 4042 cmd.code = sc->noise_gain; 4043 cmd.ngroups = 1; 4044 cmd.isvalid = 1; 4045 /* Get first available RX antenna as referential. */ 4046 ant = IWN_LSB(sc->rxchainmask); 4047 /* Set differential gains for other antennas. */ 4048 for (i = ant + 1; i < 3; i++) { 4049 if (sc->chainmask & (1 << i)) { 4050 /* The delta is relative to antenna "ant". */ 4051 delta = ((int32_t)calib->noise[ant] - 4052 (int32_t)calib->noise[i]) / div; 4053 /* Limit to [-4.5dB,+4.5dB]. */ 4054 cmd.gain[i - 1] = MIN(abs(delta), 3); 4055 if (delta < 0) 4056 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4057 } 4058 } 4059 DPRINTF(("setting differential gains: %x/%x (%x)\n", 4060 cmd.gain[0], cmd.gain[1], sc->chainmask)); 4061 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4062 } 4063 4064 /* 4065 * Tune RF RX sensitivity based on the number of false alarms detected 4066 * during the last beacon period. 4067 */ 4068 static void 4069 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4070 { 4071 #define inc(val, inc, max) \ 4072 if ((val) < (max)) { \ 4073 if ((val) < (max) - (inc)) \ 4074 (val) += (inc); \ 4075 else \ 4076 (val) = (max); \ 4077 needs_update = 1; \ 4078 } 4079 #define dec(val, dec, min) \ 4080 if ((val) > (min)) { \ 4081 if ((val) > (min) + (dec)) \ 4082 (val) -= (dec); \ 4083 else \ 4084 (val) = (min); \ 4085 needs_update = 1; \ 4086 } 4087 4088 const struct iwn_sensitivity_limits *limits = sc->limits; 4089 struct iwn_calib_state *calib = &sc->calib; 4090 uint32_t val, rxena, fa; 4091 uint32_t energy[3], energy_min; 4092 uint8_t noise[3], noise_ref; 4093 int i, needs_update = 0; 4094 4095 /* Check that we've been enabled long enough. */ 4096 if ((rxena = le32toh(stats->general.load)) == 0) 4097 return; 4098 4099 /* Compute number of false alarms since last call for OFDM. */ 4100 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4101 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4102 fa *= 200 * 1024; /* 200TU */ 4103 4104 /* Save counters values for next call. */ 4105 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4106 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4107 4108 if (fa > 50 * rxena) { 4109 /* High false alarm count, decrease sensitivity. */ 4110 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4111 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4112 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4113 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4114 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4115 4116 } else if (fa < 5 * rxena) { 4117 /* Low false alarm count, increase sensitivity. */ 4118 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4119 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4120 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4121 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4122 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4123 } 4124 4125 /* Compute maximum noise among 3 receivers. */ 4126 for (i = 0; i < 3; i++) 4127 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4128 val = MAX(noise[0], noise[1]); 4129 val = MAX(noise[2], val); 4130 /* Insert it into our samples table. */ 4131 calib->noise_samples[calib->cur_noise_sample] = val; 4132 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4133 4134 /* Compute maximum noise among last 20 samples. */ 4135 noise_ref = calib->noise_samples[0]; 4136 for (i = 1; i < 20; i++) 4137 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4138 4139 /* Compute maximum energy among 3 receivers. */ 4140 for (i = 0; i < 3; i++) 4141 energy[i] = le32toh(stats->general.energy[i]); 4142 val = MIN(energy[0], energy[1]); 4143 val = MIN(energy[2], val); 4144 /* Insert it into our samples table. */ 4145 calib->energy_samples[calib->cur_energy_sample] = val; 4146 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4147 4148 /* Compute minimum energy among last 10 samples. */ 4149 energy_min = calib->energy_samples[0]; 4150 for (i = 1; i < 10; i++) 4151 energy_min = MAX(energy_min, calib->energy_samples[i]); 4152 energy_min += 6; 4153 4154 /* Compute number of false alarms since last call for CCK. */ 4155 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4156 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4157 fa *= 200 * 1024; /* 200TU */ 4158 4159 /* Save counters values for next call. */ 4160 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4161 calib->fa_cck = le32toh(stats->cck.fa); 4162 4163 if (fa > 50 * rxena) { 4164 /* High false alarm count, decrease sensitivity. */ 4165 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4166 calib->cck_state = IWN_CCK_STATE_HIFA; 4167 calib->low_fa = 0; 4168 4169 if (calib->cck_x4 > 160) { 4170 calib->noise_ref = noise_ref; 4171 if (calib->energy_cck > 2) 4172 dec(calib->energy_cck, 2, energy_min); 4173 } 4174 if (calib->cck_x4 < 160) { 4175 calib->cck_x4 = 161; 4176 needs_update = 1; 4177 } else 4178 inc(calib->cck_x4, 3, limits->max_cck_x4); 4179 4180 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4181 4182 } else if (fa < 5 * rxena) { 4183 /* Low false alarm count, increase sensitivity. */ 4184 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4185 calib->cck_state = IWN_CCK_STATE_LOFA; 4186 calib->low_fa++; 4187 4188 if (calib->cck_state != IWN_CCK_STATE_INIT && 4189 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4190 calib->low_fa > 100)) { 4191 inc(calib->energy_cck, 2, limits->min_energy_cck); 4192 dec(calib->cck_x4, 3, limits->min_cck_x4); 4193 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4194 } 4195 } else { 4196 /* Not worth to increase or decrease sensitivity. */ 4197 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4198 calib->low_fa = 0; 4199 calib->noise_ref = noise_ref; 4200 4201 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4202 /* Previous interval had many false alarms. */ 4203 dec(calib->energy_cck, 8, energy_min); 4204 } 4205 calib->cck_state = IWN_CCK_STATE_INIT; 4206 } 4207 4208 if (needs_update) 4209 (void)iwn_send_sensitivity(sc); 4210 #undef dec 4211 #undef inc 4212 } 4213 4214 static int 4215 iwn_send_sensitivity(struct iwn_softc *sc) 4216 { 4217 struct iwn_calib_state *calib = &sc->calib; 4218 struct iwn_enhanced_sensitivity_cmd cmd; 4219 int len; 4220 4221 memset(&cmd, 0, sizeof cmd); 4222 len = sizeof (struct iwn_sensitivity_cmd); 4223 cmd.which = IWN_SENSITIVITY_WORKTBL; 4224 /* OFDM modulation. */ 4225 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4226 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4227 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4228 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4229 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4230 cmd.energy_ofdm_th = htole16(62); 4231 /* CCK modulation. */ 4232 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4233 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4234 cmd.energy_cck = htole16(calib->energy_cck); 4235 /* Barker modulation: use default values. */ 4236 cmd.corr_barker = htole16(190); 4237 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 4238 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4239 goto send; 4240 /* Enhanced sensitivity settings. */ 4241 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4242 cmd.ofdm_det_slope_mrc = htole16(668); 4243 cmd.ofdm_det_icept_mrc = htole16(4); 4244 cmd.ofdm_det_slope = htole16(486); 4245 cmd.ofdm_det_icept = htole16(37); 4246 cmd.cck_det_slope_mrc = htole16(853); 4247 cmd.cck_det_icept_mrc = htole16(4); 4248 cmd.cck_det_slope = htole16(476); 4249 cmd.cck_det_icept = htole16(99); 4250 send: 4251 DPRINTFN(2, ("setting sensitivity %d/%d/%d/%d/%d/%d/%d\n", 4252 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4253 calib->ofdm_mrc_x4, calib->cck_x4, calib->cck_mrc_x4, 4254 calib->energy_cck)); 4255 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4256 } 4257 4258 /* 4259 * Set STA mode power saving level (between 0 and 5). 4260 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4261 */ 4262 static int 4263 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4264 { 4265 struct iwn_pmgt_cmd cmd; 4266 const struct iwn_pmgt *pmgt; 4267 uint32_t maxp, skip_dtim; 4268 pcireg_t reg; 4269 int i; 4270 4271 /* Select which PS parameters to use. */ 4272 if (dtim <= 2) 4273 pmgt = &iwn_pmgt[0][level]; 4274 else if (dtim <= 10) 4275 pmgt = &iwn_pmgt[1][level]; 4276 else 4277 pmgt = &iwn_pmgt[2][level]; 4278 4279 memset(&cmd, 0, sizeof cmd); 4280 if (level != 0) /* not CAM */ 4281 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4282 if (level == 5) 4283 cmd.flags |= htole16(IWN_PS_FAST_PD); 4284 /* Retrieve PCIe Active State Power Management (ASPM). */ 4285 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4286 sc->sc_cap_off + PCIE_LCSR); 4287 if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4288 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4289 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4290 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4291 4292 if (dtim == 0) { 4293 dtim = 1; 4294 skip_dtim = 0; 4295 } else 4296 skip_dtim = pmgt->skip_dtim; 4297 if (skip_dtim != 0) { 4298 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4299 maxp = pmgt->intval[4]; 4300 if (maxp == (uint32_t)-1) 4301 maxp = dtim * (skip_dtim + 1); 4302 else if (maxp > dtim) 4303 maxp = (maxp / dtim) * dtim; 4304 } else 4305 maxp = dtim; 4306 for (i = 0; i < 5; i++) 4307 cmd.intval[i] = htole32(MIN(maxp, pmgt->intval[i])); 4308 4309 DPRINTF(("setting power saving level to %d\n", level)); 4310 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4311 } 4312 4313 int 4314 iwn5000_runtime_calib(struct iwn_softc *sc) 4315 { 4316 struct iwn5000_calib_config cmd; 4317 4318 memset(&cmd, 0, sizeof cmd); 4319 cmd.ucode.once.enable = 0xffffffff; 4320 cmd.ucode.once.start = IWN5000_CALIB_DC; 4321 DPRINTF(("configuring runtime calibration\n")); 4322 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4323 } 4324 4325 static int 4326 iwn_config_bt_coex_bluetooth(struct iwn_softc *sc) 4327 { 4328 struct iwn_bluetooth bluetooth; 4329 4330 memset(&bluetooth, 0, sizeof bluetooth); 4331 bluetooth.flags = IWN_BT_COEX_ENABLE; 4332 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF; 4333 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF; 4334 4335 DPRINTF(("configuring bluetooth coexistence\n")); 4336 return iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0); 4337 } 4338 4339 static int 4340 iwn_config_bt_coex_prio_table(struct iwn_softc *sc) 4341 { 4342 uint8_t prio_table[16]; 4343 4344 memset(&prio_table, 0, sizeof prio_table); 4345 prio_table[ 0] = 6; /* init calibration 1 */ 4346 prio_table[ 1] = 7; /* init calibration 2 */ 4347 prio_table[ 2] = 2; /* periodic calib low 1 */ 4348 prio_table[ 3] = 3; /* periodic calib low 2 */ 4349 prio_table[ 4] = 4; /* periodic calib high 1 */ 4350 prio_table[ 5] = 5; /* periodic calib high 2 */ 4351 prio_table[ 6] = 6; /* dtim */ 4352 prio_table[ 7] = 8; /* scan52 */ 4353 prio_table[ 8] = 10; /* scan24 */ 4354 4355 DPRINTF(("sending priority lookup table\n")); 4356 return iwn_cmd(sc, IWN_CMD_BT_COEX_PRIO_TABLE, 4357 &prio_table, sizeof prio_table, 0); 4358 } 4359 4360 static int 4361 iwn_config_bt_coex_adv_config(struct iwn_softc *sc, struct iwn_bt_basic *basic, 4362 size_t len) 4363 { 4364 struct iwn_btcoex_prot btprot; 4365 int error; 4366 4367 basic->bt.flags = IWN_BT_COEX_ENABLE; 4368 basic->bt.lead_time = IWN_BT_LEAD_TIME_DEF; 4369 basic->bt.max_kill = IWN_BT_MAX_KILL_DEF; 4370 basic->bt.bt3_timer_t7_value = IWN_BT_BT3_T7_DEF; 4371 basic->bt.kill_ack_mask = IWN_BT_KILL_ACK_MASK_DEF; 4372 basic->bt.kill_cts_mask = IWN_BT_KILL_CTS_MASK_DEF; 4373 basic->bt3_prio_sample_time = IWN_BT_BT3_PRIO_SAMPLE_DEF; 4374 basic->bt3_timer_t2_value = IWN_BT_BT3_T2_DEF; 4375 basic->bt3_lookup_table[ 0] = htole32(0xaaaaaaaa); /* Normal */ 4376 basic->bt3_lookup_table[ 1] = htole32(0xaaaaaaaa); 4377 basic->bt3_lookup_table[ 2] = htole32(0xaeaaaaaa); 4378 basic->bt3_lookup_table[ 3] = htole32(0xaaaaaaaa); 4379 basic->bt3_lookup_table[ 4] = htole32(0xcc00ff28); 4380 basic->bt3_lookup_table[ 5] = htole32(0x0000aaaa); 4381 basic->bt3_lookup_table[ 6] = htole32(0xcc00aaaa); 4382 basic->bt3_lookup_table[ 7] = htole32(0x0000aaaa); 4383 basic->bt3_lookup_table[ 8] = htole32(0xc0004000); 4384 basic->bt3_lookup_table[ 9] = htole32(0x00004000); 4385 basic->bt3_lookup_table[10] = htole32(0xf0005000); 4386 basic->bt3_lookup_table[11] = htole32(0xf0005000); 4387 basic->reduce_txpower = 0; /* as not implemented */ 4388 basic->valid = IWN_BT_ALL_VALID_MASK; 4389 4390 DPRINTF(("configuring advanced bluetooth coexistence v1\n")); 4391 error = iwn_cmd(sc, IWN_CMD_BT_COEX, basic, len, 0); 4392 if (error != 0) { 4393 aprint_error_dev(sc->sc_dev, 4394 "could not configure advanced bluetooth coexistence\n"); 4395 return error; 4396 } 4397 4398 error = iwn_config_bt_coex_prio_table(sc); 4399 if (error != 0) { 4400 aprint_error_dev(sc->sc_dev, 4401 "could not configure send BT priority table\n"); 4402 return error; 4403 } 4404 4405 /* Force BT state machine change */ 4406 memset(&btprot, 0, sizeof btprot); 4407 btprot.open = 1; 4408 btprot.type = 1; 4409 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4410 if (error != 0) { 4411 aprint_error_dev(sc->sc_dev, "could not open BT protcol\n"); 4412 return error; 4413 } 4414 4415 btprot.open = 0; 4416 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof btprot, 1); 4417 if (error != 0) { 4418 aprint_error_dev(sc->sc_dev, "could not close BT protcol\n"); 4419 return error; 4420 } 4421 return 0; 4422 } 4423 4424 static int 4425 iwn_config_bt_coex_adv1(struct iwn_softc *sc) 4426 { 4427 struct iwn_bt_adv1 d; 4428 4429 memset(&d, 0, sizeof d); 4430 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4431 d.tx_prio_boost = 0; 4432 d.rx_prio_boost = 0; 4433 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4434 } 4435 4436 static int 4437 iwn_config_bt_coex_adv2(struct iwn_softc *sc) 4438 { 4439 struct iwn_bt_adv2 d; 4440 4441 memset(&d, 0, sizeof d); 4442 d.prio_boost = IWN_BT_PRIO_BOOST_DEF; 4443 d.tx_prio_boost = 0; 4444 d.rx_prio_boost = 0; 4445 return iwn_config_bt_coex_adv_config(sc, &d.basic, sizeof d); 4446 } 4447 4448 static int 4449 iwn_config(struct iwn_softc *sc) 4450 { 4451 struct iwn_ops *ops = &sc->ops; 4452 struct ieee80211com *ic = &sc->sc_ic; 4453 struct ifnet *ifp = ic->ic_ifp; 4454 uint32_t txmask; 4455 uint16_t rxchain; 4456 int error; 4457 4458 error = ops->config_bt_coex(sc); 4459 if (error != 0) { 4460 aprint_error_dev(sc->sc_dev, 4461 "could not configure bluetooth coexistence\n"); 4462 return error; 4463 } 4464 4465 /* Set radio temperature sensor offset. */ 4466 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4467 error = iwn6000_temp_offset_calib(sc); 4468 if (error != 0) { 4469 aprint_error_dev(sc->sc_dev, 4470 "could not set temperature offset\n"); 4471 return error; 4472 } 4473 } 4474 4475 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4476 sc->hw_type == IWN_HW_REV_TYPE_2000 || 4477 sc->hw_type == IWN_HW_REV_TYPE_135 || 4478 sc->hw_type == IWN_HW_REV_TYPE_105) { 4479 error = iwn2000_temp_offset_calib(sc); 4480 if (error != 0) { 4481 aprint_error_dev(sc->sc_dev, 4482 "could not set temperature offset\n"); 4483 return error; 4484 } 4485 } 4486 4487 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 4488 sc->hw_type == IWN_HW_REV_TYPE_6005) { 4489 /* Configure runtime DC calibration. */ 4490 error = iwn5000_runtime_calib(sc); 4491 if (error != 0) { 4492 aprint_error_dev(sc->sc_dev, 4493 "could not configure runtime calibration\n"); 4494 return error; 4495 } 4496 } 4497 4498 /* Configure valid TX chains for 5000 Series. */ 4499 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4500 txmask = htole32(sc->txchainmask); 4501 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 4502 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 4503 sizeof txmask, 0); 4504 if (error != 0) { 4505 aprint_error_dev(sc->sc_dev, 4506 "could not configure valid TX chains\n"); 4507 return error; 4508 } 4509 } 4510 4511 /* Set mode, channel, RX filter and enable RX. */ 4512 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 4513 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4514 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 4515 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 4516 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 4517 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4518 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) 4519 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4520 switch (ic->ic_opmode) { 4521 case IEEE80211_M_STA: 4522 sc->rxon.mode = IWN_MODE_STA; 4523 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 4524 break; 4525 case IEEE80211_M_MONITOR: 4526 sc->rxon.mode = IWN_MODE_MONITOR; 4527 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 4528 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 4529 break; 4530 default: 4531 /* Should not get there. */ 4532 break; 4533 } 4534 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 4535 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 4536 sc->rxon.ht_single_mask = 0xff; 4537 sc->rxon.ht_dual_mask = 0xff; 4538 sc->rxon.ht_triple_mask = 0xff; 4539 rxchain = 4540 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4541 IWN_RXCHAIN_MIMO_COUNT(2) | 4542 IWN_RXCHAIN_IDLE_COUNT(2); 4543 sc->rxon.rxchain = htole16(rxchain); 4544 DPRINTF(("setting configuration\n")); 4545 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 4546 if (error != 0) { 4547 aprint_error_dev(sc->sc_dev, 4548 "RXON command failed\n"); 4549 return error; 4550 } 4551 4552 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 4553 aprint_error_dev(sc->sc_dev, 4554 "could not add broadcast node\n"); 4555 return error; 4556 } 4557 4558 /* Configuration has changed, set TX power accordingly. */ 4559 if ((error = ops->set_txpower(sc, 0)) != 0) { 4560 aprint_error_dev(sc->sc_dev, 4561 "could not set TX power\n"); 4562 return error; 4563 } 4564 4565 if ((error = iwn_set_critical_temp(sc)) != 0) { 4566 aprint_error_dev(sc->sc_dev, 4567 "could not set critical temperature\n"); 4568 return error; 4569 } 4570 4571 /* Set power saving level to CAM during initialization. */ 4572 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 4573 aprint_error_dev(sc->sc_dev, 4574 "could not set power saving level\n"); 4575 return error; 4576 } 4577 return 0; 4578 } 4579 4580 static uint16_t 4581 iwn_get_active_dwell_time(struct iwn_softc *sc, uint16_t flags, 4582 uint8_t n_probes) 4583 { 4584 /* No channel? Default to 2GHz settings */ 4585 if (flags & IEEE80211_CHAN_2GHZ) 4586 return IWN_ACTIVE_DWELL_TIME_2GHZ + 4587 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1); 4588 4589 /* 5GHz dwell time */ 4590 return IWN_ACTIVE_DWELL_TIME_5GHZ + 4591 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1); 4592 } 4593 4594 /* 4595 * Limit the total dwell time to 85% of the beacon interval. 4596 * 4597 * Returns the dwell time in milliseconds. 4598 */ 4599 static uint16_t 4600 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 4601 { 4602 struct ieee80211com *ic = &sc->sc_ic; 4603 struct ieee80211_node *ni = ic->ic_bss; 4604 int bintval = 0; 4605 4606 /* bintval is in TU (1.024mS) */ 4607 if (ni != NULL) 4608 bintval = ni->ni_intval; 4609 4610 /* 4611 * If it's non-zero, we should calculate the minimum of 4612 * it and the DWELL_BASE. 4613 * 4614 * XXX Yes, the math should take into account that bintval 4615 * is 1.024mS, not 1mS.. 4616 */ 4617 if (bintval > 0) 4618 return MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)); 4619 4620 /* No association context? Default */ 4621 return IWN_PASSIVE_DWELL_BASE; 4622 } 4623 4624 static uint16_t 4625 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 4626 { 4627 uint16_t passive; 4628 if (flags & IEEE80211_CHAN_2GHZ) 4629 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 4630 else 4631 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 4632 4633 /* Clamp to the beacon interval if we're associated */ 4634 return iwn_limit_dwell(sc, passive); 4635 } 4636 4637 static int 4638 iwn_scan(struct iwn_softc *sc, uint16_t flags) 4639 { 4640 struct ieee80211com *ic = &sc->sc_ic; 4641 struct iwn_scan_hdr *hdr; 4642 struct iwn_cmd_data *tx; 4643 struct iwn_scan_essid *essid; 4644 struct iwn_scan_chan *chan; 4645 struct ieee80211_frame *wh; 4646 struct ieee80211_rateset *rs; 4647 struct ieee80211_channel *c; 4648 uint8_t *buf, *frm; 4649 uint16_t rxchain, dwell_active, dwell_passive; 4650 uint8_t txant; 4651 int buflen, error, is_active; 4652 4653 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 4654 if (buf == NULL) { 4655 aprint_error_dev(sc->sc_dev, 4656 "could not allocate buffer for scan command\n"); 4657 return ENOMEM; 4658 } 4659 hdr = (struct iwn_scan_hdr *)buf; 4660 /* 4661 * Move to the next channel if no frames are received within 10ms 4662 * after sending the probe request. 4663 */ 4664 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 4665 hdr->quiet_threshold = htole16(1); /* min # of packets */ 4666 4667 /* Select antennas for scanning. */ 4668 rxchain = 4669 IWN_RXCHAIN_VALID(sc->rxchainmask) | 4670 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 4671 IWN_RXCHAIN_DRIVER_FORCE; 4672 if ((flags & IEEE80211_CHAN_5GHZ) && 4673 sc->hw_type == IWN_HW_REV_TYPE_4965) { 4674 /* Ant A must be avoided in 5GHz because of an HW bug. */ 4675 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC); 4676 } else /* Use all available RX antennas. */ 4677 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 4678 hdr->rxchain = htole16(rxchain); 4679 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 4680 4681 tx = (struct iwn_cmd_data *)(hdr + 1); 4682 tx->flags = htole32(IWN_TX_AUTO_SEQ); 4683 tx->id = sc->broadcast_id; 4684 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4685 4686 if (flags & IEEE80211_CHAN_5GHZ) { 4687 hdr->crc_threshold = 0xffff; 4688 /* Send probe requests at 6Mbps. */ 4689 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 4690 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 4691 } else { 4692 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 4693 /* Send probe requests at 1Mbps. */ 4694 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 4695 tx->rflags = IWN_RFLAG_CCK; 4696 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 4697 } 4698 /* Use the first valid TX antenna. */ 4699 txant = IWN_LSB(sc->txchainmask); 4700 tx->rflags |= IWN_RFLAG_ANT(txant); 4701 4702 /* 4703 * Only do active scanning if we're announcing a probe request 4704 * for a given SSID (or more, if we ever add it to the driver.) 4705 */ 4706 is_active = 0; 4707 4708 essid = (struct iwn_scan_essid *)(tx + 1); 4709 if (ic->ic_des_esslen != 0) { 4710 essid[0].id = IEEE80211_ELEMID_SSID; 4711 essid[0].len = ic->ic_des_esslen; 4712 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 4713 4714 is_active = 1; 4715 } 4716 /* 4717 * Build a probe request frame. Most of the following code is a 4718 * copy & paste of what is done in net80211. 4719 */ 4720 wh = (struct ieee80211_frame *)(essid + 20); 4721 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 4722 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 4723 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 4724 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 4725 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 4726 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 4727 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 4728 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 4729 4730 frm = (uint8_t *)(wh + 1); 4731 frm = ieee80211_add_ssid(frm, NULL, 0); 4732 frm = ieee80211_add_rates(frm, rs); 4733 #ifndef IEEE80211_NO_HT 4734 if (ic->ic_flags & IEEE80211_F_HTON) 4735 frm = ieee80211_add_htcaps(frm, ic); 4736 #endif 4737 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 4738 frm = ieee80211_add_xrates(frm, rs); 4739 4740 /* Set length of probe request. */ 4741 tx->len = htole16(frm - (uint8_t *)wh); 4742 4743 4744 /* 4745 * If active scanning is requested but a certain channel is 4746 * marked passive, we can do active scanning if we detect 4747 * transmissions. 4748 * 4749 * There is an issue with some firmware versions that triggers 4750 * a sysassert on a "good CRC threshold" of zero (== disabled), 4751 * on a radar channel even though this means that we should NOT 4752 * send probes. 4753 * 4754 * The "good CRC threshold" is the number of frames that we 4755 * need to receive during our dwell time on a channel before 4756 * sending out probes -- setting this to a huge value will 4757 * mean we never reach it, but at the same time work around 4758 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 4759 * here instead of IWN_GOOD_CRC_TH_DISABLED. 4760 * 4761 * This was fixed in later versions along with some other 4762 * scan changes, and the threshold behaves as a flag in those 4763 * versions. 4764 */ 4765 4766 /* 4767 * If we're doing active scanning, set the crc_threshold 4768 * to a suitable value. This is different to active veruss 4769 * passive scanning depending upon the channel flags; the 4770 * firmware will obey that particular check for us. 4771 */ 4772 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 4773 hdr->crc_threshold = is_active ? 4774 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 4775 else 4776 hdr->crc_threshold = is_active ? 4777 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 4778 4779 chan = (struct iwn_scan_chan *)frm; 4780 for (c = &ic->ic_channels[1]; 4781 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 4782 if ((c->ic_flags & flags) != flags) 4783 continue; 4784 4785 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 4786 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 4787 chan->flags = 0; 4788 if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) 4789 chan->flags |= htole32(IWN_CHAN_ACTIVE); 4790 if (ic->ic_des_esslen != 0) 4791 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 4792 4793 /* 4794 * Calculate the active/passive dwell times. 4795 */ 4796 4797 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 4798 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 4799 4800 /* Make sure they're valid */ 4801 if (dwell_passive <= dwell_active) 4802 dwell_passive = dwell_active + 1; 4803 4804 chan->active = htole16(dwell_active); 4805 chan->passive = htole16(dwell_passive); 4806 4807 chan->dsp_gain = 0x6e; 4808 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4809 chan->rf_gain = 0x3b; 4810 } else { 4811 chan->rf_gain = 0x28; 4812 } 4813 hdr->nchan++; 4814 chan++; 4815 } 4816 4817 buflen = (uint8_t *)chan - buf; 4818 hdr->len = htole16(buflen); 4819 4820 DPRINTF(("sending scan command nchan=%d\n", hdr->nchan)); 4821 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 4822 free(buf, M_DEVBUF); 4823 return error; 4824 } 4825 4826 static int 4827 iwn_auth(struct iwn_softc *sc) 4828 { 4829 struct iwn_ops *ops = &sc->ops; 4830 struct ieee80211com *ic = &sc->sc_ic; 4831 struct ieee80211_node *ni = ic->ic_bss; 4832 int error; 4833 4834 /* Update adapter configuration. */ 4835 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 4836 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 4837 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 4838 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 4839 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 4840 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4841 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4842 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4843 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4844 switch (ic->ic_curmode) { 4845 case IEEE80211_MODE_11A: 4846 sc->rxon.cck_mask = 0; 4847 sc->rxon.ofdm_mask = 0x15; 4848 break; 4849 case IEEE80211_MODE_11B: 4850 sc->rxon.cck_mask = 0x03; 4851 sc->rxon.ofdm_mask = 0; 4852 break; 4853 default: /* Assume 802.11b/g. */ 4854 sc->rxon.cck_mask = 0x0f; 4855 sc->rxon.ofdm_mask = 0x15; 4856 } 4857 DPRINTF(("rxon chan %d flags %x cck %x ofdm %x\n", sc->rxon.chan, 4858 sc->rxon.flags, sc->rxon.cck_mask, sc->rxon.ofdm_mask)); 4859 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4860 if (error != 0) { 4861 aprint_error_dev(sc->sc_dev, 4862 "RXON command failed\n"); 4863 return error; 4864 } 4865 4866 /* Configuration has changed, set TX power accordingly. */ 4867 if ((error = ops->set_txpower(sc, 1)) != 0) { 4868 aprint_error_dev(sc->sc_dev, 4869 "could not set TX power\n"); 4870 return error; 4871 } 4872 /* 4873 * Reconfiguring RXON clears the firmware nodes table so we must 4874 * add the broadcast node again. 4875 */ 4876 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 4877 aprint_error_dev(sc->sc_dev, 4878 "could not add broadcast node\n"); 4879 return error; 4880 } 4881 return 0; 4882 } 4883 4884 static int 4885 iwn_run(struct iwn_softc *sc) 4886 { 4887 struct iwn_ops *ops = &sc->ops; 4888 struct ieee80211com *ic = &sc->sc_ic; 4889 struct ieee80211_node *ni = ic->ic_bss; 4890 struct iwn_node_info node; 4891 int error; 4892 4893 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4894 /* Link LED blinks while monitoring. */ 4895 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 4896 return 0; 4897 } 4898 if ((error = iwn_set_timing(sc, ni)) != 0) { 4899 aprint_error_dev(sc->sc_dev, 4900 "could not set timing\n"); 4901 return error; 4902 } 4903 4904 /* Update adapter configuration. */ 4905 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 4906 /* Short preamble and slot time are negotiated when associating. */ 4907 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 4908 if (ic->ic_flags & IEEE80211_F_SHSLOT) 4909 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 4910 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 4911 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 4912 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 4913 DPRINTF(("rxon chan %d flags %x\n", sc->rxon.chan, sc->rxon.flags)); 4914 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4915 if (error != 0) { 4916 aprint_error_dev(sc->sc_dev, 4917 "could not update configuration\n"); 4918 return error; 4919 } 4920 4921 /* Configuration has changed, set TX power accordingly. */ 4922 if ((error = ops->set_txpower(sc, 1)) != 0) { 4923 aprint_error_dev(sc->sc_dev, 4924 "could not set TX power\n"); 4925 return error; 4926 } 4927 4928 /* Fake a join to initialize the TX rate. */ 4929 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 4930 iwn_newassoc(ni, 1); 4931 4932 /* Add BSS node. */ 4933 memset(&node, 0, sizeof node); 4934 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 4935 node.id = IWN_ID_BSS; 4936 #ifdef notyet 4937 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) | 4938 IWN_AMDPU_DENSITY(5)); /* 2us */ 4939 #endif 4940 DPRINTF(("adding BSS node\n")); 4941 error = ops->add_node(sc, &node, 1); 4942 if (error != 0) { 4943 aprint_error_dev(sc->sc_dev, 4944 "could not add BSS node\n"); 4945 return error; 4946 } 4947 DPRINTF(("setting link quality for node %d\n", node.id)); 4948 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 4949 aprint_error_dev(sc->sc_dev, 4950 "could not setup link quality for node %d\n", node.id); 4951 return error; 4952 } 4953 4954 if ((error = iwn_init_sensitivity(sc)) != 0) { 4955 aprint_error_dev(sc->sc_dev, 4956 "could not set sensitivity\n"); 4957 return error; 4958 } 4959 /* Start periodic calibration timer. */ 4960 sc->calib.state = IWN_CALIB_STATE_ASSOC; 4961 sc->calib_cnt = 0; 4962 callout_schedule(&sc->calib_to, hz/2); 4963 4964 /* Link LED always on while associated. */ 4965 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 4966 return 0; 4967 } 4968 4969 #ifdef IWN_HWCRYPTO 4970 /* 4971 * We support CCMP hardware encryption/decryption of unicast frames only. 4972 * HW support for TKIP really sucks. We should let TKIP die anyway. 4973 */ 4974 static int 4975 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 4976 struct ieee80211_key *k) 4977 { 4978 struct iwn_softc *sc = ic->ic_softc; 4979 struct iwn_ops *ops = &sc->ops; 4980 struct iwn_node *wn = (void *)ni; 4981 struct iwn_node_info node; 4982 uint16_t kflags; 4983 4984 if ((k->k_flags & IEEE80211_KEY_GROUP) || 4985 k->k_cipher != IEEE80211_CIPHER_CCMP) 4986 return ieee80211_set_key(ic, ni, k); 4987 4988 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 4989 if (k->k_flags & IEEE80211_KEY_GROUP) 4990 kflags |= IWN_KFLAG_GROUP; 4991 4992 memset(&node, 0, sizeof node); 4993 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 4994 sc->broadcast_id : wn->id; 4995 node.control = IWN_NODE_UPDATE; 4996 node.flags = IWN_FLAG_SET_KEY; 4997 node.kflags = htole16(kflags); 4998 node.kid = k->k_id; 4999 memcpy(node.key, k->k_key, k->k_len); 5000 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 5001 return ops->add_node(sc, &node, 1); 5002 } 5003 5004 static void 5005 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5006 struct ieee80211_key *k) 5007 { 5008 struct iwn_softc *sc = ic->ic_softc; 5009 struct iwn_ops *ops = &sc->ops; 5010 struct iwn_node *wn = (void *)ni; 5011 struct iwn_node_info node; 5012 5013 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5014 k->k_cipher != IEEE80211_CIPHER_CCMP) { 5015 /* See comment about other ciphers above. */ 5016 ieee80211_delete_key(ic, ni, k); 5017 return; 5018 } 5019 if (ic->ic_state != IEEE80211_S_RUN) 5020 return; /* Nothing to do. */ 5021 memset(&node, 0, sizeof node); 5022 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5023 sc->broadcast_id : wn->id; 5024 node.control = IWN_NODE_UPDATE; 5025 node.flags = IWN_FLAG_SET_KEY; 5026 node.kflags = htole16(IWN_KFLAG_INVALID); 5027 node.kid = 0xff; 5028 DPRINTF(("delete keys for node %d\n", node.id)); 5029 (void)ops->add_node(sc, &node, 1); 5030 } 5031 #endif 5032 5033 /* XXX Added for NetBSD (copied from rev 1.39). */ 5034 5035 static int 5036 iwn_wme_update(struct ieee80211com *ic) 5037 { 5038 #define IWN_EXP2(v) htole16((1 << (v)) - 1) 5039 #define IWN_USEC(v) htole16(IEEE80211_TXOP_TO_US(v)) 5040 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5041 const struct wmeParams *wmep; 5042 struct iwn_edca_params cmd; 5043 int ac; 5044 5045 /* don't override default WME values if WME is not actually enabled */ 5046 if (!(ic->ic_flags & IEEE80211_F_WME)) 5047 return 0; 5048 cmd.flags = 0; 5049 for (ac = 0; ac < WME_NUM_AC; ac++) { 5050 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 5051 cmd.ac[ac].aifsn = wmep->wmep_aifsn; 5052 cmd.ac[ac].cwmin = IWN_EXP2(wmep->wmep_logcwmin); 5053 cmd.ac[ac].cwmax = IWN_EXP2(wmep->wmep_logcwmax); 5054 cmd.ac[ac].txoplimit = IWN_USEC(wmep->wmep_txopLimit); 5055 5056 DPRINTF(("setting WME for queue %d aifsn=%d cwmin=%d cwmax=%d " 5057 "txop=%d\n", ac, cmd.ac[ac].aifsn, 5058 cmd.ac[ac].cwmin, 5059 cmd.ac[ac].cwmax, cmd.ac[ac].txoplimit)); 5060 } 5061 return iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5062 #undef IWN_USEC 5063 #undef IWN_EXP2 5064 } 5065 5066 #ifndef IEEE80211_NO_HT 5067 /* 5068 * This function is called by upper layer when an ADDBA request is received 5069 * from another STA and before the ADDBA response is sent. 5070 */ 5071 static int 5072 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5073 uint8_t tid) 5074 { 5075 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5076 struct iwn_softc *sc = ic->ic_softc; 5077 struct iwn_ops *ops = &sc->ops; 5078 struct iwn_node *wn = (void *)ni; 5079 struct iwn_node_info node; 5080 5081 memset(&node, 0, sizeof node); 5082 node.id = wn->id; 5083 node.control = IWN_NODE_UPDATE; 5084 node.flags = IWN_FLAG_SET_ADDBA; 5085 node.addba_tid = tid; 5086 node.addba_ssn = htole16(ba->ba_winstart); 5087 DPRINTFN(2, ("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 5088 ba->ba_winstart)); 5089 return ops->add_node(sc, &node, 1); 5090 } 5091 5092 /* 5093 * This function is called by upper layer on teardown of an HT-immediate 5094 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5095 */ 5096 static void 5097 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5098 uint8_t tid) 5099 { 5100 struct iwn_softc *sc = ic->ic_softc; 5101 struct iwn_ops *ops = &sc->ops; 5102 struct iwn_node *wn = (void *)ni; 5103 struct iwn_node_info node; 5104 5105 memset(&node, 0, sizeof node); 5106 node.id = wn->id; 5107 node.control = IWN_NODE_UPDATE; 5108 node.flags = IWN_FLAG_SET_DELBA; 5109 node.delba_tid = tid; 5110 DPRINTFN(2, ("DELBA RA=%d TID=%d\n", wn->id, tid)); 5111 (void)ops->add_node(sc, &node, 1); 5112 } 5113 5114 /* 5115 * This function is called by upper layer when an ADDBA response is received 5116 * from another STA. 5117 */ 5118 static int 5119 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5120 uint8_t tid) 5121 { 5122 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5123 struct iwn_softc *sc = ic->ic_softc; 5124 struct iwn_ops *ops = &sc->ops; 5125 struct iwn_node *wn = (void *)ni; 5126 struct iwn_node_info node; 5127 int error; 5128 5129 /* Enable TX for the specified RA/TID. */ 5130 wn->disable_tid &= ~(1 << tid); 5131 memset(&node, 0, sizeof node); 5132 node.id = wn->id; 5133 node.control = IWN_NODE_UPDATE; 5134 node.flags = IWN_FLAG_SET_DISABLE_TID; 5135 node.disable_tid = htole16(wn->disable_tid); 5136 error = ops->add_node(sc, &node, 1); 5137 if (error != 0) 5138 return error; 5139 5140 if ((error = iwn_nic_lock(sc)) != 0) 5141 return error; 5142 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5143 iwn_nic_unlock(sc); 5144 return 0; 5145 } 5146 5147 static void 5148 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5149 uint8_t tid) 5150 { 5151 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5152 struct iwn_softc *sc = ic->ic_softc; 5153 struct iwn_ops *ops = &sc->ops; 5154 5155 if (iwn_nic_lock(sc) != 0) 5156 return; 5157 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5158 iwn_nic_unlock(sc); 5159 } 5160 5161 static void 5162 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5163 uint8_t tid, uint16_t ssn) 5164 { 5165 struct iwn_node *wn = (void *)ni; 5166 int qid = 7 + tid; 5167 5168 /* Stop TX scheduler while we're changing its configuration. */ 5169 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5170 IWN4965_TXQ_STATUS_CHGACT); 5171 5172 /* Assign RA/TID translation to the queue. */ 5173 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5174 wn->id << 4 | tid); 5175 5176 /* Enable chain-building mode for the queue. */ 5177 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5178 5179 /* Set starting sequence number from the ADDBA request. */ 5180 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5181 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5182 5183 /* Set scheduler window size. */ 5184 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5185 IWN_SCHED_WINSZ); 5186 /* Set scheduler frame limit. */ 5187 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5188 IWN_SCHED_LIMIT << 16); 5189 5190 /* Enable interrupts for the queue. */ 5191 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5192 5193 /* Mark the queue as active. */ 5194 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5195 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5196 iwn_tid2fifo[tid] << 1); 5197 } 5198 5199 static void 5200 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5201 { 5202 int qid = 7 + tid; 5203 5204 /* Stop TX scheduler while we're changing its configuration. */ 5205 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5206 IWN4965_TXQ_STATUS_CHGACT); 5207 5208 /* Set starting sequence number from the ADDBA request. */ 5209 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5210 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5211 5212 /* Disable interrupts for the queue. */ 5213 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5214 5215 /* Mark the queue as inactive. */ 5216 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5217 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5218 } 5219 5220 static void 5221 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5222 uint8_t tid, uint16_t ssn) 5223 { 5224 struct iwn_node *wn = (void *)ni; 5225 int qid = 10 + tid; 5226 5227 /* Stop TX scheduler while we're changing its configuration. */ 5228 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5229 IWN5000_TXQ_STATUS_CHGACT); 5230 5231 /* Assign RA/TID translation to the queue. */ 5232 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5233 wn->id << 4 | tid); 5234 5235 /* Enable chain-building mode for the queue. */ 5236 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5237 5238 /* Enable aggregation for the queue. */ 5239 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5240 5241 /* Set starting sequence number from the ADDBA request. */ 5242 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5243 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5244 5245 /* Set scheduler window size and frame limit. */ 5246 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5247 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5248 5249 /* Enable interrupts for the queue. */ 5250 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5251 5252 /* Mark the queue as active. */ 5253 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5254 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5255 } 5256 5257 static void 5258 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5259 { 5260 int qid = 10 + tid; 5261 5262 /* Stop TX scheduler while we're changing its configuration. */ 5263 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5264 IWN5000_TXQ_STATUS_CHGACT); 5265 5266 /* Disable aggregation for the queue. */ 5267 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5268 5269 /* Set starting sequence number from the ADDBA request. */ 5270 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5271 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5272 5273 /* Disable interrupts for the queue. */ 5274 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5275 5276 /* Mark the queue as inactive. */ 5277 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5278 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5279 } 5280 #endif /* !IEEE80211_NO_HT */ 5281 5282 /* 5283 * Query calibration tables from the initialization firmware. We do this 5284 * only once at first boot. Called from a process context. 5285 */ 5286 static int 5287 iwn5000_query_calibration(struct iwn_softc *sc) 5288 { 5289 struct iwn5000_calib_config cmd; 5290 int error; 5291 5292 memset(&cmd, 0, sizeof cmd); 5293 cmd.ucode.once.enable = 0xffffffff; 5294 cmd.ucode.once.start = 0xffffffff; 5295 cmd.ucode.once.send = 0xffffffff; 5296 cmd.ucode.flags = 0xffffffff; 5297 DPRINTF(("sending calibration query\n")); 5298 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5299 if (error != 0) 5300 return error; 5301 5302 /* Wait at most two seconds for calibration to complete. */ 5303 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5304 error = tsleep(sc, PCATCH, "iwncal", 2 * hz); 5305 return error; 5306 } 5307 5308 /* 5309 * Send calibration results to the runtime firmware. These results were 5310 * obtained on first boot from the initialization firmware. 5311 */ 5312 static int 5313 iwn5000_send_calibration(struct iwn_softc *sc) 5314 { 5315 int idx, error; 5316 5317 for (idx = 0; idx < 5; idx++) { 5318 if (sc->calibcmd[idx].buf == NULL) 5319 continue; /* No results available. */ 5320 DPRINTF(("send calibration result idx=%d len=%d\n", 5321 idx, sc->calibcmd[idx].len)); 5322 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5323 sc->calibcmd[idx].len, 0); 5324 if (error != 0) { 5325 aprint_error_dev(sc->sc_dev, 5326 "could not send calibration result\n"); 5327 return error; 5328 } 5329 } 5330 return 0; 5331 } 5332 5333 static int 5334 iwn5000_send_wimax_coex(struct iwn_softc *sc) 5335 { 5336 struct iwn5000_wimax_coex wimax; 5337 5338 #ifdef notyet 5339 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5340 /* Enable WiMAX coexistence for combo adapters. */ 5341 wimax.flags = 5342 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5343 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5344 IWN_WIMAX_COEX_STA_TABLE_VALID | 5345 IWN_WIMAX_COEX_ENABLE; 5346 memcpy(wimax.events, iwn6050_wimax_events, 5347 sizeof iwn6050_wimax_events); 5348 } else 5349 #endif 5350 { 5351 /* Disable WiMAX coexistence. */ 5352 wimax.flags = 0; 5353 memset(wimax.events, 0, sizeof wimax.events); 5354 } 5355 DPRINTF(("Configuring WiMAX coexistence\n")); 5356 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5357 } 5358 5359 static int 5360 iwn6000_temp_offset_calib(struct iwn_softc *sc) 5361 { 5362 struct iwn6000_phy_calib_temp_offset cmd; 5363 5364 memset(&cmd, 0, sizeof cmd); 5365 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 5366 cmd.ngroups = 1; 5367 cmd.isvalid = 1; 5368 if (sc->eeprom_temp != 0) 5369 cmd.offset = htole16(sc->eeprom_temp); 5370 else 5371 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5372 DPRINTF(("setting radio sensor offset to %d\n", le16toh(cmd.offset))); 5373 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5374 } 5375 5376 static int 5377 iwn2000_temp_offset_calib(struct iwn_softc *sc) 5378 { 5379 struct iwn2000_phy_calib_temp_offset cmd; 5380 5381 memset(&cmd, 0, sizeof cmd); 5382 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 5383 cmd.ngroups = 1; 5384 cmd.isvalid = 1; 5385 if (sc->eeprom_rawtemp != 0) { 5386 cmd.offset_low = htole16(sc->eeprom_rawtemp); 5387 cmd.offset_high = htole16(sc->eeprom_temp); 5388 } else { 5389 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 5390 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 5391 } 5392 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 5393 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 5394 le16toh(cmd.offset_low), le16toh(cmd.offset_high), 5395 le16toh(cmd.burnt_voltage_ref))); 5396 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5397 } 5398 5399 /* 5400 * This function is called after the runtime firmware notifies us of its 5401 * readiness (called in a process context). 5402 */ 5403 static int 5404 iwn4965_post_alive(struct iwn_softc *sc) 5405 { 5406 int error, qid; 5407 5408 if ((error = iwn_nic_lock(sc)) != 0) 5409 return error; 5410 5411 /* Clear TX scheduler state in SRAM. */ 5412 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5413 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5414 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5415 5416 /* Set physical address of TX scheduler rings (1KB aligned). */ 5417 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5418 5419 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5420 5421 /* Disable chain mode for all our 16 queues. */ 5422 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5423 5424 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5425 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5426 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5427 5428 /* Set scheduler window size. */ 5429 iwn_mem_write(sc, sc->sched_base + 5430 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 5431 /* Set scheduler frame limit. */ 5432 iwn_mem_write(sc, sc->sched_base + 5433 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5434 IWN_SCHED_LIMIT << 16); 5435 } 5436 5437 /* Enable interrupts for all our 16 queues. */ 5438 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 5439 /* Identify TX FIFO rings (0-7). */ 5440 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 5441 5442 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5443 for (qid = 0; qid < 7; qid++) { 5444 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 5445 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5446 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 5447 } 5448 iwn_nic_unlock(sc); 5449 return 0; 5450 } 5451 5452 /* 5453 * This function is called after the initialization or runtime firmware 5454 * notifies us of its readiness (called in a process context). 5455 */ 5456 static int 5457 iwn5000_post_alive(struct iwn_softc *sc) 5458 { 5459 int error, qid; 5460 5461 /* Switch to using ICT interrupt mode. */ 5462 iwn5000_ict_reset(sc); 5463 5464 if ((error = iwn_nic_lock(sc)) != 0) 5465 return error; 5466 5467 /* Clear TX scheduler state in SRAM. */ 5468 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5469 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 5470 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 5471 5472 /* Set physical address of TX scheduler rings (1KB aligned). */ 5473 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5474 5475 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5476 5477 /* Enable chain mode for all queues, except command queue. */ 5478 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 5479 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 5480 5481 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 5482 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 5483 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5484 5485 iwn_mem_write(sc, sc->sched_base + 5486 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 5487 /* Set scheduler window size and frame limit. */ 5488 iwn_mem_write(sc, sc->sched_base + 5489 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5490 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5491 } 5492 5493 /* Enable interrupts for all our 20 queues. */ 5494 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 5495 /* Identify TX FIFO rings (0-7). */ 5496 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 5497 5498 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 5499 for (qid = 0; qid < 7; qid++) { 5500 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 5501 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5502 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 5503 } 5504 iwn_nic_unlock(sc); 5505 5506 /* Configure WiMAX coexistence for combo adapters. */ 5507 error = iwn5000_send_wimax_coex(sc); 5508 if (error != 0) { 5509 aprint_error_dev(sc->sc_dev, 5510 "could not configure WiMAX coexistence\n"); 5511 return error; 5512 } 5513 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 5514 struct iwn5000_phy_calib_crystal cmd; 5515 5516 /* Perform crystal calibration. */ 5517 memset(&cmd, 0, sizeof cmd); 5518 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5519 cmd.ngroups = 1; 5520 cmd.isvalid = 1; 5521 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5522 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5523 DPRINTF(("sending crystal calibration %d, %d\n", 5524 cmd.cap_pin[0], cmd.cap_pin[1])); 5525 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5526 if (error != 0) { 5527 aprint_error_dev(sc->sc_dev, 5528 "crystal calibration failed\n"); 5529 return error; 5530 } 5531 } 5532 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 5533 /* Query calibration from the initialization firmware. */ 5534 if ((error = iwn5000_query_calibration(sc)) != 0) { 5535 aprint_error_dev(sc->sc_dev, 5536 "could not query calibration\n"); 5537 return error; 5538 } 5539 /* 5540 * We have the calibration results now, reboot with the 5541 * runtime firmware (call ourselves recursively!) 5542 */ 5543 iwn_hw_stop(sc); 5544 error = iwn_hw_init(sc); 5545 } else { 5546 /* Send calibration results to runtime firmware. */ 5547 error = iwn5000_send_calibration(sc); 5548 } 5549 return error; 5550 } 5551 5552 /* 5553 * The firmware boot code is small and is intended to be copied directly into 5554 * the NIC internal memory (no DMA transfer). 5555 */ 5556 static int 5557 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 5558 { 5559 int error, ntries; 5560 5561 size /= sizeof (uint32_t); 5562 5563 if ((error = iwn_nic_lock(sc)) != 0) 5564 return error; 5565 5566 /* Copy microcode image into NIC memory. */ 5567 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 5568 (const uint32_t *)ucode, size); 5569 5570 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 5571 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 5572 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 5573 5574 /* Start boot load now. */ 5575 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 5576 5577 /* Wait for transfer to complete. */ 5578 for (ntries = 0; ntries < 1000; ntries++) { 5579 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 5580 IWN_BSM_WR_CTRL_START)) 5581 break; 5582 DELAY(10); 5583 } 5584 if (ntries == 1000) { 5585 aprint_error_dev(sc->sc_dev, 5586 "could not load boot firmware\n"); 5587 iwn_nic_unlock(sc); 5588 return ETIMEDOUT; 5589 } 5590 5591 /* Enable boot after power up. */ 5592 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 5593 5594 iwn_nic_unlock(sc); 5595 return 0; 5596 } 5597 5598 static int 5599 iwn4965_load_firmware(struct iwn_softc *sc) 5600 { 5601 struct iwn_fw_info *fw = &sc->fw; 5602 struct iwn_dma_info *dma = &sc->fw_dma; 5603 int error; 5604 5605 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 5606 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 5607 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 5608 BUS_DMASYNC_PREWRITE); 5609 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5610 fw->init.text, fw->init.textsz); 5611 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5612 fw->init.textsz, BUS_DMASYNC_PREWRITE); 5613 5614 /* Tell adapter where to find initialization sections. */ 5615 if ((error = iwn_nic_lock(sc)) != 0) 5616 return error; 5617 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5618 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 5619 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5620 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5621 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 5622 iwn_nic_unlock(sc); 5623 5624 /* Load firmware boot code. */ 5625 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 5626 if (error != 0) { 5627 aprint_error_dev(sc->sc_dev, 5628 "could not load boot firmware\n"); 5629 return error; 5630 } 5631 /* Now press "execute". */ 5632 IWN_WRITE(sc, IWN_RESET, 0); 5633 5634 /* Wait at most one second for first alive notification. */ 5635 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 5636 aprint_error_dev(sc->sc_dev, 5637 "timeout waiting for adapter to initialize\n"); 5638 return error; 5639 } 5640 5641 /* Retrieve current temperature for initial TX power calibration. */ 5642 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 5643 sc->temp = iwn4965_get_temperature(sc); 5644 5645 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 5646 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 5647 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 5648 BUS_DMASYNC_PREWRITE); 5649 memcpy((char *)dma->vaddr + IWN4965_FW_DATA_MAXSZ, 5650 fw->main.text, fw->main.textsz); 5651 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 5652 fw->main.textsz, BUS_DMASYNC_PREWRITE); 5653 5654 /* Tell adapter where to find runtime sections. */ 5655 if ((error = iwn_nic_lock(sc)) != 0) 5656 return error; 5657 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 5658 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 5659 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 5660 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 5661 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 5662 IWN_FW_UPDATED | fw->main.textsz); 5663 iwn_nic_unlock(sc); 5664 5665 return 0; 5666 } 5667 5668 static int 5669 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 5670 const uint8_t *section, int size) 5671 { 5672 struct iwn_dma_info *dma = &sc->fw_dma; 5673 int error; 5674 5675 /* Copy firmware section into pre-allocated DMA-safe memory. */ 5676 memcpy(dma->vaddr, section, size); 5677 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 5678 5679 if ((error = iwn_nic_lock(sc)) != 0) 5680 return error; 5681 5682 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5683 IWN_FH_TX_CONFIG_DMA_PAUSE); 5684 5685 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 5686 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 5687 IWN_LOADDR(dma->paddr)); 5688 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 5689 IWN_HIADDR(dma->paddr) << 28 | size); 5690 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 5691 IWN_FH_TXBUF_STATUS_TBNUM(1) | 5692 IWN_FH_TXBUF_STATUS_TBIDX(1) | 5693 IWN_FH_TXBUF_STATUS_TFBD_VALID); 5694 5695 /* Kick Flow Handler to start DMA transfer. */ 5696 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 5697 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 5698 5699 iwn_nic_unlock(sc); 5700 5701 /* Wait at most five seconds for FH DMA transfer to complete. */ 5702 return tsleep(sc, PCATCH, "iwninit", 5 * hz); 5703 } 5704 5705 static int 5706 iwn5000_load_firmware(struct iwn_softc *sc) 5707 { 5708 struct iwn_fw_part *fw; 5709 int error; 5710 5711 /* Load the initialization firmware on first boot only. */ 5712 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 5713 &sc->fw.main : &sc->fw.init; 5714 5715 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 5716 fw->text, fw->textsz); 5717 if (error != 0) { 5718 aprint_error_dev(sc->sc_dev, 5719 "could not load firmware %s section\n", ".text"); 5720 return error; 5721 } 5722 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 5723 fw->data, fw->datasz); 5724 if (error != 0) { 5725 aprint_error_dev(sc->sc_dev, 5726 "could not load firmware %s section\n", ".data"); 5727 return error; 5728 } 5729 5730 /* Now press "execute". */ 5731 IWN_WRITE(sc, IWN_RESET, 0); 5732 return 0; 5733 } 5734 5735 /* 5736 * Extract text and data sections from a legacy firmware image. 5737 */ 5738 static int 5739 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 5740 { 5741 const uint32_t *ptr; 5742 size_t hdrlen = 24; 5743 uint32_t rev; 5744 5745 ptr = (const uint32_t *)fw->data; 5746 rev = le32toh(*ptr++); 5747 5748 sc->ucode_rev = rev; 5749 5750 /* Check firmware API version. */ 5751 if (IWN_FW_API(rev) <= 1) { 5752 aprint_error_dev(sc->sc_dev, 5753 "bad firmware, need API version >=2\n"); 5754 return EINVAL; 5755 } 5756 if (IWN_FW_API(rev) >= 3) { 5757 /* Skip build number (version 2 header). */ 5758 hdrlen += 4; 5759 ptr++; 5760 } 5761 if (fw->size < hdrlen) { 5762 aprint_error_dev(sc->sc_dev, 5763 "firmware too short: %zd bytes\n", fw->size); 5764 return EINVAL; 5765 } 5766 fw->main.textsz = le32toh(*ptr++); 5767 fw->main.datasz = le32toh(*ptr++); 5768 fw->init.textsz = le32toh(*ptr++); 5769 fw->init.datasz = le32toh(*ptr++); 5770 fw->boot.textsz = le32toh(*ptr++); 5771 5772 /* Check that all firmware sections fit. */ 5773 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 5774 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 5775 aprint_error_dev(sc->sc_dev, 5776 "firmware too short: %zd bytes\n", fw->size); 5777 return EINVAL; 5778 } 5779 5780 /* Get pointers to firmware sections. */ 5781 fw->main.text = (const uint8_t *)ptr; 5782 fw->main.data = fw->main.text + fw->main.textsz; 5783 fw->init.text = fw->main.data + fw->main.datasz; 5784 fw->init.data = fw->init.text + fw->init.textsz; 5785 fw->boot.text = fw->init.data + fw->init.datasz; 5786 return 0; 5787 } 5788 5789 /* 5790 * Extract text and data sections from a TLV firmware image. 5791 */ 5792 static int 5793 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 5794 uint16_t alt) 5795 { 5796 const struct iwn_fw_tlv_hdr *hdr; 5797 const struct iwn_fw_tlv *tlv; 5798 const uint8_t *ptr, *end; 5799 uint64_t altmask; 5800 uint32_t len; 5801 5802 if (fw->size < sizeof (*hdr)) { 5803 aprint_error_dev(sc->sc_dev, 5804 "firmware too short: %zd bytes\n", fw->size); 5805 return EINVAL; 5806 } 5807 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 5808 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 5809 aprint_error_dev(sc->sc_dev, 5810 "bad firmware signature 0x%08x\n", le32toh(hdr->signature)); 5811 return EINVAL; 5812 } 5813 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 5814 le32toh(hdr->build))); 5815 sc->ucode_rev = le32toh(hdr->rev); 5816 5817 /* 5818 * Select the closest supported alternative that is less than 5819 * or equal to the specified one. 5820 */ 5821 altmask = le64toh(hdr->altmask); 5822 while (alt > 0 && !(altmask & (1ULL << alt))) 5823 alt--; /* Downgrade. */ 5824 DPRINTF(("using alternative %d\n", alt)); 5825 5826 ptr = (const uint8_t *)(hdr + 1); 5827 end = (const uint8_t *)(fw->data + fw->size); 5828 5829 /* Parse type-length-value fields. */ 5830 while (ptr + sizeof (*tlv) <= end) { 5831 tlv = (const struct iwn_fw_tlv *)ptr; 5832 len = le32toh(tlv->len); 5833 5834 ptr += sizeof (*tlv); 5835 if (ptr + len > end) { 5836 aprint_error_dev(sc->sc_dev, 5837 "firmware too short: %zd bytes\n", fw->size); 5838 return EINVAL; 5839 } 5840 /* Skip other alternatives. */ 5841 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 5842 goto next; 5843 5844 switch (le16toh(tlv->type)) { 5845 case IWN_FW_TLV_MAIN_TEXT: 5846 fw->main.text = ptr; 5847 fw->main.textsz = len; 5848 break; 5849 case IWN_FW_TLV_MAIN_DATA: 5850 fw->main.data = ptr; 5851 fw->main.datasz = len; 5852 break; 5853 case IWN_FW_TLV_INIT_TEXT: 5854 fw->init.text = ptr; 5855 fw->init.textsz = len; 5856 break; 5857 case IWN_FW_TLV_INIT_DATA: 5858 fw->init.data = ptr; 5859 fw->init.datasz = len; 5860 break; 5861 case IWN_FW_TLV_BOOT_TEXT: 5862 fw->boot.text = ptr; 5863 fw->boot.textsz = len; 5864 break; 5865 case IWN_FW_TLV_ENH_SENS: 5866 if (len != 0) { 5867 aprint_error_dev(sc->sc_dev, 5868 "TLV type %d has invalid size %u\n", 5869 le16toh(tlv->type), len); 5870 goto next; 5871 } 5872 sc->sc_flags |= IWN_FLAG_ENH_SENS; 5873 break; 5874 case IWN_FW_TLV_PHY_CALIB: 5875 if (len != sizeof(uint32_t)) { 5876 aprint_error_dev(sc->sc_dev, 5877 "TLV type %d has invalid size %u\n", 5878 le16toh(tlv->type), len); 5879 goto next; 5880 } 5881 if (le32toh(*ptr) <= IWN5000_PHY_CALIB_MAX) { 5882 sc->reset_noise_gain = le32toh(*ptr); 5883 sc->noise_gain = le32toh(*ptr) + 1; 5884 } 5885 break; 5886 case IWN_FW_TLV_FLAGS: 5887 if (len < sizeof(uint32_t)) 5888 break; 5889 if (len % sizeof(uint32_t)) 5890 break; 5891 sc->tlv_feature_flags = le32toh(*ptr); 5892 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 5893 break; 5894 default: 5895 DPRINTF(("TLV type %d not handled\n", 5896 le16toh(tlv->type))); 5897 break; 5898 } 5899 next: /* TLV fields are 32-bit aligned. */ 5900 ptr += (len + 3) & ~3; 5901 } 5902 return 0; 5903 } 5904 5905 static int 5906 iwn_read_firmware(struct iwn_softc *sc) 5907 { 5908 struct iwn_fw_info *fw = &sc->fw; 5909 firmware_handle_t fwh; 5910 int error; 5911 5912 /* 5913 * Some PHY calibration commands are firmware-dependent; these 5914 * are the default values that will be overridden if 5915 * necessary. 5916 */ 5917 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 5918 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 5919 5920 /* Initialize for error returns */ 5921 fw->data = NULL; 5922 fw->size = 0; 5923 5924 /* Open firmware image. */ 5925 if ((error = firmware_open("if_iwn", sc->fwname, &fwh)) != 0) { 5926 aprint_error_dev(sc->sc_dev, 5927 "could not get firmware handle %s\n", sc->fwname); 5928 return error; 5929 } 5930 fw->size = firmware_get_size(fwh); 5931 if (fw->size < sizeof (uint32_t)) { 5932 aprint_error_dev(sc->sc_dev, 5933 "firmware too short: %zd bytes\n", fw->size); 5934 firmware_close(fwh); 5935 return EINVAL; 5936 } 5937 5938 /* Read the firmware. */ 5939 fw->data = firmware_malloc(fw->size); 5940 if (fw->data == NULL) { 5941 aprint_error_dev(sc->sc_dev, 5942 "not enough memory to stock firmware %s\n", sc->fwname); 5943 firmware_close(fwh); 5944 return ENOMEM; 5945 } 5946 error = firmware_read(fwh, 0, fw->data, fw->size); 5947 firmware_close(fwh); 5948 if (error != 0) { 5949 aprint_error_dev(sc->sc_dev, 5950 "could not read firmware %s\n", sc->fwname); 5951 goto out; 5952 } 5953 5954 /* Retrieve text and data sections. */ 5955 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 5956 error = iwn_read_firmware_leg(sc, fw); 5957 else 5958 error = iwn_read_firmware_tlv(sc, fw, 1); 5959 if (error != 0) { 5960 aprint_error_dev(sc->sc_dev, 5961 "could not read firmware sections\n"); 5962 goto out; 5963 } 5964 5965 /* Make sure text and data sections fit in hardware memory. */ 5966 if (fw->main.textsz > sc->fw_text_maxsz || 5967 fw->main.datasz > sc->fw_data_maxsz || 5968 fw->init.textsz > sc->fw_text_maxsz || 5969 fw->init.datasz > sc->fw_data_maxsz || 5970 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 5971 (fw->boot.textsz & 3) != 0) { 5972 aprint_error_dev(sc->sc_dev, 5973 "firmware sections too large\n"); 5974 goto out; 5975 } 5976 5977 /* We can proceed with loading the firmware. */ 5978 return 0; 5979 out: 5980 firmware_free(fw->data, fw->size); 5981 fw->data = NULL; 5982 fw->size = 0; 5983 return error ? error : EINVAL; 5984 } 5985 5986 static int 5987 iwn_clock_wait(struct iwn_softc *sc) 5988 { 5989 int ntries; 5990 5991 /* Set "initialization complete" bit. */ 5992 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 5993 5994 /* Wait for clock stabilization. */ 5995 for (ntries = 0; ntries < 2500; ntries++) { 5996 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 5997 return 0; 5998 DELAY(10); 5999 } 6000 aprint_error_dev(sc->sc_dev, 6001 "timeout waiting for clock stabilization\n"); 6002 return ETIMEDOUT; 6003 } 6004 6005 static int 6006 iwn_apm_init(struct iwn_softc *sc) 6007 { 6008 pcireg_t reg; 6009 int error; 6010 6011 /* Disable L0s exit timer (NMI bug workaround). */ 6012 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6013 /* Don't wait for ICH L0s (ICH bug workaround). */ 6014 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6015 6016 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6017 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6018 6019 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6020 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6021 6022 /* Retrieve PCIe Active State Power Management (ASPM). */ 6023 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 6024 sc->sc_cap_off + PCIE_LCSR); 6025 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6026 if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 6027 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6028 else 6029 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6030 6031 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6032 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6033 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6034 6035 /* Wait for clock stabilization before accessing prph. */ 6036 if ((error = iwn_clock_wait(sc)) != 0) 6037 return error; 6038 6039 if ((error = iwn_nic_lock(sc)) != 0) 6040 return error; 6041 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6042 /* Enable DMA and BSM (Bootstrap State Machine). */ 6043 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6044 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6045 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6046 } else { 6047 /* Enable DMA. */ 6048 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6049 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6050 } 6051 DELAY(20); 6052 /* Disable L1-Active. */ 6053 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6054 iwn_nic_unlock(sc); 6055 6056 return 0; 6057 } 6058 6059 static void 6060 iwn_apm_stop_master(struct iwn_softc *sc) 6061 { 6062 int ntries; 6063 6064 /* Stop busmaster DMA activity. */ 6065 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6066 for (ntries = 0; ntries < 100; ntries++) { 6067 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6068 return; 6069 DELAY(10); 6070 } 6071 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 6072 } 6073 6074 static void 6075 iwn_apm_stop(struct iwn_softc *sc) 6076 { 6077 iwn_apm_stop_master(sc); 6078 6079 /* Reset the entire device. */ 6080 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6081 DELAY(10); 6082 /* Clear "initialization complete" bit. */ 6083 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6084 } 6085 6086 static int 6087 iwn4965_nic_config(struct iwn_softc *sc) 6088 { 6089 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6090 /* 6091 * I don't believe this to be correct but this is what the 6092 * vendor driver is doing. Probably the bits should not be 6093 * shifted in IWN_RFCFG_*. 6094 */ 6095 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6096 IWN_RFCFG_TYPE(sc->rfcfg) | 6097 IWN_RFCFG_STEP(sc->rfcfg) | 6098 IWN_RFCFG_DASH(sc->rfcfg)); 6099 } 6100 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6101 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6102 return 0; 6103 } 6104 6105 static int 6106 iwn5000_nic_config(struct iwn_softc *sc) 6107 { 6108 uint32_t tmp; 6109 int error; 6110 6111 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6112 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6113 IWN_RFCFG_TYPE(sc->rfcfg) | 6114 IWN_RFCFG_STEP(sc->rfcfg) | 6115 IWN_RFCFG_DASH(sc->rfcfg)); 6116 } 6117 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6118 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6119 6120 if ((error = iwn_nic_lock(sc)) != 0) 6121 return error; 6122 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6123 6124 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6125 /* 6126 * Select first Switching Voltage Regulator (1.32V) to 6127 * solve a stability issue related to noisy DC2DC line 6128 * in the silicon of 1000 Series. 6129 */ 6130 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6131 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6132 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6133 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6134 } 6135 iwn_nic_unlock(sc); 6136 6137 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6138 /* Use internal power amplifier only. */ 6139 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6140 } 6141 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6142 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6143 /* Indicate that ROM calibration version is >=6. */ 6144 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6145 } 6146 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6147 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6148 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6149 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6150 sc->hw_type == IWN_HW_REV_TYPE_135 || 6151 sc->hw_type == IWN_HW_REV_TYPE_105) 6152 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6153 return 0; 6154 } 6155 6156 /* 6157 * Take NIC ownership over Intel Active Management Technology (AMT). 6158 */ 6159 static int 6160 iwn_hw_prepare(struct iwn_softc *sc) 6161 { 6162 int ntries; 6163 6164 /* Check if hardware is ready. */ 6165 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6166 for (ntries = 0; ntries < 5; ntries++) { 6167 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6168 IWN_HW_IF_CONFIG_NIC_READY) 6169 return 0; 6170 DELAY(10); 6171 } 6172 6173 /* Hardware not ready, force into ready state. */ 6174 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6175 for (ntries = 0; ntries < 15000; ntries++) { 6176 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6177 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6178 break; 6179 DELAY(10); 6180 } 6181 if (ntries == 15000) 6182 return ETIMEDOUT; 6183 6184 /* Hardware should be ready now. */ 6185 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6186 for (ntries = 0; ntries < 5; ntries++) { 6187 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6188 IWN_HW_IF_CONFIG_NIC_READY) 6189 return 0; 6190 DELAY(10); 6191 } 6192 return ETIMEDOUT; 6193 } 6194 6195 static int 6196 iwn_hw_init(struct iwn_softc *sc) 6197 { 6198 struct iwn_ops *ops = &sc->ops; 6199 int error, chnl, qid; 6200 6201 /* Clear pending interrupts. */ 6202 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6203 6204 if ((error = iwn_apm_init(sc)) != 0) { 6205 aprint_error_dev(sc->sc_dev, 6206 "could not power ON adapter\n"); 6207 return error; 6208 } 6209 6210 /* Select VMAIN power source. */ 6211 if ((error = iwn_nic_lock(sc)) != 0) 6212 return error; 6213 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6214 iwn_nic_unlock(sc); 6215 6216 /* Perform adapter-specific initialization. */ 6217 if ((error = ops->nic_config(sc)) != 0) 6218 return error; 6219 6220 /* Initialize RX ring. */ 6221 if ((error = iwn_nic_lock(sc)) != 0) 6222 return error; 6223 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6224 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6225 /* Set physical address of RX ring (256-byte aligned). */ 6226 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6227 /* Set physical address of RX status (16-byte aligned). */ 6228 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6229 /* Enable RX. */ 6230 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6231 IWN_FH_RX_CONFIG_ENA | 6232 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6233 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6234 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6235 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6236 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6237 iwn_nic_unlock(sc); 6238 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6239 6240 if ((error = iwn_nic_lock(sc)) != 0) 6241 return error; 6242 6243 /* Initialize TX scheduler. */ 6244 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6245 6246 /* Set physical address of "keep warm" page (16-byte aligned). */ 6247 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6248 6249 /* Initialize TX rings. */ 6250 for (qid = 0; qid < sc->ntxqs; qid++) { 6251 struct iwn_tx_ring *txq = &sc->txq[qid]; 6252 6253 /* Set physical address of TX ring (256-byte aligned). */ 6254 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6255 txq->desc_dma.paddr >> 8); 6256 } 6257 iwn_nic_unlock(sc); 6258 6259 /* Enable DMA channels. */ 6260 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6261 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6262 IWN_FH_TX_CONFIG_DMA_ENA | 6263 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6264 } 6265 6266 /* Clear "radio off" and "commands blocked" bits. */ 6267 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6268 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6269 6270 /* Clear pending interrupts. */ 6271 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6272 /* Enable interrupt coalescing. */ 6273 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6274 /* Enable interrupts. */ 6275 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6276 6277 /* _Really_ make sure "radio off" bit is cleared! */ 6278 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6279 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6280 6281 /* Enable shadow registers. */ 6282 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6283 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6284 6285 if ((error = ops->load_firmware(sc)) != 0) { 6286 aprint_error_dev(sc->sc_dev, 6287 "could not load firmware\n"); 6288 return error; 6289 } 6290 /* Wait at most one second for firmware alive notification. */ 6291 if ((error = tsleep(sc, PCATCH, "iwninit", hz)) != 0) { 6292 aprint_error_dev(sc->sc_dev, 6293 "timeout waiting for adapter to initialize\n"); 6294 return error; 6295 } 6296 /* Do post-firmware initialization. */ 6297 return ops->post_alive(sc); 6298 } 6299 6300 static void 6301 iwn_hw_stop(struct iwn_softc *sc) 6302 { 6303 int chnl, qid, ntries; 6304 6305 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6306 6307 /* Disable interrupts. */ 6308 IWN_WRITE(sc, IWN_INT_MASK, 0); 6309 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6310 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6311 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6312 6313 /* Make sure we no longer hold the NIC lock. */ 6314 iwn_nic_unlock(sc); 6315 6316 /* Stop TX scheduler. */ 6317 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6318 6319 /* Stop all DMA channels. */ 6320 if (iwn_nic_lock(sc) == 0) { 6321 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6322 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6323 for (ntries = 0; ntries < 200; ntries++) { 6324 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6325 IWN_FH_TX_STATUS_IDLE(chnl)) 6326 break; 6327 DELAY(10); 6328 } 6329 } 6330 iwn_nic_unlock(sc); 6331 } 6332 6333 /* Stop RX ring. */ 6334 iwn_reset_rx_ring(sc, &sc->rxq); 6335 6336 /* Reset all TX rings. */ 6337 for (qid = 0; qid < sc->ntxqs; qid++) 6338 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6339 6340 if (iwn_nic_lock(sc) == 0) { 6341 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6342 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6343 iwn_nic_unlock(sc); 6344 } 6345 DELAY(5); 6346 /* Power OFF adapter. */ 6347 iwn_apm_stop(sc); 6348 } 6349 6350 static int 6351 iwn_init(struct ifnet *ifp) 6352 { 6353 struct iwn_softc *sc = ifp->if_softc; 6354 struct ieee80211com *ic = &sc->sc_ic; 6355 int error; 6356 6357 mutex_enter(&sc->sc_mtx); 6358 if (sc->sc_flags & IWN_FLAG_HW_INITED) 6359 goto out; 6360 if ((error = iwn_hw_prepare(sc)) != 0) { 6361 aprint_error_dev(sc->sc_dev, 6362 "hardware not ready\n"); 6363 goto fail; 6364 } 6365 6366 /* Check that the radio is not disabled by hardware switch. */ 6367 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6368 aprint_error_dev(sc->sc_dev, 6369 "radio is disabled by hardware switch\n"); 6370 error = EPERM; /* :-) */ 6371 goto fail; 6372 } 6373 6374 /* Read firmware images from the filesystem. */ 6375 if ((error = iwn_read_firmware(sc)) != 0) { 6376 aprint_error_dev(sc->sc_dev, 6377 "could not read firmware\n"); 6378 goto fail; 6379 } 6380 6381 /* Initialize interrupt mask to default value. */ 6382 sc->int_mask = IWN_INT_MASK_DEF; 6383 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6384 6385 /* Initialize hardware and upload firmware. */ 6386 KASSERT(sc->fw.data != NULL && sc->fw.size > 0); 6387 error = iwn_hw_init(sc); 6388 firmware_free(sc->fw.data, sc->fw.size); 6389 sc->fw.data = NULL; 6390 sc->fw.size = 0; 6391 if (error != 0) { 6392 aprint_error_dev(sc->sc_dev, 6393 "could not initialize hardware\n"); 6394 goto fail; 6395 } 6396 6397 /* Configure adapter now that it is ready. */ 6398 if ((error = iwn_config(sc)) != 0) { 6399 aprint_error_dev(sc->sc_dev, 6400 "could not configure device\n"); 6401 goto fail; 6402 } 6403 6404 sc->sc_beacon_wait = 0; 6405 6406 ifp->if_flags &= ~IFF_OACTIVE; 6407 ifp->if_flags |= IFF_RUNNING; 6408 6409 if (ic->ic_opmode != IEEE80211_M_MONITOR) 6410 ieee80211_begin_scan(ic, 0); 6411 else 6412 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 6413 6414 sc->sc_flags |= IWN_FLAG_HW_INITED; 6415 out: 6416 mutex_exit(&sc->sc_mtx); 6417 return 0; 6418 6419 fail: mutex_exit(&sc->sc_mtx); 6420 iwn_stop(ifp, 1); 6421 return error; 6422 } 6423 6424 static void 6425 iwn_stop(struct ifnet *ifp, int disable) 6426 { 6427 struct iwn_softc *sc = ifp->if_softc; 6428 struct ieee80211com *ic = &sc->sc_ic; 6429 6430 if (!disable) 6431 mutex_enter(&sc->sc_mtx); 6432 sc->sc_flags &= ~IWN_FLAG_HW_INITED; 6433 ifp->if_timer = sc->sc_tx_timer = 0; 6434 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 6435 6436 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 6437 6438 /* Power OFF hardware. */ 6439 iwn_hw_stop(sc); 6440 6441 if (!disable) 6442 mutex_exit(&sc->sc_mtx); 6443 } 6444 6445 /* 6446 * XXX MCLGETI alternative 6447 * 6448 * With IWN_USE_RBUF defined it uses the rbuf cache for receive buffers 6449 * as long as there are available free buffers then it uses MEXTMALLOC., 6450 * Without IWN_USE_RBUF defined it uses MEXTMALLOC exclusively. 6451 * The MCLGET4K code is used for testing an alternative mbuf cache. 6452 */ 6453 6454 static struct mbuf * 6455 MCLGETIalt(struct iwn_softc *sc, int how, 6456 struct ifnet *ifp __unused, u_int size) 6457 { 6458 struct mbuf *m; 6459 #ifdef IWN_USE_RBUF 6460 struct iwn_rbuf *rbuf; 6461 #endif 6462 6463 MGETHDR(m, how, MT_DATA); 6464 if (m == NULL) 6465 return NULL; 6466 6467 #ifdef IWN_USE_RBUF 6468 if (sc->rxq.nb_free_entries > 0 && 6469 (rbuf = iwn_alloc_rbuf(sc)) != NULL) { 6470 /* Attach buffer to mbuf header. */ 6471 MEXTADD(m, rbuf->vaddr, size, 0, iwn_free_rbuf, rbuf); 6472 m->m_flags |= M_EXT_RW; 6473 } 6474 else { 6475 MEXTMALLOC(m, size, how); 6476 if ((m->m_flags & M_EXT) == 0) { 6477 m_freem(m); 6478 return NULL; 6479 } 6480 } 6481 6482 #else 6483 #ifdef MCLGET4K 6484 if (size == 4096) 6485 MCLGET4K(m, how); 6486 else 6487 panic("size must be 4k"); 6488 #else 6489 MEXTMALLOC(m, size, how); 6490 #endif 6491 if ((m->m_flags & M_EXT) == 0) { 6492 m_freem(m); 6493 return NULL; 6494 } 6495 #endif 6496 6497 return m; 6498 } 6499 6500 #ifdef IWN_USE_RBUF 6501 static struct iwn_rbuf * 6502 iwn_alloc_rbuf(struct iwn_softc *sc) 6503 { 6504 struct iwn_rbuf *rbuf; 6505 mutex_enter(&sc->rxq.freelist_mtx); 6506 6507 rbuf = SLIST_FIRST(&sc->rxq.freelist); 6508 if (rbuf != NULL) { 6509 SLIST_REMOVE_HEAD(&sc->rxq.freelist, next); 6510 sc->rxq.nb_free_entries --; 6511 } 6512 mutex_exit(&sc->rxq.freelist_mtx); 6513 return rbuf; 6514 } 6515 6516 /* 6517 * This is called automatically by the network stack when the mbuf to which 6518 * our RX buffer is attached is freed. 6519 */ 6520 static void 6521 iwn_free_rbuf(struct mbuf* m, void *buf, size_t size, void *arg) 6522 { 6523 struct iwn_rbuf *rbuf = arg; 6524 struct iwn_softc *sc = rbuf->sc; 6525 6526 /* Put the RX buffer back in the free list. */ 6527 mutex_enter(&sc->rxq.freelist_mtx); 6528 SLIST_INSERT_HEAD(&sc->rxq.freelist, rbuf, next); 6529 mutex_exit(&sc->rxq.freelist_mtx); 6530 6531 sc->rxq.nb_free_entries ++; 6532 if (__predict_true(m != NULL)) 6533 pool_cache_put(mb_cache, m); 6534 } 6535 6536 static int 6537 iwn_alloc_rpool(struct iwn_softc *sc) 6538 { 6539 struct iwn_rx_ring *ring = &sc->rxq; 6540 struct iwn_rbuf *rbuf; 6541 int i, error; 6542 6543 mutex_init(&ring->freelist_mtx, MUTEX_DEFAULT, IPL_NET); 6544 6545 /* Allocate a big chunk of DMA'able memory... */ 6546 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->buf_dma, NULL, 6547 IWN_RBUF_COUNT * IWN_RBUF_SIZE, PAGE_SIZE); 6548 if (error != 0) { 6549 aprint_error_dev(sc->sc_dev, 6550 "could not allocate RX buffers DMA memory\n"); 6551 return error; 6552 } 6553 /* ...and split it into chunks of IWN_RBUF_SIZE bytes. */ 6554 SLIST_INIT(&ring->freelist); 6555 for (i = 0; i < IWN_RBUF_COUNT; i++) { 6556 rbuf = &ring->rbuf[i]; 6557 6558 rbuf->sc = sc; /* Backpointer for callbacks. */ 6559 rbuf->vaddr = (void *)((vaddr_t)ring->buf_dma.vaddr + i * IWN_RBUF_SIZE); 6560 rbuf->paddr = ring->buf_dma.paddr + i * IWN_RBUF_SIZE; 6561 6562 SLIST_INSERT_HEAD(&ring->freelist, rbuf, next); 6563 } 6564 ring->nb_free_entries = IWN_RBUF_COUNT; 6565 return 0; 6566 } 6567 6568 static void 6569 iwn_free_rpool(struct iwn_softc *sc) 6570 { 6571 iwn_dma_contig_free(&sc->rxq.buf_dma); 6572 } 6573 #endif 6574 6575 /* 6576 * XXX: Hack to set the current channel to the value advertised in beacons or 6577 * probe responses. Only used during AP detection. 6578 * XXX: Duplicated from if_iwi.c 6579 */ 6580 static void 6581 iwn_fix_channel(struct ieee80211com *ic, struct mbuf *m, 6582 struct iwn_rx_stat *stat) 6583 { 6584 struct iwn_softc *sc = ic->ic_ifp->if_softc; 6585 struct ieee80211_frame *wh; 6586 uint8_t subtype; 6587 uint8_t *frm, *efrm; 6588 6589 wh = mtod(m, struct ieee80211_frame *); 6590 6591 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 6592 return; 6593 6594 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 6595 6596 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 6597 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 6598 return; 6599 6600 if (sc->sc_flags & IWN_FLAG_SCANNING_5GHZ) { 6601 int chan = le16toh(stat->chan); 6602 if (chan < __arraycount(ic->ic_channels)) 6603 ic->ic_curchan = &ic->ic_channels[chan]; 6604 return; 6605 } 6606 6607 frm = (uint8_t *)(wh + 1); 6608 efrm = mtod(m, uint8_t *) + m->m_len; 6609 6610 frm += 12; /* skip tstamp, bintval and capinfo fields */ 6611 while (frm + 2 < efrm) { 6612 if (*frm == IEEE80211_ELEMID_DSPARMS) { 6613 #if IEEE80211_CHAN_MAX < 255 6614 if (frm[2] <= IEEE80211_CHAN_MAX) 6615 #endif 6616 ic->ic_curchan = &ic->ic_channels[frm[2]]; 6617 } 6618 6619 frm += frm[1] + 2; 6620 } 6621 } 6622 6623 #ifdef notyetMODULE 6624 6625 MODULE(MODULE_CLASS_DRIVER, if_iwn, "pci"); 6626 6627 #ifdef _MODULE 6628 #include "ioconf.c" 6629 #endif 6630 6631 static int 6632 if_iwn_modcmd(modcmd_t cmd, void *data) 6633 { 6634 int error = 0; 6635 6636 switch (cmd) { 6637 case MODULE_CMD_INIT: 6638 #ifdef _MODULE 6639 error = config_init_component(cfdriver_ioconf_if_iwn, 6640 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6641 #endif 6642 return error; 6643 case MODULE_CMD_FINI: 6644 #ifdef _MODULE 6645 error = config_fini_component(cfdriver_ioconf_if_iwn, 6646 cfattach_ioconf_if_iwn, cfdata_ioconf_if_iwn); 6647 #endif 6648 return error; 6649 case MODULE_CMD_AUTOUNLOAD: 6650 #ifdef _MODULE 6651 /* XXX This is not optional! */ 6652 #endif 6653 return error; 6654 default: 6655 return ENOTTY; 6656 } 6657 } 6658 #endif 6659
Indexes created Thu Oct 02 14:10:14 GMT 2025