if_iwnreg.h revision 1.6.2.1
1 /* $NetBSD: if_iwnreg.h,v 1.6.2.1 2010/04/30 14:43:35 uebayasi Exp $ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.38 2010/04/10 08:37:36 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini (at) free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* XXX Added for NetBSD */ 22 #define EDCA_NUM_AC 4 23 #define IEEE80211_TKIP_MICLEN 8 24 25 #define IWN_TX_RING_COUNT 256 26 #define IWN_TX_RING_LOMARK 192 27 #define IWN_TX_RING_HIMARK 224 28 #define IWN_RX_RING_COUNT_LOG 6 29 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 30 31 #define IWN4965_NTXQUEUES 16 32 #define IWN5000_NTXQUEUES 20 33 34 #define IWN4965_NDMACHNLS 7 35 #define IWN5000_NDMACHNLS 8 36 37 #define IWN_SRVC_DMACHNL 9 38 39 #define IWN_ICT_SIZE 4096 40 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 41 42 /* Maximum number of DMA segments for TX. */ 43 #define IWN_MAX_SCATTER 20 44 45 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 46 #define IWN_RBUF_SIZE (4 * 1024) 47 48 #if defined(__LP64__) 49 /* HW supports 36-bit DMA addresses. */ 50 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 51 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 52 #else 53 #define IWN_LOADDR(paddr) (paddr) 54 #define IWN_HIADDR(paddr) (0) 55 #endif 56 57 /* Base Address Register. */ 58 #define IWN_PCI_BAR0 PCI_MAPREG_START 59 60 /* 61 * Control and status registers. 62 */ 63 #define IWN_HW_IF_CONFIG 0x000 64 #define IWN_INT_COALESCING 0x004 65 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 66 #define IWN_INT 0x008 67 #define IWN_INT_MASK 0x00c 68 #define IWN_FH_INT 0x010 69 #define IWN_RESET 0x020 70 #define IWN_GP_CNTRL 0x024 71 #define IWN_HW_REV 0x028 72 #define IWN_EEPROM 0x02c 73 #define IWN_EEPROM_GP 0x030 74 #define IWN_OTP_GP 0x034 75 #define IWN_GIO 0x03c 76 #define IWN_GP_DRIVER 0x050 77 #define IWN_UCODE_GP1_CLR 0x05c 78 #define IWN_LED 0x094 79 #define IWN_DRAM_INT_TBL 0x0a0 80 #define IWN_GIO_CHICKEN 0x100 81 #define IWN_ANA_PLL 0x20c 82 #define IWN_HW_REV_WA 0x22c 83 #define IWN_DBG_HPET_MEM 0x240 84 #define IWN_DBG_LINK_PWR_MGMT 0x250 85 #define IWN_MEM_RADDR 0x40c 86 #define IWN_MEM_WADDR 0x410 87 #define IWN_MEM_WDATA 0x418 88 #define IWN_MEM_RDATA 0x41c 89 #define IWN_PRPH_WADDR 0x444 90 #define IWN_PRPH_RADDR 0x448 91 #define IWN_PRPH_WDATA 0x44c 92 #define IWN_PRPH_RDATA 0x450 93 #define IWN_HBUS_TARG_WRPTR 0x460 94 95 /* 96 * Flow-Handler registers. 97 */ 98 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 99 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 100 #define IWN_FH_KW_ADDR 0x197c 101 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 102 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 103 #define IWN_FH_STATUS_WPTR 0x1bc0 104 #define IWN_FH_RX_BASE 0x1bc4 105 #define IWN_FH_RX_WPTR 0x1bc8 106 #define IWN_FH_RX_CONFIG 0x1c00 107 #define IWN_FH_RX_STATUS 0x1c44 108 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 109 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 110 #define IWN_FH_TX_CHICKEN 0x1e98 111 #define IWN_FH_TX_STATUS 0x1eb0 112 113 /* 114 * TX scheduler registers. 115 */ 116 #define IWN_SCHED_BASE 0xa02c00 117 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 118 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 119 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 120 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 121 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 122 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 123 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 124 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 125 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 126 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 127 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 128 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 129 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 130 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 131 132 /* 133 * Offsets in TX scheduler's SRAM. 134 */ 135 #define IWN4965_SCHED_CTX_OFF 0x380 136 #define IWN4965_SCHED_CTX_LEN 416 137 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 138 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 139 #define IWN5000_SCHED_CTX_OFF 0x600 140 #define IWN5000_SCHED_CTX_LEN 520 141 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 142 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 143 144 /* 145 * NIC internal memory offsets. 146 */ 147 #define IWN_APMG_CLK_CTRL 0x3000 148 #define IWN_APMG_CLK_EN 0x3004 149 #define IWN_APMG_CLK_DIS 0x3008 150 #define IWN_APMG_PS 0x300c 151 #define IWN_APMG_DIGITAL_SVR 0x3058 152 #define IWN_APMG_ANALOG_SVR 0x306c 153 #define IWN_APMG_PCI_STT 0x3010 154 #define IWN_BSM_WR_CTRL 0x3400 155 #define IWN_BSM_WR_MEM_SRC 0x3404 156 #define IWN_BSM_WR_MEM_DST 0x3408 157 #define IWN_BSM_WR_DWCOUNT 0x340c 158 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 159 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 160 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 161 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 162 #define IWN_BSM_SRAM_BASE 0x3800 163 164 /* Possible flags for register IWN_HW_IF_CONFIG. */ 165 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 166 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 167 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 168 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 169 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 170 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 171 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 172 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 173 174 /* Possible values for register IWN_INT_PERIODIC. */ 175 #define IWN_INT_PERIODIC_DIS 0x00 176 #define IWN_INT_PERIODIC_ENA 0xff 177 178 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 179 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 180 181 /* Possible values for IWN_BSM_WR_MEM_DST. */ 182 #define IWN_FW_TEXT_BASE 0x00000000 183 #define IWN_FW_DATA_BASE 0x00800000 184 185 /* Possible flags for register IWN_RESET. */ 186 #define IWN_RESET_NEVO (1 << 0) 187 #define IWN_RESET_SW (1 << 7) 188 #define IWN_RESET_MASTER_DISABLED (1 << 8) 189 #define IWN_RESET_STOP_MASTER (1 << 9) 190 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 191 192 /* Possible flags for register IWN_GP_CNTRL. */ 193 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 194 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 195 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 196 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 197 #define IWN_GP_CNTRL_SLEEP (1 << 4) 198 #define IWN_GP_CNTRL_RFKILL (1 << 27) 199 200 /* Possible flags for register IWN_HW_REV. */ 201 #define IWN_HW_REV_TYPE_SHIFT 4 202 #define IWN_HW_REV_TYPE_MASK 0x000000f0 203 #define IWN_HW_REV_TYPE_4965 0 204 #define IWN_HW_REV_TYPE_5300 2 205 #define IWN_HW_REV_TYPE_5350 3 206 #define IWN_HW_REV_TYPE_5150 4 207 #define IWN_HW_REV_TYPE_5100 5 208 #define IWN_HW_REV_TYPE_1000 6 209 #define IWN_HW_REV_TYPE_6000 7 210 #define IWN_HW_REV_TYPE_6050 8 211 #define IWN_HW_REV_TYPE_6005 11 212 213 /* Possible flags for register IWN_GIO_CHICKEN. */ 214 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216 217 /* Possible flags for register IWN_GIO. */ 218 #define IWN_GIO_L0S_ENA (1 << 1) 219 220 /* Possible flags for register IWN_GP_DRIVER. */ 221 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225 226 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 227 #define IWN_UCODE_GP1_RFKILL (1 << 1) 228 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 229 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 230 231 /* Possible flags/values for register IWN_LED. */ 232 #define IWN_LED_BSM_CTRL (1 << 5) 233 #define IWN_LED_OFF 0x00000038 234 #define IWN_LED_ON 0x00000078 235 236 /* Possible flags for register IWN_DRAM_INT_TBL. */ 237 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 238 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 239 240 /* Possible values for register IWN_ANA_PLL. */ 241 #define IWN_ANA_PLL_INIT 0x00880300 242 243 /* Possible flags for register IWN_FH_RX_STATUS. */ 244 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 245 246 /* Possible flags for register IWN_BSM_WR_CTRL. */ 247 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 248 #define IWN_BSM_WR_CTRL_START (1 << 31) 249 250 /* Possible flags for register IWN_INT. */ 251 #define IWN_INT_ALIVE (1 << 0) 252 #define IWN_INT_WAKEUP (1 << 1) 253 #define IWN_INT_SW_RX (1 << 3) 254 #define IWN_INT_CT_REACHED (1 << 6) 255 #define IWN_INT_RF_TOGGLED (1 << 7) 256 #define IWN_INT_SW_ERR (1 << 25) 257 #define IWN_INT_SCHED (1 << 26) 258 #define IWN_INT_FH_TX (1 << 27) 259 #define IWN_INT_RX_PERIODIC (1 << 28) 260 #define IWN_INT_HW_ERR (1 << 29) 261 #define IWN_INT_FH_RX (1 << 31) 262 263 /* Shortcut. */ 264 #define IWN_INT_MASK_DEF \ 265 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 266 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 267 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 268 269 /* Possible flags for register IWN_FH_INT. */ 270 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 271 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 272 #define IWN_FH_INT_HI_PRIOR (1 << 30) 273 /* Shortcuts for the above. */ 274 #define IWN_FH_INT_TX \ 275 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 276 #define IWN_FH_INT_RX \ 277 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 278 279 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 280 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 281 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 282 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 283 284 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 285 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 286 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 287 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 288 289 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 290 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 291 292 /* Possible flags for register IWN_FH_TX_STATUS. */ 293 #define IWN_FH_TX_STATUS_IDLE(chnl) \ 294 (1 << ((chnl) + 24) | 1 << ((chnl) + 16)) 295 296 /* Possible flags for register IWN_FH_RX_CONFIG. */ 297 #define IWN_FH_RX_CONFIG_ENA (1 << 31) 298 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 299 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 300 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 301 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 302 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 303 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 304 305 /* Possible flags for register IWN_FH_TX_CONFIG. */ 306 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 307 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 308 309 /* Possible flags for register IWN_EEPROM. */ 310 #define IWN_EEPROM_READ_VALID (1 << 0) 311 #define IWN_EEPROM_CMD (1 << 1) 312 313 /* Possible flags for register IWN_EEPROM_GP. */ 314 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 315 316 /* Possible flags for register IWN_OTP_GP. */ 317 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 318 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 319 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 320 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 321 322 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 323 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 324 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 325 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 326 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 327 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 328 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 329 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 330 331 /* Possible flags for registers IWN_APMG_CLK_*. */ 332 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 333 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 334 335 /* Possible flags for register IWN_APMG_PS. */ 336 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 337 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 338 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 339 #define IWN_APMG_PS_PWR_SRC_VAUX 2 340 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 341 #define IWN_APMG_PS_RESET_REQ (1 << 26) 342 343 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 344 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 345 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 346 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 347 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 348 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 349 350 /* Possible flags for IWN_APMG_PCI_STT. */ 351 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 352 353 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 354 #define IWN_FW_UPDATED (1 << 31) 355 356 #define IWN_SCHED_WINSZ 64 357 #define IWN_SCHED_LIMIT 64 358 #define IWN4965_SCHED_COUNT 512 359 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 360 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 361 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 362 363 struct iwn_tx_desc { 364 uint8_t reserved1[3]; 365 uint8_t nsegs; 366 struct { 367 uint32_t addr; 368 uint16_t len; 369 } __packed segs[IWN_MAX_SCATTER]; 370 /* Pad to 128 bytes. */ 371 uint32_t reserved2; 372 } __packed; 373 374 struct iwn_rx_status { 375 uint16_t closed_count; 376 uint16_t closed_rx_count; 377 uint16_t finished_count; 378 uint16_t finished_rx_count; 379 uint32_t reserved[2]; 380 } __packed; 381 382 struct iwn_rx_desc { 383 uint32_t len; 384 uint8_t type; 385 #define IWN_UC_READY 1 386 #define IWN_ADD_NODE_DONE 24 387 #define IWN_TX_DONE 28 388 #define IWN5000_CALIBRATION_RESULT 102 389 #define IWN5000_CALIBRATION_DONE 103 390 #define IWN_START_SCAN 130 391 #define IWN_STOP_SCAN 132 392 #define IWN_RX_STATISTICS 156 393 #define IWN_BEACON_STATISTICS 157 394 #define IWN_STATE_CHANGED 161 395 #define IWN_BEACON_MISSED 162 396 #define IWN_RX_PHY 192 397 #define IWN_MPDU_RX_DONE 193 398 #define IWN_RX_DONE 195 399 #define IWN_RX_COMPRESSED_BA 197 400 401 uint8_t flags; 402 uint8_t idx; 403 uint8_t qid; 404 } __packed; 405 406 /* Possible RX status flags. */ 407 #define IWN_RX_NO_CRC_ERR (1 << 0) 408 #define IWN_RX_NO_OVFL_ERR (1 << 1) 409 /* Shortcut for the above. */ 410 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 411 #define IWN_RX_MPDU_MIC_OK (1 << 6) 412 #define IWN_RX_CIPHER_MASK (7 << 8) 413 #define IWN_RX_CIPHER_CCMP (2 << 8) 414 #define IWN_RX_MPDU_DEC (1 << 11) 415 #define IWN_RX_DECRYPT_MASK (3 << 11) 416 #define IWN_RX_DECRYPT_OK (3 << 11) 417 418 struct iwn_tx_cmd { 419 uint8_t code; 420 #define IWN_CMD_RXON 16 421 #define IWN_CMD_RXON_ASSOC 17 422 #define IWN_CMD_EDCA_PARAMS 19 423 #define IWN_CMD_TIMING 20 424 #define IWN_CMD_ADD_NODE 24 425 #define IWN_CMD_TX_DATA 28 426 #define IWN_CMD_LINK_QUALITY 78 427 #define IWN_CMD_SET_LED 72 428 #define IWN5000_CMD_WIMAX_COEX 90 429 #define IWN5000_CMD_CALIB_CONFIG 101 430 #define IWN_CMD_SET_POWER_MODE 119 431 #define IWN_CMD_SCAN 128 432 #define IWN_CMD_TXPOWER_DBM 149 433 #define IWN_CMD_TXPOWER 151 434 #define IWN5000_CMD_TX_ANT_CONFIG 152 435 #define IWN_CMD_BT_COEX 155 436 #define IWN_CMD_GET_STATISTICS 156 437 #define IWN_CMD_SET_CRITICAL_TEMP 164 438 #define IWN_CMD_SET_SENSITIVITY 168 439 #define IWN_CMD_PHY_CALIB 176 440 441 uint8_t flags; 442 uint8_t idx; 443 uint8_t qid; 444 uint8_t data[136]; 445 } __packed; 446 447 /* Antenna flags, used in various commands. */ 448 #define IWN_ANT_A (1 << 0) 449 #define IWN_ANT_B (1 << 1) 450 #define IWN_ANT_C (1 << 2) 451 /* Shortcuts. */ 452 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 453 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 454 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 455 456 /* Structure for command IWN_CMD_RXON. */ 457 struct iwn_rxon { 458 uint8_t myaddr[IEEE80211_ADDR_LEN]; 459 uint16_t reserved1; 460 uint8_t bssid[IEEE80211_ADDR_LEN]; 461 uint16_t reserved2; 462 uint8_t wlap[IEEE80211_ADDR_LEN]; 463 uint16_t reserved3; 464 uint8_t mode; 465 #define IWN_MODE_HOSTAP 1 466 #define IWN_MODE_STA 3 467 #define IWN_MODE_IBSS 4 468 #define IWN_MODE_MONITOR 6 469 470 uint8_t air; 471 uint16_t rxchain; 472 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 473 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 474 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 475 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 476 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 477 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 478 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 479 480 uint8_t ofdm_mask; 481 uint8_t cck_mask; 482 uint16_t associd; 483 uint32_t flags; 484 #define IWN_RXON_24GHZ (1 << 0) 485 #define IWN_RXON_CCK (1 << 1) 486 #define IWN_RXON_AUTO (1 << 2) 487 #define IWN_RXON_SHSLOT (1 << 4) 488 #define IWN_RXON_SHPREAMBLE (1 << 5) 489 #define IWN_RXON_NODIVERSITY (1 << 7) 490 #define IWN_RXON_ANTENNA_A (1 << 8) 491 #define IWN_RXON_ANTENNA_B (1 << 9) 492 #define IWN_RXON_TSF (1 << 15) 493 #define IWN_RXON_CTS_TO_SELF (1 << 30) 494 495 uint32_t filter; 496 #define IWN_FILTER_PROMISC (1 << 0) 497 #define IWN_FILTER_CTL (1 << 1) 498 #define IWN_FILTER_MULTICAST (1 << 2) 499 #define IWN_FILTER_NODECRYPT (1 << 3) 500 #define IWN_FILTER_BSS (1 << 5) 501 #define IWN_FILTER_BEACON (1 << 6) 502 503 uint8_t chan; 504 uint8_t reserved4; 505 uint8_t ht_single_mask; 506 uint8_t ht_dual_mask; 507 /* The following fields are for >=5000 Series only. */ 508 uint8_t ht_triple_mask; 509 uint8_t reserved5; 510 uint16_t acquisition; 511 uint16_t reserved6; 512 } __packed; 513 514 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 515 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 516 517 /* Structure for command IWN_CMD_ASSOCIATE. */ 518 struct iwn_assoc { 519 uint32_t flags; 520 uint32_t filter; 521 uint8_t ofdm_mask; 522 uint8_t cck_mask; 523 uint16_t reserved; 524 } __packed; 525 526 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 527 struct iwn_edca_params { 528 uint32_t flags; 529 #define IWN_EDCA_UPDATE (1 << 0) 530 #define IWN_EDCA_TXOP (1 << 4) 531 532 struct { 533 uint16_t cwmin; 534 uint16_t cwmax; 535 uint8_t aifsn; 536 uint8_t reserved; 537 uint16_t txoplimit; 538 } __packed ac[EDCA_NUM_AC]; 539 } __packed; 540 541 /* Structure for command IWN_CMD_TIMING. */ 542 struct iwn_cmd_timing { 543 uint64_t tstamp; 544 uint16_t bintval; 545 uint16_t atim; 546 uint32_t binitval; 547 uint16_t lintval; 548 uint16_t reserved; 549 } __packed; 550 551 /* Structure for command IWN_CMD_ADD_NODE. */ 552 struct iwn_node_info { 553 uint8_t control; 554 #define IWN_NODE_UPDATE (1 << 0) 555 556 uint8_t reserved1[3]; 557 558 uint8_t macaddr[IEEE80211_ADDR_LEN]; 559 uint16_t reserved2; 560 uint8_t id; 561 #define IWN_ID_BSS 0 562 #define IWN5000_ID_BROADCAST 15 563 #define IWN4965_ID_BROADCAST 31 564 565 uint8_t flags; 566 #define IWN_FLAG_SET_KEY (1 << 0) 567 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 568 #define IWN_FLAG_SET_TXRATE (1 << 2) 569 #define IWN_FLAG_SET_ADDBA (1 << 3) 570 #define IWN_FLAG_SET_DELBA (1 << 4) 571 572 uint16_t reserved3; 573 uint16_t kflags; 574 #define IWN_KFLAG_CCMP (1 << 1) 575 #define IWN_KFLAG_MAP (1 << 3) 576 #define IWN_KFLAG_KID(kid) ((kid) << 8) 577 #define IWN_KFLAG_INVALID (1 << 11) 578 #define IWN_KFLAG_GROUP (1 << 14) 579 580 uint8_t tsc2; /* TKIP TSC2 */ 581 uint8_t reserved4; 582 uint16_t ttak[5]; 583 uint8_t kid; 584 uint8_t reserved5; 585 uint8_t key[16]; 586 /* The following 3 fields are for 5000 Series only. */ 587 uint64_t tsc; 588 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 589 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 590 591 uint32_t htflags; 592 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 593 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 594 595 uint32_t mask; 596 uint16_t disable_tid; 597 uint16_t reserved6; 598 uint8_t addba_tid; 599 uint8_t delba_tid; 600 uint16_t addba_ssn; 601 uint32_t reserved7; 602 } __packed; 603 604 struct iwn4965_node_info { 605 uint8_t control; 606 uint8_t reserved1[3]; 607 uint8_t macaddr[IEEE80211_ADDR_LEN]; 608 uint16_t reserved2; 609 uint8_t id; 610 uint8_t flags; 611 uint16_t reserved3; 612 uint16_t kflags; 613 uint8_t tsc2; /* TKIP TSC2 */ 614 uint8_t reserved4; 615 uint16_t ttak[5]; 616 uint8_t kid; 617 uint8_t reserved5; 618 uint8_t key[16]; 619 uint32_t htflags; 620 uint32_t mask; 621 uint16_t disable_tid; 622 uint16_t reserved6; 623 uint8_t addba_tid; 624 uint8_t delba_tid; 625 uint16_t addba_ssn; 626 uint32_t reserved7; 627 } __packed; 628 629 #define IWN_RFLAG_CCK (1 << 1) 630 #define IWN_RFLAG_ANT(x) ((x) << 6) 631 632 /* Structure for command IWN_CMD_TX_DATA. */ 633 struct iwn_cmd_data { 634 uint16_t len; 635 uint16_t lnext; 636 uint32_t flags; 637 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 638 #define IWN_TX_NEED_RTS (1 << 1) 639 #define IWN_TX_NEED_CTS (1 << 2) 640 #define IWN_TX_NEED_ACK (1 << 3) 641 #define IWN_TX_LINKQ (1 << 4) 642 #define IWN_TX_IMM_BA (1 << 6) 643 #define IWN_TX_FULL_TXOP (1 << 7) 644 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 645 #define IWN_TX_AUTO_SEQ (1 << 13) 646 #define IWN_TX_MORE_FRAG (1 << 14) 647 #define IWN_TX_INSERT_TSTAMP (1 << 16) 648 #define IWN_TX_NEED_PADDING (1 << 20) 649 650 uint32_t scratch; 651 uint8_t plcp; 652 uint8_t rflags; 653 uint16_t xrflags; 654 655 uint8_t id; 656 uint8_t security; 657 #define IWN_CIPHER_WEP40 1 658 #define IWN_CIPHER_CCMP 2 659 #define IWN_CIPHER_TKIP 3 660 #define IWN_CIPHER_WEP104 9 661 662 uint8_t linkq; 663 uint8_t reserved2; 664 uint8_t key[16]; 665 uint16_t fnext; 666 uint16_t reserved3; 667 uint32_t lifetime; 668 #define IWN_LIFETIME_INFINITE 0xffffffff 669 670 uint32_t loaddr; 671 uint8_t hiaddr; 672 uint8_t rts_ntries; 673 uint8_t data_ntries; 674 uint8_t tid; 675 uint16_t timeout; 676 uint16_t txop; 677 } __packed; 678 679 /* Structure for command IWN_CMD_LINK_QUALITY. */ 680 #define IWN_MAX_TX_RETRIES 16 681 struct iwn_cmd_link_quality { 682 uint8_t id; 683 uint8_t reserved1; 684 uint16_t ctl; 685 uint8_t flags; 686 uint8_t mimo; 687 uint8_t antmsk_1stream; 688 uint8_t antmsk_2stream; 689 uint8_t ridx[EDCA_NUM_AC]; 690 uint16_t ampdu_limit; 691 uint8_t ampdu_threshold; 692 uint8_t ampdu_max; 693 uint32_t reserved2; 694 struct { 695 uint8_t plcp; 696 uint8_t rflags; 697 uint16_t xrflags; 698 } __packed retry[IWN_MAX_TX_RETRIES]; 699 uint32_t reserved3; 700 } __packed; 701 702 /* Structure for command IWN_CMD_SET_LED. */ 703 struct iwn_cmd_led { 704 uint32_t unit; /* multiplier (in usecs) */ 705 uint8_t which; 706 #define IWN_LED_ACTIVITY 1 707 #define IWN_LED_LINK 2 708 709 uint8_t off; 710 uint8_t on; 711 uint8_t reserved; 712 } __packed; 713 714 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 715 struct iwn5000_wimax_coex { 716 uint32_t flags; 717 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 718 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 719 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 720 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 721 722 struct iwn5000_wimax_event { 723 uint8_t request; 724 uint8_t window; 725 uint8_t reserved; 726 uint8_t flags; 727 } __packed events[16]; 728 } __packed; 729 730 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 731 struct iwn5000_calib_elem { 732 uint32_t enable; 733 uint32_t start; 734 uint32_t send; 735 uint32_t apply; 736 uint32_t reserved; 737 } __packed; 738 739 struct iwn5000_calib_status { 740 struct iwn5000_calib_elem once; 741 struct iwn5000_calib_elem perd; 742 uint32_t flags; 743 } __packed; 744 745 struct iwn5000_calib_config { 746 struct iwn5000_calib_status ucode; 747 struct iwn5000_calib_status driver; 748 uint32_t reserved; 749 } __packed; 750 751 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 752 struct iwn_pmgt_cmd { 753 uint16_t flags; 754 #define IWN_PS_ALLOW_SLEEP (1 << 0) 755 #define IWN_PS_NOTIFY (1 << 1) 756 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 757 #define IWN_PS_PCI_PMGT (1 << 3) 758 #define IWN_PS_FAST_PD (1 << 4) 759 760 uint8_t keepalive; 761 uint8_t debug; 762 uint32_t rxtimeout; 763 uint32_t txtimeout; 764 uint32_t intval[5]; 765 uint32_t beacons; 766 } __packed; 767 768 /* Structures for command IWN_CMD_SCAN. */ 769 struct iwn_scan_essid { 770 uint8_t id; 771 uint8_t len; 772 uint8_t data[IEEE80211_NWID_LEN]; 773 } __packed; 774 775 struct iwn_scan_hdr { 776 uint16_t len; 777 uint8_t reserved1; 778 uint8_t nchan; 779 uint16_t quiet_time; 780 uint16_t quiet_threshold; 781 uint16_t crc_threshold; 782 uint16_t rxchain; 783 uint32_t max_svc; /* background scans */ 784 uint32_t pause_svc; /* background scans */ 785 uint32_t flags; 786 uint32_t filter; 787 788 /* Followed by a struct iwn_cmd_data. */ 789 /* Followed by an array of 20 structs iwn_scan_essid. */ 790 /* Followed by probe request body. */ 791 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 792 } __packed; 793 794 struct iwn_scan_chan { 795 uint32_t flags; 796 #define IWN_CHAN_ACTIVE (1 << 0) 797 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 798 799 uint16_t chan; 800 uint8_t rf_gain; 801 uint8_t dsp_gain; 802 uint16_t active; /* msecs */ 803 uint16_t passive; /* msecs */ 804 } __packed; 805 806 /* Maximum size of a scan command. */ 807 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 808 809 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 810 #define IWN_RIDX_MAX 32 811 struct iwn4965_cmd_txpower { 812 uint8_t band; 813 uint8_t reserved1; 814 uint8_t chan; 815 uint8_t reserved2; 816 struct { 817 uint8_t rf_gain[2]; 818 uint8_t dsp_gain[2]; 819 } __packed power[IWN_RIDX_MAX + 1]; 820 } __packed; 821 822 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 823 struct iwn5000_cmd_txpower { 824 int8_t global_limit; /* in half-dBm */ 825 #define IWN5000_TXPOWER_AUTO 0x7f 826 #define IWN5000_TXPOWER_MAX_DBM 16 827 828 uint8_t flags; 829 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 830 831 int8_t srv_limit; /* in half-dBm */ 832 uint8_t reserved; 833 } __packed; 834 835 /* Structure for command IWN_CMD_BLUETOOTH. */ 836 struct iwn_bluetooth { 837 uint8_t flags; 838 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 839 #define IWN_BT_COEX_BT_PRIO (1 << 1) 840 #define IWN_BT_COEX_2_WIRE (1 << 2) 841 842 uint8_t lead_time; 843 #define IWN_BT_LEAD_TIME_DEF 30 844 845 uint8_t max_kill; 846 #define IWN_BT_MAX_KILL_DEF 5 847 848 uint8_t reserved; 849 uint32_t kill_ack; 850 uint32_t kill_cts; 851 } __packed; 852 853 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 854 struct iwn_critical_temp { 855 uint32_t reserved; 856 uint32_t tempM; 857 uint32_t tempR; 858 /* degK <-> degC conversion macros. */ 859 #define IWN_CTOK(c) ((c) + 273) 860 #define IWN_KTOC(k) ((k) - 273) 861 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 862 } __packed; 863 864 /* Structure for command IWN_CMD_SET_SENSITIVITY. */ 865 struct iwn_sensitivity_cmd { 866 uint16_t which; 867 #define IWN_SENSITIVITY_DEFAULTTBL 0 868 #define IWN_SENSITIVITY_WORKTBL 1 869 870 uint16_t energy_cck; 871 uint16_t energy_ofdm; 872 uint16_t corr_ofdm_x1; 873 uint16_t corr_ofdm_mrc_x1; 874 uint16_t corr_cck_mrc_x4; 875 uint16_t corr_ofdm_x4; 876 uint16_t corr_ofdm_mrc_x4; 877 uint16_t corr_barker; 878 uint16_t corr_barker_mrc; 879 uint16_t corr_cck_x4; 880 uint16_t energy_ofdm_th; 881 } __packed; 882 883 /* Structures for command IWN_CMD_PHY_CALIB. */ 884 struct iwn_phy_calib { 885 uint8_t code; 886 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 887 #define IWN5000_PHY_CALIB_DC 8 888 #define IWN5000_PHY_CALIB_LO 9 889 #define IWN5000_PHY_CALIB_TX_IQ 11 890 #define IWN5000_PHY_CALIB_CRYSTAL 15 891 #define IWN5000_PHY_CALIB_BASE_BAND 16 892 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 893 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 894 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 895 896 uint8_t group; 897 uint8_t ngroups; 898 uint8_t isvalid; 899 } __packed; 900 901 struct iwn5000_phy_calib_crystal { 902 uint8_t code; 903 uint8_t group; 904 uint8_t ngroups; 905 uint8_t isvalid; 906 907 uint8_t cap_pin[2]; 908 uint8_t reserved[2]; 909 } __packed; 910 911 struct iwn_phy_calib_gain { 912 uint8_t code; 913 uint8_t group; 914 uint8_t ngroups; 915 uint8_t isvalid; 916 917 int8_t gain[3]; 918 uint8_t reserved; 919 } __packed; 920 921 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 922 struct iwn_spectrum_cmd { 923 uint16_t len; 924 uint8_t token; 925 uint8_t id; 926 uint8_t origin; 927 uint8_t periodic; 928 uint16_t timeout; 929 uint32_t start; 930 uint32_t reserved1; 931 uint32_t flags; 932 uint32_t filter; 933 uint16_t nchan; 934 uint16_t reserved2; 935 struct { 936 uint32_t duration; 937 uint8_t chan; 938 uint8_t type; 939 #define IWN_MEASUREMENT_BASIC (1 << 0) 940 #define IWN_MEASUREMENT_CCA (1 << 1) 941 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 942 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 943 #define IWN_MEASUREMENT_FRAME (1 << 4) 944 #define IWN_MEASUREMENT_IDLE (1 << 7) 945 946 uint16_t reserved; 947 } __packed chan[10]; 948 } __packed; 949 950 /* Structure for IWN_UC_READY notification. */ 951 #define IWN_NATTEN_GROUPS 5 952 struct iwn_ucode_info { 953 uint8_t minor; 954 uint8_t major; 955 uint16_t reserved1; 956 uint8_t revision[8]; 957 uint8_t type; 958 uint8_t subtype; 959 #define IWN_UCODE_RUNTIME 0 960 #define IWN_UCODE_INIT 9 961 962 uint16_t reserved2; 963 uint32_t logptr; 964 uint32_t errptr; 965 uint32_t tstamp; 966 uint32_t valid; 967 968 /* The following fields are for UCODE_INIT only. */ 969 int32_t volt; 970 struct { 971 int32_t chan20MHz; 972 int32_t chan40MHz; 973 } __packed temp[4]; 974 int32_t atten[IWN_NATTEN_GROUPS][2]; 975 } __packed; 976 977 /* Structures for IWN_TX_DONE notification. */ 978 struct iwn4965_tx_stat { 979 uint8_t nframes; 980 uint8_t btkillcnt; 981 uint8_t rtsfailcnt; 982 uint8_t ackfailcnt; 983 uint8_t rate; 984 uint8_t rflags; 985 uint16_t xrflags; 986 uint16_t duration; 987 uint16_t reserved; 988 uint32_t power[2]; 989 uint32_t status; 990 } __packed; 991 992 struct iwn5000_tx_stat { 993 uint8_t nframes; 994 uint8_t btkillcnt; 995 uint8_t rtsfailcnt; 996 uint8_t ackfailcnt; 997 uint8_t rate; 998 uint8_t rflags; 999 uint16_t xrflags; 1000 uint16_t duration; 1001 uint16_t reserved; 1002 uint32_t power[2]; 1003 uint32_t info; 1004 uint16_t seq; 1005 uint16_t len; 1006 uint8_t tlc; 1007 uint8_t ratid; 1008 uint8_t fc[2]; 1009 uint16_t status; 1010 uint16_t sequence; 1011 } __packed; 1012 1013 /* Structure for IWN_BEACON_MISSED notification. */ 1014 struct iwn_beacon_missed { 1015 uint32_t consecutive; 1016 uint32_t total; 1017 uint32_t expected; 1018 uint32_t received; 1019 } __packed; 1020 1021 /* Structure for IWN_MPDU_RX_DONE notification. */ 1022 struct iwn_rx_mpdu { 1023 uint16_t len; 1024 uint16_t reserved; 1025 } __packed; 1026 1027 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1028 struct iwn4965_rx_phystat { 1029 uint16_t antenna; 1030 uint16_t agc; 1031 uint8_t rssi[6]; 1032 } __packed; 1033 1034 struct iwn5000_rx_phystat { 1035 uint32_t reserved1; 1036 uint32_t agc; 1037 uint16_t rssi[3]; 1038 } __packed; 1039 1040 struct iwn_rx_stat { 1041 uint8_t phy_len; 1042 uint8_t cfg_phy_len; 1043 #define IWN_STAT_MAXLEN 20 1044 1045 uint8_t id; 1046 uint8_t reserved1; 1047 uint64_t tstamp; 1048 uint32_t beacon; 1049 uint16_t flags; 1050 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1051 1052 uint16_t chan; 1053 uint8_t phybuf[32]; 1054 uint8_t rate; 1055 uint8_t rflags; 1056 uint16_t xrflags; 1057 uint16_t len; 1058 uint16_t reserve3; 1059 } __packed; 1060 1061 #define IWN_RSSI_TO_DBM 44 1062 1063 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1064 struct iwn_compressed_ba { 1065 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1066 uint16_t reserved; 1067 uint8_t id; 1068 uint8_t tid; 1069 uint16_t seq; 1070 uint64_t bitmap; 1071 uint16_t qid; 1072 uint16_t ssn; 1073 } __packed; 1074 1075 /* Structure for IWN_START_SCAN notification. */ 1076 struct iwn_start_scan { 1077 uint64_t tstamp; 1078 uint32_t tbeacon; 1079 uint8_t chan; 1080 uint8_t band; 1081 uint16_t reserved; 1082 uint32_t status; 1083 } __packed; 1084 1085 /* Structure for IWN_STOP_SCAN notification. */ 1086 struct iwn_stop_scan { 1087 uint8_t nchan; 1088 uint8_t status; 1089 uint8_t reserved; 1090 uint8_t chan; 1091 uint64_t tsf; 1092 } __packed; 1093 1094 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1095 struct iwn_spectrum_notif { 1096 uint8_t id; 1097 uint8_t token; 1098 uint8_t idx; 1099 uint8_t state; 1100 #define IWN_MEASUREMENT_START 0 1101 #define IWN_MEASUREMENT_STOP 1 1102 1103 uint32_t start; 1104 uint8_t band; 1105 uint8_t chan; 1106 uint8_t type; 1107 uint8_t reserved1; 1108 uint32_t cca_ofdm; 1109 uint32_t cca_cck; 1110 uint32_t cca_time; 1111 uint8_t basic; 1112 uint8_t reserved2[3]; 1113 uint32_t ofdm[8]; 1114 uint32_t cck[8]; 1115 uint32_t stop; 1116 uint32_t status; 1117 #define IWN_MEASUREMENT_OK 0 1118 #define IWN_MEASUREMENT_CONCURRENT 1 1119 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1120 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1121 #define IWN_MEASUREMENT_STOPPED 6 1122 #define IWN_MEASUREMENT_TIMEOUT 7 1123 #define IWN_MEASUREMENT_FAILED 8 1124 } __packed; 1125 1126 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1127 struct iwn_rx_phy_stats { 1128 uint32_t ina; 1129 uint32_t fina; 1130 uint32_t bad_plcp; 1131 uint32_t bad_crc32; 1132 uint32_t overrun; 1133 uint32_t eoverrun; 1134 uint32_t good_crc32; 1135 uint32_t fa; 1136 uint32_t bad_fina_sync; 1137 uint32_t sfd_timeout; 1138 uint32_t fina_timeout; 1139 uint32_t no_rts_ack; 1140 uint32_t rxe_limit; 1141 uint32_t ack; 1142 uint32_t cts; 1143 uint32_t ba_resp; 1144 uint32_t dsp_kill; 1145 uint32_t bad_mh; 1146 uint32_t rssi_sum; 1147 uint32_t reserved; 1148 } __packed; 1149 1150 struct iwn_rx_general_stats { 1151 uint32_t bad_cts; 1152 uint32_t bad_ack; 1153 uint32_t not_bss; 1154 uint32_t filtered; 1155 uint32_t bad_chan; 1156 uint32_t beacons; 1157 uint32_t missed_beacons; 1158 uint32_t adc_saturated; /* time in 0.8us */ 1159 uint32_t ina_searched; /* time in 0.8us */ 1160 uint32_t noise[3]; 1161 uint32_t flags; 1162 uint32_t load; 1163 uint32_t fa; 1164 uint32_t rssi[3]; 1165 uint32_t energy[3]; 1166 } __packed; 1167 1168 struct iwn_rx_ht_phy_stats { 1169 uint32_t bad_plcp; 1170 uint32_t overrun; 1171 uint32_t eoverrun; 1172 uint32_t good_crc32; 1173 uint32_t bad_crc32; 1174 uint32_t bad_mh; 1175 uint32_t good_ampdu_crc32; 1176 uint32_t ampdu; 1177 uint32_t fragment; 1178 uint32_t reserved; 1179 } __packed; 1180 1181 struct iwn_rx_stats { 1182 struct iwn_rx_phy_stats ofdm; 1183 struct iwn_rx_phy_stats cck; 1184 struct iwn_rx_general_stats general; 1185 struct iwn_rx_ht_phy_stats ht; 1186 } __packed; 1187 1188 struct iwn_tx_stats { 1189 uint32_t preamble; 1190 uint32_t rx_detected; 1191 uint32_t bt_defer; 1192 uint32_t bt_kill; 1193 uint32_t short_len; 1194 uint32_t cts_timeout; 1195 uint32_t ack_timeout; 1196 uint32_t exp_ack; 1197 uint32_t ack; 1198 uint32_t msdu; 1199 uint32_t busrt_err1; 1200 uint32_t burst_err2; 1201 uint32_t cts_collision; 1202 uint32_t ack_collision; 1203 uint32_t ba_timeout; 1204 uint32_t ba_resched; 1205 uint32_t query_ampdu; 1206 uint32_t query; 1207 uint32_t query_ampdu_frag; 1208 uint32_t query_mismatch; 1209 uint32_t not_ready; 1210 uint32_t underrun; 1211 uint32_t bt_ht_kill; 1212 uint32_t rx_ba_resp; 1213 uint32_t reserved[2]; 1214 } __packed; 1215 1216 struct iwn_general_stats { 1217 uint32_t temp; 1218 uint32_t temp_m; 1219 uint32_t burst_check; 1220 uint32_t burst; 1221 uint32_t reserved1[4]; 1222 uint32_t sleep; 1223 uint32_t slot_out; 1224 uint32_t slot_idle; 1225 uint32_t ttl_tstamp; 1226 uint32_t tx_ant_a; 1227 uint32_t tx_ant_b; 1228 uint32_t exec; 1229 uint32_t probe; 1230 uint32_t reserved2[2]; 1231 uint32_t rx_enabled; 1232 uint32_t reserved3[3]; 1233 } __packed; 1234 1235 struct iwn_stats { 1236 uint32_t flags; 1237 struct iwn_rx_stats rx; 1238 struct iwn_tx_stats tx; 1239 struct iwn_general_stats general; 1240 } __packed; 1241 1242 1243 /* Firmware error dump. */ 1244 struct iwn_fw_dump { 1245 uint32_t valid; 1246 uint32_t id; 1247 uint32_t pc; 1248 uint32_t branch_link[2]; 1249 uint32_t interrupt_link[2]; 1250 uint32_t error_data[2]; 1251 uint32_t src_line; 1252 uint32_t tsf; 1253 uint32_t time[2]; 1254 } __packed; 1255 1256 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1257 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1258 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1259 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1260 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1261 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1262 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1263 1264 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1265 1266 /* 1267 * Offsets into EEPROM. 1268 */ 1269 #define IWN_EEPROM_MAC 0x015 1270 #define IWN_EEPROM_RFCFG 0x048 1271 #define IWN4965_EEPROM_DOMAIN 0x060 1272 #define IWN4965_EEPROM_BAND1 0x063 1273 #define IWN5000_EEPROM_REG 0x066 1274 #define IWN5000_EEPROM_CAL 0x067 1275 #define IWN4965_EEPROM_BAND2 0x072 1276 #define IWN4965_EEPROM_BAND3 0x080 1277 #define IWN4965_EEPROM_BAND4 0x08d 1278 #define IWN4965_EEPROM_BAND5 0x099 1279 #define IWN4965_EEPROM_BAND6 0x0a0 1280 #define IWN4965_EEPROM_BAND7 0x0a8 1281 #define IWN4965_EEPROM_MAXPOW 0x0e8 1282 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1283 #define IWN4965_EEPROM_BANDS 0x0ea 1284 /* Indirect offsets. */ 1285 #define IWN5000_EEPROM_DOMAIN 0x001 1286 #define IWN5000_EEPROM_BAND1 0x004 1287 #define IWN5000_EEPROM_BAND2 0x013 1288 #define IWN5000_EEPROM_BAND3 0x021 1289 #define IWN5000_EEPROM_BAND4 0x02e 1290 #define IWN5000_EEPROM_BAND5 0x03a 1291 #define IWN5000_EEPROM_BAND6 0x041 1292 #define IWN5000_EEPROM_BAND7 0x049 1293 #define IWN6000_EEPROM_ENHINFO 0x054 1294 #define IWN5000_EEPROM_CRYSTAL 0x128 1295 #define IWN5000_EEPROM_TEMP 0x12a 1296 #define IWN5000_EEPROM_VOLT 0x12b 1297 1298 /* Possible flags for IWN_EEPROM_RFCFG. */ 1299 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1300 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1301 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1302 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1303 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1304 1305 struct iwn_eeprom_chan { 1306 uint8_t flags; 1307 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1308 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1309 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1310 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1311 1312 int8_t maxpwr; 1313 } __packed; 1314 1315 struct iwn_eeprom_enhinfo { 1316 uint16_t chan; 1317 int8_t chain[3]; /* max power in half-dBm */ 1318 uint8_t reserved; 1319 int8_t mimo2; /* max power in half-dBm */ 1320 int8_t mimo3; /* max power in half-dBm */ 1321 } __packed; 1322 1323 struct iwn5000_eeprom_calib_hdr { 1324 uint8_t version; 1325 uint8_t pa_type; 1326 uint16_t volt; 1327 } __packed; 1328 1329 #define IWN_NSAMPLES 3 1330 struct iwn4965_eeprom_chan_samples { 1331 uint8_t num; 1332 struct { 1333 uint8_t temp; 1334 uint8_t gain; 1335 uint8_t power; 1336 int8_t pa_det; 1337 } samples[2][IWN_NSAMPLES]; 1338 } __packed; 1339 1340 #define IWN_NBANDS 8 1341 struct iwn4965_eeprom_band { 1342 uint8_t lo; /* low channel number */ 1343 uint8_t hi; /* high channel number */ 1344 struct iwn4965_eeprom_chan_samples chans[2]; 1345 } __packed; 1346 1347 /* 1348 * Offsets of channels descriptions in EEPROM. 1349 */ 1350 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1351 IWN4965_EEPROM_BAND1, 1352 IWN4965_EEPROM_BAND2, 1353 IWN4965_EEPROM_BAND3, 1354 IWN4965_EEPROM_BAND4, 1355 IWN4965_EEPROM_BAND5, 1356 IWN4965_EEPROM_BAND6, 1357 IWN4965_EEPROM_BAND7 1358 }; 1359 1360 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1361 IWN5000_EEPROM_BAND1, 1362 IWN5000_EEPROM_BAND2, 1363 IWN5000_EEPROM_BAND3, 1364 IWN5000_EEPROM_BAND4, 1365 IWN5000_EEPROM_BAND5, 1366 IWN5000_EEPROM_BAND6, 1367 IWN5000_EEPROM_BAND7 1368 }; 1369 1370 #define IWN_CHAN_BANDS_COUNT 7 1371 #define IWN_MAX_CHAN_PER_BAND 14 1372 static const struct iwn_chan_band { 1373 uint8_t nchan; 1374 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1375 } iwn_bands[] = { 1376 /* 20MHz channels, 2GHz band. */ 1377 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1378 /* 20MHz channels, 5GHz band. */ 1379 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1380 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1381 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1382 { 6, { 145, 149, 153, 157, 161, 165 } }, 1383 /* 40MHz channels (primary channels), 2GHz band. */ 1384 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1385 /* 40MHz channels (primary channels), 5GHz band. */ 1386 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1387 }; 1388 1389 #define IWN1000_OTP_NBLOCKS 3 1390 #define IWN6000_OTP_NBLOCKS 4 1391 #define IWN6050_OTP_NBLOCKS 7 1392 1393 /* HW rate indices. */ 1394 #define IWN_RIDX_CCK1 0 1395 #define IWN_RIDX_OFDM6 4 1396 1397 static const struct iwn_rate { 1398 uint8_t rate; 1399 uint8_t plcp; 1400 uint8_t flags; 1401 } iwn_rates[IWN_RIDX_MAX + 1] = { 1402 { 2, 10, IWN_RFLAG_CCK }, 1403 { 4, 20, IWN_RFLAG_CCK }, 1404 { 11, 55, IWN_RFLAG_CCK }, 1405 { 22, 110, IWN_RFLAG_CCK }, 1406 { 12, 0xd, 0 }, 1407 { 18, 0xf, 0 }, 1408 { 24, 0x5, 0 }, 1409 { 36, 0x7, 0 }, 1410 { 48, 0x9, 0 }, 1411 { 72, 0xb, 0 }, 1412 { 96, 0x1, 0 }, 1413 { 108, 0x3, 0 }, 1414 { 120, 0x3, 0 } 1415 }; 1416 1417 #define IWN4965_MAX_PWR_INDEX 107 1418 1419 /* 1420 * RF Tx gain values from highest to lowest power (values obtained from 1421 * the reference driver.) 1422 */ 1423 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1424 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1425 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1426 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1427 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1428 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1429 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1430 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1432 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1433 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1434 }; 1435 1436 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1437 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1438 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1439 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1440 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1441 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1442 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1443 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1444 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1445 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1446 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1447 }; 1448 1449 /* 1450 * DSP pre-DAC gain values from highest to lowest power (values obtained 1451 * from the reference driver.) 1452 */ 1453 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1454 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1455 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1456 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1457 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1458 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1459 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1460 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1461 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1462 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1463 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1464 }; 1465 1466 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1467 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1468 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1469 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1470 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1471 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1472 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1473 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1474 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1475 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1476 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1477 }; 1478 1479 /* 1480 * Power saving settings (values obtained from the reference driver.) 1481 */ 1482 #define IWN_NDTIMRANGES 3 1483 #define IWN_NPOWERLEVELS 6 1484 static const struct iwn_pmgt { 1485 uint32_t rxtimeout; 1486 uint32_t txtimeout; 1487 uint32_t intval[5]; 1488 int skip_dtim; 1489 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1490 /* DTIM <= 2 */ 1491 { 1492 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1493 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1494 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1495 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1496 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1497 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1498 }, 1499 /* 3 <= DTIM <= 10 */ 1500 { 1501 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1502 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1503 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1504 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1505 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1506 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1507 }, 1508 /* DTIM >= 11 */ 1509 { 1510 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1511 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1512 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1513 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1514 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1515 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1516 } 1517 }; 1518 1519 struct iwn_sensitivity_limits { 1520 uint32_t min_ofdm_x1; 1521 uint32_t max_ofdm_x1; 1522 uint32_t min_ofdm_mrc_x1; 1523 uint32_t max_ofdm_mrc_x1; 1524 uint32_t min_ofdm_x4; 1525 uint32_t max_ofdm_x4; 1526 uint32_t min_ofdm_mrc_x4; 1527 uint32_t max_ofdm_mrc_x4; 1528 uint32_t min_cck_x4; 1529 uint32_t max_cck_x4; 1530 uint32_t min_cck_mrc_x4; 1531 uint32_t max_cck_mrc_x4; 1532 uint32_t min_energy_cck; 1533 uint32_t energy_cck; 1534 uint32_t energy_ofdm; 1535 }; 1536 1537 /* 1538 * RX sensitivity limits (values obtained from the reference driver.) 1539 */ 1540 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1541 105, 140, 1542 220, 270, 1543 85, 120, 1544 170, 210, 1545 125, 200, 1546 200, 400, 1547 97, 1548 100, 1549 100 1550 }; 1551 1552 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1553 120, 120, /* min = max for performance bug in DSP. */ 1554 240, 240, /* min = max for performance bug in DSP. */ 1555 90, 120, 1556 170, 210, 1557 125, 200, 1558 170, 400, 1559 95, 1560 95, 1561 95 1562 }; 1563 1564 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1565 105, 105, /* min = max for performance bug in DSP. */ 1566 220, 220, /* min = max for performance bug in DSP. */ 1567 90, 120, 1568 170, 210, 1569 125, 200, 1570 170, 400, 1571 95, 1572 95, 1573 95 1574 }; 1575 1576 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1577 120, 155, 1578 240, 290, 1579 90, 120, 1580 170, 210, 1581 125, 200, 1582 170, 400, 1583 95, 1584 95, 1585 95 1586 }; 1587 1588 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1589 105, 110, 1590 192, 232, 1591 80, 145, 1592 128, 232, 1593 125, 175, 1594 160, 310, 1595 97, 1596 97, 1597 100 1598 }; 1599 1600 /* Map TID to TX scheduler's FIFO. */ 1601 static const uint8_t iwn_tid2fifo[] = { 1602 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1603 }; 1604 1605 /* WiFi/WiMAX coexist event priority table for 6050. */ 1606 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1607 { 0x04, 0x03, 0x00, 0x00 }, 1608 { 0x04, 0x03, 0x00, 0x03 }, 1609 { 0x04, 0x03, 0x00, 0x03 }, 1610 { 0x04, 0x03, 0x00, 0x03 }, 1611 { 0x04, 0x03, 0x00, 0x00 }, 1612 { 0x04, 0x03, 0x00, 0x07 }, 1613 { 0x04, 0x03, 0x00, 0x00 }, 1614 { 0x04, 0x03, 0x00, 0x03 }, 1615 { 0x04, 0x03, 0x00, 0x03 }, 1616 { 0x04, 0x03, 0x00, 0x00 }, 1617 { 0x06, 0x03, 0x00, 0x07 }, 1618 { 0x04, 0x03, 0x00, 0x00 }, 1619 { 0x06, 0x06, 0x00, 0x03 }, 1620 { 0x04, 0x03, 0x00, 0x07 }, 1621 { 0x04, 0x03, 0x00, 0x00 }, 1622 { 0x04, 0x03, 0x00, 0x00 } 1623 }; 1624 1625 /* Firmware errors. */ 1626 static const char * const iwn_fw_errmsg[] = { 1627 "OK", 1628 "FAIL", 1629 "BAD_PARAM", 1630 "BAD_CHECKSUM", 1631 "NMI_INTERRUPT_WDG", 1632 "SYSASSERT", 1633 "FATAL_ERROR", 1634 "BAD_COMMAND", 1635 "HW_ERROR_TUNE_LOCK", 1636 "HW_ERROR_TEMPERATURE", 1637 "ILLEGAL_CHAN_FREQ", 1638 "VCC_NOT_STABLE", 1639 "FH_ERROR", 1640 "NMI_INTERRUPT_HOST", 1641 "NMI_INTERRUPT_ACTION_PT", 1642 "NMI_INTERRUPT_UNKNOWN", 1643 "UCODE_VERSION_MISMATCH", 1644 "HW_ERROR_ABS_LOCK", 1645 "HW_ERROR_CAL_LOCK_FAIL", 1646 "NMI_INTERRUPT_INST_ACTION_PT", 1647 "NMI_INTERRUPT_DATA_ACTION_PT", 1648 "NMI_TRM_HW_ER", 1649 "NMI_INTERRUPT_TRM", 1650 "NMI_INTERRUPT_BREAKPOINT" 1651 "DEBUG_0", 1652 "DEBUG_1", 1653 "DEBUG_2", 1654 "DEBUG_3", 1655 "ADVANCED_SYSASSERT" 1656 }; 1657 1658 /* Find least significant bit that is set. */ 1659 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1660 1661 #define IWN_READ(sc, reg) \ 1662 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1663 1664 #define IWN_WRITE(sc, reg, val) \ 1665 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1666 1667 #define IWN_WRITE_1(sc, reg, val) \ 1668 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1669 1670 #define IWN_SETBITS(sc, reg, mask) \ 1671 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1672 1673 #define IWN_CLRBITS(sc, reg, mask) \ 1674 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1675 1676 #define IWN_BARRIER_WRITE(sc) \ 1677 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1678 BUS_SPACE_BARRIER_WRITE) 1679 1680 #define IWN_BARRIER_READ_WRITE(sc) \ 1681 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1682 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1683 1684
Indexes created Fri Oct 17 00:09:41 GMT 2025