if_ixl.c revision 1.60
1 /* $NetBSD: if_ixl.c,v 1.60 2020/03/03 04:55:46 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg (at) openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 /* 51 * Copyright (c) 2019 Internet Initiative Japan, Inc. 52 * All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 64 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 65 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 66 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 67 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 68 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 69 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 70 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 71 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 72 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 73 * POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.60 2020/03/03 04:55:46 yamaguchi Exp $"); 78 79 #ifdef _KERNEL_OPT 80 #include "opt_net_mpsafe.h" 81 #include "opt_if_ixl.h" 82 #endif 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/cpu.h> 88 #include <sys/device.h> 89 #include <sys/evcnt.h> 90 #include <sys/interrupt.h> 91 #include <sys/kmem.h> 92 #include <sys/module.h> 93 #include <sys/mutex.h> 94 #include <sys/pcq.h> 95 #include <sys/syslog.h> 96 #include <sys/workqueue.h> 97 98 #include <sys/bus.h> 99 100 #include <net/bpf.h> 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 #include <net/rss_config.h> 106 107 #include <netinet/tcp.h> /* for struct tcphdr */ 108 #include <netinet/udp.h> /* for struct udphdr */ 109 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_ixlreg.h> 114 #include <dev/pci/if_ixlvar.h> 115 116 #include <prop/proplib.h> 117 118 struct ixl_softc; /* defined */ 119 120 #define I40E_PF_RESET_WAIT_COUNT 200 121 #define I40E_AQ_LARGE_BUF 512 122 123 /* bitfields for Tx queue mapping in QTX_CTL */ 124 #define I40E_QTX_CTL_VF_QUEUE 0x0 125 #define I40E_QTX_CTL_VM_QUEUE 0x1 126 #define I40E_QTX_CTL_PF_QUEUE 0x2 127 128 #define I40E_QUEUE_TYPE_EOL 0x7ff 129 #define I40E_INTR_NOTX_QUEUE 0 130 131 #define I40E_QUEUE_TYPE_RX 0x0 132 #define I40E_QUEUE_TYPE_TX 0x1 133 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 134 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 135 136 #define I40E_ITR_INDEX_RX 0x0 137 #define I40E_ITR_INDEX_TX 0x1 138 #define I40E_ITR_INDEX_OTHER 0x2 139 #define I40E_ITR_INDEX_NONE 0x3 140 141 #define I40E_INTR_NOTX_QUEUE 0 142 #define I40E_INTR_NOTX_INTR 0 143 #define I40E_INTR_NOTX_RX_QUEUE 0 144 #define I40E_INTR_NOTX_TX_QUEUE 1 145 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 146 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 147 148 #define BIT_ULL(a) (1ULL << (a)) 149 #define IXL_RSS_HENA_DEFAULT_BASE \ 150 (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 151 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 152 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 153 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 154 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 155 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 156 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 157 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 158 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 159 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 160 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 161 #define IXL_RSS_HENA_DEFAULT_XL710 IXL_RSS_HENA_DEFAULT_BASE 162 #define IXL_RSS_HENA_DEFAULT_X722 (IXL_RSS_HENA_DEFAULT_XL710 | \ 163 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 164 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 165 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 166 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 167 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 168 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK)) 169 #define I40E_HASH_LUT_SIZE_128 0 170 #define IXL_RSS_KEY_SIZE_REG 13 171 172 #define IXL_ICR0_CRIT_ERR_MASK \ 173 (I40E_PFINT_ICR0_PCI_EXCEPTION_MASK | \ 174 I40E_PFINT_ICR0_ECC_ERR_MASK | \ 175 I40E_PFINT_ICR0_PE_CRITERR_MASK) 176 177 #define IXL_QUEUE_MAX_XL710 64 178 #define IXL_QUEUE_MAX_X722 128 179 180 #define IXL_TX_PKT_DESCS 8 181 #define IXL_TX_PKT_MAXSIZE (MCLBYTES * IXL_TX_PKT_DESCS) 182 #define IXL_TX_QUEUE_ALIGN 128 183 #define IXL_RX_QUEUE_ALIGN 128 184 185 #define IXL_MCLBYTES (MCLBYTES - ETHER_ALIGN) 186 #define IXL_MTU_ETHERLEN ETHER_HDR_LEN \ 187 + ETHER_CRC_LEN 188 #if 0 189 #define IXL_MAX_MTU (9728 - IXL_MTU_ETHERLEN) 190 #else 191 /* (dbuff * 5) - ETHER_HDR_LEN - ETHER_CRC_LEN */ 192 #define IXL_MAX_MTU (9600 - IXL_MTU_ETHERLEN) 193 #endif 194 #define IXL_MIN_MTU (ETHER_MIN_LEN - ETHER_CRC_LEN) 195 196 #define IXL_PCIREG PCI_MAPREG_START 197 198 #define IXL_ITR0 0x0 199 #define IXL_ITR1 0x1 200 #define IXL_ITR2 0x2 201 #define IXL_NOITR 0x3 202 203 #define IXL_AQ_NUM 256 204 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 205 #define IXL_AQ_ALIGN 64 /* lol */ 206 #define IXL_AQ_BUFLEN 4096 207 208 #define IXL_HMC_ROUNDUP 512 209 #define IXL_HMC_PGSIZE 4096 210 #define IXL_HMC_DVASZ sizeof(uint64_t) 211 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 212 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 213 #define IXL_HMC_PDVALID 1ULL 214 215 #define IXL_ATQ_EXEC_TIMEOUT (10 * hz) 216 217 #define IXL_SRRD_SRCTL_ATTEMPTS 100000 218 219 struct ixl_aq_regs { 220 bus_size_t atq_tail; 221 bus_size_t atq_head; 222 bus_size_t atq_len; 223 bus_size_t atq_bal; 224 bus_size_t atq_bah; 225 226 bus_size_t arq_tail; 227 bus_size_t arq_head; 228 bus_size_t arq_len; 229 bus_size_t arq_bal; 230 bus_size_t arq_bah; 231 232 uint32_t atq_len_enable; 233 uint32_t atq_tail_mask; 234 uint32_t atq_head_mask; 235 236 uint32_t arq_len_enable; 237 uint32_t arq_tail_mask; 238 uint32_t arq_head_mask; 239 }; 240 241 struct ixl_phy_type { 242 uint64_t phy_type; 243 uint64_t ifm_type; 244 }; 245 246 struct ixl_speed_type { 247 uint8_t dev_speed; 248 uint64_t net_speed; 249 }; 250 251 struct ixl_aq_buf { 252 SIMPLEQ_ENTRY(ixl_aq_buf) 253 aqb_entry; 254 void *aqb_data; 255 bus_dmamap_t aqb_map; 256 bus_dma_segment_t aqb_seg; 257 size_t aqb_size; 258 int aqb_nsegs; 259 }; 260 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 261 262 struct ixl_dmamem { 263 bus_dmamap_t ixm_map; 264 bus_dma_segment_t ixm_seg; 265 int ixm_nsegs; 266 size_t ixm_size; 267 void *ixm_kva; 268 }; 269 270 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 271 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 272 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 273 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 274 275 struct ixl_hmc_entry { 276 uint64_t hmc_base; 277 uint32_t hmc_count; 278 uint64_t hmc_size; 279 }; 280 281 enum ixl_hmc_types { 282 IXL_HMC_LAN_TX = 0, 283 IXL_HMC_LAN_RX, 284 IXL_HMC_FCOE_CTX, 285 IXL_HMC_FCOE_FILTER, 286 IXL_HMC_COUNT 287 }; 288 289 struct ixl_hmc_pack { 290 uint16_t offset; 291 uint16_t width; 292 uint16_t lsb; 293 }; 294 295 /* 296 * these hmc objects have weird sizes and alignments, so these are abstract 297 * representations of them that are nice for c to populate. 298 * 299 * the packing code relies on little-endian values being stored in the fields, 300 * no high bits in the fields being set, and the fields must be packed in the 301 * same order as they are in the ctx structure. 302 */ 303 304 struct ixl_hmc_rxq { 305 uint16_t head; 306 uint8_t cpuid; 307 uint64_t base; 308 #define IXL_HMC_RXQ_BASE_UNIT 128 309 uint16_t qlen; 310 uint16_t dbuff; 311 #define IXL_HMC_RXQ_DBUFF_UNIT 128 312 uint8_t hbuff; 313 #define IXL_HMC_RXQ_HBUFF_UNIT 64 314 uint8_t dtype; 315 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 316 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 317 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 318 uint8_t dsize; 319 #define IXL_HMC_RXQ_DSIZE_16 0 320 #define IXL_HMC_RXQ_DSIZE_32 1 321 uint8_t crcstrip; 322 uint8_t fc_ena; 323 uint8_t l2sel; 324 uint8_t hsplit_0; 325 uint8_t hsplit_1; 326 uint8_t showiv; 327 uint16_t rxmax; 328 uint8_t tphrdesc_ena; 329 uint8_t tphwdesc_ena; 330 uint8_t tphdata_ena; 331 uint8_t tphhead_ena; 332 uint8_t lrxqthresh; 333 uint8_t prefena; 334 }; 335 336 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 337 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 338 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 339 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 340 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 341 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 342 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 343 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 344 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 345 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 346 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 347 { offsetof(struct ixl_hmc_rxq, l2sel), 1, 119 }, 348 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 349 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 350 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 351 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 352 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 353 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 354 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 355 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 356 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 357 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 358 }; 359 360 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 361 362 struct ixl_hmc_txq { 363 uint16_t head; 364 uint8_t new_context; 365 uint64_t base; 366 #define IXL_HMC_TXQ_BASE_UNIT 128 367 uint8_t fc_ena; 368 uint8_t timesync_ena; 369 uint8_t fd_ena; 370 uint8_t alt_vlan_ena; 371 uint8_t cpuid; 372 uint16_t thead_wb; 373 uint8_t head_wb_ena; 374 #define IXL_HMC_TXQ_DESC_WB 0 375 #define IXL_HMC_TXQ_HEAD_WB 1 376 uint16_t qlen; 377 uint8_t tphrdesc_ena; 378 uint8_t tphrpacket_ena; 379 uint8_t tphwdesc_ena; 380 uint64_t head_wb_addr; 381 uint32_t crc; 382 uint16_t rdylist; 383 uint8_t rdylist_act; 384 }; 385 386 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 387 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 388 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 389 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 390 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 391 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 392 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 393 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 394 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 395 /* line 1 */ 396 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 397 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 398 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 399 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 400 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 401 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 402 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 403 /* line 7 */ 404 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 405 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 406 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 407 }; 408 409 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 410 411 struct ixl_work { 412 struct work ixw_cookie; 413 void (*ixw_func)(void *); 414 void *ixw_arg; 415 unsigned int ixw_added; 416 }; 417 #define IXL_WORKQUEUE_PRI PRI_SOFTNET 418 419 struct ixl_tx_map { 420 struct mbuf *txm_m; 421 bus_dmamap_t txm_map; 422 unsigned int txm_eop; 423 }; 424 425 struct ixl_tx_ring { 426 kmutex_t txr_lock; 427 struct ixl_softc *txr_sc; 428 429 unsigned int txr_prod; 430 unsigned int txr_cons; 431 432 struct ixl_tx_map *txr_maps; 433 struct ixl_dmamem txr_mem; 434 435 bus_size_t txr_tail; 436 unsigned int txr_qid; 437 pcq_t *txr_intrq; 438 void *txr_si; 439 440 struct evcnt txr_defragged; 441 struct evcnt txr_defrag_failed; 442 struct evcnt txr_pcqdrop; 443 struct evcnt txr_transmitdef; 444 struct evcnt txr_intr; 445 struct evcnt txr_defer; 446 }; 447 448 struct ixl_rx_map { 449 struct mbuf *rxm_m; 450 bus_dmamap_t rxm_map; 451 }; 452 453 struct ixl_rx_ring { 454 kmutex_t rxr_lock; 455 456 unsigned int rxr_prod; 457 unsigned int rxr_cons; 458 459 struct ixl_rx_map *rxr_maps; 460 struct ixl_dmamem rxr_mem; 461 462 struct mbuf *rxr_m_head; 463 struct mbuf **rxr_m_tail; 464 465 bus_size_t rxr_tail; 466 unsigned int rxr_qid; 467 468 struct evcnt rxr_mgethdr_failed; 469 struct evcnt rxr_mgetcl_failed; 470 struct evcnt rxr_mbuf_load_failed; 471 struct evcnt rxr_intr; 472 struct evcnt rxr_defer; 473 }; 474 475 struct ixl_queue_pair { 476 struct ixl_softc *qp_sc; 477 struct ixl_tx_ring *qp_txr; 478 struct ixl_rx_ring *qp_rxr; 479 480 char qp_name[16]; 481 482 void *qp_si; 483 struct work qp_work; 484 bool qp_workqueue; 485 }; 486 487 struct ixl_atq { 488 struct ixl_aq_desc iatq_desc; 489 void (*iatq_fn)(struct ixl_softc *, 490 const struct ixl_aq_desc *); 491 }; 492 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 493 494 struct ixl_product { 495 unsigned int vendor_id; 496 unsigned int product_id; 497 }; 498 499 struct ixl_stats_counters { 500 bool isc_has_offset; 501 struct evcnt isc_crc_errors; 502 uint64_t isc_crc_errors_offset; 503 struct evcnt isc_illegal_bytes; 504 uint64_t isc_illegal_bytes_offset; 505 struct evcnt isc_rx_bytes; 506 uint64_t isc_rx_bytes_offset; 507 struct evcnt isc_rx_discards; 508 uint64_t isc_rx_discards_offset; 509 struct evcnt isc_rx_unicast; 510 uint64_t isc_rx_unicast_offset; 511 struct evcnt isc_rx_multicast; 512 uint64_t isc_rx_multicast_offset; 513 struct evcnt isc_rx_broadcast; 514 uint64_t isc_rx_broadcast_offset; 515 struct evcnt isc_rx_size_64; 516 uint64_t isc_rx_size_64_offset; 517 struct evcnt isc_rx_size_127; 518 uint64_t isc_rx_size_127_offset; 519 struct evcnt isc_rx_size_255; 520 uint64_t isc_rx_size_255_offset; 521 struct evcnt isc_rx_size_511; 522 uint64_t isc_rx_size_511_offset; 523 struct evcnt isc_rx_size_1023; 524 uint64_t isc_rx_size_1023_offset; 525 struct evcnt isc_rx_size_1522; 526 uint64_t isc_rx_size_1522_offset; 527 struct evcnt isc_rx_size_big; 528 uint64_t isc_rx_size_big_offset; 529 struct evcnt isc_rx_undersize; 530 uint64_t isc_rx_undersize_offset; 531 struct evcnt isc_rx_oversize; 532 uint64_t isc_rx_oversize_offset; 533 struct evcnt isc_rx_fragments; 534 uint64_t isc_rx_fragments_offset; 535 struct evcnt isc_rx_jabber; 536 uint64_t isc_rx_jabber_offset; 537 struct evcnt isc_tx_bytes; 538 uint64_t isc_tx_bytes_offset; 539 struct evcnt isc_tx_dropped_link_down; 540 uint64_t isc_tx_dropped_link_down_offset; 541 struct evcnt isc_tx_unicast; 542 uint64_t isc_tx_unicast_offset; 543 struct evcnt isc_tx_multicast; 544 uint64_t isc_tx_multicast_offset; 545 struct evcnt isc_tx_broadcast; 546 uint64_t isc_tx_broadcast_offset; 547 struct evcnt isc_tx_size_64; 548 uint64_t isc_tx_size_64_offset; 549 struct evcnt isc_tx_size_127; 550 uint64_t isc_tx_size_127_offset; 551 struct evcnt isc_tx_size_255; 552 uint64_t isc_tx_size_255_offset; 553 struct evcnt isc_tx_size_511; 554 uint64_t isc_tx_size_511_offset; 555 struct evcnt isc_tx_size_1023; 556 uint64_t isc_tx_size_1023_offset; 557 struct evcnt isc_tx_size_1522; 558 uint64_t isc_tx_size_1522_offset; 559 struct evcnt isc_tx_size_big; 560 uint64_t isc_tx_size_big_offset; 561 struct evcnt isc_mac_local_faults; 562 uint64_t isc_mac_local_faults_offset; 563 struct evcnt isc_mac_remote_faults; 564 uint64_t isc_mac_remote_faults_offset; 565 struct evcnt isc_link_xon_rx; 566 uint64_t isc_link_xon_rx_offset; 567 struct evcnt isc_link_xon_tx; 568 uint64_t isc_link_xon_tx_offset; 569 struct evcnt isc_link_xoff_rx; 570 uint64_t isc_link_xoff_rx_offset; 571 struct evcnt isc_link_xoff_tx; 572 uint64_t isc_link_xoff_tx_offset; 573 struct evcnt isc_vsi_rx_discards; 574 uint64_t isc_vsi_rx_discards_offset; 575 struct evcnt isc_vsi_rx_bytes; 576 uint64_t isc_vsi_rx_bytes_offset; 577 struct evcnt isc_vsi_rx_unicast; 578 uint64_t isc_vsi_rx_unicast_offset; 579 struct evcnt isc_vsi_rx_multicast; 580 uint64_t isc_vsi_rx_multicast_offset; 581 struct evcnt isc_vsi_rx_broadcast; 582 uint64_t isc_vsi_rx_broadcast_offset; 583 struct evcnt isc_vsi_tx_errors; 584 uint64_t isc_vsi_tx_errors_offset; 585 struct evcnt isc_vsi_tx_bytes; 586 uint64_t isc_vsi_tx_bytes_offset; 587 struct evcnt isc_vsi_tx_unicast; 588 uint64_t isc_vsi_tx_unicast_offset; 589 struct evcnt isc_vsi_tx_multicast; 590 uint64_t isc_vsi_tx_multicast_offset; 591 struct evcnt isc_vsi_tx_broadcast; 592 uint64_t isc_vsi_tx_broadcast_offset; 593 }; 594 595 /* 596 * Locking notes: 597 * + a field in ixl_tx_ring is protected by txr_lock (a spin mutex), and 598 * a field in ixl_rx_ring is protected by rxr_lock (a spin mutex). 599 * - more than one lock of them cannot be held at once. 600 * + a field named sc_atq_* in ixl_softc is protected by sc_atq_lock 601 * (a spin mutex). 602 * - the lock cannot held with txr_lock or rxr_lock. 603 * + a field named sc_arq_* is not protected by any lock. 604 * - operations for sc_arq_* is done in one context related to 605 * sc_arq_task. 606 * + other fields in ixl_softc is protected by sc_cfg_lock 607 * (an adaptive mutex) 608 * - It must be held before another lock is held, and It can be 609 * released after the other lock is released. 610 * */ 611 612 struct ixl_softc { 613 device_t sc_dev; 614 struct ethercom sc_ec; 615 bool sc_attached; 616 bool sc_dead; 617 uint32_t sc_port; 618 struct sysctllog *sc_sysctllog; 619 struct workqueue *sc_workq; 620 struct workqueue *sc_workq_txrx; 621 int sc_stats_intval; 622 callout_t sc_stats_callout; 623 struct ixl_work sc_stats_task; 624 struct ixl_stats_counters 625 sc_stats_counters; 626 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 627 struct ifmedia sc_media; 628 uint64_t sc_media_status; 629 uint64_t sc_media_active; 630 uint64_t sc_phy_types; 631 uint8_t sc_phy_abilities; 632 uint8_t sc_phy_linkspeed; 633 uint8_t sc_phy_fec_cfg; 634 uint16_t sc_eee_cap; 635 uint32_t sc_eeer_val; 636 uint8_t sc_d3_lpan; 637 kmutex_t sc_cfg_lock; 638 enum i40e_mac_type sc_mac_type; 639 uint32_t sc_rss_table_size; 640 uint32_t sc_rss_table_entry_width; 641 bool sc_txrx_workqueue; 642 u_int sc_tx_process_limit; 643 u_int sc_rx_process_limit; 644 u_int sc_tx_intr_process_limit; 645 u_int sc_rx_intr_process_limit; 646 647 int sc_cur_ec_capenable; 648 649 struct pci_attach_args sc_pa; 650 pci_intr_handle_t *sc_ihp; 651 void **sc_ihs; 652 unsigned int sc_nintrs; 653 654 bus_dma_tag_t sc_dmat; 655 bus_space_tag_t sc_memt; 656 bus_space_handle_t sc_memh; 657 bus_size_t sc_mems; 658 659 uint8_t sc_pf_id; 660 uint16_t sc_uplink_seid; /* le */ 661 uint16_t sc_downlink_seid; /* le */ 662 uint16_t sc_vsi_number; 663 uint16_t sc_vsi_stat_counter_idx; 664 uint16_t sc_seid; 665 unsigned int sc_base_queue; 666 667 pci_intr_type_t sc_intrtype; 668 unsigned int sc_msix_vector_queue; 669 670 struct ixl_dmamem sc_scratch; 671 struct ixl_dmamem sc_aqbuf; 672 673 const struct ixl_aq_regs * 674 sc_aq_regs; 675 uint32_t sc_aq_flags; 676 #define IXL_SC_AQ_FLAG_RXCTL __BIT(0) 677 #define IXL_SC_AQ_FLAG_NVMLOCK __BIT(1) 678 #define IXL_SC_AQ_FLAG_NVMREAD __BIT(2) 679 #define IXL_SC_AQ_FLAG_RSS __BIT(3) 680 681 kmutex_t sc_atq_lock; 682 kcondvar_t sc_atq_cv; 683 struct ixl_dmamem sc_atq; 684 unsigned int sc_atq_prod; 685 unsigned int sc_atq_cons; 686 687 struct ixl_dmamem sc_arq; 688 struct ixl_work sc_arq_task; 689 struct ixl_aq_bufs sc_arq_idle; 690 struct ixl_aq_buf *sc_arq_live[IXL_AQ_NUM]; 691 unsigned int sc_arq_prod; 692 unsigned int sc_arq_cons; 693 694 struct ixl_work sc_link_state_task; 695 struct ixl_atq sc_link_state_atq; 696 697 struct ixl_dmamem sc_hmc_sd; 698 struct ixl_dmamem sc_hmc_pd; 699 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 700 701 unsigned int sc_tx_ring_ndescs; 702 unsigned int sc_rx_ring_ndescs; 703 unsigned int sc_nqueue_pairs; 704 unsigned int sc_nqueue_pairs_max; 705 unsigned int sc_nqueue_pairs_device; 706 struct ixl_queue_pair *sc_qps; 707 708 struct evcnt sc_event_atq; 709 struct evcnt sc_event_link; 710 struct evcnt sc_event_ecc_err; 711 struct evcnt sc_event_pci_exception; 712 struct evcnt sc_event_crit_err; 713 }; 714 715 #define IXL_TXRX_PROCESS_UNLIMIT UINT_MAX 716 #define IXL_TX_PROCESS_LIMIT 256 717 #define IXL_RX_PROCESS_LIMIT 256 718 #define IXL_TX_INTR_PROCESS_LIMIT 256 719 #define IXL_RX_INTR_PROCESS_LIMIT 0U 720 721 #define IXL_IFCAP_RXCSUM (IFCAP_CSUM_IPv4_Rx | \ 722 IFCAP_CSUM_TCPv4_Rx | \ 723 IFCAP_CSUM_UDPv4_Rx | \ 724 IFCAP_CSUM_TCPv6_Rx | \ 725 IFCAP_CSUM_UDPv6_Rx) 726 #define IXL_IFCAP_TXCSUM (IFCAP_CSUM_IPv4_Tx | \ 727 IFCAP_CSUM_TCPv4_Tx | \ 728 IFCAP_CSUM_UDPv4_Tx | \ 729 IFCAP_CSUM_TCPv6_Tx | \ 730 IFCAP_CSUM_UDPv6_Tx) 731 #define IXL_CSUM_ALL_OFFLOAD (M_CSUM_IPv4 | \ 732 M_CSUM_TCPv4 | M_CSUM_TCPv6 | \ 733 M_CSUM_UDPv4 | M_CSUM_UDPv6) 734 735 #define delaymsec(_x) DELAY(1000 * (_x)) 736 #ifdef IXL_DEBUG 737 #define DDPRINTF(sc, fmt, args...) \ 738 do { \ 739 if ((sc) != NULL) { \ 740 device_printf( \ 741 ((struct ixl_softc *)(sc))->sc_dev, \ 742 ""); \ 743 } \ 744 printf("%s:\t" fmt, __func__, ##args); \ 745 } while (0) 746 #else 747 #define DDPRINTF(sc, fmt, args...) __nothing 748 #endif 749 #ifndef IXL_STATS_INTERVAL_MSEC 750 #define IXL_STATS_INTERVAL_MSEC 10000 751 #endif 752 #ifndef IXL_QUEUE_NUM 753 #define IXL_QUEUE_NUM 0 754 #endif 755 756 static bool ixl_param_nomsix = false; 757 static int ixl_param_stats_interval = IXL_STATS_INTERVAL_MSEC; 758 static int ixl_param_nqps_limit = IXL_QUEUE_NUM; 759 static unsigned int ixl_param_tx_ndescs = 1024; 760 static unsigned int ixl_param_rx_ndescs = 1024; 761 762 static enum i40e_mac_type 763 ixl_mactype(pci_product_id_t); 764 static void ixl_clear_hw(struct ixl_softc *); 765 static int ixl_pf_reset(struct ixl_softc *); 766 767 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 768 bus_size_t, bus_size_t); 769 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 770 771 static int ixl_arq_fill(struct ixl_softc *); 772 static void ixl_arq_unfill(struct ixl_softc *); 773 774 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 775 unsigned int); 776 static void ixl_atq_set(struct ixl_atq *, 777 void (*)(struct ixl_softc *, const struct ixl_aq_desc *)); 778 static int ixl_atq_post_locked(struct ixl_softc *, struct ixl_atq *); 779 static void ixl_atq_done(struct ixl_softc *); 780 static int ixl_atq_exec(struct ixl_softc *, struct ixl_atq *); 781 static int ixl_atq_exec_locked(struct ixl_softc *, struct ixl_atq *); 782 static int ixl_get_version(struct ixl_softc *); 783 static int ixl_get_nvm_version(struct ixl_softc *); 784 static int ixl_get_hw_capabilities(struct ixl_softc *); 785 static int ixl_pxe_clear(struct ixl_softc *); 786 static int ixl_lldp_shut(struct ixl_softc *); 787 static int ixl_get_mac(struct ixl_softc *); 788 static int ixl_get_switch_config(struct ixl_softc *); 789 static int ixl_phy_mask_ints(struct ixl_softc *); 790 static int ixl_get_phy_info(struct ixl_softc *); 791 static int ixl_set_phy_config(struct ixl_softc *, uint8_t, uint8_t, bool); 792 static int ixl_set_phy_autoselect(struct ixl_softc *); 793 static int ixl_restart_an(struct ixl_softc *); 794 static int ixl_hmc(struct ixl_softc *); 795 static void ixl_hmc_free(struct ixl_softc *); 796 static int ixl_get_vsi(struct ixl_softc *); 797 static int ixl_set_vsi(struct ixl_softc *); 798 static void ixl_set_filter_control(struct ixl_softc *); 799 static void ixl_get_link_status(void *); 800 static int ixl_get_link_status_poll(struct ixl_softc *, int *); 801 static void ixl_get_link_status_done(struct ixl_softc *, 802 const struct ixl_aq_desc *); 803 static int ixl_set_link_status(struct ixl_softc *, 804 const struct ixl_aq_desc *); 805 static uint64_t ixl_search_link_speed(uint8_t); 806 static uint8_t ixl_search_baudrate(uint64_t); 807 static void ixl_config_rss(struct ixl_softc *); 808 static int ixl_add_macvlan(struct ixl_softc *, const uint8_t *, 809 uint16_t, uint16_t); 810 static int ixl_remove_macvlan(struct ixl_softc *, const uint8_t *, 811 uint16_t, uint16_t); 812 static void ixl_arq(void *); 813 static void ixl_hmc_pack(void *, const void *, 814 const struct ixl_hmc_pack *, unsigned int); 815 static uint32_t ixl_rd_rx_csr(struct ixl_softc *, uint32_t); 816 static void ixl_wr_rx_csr(struct ixl_softc *, uint32_t, uint32_t); 817 static int ixl_rd16_nvm(struct ixl_softc *, uint16_t, uint16_t *); 818 819 static int ixl_match(device_t, cfdata_t, void *); 820 static void ixl_attach(device_t, device_t, void *); 821 static int ixl_detach(device_t, int); 822 823 static void ixl_media_add(struct ixl_softc *); 824 static int ixl_media_change(struct ifnet *); 825 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 826 static void ixl_watchdog(struct ifnet *); 827 static int ixl_ioctl(struct ifnet *, u_long, void *); 828 static void ixl_start(struct ifnet *); 829 static int ixl_transmit(struct ifnet *, struct mbuf *); 830 static void ixl_deferred_transmit(void *); 831 static int ixl_intr(void *); 832 static int ixl_queue_intr(void *); 833 static int ixl_other_intr(void *); 834 static void ixl_handle_queue(void *); 835 static void ixl_handle_queue_wk(struct work *, void *); 836 static void ixl_sched_handle_queue(struct ixl_softc *, 837 struct ixl_queue_pair *); 838 static int ixl_init(struct ifnet *); 839 static int ixl_init_locked(struct ixl_softc *); 840 static void ixl_stop(struct ifnet *, int); 841 static void ixl_stop_locked(struct ixl_softc *); 842 static int ixl_iff(struct ixl_softc *); 843 static int ixl_ifflags_cb(struct ethercom *); 844 static int ixl_setup_interrupts(struct ixl_softc *); 845 static int ixl_establish_intx(struct ixl_softc *); 846 static int ixl_establish_msix(struct ixl_softc *); 847 static void ixl_enable_queue_intr(struct ixl_softc *, 848 struct ixl_queue_pair *); 849 static void ixl_disable_queue_intr(struct ixl_softc *, 850 struct ixl_queue_pair *); 851 static void ixl_enable_other_intr(struct ixl_softc *); 852 static void ixl_disable_other_intr(struct ixl_softc *); 853 static void ixl_config_queue_intr(struct ixl_softc *); 854 static void ixl_config_other_intr(struct ixl_softc *); 855 856 static struct ixl_tx_ring * 857 ixl_txr_alloc(struct ixl_softc *, unsigned int); 858 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 859 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 860 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 861 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 862 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 863 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 864 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 865 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *, u_int); 866 867 static struct ixl_rx_ring * 868 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 869 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 870 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 871 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 872 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 873 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 874 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 875 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *, u_int); 876 static int ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 877 878 static struct workqueue * 879 ixl_workq_create(const char *, pri_t, int, int); 880 static void ixl_workq_destroy(struct workqueue *); 881 static int ixl_workqs_teardown(device_t); 882 static void ixl_work_set(struct ixl_work *, void (*)(void *), void *); 883 static void ixl_work_add(struct workqueue *, struct ixl_work *); 884 static void ixl_work_wait(struct workqueue *, struct ixl_work *); 885 static void ixl_workq_work(struct work *, void *); 886 static const struct ixl_product * 887 ixl_lookup(const struct pci_attach_args *pa); 888 static void ixl_link_state_update(struct ixl_softc *, 889 const struct ixl_aq_desc *); 890 static int ixl_vlan_cb(struct ethercom *, uint16_t, bool); 891 static int ixl_setup_vlan_hwfilter(struct ixl_softc *); 892 static void ixl_teardown_vlan_hwfilter(struct ixl_softc *); 893 static int ixl_update_macvlan(struct ixl_softc *); 894 static int ixl_setup_interrupts(struct ixl_softc *);; 895 static void ixl_teardown_interrupts(struct ixl_softc *); 896 static int ixl_setup_stats(struct ixl_softc *); 897 static void ixl_teardown_stats(struct ixl_softc *); 898 static void ixl_stats_callout(void *); 899 static void ixl_stats_update(void *); 900 static int ixl_setup_sysctls(struct ixl_softc *); 901 static void ixl_teardown_sysctls(struct ixl_softc *); 902 static int ixl_queue_pairs_alloc(struct ixl_softc *); 903 static void ixl_queue_pairs_free(struct ixl_softc *); 904 905 static const struct ixl_phy_type ixl_phy_type_map[] = { 906 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 907 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 908 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 909 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 910 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 911 { 1ULL << IXL_PHY_TYPE_XAUI | 912 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 913 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 914 { 1ULL << IXL_PHY_TYPE_XLAUI | 915 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 916 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 917 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 918 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 919 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 920 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 921 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 922 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 923 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 924 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 925 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 926 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 927 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 928 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_TWINAX }, 929 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 930 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 931 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 932 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 933 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 934 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 935 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 936 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 937 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 938 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 939 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_ACC }, 940 }; 941 942 static const struct ixl_speed_type ixl_speed_type_map[] = { 943 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 944 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 945 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 946 { IXL_AQ_LINK_SPEED_1000MB, IF_Mbps(1000) }, 947 { IXL_AQ_LINK_SPEED_100MB, IF_Mbps(100)}, 948 }; 949 950 static const struct ixl_aq_regs ixl_pf_aq_regs = { 951 .atq_tail = I40E_PF_ATQT, 952 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 953 .atq_head = I40E_PF_ATQH, 954 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 955 .atq_len = I40E_PF_ATQLEN, 956 .atq_bal = I40E_PF_ATQBAL, 957 .atq_bah = I40E_PF_ATQBAH, 958 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 959 960 .arq_tail = I40E_PF_ARQT, 961 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 962 .arq_head = I40E_PF_ARQH, 963 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 964 .arq_len = I40E_PF_ARQLEN, 965 .arq_bal = I40E_PF_ARQBAL, 966 .arq_bah = I40E_PF_ARQBAH, 967 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 968 }; 969 970 #define ixl_rd(_s, _r) \ 971 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 972 #define ixl_wr(_s, _r, _v) \ 973 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 974 #define ixl_barrier(_s, _r, _l, _o) \ 975 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 976 #define ixl_flush(_s) (void)ixl_rd((_s), I40E_GLGEN_STAT) 977 #define ixl_nqueues(_sc) (1 << ((_sc)->sc_nqueue_pairs - 1)) 978 979 static inline uint32_t 980 ixl_dmamem_hi(struct ixl_dmamem *ixm) 981 { 982 uint32_t retval; 983 uint64_t val; 984 985 if (sizeof(IXL_DMA_DVA(ixm)) > 4) { 986 val = (intptr_t)IXL_DMA_DVA(ixm); 987 retval = (uint32_t)(val >> 32); 988 } else { 989 retval = 0; 990 } 991 992 return retval; 993 } 994 995 static inline uint32_t 996 ixl_dmamem_lo(struct ixl_dmamem *ixm) 997 { 998 999 return (uint32_t)IXL_DMA_DVA(ixm); 1000 } 1001 1002 static inline void 1003 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 1004 { 1005 uint64_t val; 1006 1007 if (sizeof(addr) > 4) { 1008 val = (intptr_t)addr; 1009 iaq->iaq_param[2] = htole32(val >> 32); 1010 } else { 1011 iaq->iaq_param[2] = htole32(0); 1012 } 1013 1014 iaq->iaq_param[3] = htole32(addr); 1015 } 1016 1017 static inline unsigned int 1018 ixl_rxr_unrefreshed(unsigned int prod, unsigned int cons, unsigned int ndescs) 1019 { 1020 unsigned int num; 1021 1022 if (prod < cons) 1023 num = cons - prod; 1024 else 1025 num = (ndescs - prod) + cons; 1026 1027 if (__predict_true(num > 0)) { 1028 /* device cannot receive packets if all descripter is filled */ 1029 num -= 1; 1030 } 1031 1032 return num; 1033 } 1034 1035 CFATTACH_DECL3_NEW(ixl, sizeof(struct ixl_softc), 1036 ixl_match, ixl_attach, ixl_detach, NULL, NULL, NULL, 1037 DVF_DETACH_SHUTDOWN); 1038 1039 static const struct ixl_product ixl_products[] = { 1040 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_SFP }, 1041 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_KX_B }, 1042 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_KX_C }, 1043 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_A }, 1044 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_B }, 1045 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_C }, 1046 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T }, 1047 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 1048 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 1049 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 1050 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 1051 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28 }, 1052 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_KX }, 1053 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_QSFP }, 1054 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_SFP }, 1055 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G_BASET }, 1056 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_BASET }, 1057 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_I_SFP }, 1058 /* required last entry */ 1059 {0, 0} 1060 }; 1061 1062 static const struct ixl_product * 1063 ixl_lookup(const struct pci_attach_args *pa) 1064 { 1065 const struct ixl_product *ixlp; 1066 1067 for (ixlp = ixl_products; ixlp->vendor_id != 0; ixlp++) { 1068 if (PCI_VENDOR(pa->pa_id) == ixlp->vendor_id && 1069 PCI_PRODUCT(pa->pa_id) == ixlp->product_id) 1070 return ixlp; 1071 } 1072 1073 return NULL; 1074 } 1075 1076 static int 1077 ixl_match(device_t parent, cfdata_t match, void *aux) 1078 { 1079 const struct pci_attach_args *pa = aux; 1080 1081 return (ixl_lookup(pa) != NULL) ? 1 : 0; 1082 } 1083 1084 static void 1085 ixl_attach(device_t parent, device_t self, void *aux) 1086 { 1087 struct ixl_softc *sc; 1088 struct pci_attach_args *pa = aux; 1089 struct ifnet *ifp; 1090 pcireg_t memtype; 1091 uint32_t firstq, port, ari, func; 1092 char xnamebuf[32]; 1093 int tries, rv, link; 1094 1095 sc = device_private(self); 1096 sc->sc_dev = self; 1097 ifp = &sc->sc_ec.ec_if; 1098 1099 sc->sc_pa = *pa; 1100 sc->sc_dmat = (pci_dma64_available(pa)) ? 1101 pa->pa_dmat64 : pa->pa_dmat; 1102 sc->sc_aq_regs = &ixl_pf_aq_regs; 1103 1104 sc->sc_mac_type = ixl_mactype(PCI_PRODUCT(pa->pa_id)); 1105 1106 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IXL_PCIREG); 1107 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1108 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 1109 aprint_error(": unable to map registers\n"); 1110 return; 1111 } 1112 1113 mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET); 1114 1115 firstq = ixl_rd(sc, I40E_PFLAN_QALLOC); 1116 firstq &= I40E_PFLAN_QALLOC_FIRSTQ_MASK; 1117 firstq >>= I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1118 sc->sc_base_queue = firstq; 1119 1120 ixl_clear_hw(sc); 1121 if (ixl_pf_reset(sc) == -1) { 1122 /* error printed by ixl pf_reset */ 1123 goto unmap; 1124 } 1125 1126 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1127 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1128 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1129 sc->sc_port = port; 1130 aprint_normal(": port %u", sc->sc_port); 1131 1132 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1133 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1134 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1135 1136 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1137 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1138 1139 /* initialise the adminq */ 1140 1141 mutex_init(&sc->sc_atq_lock, MUTEX_DEFAULT, IPL_NET); 1142 1143 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1144 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1145 aprint_error("\n" "%s: unable to allocate atq\n", 1146 device_xname(self)); 1147 goto unmap; 1148 } 1149 1150 SIMPLEQ_INIT(&sc->sc_arq_idle); 1151 ixl_work_set(&sc->sc_arq_task, ixl_arq, sc); 1152 sc->sc_arq_cons = 0; 1153 sc->sc_arq_prod = 0; 1154 1155 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1156 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1157 aprint_error("\n" "%s: unable to allocate arq\n", 1158 device_xname(self)); 1159 goto free_atq; 1160 } 1161 1162 if (!ixl_arq_fill(sc)) { 1163 aprint_error("\n" "%s: unable to fill arq descriptors\n", 1164 device_xname(self)); 1165 goto free_arq; 1166 } 1167 1168 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1169 0, IXL_DMA_LEN(&sc->sc_atq), 1170 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1171 1172 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1173 0, IXL_DMA_LEN(&sc->sc_arq), 1174 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1175 1176 for (tries = 0; tries < 10; tries++) { 1177 sc->sc_atq_cons = 0; 1178 sc->sc_atq_prod = 0; 1179 1180 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1181 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1182 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1183 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1184 1185 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1186 1187 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1188 ixl_dmamem_lo(&sc->sc_atq)); 1189 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1190 ixl_dmamem_hi(&sc->sc_atq)); 1191 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1192 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1193 1194 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1195 ixl_dmamem_lo(&sc->sc_arq)); 1196 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1197 ixl_dmamem_hi(&sc->sc_arq)); 1198 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1199 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1200 1201 rv = ixl_get_version(sc); 1202 if (rv == 0) 1203 break; 1204 if (rv != ETIMEDOUT) { 1205 aprint_error(", unable to get firmware version\n"); 1206 goto shutdown; 1207 } 1208 1209 delaymsec(100); 1210 } 1211 1212 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1213 1214 if (ixl_dmamem_alloc(sc, &sc->sc_aqbuf, IXL_AQ_BUFLEN, 0) != 0) { 1215 aprint_error_dev(self, ", unable to allocate nvm buffer\n"); 1216 goto shutdown; 1217 } 1218 1219 ixl_get_nvm_version(sc); 1220 1221 if (sc->sc_mac_type == I40E_MAC_X722) 1222 sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_X722; 1223 else 1224 sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_XL710; 1225 1226 rv = ixl_get_hw_capabilities(sc); 1227 if (rv != 0) { 1228 aprint_error(", GET HW CAPABILITIES %s\n", 1229 rv == ETIMEDOUT ? "timeout" : "error"); 1230 goto free_aqbuf; 1231 } 1232 1233 sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_device, ncpu); 1234 if (ixl_param_nqps_limit > 0) { 1235 sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_max, 1236 ixl_param_nqps_limit); 1237 } 1238 1239 sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max; 1240 sc->sc_tx_ring_ndescs = ixl_param_tx_ndescs; 1241 sc->sc_rx_ring_ndescs = ixl_param_rx_ndescs; 1242 1243 KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_rx_ring_ndescs); 1244 KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_tx_ring_ndescs); 1245 1246 if (ixl_get_mac(sc) != 0) { 1247 /* error printed by ixl_get_mac */ 1248 goto free_aqbuf; 1249 } 1250 1251 aprint_normal("\n"); 1252 aprint_naive("\n"); 1253 1254 aprint_normal_dev(self, "Ethernet address %s\n", 1255 ether_sprintf(sc->sc_enaddr)); 1256 1257 rv = ixl_pxe_clear(sc); 1258 if (rv != 0) { 1259 aprint_debug_dev(self, "CLEAR PXE MODE %s\n", 1260 rv == ETIMEDOUT ? "timeout" : "error"); 1261 } 1262 1263 ixl_set_filter_control(sc); 1264 1265 if (ixl_hmc(sc) != 0) { 1266 /* error printed by ixl_hmc */ 1267 goto free_aqbuf; 1268 } 1269 1270 if (ixl_lldp_shut(sc) != 0) { 1271 /* error printed by ixl_lldp_shut */ 1272 goto free_hmc; 1273 } 1274 1275 if (ixl_phy_mask_ints(sc) != 0) { 1276 /* error printed by ixl_phy_mask_ints */ 1277 goto free_hmc; 1278 } 1279 1280 if (ixl_restart_an(sc) != 0) { 1281 /* error printed by ixl_restart_an */ 1282 goto free_hmc; 1283 } 1284 1285 if (ixl_get_switch_config(sc) != 0) { 1286 /* error printed by ixl_get_switch_config */ 1287 goto free_hmc; 1288 } 1289 1290 rv = ixl_get_link_status_poll(sc, NULL); 1291 if (rv != 0) { 1292 aprint_error_dev(self, "GET LINK STATUS %s\n", 1293 rv == ETIMEDOUT ? "timeout" : "error"); 1294 goto free_hmc; 1295 } 1296 1297 /* 1298 * The FW often returns EIO in "Get PHY Abilities" command 1299 * if there is no delay 1300 */ 1301 DELAY(500); 1302 if (ixl_get_phy_info(sc) != 0) { 1303 /* error printed by ixl_get_phy_info */ 1304 goto free_hmc; 1305 } 1306 1307 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1308 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1309 aprint_error_dev(self, "unable to allocate scratch buffer\n"); 1310 goto free_hmc; 1311 } 1312 1313 rv = ixl_get_vsi(sc); 1314 if (rv != 0) { 1315 aprint_error_dev(self, "GET VSI %s %d\n", 1316 rv == ETIMEDOUT ? "timeout" : "error", rv); 1317 goto free_scratch; 1318 } 1319 1320 rv = ixl_set_vsi(sc); 1321 if (rv != 0) { 1322 aprint_error_dev(self, "UPDATE VSI error %s %d\n", 1323 rv == ETIMEDOUT ? "timeout" : "error", rv); 1324 goto free_scratch; 1325 } 1326 1327 if (ixl_queue_pairs_alloc(sc) != 0) { 1328 /* error printed by ixl_queue_pairs_alloc */ 1329 goto free_scratch; 1330 } 1331 1332 if (ixl_setup_interrupts(sc) != 0) { 1333 /* error printed by ixl_setup_interrupts */ 1334 goto free_queue_pairs; 1335 } 1336 1337 if (ixl_setup_stats(sc) != 0) { 1338 aprint_error_dev(self, "failed to setup event counters\n"); 1339 goto teardown_intrs; 1340 } 1341 1342 if (ixl_setup_sysctls(sc) != 0) { 1343 /* error printed by ixl_setup_sysctls */ 1344 goto teardown_stats; 1345 } 1346 1347 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self)); 1348 sc->sc_workq = ixl_workq_create(xnamebuf, IXL_WORKQUEUE_PRI, 1349 IPL_NET, WQ_MPSAFE); 1350 if (sc->sc_workq == NULL) 1351 goto teardown_sysctls; 1352 1353 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self)); 1354 rv = workqueue_create(&sc->sc_workq_txrx, xnamebuf, ixl_handle_queue_wk, 1355 sc, IXL_WORKQUEUE_PRI, IPL_NET, WQ_PERCPU | WQ_MPSAFE); 1356 if (rv != 0) { 1357 sc->sc_workq_txrx = NULL; 1358 goto teardown_wqs; 1359 } 1360 1361 snprintf(xnamebuf, sizeof(xnamebuf), "%s_atq_cv", device_xname(self)); 1362 cv_init(&sc->sc_atq_cv, xnamebuf); 1363 1364 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1365 1366 ifp->if_softc = sc; 1367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1368 ifp->if_extflags = IFEF_MPSAFE; 1369 ifp->if_ioctl = ixl_ioctl; 1370 ifp->if_start = ixl_start; 1371 ifp->if_transmit = ixl_transmit; 1372 ifp->if_watchdog = ixl_watchdog; 1373 ifp->if_init = ixl_init; 1374 ifp->if_stop = ixl_stop; 1375 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1376 IFQ_SET_READY(&ifp->if_snd); 1377 ifp->if_capabilities |= IXL_IFCAP_RXCSUM; 1378 ifp->if_capabilities |= IXL_IFCAP_TXCSUM; 1379 #if 0 1380 ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6; 1381 #endif 1382 ether_set_vlan_cb(&sc->sc_ec, ixl_vlan_cb); 1383 sc->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1384 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1385 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER; 1386 1387 sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities; 1388 /* Disable VLAN_HWFILTER by default */ 1389 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1390 1391 sc->sc_cur_ec_capenable = sc->sc_ec.ec_capenable; 1392 1393 sc->sc_ec.ec_ifmedia = &sc->sc_media; 1394 ifmedia_init(&sc->sc_media, IFM_IMASK, ixl_media_change, 1395 ixl_media_status); 1396 1397 ixl_media_add(sc); 1398 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1399 if (ISSET(sc->sc_phy_abilities, 1400 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) { 1401 ifmedia_add(&sc->sc_media, 1402 IFM_ETHER | IFM_AUTO | IFM_FLOW, 0, NULL); 1403 } 1404 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_NONE, 0, NULL); 1405 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1406 1407 if_attach(ifp); 1408 if_deferred_start_init(ifp, NULL); 1409 ether_ifattach(ifp, sc->sc_enaddr); 1410 ether_set_ifflags_cb(&sc->sc_ec, ixl_ifflags_cb); 1411 1412 rv = ixl_get_link_status_poll(sc, &link); 1413 if (rv != 0) 1414 link = LINK_STATE_UNKNOWN; 1415 if_link_state_change(ifp, link); 1416 1417 ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done); 1418 ixl_work_set(&sc->sc_link_state_task, ixl_get_link_status, sc); 1419 1420 ixl_config_other_intr(sc); 1421 ixl_enable_other_intr(sc); 1422 1423 ixl_set_phy_autoselect(sc); 1424 1425 /* remove default mac filter and replace it so we can see vlans */ 1426 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 0); 1427 if (rv != ENOENT) { 1428 aprint_debug_dev(self, 1429 "unable to remove macvlan %u\n", rv); 1430 } 1431 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 1432 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1433 if (rv != ENOENT) { 1434 aprint_debug_dev(self, 1435 "unable to remove macvlan, ignore vlan %u\n", rv); 1436 } 1437 1438 if (ixl_update_macvlan(sc) != 0) { 1439 aprint_debug_dev(self, 1440 "couldn't enable vlan hardware filter\n"); 1441 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1442 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 1443 } 1444 1445 sc->sc_txrx_workqueue = true; 1446 sc->sc_tx_process_limit = IXL_TX_PROCESS_LIMIT; 1447 sc->sc_rx_process_limit = IXL_RX_PROCESS_LIMIT; 1448 sc->sc_tx_intr_process_limit = IXL_TX_INTR_PROCESS_LIMIT; 1449 sc->sc_rx_intr_process_limit = IXL_RX_INTR_PROCESS_LIMIT; 1450 1451 ixl_stats_update(sc); 1452 sc->sc_stats_counters.isc_has_offset = true; 1453 1454 if (pmf_device_register(self, NULL, NULL) != true) 1455 aprint_debug_dev(self, "couldn't establish power handler\n"); 1456 sc->sc_attached = true; 1457 return; 1458 1459 teardown_wqs: 1460 config_finalize_register(self, ixl_workqs_teardown); 1461 teardown_sysctls: 1462 ixl_teardown_sysctls(sc); 1463 teardown_stats: 1464 ixl_teardown_stats(sc); 1465 teardown_intrs: 1466 ixl_teardown_interrupts(sc); 1467 free_queue_pairs: 1468 ixl_queue_pairs_free(sc); 1469 free_scratch: 1470 ixl_dmamem_free(sc, &sc->sc_scratch); 1471 free_hmc: 1472 ixl_hmc_free(sc); 1473 free_aqbuf: 1474 ixl_dmamem_free(sc, &sc->sc_aqbuf); 1475 shutdown: 1476 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1477 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1478 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1479 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1480 1481 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1482 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1483 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1484 1485 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1486 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1487 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1488 1489 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1490 0, IXL_DMA_LEN(&sc->sc_arq), 1491 BUS_DMASYNC_POSTREAD); 1492 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1493 0, IXL_DMA_LEN(&sc->sc_atq), 1494 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1495 1496 ixl_arq_unfill(sc); 1497 free_arq: 1498 ixl_dmamem_free(sc, &sc->sc_arq); 1499 free_atq: 1500 ixl_dmamem_free(sc, &sc->sc_atq); 1501 unmap: 1502 mutex_destroy(&sc->sc_atq_lock); 1503 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1504 mutex_destroy(&sc->sc_cfg_lock); 1505 sc->sc_mems = 0; 1506 1507 sc->sc_attached = false; 1508 } 1509 1510 static int 1511 ixl_detach(device_t self, int flags) 1512 { 1513 struct ixl_softc *sc = device_private(self); 1514 struct ifnet *ifp = &sc->sc_ec.ec_if; 1515 1516 if (!sc->sc_attached) 1517 return 0; 1518 1519 ixl_stop(ifp, 1); 1520 1521 ixl_disable_other_intr(sc); 1522 1523 callout_halt(&sc->sc_stats_callout, NULL); 1524 ixl_work_wait(sc->sc_workq, &sc->sc_stats_task); 1525 1526 /* wait for ATQ handler */ 1527 mutex_enter(&sc->sc_atq_lock); 1528 mutex_exit(&sc->sc_atq_lock); 1529 1530 ixl_work_wait(sc->sc_workq, &sc->sc_arq_task); 1531 ixl_work_wait(sc->sc_workq, &sc->sc_link_state_task); 1532 1533 if (sc->sc_workq != NULL) { 1534 ixl_workq_destroy(sc->sc_workq); 1535 sc->sc_workq = NULL; 1536 } 1537 1538 if (sc->sc_workq_txrx != NULL) { 1539 workqueue_destroy(sc->sc_workq_txrx); 1540 sc->sc_workq_txrx = NULL; 1541 } 1542 1543 ether_ifdetach(ifp); 1544 if_detach(ifp); 1545 ifmedia_fini(&sc->sc_media); 1546 1547 ixl_teardown_interrupts(sc); 1548 ixl_teardown_stats(sc); 1549 ixl_teardown_sysctls(sc); 1550 1551 ixl_queue_pairs_free(sc); 1552 1553 ixl_dmamem_free(sc, &sc->sc_scratch); 1554 ixl_hmc_free(sc); 1555 1556 /* shutdown */ 1557 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1558 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1559 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1560 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1561 1562 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1563 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1564 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1565 1566 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1567 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1568 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1569 1570 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1571 0, IXL_DMA_LEN(&sc->sc_arq), 1572 BUS_DMASYNC_POSTREAD); 1573 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1574 0, IXL_DMA_LEN(&sc->sc_atq), 1575 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1576 1577 ixl_arq_unfill(sc); 1578 1579 ixl_dmamem_free(sc, &sc->sc_arq); 1580 ixl_dmamem_free(sc, &sc->sc_atq); 1581 ixl_dmamem_free(sc, &sc->sc_aqbuf); 1582 1583 cv_destroy(&sc->sc_atq_cv); 1584 mutex_destroy(&sc->sc_atq_lock); 1585 1586 if (sc->sc_mems != 0) { 1587 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1588 sc->sc_mems = 0; 1589 } 1590 1591 mutex_destroy(&sc->sc_cfg_lock); 1592 1593 return 0; 1594 } 1595 1596 static int 1597 ixl_workqs_teardown(device_t self) 1598 { 1599 struct ixl_softc *sc = device_private(self); 1600 1601 if (sc->sc_workq != NULL) { 1602 ixl_workq_destroy(sc->sc_workq); 1603 sc->sc_workq = NULL; 1604 } 1605 1606 if (sc->sc_workq_txrx != NULL) { 1607 workqueue_destroy(sc->sc_workq_txrx); 1608 sc->sc_workq_txrx = NULL; 1609 } 1610 1611 return 0; 1612 } 1613 1614 static int 1615 ixl_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 1616 { 1617 struct ifnet *ifp = &ec->ec_if; 1618 struct ixl_softc *sc = ifp->if_softc; 1619 int rv; 1620 1621 if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 1622 return 0; 1623 } 1624 1625 if (set) { 1626 rv = ixl_add_macvlan(sc, sc->sc_enaddr, vid, 1627 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 1628 if (rv == 0) { 1629 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 1630 vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 1631 } 1632 } else { 1633 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, vid, 1634 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 1635 (void)ixl_remove_macvlan(sc, etherbroadcastaddr, vid, 1636 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 1637 } 1638 1639 return rv; 1640 } 1641 1642 static void 1643 ixl_media_add(struct ixl_softc *sc) 1644 { 1645 struct ifmedia *ifm = &sc->sc_media; 1646 const struct ixl_phy_type *itype; 1647 unsigned int i; 1648 bool flow; 1649 1650 if (ISSET(sc->sc_phy_abilities, 1651 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) { 1652 flow = true; 1653 } else { 1654 flow = false; 1655 } 1656 1657 for (i = 0; i < __arraycount(ixl_phy_type_map); i++) { 1658 itype = &ixl_phy_type_map[i]; 1659 1660 if (ISSET(sc->sc_phy_types, itype->phy_type)) { 1661 ifmedia_add(ifm, 1662 IFM_ETHER | IFM_FDX | itype->ifm_type, 0, NULL); 1663 1664 if (flow) { 1665 ifmedia_add(ifm, 1666 IFM_ETHER | IFM_FDX | IFM_FLOW | 1667 itype->ifm_type, 0, NULL); 1668 } 1669 1670 if (itype->ifm_type != IFM_100_TX) 1671 continue; 1672 1673 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 1674 0, NULL); 1675 if (flow) { 1676 ifmedia_add(ifm, 1677 IFM_ETHER | IFM_FLOW | itype->ifm_type, 1678 0, NULL); 1679 } 1680 } 1681 } 1682 } 1683 1684 static void 1685 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1686 { 1687 struct ixl_softc *sc = ifp->if_softc; 1688 1689 ifmr->ifm_status = sc->sc_media_status; 1690 ifmr->ifm_active = sc->sc_media_active; 1691 1692 mutex_enter(&sc->sc_cfg_lock); 1693 if (ifp->if_link_state == LINK_STATE_UP) 1694 SET(ifmr->ifm_status, IFM_ACTIVE); 1695 mutex_exit(&sc->sc_cfg_lock); 1696 } 1697 1698 static int 1699 ixl_media_change(struct ifnet *ifp) 1700 { 1701 struct ixl_softc *sc = ifp->if_softc; 1702 struct ifmedia *ifm = &sc->sc_media; 1703 uint64_t ifm_active = sc->sc_media_active; 1704 uint8_t link_speed, abilities; 1705 1706 switch (IFM_SUBTYPE(ifm_active)) { 1707 case IFM_1000_SGMII: 1708 case IFM_1000_KX: 1709 case IFM_10G_KX4: 1710 case IFM_10G_KR: 1711 case IFM_40G_KR4: 1712 case IFM_20G_KR2: 1713 case IFM_25G_KR: 1714 /* backplanes */ 1715 return EINVAL; 1716 } 1717 1718 abilities = IXL_PHY_ABILITY_AUTONEGO | IXL_PHY_ABILITY_LINKUP; 1719 1720 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1721 case IFM_AUTO: 1722 link_speed = sc->sc_phy_linkspeed; 1723 break; 1724 case IFM_NONE: 1725 link_speed = 0; 1726 CLR(abilities, IXL_PHY_ABILITY_LINKUP); 1727 break; 1728 default: 1729 link_speed = ixl_search_baudrate( 1730 ifmedia_baudrate(ifm->ifm_media)); 1731 } 1732 1733 if (ISSET(abilities, IXL_PHY_ABILITY_LINKUP)) { 1734 if (ISSET(link_speed, sc->sc_phy_linkspeed) == 0) 1735 return EINVAL; 1736 } 1737 1738 if (ifm->ifm_media & IFM_FLOW) { 1739 abilities |= sc->sc_phy_abilities & 1740 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX); 1741 } 1742 1743 return ixl_set_phy_config(sc, link_speed, abilities, false); 1744 } 1745 1746 static void 1747 ixl_watchdog(struct ifnet *ifp) 1748 { 1749 1750 } 1751 1752 static void 1753 ixl_del_all_multiaddr(struct ixl_softc *sc) 1754 { 1755 struct ethercom *ec = &sc->sc_ec; 1756 struct ether_multi *enm; 1757 struct ether_multistep step; 1758 1759 ETHER_LOCK(ec); 1760 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1761 ETHER_NEXT_MULTI(step, enm)) { 1762 ixl_remove_macvlan(sc, enm->enm_addrlo, 0, 1763 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1764 } 1765 ETHER_UNLOCK(ec); 1766 } 1767 1768 static int 1769 ixl_add_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1770 { 1771 struct ifnet *ifp = &sc->sc_ec.ec_if; 1772 int rv; 1773 1774 if (ISSET(ifp->if_flags, IFF_ALLMULTI)) 1775 return 0; 1776 1777 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) { 1778 ixl_del_all_multiaddr(sc); 1779 SET(ifp->if_flags, IFF_ALLMULTI); 1780 return ENETRESET; 1781 } 1782 1783 /* multicast address can not use VLAN HWFILTER */ 1784 rv = ixl_add_macvlan(sc, addrlo, 0, 1785 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1786 1787 if (rv == ENOSPC) { 1788 ixl_del_all_multiaddr(sc); 1789 SET(ifp->if_flags, IFF_ALLMULTI); 1790 return ENETRESET; 1791 } 1792 1793 return rv; 1794 } 1795 1796 static int 1797 ixl_del_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1798 { 1799 struct ifnet *ifp = &sc->sc_ec.ec_if; 1800 struct ethercom *ec = &sc->sc_ec; 1801 struct ether_multi *enm, *enm_last; 1802 struct ether_multistep step; 1803 int error, rv = 0; 1804 1805 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1806 ixl_remove_macvlan(sc, addrlo, 0, 1807 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1808 return 0; 1809 } 1810 1811 ETHER_LOCK(ec); 1812 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1813 ETHER_NEXT_MULTI(step, enm)) { 1814 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1815 ETHER_ADDR_LEN) != 0) { 1816 goto out; 1817 } 1818 } 1819 1820 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1821 ETHER_NEXT_MULTI(step, enm)) { 1822 error = ixl_add_macvlan(sc, enm->enm_addrlo, 0, 1823 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1824 if (error != 0) 1825 break; 1826 } 1827 1828 if (enm != NULL) { 1829 enm_last = enm; 1830 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1831 ETHER_NEXT_MULTI(step, enm)) { 1832 if (enm == enm_last) 1833 break; 1834 1835 ixl_remove_macvlan(sc, enm->enm_addrlo, 0, 1836 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1837 } 1838 } else { 1839 CLR(ifp->if_flags, IFF_ALLMULTI); 1840 rv = ENETRESET; 1841 } 1842 1843 out: 1844 ETHER_UNLOCK(ec); 1845 return rv; 1846 } 1847 1848 static int 1849 ixl_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1850 { 1851 struct ifreq *ifr = (struct ifreq *)data; 1852 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 1853 const struct sockaddr *sa; 1854 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 1855 int s, error = 0; 1856 unsigned int nmtu; 1857 1858 switch (cmd) { 1859 case SIOCSIFMTU: 1860 nmtu = ifr->ifr_mtu; 1861 1862 if (nmtu < IXL_MIN_MTU || nmtu > IXL_MAX_MTU) { 1863 error = EINVAL; 1864 break; 1865 } 1866 if (ifp->if_mtu != nmtu) { 1867 s = splnet(); 1868 error = ether_ioctl(ifp, cmd, data); 1869 splx(s); 1870 if (error == ENETRESET) 1871 error = ixl_init(ifp); 1872 } 1873 break; 1874 case SIOCADDMULTI: 1875 sa = ifreq_getaddr(SIOCADDMULTI, ifr); 1876 if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) { 1877 error = ether_multiaddr(sa, addrlo, addrhi); 1878 if (error != 0) 1879 return error; 1880 1881 error = ixl_add_multi(sc, addrlo, addrhi); 1882 if (error != 0 && error != ENETRESET) { 1883 ether_delmulti(sa, &sc->sc_ec); 1884 error = EIO; 1885 } 1886 } 1887 break; 1888 1889 case SIOCDELMULTI: 1890 sa = ifreq_getaddr(SIOCDELMULTI, ifr); 1891 if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) { 1892 error = ether_multiaddr(sa, addrlo, addrhi); 1893 if (error != 0) 1894 return error; 1895 1896 error = ixl_del_multi(sc, addrlo, addrhi); 1897 } 1898 break; 1899 1900 default: 1901 s = splnet(); 1902 error = ether_ioctl(ifp, cmd, data); 1903 splx(s); 1904 } 1905 1906 if (error == ENETRESET) 1907 error = ixl_iff(sc); 1908 1909 return error; 1910 } 1911 1912 static enum i40e_mac_type 1913 ixl_mactype(pci_product_id_t id) 1914 { 1915 1916 switch (id) { 1917 case PCI_PRODUCT_INTEL_XL710_SFP: 1918 case PCI_PRODUCT_INTEL_XL710_KX_B: 1919 case PCI_PRODUCT_INTEL_XL710_KX_C: 1920 case PCI_PRODUCT_INTEL_XL710_QSFP_A: 1921 case PCI_PRODUCT_INTEL_XL710_QSFP_B: 1922 case PCI_PRODUCT_INTEL_XL710_QSFP_C: 1923 case PCI_PRODUCT_INTEL_X710_10G_T: 1924 case PCI_PRODUCT_INTEL_XL710_20G_BP_1: 1925 case PCI_PRODUCT_INTEL_XL710_20G_BP_2: 1926 case PCI_PRODUCT_INTEL_X710_T4_10G: 1927 case PCI_PRODUCT_INTEL_XXV710_25G_BP: 1928 case PCI_PRODUCT_INTEL_XXV710_25G_SFP28: 1929 return I40E_MAC_XL710; 1930 1931 case PCI_PRODUCT_INTEL_X722_KX: 1932 case PCI_PRODUCT_INTEL_X722_QSFP: 1933 case PCI_PRODUCT_INTEL_X722_SFP: 1934 case PCI_PRODUCT_INTEL_X722_1G_BASET: 1935 case PCI_PRODUCT_INTEL_X722_10G_BASET: 1936 case PCI_PRODUCT_INTEL_X722_I_SFP: 1937 return I40E_MAC_X722; 1938 } 1939 1940 return I40E_MAC_GENERIC; 1941 } 1942 1943 static inline void * 1944 ixl_hmc_kva(struct ixl_softc *sc, enum ixl_hmc_types type, unsigned int i) 1945 { 1946 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 1947 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 1948 1949 if (i >= e->hmc_count) 1950 return NULL; 1951 1952 kva += e->hmc_base; 1953 kva += i * e->hmc_size; 1954 1955 return kva; 1956 } 1957 1958 static inline size_t 1959 ixl_hmc_len(struct ixl_softc *sc, enum ixl_hmc_types type) 1960 { 1961 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 1962 1963 return e->hmc_size; 1964 } 1965 1966 static void 1967 ixl_enable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp) 1968 { 1969 struct ixl_rx_ring *rxr = qp->qp_rxr; 1970 1971 ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid), 1972 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1973 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1974 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1975 ixl_flush(sc); 1976 } 1977 1978 static void 1979 ixl_disable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp) 1980 { 1981 struct ixl_rx_ring *rxr = qp->qp_rxr; 1982 1983 ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid), 1984 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1985 ixl_flush(sc); 1986 } 1987 1988 static void 1989 ixl_enable_other_intr(struct ixl_softc *sc) 1990 { 1991 1992 ixl_wr(sc, I40E_PFINT_DYN_CTL0, 1993 I40E_PFINT_DYN_CTL0_INTENA_MASK | 1994 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 1995 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)); 1996 ixl_flush(sc); 1997 } 1998 1999 static void 2000 ixl_disable_other_intr(struct ixl_softc *sc) 2001 { 2002 2003 ixl_wr(sc, I40E_PFINT_DYN_CTL0, 2004 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)); 2005 ixl_flush(sc); 2006 } 2007 2008 static int 2009 ixl_reinit(struct ixl_softc *sc) 2010 { 2011 struct ixl_rx_ring *rxr; 2012 struct ixl_tx_ring *txr; 2013 unsigned int i; 2014 uint32_t reg; 2015 2016 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2017 2018 if (ixl_get_vsi(sc) != 0) 2019 return EIO; 2020 2021 if (ixl_set_vsi(sc) != 0) 2022 return EIO; 2023 2024 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2025 txr = sc->sc_qps[i].qp_txr; 2026 rxr = sc->sc_qps[i].qp_rxr; 2027 2028 ixl_txr_config(sc, txr); 2029 ixl_rxr_config(sc, rxr); 2030 } 2031 2032 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2033 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_PREWRITE); 2034 2035 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2036 txr = sc->sc_qps[i].qp_txr; 2037 rxr = sc->sc_qps[i].qp_rxr; 2038 2039 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 2040 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 2041 ixl_flush(sc); 2042 2043 ixl_wr(sc, txr->txr_tail, txr->txr_prod); 2044 ixl_wr(sc, rxr->rxr_tail, rxr->rxr_prod); 2045 2046 /* ixl_rxfill() needs lock held */ 2047 mutex_enter(&rxr->rxr_lock); 2048 ixl_rxfill(sc, rxr); 2049 mutex_exit(&rxr->rxr_lock); 2050 2051 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2052 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2053 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2054 if (ixl_rxr_enabled(sc, rxr) != 0) 2055 goto stop; 2056 2057 ixl_txr_qdis(sc, txr, 1); 2058 2059 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2060 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2061 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2062 2063 if (ixl_txr_enabled(sc, txr) != 0) 2064 goto stop; 2065 } 2066 2067 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2068 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE); 2069 2070 return 0; 2071 2072 stop: 2073 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2074 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE); 2075 2076 return ETIMEDOUT; 2077 } 2078 2079 static int 2080 ixl_init_locked(struct ixl_softc *sc) 2081 { 2082 struct ifnet *ifp = &sc->sc_ec.ec_if; 2083 unsigned int i; 2084 int error, eccap_change; 2085 2086 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2087 2088 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2089 ixl_stop_locked(sc); 2090 2091 if (sc->sc_dead) { 2092 return ENXIO; 2093 } 2094 2095 eccap_change = sc->sc_ec.ec_capenable ^ sc->sc_cur_ec_capenable; 2096 if (ISSET(eccap_change, ETHERCAP_VLAN_HWTAGGING)) 2097 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING; 2098 2099 if (ISSET(eccap_change, ETHERCAP_VLAN_HWFILTER)) { 2100 if (ixl_update_macvlan(sc) == 0) { 2101 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER; 2102 } else { 2103 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 2104 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 2105 } 2106 } 2107 2108 if (sc->sc_intrtype != PCI_INTR_TYPE_MSIX) 2109 sc->sc_nqueue_pairs = 1; 2110 else 2111 sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max; 2112 2113 error = ixl_reinit(sc); 2114 if (error) { 2115 ixl_stop_locked(sc); 2116 return error; 2117 } 2118 2119 SET(ifp->if_flags, IFF_RUNNING); 2120 CLR(ifp->if_flags, IFF_OACTIVE); 2121 2122 (void)ixl_get_link_status(sc); 2123 2124 ixl_config_rss(sc); 2125 ixl_config_queue_intr(sc); 2126 2127 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2128 ixl_enable_queue_intr(sc, &sc->sc_qps[i]); 2129 } 2130 2131 error = ixl_iff(sc); 2132 if (error) { 2133 ixl_stop_locked(sc); 2134 return error; 2135 } 2136 2137 callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval)); 2138 2139 return 0; 2140 } 2141 2142 static int 2143 ixl_init(struct ifnet *ifp) 2144 { 2145 struct ixl_softc *sc = ifp->if_softc; 2146 int error; 2147 2148 mutex_enter(&sc->sc_cfg_lock); 2149 error = ixl_init_locked(sc); 2150 mutex_exit(&sc->sc_cfg_lock); 2151 2152 return error; 2153 } 2154 2155 static int 2156 ixl_iff(struct ixl_softc *sc) 2157 { 2158 struct ifnet *ifp = &sc->sc_ec.ec_if; 2159 struct ixl_atq iatq; 2160 struct ixl_aq_desc *iaq; 2161 struct ixl_aq_vsi_promisc_param *param; 2162 uint16_t flag_add, flag_del; 2163 int error; 2164 2165 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2166 return 0; 2167 2168 memset(&iatq, 0, sizeof(iatq)); 2169 2170 iaq = &iatq.iatq_desc; 2171 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2172 2173 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2174 param->flags = htole16(0); 2175 2176 if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER) 2177 || ISSET(ifp->if_flags, IFF_PROMISC)) { 2178 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2179 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2180 } 2181 2182 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2183 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2184 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2185 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2186 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2187 } 2188 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2189 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2190 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2191 param->seid = sc->sc_seid; 2192 2193 error = ixl_atq_exec(sc, &iatq); 2194 if (error) 2195 return error; 2196 2197 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2198 return EIO; 2199 2200 if (memcmp(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN) != 0) { 2201 if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 2202 flag_add = IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH; 2203 flag_del = IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH; 2204 } else { 2205 flag_add = IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN; 2206 flag_del = IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN; 2207 } 2208 2209 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, flag_del); 2210 2211 memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 2212 ixl_add_macvlan(sc, sc->sc_enaddr, 0, flag_add); 2213 } 2214 return 0; 2215 } 2216 2217 static void 2218 ixl_stop_rendezvous(struct ixl_softc *sc) 2219 { 2220 struct ixl_tx_ring *txr; 2221 struct ixl_rx_ring *rxr; 2222 unsigned int i; 2223 2224 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2225 txr = sc->sc_qps[i].qp_txr; 2226 rxr = sc->sc_qps[i].qp_rxr; 2227 2228 mutex_enter(&txr->txr_lock); 2229 mutex_exit(&txr->txr_lock); 2230 2231 mutex_enter(&rxr->rxr_lock); 2232 mutex_exit(&rxr->rxr_lock); 2233 2234 sc->sc_qps[i].qp_workqueue = false; 2235 workqueue_wait(sc->sc_workq_txrx, 2236 &sc->sc_qps[i].qp_work); 2237 } 2238 } 2239 2240 static void 2241 ixl_stop_locked(struct ixl_softc *sc) 2242 { 2243 struct ifnet *ifp = &sc->sc_ec.ec_if; 2244 struct ixl_rx_ring *rxr; 2245 struct ixl_tx_ring *txr; 2246 unsigned int i; 2247 uint32_t reg; 2248 2249 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2250 2251 CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE); 2252 callout_stop(&sc->sc_stats_callout); 2253 2254 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2255 txr = sc->sc_qps[i].qp_txr; 2256 rxr = sc->sc_qps[i].qp_rxr; 2257 2258 ixl_disable_queue_intr(sc, &sc->sc_qps[i]); 2259 2260 mutex_enter(&txr->txr_lock); 2261 ixl_txr_qdis(sc, txr, 0); 2262 mutex_exit(&txr->txr_lock); 2263 } 2264 2265 /* XXX wait at least 400 usec for all tx queues in one go */ 2266 ixl_flush(sc); 2267 DELAY(500); 2268 2269 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2270 txr = sc->sc_qps[i].qp_txr; 2271 rxr = sc->sc_qps[i].qp_rxr; 2272 2273 mutex_enter(&txr->txr_lock); 2274 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2275 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2276 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2277 mutex_exit(&txr->txr_lock); 2278 2279 mutex_enter(&rxr->rxr_lock); 2280 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2281 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2282 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2283 mutex_exit(&rxr->rxr_lock); 2284 } 2285 2286 /* XXX short wait for all queue disables to settle */ 2287 ixl_flush(sc); 2288 DELAY(50); 2289 2290 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2291 txr = sc->sc_qps[i].qp_txr; 2292 rxr = sc->sc_qps[i].qp_rxr; 2293 2294 mutex_enter(&txr->txr_lock); 2295 if (ixl_txr_disabled(sc, txr) != 0) { 2296 mutex_exit(&txr->txr_lock); 2297 goto die; 2298 } 2299 mutex_exit(&txr->txr_lock); 2300 2301 mutex_enter(&rxr->rxr_lock); 2302 if (ixl_rxr_disabled(sc, rxr) != 0) { 2303 mutex_exit(&rxr->rxr_lock); 2304 goto die; 2305 } 2306 mutex_exit(&rxr->rxr_lock); 2307 } 2308 2309 ixl_stop_rendezvous(sc); 2310 2311 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2312 txr = sc->sc_qps[i].qp_txr; 2313 rxr = sc->sc_qps[i].qp_rxr; 2314 2315 mutex_enter(&txr->txr_lock); 2316 ixl_txr_unconfig(sc, txr); 2317 mutex_exit(&txr->txr_lock); 2318 2319 mutex_enter(&rxr->rxr_lock); 2320 ixl_rxr_unconfig(sc, rxr); 2321 mutex_exit(&rxr->rxr_lock); 2322 2323 ixl_txr_clean(sc, txr); 2324 ixl_rxr_clean(sc, rxr); 2325 } 2326 2327 return; 2328 die: 2329 sc->sc_dead = true; 2330 log(LOG_CRIT, "%s: failed to shut down rings", 2331 device_xname(sc->sc_dev)); 2332 return; 2333 } 2334 2335 static void 2336 ixl_stop(struct ifnet *ifp, int disable) 2337 { 2338 struct ixl_softc *sc = ifp->if_softc; 2339 2340 mutex_enter(&sc->sc_cfg_lock); 2341 ixl_stop_locked(sc); 2342 mutex_exit(&sc->sc_cfg_lock); 2343 } 2344 2345 static int 2346 ixl_queue_pairs_alloc(struct ixl_softc *sc) 2347 { 2348 struct ixl_queue_pair *qp; 2349 unsigned int i; 2350 size_t sz; 2351 2352 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2353 sc->sc_qps = kmem_zalloc(sz, KM_SLEEP); 2354 2355 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2356 qp = &sc->sc_qps[i]; 2357 2358 qp->qp_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 2359 ixl_handle_queue, qp); 2360 if (qp->qp_si == NULL) 2361 goto free; 2362 2363 qp->qp_txr = ixl_txr_alloc(sc, i); 2364 if (qp->qp_txr == NULL) 2365 goto free; 2366 2367 qp->qp_rxr = ixl_rxr_alloc(sc, i); 2368 if (qp->qp_rxr == NULL) 2369 goto free; 2370 2371 qp->qp_sc = sc; 2372 snprintf(qp->qp_name, sizeof(qp->qp_name), 2373 "%s-TXRX%d", device_xname(sc->sc_dev), i); 2374 } 2375 2376 return 0; 2377 free: 2378 if (sc->sc_qps != NULL) { 2379 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2380 qp = &sc->sc_qps[i]; 2381 2382 if (qp->qp_txr != NULL) 2383 ixl_txr_free(sc, qp->qp_txr); 2384 if (qp->qp_rxr != NULL) 2385 ixl_rxr_free(sc, qp->qp_rxr); 2386 if (qp->qp_si != NULL) 2387 softint_disestablish(qp->qp_si); 2388 } 2389 2390 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2391 kmem_free(sc->sc_qps, sz); 2392 sc->sc_qps = NULL; 2393 } 2394 2395 return -1; 2396 } 2397 2398 static void 2399 ixl_queue_pairs_free(struct ixl_softc *sc) 2400 { 2401 struct ixl_queue_pair *qp; 2402 unsigned int i; 2403 size_t sz; 2404 2405 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2406 qp = &sc->sc_qps[i]; 2407 ixl_txr_free(sc, qp->qp_txr); 2408 ixl_rxr_free(sc, qp->qp_rxr); 2409 softint_disestablish(qp->qp_si); 2410 } 2411 2412 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2413 kmem_free(sc->sc_qps, sz); 2414 sc->sc_qps = NULL; 2415 } 2416 2417 static struct ixl_tx_ring * 2418 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2419 { 2420 struct ixl_tx_ring *txr = NULL; 2421 struct ixl_tx_map *maps = NULL, *txm; 2422 unsigned int i; 2423 2424 txr = kmem_zalloc(sizeof(*txr), KM_SLEEP); 2425 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs, 2426 KM_SLEEP); 2427 2428 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2429 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2430 IXL_TX_QUEUE_ALIGN) != 0) 2431 goto free; 2432 2433 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2434 txm = &maps[i]; 2435 2436 if (bus_dmamap_create(sc->sc_dmat, IXL_TX_PKT_MAXSIZE, 2437 IXL_TX_PKT_DESCS, IXL_TX_PKT_MAXSIZE, 0, 2438 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &txm->txm_map) != 0) 2439 goto uncreate; 2440 2441 txm->txm_eop = -1; 2442 txm->txm_m = NULL; 2443 } 2444 2445 txr->txr_cons = txr->txr_prod = 0; 2446 txr->txr_maps = maps; 2447 2448 txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP); 2449 if (txr->txr_intrq == NULL) 2450 goto uncreate; 2451 2452 txr->txr_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 2453 ixl_deferred_transmit, txr); 2454 if (txr->txr_si == NULL) 2455 goto destroy_pcq; 2456 2457 txr->txr_tail = I40E_QTX_TAIL(qid); 2458 txr->txr_qid = qid; 2459 txr->txr_sc = sc; 2460 mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET); 2461 2462 return txr; 2463 2464 destroy_pcq: 2465 pcq_destroy(txr->txr_intrq); 2466 uncreate: 2467 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2468 txm = &maps[i]; 2469 2470 if (txm->txm_map == NULL) 2471 continue; 2472 2473 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2474 } 2475 2476 ixl_dmamem_free(sc, &txr->txr_mem); 2477 free: 2478 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2479 kmem_free(txr, sizeof(*txr)); 2480 2481 return NULL; 2482 } 2483 2484 static void 2485 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2486 { 2487 unsigned int qid; 2488 bus_size_t reg; 2489 uint32_t r; 2490 2491 qid = txr->txr_qid + sc->sc_base_queue; 2492 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2493 qid %= 128; 2494 2495 r = ixl_rd(sc, reg); 2496 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2497 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2498 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2499 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2500 ixl_wr(sc, reg, r); 2501 } 2502 2503 static void 2504 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2505 { 2506 struct ixl_hmc_txq txq; 2507 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2508 void *hmc; 2509 2510 memset(&txq, 0, sizeof(txq)); 2511 txq.head = htole16(txr->txr_cons); 2512 txq.new_context = 1; 2513 txq.base = htole64(IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2514 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2515 txq.qlen = htole16(sc->sc_tx_ring_ndescs); 2516 txq.tphrdesc_ena = 0; 2517 txq.tphrpacket_ena = 0; 2518 txq.tphwdesc_ena = 0; 2519 txq.rdylist = data->qs_handle[0]; 2520 2521 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2522 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2523 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, 2524 __arraycount(ixl_hmc_pack_txq)); 2525 } 2526 2527 static void 2528 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2529 { 2530 void *hmc; 2531 2532 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2533 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2534 txr->txr_cons = txr->txr_prod = 0; 2535 } 2536 2537 static void 2538 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2539 { 2540 struct ixl_tx_map *maps, *txm; 2541 bus_dmamap_t map; 2542 unsigned int i; 2543 2544 maps = txr->txr_maps; 2545 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2546 txm = &maps[i]; 2547 2548 if (txm->txm_m == NULL) 2549 continue; 2550 2551 map = txm->txm_map; 2552 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2553 BUS_DMASYNC_POSTWRITE); 2554 bus_dmamap_unload(sc->sc_dmat, map); 2555 2556 m_freem(txm->txm_m); 2557 txm->txm_m = NULL; 2558 } 2559 } 2560 2561 static int 2562 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2563 { 2564 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2565 uint32_t reg; 2566 int i; 2567 2568 for (i = 0; i < 10; i++) { 2569 reg = ixl_rd(sc, ena); 2570 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2571 return 0; 2572 2573 delaymsec(10); 2574 } 2575 2576 return ETIMEDOUT; 2577 } 2578 2579 static int 2580 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2581 { 2582 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2583 uint32_t reg; 2584 int i; 2585 2586 KASSERT(mutex_owned(&txr->txr_lock)); 2587 2588 for (i = 0; i < 10; i++) { 2589 reg = ixl_rd(sc, ena); 2590 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2591 return 0; 2592 2593 delaymsec(10); 2594 } 2595 2596 return ETIMEDOUT; 2597 } 2598 2599 static void 2600 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2601 { 2602 struct ixl_tx_map *maps, *txm; 2603 struct mbuf *m; 2604 unsigned int i; 2605 2606 softint_disestablish(txr->txr_si); 2607 while ((m = pcq_get(txr->txr_intrq)) != NULL) 2608 m_freem(m); 2609 pcq_destroy(txr->txr_intrq); 2610 2611 maps = txr->txr_maps; 2612 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2613 txm = &maps[i]; 2614 2615 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2616 } 2617 2618 ixl_dmamem_free(sc, &txr->txr_mem); 2619 mutex_destroy(&txr->txr_lock); 2620 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2621 kmem_free(txr, sizeof(*txr)); 2622 } 2623 2624 static inline int 2625 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0, 2626 struct ixl_tx_ring *txr) 2627 { 2628 struct mbuf *m; 2629 int error; 2630 2631 KASSERT(mutex_owned(&txr->txr_lock)); 2632 2633 m = *m0; 2634 2635 error = bus_dmamap_load_mbuf(dmat, map, m, 2636 BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2637 if (error != EFBIG) 2638 return error; 2639 2640 m = m_defrag(m, M_DONTWAIT); 2641 if (m != NULL) { 2642 *m0 = m; 2643 txr->txr_defragged.ev_count++; 2644 2645 error = bus_dmamap_load_mbuf(dmat, map, m, 2646 BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2647 } else { 2648 txr->txr_defrag_failed.ev_count++; 2649 error = ENOBUFS; 2650 } 2651 2652 return error; 2653 } 2654 2655 static inline int 2656 ixl_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd) 2657 { 2658 struct ether_header *eh; 2659 size_t len; 2660 uint64_t cmd; 2661 2662 cmd = 0; 2663 2664 eh = mtod(m, struct ether_header *); 2665 switch (htons(eh->ether_type)) { 2666 case ETHERTYPE_IP: 2667 case ETHERTYPE_IPV6: 2668 len = ETHER_HDR_LEN; 2669 break; 2670 case ETHERTYPE_VLAN: 2671 len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2672 break; 2673 default: 2674 len = 0; 2675 } 2676 cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT); 2677 2678 if (m->m_pkthdr.csum_flags & 2679 (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 2680 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4; 2681 } 2682 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2683 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM; 2684 } 2685 2686 if (m->m_pkthdr.csum_flags & 2687 (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 2688 cmd |= IXL_TX_DESC_CMD_IIPT_IPV6; 2689 } 2690 2691 switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) { 2692 case IXL_TX_DESC_CMD_IIPT_IPV4: 2693 case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM: 2694 len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2695 break; 2696 case IXL_TX_DESC_CMD_IIPT_IPV6: 2697 len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2698 break; 2699 default: 2700 len = 0; 2701 } 2702 cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT); 2703 2704 if (m->m_pkthdr.csum_flags & 2705 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) { 2706 len = sizeof(struct tcphdr); 2707 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2708 } else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) { 2709 len = sizeof(struct udphdr); 2710 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2711 } else { 2712 len = 0; 2713 } 2714 cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT); 2715 2716 *cmd_txd |= cmd; 2717 return 0; 2718 } 2719 2720 static void 2721 ixl_tx_common_locked(struct ifnet *ifp, struct ixl_tx_ring *txr, 2722 bool is_transmit) 2723 { 2724 struct ixl_softc *sc = ifp->if_softc; 2725 struct ixl_tx_desc *ring, *txd; 2726 struct ixl_tx_map *txm; 2727 bus_dmamap_t map; 2728 struct mbuf *m; 2729 uint64_t cmd, cmd_txd; 2730 unsigned int prod, free, last, i; 2731 unsigned int mask; 2732 int post = 0; 2733 2734 KASSERT(mutex_owned(&txr->txr_lock)); 2735 2736 if (!ISSET(ifp->if_flags, IFF_RUNNING) 2737 || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) { 2738 if (!is_transmit) 2739 IFQ_PURGE(&ifp->if_snd); 2740 return; 2741 } 2742 2743 prod = txr->txr_prod; 2744 free = txr->txr_cons; 2745 if (free <= prod) 2746 free += sc->sc_tx_ring_ndescs; 2747 free -= prod; 2748 2749 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2750 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2751 2752 ring = IXL_DMA_KVA(&txr->txr_mem); 2753 mask = sc->sc_tx_ring_ndescs - 1; 2754 last = prod; 2755 cmd = 0; 2756 txd = NULL; 2757 2758 for (;;) { 2759 if (free <= IXL_TX_PKT_DESCS) { 2760 if (!is_transmit) 2761 SET(ifp->if_flags, IFF_OACTIVE); 2762 break; 2763 } 2764 2765 if (is_transmit) 2766 m = pcq_get(txr->txr_intrq); 2767 else 2768 IFQ_DEQUEUE(&ifp->if_snd, m); 2769 2770 if (m == NULL) 2771 break; 2772 2773 txm = &txr->txr_maps[prod]; 2774 map = txm->txm_map; 2775 2776 if (ixl_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) { 2777 if_statinc(ifp, if_oerrors); 2778 m_freem(m); 2779 continue; 2780 } 2781 2782 cmd_txd = 0; 2783 if (m->m_pkthdr.csum_flags & IXL_CSUM_ALL_OFFLOAD) { 2784 ixl_tx_setup_offloads(m, &cmd_txd); 2785 } 2786 2787 if (vlan_has_tag(m)) { 2788 cmd_txd |= (uint64_t)vlan_get_tag(m) << 2789 IXL_TX_DESC_L2TAG1_SHIFT; 2790 cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1; 2791 } 2792 2793 bus_dmamap_sync(sc->sc_dmat, map, 0, 2794 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2795 2796 for (i = 0; i < (unsigned int)map->dm_nsegs; i++) { 2797 txd = &ring[prod]; 2798 2799 cmd = (uint64_t)map->dm_segs[i].ds_len << 2800 IXL_TX_DESC_BSIZE_SHIFT; 2801 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2802 cmd |= cmd_txd; 2803 2804 txd->addr = htole64(map->dm_segs[i].ds_addr); 2805 txd->cmd = htole64(cmd); 2806 2807 last = prod; 2808 2809 prod++; 2810 prod &= mask; 2811 } 2812 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2813 txd->cmd = htole64(cmd); 2814 2815 txm->txm_m = m; 2816 txm->txm_eop = last; 2817 2818 bpf_mtap(ifp, m, BPF_D_OUT); 2819 2820 free -= i; 2821 post = 1; 2822 } 2823 2824 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2825 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2826 2827 if (post) { 2828 txr->txr_prod = prod; 2829 ixl_wr(sc, txr->txr_tail, prod); 2830 } 2831 } 2832 2833 static int 2834 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr, u_int txlimit) 2835 { 2836 struct ifnet *ifp = &sc->sc_ec.ec_if; 2837 struct ixl_tx_desc *ring, *txd; 2838 struct ixl_tx_map *txm; 2839 struct mbuf *m; 2840 bus_dmamap_t map; 2841 unsigned int cons, prod, last; 2842 unsigned int mask; 2843 uint64_t dtype; 2844 int done = 0, more = 0; 2845 2846 KASSERT(mutex_owned(&txr->txr_lock)); 2847 2848 prod = txr->txr_prod; 2849 cons = txr->txr_cons; 2850 2851 if (cons == prod) 2852 return 0; 2853 2854 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2855 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2856 2857 ring = IXL_DMA_KVA(&txr->txr_mem); 2858 mask = sc->sc_tx_ring_ndescs - 1; 2859 2860 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2861 2862 do { 2863 if (txlimit-- <= 0) { 2864 more = 1; 2865 break; 2866 } 2867 2868 txm = &txr->txr_maps[cons]; 2869 last = txm->txm_eop; 2870 txd = &ring[last]; 2871 2872 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2873 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2874 break; 2875 2876 map = txm->txm_map; 2877 2878 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2879 BUS_DMASYNC_POSTWRITE); 2880 bus_dmamap_unload(sc->sc_dmat, map); 2881 2882 m = txm->txm_m; 2883 if (m != NULL) { 2884 if_statinc_ref(nsr, if_opackets); 2885 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2886 if (ISSET(m->m_flags, M_MCAST)) 2887 if_statinc_ref(nsr, if_omcasts); 2888 m_freem(m); 2889 } 2890 2891 txm->txm_m = NULL; 2892 txm->txm_eop = -1; 2893 2894 cons = last + 1; 2895 cons &= mask; 2896 done = 1; 2897 } while (cons != prod); 2898 2899 IF_STAT_PUTREF(ifp); 2900 2901 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2902 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2903 2904 txr->txr_cons = cons; 2905 2906 if (done) { 2907 softint_schedule(txr->txr_si); 2908 if (txr->txr_qid == 0) { 2909 CLR(ifp->if_flags, IFF_OACTIVE); 2910 if_schedule_deferred_start(ifp); 2911 } 2912 } 2913 2914 return more; 2915 } 2916 2917 static void 2918 ixl_start(struct ifnet *ifp) 2919 { 2920 struct ixl_softc *sc; 2921 struct ixl_tx_ring *txr; 2922 2923 sc = ifp->if_softc; 2924 txr = sc->sc_qps[0].qp_txr; 2925 2926 mutex_enter(&txr->txr_lock); 2927 ixl_tx_common_locked(ifp, txr, false); 2928 mutex_exit(&txr->txr_lock); 2929 } 2930 2931 static inline unsigned int 2932 ixl_select_txqueue(struct ixl_softc *sc, struct mbuf *m) 2933 { 2934 u_int cpuid; 2935 2936 cpuid = cpu_index(curcpu()); 2937 2938 return (unsigned int)(cpuid % sc->sc_nqueue_pairs); 2939 } 2940 2941 static int 2942 ixl_transmit(struct ifnet *ifp, struct mbuf *m) 2943 { 2944 struct ixl_softc *sc; 2945 struct ixl_tx_ring *txr; 2946 unsigned int qid; 2947 2948 sc = ifp->if_softc; 2949 qid = ixl_select_txqueue(sc, m); 2950 2951 txr = sc->sc_qps[qid].qp_txr; 2952 2953 if (__predict_false(!pcq_put(txr->txr_intrq, m))) { 2954 mutex_enter(&txr->txr_lock); 2955 txr->txr_pcqdrop.ev_count++; 2956 mutex_exit(&txr->txr_lock); 2957 2958 m_freem(m); 2959 return ENOBUFS; 2960 } 2961 2962 if (mutex_tryenter(&txr->txr_lock)) { 2963 ixl_tx_common_locked(ifp, txr, true); 2964 mutex_exit(&txr->txr_lock); 2965 } else { 2966 kpreempt_disable(); 2967 softint_schedule(txr->txr_si); 2968 kpreempt_enable(); 2969 } 2970 2971 return 0; 2972 } 2973 2974 static void 2975 ixl_deferred_transmit(void *xtxr) 2976 { 2977 struct ixl_tx_ring *txr = xtxr; 2978 struct ixl_softc *sc = txr->txr_sc; 2979 struct ifnet *ifp = &sc->sc_ec.ec_if; 2980 2981 mutex_enter(&txr->txr_lock); 2982 txr->txr_transmitdef.ev_count++; 2983 if (pcq_peek(txr->txr_intrq) != NULL) 2984 ixl_tx_common_locked(ifp, txr, true); 2985 mutex_exit(&txr->txr_lock); 2986 } 2987 2988 static struct ixl_rx_ring * 2989 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 2990 { 2991 struct ixl_rx_ring *rxr = NULL; 2992 struct ixl_rx_map *maps = NULL, *rxm; 2993 unsigned int i; 2994 2995 rxr = kmem_zalloc(sizeof(*rxr), KM_SLEEP); 2996 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_rx_ring_ndescs, 2997 KM_SLEEP); 2998 2999 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 3000 sizeof(struct ixl_rx_rd_desc_32) * sc->sc_rx_ring_ndescs, 3001 IXL_RX_QUEUE_ALIGN) != 0) 3002 goto free; 3003 3004 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3005 rxm = &maps[i]; 3006 3007 if (bus_dmamap_create(sc->sc_dmat, 3008 IXL_MCLBYTES, 1, IXL_MCLBYTES, 0, 3009 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &rxm->rxm_map) != 0) 3010 goto uncreate; 3011 3012 rxm->rxm_m = NULL; 3013 } 3014 3015 rxr->rxr_cons = rxr->rxr_prod = 0; 3016 rxr->rxr_m_head = NULL; 3017 rxr->rxr_m_tail = &rxr->rxr_m_head; 3018 rxr->rxr_maps = maps; 3019 3020 rxr->rxr_tail = I40E_QRX_TAIL(qid); 3021 rxr->rxr_qid = qid; 3022 mutex_init(&rxr->rxr_lock, MUTEX_DEFAULT, IPL_NET); 3023 3024 return rxr; 3025 3026 uncreate: 3027 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3028 rxm = &maps[i]; 3029 3030 if (rxm->rxm_map == NULL) 3031 continue; 3032 3033 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3034 } 3035 3036 ixl_dmamem_free(sc, &rxr->rxr_mem); 3037 free: 3038 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 3039 kmem_free(rxr, sizeof(*rxr)); 3040 3041 return NULL; 3042 } 3043 3044 static void 3045 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3046 { 3047 struct ixl_rx_map *maps, *rxm; 3048 bus_dmamap_t map; 3049 unsigned int i; 3050 3051 maps = rxr->rxr_maps; 3052 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3053 rxm = &maps[i]; 3054 3055 if (rxm->rxm_m == NULL) 3056 continue; 3057 3058 map = rxm->rxm_map; 3059 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3060 BUS_DMASYNC_POSTWRITE); 3061 bus_dmamap_unload(sc->sc_dmat, map); 3062 3063 m_freem(rxm->rxm_m); 3064 rxm->rxm_m = NULL; 3065 } 3066 3067 m_freem(rxr->rxr_m_head); 3068 rxr->rxr_m_head = NULL; 3069 rxr->rxr_m_tail = &rxr->rxr_m_head; 3070 3071 rxr->rxr_prod = rxr->rxr_cons = 0; 3072 } 3073 3074 static int 3075 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3076 { 3077 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3078 uint32_t reg; 3079 int i; 3080 3081 for (i = 0; i < 10; i++) { 3082 reg = ixl_rd(sc, ena); 3083 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3084 return 0; 3085 3086 delaymsec(10); 3087 } 3088 3089 return ETIMEDOUT; 3090 } 3091 3092 static int 3093 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3094 { 3095 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3096 uint32_t reg; 3097 int i; 3098 3099 KASSERT(mutex_owned(&rxr->rxr_lock)); 3100 3101 for (i = 0; i < 10; i++) { 3102 reg = ixl_rd(sc, ena); 3103 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3104 return 0; 3105 3106 delaymsec(10); 3107 } 3108 3109 return ETIMEDOUT; 3110 } 3111 3112 static void 3113 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3114 { 3115 struct ixl_hmc_rxq rxq; 3116 struct ifnet *ifp = &sc->sc_ec.ec_if; 3117 uint16_t rxmax; 3118 void *hmc; 3119 3120 memset(&rxq, 0, sizeof(rxq)); 3121 rxmax = ifp->if_mtu + IXL_MTU_ETHERLEN; 3122 3123 rxq.head = htole16(rxr->rxr_cons); 3124 rxq.base = htole64(IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3125 rxq.qlen = htole16(sc->sc_rx_ring_ndescs); 3126 rxq.dbuff = htole16(IXL_MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3127 rxq.hbuff = 0; 3128 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3129 rxq.dsize = IXL_HMC_RXQ_DSIZE_32; 3130 rxq.crcstrip = 1; 3131 rxq.l2sel = 1; 3132 rxq.showiv = 1; 3133 rxq.rxmax = htole16(rxmax); 3134 rxq.tphrdesc_ena = 0; 3135 rxq.tphwdesc_ena = 0; 3136 rxq.tphdata_ena = 0; 3137 rxq.tphhead_ena = 0; 3138 rxq.lrxqthresh = 0; 3139 rxq.prefena = 1; 3140 3141 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3142 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3143 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, 3144 __arraycount(ixl_hmc_pack_rxq)); 3145 } 3146 3147 static void 3148 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3149 { 3150 void *hmc; 3151 3152 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3153 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3154 rxr->rxr_cons = rxr->rxr_prod = 0; 3155 } 3156 3157 static void 3158 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3159 { 3160 struct ixl_rx_map *maps, *rxm; 3161 unsigned int i; 3162 3163 maps = rxr->rxr_maps; 3164 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3165 rxm = &maps[i]; 3166 3167 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3168 } 3169 3170 ixl_dmamem_free(sc, &rxr->rxr_mem); 3171 mutex_destroy(&rxr->rxr_lock); 3172 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 3173 kmem_free(rxr, sizeof(*rxr)); 3174 } 3175 3176 static inline void 3177 ixl_rx_csum(struct mbuf *m, uint64_t qword) 3178 { 3179 int flags_mask; 3180 3181 if (!ISSET(qword, IXL_RX_DESC_L3L4P)) { 3182 /* No L3 or L4 checksum was calculated */ 3183 return; 3184 } 3185 3186 switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) { 3187 case IXL_RX_DESC_PTYPE_IPV4FRAG: 3188 case IXL_RX_DESC_PTYPE_IPV4: 3189 case IXL_RX_DESC_PTYPE_SCTPV4: 3190 case IXL_RX_DESC_PTYPE_ICMPV4: 3191 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3192 break; 3193 case IXL_RX_DESC_PTYPE_TCPV4: 3194 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3195 flags_mask |= M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD; 3196 break; 3197 case IXL_RX_DESC_PTYPE_UDPV4: 3198 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3199 flags_mask |= M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD; 3200 break; 3201 case IXL_RX_DESC_PTYPE_TCPV6: 3202 flags_mask = M_CSUM_TCPv6 | M_CSUM_TCP_UDP_BAD; 3203 break; 3204 case IXL_RX_DESC_PTYPE_UDPV6: 3205 flags_mask = M_CSUM_UDPv6 | M_CSUM_TCP_UDP_BAD; 3206 break; 3207 default: 3208 flags_mask = 0; 3209 } 3210 3211 m->m_pkthdr.csum_flags |= (flags_mask & (M_CSUM_IPv4 | 3212 M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)); 3213 3214 if (ISSET(qword, IXL_RX_DESC_IPE)) { 3215 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_IPv4_BAD); 3216 } 3217 3218 if (ISSET(qword, IXL_RX_DESC_L4E)) { 3219 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_TCP_UDP_BAD); 3220 } 3221 } 3222 3223 static int 3224 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr, u_int rxlimit) 3225 { 3226 struct ifnet *ifp = &sc->sc_ec.ec_if; 3227 struct ixl_rx_wb_desc_32 *ring, *rxd; 3228 struct ixl_rx_map *rxm; 3229 bus_dmamap_t map; 3230 unsigned int cons, prod; 3231 struct mbuf *m; 3232 uint64_t word, word0; 3233 unsigned int len; 3234 unsigned int mask; 3235 int done = 0, more = 0; 3236 3237 KASSERT(mutex_owned(&rxr->rxr_lock)); 3238 3239 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3240 return 0; 3241 3242 prod = rxr->rxr_prod; 3243 cons = rxr->rxr_cons; 3244 3245 if (cons == prod) 3246 return 0; 3247 3248 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3249 0, IXL_DMA_LEN(&rxr->rxr_mem), 3250 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3251 3252 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3253 mask = sc->sc_rx_ring_ndescs - 1; 3254 3255 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 3256 3257 do { 3258 if (rxlimit-- <= 0) { 3259 more = 1; 3260 break; 3261 } 3262 3263 rxd = &ring[cons]; 3264 3265 word = le64toh(rxd->qword1); 3266 3267 if (!ISSET(word, IXL_RX_DESC_DD)) 3268 break; 3269 3270 rxm = &rxr->rxr_maps[cons]; 3271 3272 map = rxm->rxm_map; 3273 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3274 BUS_DMASYNC_POSTREAD); 3275 bus_dmamap_unload(sc->sc_dmat, map); 3276 3277 m = rxm->rxm_m; 3278 rxm->rxm_m = NULL; 3279 3280 KASSERT(m != NULL); 3281 3282 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3283 m->m_len = len; 3284 m->m_pkthdr.len = 0; 3285 3286 m->m_next = NULL; 3287 *rxr->rxr_m_tail = m; 3288 rxr->rxr_m_tail = &m->m_next; 3289 3290 m = rxr->rxr_m_head; 3291 m->m_pkthdr.len += len; 3292 3293 if (ISSET(word, IXL_RX_DESC_EOP)) { 3294 word0 = le64toh(rxd->qword0); 3295 3296 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 3297 vlan_set_tag(m, 3298 __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK)); 3299 } 3300 3301 if ((ifp->if_capenable & IXL_IFCAP_RXCSUM) != 0) 3302 ixl_rx_csum(m, word); 3303 3304 if (!ISSET(word, 3305 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3306 m_set_rcvif(m, ifp); 3307 if_statinc_ref(nsr, if_ipackets); 3308 if_statadd_ref(nsr, if_ibytes, 3309 m->m_pkthdr.len); 3310 if_percpuq_enqueue(ifp->if_percpuq, m); 3311 } else { 3312 if_statinc_ref(nsr, if_ierrors); 3313 m_freem(m); 3314 } 3315 3316 rxr->rxr_m_head = NULL; 3317 rxr->rxr_m_tail = &rxr->rxr_m_head; 3318 } 3319 3320 cons++; 3321 cons &= mask; 3322 3323 done = 1; 3324 } while (cons != prod); 3325 3326 if (done) { 3327 rxr->rxr_cons = cons; 3328 if (ixl_rxfill(sc, rxr) == -1) 3329 if_statinc_ref(nsr, if_iqdrops); 3330 } 3331 3332 IF_STAT_PUTREF(ifp); 3333 3334 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3335 0, IXL_DMA_LEN(&rxr->rxr_mem), 3336 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3337 3338 return more; 3339 } 3340 3341 static int 3342 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3343 { 3344 struct ixl_rx_rd_desc_32 *ring, *rxd; 3345 struct ixl_rx_map *rxm; 3346 bus_dmamap_t map; 3347 struct mbuf *m; 3348 unsigned int prod; 3349 unsigned int slots; 3350 unsigned int mask; 3351 int post = 0, error = 0; 3352 3353 KASSERT(mutex_owned(&rxr->rxr_lock)); 3354 3355 prod = rxr->rxr_prod; 3356 slots = ixl_rxr_unrefreshed(rxr->rxr_prod, rxr->rxr_cons, 3357 sc->sc_rx_ring_ndescs); 3358 3359 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3360 mask = sc->sc_rx_ring_ndescs - 1; 3361 3362 if (__predict_false(slots <= 0)) 3363 return -1; 3364 3365 do { 3366 rxm = &rxr->rxr_maps[prod]; 3367 3368 MGETHDR(m, M_DONTWAIT, MT_DATA); 3369 if (m == NULL) { 3370 rxr->rxr_mgethdr_failed.ev_count++; 3371 error = -1; 3372 break; 3373 } 3374 3375 MCLGET(m, M_DONTWAIT); 3376 if (!ISSET(m->m_flags, M_EXT)) { 3377 rxr->rxr_mgetcl_failed.ev_count++; 3378 error = -1; 3379 m_freem(m); 3380 break; 3381 } 3382 3383 m->m_len = m->m_pkthdr.len = MCLBYTES; 3384 m_adj(m, ETHER_ALIGN); 3385 3386 map = rxm->rxm_map; 3387 3388 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3389 BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 3390 rxr->rxr_mbuf_load_failed.ev_count++; 3391 error = -1; 3392 m_freem(m); 3393 break; 3394 } 3395 3396 rxm->rxm_m = m; 3397 3398 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3399 BUS_DMASYNC_PREREAD); 3400 3401 rxd = &ring[prod]; 3402 3403 rxd->paddr = htole64(map->dm_segs[0].ds_addr); 3404 rxd->haddr = htole64(0); 3405 3406 prod++; 3407 prod &= mask; 3408 3409 post = 1; 3410 3411 } while (--slots); 3412 3413 if (post) { 3414 rxr->rxr_prod = prod; 3415 ixl_wr(sc, rxr->rxr_tail, prod); 3416 } 3417 3418 return error; 3419 } 3420 3421 static inline int 3422 ixl_handle_queue_common(struct ixl_softc *sc, struct ixl_queue_pair *qp, 3423 u_int txlimit, struct evcnt *txevcnt, 3424 u_int rxlimit, struct evcnt *rxevcnt) 3425 { 3426 struct ixl_tx_ring *txr = qp->qp_txr; 3427 struct ixl_rx_ring *rxr = qp->qp_rxr; 3428 int txmore, rxmore; 3429 int rv; 3430 3431 mutex_enter(&txr->txr_lock); 3432 txevcnt->ev_count++; 3433 txmore = ixl_txeof(sc, txr, txlimit); 3434 mutex_exit(&txr->txr_lock); 3435 3436 mutex_enter(&rxr->rxr_lock); 3437 rxevcnt->ev_count++; 3438 rxmore = ixl_rxeof(sc, rxr, rxlimit); 3439 mutex_exit(&rxr->rxr_lock); 3440 3441 rv = txmore | (rxmore << 1); 3442 3443 return rv; 3444 } 3445 3446 static void 3447 ixl_sched_handle_queue(struct ixl_softc *sc, struct ixl_queue_pair *qp) 3448 { 3449 3450 if (qp->qp_workqueue) 3451 workqueue_enqueue(sc->sc_workq_txrx, &qp->qp_work, NULL); 3452 else 3453 softint_schedule(qp->qp_si); 3454 } 3455 3456 static int 3457 ixl_intr(void *xsc) 3458 { 3459 struct ixl_softc *sc = xsc; 3460 struct ixl_tx_ring *txr; 3461 struct ixl_rx_ring *rxr; 3462 uint32_t icr, rxintr, txintr; 3463 int rv = 0; 3464 unsigned int i; 3465 3466 KASSERT(sc != NULL); 3467 3468 ixl_enable_other_intr(sc); 3469 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3470 3471 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3472 atomic_inc_64(&sc->sc_event_atq.ev_count); 3473 ixl_atq_done(sc); 3474 ixl_work_add(sc->sc_workq, &sc->sc_arq_task); 3475 rv = 1; 3476 } 3477 3478 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3479 atomic_inc_64(&sc->sc_event_link.ev_count); 3480 ixl_work_add(sc->sc_workq, &sc->sc_link_state_task); 3481 rv = 1; 3482 } 3483 3484 rxintr = icr & I40E_INTR_NOTX_RX_MASK; 3485 txintr = icr & I40E_INTR_NOTX_TX_MASK; 3486 3487 if (txintr || rxintr) { 3488 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3489 txr = sc->sc_qps[i].qp_txr; 3490 rxr = sc->sc_qps[i].qp_rxr; 3491 3492 ixl_handle_queue_common(sc, &sc->sc_qps[i], 3493 IXL_TXRX_PROCESS_UNLIMIT, &txr->txr_intr, 3494 IXL_TXRX_PROCESS_UNLIMIT, &rxr->rxr_intr); 3495 } 3496 rv = 1; 3497 } 3498 3499 return rv; 3500 } 3501 3502 static int 3503 ixl_queue_intr(void *xqp) 3504 { 3505 struct ixl_queue_pair *qp = xqp; 3506 struct ixl_tx_ring *txr = qp->qp_txr; 3507 struct ixl_rx_ring *rxr = qp->qp_rxr; 3508 struct ixl_softc *sc = qp->qp_sc; 3509 u_int txlimit, rxlimit; 3510 int more; 3511 3512 txlimit = sc->sc_tx_intr_process_limit; 3513 rxlimit = sc->sc_rx_intr_process_limit; 3514 qp->qp_workqueue = sc->sc_txrx_workqueue; 3515 3516 more = ixl_handle_queue_common(sc, qp, 3517 txlimit, &txr->txr_intr, rxlimit, &rxr->rxr_intr); 3518 3519 if (more != 0) { 3520 ixl_sched_handle_queue(sc, qp); 3521 } else { 3522 /* for ALTQ */ 3523 if (txr->txr_qid == 0) 3524 if_schedule_deferred_start(&sc->sc_ec.ec_if); 3525 softint_schedule(txr->txr_si); 3526 3527 ixl_enable_queue_intr(sc, qp); 3528 } 3529 3530 return 1; 3531 } 3532 3533 static void 3534 ixl_handle_queue_wk(struct work *wk, void *xsc) 3535 { 3536 struct ixl_queue_pair *qp; 3537 3538 qp = container_of(wk, struct ixl_queue_pair, qp_work); 3539 ixl_handle_queue(qp); 3540 } 3541 3542 static void 3543 ixl_handle_queue(void *xqp) 3544 { 3545 struct ixl_queue_pair *qp = xqp; 3546 struct ixl_softc *sc = qp->qp_sc; 3547 struct ixl_tx_ring *txr = qp->qp_txr; 3548 struct ixl_rx_ring *rxr = qp->qp_rxr; 3549 u_int txlimit, rxlimit; 3550 int more; 3551 3552 txlimit = sc->sc_tx_process_limit; 3553 rxlimit = sc->sc_rx_process_limit; 3554 3555 more = ixl_handle_queue_common(sc, qp, 3556 txlimit, &txr->txr_defer, rxlimit, &rxr->rxr_defer); 3557 3558 if (more != 0) 3559 ixl_sched_handle_queue(sc, qp); 3560 else 3561 ixl_enable_queue_intr(sc, qp); 3562 } 3563 3564 static inline void 3565 ixl_print_hmc_error(struct ixl_softc *sc, uint32_t reg) 3566 { 3567 uint32_t hmc_idx, hmc_isvf; 3568 uint32_t hmc_errtype, hmc_objtype, hmc_data; 3569 3570 hmc_idx = reg & I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK; 3571 hmc_idx = hmc_idx >> I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT; 3572 hmc_isvf = reg & I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK; 3573 hmc_isvf = hmc_isvf >> I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT; 3574 hmc_errtype = reg & I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK; 3575 hmc_errtype = hmc_errtype >> I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT; 3576 hmc_objtype = reg & I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK; 3577 hmc_objtype = hmc_objtype >> I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT; 3578 hmc_data = ixl_rd(sc, I40E_PFHMC_ERRORDATA); 3579 3580 device_printf(sc->sc_dev, 3581 "HMC Error (idx=0x%x, isvf=0x%x, err=0x%x, obj=0x%x, data=0x%x)\n", 3582 hmc_idx, hmc_isvf, hmc_errtype, hmc_objtype, hmc_data); 3583 } 3584 3585 static int 3586 ixl_other_intr(void *xsc) 3587 { 3588 struct ixl_softc *sc = xsc; 3589 uint32_t icr, mask, reg; 3590 int rv; 3591 3592 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3593 mask = ixl_rd(sc, I40E_PFINT_ICR0_ENA); 3594 3595 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3596 atomic_inc_64(&sc->sc_event_atq.ev_count); 3597 ixl_atq_done(sc); 3598 ixl_work_add(sc->sc_workq, &sc->sc_arq_task); 3599 rv = 1; 3600 } 3601 3602 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3603 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3604 device_printf(sc->sc_dev, "link stat changed\n"); 3605 3606 atomic_inc_64(&sc->sc_event_link.ev_count); 3607 ixl_work_add(sc->sc_workq, &sc->sc_link_state_task); 3608 rv = 1; 3609 } 3610 3611 if (ISSET(icr, I40E_PFINT_ICR0_GRST_MASK)) { 3612 CLR(mask, I40E_PFINT_ICR0_ENA_GRST_MASK); 3613 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 3614 reg = reg & I40E_GLGEN_RSTAT_RESET_TYPE_MASK; 3615 reg = reg >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; 3616 3617 device_printf(sc->sc_dev, "GRST: %s\n", 3618 reg == I40E_RESET_CORER ? "CORER" : 3619 reg == I40E_RESET_GLOBR ? "GLOBR" : 3620 reg == I40E_RESET_EMPR ? "EMPR" : 3621 "POR"); 3622 } 3623 3624 if (ISSET(icr, I40E_PFINT_ICR0_ECC_ERR_MASK)) 3625 atomic_inc_64(&sc->sc_event_ecc_err.ev_count); 3626 if (ISSET(icr, I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)) 3627 atomic_inc_64(&sc->sc_event_pci_exception.ev_count); 3628 if (ISSET(icr, I40E_PFINT_ICR0_PE_CRITERR_MASK)) 3629 atomic_inc_64(&sc->sc_event_crit_err.ev_count); 3630 3631 if (ISSET(icr, IXL_ICR0_CRIT_ERR_MASK)) { 3632 CLR(mask, IXL_ICR0_CRIT_ERR_MASK); 3633 device_printf(sc->sc_dev, "critical error\n"); 3634 } 3635 3636 if (ISSET(icr, I40E_PFINT_ICR0_HMC_ERR_MASK)) { 3637 reg = ixl_rd(sc, I40E_PFHMC_ERRORINFO); 3638 if (ISSET(reg, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK)) 3639 ixl_print_hmc_error(sc, reg); 3640 ixl_wr(sc, I40E_PFHMC_ERRORINFO, 0); 3641 } 3642 3643 ixl_wr(sc, I40E_PFINT_ICR0_ENA, mask); 3644 ixl_flush(sc); 3645 ixl_enable_other_intr(sc); 3646 return rv; 3647 } 3648 3649 static void 3650 ixl_get_link_status_done(struct ixl_softc *sc, 3651 const struct ixl_aq_desc *iaq) 3652 { 3653 3654 ixl_link_state_update(sc, iaq); 3655 } 3656 3657 static void 3658 ixl_get_link_status(void *xsc) 3659 { 3660 struct ixl_softc *sc = xsc; 3661 struct ixl_aq_desc *iaq; 3662 struct ixl_aq_link_param *param; 3663 int error; 3664 3665 mutex_enter(&sc->sc_atq_lock); 3666 3667 iaq = &sc->sc_link_state_atq.iatq_desc; 3668 memset(iaq, 0, sizeof(*iaq)); 3669 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3670 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3671 param->notify = IXL_AQ_LINK_NOTIFY; 3672 3673 error = ixl_atq_exec_locked(sc, &sc->sc_link_state_atq); 3674 if (error == 0) { 3675 ixl_get_link_status_done(sc, iaq); 3676 } 3677 3678 ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done); 3679 3680 mutex_exit(&sc->sc_atq_lock); 3681 } 3682 3683 static void 3684 ixl_link_state_update(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3685 { 3686 struct ifnet *ifp = &sc->sc_ec.ec_if; 3687 int link_state; 3688 3689 KASSERT(kpreempt_disabled()); 3690 3691 link_state = ixl_set_link_status(sc, iaq); 3692 3693 if (ifp->if_link_state != link_state) 3694 if_link_state_change(ifp, link_state); 3695 3696 if (link_state != LINK_STATE_DOWN) { 3697 if_schedule_deferred_start(ifp); 3698 } 3699 } 3700 3701 static void 3702 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq, 3703 const char *msg) 3704 { 3705 char buf[512]; 3706 size_t len; 3707 3708 len = sizeof(buf); 3709 buf[--len] = '\0'; 3710 3711 device_printf(sc->sc_dev, "%s\n", msg); 3712 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags)); 3713 device_printf(sc->sc_dev, "flags %s opcode %04x\n", 3714 buf, le16toh(iaq->iaq_opcode)); 3715 device_printf(sc->sc_dev, "datalen %u retval %u\n", 3716 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval)); 3717 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie); 3718 device_printf(sc->sc_dev, "%08x %08x %08x %08x\n", 3719 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]), 3720 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3])); 3721 } 3722 3723 static void 3724 ixl_arq(void *xsc) 3725 { 3726 struct ixl_softc *sc = xsc; 3727 struct ixl_aq_desc *arq, *iaq; 3728 struct ixl_aq_buf *aqb; 3729 unsigned int cons = sc->sc_arq_cons; 3730 unsigned int prod; 3731 int done = 0; 3732 3733 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3734 sc->sc_aq_regs->arq_head_mask; 3735 3736 if (cons == prod) 3737 goto done; 3738 3739 arq = IXL_DMA_KVA(&sc->sc_arq); 3740 3741 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3742 0, IXL_DMA_LEN(&sc->sc_arq), 3743 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3744 3745 do { 3746 iaq = &arq[cons]; 3747 aqb = sc->sc_arq_live[cons]; 3748 3749 KASSERT(aqb != NULL); 3750 3751 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3752 BUS_DMASYNC_POSTREAD); 3753 3754 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3755 ixl_aq_dump(sc, iaq, "arq event"); 3756 3757 switch (iaq->iaq_opcode) { 3758 case htole16(IXL_AQ_OP_PHY_LINK_STATUS): 3759 kpreempt_disable(); 3760 ixl_link_state_update(sc, iaq); 3761 kpreempt_enable(); 3762 break; 3763 } 3764 3765 memset(iaq, 0, sizeof(*iaq)); 3766 sc->sc_arq_live[cons] = NULL; 3767 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3768 3769 cons++; 3770 cons &= IXL_AQ_MASK; 3771 3772 done = 1; 3773 } while (cons != prod); 3774 3775 if (done) { 3776 sc->sc_arq_cons = cons; 3777 ixl_arq_fill(sc); 3778 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3779 0, IXL_DMA_LEN(&sc->sc_arq), 3780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3781 } 3782 3783 done: 3784 ixl_enable_other_intr(sc); 3785 } 3786 3787 static void 3788 ixl_atq_set(struct ixl_atq *iatq, 3789 void (*fn)(struct ixl_softc *, const struct ixl_aq_desc *)) 3790 { 3791 3792 iatq->iatq_fn = fn; 3793 } 3794 3795 static int 3796 ixl_atq_post_locked(struct ixl_softc *sc, struct ixl_atq *iatq) 3797 { 3798 struct ixl_aq_desc *atq, *slot; 3799 unsigned int prod, cons, prod_next; 3800 3801 /* assert locked */ 3802 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3803 3804 atq = IXL_DMA_KVA(&sc->sc_atq); 3805 prod = sc->sc_atq_prod; 3806 cons = sc->sc_atq_cons; 3807 prod_next = (prod +1) & IXL_AQ_MASK; 3808 3809 if (cons == prod_next) 3810 return ENOMEM; 3811 3812 slot = &atq[prod]; 3813 3814 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3815 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3816 3817 KASSERT(iatq->iatq_fn != NULL); 3818 *slot = iatq->iatq_desc; 3819 slot->iaq_cookie = (uint64_t)((intptr_t)iatq); 3820 3821 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3822 ixl_aq_dump(sc, slot, "atq command"); 3823 3824 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3825 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3826 3827 sc->sc_atq_prod = prod_next; 3828 ixl_wr(sc, sc->sc_aq_regs->atq_tail, sc->sc_atq_prod); 3829 3830 return 0; 3831 } 3832 3833 static void 3834 ixl_atq_done_locked(struct ixl_softc *sc) 3835 { 3836 struct ixl_aq_desc *atq, *slot; 3837 struct ixl_atq *iatq; 3838 unsigned int cons; 3839 unsigned int prod; 3840 3841 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3842 3843 prod = sc->sc_atq_prod; 3844 cons = sc->sc_atq_cons; 3845 3846 if (prod == cons) 3847 return; 3848 3849 atq = IXL_DMA_KVA(&sc->sc_atq); 3850 3851 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3852 0, IXL_DMA_LEN(&sc->sc_atq), 3853 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3854 3855 do { 3856 slot = &atq[cons]; 3857 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3858 break; 3859 3860 iatq = (struct ixl_atq *)((intptr_t)slot->iaq_cookie); 3861 iatq->iatq_desc = *slot; 3862 3863 memset(slot, 0, sizeof(*slot)); 3864 3865 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3866 ixl_aq_dump(sc, &iatq->iatq_desc, "atq response"); 3867 3868 (*iatq->iatq_fn)(sc, &iatq->iatq_desc); 3869 3870 cons++; 3871 cons &= IXL_AQ_MASK; 3872 } while (cons != prod); 3873 3874 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3875 0, IXL_DMA_LEN(&sc->sc_atq), 3876 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3877 3878 sc->sc_atq_cons = cons; 3879 } 3880 3881 static void 3882 ixl_atq_done(struct ixl_softc *sc) 3883 { 3884 3885 mutex_enter(&sc->sc_atq_lock); 3886 ixl_atq_done_locked(sc); 3887 mutex_exit(&sc->sc_atq_lock); 3888 } 3889 3890 static void 3891 ixl_wakeup(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3892 { 3893 3894 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3895 3896 cv_signal(&sc->sc_atq_cv); 3897 } 3898 3899 static int 3900 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq) 3901 { 3902 int error; 3903 3904 mutex_enter(&sc->sc_atq_lock); 3905 error = ixl_atq_exec_locked(sc, iatq); 3906 mutex_exit(&sc->sc_atq_lock); 3907 3908 return error; 3909 } 3910 3911 static int 3912 ixl_atq_exec_locked(struct ixl_softc *sc, struct ixl_atq *iatq) 3913 { 3914 int error; 3915 3916 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3917 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3918 3919 ixl_atq_set(iatq, ixl_wakeup); 3920 3921 error = ixl_atq_post_locked(sc, iatq); 3922 if (error) 3923 return error; 3924 3925 error = cv_timedwait(&sc->sc_atq_cv, &sc->sc_atq_lock, 3926 IXL_ATQ_EXEC_TIMEOUT); 3927 3928 return error; 3929 } 3930 3931 static int 3932 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3933 { 3934 struct ixl_aq_desc *atq, *slot; 3935 unsigned int prod; 3936 unsigned int t = 0; 3937 3938 mutex_enter(&sc->sc_atq_lock); 3939 3940 atq = IXL_DMA_KVA(&sc->sc_atq); 3941 prod = sc->sc_atq_prod; 3942 slot = atq + prod; 3943 3944 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3945 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3946 3947 *slot = *iaq; 3948 slot->iaq_flags |= htole16(IXL_AQ_SI); 3949 3950 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3951 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3952 3953 prod++; 3954 prod &= IXL_AQ_MASK; 3955 sc->sc_atq_prod = prod; 3956 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3957 3958 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3959 delaymsec(1); 3960 3961 if (t++ > tm) { 3962 mutex_exit(&sc->sc_atq_lock); 3963 return ETIMEDOUT; 3964 } 3965 } 3966 3967 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3968 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3969 *iaq = *slot; 3970 memset(slot, 0, sizeof(*slot)); 3971 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3972 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3973 3974 sc->sc_atq_cons = prod; 3975 3976 mutex_exit(&sc->sc_atq_lock); 3977 3978 return 0; 3979 } 3980 3981 static int 3982 ixl_get_version(struct ixl_softc *sc) 3983 { 3984 struct ixl_aq_desc iaq; 3985 uint32_t fwbuild, fwver, apiver; 3986 uint16_t api_maj_ver, api_min_ver; 3987 3988 memset(&iaq, 0, sizeof(iaq)); 3989 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3990 3991 iaq.iaq_retval = le16toh(23); 3992 3993 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 3994 return ETIMEDOUT; 3995 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 3996 return EIO; 3997 3998 fwbuild = le32toh(iaq.iaq_param[1]); 3999 fwver = le32toh(iaq.iaq_param[2]); 4000 apiver = le32toh(iaq.iaq_param[3]); 4001 4002 api_maj_ver = (uint16_t)apiver; 4003 api_min_ver = (uint16_t)(apiver >> 16); 4004 4005 aprint_normal(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 4006 (uint16_t)(fwver >> 16), fwbuild, api_maj_ver, api_min_ver); 4007 4008 if (sc->sc_mac_type == I40E_MAC_X722) { 4009 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK | 4010 IXL_SC_AQ_FLAG_NVMREAD); 4011 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL); 4012 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS); 4013 } 4014 4015 #define IXL_API_VER(maj, min) (((uint32_t)(maj) << 16) | (min)) 4016 if (IXL_API_VER(api_maj_ver, api_min_ver) >= IXL_API_VER(1, 5)) { 4017 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL); 4018 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK); 4019 } 4020 #undef IXL_API_VER 4021 4022 return 0; 4023 } 4024 4025 static int 4026 ixl_get_nvm_version(struct ixl_softc *sc) 4027 { 4028 uint16_t nvmver, cfg_ptr, eetrack_hi, eetrack_lo, oem_hi, oem_lo; 4029 uint32_t eetrack, oem; 4030 uint16_t nvm_maj_ver, nvm_min_ver, oem_build; 4031 uint8_t oem_ver, oem_patch; 4032 4033 nvmver = cfg_ptr = eetrack_hi = eetrack_lo = oem_hi = oem_lo = 0; 4034 ixl_rd16_nvm(sc, I40E_SR_NVM_DEV_STARTER_VERSION, &nvmver); 4035 ixl_rd16_nvm(sc, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 4036 ixl_rd16_nvm(sc, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 4037 ixl_rd16_nvm(sc, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); 4038 ixl_rd16_nvm(sc, cfg_ptr + I40E_NVM_OEM_VER_OFF, &oem_hi); 4039 ixl_rd16_nvm(sc, cfg_ptr + I40E_NVM_OEM_VER_OFF + 1, &oem_lo); 4040 4041 nvm_maj_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_HI_MASK); 4042 nvm_min_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_LO_MASK); 4043 eetrack = ((uint32_t)eetrack_hi << 16) | eetrack_lo; 4044 oem = ((uint32_t)oem_hi << 16) | oem_lo; 4045 oem_ver = __SHIFTOUT(oem, IXL_NVM_OEMVERSION_MASK); 4046 oem_build = __SHIFTOUT(oem, IXL_NVM_OEMBUILD_MASK); 4047 oem_patch = __SHIFTOUT(oem, IXL_NVM_OEMPATCH_MASK); 4048 4049 aprint_normal(" nvm %x.%02x etid %08x oem %d.%d.%d", 4050 nvm_maj_ver, nvm_min_ver, eetrack, 4051 oem_ver, oem_build, oem_patch); 4052 4053 return 0; 4054 } 4055 4056 static int 4057 ixl_pxe_clear(struct ixl_softc *sc) 4058 { 4059 struct ixl_aq_desc iaq; 4060 int rv; 4061 4062 memset(&iaq, 0, sizeof(iaq)); 4063 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 4064 iaq.iaq_param[0] = htole32(0x2); 4065 4066 rv = ixl_atq_poll(sc, &iaq, 250); 4067 4068 ixl_wr(sc, I40E_GLLAN_RCTL_0, 0x1); 4069 4070 if (rv != 0) 4071 return ETIMEDOUT; 4072 4073 switch (iaq.iaq_retval) { 4074 case htole16(IXL_AQ_RC_OK): 4075 case htole16(IXL_AQ_RC_EEXIST): 4076 break; 4077 default: 4078 return EIO; 4079 } 4080 4081 return 0; 4082 } 4083 4084 static int 4085 ixl_lldp_shut(struct ixl_softc *sc) 4086 { 4087 struct ixl_aq_desc iaq; 4088 4089 memset(&iaq, 0, sizeof(iaq)); 4090 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 4091 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 4092 4093 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4094 aprint_error_dev(sc->sc_dev, "STOP LLDP AGENT timeout\n"); 4095 return -1; 4096 } 4097 4098 switch (iaq.iaq_retval) { 4099 case htole16(IXL_AQ_RC_EMODE): 4100 case htole16(IXL_AQ_RC_EPERM): 4101 /* ignore silently */ 4102 default: 4103 break; 4104 } 4105 4106 return 0; 4107 } 4108 4109 static void 4110 ixl_parse_hw_capability(struct ixl_softc *sc, struct ixl_aq_capability *cap) 4111 { 4112 uint16_t id; 4113 uint32_t number, logical_id; 4114 4115 id = le16toh(cap->cap_id); 4116 number = le32toh(cap->number); 4117 logical_id = le32toh(cap->logical_id); 4118 4119 switch (id) { 4120 case IXL_AQ_CAP_RSS: 4121 sc->sc_rss_table_size = number; 4122 sc->sc_rss_table_entry_width = logical_id; 4123 break; 4124 case IXL_AQ_CAP_RXQ: 4125 case IXL_AQ_CAP_TXQ: 4126 sc->sc_nqueue_pairs_device = MIN(number, 4127 sc->sc_nqueue_pairs_device); 4128 break; 4129 } 4130 } 4131 4132 static int 4133 ixl_get_hw_capabilities(struct ixl_softc *sc) 4134 { 4135 struct ixl_dmamem idm; 4136 struct ixl_aq_desc iaq; 4137 struct ixl_aq_capability *caps; 4138 size_t i, ncaps; 4139 bus_size_t caps_size; 4140 uint16_t status; 4141 int rv; 4142 4143 caps_size = sizeof(caps[0]) * 40; 4144 memset(&iaq, 0, sizeof(iaq)); 4145 iaq.iaq_opcode = htole16(IXL_AQ_OP_LIST_FUNC_CAP); 4146 4147 do { 4148 if (ixl_dmamem_alloc(sc, &idm, caps_size, 0) != 0) { 4149 return -1; 4150 } 4151 4152 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4153 (caps_size > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4154 iaq.iaq_datalen = htole16(caps_size); 4155 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4156 4157 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, 4158 IXL_DMA_LEN(&idm), BUS_DMASYNC_PREREAD); 4159 4160 rv = ixl_atq_poll(sc, &iaq, 250); 4161 4162 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, 4163 IXL_DMA_LEN(&idm), BUS_DMASYNC_POSTREAD); 4164 4165 if (rv != 0) { 4166 aprint_error(", HW capabilities timeout\n"); 4167 goto done; 4168 } 4169 4170 status = le16toh(iaq.iaq_retval); 4171 4172 if (status == IXL_AQ_RC_ENOMEM) { 4173 caps_size = le16toh(iaq.iaq_datalen); 4174 ixl_dmamem_free(sc, &idm); 4175 } 4176 } while (status == IXL_AQ_RC_ENOMEM); 4177 4178 if (status != IXL_AQ_RC_OK) { 4179 aprint_error(", HW capabilities error\n"); 4180 goto done; 4181 } 4182 4183 caps = IXL_DMA_KVA(&idm); 4184 ncaps = le16toh(iaq.iaq_param[1]); 4185 4186 for (i = 0; i < ncaps; i++) { 4187 ixl_parse_hw_capability(sc, &caps[i]); 4188 } 4189 4190 done: 4191 ixl_dmamem_free(sc, &idm); 4192 return rv; 4193 } 4194 4195 static int 4196 ixl_get_mac(struct ixl_softc *sc) 4197 { 4198 struct ixl_dmamem idm; 4199 struct ixl_aq_desc iaq; 4200 struct ixl_aq_mac_addresses *addrs; 4201 int rv; 4202 4203 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 4204 aprint_error(", unable to allocate mac addresses\n"); 4205 return -1; 4206 } 4207 4208 memset(&iaq, 0, sizeof(iaq)); 4209 iaq.iaq_flags = htole16(IXL_AQ_BUF); 4210 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 4211 iaq.iaq_datalen = htole16(sizeof(*addrs)); 4212 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4213 4214 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4215 BUS_DMASYNC_PREREAD); 4216 4217 rv = ixl_atq_poll(sc, &iaq, 250); 4218 4219 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4220 BUS_DMASYNC_POSTREAD); 4221 4222 if (rv != 0) { 4223 aprint_error(", MAC ADDRESS READ timeout\n"); 4224 rv = -1; 4225 goto done; 4226 } 4227 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4228 aprint_error(", MAC ADDRESS READ error\n"); 4229 rv = -1; 4230 goto done; 4231 } 4232 4233 addrs = IXL_DMA_KVA(&idm); 4234 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 4235 printf(", port address is not valid\n"); 4236 goto done; 4237 } 4238 4239 memcpy(sc->sc_enaddr, addrs->port, ETHER_ADDR_LEN); 4240 rv = 0; 4241 4242 done: 4243 ixl_dmamem_free(sc, &idm); 4244 return rv; 4245 } 4246 4247 static int 4248 ixl_get_switch_config(struct ixl_softc *sc) 4249 { 4250 struct ixl_dmamem idm; 4251 struct ixl_aq_desc iaq; 4252 struct ixl_aq_switch_config *hdr; 4253 struct ixl_aq_switch_config_element *elms, *elm; 4254 unsigned int nelm, i; 4255 int rv; 4256 4257 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4258 aprint_error_dev(sc->sc_dev, 4259 "unable to allocate switch config buffer\n"); 4260 return -1; 4261 } 4262 4263 memset(&iaq, 0, sizeof(iaq)); 4264 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4265 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4266 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 4267 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 4268 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4269 4270 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4271 BUS_DMASYNC_PREREAD); 4272 4273 rv = ixl_atq_poll(sc, &iaq, 250); 4274 4275 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4276 BUS_DMASYNC_POSTREAD); 4277 4278 if (rv != 0) { 4279 aprint_error_dev(sc->sc_dev, "GET SWITCH CONFIG timeout\n"); 4280 rv = -1; 4281 goto done; 4282 } 4283 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4284 aprint_error_dev(sc->sc_dev, "GET SWITCH CONFIG error\n"); 4285 rv = -1; 4286 goto done; 4287 } 4288 4289 hdr = IXL_DMA_KVA(&idm); 4290 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 4291 4292 nelm = le16toh(hdr->num_reported); 4293 if (nelm < 1) { 4294 aprint_error_dev(sc->sc_dev, "no switch config available\n"); 4295 rv = -1; 4296 goto done; 4297 } 4298 4299 for (i = 0; i < nelm; i++) { 4300 elm = &elms[i]; 4301 4302 aprint_debug_dev(sc->sc_dev, 4303 "type %x revision %u seid %04x\n", 4304 elm->type, elm->revision, le16toh(elm->seid)); 4305 aprint_debug_dev(sc->sc_dev, 4306 "uplink %04x downlink %04x\n", 4307 le16toh(elm->uplink_seid), 4308 le16toh(elm->downlink_seid)); 4309 aprint_debug_dev(sc->sc_dev, 4310 "conntype %x scheduler %04x extra %04x\n", 4311 elm->connection_type, 4312 le16toh(elm->scheduler_id), 4313 le16toh(elm->element_info)); 4314 } 4315 4316 elm = &elms[0]; 4317 4318 sc->sc_uplink_seid = elm->uplink_seid; 4319 sc->sc_downlink_seid = elm->downlink_seid; 4320 sc->sc_seid = elm->seid; 4321 4322 if ((sc->sc_uplink_seid == htole16(0)) != 4323 (sc->sc_downlink_seid == htole16(0))) { 4324 aprint_error_dev(sc->sc_dev, "SEIDs are misconfigured\n"); 4325 rv = -1; 4326 goto done; 4327 } 4328 4329 done: 4330 ixl_dmamem_free(sc, &idm); 4331 return rv; 4332 } 4333 4334 static int 4335 ixl_phy_mask_ints(struct ixl_softc *sc) 4336 { 4337 struct ixl_aq_desc iaq; 4338 4339 memset(&iaq, 0, sizeof(iaq)); 4340 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 4341 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 4342 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 4343 IXL_AQ_PHY_EV_MEDIA_NA)); 4344 4345 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4346 aprint_error_dev(sc->sc_dev, "SET PHY EVENT MASK timeout\n"); 4347 return -1; 4348 } 4349 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4350 aprint_error_dev(sc->sc_dev, "SET PHY EVENT MASK error\n"); 4351 return -1; 4352 } 4353 4354 return 0; 4355 } 4356 4357 static int 4358 ixl_get_phy_abilities(struct ixl_softc *sc,struct ixl_dmamem *idm) 4359 { 4360 struct ixl_aq_desc iaq; 4361 int rv; 4362 4363 memset(&iaq, 0, sizeof(iaq)); 4364 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4365 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4366 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 4367 iaq.iaq_datalen = htole16(IXL_DMA_LEN(idm)); 4368 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 4369 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 4370 4371 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4372 BUS_DMASYNC_PREREAD); 4373 4374 rv = ixl_atq_poll(sc, &iaq, 250); 4375 4376 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4377 BUS_DMASYNC_POSTREAD); 4378 4379 if (rv != 0) 4380 return -1; 4381 4382 return le16toh(iaq.iaq_retval); 4383 } 4384 4385 static int 4386 ixl_get_phy_info(struct ixl_softc *sc) 4387 { 4388 struct ixl_dmamem idm; 4389 struct ixl_aq_phy_abilities *phy; 4390 int rv; 4391 4392 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4393 aprint_error_dev(sc->sc_dev, 4394 "unable to allocate phy abilities buffer\n"); 4395 return -1; 4396 } 4397 4398 rv = ixl_get_phy_abilities(sc, &idm); 4399 switch (rv) { 4400 case -1: 4401 aprint_error_dev(sc->sc_dev, "GET PHY ABILITIES timeout\n"); 4402 goto done; 4403 case IXL_AQ_RC_OK: 4404 break; 4405 case IXL_AQ_RC_EIO: 4406 aprint_error_dev(sc->sc_dev,"unable to query phy types\n"); 4407 goto done; 4408 default: 4409 aprint_error_dev(sc->sc_dev, 4410 "GET PHY ABILITIIES error %u\n", rv); 4411 goto done; 4412 } 4413 4414 phy = IXL_DMA_KVA(&idm); 4415 4416 sc->sc_phy_types = le32toh(phy->phy_type); 4417 sc->sc_phy_types |= (uint64_t)le32toh(phy->phy_type_ext) << 32; 4418 4419 sc->sc_phy_abilities = phy->abilities; 4420 sc->sc_phy_linkspeed = phy->link_speed; 4421 sc->sc_phy_fec_cfg = phy->fec_cfg_curr_mod_ext_info & 4422 (IXL_AQ_ENABLE_FEC_KR | IXL_AQ_ENABLE_FEC_RS | 4423 IXL_AQ_REQUEST_FEC_KR | IXL_AQ_REQUEST_FEC_RS); 4424 sc->sc_eee_cap = phy->eee_capability; 4425 sc->sc_eeer_val = phy->eeer_val; 4426 sc->sc_d3_lpan = phy->d3_lpan; 4427 4428 rv = 0; 4429 4430 done: 4431 ixl_dmamem_free(sc, &idm); 4432 return rv; 4433 } 4434 4435 static int 4436 ixl_set_phy_config(struct ixl_softc *sc, 4437 uint8_t link_speed, uint8_t abilities, bool polling) 4438 { 4439 struct ixl_aq_phy_param *param; 4440 struct ixl_atq iatq; 4441 struct ixl_aq_desc *iaq; 4442 int error; 4443 4444 memset(&iatq, 0, sizeof(iatq)); 4445 4446 iaq = &iatq.iatq_desc; 4447 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_CONFIG); 4448 param = (struct ixl_aq_phy_param *)&iaq->iaq_param; 4449 param->phy_types = htole32((uint32_t)sc->sc_phy_types); 4450 param->phy_type_ext = (uint8_t)(sc->sc_phy_types >> 32); 4451 param->link_speed = link_speed; 4452 param->abilities = abilities | IXL_AQ_PHY_ABILITY_AUTO_LINK; 4453 param->fec_cfg = sc->sc_phy_fec_cfg; 4454 param->eee_capability = sc->sc_eee_cap; 4455 param->eeer_val = sc->sc_eeer_val; 4456 param->d3_lpan = sc->sc_d3_lpan; 4457 4458 if (polling) 4459 error = ixl_atq_poll(sc, iaq, 250); 4460 else 4461 error = ixl_atq_exec(sc, &iatq); 4462 4463 if (error != 0) 4464 return error; 4465 4466 switch (le16toh(iaq->iaq_retval)) { 4467 case IXL_AQ_RC_OK: 4468 break; 4469 case IXL_AQ_RC_EPERM: 4470 return EPERM; 4471 default: 4472 return EIO; 4473 } 4474 4475 return 0; 4476 } 4477 4478 static int 4479 ixl_set_phy_autoselect(struct ixl_softc *sc) 4480 { 4481 uint8_t link_speed, abilities; 4482 4483 link_speed = sc->sc_phy_linkspeed; 4484 abilities = IXL_PHY_ABILITY_LINKUP | IXL_PHY_ABILITY_AUTONEGO; 4485 4486 return ixl_set_phy_config(sc, link_speed, abilities, true); 4487 } 4488 4489 static int 4490 ixl_get_link_status_poll(struct ixl_softc *sc, int *l) 4491 { 4492 struct ixl_aq_desc iaq; 4493 struct ixl_aq_link_param *param; 4494 int link; 4495 4496 memset(&iaq, 0, sizeof(iaq)); 4497 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 4498 param = (struct ixl_aq_link_param *)iaq.iaq_param; 4499 param->notify = IXL_AQ_LINK_NOTIFY; 4500 4501 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4502 return ETIMEDOUT; 4503 } 4504 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4505 return EIO; 4506 } 4507 4508 link = ixl_set_link_status(sc, &iaq); 4509 4510 if (l != NULL) 4511 *l = link; 4512 4513 return 0; 4514 } 4515 4516 static int 4517 ixl_get_vsi(struct ixl_softc *sc) 4518 { 4519 struct ixl_dmamem *vsi = &sc->sc_scratch; 4520 struct ixl_aq_desc iaq; 4521 struct ixl_aq_vsi_param *param; 4522 struct ixl_aq_vsi_reply *reply; 4523 struct ixl_aq_vsi_data *data; 4524 int rv; 4525 4526 /* grumble, vsi info isn't "known" at compile time */ 4527 4528 memset(&iaq, 0, sizeof(iaq)); 4529 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4530 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4531 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4532 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi)); 4533 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4534 4535 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4536 param->uplink_seid = sc->sc_seid; 4537 4538 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4539 BUS_DMASYNC_PREREAD); 4540 4541 rv = ixl_atq_poll(sc, &iaq, 250); 4542 4543 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4544 BUS_DMASYNC_POSTREAD); 4545 4546 if (rv != 0) { 4547 return ETIMEDOUT; 4548 } 4549 4550 switch (le16toh(iaq.iaq_retval)) { 4551 case IXL_AQ_RC_OK: 4552 break; 4553 case IXL_AQ_RC_ENOENT: 4554 return ENOENT; 4555 case IXL_AQ_RC_EACCES: 4556 return EACCES; 4557 default: 4558 return EIO; 4559 } 4560 4561 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4562 sc->sc_vsi_number = le16toh(reply->vsi_number); 4563 data = IXL_DMA_KVA(vsi); 4564 sc->sc_vsi_stat_counter_idx = le16toh(data->stat_counter_idx); 4565 4566 return 0; 4567 } 4568 4569 static int 4570 ixl_set_vsi(struct ixl_softc *sc) 4571 { 4572 struct ixl_dmamem *vsi = &sc->sc_scratch; 4573 struct ixl_aq_desc iaq; 4574 struct ixl_aq_vsi_param *param; 4575 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4576 unsigned int qnum; 4577 uint16_t val; 4578 int rv; 4579 4580 qnum = sc->sc_nqueue_pairs - 1; 4581 4582 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4583 IXL_AQ_VSI_VALID_VLAN); 4584 4585 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4586 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4587 data->queue_mapping[0] = htole16(0); 4588 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4589 (qnum << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4590 4591 val = le16toh(data->port_vlan_flags); 4592 CLR(val, IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK); 4593 SET(val, IXL_AQ_VSI_PVLAN_MODE_ALL); 4594 4595 if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWTAGGING)) { 4596 SET(val, IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH); 4597 } else { 4598 SET(val, IXL_AQ_VSI_PVLAN_EMOD_NOTHING); 4599 } 4600 4601 data->port_vlan_flags = htole16(val); 4602 4603 /* grumble, vsi info isn't "known" at compile time */ 4604 4605 memset(&iaq, 0, sizeof(iaq)); 4606 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4607 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4608 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4609 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi)); 4610 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4611 4612 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4613 param->uplink_seid = sc->sc_seid; 4614 4615 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4616 BUS_DMASYNC_PREWRITE); 4617 4618 rv = ixl_atq_poll(sc, &iaq, 250); 4619 4620 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4621 BUS_DMASYNC_POSTWRITE); 4622 4623 if (rv != 0) { 4624 return ETIMEDOUT; 4625 } 4626 4627 switch (le16toh(iaq.iaq_retval)) { 4628 case IXL_AQ_RC_OK: 4629 break; 4630 case IXL_AQ_RC_ENOENT: 4631 return ENOENT; 4632 case IXL_AQ_RC_EACCES: 4633 return EACCES; 4634 default: 4635 return EIO; 4636 } 4637 4638 return 0; 4639 } 4640 4641 static void 4642 ixl_set_filter_control(struct ixl_softc *sc) 4643 { 4644 uint32_t reg; 4645 4646 reg = ixl_rd_rx_csr(sc, I40E_PFQF_CTL_0); 4647 4648 CLR(reg, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 4649 SET(reg, I40E_HASH_LUT_SIZE_128 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT); 4650 4651 SET(reg, I40E_PFQF_CTL_0_FD_ENA_MASK); 4652 SET(reg, I40E_PFQF_CTL_0_ETYPE_ENA_MASK); 4653 SET(reg, I40E_PFQF_CTL_0_MACVLAN_ENA_MASK); 4654 4655 ixl_wr_rx_csr(sc, I40E_PFQF_CTL_0, reg); 4656 } 4657 4658 static inline void 4659 ixl_get_default_rss_key(uint32_t *buf, size_t len) 4660 { 4661 size_t cplen; 4662 uint8_t rss_seed[RSS_KEYSIZE]; 4663 4664 rss_getkey(rss_seed); 4665 memset(buf, 0, len); 4666 4667 cplen = MIN(len, sizeof(rss_seed)); 4668 memcpy(buf, rss_seed, cplen); 4669 } 4670 4671 static int 4672 ixl_set_rss_key(struct ixl_softc *sc, uint8_t *key, size_t keylen) 4673 { 4674 struct ixl_dmamem *idm; 4675 struct ixl_atq iatq; 4676 struct ixl_aq_desc *iaq; 4677 struct ixl_aq_rss_key_param *param; 4678 struct ixl_aq_rss_key_data *data; 4679 size_t len, datalen, stdlen, extlen; 4680 uint16_t vsi_id; 4681 int rv; 4682 4683 memset(&iatq, 0, sizeof(iatq)); 4684 iaq = &iatq.iatq_desc; 4685 idm = &sc->sc_aqbuf; 4686 4687 datalen = sizeof(*data); 4688 4689 /*XXX The buf size has to be less than the size of the register */ 4690 datalen = MIN(IXL_RSS_KEY_SIZE_REG * sizeof(uint32_t), datalen); 4691 4692 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4693 (datalen > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4694 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_KEY); 4695 iaq->iaq_datalen = htole16(datalen); 4696 4697 param = (struct ixl_aq_rss_key_param *)iaq->iaq_param; 4698 vsi_id = (sc->sc_vsi_number << IXL_AQ_RSSKEY_VSI_ID_SHIFT) | 4699 IXL_AQ_RSSKEY_VSI_VALID; 4700 param->vsi_id = htole16(vsi_id); 4701 4702 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 4703 data = IXL_DMA_KVA(idm); 4704 4705 len = MIN(keylen, datalen); 4706 stdlen = MIN(sizeof(data->standard_rss_key), len); 4707 memcpy(data->standard_rss_key, key, stdlen); 4708 len = (len > stdlen) ? (len - stdlen) : 0; 4709 4710 extlen = MIN(sizeof(data->extended_hash_key), len); 4711 extlen = (stdlen < keylen) ? 0 : keylen - stdlen; 4712 memcpy(data->extended_hash_key, key + stdlen, extlen); 4713 4714 ixl_aq_dva(iaq, IXL_DMA_DVA(idm)); 4715 4716 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4717 IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE); 4718 4719 rv = ixl_atq_exec(sc, &iatq); 4720 4721 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4722 IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE); 4723 4724 if (rv != 0) { 4725 return ETIMEDOUT; 4726 } 4727 4728 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) { 4729 return EIO; 4730 } 4731 4732 return 0; 4733 } 4734 4735 static int 4736 ixl_set_rss_lut(struct ixl_softc *sc, uint8_t *lut, size_t lutlen) 4737 { 4738 struct ixl_dmamem *idm; 4739 struct ixl_atq iatq; 4740 struct ixl_aq_desc *iaq; 4741 struct ixl_aq_rss_lut_param *param; 4742 uint16_t vsi_id; 4743 uint8_t *data; 4744 size_t dmalen; 4745 int rv; 4746 4747 memset(&iatq, 0, sizeof(iatq)); 4748 iaq = &iatq.iatq_desc; 4749 idm = &sc->sc_aqbuf; 4750 4751 dmalen = MIN(lutlen, IXL_DMA_LEN(idm)); 4752 4753 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4754 (dmalen > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4755 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_LUT); 4756 iaq->iaq_datalen = htole16(dmalen); 4757 4758 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 4759 data = IXL_DMA_KVA(idm); 4760 memcpy(data, lut, dmalen); 4761 ixl_aq_dva(iaq, IXL_DMA_DVA(idm)); 4762 4763 param = (struct ixl_aq_rss_lut_param *)iaq->iaq_param; 4764 vsi_id = (sc->sc_vsi_number << IXL_AQ_RSSLUT_VSI_ID_SHIFT) | 4765 IXL_AQ_RSSLUT_VSI_VALID; 4766 param->vsi_id = htole16(vsi_id); 4767 param->flags = htole16(IXL_AQ_RSSLUT_TABLE_TYPE_PF << 4768 IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT); 4769 4770 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4771 IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE); 4772 4773 rv = ixl_atq_exec(sc, &iatq); 4774 4775 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4776 IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE); 4777 4778 if (rv != 0) { 4779 return ETIMEDOUT; 4780 } 4781 4782 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) { 4783 return EIO; 4784 } 4785 4786 return 0; 4787 } 4788 4789 static int 4790 ixl_register_rss_key(struct ixl_softc *sc) 4791 { 4792 uint32_t rss_seed[IXL_RSS_KEY_SIZE_REG]; 4793 int rv; 4794 size_t i; 4795 4796 ixl_get_default_rss_key(rss_seed, sizeof(rss_seed)); 4797 4798 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS)){ 4799 rv = ixl_set_rss_key(sc, (uint8_t*)rss_seed, 4800 sizeof(rss_seed)); 4801 } else { 4802 rv = 0; 4803 for (i = 0; i < IXL_RSS_KEY_SIZE_REG; i++) { 4804 ixl_wr_rx_csr(sc, I40E_PFQF_HKEY(i), rss_seed[i]); 4805 } 4806 } 4807 4808 return rv; 4809 } 4810 4811 static void 4812 ixl_register_rss_pctype(struct ixl_softc *sc) 4813 { 4814 uint64_t set_hena = 0; 4815 uint32_t hena0, hena1; 4816 4817 /* 4818 * We use TCP/UDP with IPv4/IPv6 by default. 4819 * Note: the device can not use just IP header in each 4820 * TCP/UDP packets for the RSS hash calculation. 4821 */ 4822 if (sc->sc_mac_type == I40E_MAC_X722) 4823 set_hena = IXL_RSS_HENA_DEFAULT_X722; 4824 else 4825 set_hena = IXL_RSS_HENA_DEFAULT_XL710; 4826 4827 hena0 = ixl_rd_rx_csr(sc, I40E_PFQF_HENA(0)); 4828 hena1 = ixl_rd_rx_csr(sc, I40E_PFQF_HENA(1)); 4829 4830 SET(hena0, set_hena); 4831 SET(hena1, set_hena >> 32); 4832 4833 ixl_wr_rx_csr(sc, I40E_PFQF_HENA(0), hena0); 4834 ixl_wr_rx_csr(sc, I40E_PFQF_HENA(1), hena1); 4835 } 4836 4837 static int 4838 ixl_register_rss_hlut(struct ixl_softc *sc) 4839 { 4840 unsigned int qid; 4841 uint8_t hlut_buf[512], lut_mask; 4842 uint32_t *hluts; 4843 size_t i, hluts_num; 4844 int rv; 4845 4846 lut_mask = (0x01 << sc->sc_rss_table_entry_width) - 1; 4847 4848 for (i = 0; i < sc->sc_rss_table_size; i++) { 4849 qid = i % sc->sc_nqueue_pairs; 4850 hlut_buf[i] = qid & lut_mask; 4851 } 4852 4853 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS)) { 4854 rv = ixl_set_rss_lut(sc, hlut_buf, sizeof(hlut_buf)); 4855 } else { 4856 rv = 0; 4857 hluts = (uint32_t *)hlut_buf; 4858 hluts_num = sc->sc_rss_table_size >> 2; 4859 for (i = 0; i < hluts_num; i++) { 4860 ixl_wr(sc, I40E_PFQF_HLUT(i), hluts[i]); 4861 } 4862 ixl_flush(sc); 4863 } 4864 4865 return rv; 4866 } 4867 4868 static void 4869 ixl_config_rss(struct ixl_softc *sc) 4870 { 4871 4872 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 4873 4874 ixl_register_rss_key(sc); 4875 ixl_register_rss_pctype(sc); 4876 ixl_register_rss_hlut(sc); 4877 } 4878 4879 static const struct ixl_phy_type * 4880 ixl_search_phy_type(uint8_t phy_type) 4881 { 4882 const struct ixl_phy_type *itype; 4883 uint64_t mask; 4884 unsigned int i; 4885 4886 if (phy_type >= 64) 4887 return NULL; 4888 4889 mask = 1ULL << phy_type; 4890 4891 for (i = 0; i < __arraycount(ixl_phy_type_map); i++) { 4892 itype = &ixl_phy_type_map[i]; 4893 4894 if (ISSET(itype->phy_type, mask)) 4895 return itype; 4896 } 4897 4898 return NULL; 4899 } 4900 4901 static uint64_t 4902 ixl_search_link_speed(uint8_t link_speed) 4903 { 4904 const struct ixl_speed_type *type; 4905 unsigned int i; 4906 4907 for (i = 0; i < __arraycount(ixl_speed_type_map); i++) { 4908 type = &ixl_speed_type_map[i]; 4909 4910 if (ISSET(type->dev_speed, link_speed)) 4911 return type->net_speed; 4912 } 4913 4914 return 0; 4915 } 4916 4917 static uint8_t 4918 ixl_search_baudrate(uint64_t baudrate) 4919 { 4920 const struct ixl_speed_type *type; 4921 unsigned int i; 4922 4923 for (i = 0; i < __arraycount(ixl_speed_type_map); i++) { 4924 type = &ixl_speed_type_map[i]; 4925 4926 if (type->net_speed == baudrate) { 4927 return type->dev_speed; 4928 } 4929 } 4930 4931 return 0; 4932 } 4933 4934 static int 4935 ixl_restart_an(struct ixl_softc *sc) 4936 { 4937 struct ixl_aq_desc iaq; 4938 4939 memset(&iaq, 0, sizeof(iaq)); 4940 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4941 iaq.iaq_param[0] = 4942 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4943 4944 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4945 aprint_error_dev(sc->sc_dev, "RESTART AN timeout\n"); 4946 return -1; 4947 } 4948 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4949 aprint_error_dev(sc->sc_dev, "RESTART AN error\n"); 4950 return -1; 4951 } 4952 4953 return 0; 4954 } 4955 4956 static int 4957 ixl_add_macvlan(struct ixl_softc *sc, const uint8_t *macaddr, 4958 uint16_t vlan, uint16_t flags) 4959 { 4960 struct ixl_aq_desc iaq; 4961 struct ixl_aq_add_macvlan *param; 4962 struct ixl_aq_add_macvlan_elem *elem; 4963 4964 memset(&iaq, 0, sizeof(iaq)); 4965 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4966 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4967 iaq.iaq_datalen = htole16(sizeof(*elem)); 4968 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4969 4970 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4971 param->num_addrs = htole16(1); 4972 param->seid0 = htole16(0x8000) | sc->sc_seid; 4973 param->seid1 = 0; 4974 param->seid2 = 0; 4975 4976 elem = IXL_DMA_KVA(&sc->sc_scratch); 4977 memset(elem, 0, sizeof(*elem)); 4978 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4979 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4980 elem->vlan = htole16(vlan); 4981 4982 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4983 return IXL_AQ_RC_EINVAL; 4984 } 4985 4986 switch (le16toh(iaq.iaq_retval)) { 4987 case IXL_AQ_RC_OK: 4988 break; 4989 case IXL_AQ_RC_ENOSPC: 4990 return ENOSPC; 4991 case IXL_AQ_RC_ENOENT: 4992 return ENOENT; 4993 case IXL_AQ_RC_EACCES: 4994 return EACCES; 4995 case IXL_AQ_RC_EEXIST: 4996 return EEXIST; 4997 case IXL_AQ_RC_EINVAL: 4998 return EINVAL; 4999 default: 5000 return EIO; 5001 } 5002 5003 return 0; 5004 } 5005 5006 static int 5007 ixl_remove_macvlan(struct ixl_softc *sc, const uint8_t *macaddr, 5008 uint16_t vlan, uint16_t flags) 5009 { 5010 struct ixl_aq_desc iaq; 5011 struct ixl_aq_remove_macvlan *param; 5012 struct ixl_aq_remove_macvlan_elem *elem; 5013 5014 memset(&iaq, 0, sizeof(iaq)); 5015 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5016 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 5017 iaq.iaq_datalen = htole16(sizeof(*elem)); 5018 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 5019 5020 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 5021 param->num_addrs = htole16(1); 5022 param->seid0 = htole16(0x8000) | sc->sc_seid; 5023 param->seid1 = 0; 5024 param->seid2 = 0; 5025 5026 elem = IXL_DMA_KVA(&sc->sc_scratch); 5027 memset(elem, 0, sizeof(*elem)); 5028 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 5029 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 5030 elem->vlan = htole16(vlan); 5031 5032 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 5033 return EINVAL; 5034 } 5035 5036 switch (le16toh(iaq.iaq_retval)) { 5037 case IXL_AQ_RC_OK: 5038 break; 5039 case IXL_AQ_RC_ENOENT: 5040 return ENOENT; 5041 case IXL_AQ_RC_EACCES: 5042 return EACCES; 5043 case IXL_AQ_RC_EINVAL: 5044 return EINVAL; 5045 default: 5046 return EIO; 5047 } 5048 5049 return 0; 5050 } 5051 5052 static int 5053 ixl_hmc(struct ixl_softc *sc) 5054 { 5055 struct { 5056 uint32_t count; 5057 uint32_t minsize; 5058 bus_size_t objsiz; 5059 bus_size_t setoff; 5060 bus_size_t setcnt; 5061 } regs[] = { 5062 { 5063 0, 5064 IXL_HMC_TXQ_MINSIZE, 5065 I40E_GLHMC_LANTXOBJSZ, 5066 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 5067 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 5068 }, 5069 { 5070 0, 5071 IXL_HMC_RXQ_MINSIZE, 5072 I40E_GLHMC_LANRXOBJSZ, 5073 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 5074 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 5075 }, 5076 { 5077 0, 5078 0, 5079 I40E_GLHMC_FCOEDDPOBJSZ, 5080 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 5081 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 5082 }, 5083 { 5084 0, 5085 0, 5086 I40E_GLHMC_FCOEFOBJSZ, 5087 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 5088 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 5089 }, 5090 }; 5091 struct ixl_hmc_entry *e; 5092 uint64_t size, dva; 5093 uint8_t *kva; 5094 uint64_t *sdpage; 5095 unsigned int i; 5096 int npages, tables; 5097 uint32_t reg; 5098 5099 CTASSERT(__arraycount(regs) <= __arraycount(sc->sc_hmc_entries)); 5100 5101 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 5102 ixl_rd(sc, I40E_GLHMC_LANQMAX); 5103 5104 size = 0; 5105 for (i = 0; i < __arraycount(regs); i++) { 5106 e = &sc->sc_hmc_entries[i]; 5107 5108 e->hmc_count = regs[i].count; 5109 reg = ixl_rd(sc, regs[i].objsiz); 5110 e->hmc_size = BIT_ULL(0x3F & reg); 5111 e->hmc_base = size; 5112 5113 if ((e->hmc_size * 8) < regs[i].minsize) { 5114 aprint_error_dev(sc->sc_dev, 5115 "kernel hmc entry is too big\n"); 5116 return -1; 5117 } 5118 5119 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 5120 } 5121 size = roundup(size, IXL_HMC_PGSIZE); 5122 npages = size / IXL_HMC_PGSIZE; 5123 5124 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 5125 5126 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 5127 aprint_error_dev(sc->sc_dev, 5128 "unable to allocate hmc pd memory\n"); 5129 return -1; 5130 } 5131 5132 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 5133 IXL_HMC_PGSIZE) != 0) { 5134 aprint_error_dev(sc->sc_dev, 5135 "unable to allocate hmc sd memory\n"); 5136 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 5137 return -1; 5138 } 5139 5140 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 5141 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 5142 5143 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 5144 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 5145 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5146 5147 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 5148 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 5149 memset(sdpage, 0, IXL_DMA_LEN(&sc->sc_hmc_sd)); 5150 5151 for (i = 0; (int)i < npages; i++) { 5152 *sdpage = htole64(dva | IXL_HMC_PDVALID); 5153 sdpage++; 5154 5155 dva += IXL_HMC_PGSIZE; 5156 } 5157 5158 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 5159 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 5160 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5161 5162 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 5163 for (i = 0; (int)i < tables; i++) { 5164 uint32_t count; 5165 5166 KASSERT(npages >= 0); 5167 5168 count = ((unsigned int)npages > IXL_HMC_PGS) ? 5169 IXL_HMC_PGS : (unsigned int)npages; 5170 5171 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 5172 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 5173 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 5174 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 5175 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 5176 ixl_wr(sc, I40E_PFHMC_SDCMD, 5177 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 5178 5179 npages -= IXL_HMC_PGS; 5180 dva += IXL_HMC_PGSIZE; 5181 } 5182 5183 for (i = 0; i < __arraycount(regs); i++) { 5184 e = &sc->sc_hmc_entries[i]; 5185 5186 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 5187 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 5188 } 5189 5190 return 0; 5191 } 5192 5193 static void 5194 ixl_hmc_free(struct ixl_softc *sc) 5195 { 5196 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 5197 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 5198 } 5199 5200 static void 5201 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 5202 unsigned int npacking) 5203 { 5204 uint8_t *dst = d; 5205 const uint8_t *src = s; 5206 unsigned int i; 5207 5208 for (i = 0; i < npacking; i++) { 5209 const struct ixl_hmc_pack *pack = &packing[i]; 5210 unsigned int offset = pack->lsb / 8; 5211 unsigned int align = pack->lsb % 8; 5212 const uint8_t *in = src + pack->offset; 5213 uint8_t *out = dst + offset; 5214 int width = pack->width; 5215 unsigned int inbits = 0; 5216 5217 if (align) { 5218 inbits = (*in++) << align; 5219 *out++ |= (inbits & 0xff); 5220 inbits >>= 8; 5221 5222 width -= 8 - align; 5223 } 5224 5225 while (width >= 8) { 5226 inbits |= (*in++) << align; 5227 *out++ = (inbits & 0xff); 5228 inbits >>= 8; 5229 5230 width -= 8; 5231 } 5232 5233 if (width > 0) { 5234 inbits |= (*in) << align; 5235 *out |= (inbits & ((1 << width) - 1)); 5236 } 5237 } 5238 } 5239 5240 static struct ixl_aq_buf * 5241 ixl_aqb_alloc(struct ixl_softc *sc) 5242 { 5243 struct ixl_aq_buf *aqb; 5244 5245 aqb = kmem_alloc(sizeof(*aqb), KM_SLEEP); 5246 5247 aqb->aqb_size = IXL_AQ_BUFLEN; 5248 5249 if (bus_dmamap_create(sc->sc_dmat, aqb->aqb_size, 1, 5250 aqb->aqb_size, 0, 5251 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &aqb->aqb_map) != 0) 5252 goto free; 5253 if (bus_dmamem_alloc(sc->sc_dmat, aqb->aqb_size, 5254 IXL_AQ_ALIGN, 0, &aqb->aqb_seg, 1, &aqb->aqb_nsegs, 5255 BUS_DMA_WAITOK) != 0) 5256 goto destroy; 5257 if (bus_dmamem_map(sc->sc_dmat, &aqb->aqb_seg, aqb->aqb_nsegs, 5258 aqb->aqb_size, &aqb->aqb_data, BUS_DMA_WAITOK) != 0) 5259 goto dma_free; 5260 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 5261 aqb->aqb_size, NULL, BUS_DMA_WAITOK) != 0) 5262 goto unmap; 5263 5264 return aqb; 5265 unmap: 5266 bus_dmamem_unmap(sc->sc_dmat, aqb->aqb_data, aqb->aqb_size); 5267 dma_free: 5268 bus_dmamem_free(sc->sc_dmat, &aqb->aqb_seg, 1); 5269 destroy: 5270 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 5271 free: 5272 kmem_free(aqb, sizeof(*aqb)); 5273 5274 return NULL; 5275 } 5276 5277 static void 5278 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 5279 { 5280 5281 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 5282 bus_dmamem_unmap(sc->sc_dmat, aqb->aqb_data, aqb->aqb_size); 5283 bus_dmamem_free(sc->sc_dmat, &aqb->aqb_seg, 1); 5284 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 5285 kmem_free(aqb, sizeof(*aqb)); 5286 } 5287 5288 static int 5289 ixl_arq_fill(struct ixl_softc *sc) 5290 { 5291 struct ixl_aq_buf *aqb; 5292 struct ixl_aq_desc *arq, *iaq; 5293 unsigned int prod = sc->sc_arq_prod; 5294 unsigned int n; 5295 int post = 0; 5296 5297 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 5298 IXL_AQ_NUM); 5299 arq = IXL_DMA_KVA(&sc->sc_arq); 5300 5301 if (__predict_false(n <= 0)) 5302 return 0; 5303 5304 do { 5305 aqb = sc->sc_arq_live[prod]; 5306 iaq = &arq[prod]; 5307 5308 if (aqb == NULL) { 5309 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 5310 if (aqb != NULL) { 5311 SIMPLEQ_REMOVE(&sc->sc_arq_idle, aqb, 5312 ixl_aq_buf, aqb_entry); 5313 } else if ((aqb = ixl_aqb_alloc(sc)) == NULL) { 5314 break; 5315 } 5316 5317 sc->sc_arq_live[prod] = aqb; 5318 memset(aqb->aqb_data, 0, aqb->aqb_size); 5319 5320 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 5321 aqb->aqb_size, BUS_DMASYNC_PREREAD); 5322 5323 iaq->iaq_flags = htole16(IXL_AQ_BUF | 5324 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? 5325 IXL_AQ_LB : 0)); 5326 iaq->iaq_opcode = 0; 5327 iaq->iaq_datalen = htole16(aqb->aqb_size); 5328 iaq->iaq_retval = 0; 5329 iaq->iaq_cookie = 0; 5330 iaq->iaq_param[0] = 0; 5331 iaq->iaq_param[1] = 0; 5332 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 5333 } 5334 5335 prod++; 5336 prod &= IXL_AQ_MASK; 5337 5338 post = 1; 5339 5340 } while (--n); 5341 5342 if (post) { 5343 sc->sc_arq_prod = prod; 5344 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 5345 } 5346 5347 return post; 5348 } 5349 5350 static void 5351 ixl_arq_unfill(struct ixl_softc *sc) 5352 { 5353 struct ixl_aq_buf *aqb; 5354 unsigned int i; 5355 5356 for (i = 0; i < __arraycount(sc->sc_arq_live); i++) { 5357 aqb = sc->sc_arq_live[i]; 5358 if (aqb == NULL) 5359 continue; 5360 5361 sc->sc_arq_live[i] = NULL; 5362 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 5363 BUS_DMASYNC_POSTREAD); 5364 ixl_aqb_free(sc, aqb); 5365 } 5366 5367 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle)) != NULL) { 5368 SIMPLEQ_REMOVE(&sc->sc_arq_idle, aqb, 5369 ixl_aq_buf, aqb_entry); 5370 ixl_aqb_free(sc, aqb); 5371 } 5372 } 5373 5374 static void 5375 ixl_clear_hw(struct ixl_softc *sc) 5376 { 5377 uint32_t num_queues, base_queue; 5378 uint32_t num_pf_int; 5379 uint32_t num_vf_int; 5380 uint32_t num_vfs; 5381 uint32_t i, j; 5382 uint32_t val; 5383 uint32_t eol = 0x7ff; 5384 5385 /* get number of interrupts, queues, and vfs */ 5386 val = ixl_rd(sc, I40E_GLPCI_CNF2); 5387 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 5388 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 5389 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 5390 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 5391 5392 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 5393 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 5394 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 5395 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 5396 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 5397 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 5398 num_queues = (j - base_queue) + 1; 5399 else 5400 num_queues = 0; 5401 5402 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 5403 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 5404 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 5405 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 5406 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 5407 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 5408 num_vfs = (j - i) + 1; 5409 else 5410 num_vfs = 0; 5411 5412 /* stop all the interrupts */ 5413 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 5414 ixl_flush(sc); 5415 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 5416 for (i = 0; i < num_pf_int - 2; i++) 5417 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 5418 ixl_flush(sc); 5419 5420 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 5421 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5422 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 5423 for (i = 0; i < num_pf_int - 2; i++) 5424 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 5425 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5426 for (i = 0; i < num_vfs; i++) 5427 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 5428 for (i = 0; i < num_vf_int - 2; i++) 5429 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 5430 5431 /* warn the HW of the coming Tx disables */ 5432 for (i = 0; i < num_queues; i++) { 5433 uint32_t abs_queue_idx = base_queue + i; 5434 uint32_t reg_block = 0; 5435 5436 if (abs_queue_idx >= 128) { 5437 reg_block = abs_queue_idx / 128; 5438 abs_queue_idx %= 128; 5439 } 5440 5441 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 5442 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 5443 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 5444 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 5445 5446 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 5447 } 5448 delaymsec(400); 5449 5450 /* stop all the queues */ 5451 for (i = 0; i < num_queues; i++) { 5452 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 5453 ixl_wr(sc, I40E_QTX_ENA(i), 0); 5454 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 5455 ixl_wr(sc, I40E_QRX_ENA(i), 0); 5456 } 5457 5458 /* short wait for all queue disables to settle */ 5459 delaymsec(50); 5460 } 5461 5462 static int 5463 ixl_pf_reset(struct ixl_softc *sc) 5464 { 5465 uint32_t cnt = 0; 5466 uint32_t cnt1 = 0; 5467 uint32_t reg = 0, reg0 = 0; 5468 uint32_t grst_del; 5469 5470 /* 5471 * Poll for Global Reset steady state in case of recent GRST. 5472 * The grst delay value is in 100ms units, and we'll wait a 5473 * couple counts longer to be sure we don't just miss the end. 5474 */ 5475 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 5476 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 5477 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 5478 5479 grst_del = grst_del * 20; 5480 5481 for (cnt = 0; cnt < grst_del; cnt++) { 5482 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 5483 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 5484 break; 5485 delaymsec(100); 5486 } 5487 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5488 aprint_error(", Global reset polling failed to complete\n"); 5489 return -1; 5490 } 5491 5492 /* Now Wait for the FW to be ready */ 5493 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 5494 reg = ixl_rd(sc, I40E_GLNVM_ULD); 5495 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5496 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 5497 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5498 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 5499 break; 5500 5501 delaymsec(10); 5502 } 5503 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5504 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 5505 aprint_error(", wait for FW Reset complete timed out " 5506 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 5507 return -1; 5508 } 5509 5510 /* 5511 * If there was a Global Reset in progress when we got here, 5512 * we don't need to do the PF Reset 5513 */ 5514 if (cnt == 0) { 5515 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5516 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 5517 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 5518 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5519 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 5520 break; 5521 delaymsec(1); 5522 5523 reg0 = ixl_rd(sc, I40E_GLGEN_RSTAT); 5524 if (reg0 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5525 aprint_error(", Core reset upcoming." 5526 " Skipping PF reset reset request\n"); 5527 return -1; 5528 } 5529 } 5530 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 5531 aprint_error(", PF reset polling failed to complete" 5532 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 5533 return -1; 5534 } 5535 } 5536 5537 return 0; 5538 } 5539 5540 static int 5541 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 5542 bus_size_t size, bus_size_t align) 5543 { 5544 ixm->ixm_size = size; 5545 5546 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 5547 ixm->ixm_size, 0, 5548 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 5549 &ixm->ixm_map) != 0) 5550 return 1; 5551 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5552 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5553 BUS_DMA_WAITOK) != 0) 5554 goto destroy; 5555 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5556 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5557 goto free; 5558 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5559 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5560 goto unmap; 5561 5562 memset(ixm->ixm_kva, 0, ixm->ixm_size); 5563 5564 return 0; 5565 unmap: 5566 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5567 free: 5568 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5569 destroy: 5570 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5571 return 1; 5572 } 5573 5574 static void 5575 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5576 { 5577 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5578 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5579 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5580 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5581 } 5582 5583 static int 5584 ixl_setup_vlan_hwfilter(struct ixl_softc *sc) 5585 { 5586 struct ethercom *ec = &sc->sc_ec; 5587 struct vlanid_list *vlanidp; 5588 int rv; 5589 5590 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 5591 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 5592 ixl_remove_macvlan(sc, etherbroadcastaddr, 0, 5593 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 5594 5595 rv = ixl_add_macvlan(sc, sc->sc_enaddr, 0, 5596 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5597 if (rv != 0) 5598 return rv; 5599 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 0, 5600 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5601 if (rv != 0) 5602 return rv; 5603 5604 ETHER_LOCK(ec); 5605 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 5606 rv = ixl_add_macvlan(sc, sc->sc_enaddr, 5607 vlanidp->vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5608 if (rv != 0) 5609 break; 5610 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 5611 vlanidp->vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5612 if (rv != 0) 5613 break; 5614 } 5615 ETHER_UNLOCK(ec); 5616 5617 return rv; 5618 } 5619 5620 static void 5621 ixl_teardown_vlan_hwfilter(struct ixl_softc *sc) 5622 { 5623 struct vlanid_list *vlanidp; 5624 struct ethercom *ec = &sc->sc_ec; 5625 5626 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 5627 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5628 ixl_remove_macvlan(sc, etherbroadcastaddr, 0, 5629 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5630 5631 ETHER_LOCK(ec); 5632 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 5633 ixl_remove_macvlan(sc, sc->sc_enaddr, 5634 vlanidp->vid, IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5635 ixl_remove_macvlan(sc, etherbroadcastaddr, 5636 vlanidp->vid, IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5637 } 5638 ETHER_UNLOCK(ec); 5639 5640 ixl_add_macvlan(sc, sc->sc_enaddr, 0, 5641 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 5642 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 5643 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 5644 } 5645 5646 static int 5647 ixl_update_macvlan(struct ixl_softc *sc) 5648 { 5649 int rv = 0; 5650 int next_ec_capenable = sc->sc_ec.ec_capenable; 5651 5652 if (ISSET(next_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 5653 rv = ixl_setup_vlan_hwfilter(sc); 5654 if (rv != 0) 5655 ixl_teardown_vlan_hwfilter(sc); 5656 } else { 5657 ixl_teardown_vlan_hwfilter(sc); 5658 } 5659 5660 return rv; 5661 } 5662 5663 static int 5664 ixl_ifflags_cb(struct ethercom *ec) 5665 { 5666 struct ifnet *ifp = &ec->ec_if; 5667 struct ixl_softc *sc = ifp->if_softc; 5668 int rv, change; 5669 5670 mutex_enter(&sc->sc_cfg_lock); 5671 5672 change = ec->ec_capenable ^ sc->sc_cur_ec_capenable; 5673 5674 if (ISSET(change, ETHERCAP_VLAN_HWTAGGING)) { 5675 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING; 5676 rv = ENETRESET; 5677 goto out; 5678 } 5679 5680 if (ISSET(change, ETHERCAP_VLAN_HWFILTER)) { 5681 rv = ixl_update_macvlan(sc); 5682 if (rv == 0) { 5683 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER; 5684 } else { 5685 CLR(ec->ec_capenable, ETHERCAP_VLAN_HWFILTER); 5686 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 5687 } 5688 } 5689 5690 rv = ixl_iff(sc); 5691 out: 5692 mutex_exit(&sc->sc_cfg_lock); 5693 5694 return rv; 5695 } 5696 5697 static int 5698 ixl_set_link_status(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 5699 { 5700 const struct ixl_aq_link_status *status; 5701 const struct ixl_phy_type *itype; 5702 5703 uint64_t ifm_active = IFM_ETHER; 5704 uint64_t ifm_status = IFM_AVALID; 5705 int link_state = LINK_STATE_DOWN; 5706 uint64_t baudrate = 0; 5707 5708 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 5709 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) { 5710 ifm_active |= IFM_NONE; 5711 goto done; 5712 } 5713 5714 ifm_active |= IFM_FDX; 5715 ifm_status |= IFM_ACTIVE; 5716 link_state = LINK_STATE_UP; 5717 5718 itype = ixl_search_phy_type(status->phy_type); 5719 if (itype != NULL) 5720 ifm_active |= itype->ifm_type; 5721 5722 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 5723 ifm_active |= IFM_ETH_TXPAUSE; 5724 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 5725 ifm_active |= IFM_ETH_RXPAUSE; 5726 5727 baudrate = ixl_search_link_speed(status->link_speed); 5728 5729 done: 5730 sc->sc_media_active = ifm_active; 5731 sc->sc_media_status = ifm_status; 5732 5733 sc->sc_ec.ec_if.if_baudrate = baudrate; 5734 5735 return link_state; 5736 } 5737 5738 static int 5739 ixl_establish_intx(struct ixl_softc *sc) 5740 { 5741 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 5742 pci_intr_handle_t *intr; 5743 char xnamebuf[32]; 5744 char intrbuf[PCI_INTRSTR_LEN]; 5745 char const *intrstr; 5746 5747 KASSERT(sc->sc_nintrs == 1); 5748 5749 intr = &sc->sc_ihp[0]; 5750 5751 intrstr = pci_intr_string(pc, *intr, intrbuf, sizeof(intrbuf)); 5752 snprintf(xnamebuf, sizeof(xnamebuf), "%s:legacy", 5753 device_xname(sc->sc_dev)); 5754 5755 sc->sc_ihs[0] = pci_intr_establish_xname(pc, *intr, IPL_NET, ixl_intr, 5756 sc, xnamebuf); 5757 5758 if (sc->sc_ihs[0] == NULL) { 5759 aprint_error_dev(sc->sc_dev, 5760 "unable to establish interrupt at %s\n", intrstr); 5761 return -1; 5762 } 5763 5764 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 5765 return 0; 5766 } 5767 5768 static int 5769 ixl_establish_msix(struct ixl_softc *sc) 5770 { 5771 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 5772 kcpuset_t *affinity; 5773 unsigned int vector = 0; 5774 unsigned int i; 5775 int affinity_to, r; 5776 char xnamebuf[32]; 5777 char intrbuf[PCI_INTRSTR_LEN]; 5778 char const *intrstr; 5779 5780 kcpuset_create(&affinity, false); 5781 5782 /* the "other" intr is mapped to vector 0 */ 5783 vector = 0; 5784 intrstr = pci_intr_string(pc, sc->sc_ihp[vector], 5785 intrbuf, sizeof(intrbuf)); 5786 snprintf(xnamebuf, sizeof(xnamebuf), "%s others", 5787 device_xname(sc->sc_dev)); 5788 sc->sc_ihs[vector] = pci_intr_establish_xname(pc, 5789 sc->sc_ihp[vector], IPL_NET, ixl_other_intr, 5790 sc, xnamebuf); 5791 if (sc->sc_ihs[vector] == NULL) { 5792 aprint_error_dev(sc->sc_dev, 5793 "unable to establish interrupt at %s\n", intrstr); 5794 goto fail; 5795 } 5796 5797 aprint_normal_dev(sc->sc_dev, "other interrupt at %s", intrstr); 5798 5799 affinity_to = ncpu > (int)sc->sc_nqueue_pairs_max ? 1 : 0; 5800 affinity_to = (affinity_to + sc->sc_nqueue_pairs_max) % ncpu; 5801 5802 kcpuset_zero(affinity); 5803 kcpuset_set(affinity, affinity_to); 5804 r = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 5805 if (r == 0) { 5806 aprint_normal(", affinity to %u", affinity_to); 5807 } 5808 aprint_normal("\n"); 5809 vector++; 5810 5811 sc->sc_msix_vector_queue = vector; 5812 affinity_to = ncpu > (int)sc->sc_nqueue_pairs_max ? 1 : 0; 5813 5814 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 5815 intrstr = pci_intr_string(pc, sc->sc_ihp[vector], 5816 intrbuf, sizeof(intrbuf)); 5817 snprintf(xnamebuf, sizeof(xnamebuf), "%s TXRX%d", 5818 device_xname(sc->sc_dev), i); 5819 5820 sc->sc_ihs[vector] = pci_intr_establish_xname(pc, 5821 sc->sc_ihp[vector], IPL_NET, ixl_queue_intr, 5822 (void *)&sc->sc_qps[i], xnamebuf); 5823 5824 if (sc->sc_ihs[vector] == NULL) { 5825 aprint_error_dev(sc->sc_dev, 5826 "unable to establish interrupt at %s\n", intrstr); 5827 goto fail; 5828 } 5829 5830 aprint_normal_dev(sc->sc_dev, 5831 "for TXRX%d interrupt at %s",i , intrstr); 5832 5833 kcpuset_zero(affinity); 5834 kcpuset_set(affinity, affinity_to); 5835 r = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 5836 if (r == 0) { 5837 aprint_normal(", affinity to %u", affinity_to); 5838 affinity_to = (affinity_to + 1) % ncpu; 5839 } 5840 aprint_normal("\n"); 5841 vector++; 5842 } 5843 5844 kcpuset_destroy(affinity); 5845 5846 return 0; 5847 fail: 5848 for (i = 0; i < vector; i++) { 5849 pci_intr_disestablish(pc, sc->sc_ihs[i]); 5850 } 5851 5852 sc->sc_msix_vector_queue = 0; 5853 sc->sc_msix_vector_queue = 0; 5854 kcpuset_destroy(affinity); 5855 5856 return -1; 5857 } 5858 5859 static void 5860 ixl_config_queue_intr(struct ixl_softc *sc) 5861 { 5862 unsigned int i, vector; 5863 5864 if (sc->sc_intrtype == PCI_INTR_TYPE_MSIX) { 5865 vector = sc->sc_msix_vector_queue; 5866 } else { 5867 vector = I40E_INTR_NOTX_INTR; 5868 5869 ixl_wr(sc, I40E_PFINT_LNKLST0, 5870 (I40E_INTR_NOTX_QUEUE << 5871 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 5872 (I40E_QUEUE_TYPE_RX << 5873 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 5874 } 5875 5876 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 5877 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 0); 5878 ixl_flush(sc); 5879 5880 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 5881 ((i) << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 5882 (I40E_QUEUE_TYPE_RX << 5883 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 5884 5885 ixl_wr(sc, I40E_QINT_RQCTL(i), 5886 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 5887 (I40E_ITR_INDEX_RX << 5888 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 5889 (I40E_INTR_NOTX_RX_QUEUE << 5890 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 5891 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 5892 (I40E_QUEUE_TYPE_TX << 5893 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 5894 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 5895 5896 ixl_wr(sc, I40E_QINT_TQCTL(i), 5897 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 5898 (I40E_ITR_INDEX_TX << 5899 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 5900 (I40E_INTR_NOTX_TX_QUEUE << 5901 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 5902 (I40E_QUEUE_TYPE_EOL << 5903 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 5904 (I40E_QUEUE_TYPE_RX << 5905 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 5906 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 5907 5908 if (sc->sc_intrtype == PCI_INTR_TYPE_MSIX) 5909 vector++; 5910 } 5911 ixl_flush(sc); 5912 5913 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_RX), 0x7a); 5914 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_TX), 0x7a); 5915 ixl_flush(sc); 5916 } 5917 5918 static void 5919 ixl_config_other_intr(struct ixl_softc *sc) 5920 { 5921 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 5922 (void)ixl_rd(sc, I40E_PFINT_ICR0); 5923 5924 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 5925 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 5926 I40E_PFINT_ICR0_ENA_GRST_MASK | 5927 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 5928 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 5929 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | 5930 I40E_PFINT_ICR0_ENA_VFLR_MASK | 5931 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | 5932 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | 5933 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK); 5934 5935 ixl_wr(sc, I40E_PFINT_LNKLST0, 0x7FF); 5936 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_OTHER), 0); 5937 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 5938 (I40E_ITR_INDEX_OTHER << 5939 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)); 5940 ixl_flush(sc); 5941 } 5942 5943 static int 5944 ixl_setup_interrupts(struct ixl_softc *sc) 5945 { 5946 struct pci_attach_args *pa = &sc->sc_pa; 5947 pci_intr_type_t max_type, intr_type; 5948 int counts[PCI_INTR_TYPE_SIZE]; 5949 int error; 5950 unsigned int i; 5951 bool retry; 5952 5953 memset(counts, 0, sizeof(counts)); 5954 max_type = PCI_INTR_TYPE_MSIX; 5955 /* QPs + other interrupt */ 5956 counts[PCI_INTR_TYPE_MSIX] = sc->sc_nqueue_pairs_max + 1; 5957 counts[PCI_INTR_TYPE_INTX] = 1; 5958 5959 if (ixl_param_nomsix) 5960 counts[PCI_INTR_TYPE_MSIX] = 0; 5961 5962 do { 5963 retry = false; 5964 error = pci_intr_alloc(pa, &sc->sc_ihp, counts, max_type); 5965 if (error != 0) { 5966 aprint_error_dev(sc->sc_dev, 5967 "couldn't map interrupt\n"); 5968 break; 5969 } 5970 5971 intr_type = pci_intr_type(pa->pa_pc, sc->sc_ihp[0]); 5972 sc->sc_nintrs = counts[intr_type]; 5973 KASSERT(sc->sc_nintrs > 0); 5974 5975 for (i = 0; i < sc->sc_nintrs; i++) { 5976 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[i], 5977 PCI_INTR_MPSAFE, true); 5978 } 5979 5980 sc->sc_ihs = kmem_alloc(sizeof(sc->sc_ihs[0]) * sc->sc_nintrs, 5981 KM_SLEEP); 5982 5983 if (intr_type == PCI_INTR_TYPE_MSIX) { 5984 error = ixl_establish_msix(sc); 5985 if (error) { 5986 counts[PCI_INTR_TYPE_MSIX] = 0; 5987 retry = true; 5988 } 5989 } else if (intr_type == PCI_INTR_TYPE_INTX) { 5990 error = ixl_establish_intx(sc); 5991 } else { 5992 error = -1; 5993 } 5994 5995 if (error) { 5996 kmem_free(sc->sc_ihs, 5997 sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 5998 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 5999 } else { 6000 sc->sc_intrtype = intr_type; 6001 } 6002 } while (retry); 6003 6004 return error; 6005 } 6006 6007 static void 6008 ixl_teardown_interrupts(struct ixl_softc *sc) 6009 { 6010 struct pci_attach_args *pa = &sc->sc_pa; 6011 unsigned int i; 6012 6013 for (i = 0; i < sc->sc_nintrs; i++) { 6014 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[i]); 6015 } 6016 6017 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 6018 6019 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 6020 sc->sc_ihs = NULL; 6021 sc->sc_nintrs = 0; 6022 } 6023 6024 static int 6025 ixl_setup_stats(struct ixl_softc *sc) 6026 { 6027 struct ixl_queue_pair *qp; 6028 struct ixl_tx_ring *txr; 6029 struct ixl_rx_ring *rxr; 6030 struct ixl_stats_counters *isc; 6031 unsigned int i; 6032 6033 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 6034 qp = &sc->sc_qps[i]; 6035 txr = qp->qp_txr; 6036 rxr = qp->qp_rxr; 6037 6038 evcnt_attach_dynamic(&txr->txr_defragged, EVCNT_TYPE_MISC, 6039 NULL, qp->qp_name, "m_defrag successed"); 6040 evcnt_attach_dynamic(&txr->txr_defrag_failed, EVCNT_TYPE_MISC, 6041 NULL, qp->qp_name, "m_defrag_failed"); 6042 evcnt_attach_dynamic(&txr->txr_pcqdrop, EVCNT_TYPE_MISC, 6043 NULL, qp->qp_name, "Dropped in pcq"); 6044 evcnt_attach_dynamic(&txr->txr_transmitdef, EVCNT_TYPE_MISC, 6045 NULL, qp->qp_name, "Deferred transmit"); 6046 evcnt_attach_dynamic(&txr->txr_intr, EVCNT_TYPE_INTR, 6047 NULL, qp->qp_name, "Interrupt on queue"); 6048 evcnt_attach_dynamic(&txr->txr_defer, EVCNT_TYPE_MISC, 6049 NULL, qp->qp_name, "Handled queue in softint/workqueue"); 6050 6051 evcnt_attach_dynamic(&rxr->rxr_mgethdr_failed, EVCNT_TYPE_MISC, 6052 NULL, qp->qp_name, "MGETHDR failed"); 6053 evcnt_attach_dynamic(&rxr->rxr_mgetcl_failed, EVCNT_TYPE_MISC, 6054 NULL, qp->qp_name, "MCLGET failed"); 6055 evcnt_attach_dynamic(&rxr->rxr_mbuf_load_failed, 6056 EVCNT_TYPE_MISC, NULL, qp->qp_name, 6057 "bus_dmamap_load_mbuf failed"); 6058 evcnt_attach_dynamic(&rxr->rxr_intr, EVCNT_TYPE_INTR, 6059 NULL, qp->qp_name, "Interrupt on queue"); 6060 evcnt_attach_dynamic(&rxr->rxr_defer, EVCNT_TYPE_MISC, 6061 NULL, qp->qp_name, "Handled queue in softint/workqueue"); 6062 } 6063 6064 evcnt_attach_dynamic(&sc->sc_event_atq, EVCNT_TYPE_INTR, 6065 NULL, device_xname(sc->sc_dev), "Interrupt for other events"); 6066 evcnt_attach_dynamic(&sc->sc_event_link, EVCNT_TYPE_MISC, 6067 NULL, device_xname(sc->sc_dev), "Link status event"); 6068 evcnt_attach_dynamic(&sc->sc_event_ecc_err, EVCNT_TYPE_MISC, 6069 NULL, device_xname(sc->sc_dev), "ECC error"); 6070 evcnt_attach_dynamic(&sc->sc_event_pci_exception, EVCNT_TYPE_MISC, 6071 NULL, device_xname(sc->sc_dev), "PCI exception"); 6072 evcnt_attach_dynamic(&sc->sc_event_crit_err, EVCNT_TYPE_MISC, 6073 NULL, device_xname(sc->sc_dev), "Critical error"); 6074 6075 isc = &sc->sc_stats_counters; 6076 evcnt_attach_dynamic(&isc->isc_crc_errors, EVCNT_TYPE_MISC, 6077 NULL, device_xname(sc->sc_dev), "CRC errors"); 6078 evcnt_attach_dynamic(&isc->isc_illegal_bytes, EVCNT_TYPE_MISC, 6079 NULL, device_xname(sc->sc_dev), "Illegal bytes"); 6080 evcnt_attach_dynamic(&isc->isc_mac_local_faults, EVCNT_TYPE_MISC, 6081 NULL, device_xname(sc->sc_dev), "Mac local faults"); 6082 evcnt_attach_dynamic(&isc->isc_mac_remote_faults, EVCNT_TYPE_MISC, 6083 NULL, device_xname(sc->sc_dev), "Mac remote faults"); 6084 evcnt_attach_dynamic(&isc->isc_link_xon_rx, EVCNT_TYPE_MISC, 6085 NULL, device_xname(sc->sc_dev), "Rx xon"); 6086 evcnt_attach_dynamic(&isc->isc_link_xon_tx, EVCNT_TYPE_MISC, 6087 NULL, device_xname(sc->sc_dev), "Tx xon"); 6088 evcnt_attach_dynamic(&isc->isc_link_xoff_rx, EVCNT_TYPE_MISC, 6089 NULL, device_xname(sc->sc_dev), "Rx xoff"); 6090 evcnt_attach_dynamic(&isc->isc_link_xoff_tx, EVCNT_TYPE_MISC, 6091 NULL, device_xname(sc->sc_dev), "Tx xoff"); 6092 evcnt_attach_dynamic(&isc->isc_rx_fragments, EVCNT_TYPE_MISC, 6093 NULL, device_xname(sc->sc_dev), "Rx fragments"); 6094 evcnt_attach_dynamic(&isc->isc_rx_jabber, EVCNT_TYPE_MISC, 6095 NULL, device_xname(sc->sc_dev), "Rx jabber"); 6096 6097 evcnt_attach_dynamic(&isc->isc_rx_size_64, EVCNT_TYPE_MISC, 6098 NULL, device_xname(sc->sc_dev), "Rx size 64"); 6099 evcnt_attach_dynamic(&isc->isc_rx_size_127, EVCNT_TYPE_MISC, 6100 NULL, device_xname(sc->sc_dev), "Rx size 127"); 6101 evcnt_attach_dynamic(&isc->isc_rx_size_255, EVCNT_TYPE_MISC, 6102 NULL, device_xname(sc->sc_dev), "Rx size 255"); 6103 evcnt_attach_dynamic(&isc->isc_rx_size_511, EVCNT_TYPE_MISC, 6104 NULL, device_xname(sc->sc_dev), "Rx size 511"); 6105 evcnt_attach_dynamic(&isc->isc_rx_size_1023, EVCNT_TYPE_MISC, 6106 NULL, device_xname(sc->sc_dev), "Rx size 1023"); 6107 evcnt_attach_dynamic(&isc->isc_rx_size_1522, EVCNT_TYPE_MISC, 6108 NULL, device_xname(sc->sc_dev), "Rx size 1522"); 6109 evcnt_attach_dynamic(&isc->isc_rx_size_big, EVCNT_TYPE_MISC, 6110 NULL, device_xname(sc->sc_dev), "Rx jumbo packets"); 6111 evcnt_attach_dynamic(&isc->isc_rx_undersize, EVCNT_TYPE_MISC, 6112 NULL, device_xname(sc->sc_dev), "Rx under size"); 6113 evcnt_attach_dynamic(&isc->isc_rx_oversize, EVCNT_TYPE_MISC, 6114 NULL, device_xname(sc->sc_dev), "Rx over size"); 6115 6116 evcnt_attach_dynamic(&isc->isc_rx_bytes, EVCNT_TYPE_MISC, 6117 NULL, device_xname(sc->sc_dev), "Rx bytes / port"); 6118 evcnt_attach_dynamic(&isc->isc_rx_discards, EVCNT_TYPE_MISC, 6119 NULL, device_xname(sc->sc_dev), "Rx discards / port"); 6120 evcnt_attach_dynamic(&isc->isc_rx_unicast, EVCNT_TYPE_MISC, 6121 NULL, device_xname(sc->sc_dev), "Rx unicast / port"); 6122 evcnt_attach_dynamic(&isc->isc_rx_multicast, EVCNT_TYPE_MISC, 6123 NULL, device_xname(sc->sc_dev), "Rx multicast / port"); 6124 evcnt_attach_dynamic(&isc->isc_rx_broadcast, EVCNT_TYPE_MISC, 6125 NULL, device_xname(sc->sc_dev), "Rx broadcast / port"); 6126 6127 evcnt_attach_dynamic(&isc->isc_vsi_rx_bytes, EVCNT_TYPE_MISC, 6128 NULL, device_xname(sc->sc_dev), "Rx bytes / vsi"); 6129 evcnt_attach_dynamic(&isc->isc_vsi_rx_discards, EVCNT_TYPE_MISC, 6130 NULL, device_xname(sc->sc_dev), "Rx discard / vsi"); 6131 evcnt_attach_dynamic(&isc->isc_vsi_rx_unicast, EVCNT_TYPE_MISC, 6132 NULL, device_xname(sc->sc_dev), "Rx unicast / vsi"); 6133 evcnt_attach_dynamic(&isc->isc_vsi_rx_multicast, EVCNT_TYPE_MISC, 6134 NULL, device_xname(sc->sc_dev), "Rx multicast / vsi"); 6135 evcnt_attach_dynamic(&isc->isc_vsi_rx_broadcast, EVCNT_TYPE_MISC, 6136 NULL, device_xname(sc->sc_dev), "Rx broadcast / vsi"); 6137 6138 evcnt_attach_dynamic(&isc->isc_tx_size_64, EVCNT_TYPE_MISC, 6139 NULL, device_xname(sc->sc_dev), "Tx size 64"); 6140 evcnt_attach_dynamic(&isc->isc_tx_size_127, EVCNT_TYPE_MISC, 6141 NULL, device_xname(sc->sc_dev), "Tx size 127"); 6142 evcnt_attach_dynamic(&isc->isc_tx_size_255, EVCNT_TYPE_MISC, 6143 NULL, device_xname(sc->sc_dev), "Tx size 255"); 6144 evcnt_attach_dynamic(&isc->isc_tx_size_511, EVCNT_TYPE_MISC, 6145 NULL, device_xname(sc->sc_dev), "Tx size 511"); 6146 evcnt_attach_dynamic(&isc->isc_tx_size_1023, EVCNT_TYPE_MISC, 6147 NULL, device_xname(sc->sc_dev), "Tx size 1023"); 6148 evcnt_attach_dynamic(&isc->isc_tx_size_1522, EVCNT_TYPE_MISC, 6149 NULL, device_xname(sc->sc_dev), "Tx size 1522"); 6150 evcnt_attach_dynamic(&isc->isc_tx_size_big, EVCNT_TYPE_MISC, 6151 NULL, device_xname(sc->sc_dev), "Tx jumbo packets"); 6152 6153 evcnt_attach_dynamic(&isc->isc_tx_bytes, EVCNT_TYPE_MISC, 6154 NULL, device_xname(sc->sc_dev), "Tx bytes / port"); 6155 evcnt_attach_dynamic(&isc->isc_tx_dropped_link_down, EVCNT_TYPE_MISC, 6156 NULL, device_xname(sc->sc_dev), 6157 "Tx dropped due to link down / port"); 6158 evcnt_attach_dynamic(&isc->isc_tx_unicast, EVCNT_TYPE_MISC, 6159 NULL, device_xname(sc->sc_dev), "Tx unicast / port"); 6160 evcnt_attach_dynamic(&isc->isc_tx_multicast, EVCNT_TYPE_MISC, 6161 NULL, device_xname(sc->sc_dev), "Tx multicast / port"); 6162 evcnt_attach_dynamic(&isc->isc_tx_broadcast, EVCNT_TYPE_MISC, 6163 NULL, device_xname(sc->sc_dev), "Tx broadcast / port"); 6164 6165 evcnt_attach_dynamic(&isc->isc_vsi_tx_bytes, EVCNT_TYPE_MISC, 6166 NULL, device_xname(sc->sc_dev), "Tx bytes / vsi"); 6167 evcnt_attach_dynamic(&isc->isc_vsi_tx_errors, EVCNT_TYPE_MISC, 6168 NULL, device_xname(sc->sc_dev), "Tx errors / vsi"); 6169 evcnt_attach_dynamic(&isc->isc_vsi_tx_unicast, EVCNT_TYPE_MISC, 6170 NULL, device_xname(sc->sc_dev), "Tx unicast / vsi"); 6171 evcnt_attach_dynamic(&isc->isc_vsi_tx_multicast, EVCNT_TYPE_MISC, 6172 NULL, device_xname(sc->sc_dev), "Tx multicast / vsi"); 6173 evcnt_attach_dynamic(&isc->isc_vsi_tx_broadcast, EVCNT_TYPE_MISC, 6174 NULL, device_xname(sc->sc_dev), "Tx broadcast / vsi"); 6175 6176 sc->sc_stats_intval = ixl_param_stats_interval; 6177 callout_init(&sc->sc_stats_callout, CALLOUT_MPSAFE); 6178 callout_setfunc(&sc->sc_stats_callout, ixl_stats_callout, sc); 6179 ixl_work_set(&sc->sc_stats_task, ixl_stats_update, sc); 6180 6181 return 0; 6182 } 6183 6184 static void 6185 ixl_teardown_stats(struct ixl_softc *sc) 6186 { 6187 struct ixl_tx_ring *txr; 6188 struct ixl_rx_ring *rxr; 6189 struct ixl_stats_counters *isc; 6190 unsigned int i; 6191 6192 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 6193 txr = sc->sc_qps[i].qp_txr; 6194 rxr = sc->sc_qps[i].qp_rxr; 6195 6196 evcnt_detach(&txr->txr_defragged); 6197 evcnt_detach(&txr->txr_defrag_failed); 6198 evcnt_detach(&txr->txr_pcqdrop); 6199 evcnt_detach(&txr->txr_transmitdef); 6200 evcnt_detach(&txr->txr_intr); 6201 evcnt_detach(&txr->txr_defer); 6202 6203 evcnt_detach(&rxr->rxr_mgethdr_failed); 6204 evcnt_detach(&rxr->rxr_mgetcl_failed); 6205 evcnt_detach(&rxr->rxr_mbuf_load_failed); 6206 evcnt_detach(&rxr->rxr_intr); 6207 evcnt_detach(&rxr->rxr_defer); 6208 } 6209 6210 isc = &sc->sc_stats_counters; 6211 evcnt_detach(&isc->isc_crc_errors); 6212 evcnt_detach(&isc->isc_illegal_bytes); 6213 evcnt_detach(&isc->isc_mac_local_faults); 6214 evcnt_detach(&isc->isc_mac_remote_faults); 6215 evcnt_detach(&isc->isc_link_xon_rx); 6216 evcnt_detach(&isc->isc_link_xon_tx); 6217 evcnt_detach(&isc->isc_link_xoff_rx); 6218 evcnt_detach(&isc->isc_link_xoff_tx); 6219 evcnt_detach(&isc->isc_rx_fragments); 6220 evcnt_detach(&isc->isc_rx_jabber); 6221 evcnt_detach(&isc->isc_rx_bytes); 6222 evcnt_detach(&isc->isc_rx_discards); 6223 evcnt_detach(&isc->isc_rx_unicast); 6224 evcnt_detach(&isc->isc_rx_multicast); 6225 evcnt_detach(&isc->isc_rx_broadcast); 6226 evcnt_detach(&isc->isc_rx_size_64); 6227 evcnt_detach(&isc->isc_rx_size_127); 6228 evcnt_detach(&isc->isc_rx_size_255); 6229 evcnt_detach(&isc->isc_rx_size_511); 6230 evcnt_detach(&isc->isc_rx_size_1023); 6231 evcnt_detach(&isc->isc_rx_size_1522); 6232 evcnt_detach(&isc->isc_rx_size_big); 6233 evcnt_detach(&isc->isc_rx_undersize); 6234 evcnt_detach(&isc->isc_rx_oversize); 6235 evcnt_detach(&isc->isc_tx_bytes); 6236 evcnt_detach(&isc->isc_tx_dropped_link_down); 6237 evcnt_detach(&isc->isc_tx_unicast); 6238 evcnt_detach(&isc->isc_tx_multicast); 6239 evcnt_detach(&isc->isc_tx_broadcast); 6240 evcnt_detach(&isc->isc_tx_size_64); 6241 evcnt_detach(&isc->isc_tx_size_127); 6242 evcnt_detach(&isc->isc_tx_size_255); 6243 evcnt_detach(&isc->isc_tx_size_511); 6244 evcnt_detach(&isc->isc_tx_size_1023); 6245 evcnt_detach(&isc->isc_tx_size_1522); 6246 evcnt_detach(&isc->isc_tx_size_big); 6247 evcnt_detach(&isc->isc_vsi_rx_discards); 6248 evcnt_detach(&isc->isc_vsi_rx_bytes); 6249 evcnt_detach(&isc->isc_vsi_rx_unicast); 6250 evcnt_detach(&isc->isc_vsi_rx_multicast); 6251 evcnt_detach(&isc->isc_vsi_rx_broadcast); 6252 evcnt_detach(&isc->isc_vsi_tx_errors); 6253 evcnt_detach(&isc->isc_vsi_tx_bytes); 6254 evcnt_detach(&isc->isc_vsi_tx_unicast); 6255 evcnt_detach(&isc->isc_vsi_tx_multicast); 6256 evcnt_detach(&isc->isc_vsi_tx_broadcast); 6257 6258 evcnt_detach(&sc->sc_event_atq); 6259 evcnt_detach(&sc->sc_event_link); 6260 evcnt_detach(&sc->sc_event_ecc_err); 6261 evcnt_detach(&sc->sc_event_pci_exception); 6262 evcnt_detach(&sc->sc_event_crit_err); 6263 6264 callout_destroy(&sc->sc_stats_callout); 6265 } 6266 6267 static void 6268 ixl_stats_callout(void *xsc) 6269 { 6270 struct ixl_softc *sc = xsc; 6271 6272 ixl_work_add(sc->sc_workq, &sc->sc_stats_task); 6273 callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval)); 6274 } 6275 6276 static uint64_t 6277 ixl_stat_delta(struct ixl_softc *sc, uint32_t reg_hi, uint32_t reg_lo, 6278 uint64_t *offset, bool has_offset) 6279 { 6280 uint64_t value, delta; 6281 int bitwidth; 6282 6283 bitwidth = reg_hi == 0 ? 32 : 48; 6284 6285 value = ixl_rd(sc, reg_lo); 6286 6287 if (bitwidth > 32) { 6288 value |= ((uint64_t)ixl_rd(sc, reg_hi) << 32); 6289 } 6290 6291 if (__predict_true(has_offset)) { 6292 delta = value; 6293 if (value < *offset) 6294 delta += ((uint64_t)1 << bitwidth); 6295 delta -= *offset; 6296 } else { 6297 delta = 0; 6298 } 6299 atomic_swap_64(offset, value); 6300 6301 return delta; 6302 } 6303 6304 static void 6305 ixl_stats_update(void *xsc) 6306 { 6307 struct ixl_softc *sc = xsc; 6308 struct ixl_stats_counters *isc; 6309 uint64_t delta; 6310 6311 isc = &sc->sc_stats_counters; 6312 6313 /* errors */ 6314 delta = ixl_stat_delta(sc, 6315 0, I40E_GLPRT_CRCERRS(sc->sc_port), 6316 &isc->isc_crc_errors_offset, isc->isc_has_offset); 6317 atomic_add_64(&isc->isc_crc_errors.ev_count, delta); 6318 6319 delta = ixl_stat_delta(sc, 6320 0, I40E_GLPRT_ILLERRC(sc->sc_port), 6321 &isc->isc_illegal_bytes_offset, isc->isc_has_offset); 6322 atomic_add_64(&isc->isc_illegal_bytes.ev_count, delta); 6323 6324 /* rx */ 6325 delta = ixl_stat_delta(sc, 6326 I40E_GLPRT_GORCH(sc->sc_port), I40E_GLPRT_GORCL(sc->sc_port), 6327 &isc->isc_rx_bytes_offset, isc->isc_has_offset); 6328 atomic_add_64(&isc->isc_rx_bytes.ev_count, delta); 6329 6330 delta = ixl_stat_delta(sc, 6331 0, I40E_GLPRT_RDPC(sc->sc_port), 6332 &isc->isc_rx_discards_offset, isc->isc_has_offset); 6333 atomic_add_64(&isc->isc_rx_discards.ev_count, delta); 6334 6335 delta = ixl_stat_delta(sc, 6336 I40E_GLPRT_UPRCH(sc->sc_port), I40E_GLPRT_UPRCL(sc->sc_port), 6337 &isc->isc_rx_unicast_offset, isc->isc_has_offset); 6338 atomic_add_64(&isc->isc_rx_unicast.ev_count, delta); 6339 6340 delta = ixl_stat_delta(sc, 6341 I40E_GLPRT_MPRCH(sc->sc_port), I40E_GLPRT_MPRCL(sc->sc_port), 6342 &isc->isc_rx_multicast_offset, isc->isc_has_offset); 6343 atomic_add_64(&isc->isc_rx_multicast.ev_count, delta); 6344 6345 delta = ixl_stat_delta(sc, 6346 I40E_GLPRT_BPRCH(sc->sc_port), I40E_GLPRT_BPRCL(sc->sc_port), 6347 &isc->isc_rx_broadcast_offset, isc->isc_has_offset); 6348 atomic_add_64(&isc->isc_rx_broadcast.ev_count, delta); 6349 6350 /* Packet size stats rx */ 6351 delta = ixl_stat_delta(sc, 6352 I40E_GLPRT_PRC64H(sc->sc_port), I40E_GLPRT_PRC64L(sc->sc_port), 6353 &isc->isc_rx_size_64_offset, isc->isc_has_offset); 6354 atomic_add_64(&isc->isc_rx_size_64.ev_count, delta); 6355 6356 delta = ixl_stat_delta(sc, 6357 I40E_GLPRT_PRC127H(sc->sc_port), I40E_GLPRT_PRC127L(sc->sc_port), 6358 &isc->isc_rx_size_127_offset, isc->isc_has_offset); 6359 atomic_add_64(&isc->isc_rx_size_127.ev_count, delta); 6360 6361 delta = ixl_stat_delta(sc, 6362 I40E_GLPRT_PRC255H(sc->sc_port), I40E_GLPRT_PRC255L(sc->sc_port), 6363 &isc->isc_rx_size_255_offset, isc->isc_has_offset); 6364 atomic_add_64(&isc->isc_rx_size_255.ev_count, delta); 6365 6366 delta = ixl_stat_delta(sc, 6367 I40E_GLPRT_PRC511H(sc->sc_port), I40E_GLPRT_PRC511L(sc->sc_port), 6368 &isc->isc_rx_size_511_offset, isc->isc_has_offset); 6369 atomic_add_64(&isc->isc_rx_size_511.ev_count, delta); 6370 6371 delta = ixl_stat_delta(sc, 6372 I40E_GLPRT_PRC1023H(sc->sc_port), I40E_GLPRT_PRC1023L(sc->sc_port), 6373 &isc->isc_rx_size_1023_offset, isc->isc_has_offset); 6374 atomic_add_64(&isc->isc_rx_size_1023.ev_count, delta); 6375 6376 delta = ixl_stat_delta(sc, 6377 I40E_GLPRT_PRC1522H(sc->sc_port), I40E_GLPRT_PRC1522L(sc->sc_port), 6378 &isc->isc_rx_size_1522_offset, isc->isc_has_offset); 6379 atomic_add_64(&isc->isc_rx_size_1522.ev_count, delta); 6380 6381 delta = ixl_stat_delta(sc, 6382 I40E_GLPRT_PRC9522H(sc->sc_port), I40E_GLPRT_PRC9522L(sc->sc_port), 6383 &isc->isc_rx_size_big_offset, isc->isc_has_offset); 6384 atomic_add_64(&isc->isc_rx_size_big.ev_count, delta); 6385 6386 delta = ixl_stat_delta(sc, 6387 0, I40E_GLPRT_RUC(sc->sc_port), 6388 &isc->isc_rx_undersize_offset, isc->isc_has_offset); 6389 atomic_add_64(&isc->isc_rx_undersize.ev_count, delta); 6390 6391 delta = ixl_stat_delta(sc, 6392 0, I40E_GLPRT_ROC(sc->sc_port), 6393 &isc->isc_rx_oversize_offset, isc->isc_has_offset); 6394 atomic_add_64(&isc->isc_rx_oversize.ev_count, delta); 6395 6396 /* tx */ 6397 delta = ixl_stat_delta(sc, 6398 I40E_GLPRT_GOTCH(sc->sc_port), I40E_GLPRT_GOTCL(sc->sc_port), 6399 &isc->isc_tx_bytes_offset, isc->isc_has_offset); 6400 atomic_add_64(&isc->isc_tx_bytes.ev_count, delta); 6401 6402 delta = ixl_stat_delta(sc, 6403 0, I40E_GLPRT_TDOLD(sc->sc_port), 6404 &isc->isc_tx_dropped_link_down_offset, isc->isc_has_offset); 6405 atomic_add_64(&isc->isc_tx_dropped_link_down.ev_count, delta); 6406 6407 delta = ixl_stat_delta(sc, 6408 I40E_GLPRT_UPTCH(sc->sc_port), I40E_GLPRT_UPTCL(sc->sc_port), 6409 &isc->isc_tx_unicast_offset, isc->isc_has_offset); 6410 atomic_add_64(&isc->isc_tx_unicast.ev_count, delta); 6411 6412 delta = ixl_stat_delta(sc, 6413 I40E_GLPRT_MPTCH(sc->sc_port), I40E_GLPRT_MPTCL(sc->sc_port), 6414 &isc->isc_tx_multicast_offset, isc->isc_has_offset); 6415 atomic_add_64(&isc->isc_tx_multicast.ev_count, delta); 6416 6417 delta = ixl_stat_delta(sc, 6418 I40E_GLPRT_BPTCH(sc->sc_port), I40E_GLPRT_BPTCL(sc->sc_port), 6419 &isc->isc_tx_broadcast_offset, isc->isc_has_offset); 6420 atomic_add_64(&isc->isc_tx_broadcast.ev_count, delta); 6421 6422 /* Packet size stats tx */ 6423 delta = ixl_stat_delta(sc, 6424 I40E_GLPRT_PTC64L(sc->sc_port), I40E_GLPRT_PTC64L(sc->sc_port), 6425 &isc->isc_tx_size_64_offset, isc->isc_has_offset); 6426 atomic_add_64(&isc->isc_tx_size_64.ev_count, delta); 6427 6428 delta = ixl_stat_delta(sc, 6429 I40E_GLPRT_PTC127H(sc->sc_port), I40E_GLPRT_PTC127L(sc->sc_port), 6430 &isc->isc_tx_size_127_offset, isc->isc_has_offset); 6431 atomic_add_64(&isc->isc_tx_size_127.ev_count, delta); 6432 6433 delta = ixl_stat_delta(sc, 6434 I40E_GLPRT_PTC255H(sc->sc_port), I40E_GLPRT_PTC255L(sc->sc_port), 6435 &isc->isc_tx_size_255_offset, isc->isc_has_offset); 6436 atomic_add_64(&isc->isc_tx_size_255.ev_count, delta); 6437 6438 delta = ixl_stat_delta(sc, 6439 I40E_GLPRT_PTC511H(sc->sc_port), I40E_GLPRT_PTC511L(sc->sc_port), 6440 &isc->isc_tx_size_511_offset, isc->isc_has_offset); 6441 atomic_add_64(&isc->isc_tx_size_511.ev_count, delta); 6442 6443 delta = ixl_stat_delta(sc, 6444 I40E_GLPRT_PTC1023H(sc->sc_port), I40E_GLPRT_PTC1023L(sc->sc_port), 6445 &isc->isc_tx_size_1023_offset, isc->isc_has_offset); 6446 atomic_add_64(&isc->isc_tx_size_1023.ev_count, delta); 6447 6448 delta = ixl_stat_delta(sc, 6449 I40E_GLPRT_PTC1522H(sc->sc_port), I40E_GLPRT_PTC1522L(sc->sc_port), 6450 &isc->isc_tx_size_1522_offset, isc->isc_has_offset); 6451 atomic_add_64(&isc->isc_tx_size_1522.ev_count, delta); 6452 6453 delta = ixl_stat_delta(sc, 6454 I40E_GLPRT_PTC9522H(sc->sc_port), I40E_GLPRT_PTC9522L(sc->sc_port), 6455 &isc->isc_tx_size_big_offset, isc->isc_has_offset); 6456 atomic_add_64(&isc->isc_tx_size_big.ev_count, delta); 6457 6458 /* mac faults */ 6459 delta = ixl_stat_delta(sc, 6460 0, I40E_GLPRT_MLFC(sc->sc_port), 6461 &isc->isc_mac_local_faults_offset, isc->isc_has_offset); 6462 atomic_add_64(&isc->isc_mac_local_faults.ev_count, delta); 6463 6464 delta = ixl_stat_delta(sc, 6465 0, I40E_GLPRT_MRFC(sc->sc_port), 6466 &isc->isc_mac_remote_faults_offset, isc->isc_has_offset); 6467 atomic_add_64(&isc->isc_mac_remote_faults.ev_count, delta); 6468 6469 /* Flow control (LFC) stats */ 6470 delta = ixl_stat_delta(sc, 6471 0, I40E_GLPRT_LXONRXC(sc->sc_port), 6472 &isc->isc_link_xon_rx_offset, isc->isc_has_offset); 6473 atomic_add_64(&isc->isc_link_xon_rx.ev_count, delta); 6474 6475 delta = ixl_stat_delta(sc, 6476 0, I40E_GLPRT_LXONTXC(sc->sc_port), 6477 &isc->isc_link_xon_tx_offset, isc->isc_has_offset); 6478 atomic_add_64(&isc->isc_link_xon_tx.ev_count, delta); 6479 6480 delta = ixl_stat_delta(sc, 6481 0, I40E_GLPRT_LXOFFRXC(sc->sc_port), 6482 &isc->isc_link_xoff_rx_offset, isc->isc_has_offset); 6483 atomic_add_64(&isc->isc_link_xoff_rx.ev_count, delta); 6484 6485 delta = ixl_stat_delta(sc, 6486 0, I40E_GLPRT_LXOFFTXC(sc->sc_port), 6487 &isc->isc_link_xoff_tx_offset, isc->isc_has_offset); 6488 atomic_add_64(&isc->isc_link_xoff_tx.ev_count, delta); 6489 6490 /* fragments */ 6491 delta = ixl_stat_delta(sc, 6492 0, I40E_GLPRT_RFC(sc->sc_port), 6493 &isc->isc_rx_fragments_offset, isc->isc_has_offset); 6494 atomic_add_64(&isc->isc_rx_fragments.ev_count, delta); 6495 6496 delta = ixl_stat_delta(sc, 6497 0, I40E_GLPRT_RJC(sc->sc_port), 6498 &isc->isc_rx_jabber_offset, isc->isc_has_offset); 6499 atomic_add_64(&isc->isc_rx_jabber.ev_count, delta); 6500 6501 /* VSI rx counters */ 6502 delta = ixl_stat_delta(sc, 6503 0, I40E_GLV_RDPC(sc->sc_vsi_stat_counter_idx), 6504 &isc->isc_vsi_rx_discards_offset, isc->isc_has_offset); 6505 atomic_add_64(&isc->isc_vsi_rx_discards.ev_count, delta); 6506 6507 delta = ixl_stat_delta(sc, 6508 I40E_GLV_GORCH(sc->sc_vsi_stat_counter_idx), 6509 I40E_GLV_GORCL(sc->sc_vsi_stat_counter_idx), 6510 &isc->isc_vsi_rx_bytes_offset, isc->isc_has_offset); 6511 atomic_add_64(&isc->isc_vsi_rx_bytes.ev_count, delta); 6512 6513 delta = ixl_stat_delta(sc, 6514 I40E_GLV_UPRCH(sc->sc_vsi_stat_counter_idx), 6515 I40E_GLV_UPRCL(sc->sc_vsi_stat_counter_idx), 6516 &isc->isc_vsi_rx_unicast_offset, isc->isc_has_offset); 6517 atomic_add_64(&isc->isc_vsi_rx_unicast.ev_count, delta); 6518 6519 delta = ixl_stat_delta(sc, 6520 I40E_GLV_MPRCH(sc->sc_vsi_stat_counter_idx), 6521 I40E_GLV_MPRCL(sc->sc_vsi_stat_counter_idx), 6522 &isc->isc_vsi_rx_multicast_offset, isc->isc_has_offset); 6523 atomic_add_64(&isc->isc_vsi_rx_multicast.ev_count, delta); 6524 6525 delta = ixl_stat_delta(sc, 6526 I40E_GLV_BPRCH(sc->sc_vsi_stat_counter_idx), 6527 I40E_GLV_BPRCL(sc->sc_vsi_stat_counter_idx), 6528 &isc->isc_vsi_rx_broadcast_offset, isc->isc_has_offset); 6529 atomic_add_64(&isc->isc_vsi_rx_broadcast.ev_count, delta); 6530 6531 /* VSI tx counters */ 6532 delta = ixl_stat_delta(sc, 6533 0, I40E_GLV_TEPC(sc->sc_vsi_stat_counter_idx), 6534 &isc->isc_vsi_tx_errors_offset, isc->isc_has_offset); 6535 atomic_add_64(&isc->isc_vsi_tx_errors.ev_count, delta); 6536 6537 delta = ixl_stat_delta(sc, 6538 I40E_GLV_GOTCH(sc->sc_vsi_stat_counter_idx), 6539 I40E_GLV_GOTCL(sc->sc_vsi_stat_counter_idx), 6540 &isc->isc_vsi_tx_bytes_offset, isc->isc_has_offset); 6541 atomic_add_64(&isc->isc_vsi_tx_bytes.ev_count, delta); 6542 6543 delta = ixl_stat_delta(sc, 6544 I40E_GLV_UPTCH(sc->sc_vsi_stat_counter_idx), 6545 I40E_GLV_UPTCL(sc->sc_vsi_stat_counter_idx), 6546 &isc->isc_vsi_tx_unicast_offset, isc->isc_has_offset); 6547 atomic_add_64(&isc->isc_vsi_tx_unicast.ev_count, delta); 6548 6549 delta = ixl_stat_delta(sc, 6550 I40E_GLV_MPTCH(sc->sc_vsi_stat_counter_idx), 6551 I40E_GLV_MPTCL(sc->sc_vsi_stat_counter_idx), 6552 &isc->isc_vsi_tx_multicast_offset, isc->isc_has_offset); 6553 atomic_add_64(&isc->isc_vsi_tx_multicast.ev_count, delta); 6554 6555 delta = ixl_stat_delta(sc, 6556 I40E_GLV_BPTCH(sc->sc_vsi_stat_counter_idx), 6557 I40E_GLV_BPTCL(sc->sc_vsi_stat_counter_idx), 6558 &isc->isc_vsi_tx_broadcast_offset, isc->isc_has_offset); 6559 atomic_add_64(&isc->isc_vsi_tx_broadcast.ev_count, delta); 6560 } 6561 6562 static int 6563 ixl_setup_sysctls(struct ixl_softc *sc) 6564 { 6565 const char *devname; 6566 struct sysctllog **log; 6567 const struct sysctlnode *rnode, *rxnode, *txnode; 6568 int error; 6569 6570 log = &sc->sc_sysctllog; 6571 devname = device_xname(sc->sc_dev); 6572 6573 error = sysctl_createv(log, 0, NULL, &rnode, 6574 0, CTLTYPE_NODE, devname, 6575 SYSCTL_DESCR("ixl information and settings"), 6576 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 6577 if (error) 6578 goto out; 6579 6580 error = sysctl_createv(log, 0, &rnode, NULL, 6581 CTLFLAG_READWRITE, CTLTYPE_BOOL, "txrx_workqueue", 6582 SYSCTL_DESCR("Use workqueue for packet processing"), 6583 NULL, 0, &sc->sc_txrx_workqueue, 0, CTL_CREATE, CTL_EOL); 6584 if (error) 6585 goto out; 6586 6587 error = sysctl_createv(log, 0, &rnode, NULL, 6588 CTLFLAG_READONLY, CTLTYPE_INT, "stats_interval", 6589 SYSCTL_DESCR("Statistics collection interval in milliseconds"), 6590 NULL, 0, &sc->sc_stats_intval, 0, CTL_CREATE, CTL_EOL); 6591 6592 error = sysctl_createv(log, 0, &rnode, &rxnode, 6593 0, CTLTYPE_NODE, "rx", 6594 SYSCTL_DESCR("ixl information and settings for Rx"), 6595 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 6596 if (error) 6597 goto out; 6598 6599 error = sysctl_createv(log, 0, &rxnode, NULL, 6600 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 6601 SYSCTL_DESCR("max number of Rx packets" 6602 " to process for interrupt processing"), 6603 NULL, 0, &sc->sc_rx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 6604 if (error) 6605 goto out; 6606 6607 error = sysctl_createv(log, 0, &rxnode, NULL, 6608 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 6609 SYSCTL_DESCR("max number of Rx packets" 6610 " to process for deferred processing"), 6611 NULL, 0, &sc->sc_rx_process_limit, 0, CTL_CREATE, CTL_EOL); 6612 if (error) 6613 goto out; 6614 6615 error = sysctl_createv(log, 0, &rnode, &txnode, 6616 0, CTLTYPE_NODE, "tx", 6617 SYSCTL_DESCR("ixl information and settings for Tx"), 6618 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 6619 if (error) 6620 goto out; 6621 6622 error = sysctl_createv(log, 0, &txnode, NULL, 6623 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 6624 SYSCTL_DESCR("max number of Tx packets" 6625 " to process for interrupt processing"), 6626 NULL, 0, &sc->sc_tx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 6627 if (error) 6628 goto out; 6629 6630 error = sysctl_createv(log, 0, &txnode, NULL, 6631 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 6632 SYSCTL_DESCR("max number of Tx packets" 6633 " to process for deferred processing"), 6634 NULL, 0, &sc->sc_tx_process_limit, 0, CTL_CREATE, CTL_EOL); 6635 if (error) 6636 goto out; 6637 6638 out: 6639 if (error) { 6640 aprint_error_dev(sc->sc_dev, 6641 "unable to create sysctl node\n"); 6642 sysctl_teardown(log); 6643 } 6644 6645 return error; 6646 } 6647 6648 static void 6649 ixl_teardown_sysctls(struct ixl_softc *sc) 6650 { 6651 6652 sysctl_teardown(&sc->sc_sysctllog); 6653 } 6654 6655 static struct workqueue * 6656 ixl_workq_create(const char *name, pri_t prio, int ipl, int flags) 6657 { 6658 struct workqueue *wq; 6659 int error; 6660 6661 error = workqueue_create(&wq, name, ixl_workq_work, NULL, 6662 prio, ipl, flags); 6663 6664 if (error) 6665 return NULL; 6666 6667 return wq; 6668 } 6669 6670 static void 6671 ixl_workq_destroy(struct workqueue *wq) 6672 { 6673 6674 workqueue_destroy(wq); 6675 } 6676 6677 static void 6678 ixl_work_set(struct ixl_work *work, void (*func)(void *), void *arg) 6679 { 6680 6681 memset(work, 0, sizeof(*work)); 6682 work->ixw_func = func; 6683 work->ixw_arg = arg; 6684 } 6685 6686 static void 6687 ixl_work_add(struct workqueue *wq, struct ixl_work *work) 6688 { 6689 if (atomic_cas_uint(&work->ixw_added, 0, 1) != 0) 6690 return; 6691 6692 kpreempt_disable(); 6693 workqueue_enqueue(wq, &work->ixw_cookie, NULL); 6694 kpreempt_enable(); 6695 } 6696 6697 static void 6698 ixl_work_wait(struct workqueue *wq, struct ixl_work *work) 6699 { 6700 6701 workqueue_wait(wq, &work->ixw_cookie); 6702 } 6703 6704 static void 6705 ixl_workq_work(struct work *wk, void *context) 6706 { 6707 struct ixl_work *work; 6708 6709 work = container_of(wk, struct ixl_work, ixw_cookie); 6710 6711 atomic_swap_uint(&work->ixw_added, 0); 6712 work->ixw_func(work->ixw_arg); 6713 } 6714 6715 static int 6716 ixl_rx_ctl_read(struct ixl_softc *sc, uint32_t reg, uint32_t *rv) 6717 { 6718 struct ixl_aq_desc iaq; 6719 6720 memset(&iaq, 0, sizeof(iaq)); 6721 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_READ); 6722 iaq.iaq_param[1] = htole32(reg); 6723 6724 if (ixl_atq_poll(sc, &iaq, 250) != 0) 6725 return ETIMEDOUT; 6726 6727 switch (htole16(iaq.iaq_retval)) { 6728 case IXL_AQ_RC_OK: 6729 /* success */ 6730 break; 6731 case IXL_AQ_RC_EACCES: 6732 return EPERM; 6733 case IXL_AQ_RC_EAGAIN: 6734 return EAGAIN; 6735 default: 6736 return EIO; 6737 } 6738 6739 *rv = htole32(iaq.iaq_param[3]); 6740 return 0; 6741 } 6742 6743 static uint32_t 6744 ixl_rd_rx_csr(struct ixl_softc *sc, uint32_t reg) 6745 { 6746 uint32_t val; 6747 int rv, retry, retry_limit; 6748 6749 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL)) { 6750 retry_limit = 5; 6751 } else { 6752 retry_limit = 0; 6753 } 6754 6755 for (retry = 0; retry < retry_limit; retry++) { 6756 rv = ixl_rx_ctl_read(sc, reg, &val); 6757 if (rv == 0) 6758 return val; 6759 else if (rv == EAGAIN) 6760 delaymsec(1); 6761 else 6762 break; 6763 } 6764 6765 val = ixl_rd(sc, reg); 6766 6767 return val; 6768 } 6769 6770 static int 6771 ixl_rx_ctl_write(struct ixl_softc *sc, uint32_t reg, uint32_t value) 6772 { 6773 struct ixl_aq_desc iaq; 6774 6775 memset(&iaq, 0, sizeof(iaq)); 6776 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_WRITE); 6777 iaq.iaq_param[1] = htole32(reg); 6778 iaq.iaq_param[3] = htole32(value); 6779 6780 if (ixl_atq_poll(sc, &iaq, 250) != 0) 6781 return ETIMEDOUT; 6782 6783 switch (htole16(iaq.iaq_retval)) { 6784 case IXL_AQ_RC_OK: 6785 /* success */ 6786 break; 6787 case IXL_AQ_RC_EACCES: 6788 return EPERM; 6789 case IXL_AQ_RC_EAGAIN: 6790 return EAGAIN; 6791 default: 6792 return EIO; 6793 } 6794 6795 return 0; 6796 } 6797 6798 static void 6799 ixl_wr_rx_csr(struct ixl_softc *sc, uint32_t reg, uint32_t value) 6800 { 6801 int rv, retry, retry_limit; 6802 6803 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL)) { 6804 retry_limit = 5; 6805 } else { 6806 retry_limit = 0; 6807 } 6808 6809 for (retry = 0; retry < retry_limit; retry++) { 6810 rv = ixl_rx_ctl_write(sc, reg, value); 6811 if (rv == 0) 6812 return; 6813 else if (rv == EAGAIN) 6814 delaymsec(1); 6815 else 6816 break; 6817 } 6818 6819 ixl_wr(sc, reg, value); 6820 } 6821 6822 static int 6823 ixl_nvm_lock(struct ixl_softc *sc, char rw) 6824 { 6825 struct ixl_aq_desc iaq; 6826 struct ixl_aq_req_resource_param *param; 6827 int rv; 6828 6829 if (!ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK)) 6830 return 0; 6831 6832 memset(&iaq, 0, sizeof(iaq)); 6833 iaq.iaq_opcode = htole16(IXL_AQ_OP_REQUEST_RESOURCE); 6834 6835 param = (struct ixl_aq_req_resource_param *)&iaq.iaq_param; 6836 param->resource_id = htole16(IXL_AQ_RESOURCE_ID_NVM); 6837 if (rw == 'R') { 6838 param->access_type = htole16(IXL_AQ_RESOURCE_ACCES_READ); 6839 } else { 6840 param->access_type = htole16(IXL_AQ_RESOURCE_ACCES_WRITE); 6841 } 6842 6843 rv = ixl_atq_poll(sc, &iaq, 250); 6844 6845 if (rv != 0) 6846 return ETIMEDOUT; 6847 6848 switch (le16toh(iaq.iaq_retval)) { 6849 case IXL_AQ_RC_OK: 6850 break; 6851 case IXL_AQ_RC_EACCES: 6852 return EACCES; 6853 case IXL_AQ_RC_EBUSY: 6854 return EBUSY; 6855 case IXL_AQ_RC_EPERM: 6856 return EPERM; 6857 } 6858 6859 return 0; 6860 } 6861 6862 static int 6863 ixl_nvm_unlock(struct ixl_softc *sc) 6864 { 6865 struct ixl_aq_desc iaq; 6866 struct ixl_aq_rel_resource_param *param; 6867 int rv; 6868 6869 if (!ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK)) 6870 return 0; 6871 6872 memset(&iaq, 0, sizeof(iaq)); 6873 iaq.iaq_opcode = htole16(IXL_AQ_OP_RELEASE_RESOURCE); 6874 6875 param = (struct ixl_aq_rel_resource_param *)&iaq.iaq_param; 6876 param->resource_id = htole16(IXL_AQ_RESOURCE_ID_NVM); 6877 6878 rv = ixl_atq_poll(sc, &iaq, 250); 6879 6880 if (rv != 0) 6881 return ETIMEDOUT; 6882 6883 switch (le16toh(iaq.iaq_retval)) { 6884 case IXL_AQ_RC_OK: 6885 break; 6886 default: 6887 return EIO; 6888 } 6889 return 0; 6890 } 6891 6892 static int 6893 ixl_srdone_poll(struct ixl_softc *sc) 6894 { 6895 int wait_count; 6896 uint32_t reg; 6897 6898 for (wait_count = 0; wait_count < IXL_SRRD_SRCTL_ATTEMPTS; 6899 wait_count++) { 6900 reg = ixl_rd(sc, I40E_GLNVM_SRCTL); 6901 if (ISSET(reg, I40E_GLNVM_SRCTL_DONE_MASK)) 6902 break; 6903 6904 delaymsec(5); 6905 } 6906 6907 if (wait_count == IXL_SRRD_SRCTL_ATTEMPTS) 6908 return -1; 6909 6910 return 0; 6911 } 6912 6913 static int 6914 ixl_nvm_read_srctl(struct ixl_softc *sc, uint16_t offset, uint16_t *data) 6915 { 6916 uint32_t reg; 6917 6918 if (ixl_srdone_poll(sc) != 0) 6919 return ETIMEDOUT; 6920 6921 reg = ((uint32_t)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 6922 __BIT(I40E_GLNVM_SRCTL_START_SHIFT); 6923 ixl_wr(sc, I40E_GLNVM_SRCTL, reg); 6924 6925 if (ixl_srdone_poll(sc) != 0) { 6926 aprint_debug("NVM read error: couldn't access " 6927 "Shadow RAM address: 0x%x\n", offset); 6928 return ETIMEDOUT; 6929 } 6930 6931 reg = ixl_rd(sc, I40E_GLNVM_SRDATA); 6932 *data = (uint16_t)__SHIFTOUT(reg, I40E_GLNVM_SRDATA_RDDATA_MASK); 6933 6934 return 0; 6935 } 6936 6937 static int 6938 ixl_nvm_read_aq(struct ixl_softc *sc, uint16_t offset_word, 6939 void *data, size_t len) 6940 { 6941 struct ixl_dmamem *idm; 6942 struct ixl_aq_desc iaq; 6943 struct ixl_aq_nvm_param *param; 6944 uint32_t offset_bytes; 6945 int rv; 6946 6947 idm = &sc->sc_aqbuf; 6948 if (len > IXL_DMA_LEN(idm)) 6949 return ENOMEM; 6950 6951 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 6952 memset(&iaq, 0, sizeof(iaq)); 6953 iaq.iaq_opcode = htole16(IXL_AQ_OP_NVM_READ); 6954 iaq.iaq_flags = htole16(IXL_AQ_BUF | 6955 ((len > I40E_AQ_LARGE_BUF) ? IXL_AQ_LB : 0)); 6956 iaq.iaq_datalen = htole16(len); 6957 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 6958 6959 param = (struct ixl_aq_nvm_param *)iaq.iaq_param; 6960 param->command_flags = IXL_AQ_NVM_LAST_CMD; 6961 param->module_pointer = 0; 6962 param->length = htole16(len); 6963 offset_bytes = (uint32_t)offset_word * 2; 6964 offset_bytes &= 0x00FFFFFF; 6965 param->offset = htole32(offset_bytes); 6966 6967 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 6968 BUS_DMASYNC_PREREAD); 6969 6970 rv = ixl_atq_poll(sc, &iaq, 250); 6971 6972 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 6973 BUS_DMASYNC_POSTREAD); 6974 6975 if (rv != 0) { 6976 return ETIMEDOUT; 6977 } 6978 6979 switch (le16toh(iaq.iaq_retval)) { 6980 case IXL_AQ_RC_OK: 6981 break; 6982 case IXL_AQ_RC_EPERM: 6983 return EPERM; 6984 case IXL_AQ_RC_EINVAL: 6985 return EINVAL; 6986 case IXL_AQ_RC_EBUSY: 6987 return EBUSY; 6988 case IXL_AQ_RC_EIO: 6989 default: 6990 return EIO; 6991 } 6992 6993 memcpy(data, IXL_DMA_KVA(idm), len); 6994 6995 return 0; 6996 } 6997 6998 static int 6999 ixl_rd16_nvm(struct ixl_softc *sc, uint16_t offset, uint16_t *data) 7000 { 7001 int error; 7002 uint16_t buf; 7003 7004 error = ixl_nvm_lock(sc, 'R'); 7005 if (error) 7006 return error; 7007 7008 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMREAD)) { 7009 error = ixl_nvm_read_aq(sc, offset, 7010 &buf, sizeof(buf)); 7011 if (error == 0) 7012 *data = le16toh(buf); 7013 } else { 7014 error = ixl_nvm_read_srctl(sc, offset, &buf); 7015 if (error == 0) 7016 *data = buf; 7017 } 7018 7019 ixl_nvm_unlock(sc); 7020 7021 return error; 7022 } 7023 7024 MODULE(MODULE_CLASS_DRIVER, if_ixl, "pci"); 7025 7026 #ifdef _MODULE 7027 #include "ioconf.c" 7028 #endif 7029 7030 #ifdef _MODULE 7031 static void 7032 ixl_parse_modprop(prop_dictionary_t dict) 7033 { 7034 prop_object_t obj; 7035 int64_t val; 7036 uint64_t uval; 7037 7038 if (dict == NULL) 7039 return; 7040 7041 obj = prop_dictionary_get(dict, "nomsix"); 7042 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_BOOL) { 7043 ixl_param_nomsix = prop_bool_true((prop_bool_t)obj); 7044 } 7045 7046 obj = prop_dictionary_get(dict, "stats_interval"); 7047 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7048 val = prop_number_integer_value((prop_number_t)obj); 7049 7050 /* the range has no reason */ 7051 if (100 < val && val < 180000) { 7052 ixl_param_stats_interval = val; 7053 } 7054 } 7055 7056 obj = prop_dictionary_get(dict, "nqps_limit"); 7057 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7058 val = prop_number_integer_value((prop_number_t)obj); 7059 7060 if (val <= INT32_MAX) 7061 ixl_param_nqps_limit = val; 7062 } 7063 7064 obj = prop_dictionary_get(dict, "rx_ndescs"); 7065 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7066 uval = prop_number_unsigned_integer_value((prop_number_t)obj); 7067 7068 if (uval > 8) 7069 ixl_param_rx_ndescs = uval; 7070 } 7071 7072 obj = prop_dictionary_get(dict, "tx_ndescs"); 7073 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7074 uval = prop_number_unsigned_integer_value((prop_number_t)obj); 7075 7076 if (uval > IXL_TX_PKT_DESCS) 7077 ixl_param_tx_ndescs = uval; 7078 } 7079 7080 } 7081 #endif 7082 7083 static int 7084 if_ixl_modcmd(modcmd_t cmd, void *opaque) 7085 { 7086 int error = 0; 7087 7088 #ifdef _MODULE 7089 switch (cmd) { 7090 case MODULE_CMD_INIT: 7091 ixl_parse_modprop((prop_dictionary_t)opaque); 7092 error = config_init_component(cfdriver_ioconf_if_ixl, 7093 cfattach_ioconf_if_ixl, cfdata_ioconf_if_ixl); 7094 break; 7095 case MODULE_CMD_FINI: 7096 error = config_fini_component(cfdriver_ioconf_if_ixl, 7097 cfattach_ioconf_if_ixl, cfdata_ioconf_if_ixl); 7098 break; 7099 default: 7100 error = ENOTTY; 7101 break; 7102 } 7103 #endif 7104 7105 return error; 7106 } 7107
Indexes created Sun Sep 21 16:09:51 GMT 2025