if_ixl.c revision 1.63
1 /* $NetBSD: if_ixl.c,v 1.63 2020/03/13 05:40:20 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg (at) openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 /* 51 * Copyright (c) 2019 Internet Initiative Japan, Inc. 52 * All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 64 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 65 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 66 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 67 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 68 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 69 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 70 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 71 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 72 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 73 * POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.63 2020/03/13 05:40:20 yamaguchi Exp $"); 78 79 #ifdef _KERNEL_OPT 80 #include "opt_net_mpsafe.h" 81 #include "opt_if_ixl.h" 82 #endif 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/cpu.h> 88 #include <sys/device.h> 89 #include <sys/evcnt.h> 90 #include <sys/interrupt.h> 91 #include <sys/kmem.h> 92 #include <sys/module.h> 93 #include <sys/mutex.h> 94 #include <sys/pcq.h> 95 #include <sys/syslog.h> 96 #include <sys/workqueue.h> 97 98 #include <sys/bus.h> 99 100 #include <net/bpf.h> 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 #include <net/rss_config.h> 106 107 #include <netinet/tcp.h> /* for struct tcphdr */ 108 #include <netinet/udp.h> /* for struct udphdr */ 109 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_ixlreg.h> 114 #include <dev/pci/if_ixlvar.h> 115 116 #include <prop/proplib.h> 117 118 struct ixl_softc; /* defined */ 119 120 #define I40E_PF_RESET_WAIT_COUNT 200 121 #define I40E_AQ_LARGE_BUF 512 122 123 /* bitfields for Tx queue mapping in QTX_CTL */ 124 #define I40E_QTX_CTL_VF_QUEUE 0x0 125 #define I40E_QTX_CTL_VM_QUEUE 0x1 126 #define I40E_QTX_CTL_PF_QUEUE 0x2 127 128 #define I40E_QUEUE_TYPE_EOL 0x7ff 129 #define I40E_INTR_NOTX_QUEUE 0 130 131 #define I40E_QUEUE_TYPE_RX 0x0 132 #define I40E_QUEUE_TYPE_TX 0x1 133 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 134 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 135 136 #define I40E_ITR_INDEX_RX 0x0 137 #define I40E_ITR_INDEX_TX 0x1 138 #define I40E_ITR_INDEX_OTHER 0x2 139 #define I40E_ITR_INDEX_NONE 0x3 140 141 #define I40E_INTR_NOTX_QUEUE 0 142 #define I40E_INTR_NOTX_INTR 0 143 #define I40E_INTR_NOTX_RX_QUEUE 0 144 #define I40E_INTR_NOTX_TX_QUEUE 1 145 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 146 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 147 148 #define BIT_ULL(a) (1ULL << (a)) 149 #define IXL_RSS_HENA_DEFAULT_BASE \ 150 (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 151 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 152 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 153 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 154 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 155 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 156 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 157 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 158 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 159 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 160 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 161 #define IXL_RSS_HENA_DEFAULT_XL710 IXL_RSS_HENA_DEFAULT_BASE 162 #define IXL_RSS_HENA_DEFAULT_X722 (IXL_RSS_HENA_DEFAULT_XL710 | \ 163 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 164 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 165 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 166 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 167 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 168 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK)) 169 #define I40E_HASH_LUT_SIZE_128 0 170 #define IXL_RSS_KEY_SIZE_REG 13 171 172 #define IXL_ICR0_CRIT_ERR_MASK \ 173 (I40E_PFINT_ICR0_PCI_EXCEPTION_MASK | \ 174 I40E_PFINT_ICR0_ECC_ERR_MASK | \ 175 I40E_PFINT_ICR0_PE_CRITERR_MASK) 176 177 #define IXL_QUEUE_MAX_XL710 64 178 #define IXL_QUEUE_MAX_X722 128 179 180 #define IXL_TX_PKT_DESCS 8 181 #define IXL_TX_PKT_MAXSIZE (MCLBYTES * IXL_TX_PKT_DESCS) 182 #define IXL_TX_QUEUE_ALIGN 128 183 #define IXL_RX_QUEUE_ALIGN 128 184 185 #define IXL_MCLBYTES (MCLBYTES - ETHER_ALIGN) 186 #define IXL_MTU_ETHERLEN ETHER_HDR_LEN \ 187 + ETHER_CRC_LEN 188 #if 0 189 #define IXL_MAX_MTU (9728 - IXL_MTU_ETHERLEN) 190 #else 191 /* (dbuff * 5) - ETHER_HDR_LEN - ETHER_CRC_LEN */ 192 #define IXL_MAX_MTU (9600 - IXL_MTU_ETHERLEN) 193 #endif 194 #define IXL_MIN_MTU (ETHER_MIN_LEN - ETHER_CRC_LEN) 195 196 #define IXL_PCIREG PCI_MAPREG_START 197 198 #define IXL_ITR0 0x0 199 #define IXL_ITR1 0x1 200 #define IXL_ITR2 0x2 201 #define IXL_NOITR 0x3 202 203 #define IXL_AQ_NUM 256 204 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 205 #define IXL_AQ_ALIGN 64 /* lol */ 206 #define IXL_AQ_BUFLEN 4096 207 208 #define IXL_HMC_ROUNDUP 512 209 #define IXL_HMC_PGSIZE 4096 210 #define IXL_HMC_DVASZ sizeof(uint64_t) 211 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 212 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 213 #define IXL_HMC_PDVALID 1ULL 214 215 #define IXL_ATQ_EXEC_TIMEOUT (10 * hz) 216 217 #define IXL_SRRD_SRCTL_ATTEMPTS 100000 218 219 struct ixl_aq_regs { 220 bus_size_t atq_tail; 221 bus_size_t atq_head; 222 bus_size_t atq_len; 223 bus_size_t atq_bal; 224 bus_size_t atq_bah; 225 226 bus_size_t arq_tail; 227 bus_size_t arq_head; 228 bus_size_t arq_len; 229 bus_size_t arq_bal; 230 bus_size_t arq_bah; 231 232 uint32_t atq_len_enable; 233 uint32_t atq_tail_mask; 234 uint32_t atq_head_mask; 235 236 uint32_t arq_len_enable; 237 uint32_t arq_tail_mask; 238 uint32_t arq_head_mask; 239 }; 240 241 struct ixl_phy_type { 242 uint64_t phy_type; 243 uint64_t ifm_type; 244 }; 245 246 struct ixl_speed_type { 247 uint8_t dev_speed; 248 uint64_t net_speed; 249 }; 250 251 struct ixl_aq_buf { 252 SIMPLEQ_ENTRY(ixl_aq_buf) 253 aqb_entry; 254 void *aqb_data; 255 bus_dmamap_t aqb_map; 256 bus_dma_segment_t aqb_seg; 257 size_t aqb_size; 258 int aqb_nsegs; 259 }; 260 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 261 262 struct ixl_dmamem { 263 bus_dmamap_t ixm_map; 264 bus_dma_segment_t ixm_seg; 265 int ixm_nsegs; 266 size_t ixm_size; 267 void *ixm_kva; 268 }; 269 270 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 271 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 272 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 273 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 274 275 struct ixl_hmc_entry { 276 uint64_t hmc_base; 277 uint32_t hmc_count; 278 uint64_t hmc_size; 279 }; 280 281 enum ixl_hmc_types { 282 IXL_HMC_LAN_TX = 0, 283 IXL_HMC_LAN_RX, 284 IXL_HMC_FCOE_CTX, 285 IXL_HMC_FCOE_FILTER, 286 IXL_HMC_COUNT 287 }; 288 289 struct ixl_hmc_pack { 290 uint16_t offset; 291 uint16_t width; 292 uint16_t lsb; 293 }; 294 295 /* 296 * these hmc objects have weird sizes and alignments, so these are abstract 297 * representations of them that are nice for c to populate. 298 * 299 * the packing code relies on little-endian values being stored in the fields, 300 * no high bits in the fields being set, and the fields must be packed in the 301 * same order as they are in the ctx structure. 302 */ 303 304 struct ixl_hmc_rxq { 305 uint16_t head; 306 uint8_t cpuid; 307 uint64_t base; 308 #define IXL_HMC_RXQ_BASE_UNIT 128 309 uint16_t qlen; 310 uint16_t dbuff; 311 #define IXL_HMC_RXQ_DBUFF_UNIT 128 312 uint8_t hbuff; 313 #define IXL_HMC_RXQ_HBUFF_UNIT 64 314 uint8_t dtype; 315 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 316 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 317 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 318 uint8_t dsize; 319 #define IXL_HMC_RXQ_DSIZE_16 0 320 #define IXL_HMC_RXQ_DSIZE_32 1 321 uint8_t crcstrip; 322 uint8_t fc_ena; 323 uint8_t l2sel; 324 uint8_t hsplit_0; 325 uint8_t hsplit_1; 326 uint8_t showiv; 327 uint16_t rxmax; 328 uint8_t tphrdesc_ena; 329 uint8_t tphwdesc_ena; 330 uint8_t tphdata_ena; 331 uint8_t tphhead_ena; 332 uint8_t lrxqthresh; 333 uint8_t prefena; 334 }; 335 336 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 337 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 338 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 339 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 340 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 341 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 342 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 343 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 344 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 345 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 346 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 347 { offsetof(struct ixl_hmc_rxq, l2sel), 1, 119 }, 348 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 349 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 350 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 351 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 352 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 353 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 354 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 355 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 356 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 357 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 358 }; 359 360 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 361 362 struct ixl_hmc_txq { 363 uint16_t head; 364 uint8_t new_context; 365 uint64_t base; 366 #define IXL_HMC_TXQ_BASE_UNIT 128 367 uint8_t fc_ena; 368 uint8_t timesync_ena; 369 uint8_t fd_ena; 370 uint8_t alt_vlan_ena; 371 uint8_t cpuid; 372 uint16_t thead_wb; 373 uint8_t head_wb_ena; 374 #define IXL_HMC_TXQ_DESC_WB 0 375 #define IXL_HMC_TXQ_HEAD_WB 1 376 uint16_t qlen; 377 uint8_t tphrdesc_ena; 378 uint8_t tphrpacket_ena; 379 uint8_t tphwdesc_ena; 380 uint64_t head_wb_addr; 381 uint32_t crc; 382 uint16_t rdylist; 383 uint8_t rdylist_act; 384 }; 385 386 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 387 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 388 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 389 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 390 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 391 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 392 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 393 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 394 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 395 /* line 1 */ 396 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 397 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 398 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 399 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 400 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 401 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 402 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 403 /* line 7 */ 404 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 405 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 406 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 407 }; 408 409 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 410 411 struct ixl_work { 412 struct work ixw_cookie; 413 void (*ixw_func)(void *); 414 void *ixw_arg; 415 unsigned int ixw_added; 416 }; 417 #define IXL_WORKQUEUE_PRI PRI_SOFTNET 418 419 struct ixl_tx_map { 420 struct mbuf *txm_m; 421 bus_dmamap_t txm_map; 422 unsigned int txm_eop; 423 }; 424 425 struct ixl_tx_ring { 426 kmutex_t txr_lock; 427 struct ixl_softc *txr_sc; 428 429 unsigned int txr_prod; 430 unsigned int txr_cons; 431 432 struct ixl_tx_map *txr_maps; 433 struct ixl_dmamem txr_mem; 434 435 bus_size_t txr_tail; 436 unsigned int txr_qid; 437 pcq_t *txr_intrq; 438 void *txr_si; 439 440 struct evcnt txr_defragged; 441 struct evcnt txr_defrag_failed; 442 struct evcnt txr_pcqdrop; 443 struct evcnt txr_transmitdef; 444 struct evcnt txr_intr; 445 struct evcnt txr_defer; 446 }; 447 448 struct ixl_rx_map { 449 struct mbuf *rxm_m; 450 bus_dmamap_t rxm_map; 451 }; 452 453 struct ixl_rx_ring { 454 kmutex_t rxr_lock; 455 456 unsigned int rxr_prod; 457 unsigned int rxr_cons; 458 459 struct ixl_rx_map *rxr_maps; 460 struct ixl_dmamem rxr_mem; 461 462 struct mbuf *rxr_m_head; 463 struct mbuf **rxr_m_tail; 464 465 bus_size_t rxr_tail; 466 unsigned int rxr_qid; 467 468 struct evcnt rxr_mgethdr_failed; 469 struct evcnt rxr_mgetcl_failed; 470 struct evcnt rxr_mbuf_load_failed; 471 struct evcnt rxr_intr; 472 struct evcnt rxr_defer; 473 }; 474 475 struct ixl_queue_pair { 476 struct ixl_softc *qp_sc; 477 struct ixl_tx_ring *qp_txr; 478 struct ixl_rx_ring *qp_rxr; 479 480 char qp_name[16]; 481 482 void *qp_si; 483 struct work qp_work; 484 bool qp_workqueue; 485 }; 486 487 struct ixl_atq { 488 struct ixl_aq_desc iatq_desc; 489 void (*iatq_fn)(struct ixl_softc *, 490 const struct ixl_aq_desc *); 491 }; 492 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 493 494 struct ixl_product { 495 unsigned int vendor_id; 496 unsigned int product_id; 497 }; 498 499 struct ixl_stats_counters { 500 bool isc_has_offset; 501 struct evcnt isc_crc_errors; 502 uint64_t isc_crc_errors_offset; 503 struct evcnt isc_illegal_bytes; 504 uint64_t isc_illegal_bytes_offset; 505 struct evcnt isc_rx_bytes; 506 uint64_t isc_rx_bytes_offset; 507 struct evcnt isc_rx_discards; 508 uint64_t isc_rx_discards_offset; 509 struct evcnt isc_rx_unicast; 510 uint64_t isc_rx_unicast_offset; 511 struct evcnt isc_rx_multicast; 512 uint64_t isc_rx_multicast_offset; 513 struct evcnt isc_rx_broadcast; 514 uint64_t isc_rx_broadcast_offset; 515 struct evcnt isc_rx_size_64; 516 uint64_t isc_rx_size_64_offset; 517 struct evcnt isc_rx_size_127; 518 uint64_t isc_rx_size_127_offset; 519 struct evcnt isc_rx_size_255; 520 uint64_t isc_rx_size_255_offset; 521 struct evcnt isc_rx_size_511; 522 uint64_t isc_rx_size_511_offset; 523 struct evcnt isc_rx_size_1023; 524 uint64_t isc_rx_size_1023_offset; 525 struct evcnt isc_rx_size_1522; 526 uint64_t isc_rx_size_1522_offset; 527 struct evcnt isc_rx_size_big; 528 uint64_t isc_rx_size_big_offset; 529 struct evcnt isc_rx_undersize; 530 uint64_t isc_rx_undersize_offset; 531 struct evcnt isc_rx_oversize; 532 uint64_t isc_rx_oversize_offset; 533 struct evcnt isc_rx_fragments; 534 uint64_t isc_rx_fragments_offset; 535 struct evcnt isc_rx_jabber; 536 uint64_t isc_rx_jabber_offset; 537 struct evcnt isc_tx_bytes; 538 uint64_t isc_tx_bytes_offset; 539 struct evcnt isc_tx_dropped_link_down; 540 uint64_t isc_tx_dropped_link_down_offset; 541 struct evcnt isc_tx_unicast; 542 uint64_t isc_tx_unicast_offset; 543 struct evcnt isc_tx_multicast; 544 uint64_t isc_tx_multicast_offset; 545 struct evcnt isc_tx_broadcast; 546 uint64_t isc_tx_broadcast_offset; 547 struct evcnt isc_tx_size_64; 548 uint64_t isc_tx_size_64_offset; 549 struct evcnt isc_tx_size_127; 550 uint64_t isc_tx_size_127_offset; 551 struct evcnt isc_tx_size_255; 552 uint64_t isc_tx_size_255_offset; 553 struct evcnt isc_tx_size_511; 554 uint64_t isc_tx_size_511_offset; 555 struct evcnt isc_tx_size_1023; 556 uint64_t isc_tx_size_1023_offset; 557 struct evcnt isc_tx_size_1522; 558 uint64_t isc_tx_size_1522_offset; 559 struct evcnt isc_tx_size_big; 560 uint64_t isc_tx_size_big_offset; 561 struct evcnt isc_mac_local_faults; 562 uint64_t isc_mac_local_faults_offset; 563 struct evcnt isc_mac_remote_faults; 564 uint64_t isc_mac_remote_faults_offset; 565 struct evcnt isc_link_xon_rx; 566 uint64_t isc_link_xon_rx_offset; 567 struct evcnt isc_link_xon_tx; 568 uint64_t isc_link_xon_tx_offset; 569 struct evcnt isc_link_xoff_rx; 570 uint64_t isc_link_xoff_rx_offset; 571 struct evcnt isc_link_xoff_tx; 572 uint64_t isc_link_xoff_tx_offset; 573 struct evcnt isc_vsi_rx_discards; 574 uint64_t isc_vsi_rx_discards_offset; 575 struct evcnt isc_vsi_rx_bytes; 576 uint64_t isc_vsi_rx_bytes_offset; 577 struct evcnt isc_vsi_rx_unicast; 578 uint64_t isc_vsi_rx_unicast_offset; 579 struct evcnt isc_vsi_rx_multicast; 580 uint64_t isc_vsi_rx_multicast_offset; 581 struct evcnt isc_vsi_rx_broadcast; 582 uint64_t isc_vsi_rx_broadcast_offset; 583 struct evcnt isc_vsi_tx_errors; 584 uint64_t isc_vsi_tx_errors_offset; 585 struct evcnt isc_vsi_tx_bytes; 586 uint64_t isc_vsi_tx_bytes_offset; 587 struct evcnt isc_vsi_tx_unicast; 588 uint64_t isc_vsi_tx_unicast_offset; 589 struct evcnt isc_vsi_tx_multicast; 590 uint64_t isc_vsi_tx_multicast_offset; 591 struct evcnt isc_vsi_tx_broadcast; 592 uint64_t isc_vsi_tx_broadcast_offset; 593 }; 594 595 /* 596 * Locking notes: 597 * + a field in ixl_tx_ring is protected by txr_lock (a spin mutex), and 598 * a field in ixl_rx_ring is protected by rxr_lock (a spin mutex). 599 * - more than one lock of them cannot be held at once. 600 * + a field named sc_atq_* in ixl_softc is protected by sc_atq_lock 601 * (a spin mutex). 602 * - the lock cannot held with txr_lock or rxr_lock. 603 * + a field named sc_arq_* is not protected by any lock. 604 * - operations for sc_arq_* is done in one context related to 605 * sc_arq_task. 606 * + other fields in ixl_softc is protected by sc_cfg_lock 607 * (an adaptive mutex) 608 * - It must be held before another lock is held, and It can be 609 * released after the other lock is released. 610 * */ 611 612 struct ixl_softc { 613 device_t sc_dev; 614 struct ethercom sc_ec; 615 bool sc_attached; 616 bool sc_dead; 617 uint32_t sc_port; 618 struct sysctllog *sc_sysctllog; 619 struct workqueue *sc_workq; 620 struct workqueue *sc_workq_txrx; 621 int sc_stats_intval; 622 callout_t sc_stats_callout; 623 struct ixl_work sc_stats_task; 624 struct ixl_stats_counters 625 sc_stats_counters; 626 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 627 struct ifmedia sc_media; 628 uint64_t sc_media_status; 629 uint64_t sc_media_active; 630 uint64_t sc_phy_types; 631 uint8_t sc_phy_abilities; 632 uint8_t sc_phy_linkspeed; 633 uint8_t sc_phy_fec_cfg; 634 uint16_t sc_eee_cap; 635 uint32_t sc_eeer_val; 636 uint8_t sc_d3_lpan; 637 kmutex_t sc_cfg_lock; 638 enum i40e_mac_type sc_mac_type; 639 uint32_t sc_rss_table_size; 640 uint32_t sc_rss_table_entry_width; 641 bool sc_txrx_workqueue; 642 u_int sc_tx_process_limit; 643 u_int sc_rx_process_limit; 644 u_int sc_tx_intr_process_limit; 645 u_int sc_rx_intr_process_limit; 646 647 int sc_cur_ec_capenable; 648 649 struct pci_attach_args sc_pa; 650 pci_intr_handle_t *sc_ihp; 651 void **sc_ihs; 652 unsigned int sc_nintrs; 653 654 bus_dma_tag_t sc_dmat; 655 bus_space_tag_t sc_memt; 656 bus_space_handle_t sc_memh; 657 bus_size_t sc_mems; 658 659 uint8_t sc_pf_id; 660 uint16_t sc_uplink_seid; /* le */ 661 uint16_t sc_downlink_seid; /* le */ 662 uint16_t sc_vsi_number; 663 uint16_t sc_vsi_stat_counter_idx; 664 uint16_t sc_seid; 665 unsigned int sc_base_queue; 666 667 pci_intr_type_t sc_intrtype; 668 unsigned int sc_msix_vector_queue; 669 670 struct ixl_dmamem sc_scratch; 671 struct ixl_dmamem sc_aqbuf; 672 673 const struct ixl_aq_regs * 674 sc_aq_regs; 675 uint32_t sc_aq_flags; 676 #define IXL_SC_AQ_FLAG_RXCTL __BIT(0) 677 #define IXL_SC_AQ_FLAG_NVMLOCK __BIT(1) 678 #define IXL_SC_AQ_FLAG_NVMREAD __BIT(2) 679 #define IXL_SC_AQ_FLAG_RSS __BIT(3) 680 681 kmutex_t sc_atq_lock; 682 kcondvar_t sc_atq_cv; 683 struct ixl_dmamem sc_atq; 684 unsigned int sc_atq_prod; 685 unsigned int sc_atq_cons; 686 687 struct ixl_dmamem sc_arq; 688 struct ixl_work sc_arq_task; 689 struct ixl_aq_bufs sc_arq_idle; 690 struct ixl_aq_buf *sc_arq_live[IXL_AQ_NUM]; 691 unsigned int sc_arq_prod; 692 unsigned int sc_arq_cons; 693 694 struct ixl_work sc_link_state_task; 695 struct ixl_atq sc_link_state_atq; 696 697 struct ixl_dmamem sc_hmc_sd; 698 struct ixl_dmamem sc_hmc_pd; 699 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 700 701 unsigned int sc_tx_ring_ndescs; 702 unsigned int sc_rx_ring_ndescs; 703 unsigned int sc_nqueue_pairs; 704 unsigned int sc_nqueue_pairs_max; 705 unsigned int sc_nqueue_pairs_device; 706 struct ixl_queue_pair *sc_qps; 707 708 struct evcnt sc_event_atq; 709 struct evcnt sc_event_link; 710 struct evcnt sc_event_ecc_err; 711 struct evcnt sc_event_pci_exception; 712 struct evcnt sc_event_crit_err; 713 }; 714 715 #define IXL_TXRX_PROCESS_UNLIMIT UINT_MAX 716 #define IXL_TX_PROCESS_LIMIT 256 717 #define IXL_RX_PROCESS_LIMIT 256 718 #define IXL_TX_INTR_PROCESS_LIMIT 256 719 #define IXL_RX_INTR_PROCESS_LIMIT 0U 720 721 #define IXL_IFCAP_RXCSUM (IFCAP_CSUM_IPv4_Rx | \ 722 IFCAP_CSUM_TCPv4_Rx | \ 723 IFCAP_CSUM_UDPv4_Rx | \ 724 IFCAP_CSUM_TCPv6_Rx | \ 725 IFCAP_CSUM_UDPv6_Rx) 726 #define IXL_IFCAP_TXCSUM (IFCAP_CSUM_IPv4_Tx | \ 727 IFCAP_CSUM_TCPv4_Tx | \ 728 IFCAP_CSUM_UDPv4_Tx | \ 729 IFCAP_CSUM_TCPv6_Tx | \ 730 IFCAP_CSUM_UDPv6_Tx) 731 #define IXL_CSUM_ALL_OFFLOAD (M_CSUM_IPv4 | \ 732 M_CSUM_TCPv4 | M_CSUM_TCPv6 | \ 733 M_CSUM_UDPv4 | M_CSUM_UDPv6) 734 735 #define delaymsec(_x) DELAY(1000 * (_x)) 736 #ifdef IXL_DEBUG 737 #define DDPRINTF(sc, fmt, args...) \ 738 do { \ 739 if ((sc) != NULL) { \ 740 device_printf( \ 741 ((struct ixl_softc *)(sc))->sc_dev, \ 742 ""); \ 743 } \ 744 printf("%s:\t" fmt, __func__, ##args); \ 745 } while (0) 746 #else 747 #define DDPRINTF(sc, fmt, args...) __nothing 748 #endif 749 #ifndef IXL_STATS_INTERVAL_MSEC 750 #define IXL_STATS_INTERVAL_MSEC 10000 751 #endif 752 #ifndef IXL_QUEUE_NUM 753 #define IXL_QUEUE_NUM 0 754 #endif 755 756 static bool ixl_param_nomsix = false; 757 static int ixl_param_stats_interval = IXL_STATS_INTERVAL_MSEC; 758 static int ixl_param_nqps_limit = IXL_QUEUE_NUM; 759 static unsigned int ixl_param_tx_ndescs = 1024; 760 static unsigned int ixl_param_rx_ndescs = 1024; 761 762 static enum i40e_mac_type 763 ixl_mactype(pci_product_id_t); 764 static void ixl_clear_hw(struct ixl_softc *); 765 static int ixl_pf_reset(struct ixl_softc *); 766 767 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 768 bus_size_t, bus_size_t); 769 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 770 771 static int ixl_arq_fill(struct ixl_softc *); 772 static void ixl_arq_unfill(struct ixl_softc *); 773 774 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 775 unsigned int); 776 static void ixl_atq_set(struct ixl_atq *, 777 void (*)(struct ixl_softc *, const struct ixl_aq_desc *)); 778 static int ixl_atq_post_locked(struct ixl_softc *, struct ixl_atq *); 779 static void ixl_atq_done(struct ixl_softc *); 780 static int ixl_atq_exec(struct ixl_softc *, struct ixl_atq *); 781 static int ixl_atq_exec_locked(struct ixl_softc *, struct ixl_atq *); 782 static int ixl_get_version(struct ixl_softc *); 783 static int ixl_get_nvm_version(struct ixl_softc *); 784 static int ixl_get_hw_capabilities(struct ixl_softc *); 785 static int ixl_pxe_clear(struct ixl_softc *); 786 static int ixl_lldp_shut(struct ixl_softc *); 787 static int ixl_get_mac(struct ixl_softc *); 788 static int ixl_get_switch_config(struct ixl_softc *); 789 static int ixl_phy_mask_ints(struct ixl_softc *); 790 static int ixl_get_phy_info(struct ixl_softc *); 791 static int ixl_set_phy_config(struct ixl_softc *, uint8_t, uint8_t, bool); 792 static int ixl_set_phy_autoselect(struct ixl_softc *); 793 static int ixl_restart_an(struct ixl_softc *); 794 static int ixl_hmc(struct ixl_softc *); 795 static void ixl_hmc_free(struct ixl_softc *); 796 static int ixl_get_vsi(struct ixl_softc *); 797 static int ixl_set_vsi(struct ixl_softc *); 798 static void ixl_set_filter_control(struct ixl_softc *); 799 static void ixl_get_link_status(void *); 800 static int ixl_get_link_status_poll(struct ixl_softc *, int *); 801 static void ixl_get_link_status_done(struct ixl_softc *, 802 const struct ixl_aq_desc *); 803 static int ixl_set_link_status_locked(struct ixl_softc *, 804 const struct ixl_aq_desc *); 805 static uint64_t ixl_search_link_speed(uint8_t); 806 static uint8_t ixl_search_baudrate(uint64_t); 807 static void ixl_config_rss(struct ixl_softc *); 808 static int ixl_add_macvlan(struct ixl_softc *, const uint8_t *, 809 uint16_t, uint16_t); 810 static int ixl_remove_macvlan(struct ixl_softc *, const uint8_t *, 811 uint16_t, uint16_t); 812 static void ixl_arq(void *); 813 static void ixl_hmc_pack(void *, const void *, 814 const struct ixl_hmc_pack *, unsigned int); 815 static uint32_t ixl_rd_rx_csr(struct ixl_softc *, uint32_t); 816 static void ixl_wr_rx_csr(struct ixl_softc *, uint32_t, uint32_t); 817 static int ixl_rd16_nvm(struct ixl_softc *, uint16_t, uint16_t *); 818 819 static int ixl_match(device_t, cfdata_t, void *); 820 static void ixl_attach(device_t, device_t, void *); 821 static int ixl_detach(device_t, int); 822 823 static void ixl_media_add(struct ixl_softc *); 824 static int ixl_media_change(struct ifnet *); 825 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 826 static void ixl_watchdog(struct ifnet *); 827 static int ixl_ioctl(struct ifnet *, u_long, void *); 828 static void ixl_start(struct ifnet *); 829 static int ixl_transmit(struct ifnet *, struct mbuf *); 830 static void ixl_deferred_transmit(void *); 831 static int ixl_intr(void *); 832 static int ixl_queue_intr(void *); 833 static int ixl_other_intr(void *); 834 static void ixl_handle_queue(void *); 835 static void ixl_handle_queue_wk(struct work *, void *); 836 static void ixl_sched_handle_queue(struct ixl_softc *, 837 struct ixl_queue_pair *); 838 static int ixl_init(struct ifnet *); 839 static int ixl_init_locked(struct ixl_softc *); 840 static void ixl_stop(struct ifnet *, int); 841 static void ixl_stop_locked(struct ixl_softc *); 842 static int ixl_iff(struct ixl_softc *); 843 static int ixl_ifflags_cb(struct ethercom *); 844 static int ixl_setup_interrupts(struct ixl_softc *); 845 static int ixl_establish_intx(struct ixl_softc *); 846 static int ixl_establish_msix(struct ixl_softc *); 847 static void ixl_enable_queue_intr(struct ixl_softc *, 848 struct ixl_queue_pair *); 849 static void ixl_disable_queue_intr(struct ixl_softc *, 850 struct ixl_queue_pair *); 851 static void ixl_enable_other_intr(struct ixl_softc *); 852 static void ixl_disable_other_intr(struct ixl_softc *); 853 static void ixl_config_queue_intr(struct ixl_softc *); 854 static void ixl_config_other_intr(struct ixl_softc *); 855 856 static struct ixl_tx_ring * 857 ixl_txr_alloc(struct ixl_softc *, unsigned int); 858 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 859 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 860 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 861 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 862 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 863 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 864 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 865 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *, u_int); 866 867 static struct ixl_rx_ring * 868 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 869 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 870 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 871 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 872 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 873 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 874 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 875 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *, u_int); 876 static int ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 877 878 static struct workqueue * 879 ixl_workq_create(const char *, pri_t, int, int); 880 static void ixl_workq_destroy(struct workqueue *); 881 static int ixl_workqs_teardown(device_t); 882 static void ixl_work_set(struct ixl_work *, void (*)(void *), void *); 883 static void ixl_work_add(struct workqueue *, struct ixl_work *); 884 static void ixl_work_wait(struct workqueue *, struct ixl_work *); 885 static void ixl_workq_work(struct work *, void *); 886 static const struct ixl_product * 887 ixl_lookup(const struct pci_attach_args *pa); 888 static void ixl_link_state_update(struct ixl_softc *, 889 const struct ixl_aq_desc *); 890 static int ixl_vlan_cb(struct ethercom *, uint16_t, bool); 891 static int ixl_setup_vlan_hwfilter(struct ixl_softc *); 892 static void ixl_teardown_vlan_hwfilter(struct ixl_softc *); 893 static int ixl_update_macvlan(struct ixl_softc *); 894 static int ixl_setup_interrupts(struct ixl_softc *);; 895 static void ixl_teardown_interrupts(struct ixl_softc *); 896 static int ixl_setup_stats(struct ixl_softc *); 897 static void ixl_teardown_stats(struct ixl_softc *); 898 static void ixl_stats_callout(void *); 899 static void ixl_stats_update(void *); 900 static int ixl_setup_sysctls(struct ixl_softc *); 901 static void ixl_teardown_sysctls(struct ixl_softc *); 902 static int ixl_queue_pairs_alloc(struct ixl_softc *); 903 static void ixl_queue_pairs_free(struct ixl_softc *); 904 905 static const struct ixl_phy_type ixl_phy_type_map[] = { 906 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 907 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 908 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 909 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 910 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 911 { 1ULL << IXL_PHY_TYPE_XAUI | 912 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 913 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 914 { 1ULL << IXL_PHY_TYPE_XLAUI | 915 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 916 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 917 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 918 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 919 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 920 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 921 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 922 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 923 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 924 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 925 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 926 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 927 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 928 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_TWINAX }, 929 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 930 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 931 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 932 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 933 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 934 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 935 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 936 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 937 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 938 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 939 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_ACC }, 940 }; 941 942 static const struct ixl_speed_type ixl_speed_type_map[] = { 943 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 944 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 945 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 946 { IXL_AQ_LINK_SPEED_1000MB, IF_Mbps(1000) }, 947 { IXL_AQ_LINK_SPEED_100MB, IF_Mbps(100)}, 948 }; 949 950 static const struct ixl_aq_regs ixl_pf_aq_regs = { 951 .atq_tail = I40E_PF_ATQT, 952 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 953 .atq_head = I40E_PF_ATQH, 954 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 955 .atq_len = I40E_PF_ATQLEN, 956 .atq_bal = I40E_PF_ATQBAL, 957 .atq_bah = I40E_PF_ATQBAH, 958 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 959 960 .arq_tail = I40E_PF_ARQT, 961 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 962 .arq_head = I40E_PF_ARQH, 963 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 964 .arq_len = I40E_PF_ARQLEN, 965 .arq_bal = I40E_PF_ARQBAL, 966 .arq_bah = I40E_PF_ARQBAH, 967 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 968 }; 969 970 #define ixl_rd(_s, _r) \ 971 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 972 #define ixl_wr(_s, _r, _v) \ 973 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 974 #define ixl_barrier(_s, _r, _l, _o) \ 975 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 976 #define ixl_flush(_s) (void)ixl_rd((_s), I40E_GLGEN_STAT) 977 #define ixl_nqueues(_sc) (1 << ((_sc)->sc_nqueue_pairs - 1)) 978 979 static inline uint32_t 980 ixl_dmamem_hi(struct ixl_dmamem *ixm) 981 { 982 uint32_t retval; 983 uint64_t val; 984 985 if (sizeof(IXL_DMA_DVA(ixm)) > 4) { 986 val = (intptr_t)IXL_DMA_DVA(ixm); 987 retval = (uint32_t)(val >> 32); 988 } else { 989 retval = 0; 990 } 991 992 return retval; 993 } 994 995 static inline uint32_t 996 ixl_dmamem_lo(struct ixl_dmamem *ixm) 997 { 998 999 return (uint32_t)IXL_DMA_DVA(ixm); 1000 } 1001 1002 static inline void 1003 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 1004 { 1005 uint64_t val; 1006 1007 if (sizeof(addr) > 4) { 1008 val = (intptr_t)addr; 1009 iaq->iaq_param[2] = htole32(val >> 32); 1010 } else { 1011 iaq->iaq_param[2] = htole32(0); 1012 } 1013 1014 iaq->iaq_param[3] = htole32(addr); 1015 } 1016 1017 static inline unsigned int 1018 ixl_rxr_unrefreshed(unsigned int prod, unsigned int cons, unsigned int ndescs) 1019 { 1020 unsigned int num; 1021 1022 if (prod < cons) 1023 num = cons - prod; 1024 else 1025 num = (ndescs - prod) + cons; 1026 1027 if (__predict_true(num > 0)) { 1028 /* device cannot receive packets if all descripter is filled */ 1029 num -= 1; 1030 } 1031 1032 return num; 1033 } 1034 1035 CFATTACH_DECL3_NEW(ixl, sizeof(struct ixl_softc), 1036 ixl_match, ixl_attach, ixl_detach, NULL, NULL, NULL, 1037 DVF_DETACH_SHUTDOWN); 1038 1039 static const struct ixl_product ixl_products[] = { 1040 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_SFP }, 1041 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_KX_B }, 1042 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_KX_C }, 1043 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_A }, 1044 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_B }, 1045 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_C }, 1046 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T }, 1047 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 1048 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 1049 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 1050 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 1051 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28 }, 1052 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_KX }, 1053 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_QSFP }, 1054 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_SFP }, 1055 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G_BASET }, 1056 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_BASET }, 1057 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_I_SFP }, 1058 /* required last entry */ 1059 {0, 0} 1060 }; 1061 1062 static const struct ixl_product * 1063 ixl_lookup(const struct pci_attach_args *pa) 1064 { 1065 const struct ixl_product *ixlp; 1066 1067 for (ixlp = ixl_products; ixlp->vendor_id != 0; ixlp++) { 1068 if (PCI_VENDOR(pa->pa_id) == ixlp->vendor_id && 1069 PCI_PRODUCT(pa->pa_id) == ixlp->product_id) 1070 return ixlp; 1071 } 1072 1073 return NULL; 1074 } 1075 1076 static int 1077 ixl_match(device_t parent, cfdata_t match, void *aux) 1078 { 1079 const struct pci_attach_args *pa = aux; 1080 1081 return (ixl_lookup(pa) != NULL) ? 1 : 0; 1082 } 1083 1084 static void 1085 ixl_attach(device_t parent, device_t self, void *aux) 1086 { 1087 struct ixl_softc *sc; 1088 struct pci_attach_args *pa = aux; 1089 struct ifnet *ifp; 1090 pcireg_t memtype; 1091 uint32_t firstq, port, ari, func; 1092 char xnamebuf[32]; 1093 int tries, rv, link; 1094 1095 sc = device_private(self); 1096 sc->sc_dev = self; 1097 ifp = &sc->sc_ec.ec_if; 1098 1099 sc->sc_pa = *pa; 1100 sc->sc_dmat = (pci_dma64_available(pa)) ? 1101 pa->pa_dmat64 : pa->pa_dmat; 1102 sc->sc_aq_regs = &ixl_pf_aq_regs; 1103 1104 sc->sc_mac_type = ixl_mactype(PCI_PRODUCT(pa->pa_id)); 1105 1106 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IXL_PCIREG); 1107 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1108 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 1109 aprint_error(": unable to map registers\n"); 1110 return; 1111 } 1112 1113 mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET); 1114 1115 firstq = ixl_rd(sc, I40E_PFLAN_QALLOC); 1116 firstq &= I40E_PFLAN_QALLOC_FIRSTQ_MASK; 1117 firstq >>= I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1118 sc->sc_base_queue = firstq; 1119 1120 ixl_clear_hw(sc); 1121 if (ixl_pf_reset(sc) == -1) { 1122 /* error printed by ixl pf_reset */ 1123 goto unmap; 1124 } 1125 1126 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1127 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1128 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1129 sc->sc_port = port; 1130 aprint_normal(": port %u", sc->sc_port); 1131 1132 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1133 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1134 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1135 1136 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1137 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1138 1139 /* initialise the adminq */ 1140 1141 mutex_init(&sc->sc_atq_lock, MUTEX_DEFAULT, IPL_NET); 1142 1143 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1144 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1145 aprint_error("\n" "%s: unable to allocate atq\n", 1146 device_xname(self)); 1147 goto unmap; 1148 } 1149 1150 SIMPLEQ_INIT(&sc->sc_arq_idle); 1151 ixl_work_set(&sc->sc_arq_task, ixl_arq, sc); 1152 sc->sc_arq_cons = 0; 1153 sc->sc_arq_prod = 0; 1154 1155 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1156 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1157 aprint_error("\n" "%s: unable to allocate arq\n", 1158 device_xname(self)); 1159 goto free_atq; 1160 } 1161 1162 if (!ixl_arq_fill(sc)) { 1163 aprint_error("\n" "%s: unable to fill arq descriptors\n", 1164 device_xname(self)); 1165 goto free_arq; 1166 } 1167 1168 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1169 0, IXL_DMA_LEN(&sc->sc_atq), 1170 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1171 1172 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1173 0, IXL_DMA_LEN(&sc->sc_arq), 1174 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1175 1176 for (tries = 0; tries < 10; tries++) { 1177 sc->sc_atq_cons = 0; 1178 sc->sc_atq_prod = 0; 1179 1180 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1181 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1182 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1183 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1184 1185 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1186 1187 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1188 ixl_dmamem_lo(&sc->sc_atq)); 1189 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1190 ixl_dmamem_hi(&sc->sc_atq)); 1191 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1192 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1193 1194 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1195 ixl_dmamem_lo(&sc->sc_arq)); 1196 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1197 ixl_dmamem_hi(&sc->sc_arq)); 1198 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1199 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1200 1201 rv = ixl_get_version(sc); 1202 if (rv == 0) 1203 break; 1204 if (rv != ETIMEDOUT) { 1205 aprint_error(", unable to get firmware version\n"); 1206 goto shutdown; 1207 } 1208 1209 delaymsec(100); 1210 } 1211 1212 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1213 1214 if (ixl_dmamem_alloc(sc, &sc->sc_aqbuf, IXL_AQ_BUFLEN, 0) != 0) { 1215 aprint_error_dev(self, ", unable to allocate nvm buffer\n"); 1216 goto shutdown; 1217 } 1218 1219 ixl_get_nvm_version(sc); 1220 1221 if (sc->sc_mac_type == I40E_MAC_X722) 1222 sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_X722; 1223 else 1224 sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_XL710; 1225 1226 rv = ixl_get_hw_capabilities(sc); 1227 if (rv != 0) { 1228 aprint_error(", GET HW CAPABILITIES %s\n", 1229 rv == ETIMEDOUT ? "timeout" : "error"); 1230 goto free_aqbuf; 1231 } 1232 1233 sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_device, ncpu); 1234 if (ixl_param_nqps_limit > 0) { 1235 sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_max, 1236 ixl_param_nqps_limit); 1237 } 1238 1239 sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max; 1240 sc->sc_tx_ring_ndescs = ixl_param_tx_ndescs; 1241 sc->sc_rx_ring_ndescs = ixl_param_rx_ndescs; 1242 1243 KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_rx_ring_ndescs); 1244 KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_tx_ring_ndescs); 1245 1246 if (ixl_get_mac(sc) != 0) { 1247 /* error printed by ixl_get_mac */ 1248 goto free_aqbuf; 1249 } 1250 1251 aprint_normal("\n"); 1252 aprint_naive("\n"); 1253 1254 aprint_normal_dev(self, "Ethernet address %s\n", 1255 ether_sprintf(sc->sc_enaddr)); 1256 1257 rv = ixl_pxe_clear(sc); 1258 if (rv != 0) { 1259 aprint_debug_dev(self, "CLEAR PXE MODE %s\n", 1260 rv == ETIMEDOUT ? "timeout" : "error"); 1261 } 1262 1263 ixl_set_filter_control(sc); 1264 1265 if (ixl_hmc(sc) != 0) { 1266 /* error printed by ixl_hmc */ 1267 goto free_aqbuf; 1268 } 1269 1270 if (ixl_lldp_shut(sc) != 0) { 1271 /* error printed by ixl_lldp_shut */ 1272 goto free_hmc; 1273 } 1274 1275 if (ixl_phy_mask_ints(sc) != 0) { 1276 /* error printed by ixl_phy_mask_ints */ 1277 goto free_hmc; 1278 } 1279 1280 if (ixl_restart_an(sc) != 0) { 1281 /* error printed by ixl_restart_an */ 1282 goto free_hmc; 1283 } 1284 1285 if (ixl_get_switch_config(sc) != 0) { 1286 /* error printed by ixl_get_switch_config */ 1287 goto free_hmc; 1288 } 1289 1290 rv = ixl_get_link_status_poll(sc, NULL); 1291 if (rv != 0) { 1292 aprint_error_dev(self, "GET LINK STATUS %s\n", 1293 rv == ETIMEDOUT ? "timeout" : "error"); 1294 goto free_hmc; 1295 } 1296 1297 /* 1298 * The FW often returns EIO in "Get PHY Abilities" command 1299 * if there is no delay 1300 */ 1301 DELAY(500); 1302 if (ixl_get_phy_info(sc) != 0) { 1303 /* error printed by ixl_get_phy_info */ 1304 goto free_hmc; 1305 } 1306 1307 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1308 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1309 aprint_error_dev(self, "unable to allocate scratch buffer\n"); 1310 goto free_hmc; 1311 } 1312 1313 rv = ixl_get_vsi(sc); 1314 if (rv != 0) { 1315 aprint_error_dev(self, "GET VSI %s %d\n", 1316 rv == ETIMEDOUT ? "timeout" : "error", rv); 1317 goto free_scratch; 1318 } 1319 1320 rv = ixl_set_vsi(sc); 1321 if (rv != 0) { 1322 aprint_error_dev(self, "UPDATE VSI error %s %d\n", 1323 rv == ETIMEDOUT ? "timeout" : "error", rv); 1324 goto free_scratch; 1325 } 1326 1327 if (ixl_queue_pairs_alloc(sc) != 0) { 1328 /* error printed by ixl_queue_pairs_alloc */ 1329 goto free_scratch; 1330 } 1331 1332 if (ixl_setup_interrupts(sc) != 0) { 1333 /* error printed by ixl_setup_interrupts */ 1334 goto free_queue_pairs; 1335 } 1336 1337 if (ixl_setup_stats(sc) != 0) { 1338 aprint_error_dev(self, "failed to setup event counters\n"); 1339 goto teardown_intrs; 1340 } 1341 1342 if (ixl_setup_sysctls(sc) != 0) { 1343 /* error printed by ixl_setup_sysctls */ 1344 goto teardown_stats; 1345 } 1346 1347 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self)); 1348 sc->sc_workq = ixl_workq_create(xnamebuf, IXL_WORKQUEUE_PRI, 1349 IPL_NET, WQ_MPSAFE); 1350 if (sc->sc_workq == NULL) 1351 goto teardown_sysctls; 1352 1353 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self)); 1354 rv = workqueue_create(&sc->sc_workq_txrx, xnamebuf, ixl_handle_queue_wk, 1355 sc, IXL_WORKQUEUE_PRI, IPL_NET, WQ_PERCPU | WQ_MPSAFE); 1356 if (rv != 0) { 1357 sc->sc_workq_txrx = NULL; 1358 goto teardown_wqs; 1359 } 1360 1361 snprintf(xnamebuf, sizeof(xnamebuf), "%s_atq_cv", device_xname(self)); 1362 cv_init(&sc->sc_atq_cv, xnamebuf); 1363 1364 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1365 1366 ifp->if_softc = sc; 1367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1368 ifp->if_extflags = IFEF_MPSAFE; 1369 ifp->if_ioctl = ixl_ioctl; 1370 ifp->if_start = ixl_start; 1371 ifp->if_transmit = ixl_transmit; 1372 ifp->if_watchdog = ixl_watchdog; 1373 ifp->if_init = ixl_init; 1374 ifp->if_stop = ixl_stop; 1375 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1376 IFQ_SET_READY(&ifp->if_snd); 1377 ifp->if_capabilities |= IXL_IFCAP_RXCSUM; 1378 ifp->if_capabilities |= IXL_IFCAP_TXCSUM; 1379 #if 0 1380 ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6; 1381 #endif 1382 ether_set_vlan_cb(&sc->sc_ec, ixl_vlan_cb); 1383 sc->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1384 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1385 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER; 1386 1387 sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities; 1388 /* Disable VLAN_HWFILTER by default */ 1389 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1390 1391 sc->sc_cur_ec_capenable = sc->sc_ec.ec_capenable; 1392 1393 sc->sc_ec.ec_ifmedia = &sc->sc_media; 1394 ifmedia_init(&sc->sc_media, IFM_IMASK, ixl_media_change, 1395 ixl_media_status); 1396 1397 ixl_media_add(sc); 1398 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1399 if (ISSET(sc->sc_phy_abilities, 1400 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) { 1401 ifmedia_add(&sc->sc_media, 1402 IFM_ETHER | IFM_AUTO | IFM_FLOW, 0, NULL); 1403 } 1404 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_NONE, 0, NULL); 1405 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1406 1407 if_attach(ifp); 1408 if_deferred_start_init(ifp, NULL); 1409 ether_ifattach(ifp, sc->sc_enaddr); 1410 ether_set_ifflags_cb(&sc->sc_ec, ixl_ifflags_cb); 1411 1412 rv = ixl_get_link_status_poll(sc, &link); 1413 if (rv != 0) 1414 link = LINK_STATE_UNKNOWN; 1415 if_link_state_change(ifp, link); 1416 1417 ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done); 1418 ixl_work_set(&sc->sc_link_state_task, ixl_get_link_status, sc); 1419 1420 ixl_config_other_intr(sc); 1421 ixl_enable_other_intr(sc); 1422 1423 ixl_set_phy_autoselect(sc); 1424 1425 /* remove default mac filter and replace it so we can see vlans */ 1426 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 0); 1427 if (rv != ENOENT) { 1428 aprint_debug_dev(self, 1429 "unable to remove macvlan %u\n", rv); 1430 } 1431 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 1432 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1433 if (rv != ENOENT) { 1434 aprint_debug_dev(self, 1435 "unable to remove macvlan, ignore vlan %u\n", rv); 1436 } 1437 1438 if (ixl_update_macvlan(sc) != 0) { 1439 aprint_debug_dev(self, 1440 "couldn't enable vlan hardware filter\n"); 1441 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1442 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 1443 } 1444 1445 sc->sc_txrx_workqueue = true; 1446 sc->sc_tx_process_limit = IXL_TX_PROCESS_LIMIT; 1447 sc->sc_rx_process_limit = IXL_RX_PROCESS_LIMIT; 1448 sc->sc_tx_intr_process_limit = IXL_TX_INTR_PROCESS_LIMIT; 1449 sc->sc_rx_intr_process_limit = IXL_RX_INTR_PROCESS_LIMIT; 1450 1451 ixl_stats_update(sc); 1452 sc->sc_stats_counters.isc_has_offset = true; 1453 1454 if (pmf_device_register(self, NULL, NULL) != true) 1455 aprint_debug_dev(self, "couldn't establish power handler\n"); 1456 sc->sc_attached = true; 1457 return; 1458 1459 teardown_wqs: 1460 config_finalize_register(self, ixl_workqs_teardown); 1461 teardown_sysctls: 1462 ixl_teardown_sysctls(sc); 1463 teardown_stats: 1464 ixl_teardown_stats(sc); 1465 teardown_intrs: 1466 ixl_teardown_interrupts(sc); 1467 free_queue_pairs: 1468 ixl_queue_pairs_free(sc); 1469 free_scratch: 1470 ixl_dmamem_free(sc, &sc->sc_scratch); 1471 free_hmc: 1472 ixl_hmc_free(sc); 1473 free_aqbuf: 1474 ixl_dmamem_free(sc, &sc->sc_aqbuf); 1475 shutdown: 1476 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1477 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1478 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1479 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1480 1481 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1482 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1483 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1484 1485 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1486 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1487 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1488 1489 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1490 0, IXL_DMA_LEN(&sc->sc_arq), 1491 BUS_DMASYNC_POSTREAD); 1492 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1493 0, IXL_DMA_LEN(&sc->sc_atq), 1494 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1495 1496 ixl_arq_unfill(sc); 1497 free_arq: 1498 ixl_dmamem_free(sc, &sc->sc_arq); 1499 free_atq: 1500 ixl_dmamem_free(sc, &sc->sc_atq); 1501 unmap: 1502 mutex_destroy(&sc->sc_atq_lock); 1503 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1504 mutex_destroy(&sc->sc_cfg_lock); 1505 sc->sc_mems = 0; 1506 1507 sc->sc_attached = false; 1508 } 1509 1510 static int 1511 ixl_detach(device_t self, int flags) 1512 { 1513 struct ixl_softc *sc = device_private(self); 1514 struct ifnet *ifp = &sc->sc_ec.ec_if; 1515 1516 if (!sc->sc_attached) 1517 return 0; 1518 1519 ixl_stop(ifp, 1); 1520 1521 ixl_disable_other_intr(sc); 1522 1523 callout_halt(&sc->sc_stats_callout, NULL); 1524 ixl_work_wait(sc->sc_workq, &sc->sc_stats_task); 1525 1526 /* wait for ATQ handler */ 1527 mutex_enter(&sc->sc_atq_lock); 1528 mutex_exit(&sc->sc_atq_lock); 1529 1530 ixl_work_wait(sc->sc_workq, &sc->sc_arq_task); 1531 ixl_work_wait(sc->sc_workq, &sc->sc_link_state_task); 1532 1533 if (sc->sc_workq != NULL) { 1534 ixl_workq_destroy(sc->sc_workq); 1535 sc->sc_workq = NULL; 1536 } 1537 1538 if (sc->sc_workq_txrx != NULL) { 1539 workqueue_destroy(sc->sc_workq_txrx); 1540 sc->sc_workq_txrx = NULL; 1541 } 1542 1543 ether_ifdetach(ifp); 1544 if_detach(ifp); 1545 ifmedia_fini(&sc->sc_media); 1546 1547 ixl_teardown_interrupts(sc); 1548 ixl_teardown_stats(sc); 1549 ixl_teardown_sysctls(sc); 1550 1551 ixl_queue_pairs_free(sc); 1552 1553 ixl_dmamem_free(sc, &sc->sc_scratch); 1554 ixl_hmc_free(sc); 1555 1556 /* shutdown */ 1557 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1558 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1559 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1560 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1561 1562 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1563 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1564 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1565 1566 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1567 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1568 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1569 1570 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1571 0, IXL_DMA_LEN(&sc->sc_arq), 1572 BUS_DMASYNC_POSTREAD); 1573 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1574 0, IXL_DMA_LEN(&sc->sc_atq), 1575 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1576 1577 ixl_arq_unfill(sc); 1578 1579 ixl_dmamem_free(sc, &sc->sc_arq); 1580 ixl_dmamem_free(sc, &sc->sc_atq); 1581 ixl_dmamem_free(sc, &sc->sc_aqbuf); 1582 1583 cv_destroy(&sc->sc_atq_cv); 1584 mutex_destroy(&sc->sc_atq_lock); 1585 1586 if (sc->sc_mems != 0) { 1587 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1588 sc->sc_mems = 0; 1589 } 1590 1591 mutex_destroy(&sc->sc_cfg_lock); 1592 1593 return 0; 1594 } 1595 1596 static int 1597 ixl_workqs_teardown(device_t self) 1598 { 1599 struct ixl_softc *sc = device_private(self); 1600 1601 if (sc->sc_workq != NULL) { 1602 ixl_workq_destroy(sc->sc_workq); 1603 sc->sc_workq = NULL; 1604 } 1605 1606 if (sc->sc_workq_txrx != NULL) { 1607 workqueue_destroy(sc->sc_workq_txrx); 1608 sc->sc_workq_txrx = NULL; 1609 } 1610 1611 return 0; 1612 } 1613 1614 static int 1615 ixl_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 1616 { 1617 struct ifnet *ifp = &ec->ec_if; 1618 struct ixl_softc *sc = ifp->if_softc; 1619 int rv; 1620 1621 if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 1622 return 0; 1623 } 1624 1625 if (set) { 1626 rv = ixl_add_macvlan(sc, sc->sc_enaddr, vid, 1627 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 1628 if (rv == 0) { 1629 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 1630 vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 1631 } 1632 } else { 1633 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, vid, 1634 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 1635 (void)ixl_remove_macvlan(sc, etherbroadcastaddr, vid, 1636 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 1637 } 1638 1639 return rv; 1640 } 1641 1642 static void 1643 ixl_media_add(struct ixl_softc *sc) 1644 { 1645 struct ifmedia *ifm = &sc->sc_media; 1646 const struct ixl_phy_type *itype; 1647 unsigned int i; 1648 bool flow; 1649 1650 if (ISSET(sc->sc_phy_abilities, 1651 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) { 1652 flow = true; 1653 } else { 1654 flow = false; 1655 } 1656 1657 for (i = 0; i < __arraycount(ixl_phy_type_map); i++) { 1658 itype = &ixl_phy_type_map[i]; 1659 1660 if (ISSET(sc->sc_phy_types, itype->phy_type)) { 1661 ifmedia_add(ifm, 1662 IFM_ETHER | IFM_FDX | itype->ifm_type, 0, NULL); 1663 1664 if (flow) { 1665 ifmedia_add(ifm, 1666 IFM_ETHER | IFM_FDX | IFM_FLOW | 1667 itype->ifm_type, 0, NULL); 1668 } 1669 1670 if (itype->ifm_type != IFM_100_TX) 1671 continue; 1672 1673 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 1674 0, NULL); 1675 if (flow) { 1676 ifmedia_add(ifm, 1677 IFM_ETHER | IFM_FLOW | itype->ifm_type, 1678 0, NULL); 1679 } 1680 } 1681 } 1682 } 1683 1684 static void 1685 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1686 { 1687 struct ixl_softc *sc = ifp->if_softc; 1688 1689 mutex_enter(&sc->sc_cfg_lock); 1690 ifmr->ifm_status = sc->sc_media_status; 1691 ifmr->ifm_active = sc->sc_media_active; 1692 mutex_exit(&sc->sc_cfg_lock); 1693 } 1694 1695 static int 1696 ixl_media_change(struct ifnet *ifp) 1697 { 1698 struct ixl_softc *sc = ifp->if_softc; 1699 struct ifmedia *ifm = &sc->sc_media; 1700 uint64_t ifm_active = sc->sc_media_active; 1701 uint8_t link_speed, abilities; 1702 1703 switch (IFM_SUBTYPE(ifm_active)) { 1704 case IFM_1000_SGMII: 1705 case IFM_1000_KX: 1706 case IFM_10G_KX4: 1707 case IFM_10G_KR: 1708 case IFM_40G_KR4: 1709 case IFM_20G_KR2: 1710 case IFM_25G_KR: 1711 /* backplanes */ 1712 return EINVAL; 1713 } 1714 1715 abilities = IXL_PHY_ABILITY_AUTONEGO | IXL_PHY_ABILITY_LINKUP; 1716 1717 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1718 case IFM_AUTO: 1719 link_speed = sc->sc_phy_linkspeed; 1720 break; 1721 case IFM_NONE: 1722 link_speed = 0; 1723 CLR(abilities, IXL_PHY_ABILITY_LINKUP); 1724 break; 1725 default: 1726 link_speed = ixl_search_baudrate( 1727 ifmedia_baudrate(ifm->ifm_media)); 1728 } 1729 1730 if (ISSET(abilities, IXL_PHY_ABILITY_LINKUP)) { 1731 if (ISSET(link_speed, sc->sc_phy_linkspeed) == 0) 1732 return EINVAL; 1733 } 1734 1735 if (ifm->ifm_media & IFM_FLOW) { 1736 abilities |= sc->sc_phy_abilities & 1737 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX); 1738 } 1739 1740 return ixl_set_phy_config(sc, link_speed, abilities, false); 1741 } 1742 1743 static void 1744 ixl_watchdog(struct ifnet *ifp) 1745 { 1746 1747 } 1748 1749 static void 1750 ixl_del_all_multiaddr(struct ixl_softc *sc) 1751 { 1752 struct ethercom *ec = &sc->sc_ec; 1753 struct ether_multi *enm; 1754 struct ether_multistep step; 1755 1756 ETHER_LOCK(ec); 1757 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1758 ETHER_NEXT_MULTI(step, enm)) { 1759 ixl_remove_macvlan(sc, enm->enm_addrlo, 0, 1760 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1761 } 1762 ETHER_UNLOCK(ec); 1763 } 1764 1765 static int 1766 ixl_add_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1767 { 1768 struct ifnet *ifp = &sc->sc_ec.ec_if; 1769 int rv; 1770 1771 if (ISSET(ifp->if_flags, IFF_ALLMULTI)) 1772 return 0; 1773 1774 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) { 1775 ixl_del_all_multiaddr(sc); 1776 SET(ifp->if_flags, IFF_ALLMULTI); 1777 return ENETRESET; 1778 } 1779 1780 /* multicast address can not use VLAN HWFILTER */ 1781 rv = ixl_add_macvlan(sc, addrlo, 0, 1782 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1783 1784 if (rv == ENOSPC) { 1785 ixl_del_all_multiaddr(sc); 1786 SET(ifp->if_flags, IFF_ALLMULTI); 1787 return ENETRESET; 1788 } 1789 1790 return rv; 1791 } 1792 1793 static int 1794 ixl_del_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1795 { 1796 struct ifnet *ifp = &sc->sc_ec.ec_if; 1797 struct ethercom *ec = &sc->sc_ec; 1798 struct ether_multi *enm, *enm_last; 1799 struct ether_multistep step; 1800 int error, rv = 0; 1801 1802 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1803 ixl_remove_macvlan(sc, addrlo, 0, 1804 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1805 return 0; 1806 } 1807 1808 ETHER_LOCK(ec); 1809 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1810 ETHER_NEXT_MULTI(step, enm)) { 1811 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1812 ETHER_ADDR_LEN) != 0) { 1813 goto out; 1814 } 1815 } 1816 1817 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1818 ETHER_NEXT_MULTI(step, enm)) { 1819 error = ixl_add_macvlan(sc, enm->enm_addrlo, 0, 1820 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1821 if (error != 0) 1822 break; 1823 } 1824 1825 if (enm != NULL) { 1826 enm_last = enm; 1827 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1828 ETHER_NEXT_MULTI(step, enm)) { 1829 if (enm == enm_last) 1830 break; 1831 1832 ixl_remove_macvlan(sc, enm->enm_addrlo, 0, 1833 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1834 } 1835 } else { 1836 CLR(ifp->if_flags, IFF_ALLMULTI); 1837 rv = ENETRESET; 1838 } 1839 1840 out: 1841 ETHER_UNLOCK(ec); 1842 return rv; 1843 } 1844 1845 static int 1846 ixl_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1847 { 1848 struct ifreq *ifr = (struct ifreq *)data; 1849 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 1850 const struct sockaddr *sa; 1851 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 1852 int s, error = 0; 1853 unsigned int nmtu; 1854 1855 switch (cmd) { 1856 case SIOCSIFMTU: 1857 nmtu = ifr->ifr_mtu; 1858 1859 if (nmtu < IXL_MIN_MTU || nmtu > IXL_MAX_MTU) { 1860 error = EINVAL; 1861 break; 1862 } 1863 if (ifp->if_mtu != nmtu) { 1864 s = splnet(); 1865 error = ether_ioctl(ifp, cmd, data); 1866 splx(s); 1867 if (error == ENETRESET) 1868 error = ixl_init(ifp); 1869 } 1870 break; 1871 case SIOCADDMULTI: 1872 sa = ifreq_getaddr(SIOCADDMULTI, ifr); 1873 if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) { 1874 error = ether_multiaddr(sa, addrlo, addrhi); 1875 if (error != 0) 1876 return error; 1877 1878 error = ixl_add_multi(sc, addrlo, addrhi); 1879 if (error != 0 && error != ENETRESET) { 1880 ether_delmulti(sa, &sc->sc_ec); 1881 error = EIO; 1882 } 1883 } 1884 break; 1885 1886 case SIOCDELMULTI: 1887 sa = ifreq_getaddr(SIOCDELMULTI, ifr); 1888 if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) { 1889 error = ether_multiaddr(sa, addrlo, addrhi); 1890 if (error != 0) 1891 return error; 1892 1893 error = ixl_del_multi(sc, addrlo, addrhi); 1894 } 1895 break; 1896 1897 default: 1898 s = splnet(); 1899 error = ether_ioctl(ifp, cmd, data); 1900 splx(s); 1901 } 1902 1903 if (error == ENETRESET) 1904 error = ixl_iff(sc); 1905 1906 return error; 1907 } 1908 1909 static enum i40e_mac_type 1910 ixl_mactype(pci_product_id_t id) 1911 { 1912 1913 switch (id) { 1914 case PCI_PRODUCT_INTEL_XL710_SFP: 1915 case PCI_PRODUCT_INTEL_XL710_KX_B: 1916 case PCI_PRODUCT_INTEL_XL710_KX_C: 1917 case PCI_PRODUCT_INTEL_XL710_QSFP_A: 1918 case PCI_PRODUCT_INTEL_XL710_QSFP_B: 1919 case PCI_PRODUCT_INTEL_XL710_QSFP_C: 1920 case PCI_PRODUCT_INTEL_X710_10G_T: 1921 case PCI_PRODUCT_INTEL_XL710_20G_BP_1: 1922 case PCI_PRODUCT_INTEL_XL710_20G_BP_2: 1923 case PCI_PRODUCT_INTEL_X710_T4_10G: 1924 case PCI_PRODUCT_INTEL_XXV710_25G_BP: 1925 case PCI_PRODUCT_INTEL_XXV710_25G_SFP28: 1926 return I40E_MAC_XL710; 1927 1928 case PCI_PRODUCT_INTEL_X722_KX: 1929 case PCI_PRODUCT_INTEL_X722_QSFP: 1930 case PCI_PRODUCT_INTEL_X722_SFP: 1931 case PCI_PRODUCT_INTEL_X722_1G_BASET: 1932 case PCI_PRODUCT_INTEL_X722_10G_BASET: 1933 case PCI_PRODUCT_INTEL_X722_I_SFP: 1934 return I40E_MAC_X722; 1935 } 1936 1937 return I40E_MAC_GENERIC; 1938 } 1939 1940 static inline void * 1941 ixl_hmc_kva(struct ixl_softc *sc, enum ixl_hmc_types type, unsigned int i) 1942 { 1943 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 1944 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 1945 1946 if (i >= e->hmc_count) 1947 return NULL; 1948 1949 kva += e->hmc_base; 1950 kva += i * e->hmc_size; 1951 1952 return kva; 1953 } 1954 1955 static inline size_t 1956 ixl_hmc_len(struct ixl_softc *sc, enum ixl_hmc_types type) 1957 { 1958 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 1959 1960 return e->hmc_size; 1961 } 1962 1963 static void 1964 ixl_enable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp) 1965 { 1966 struct ixl_rx_ring *rxr = qp->qp_rxr; 1967 1968 ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid), 1969 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1970 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1971 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1972 ixl_flush(sc); 1973 } 1974 1975 static void 1976 ixl_disable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp) 1977 { 1978 struct ixl_rx_ring *rxr = qp->qp_rxr; 1979 1980 ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid), 1981 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1982 ixl_flush(sc); 1983 } 1984 1985 static void 1986 ixl_enable_other_intr(struct ixl_softc *sc) 1987 { 1988 1989 ixl_wr(sc, I40E_PFINT_DYN_CTL0, 1990 I40E_PFINT_DYN_CTL0_INTENA_MASK | 1991 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 1992 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)); 1993 ixl_flush(sc); 1994 } 1995 1996 static void 1997 ixl_disable_other_intr(struct ixl_softc *sc) 1998 { 1999 2000 ixl_wr(sc, I40E_PFINT_DYN_CTL0, 2001 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)); 2002 ixl_flush(sc); 2003 } 2004 2005 static int 2006 ixl_reinit(struct ixl_softc *sc) 2007 { 2008 struct ixl_rx_ring *rxr; 2009 struct ixl_tx_ring *txr; 2010 unsigned int i; 2011 uint32_t reg; 2012 2013 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2014 2015 if (ixl_get_vsi(sc) != 0) 2016 return EIO; 2017 2018 if (ixl_set_vsi(sc) != 0) 2019 return EIO; 2020 2021 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2022 txr = sc->sc_qps[i].qp_txr; 2023 rxr = sc->sc_qps[i].qp_rxr; 2024 2025 ixl_txr_config(sc, txr); 2026 ixl_rxr_config(sc, rxr); 2027 } 2028 2029 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2030 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_PREWRITE); 2031 2032 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2033 txr = sc->sc_qps[i].qp_txr; 2034 rxr = sc->sc_qps[i].qp_rxr; 2035 2036 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 2037 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 2038 ixl_flush(sc); 2039 2040 ixl_wr(sc, txr->txr_tail, txr->txr_prod); 2041 ixl_wr(sc, rxr->rxr_tail, rxr->rxr_prod); 2042 2043 /* ixl_rxfill() needs lock held */ 2044 mutex_enter(&rxr->rxr_lock); 2045 ixl_rxfill(sc, rxr); 2046 mutex_exit(&rxr->rxr_lock); 2047 2048 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2049 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2050 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2051 if (ixl_rxr_enabled(sc, rxr) != 0) 2052 goto stop; 2053 2054 ixl_txr_qdis(sc, txr, 1); 2055 2056 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2057 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2058 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2059 2060 if (ixl_txr_enabled(sc, txr) != 0) 2061 goto stop; 2062 } 2063 2064 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2065 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE); 2066 2067 return 0; 2068 2069 stop: 2070 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2071 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE); 2072 2073 return ETIMEDOUT; 2074 } 2075 2076 static int 2077 ixl_init_locked(struct ixl_softc *sc) 2078 { 2079 struct ifnet *ifp = &sc->sc_ec.ec_if; 2080 unsigned int i; 2081 int error, eccap_change; 2082 2083 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2084 2085 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2086 ixl_stop_locked(sc); 2087 2088 if (sc->sc_dead) { 2089 return ENXIO; 2090 } 2091 2092 eccap_change = sc->sc_ec.ec_capenable ^ sc->sc_cur_ec_capenable; 2093 if (ISSET(eccap_change, ETHERCAP_VLAN_HWTAGGING)) 2094 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING; 2095 2096 if (ISSET(eccap_change, ETHERCAP_VLAN_HWFILTER)) { 2097 if (ixl_update_macvlan(sc) == 0) { 2098 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER; 2099 } else { 2100 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 2101 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 2102 } 2103 } 2104 2105 if (sc->sc_intrtype != PCI_INTR_TYPE_MSIX) 2106 sc->sc_nqueue_pairs = 1; 2107 else 2108 sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max; 2109 2110 error = ixl_reinit(sc); 2111 if (error) { 2112 ixl_stop_locked(sc); 2113 return error; 2114 } 2115 2116 SET(ifp->if_flags, IFF_RUNNING); 2117 CLR(ifp->if_flags, IFF_OACTIVE); 2118 2119 ixl_config_rss(sc); 2120 ixl_config_queue_intr(sc); 2121 2122 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2123 ixl_enable_queue_intr(sc, &sc->sc_qps[i]); 2124 } 2125 2126 error = ixl_iff(sc); 2127 if (error) { 2128 ixl_stop_locked(sc); 2129 return error; 2130 } 2131 2132 callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval)); 2133 2134 return 0; 2135 } 2136 2137 static int 2138 ixl_init(struct ifnet *ifp) 2139 { 2140 struct ixl_softc *sc = ifp->if_softc; 2141 int error; 2142 2143 mutex_enter(&sc->sc_cfg_lock); 2144 error = ixl_init_locked(sc); 2145 mutex_exit(&sc->sc_cfg_lock); 2146 2147 if (error == 0) 2148 (void)ixl_get_link_status(sc); 2149 2150 return error; 2151 } 2152 2153 static int 2154 ixl_iff(struct ixl_softc *sc) 2155 { 2156 struct ifnet *ifp = &sc->sc_ec.ec_if; 2157 struct ixl_atq iatq; 2158 struct ixl_aq_desc *iaq; 2159 struct ixl_aq_vsi_promisc_param *param; 2160 uint16_t flag_add, flag_del; 2161 int error; 2162 2163 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2164 return 0; 2165 2166 memset(&iatq, 0, sizeof(iatq)); 2167 2168 iaq = &iatq.iatq_desc; 2169 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2170 2171 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2172 param->flags = htole16(0); 2173 2174 if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER) 2175 || ISSET(ifp->if_flags, IFF_PROMISC)) { 2176 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2177 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2178 } 2179 2180 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2181 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2182 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2183 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2184 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2185 } 2186 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2187 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2188 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2189 param->seid = sc->sc_seid; 2190 2191 error = ixl_atq_exec(sc, &iatq); 2192 if (error) 2193 return error; 2194 2195 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2196 return EIO; 2197 2198 if (memcmp(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN) != 0) { 2199 if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 2200 flag_add = IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH; 2201 flag_del = IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH; 2202 } else { 2203 flag_add = IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN; 2204 flag_del = IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN; 2205 } 2206 2207 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, flag_del); 2208 2209 memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 2210 ixl_add_macvlan(sc, sc->sc_enaddr, 0, flag_add); 2211 } 2212 return 0; 2213 } 2214 2215 static void 2216 ixl_stop_rendezvous(struct ixl_softc *sc) 2217 { 2218 struct ixl_tx_ring *txr; 2219 struct ixl_rx_ring *rxr; 2220 unsigned int i; 2221 2222 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2223 txr = sc->sc_qps[i].qp_txr; 2224 rxr = sc->sc_qps[i].qp_rxr; 2225 2226 mutex_enter(&txr->txr_lock); 2227 mutex_exit(&txr->txr_lock); 2228 2229 mutex_enter(&rxr->rxr_lock); 2230 mutex_exit(&rxr->rxr_lock); 2231 2232 sc->sc_qps[i].qp_workqueue = false; 2233 workqueue_wait(sc->sc_workq_txrx, 2234 &sc->sc_qps[i].qp_work); 2235 } 2236 } 2237 2238 static void 2239 ixl_stop_locked(struct ixl_softc *sc) 2240 { 2241 struct ifnet *ifp = &sc->sc_ec.ec_if; 2242 struct ixl_rx_ring *rxr; 2243 struct ixl_tx_ring *txr; 2244 unsigned int i; 2245 uint32_t reg; 2246 2247 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2248 2249 CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE); 2250 callout_stop(&sc->sc_stats_callout); 2251 2252 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2253 txr = sc->sc_qps[i].qp_txr; 2254 rxr = sc->sc_qps[i].qp_rxr; 2255 2256 ixl_disable_queue_intr(sc, &sc->sc_qps[i]); 2257 2258 mutex_enter(&txr->txr_lock); 2259 ixl_txr_qdis(sc, txr, 0); 2260 mutex_exit(&txr->txr_lock); 2261 } 2262 2263 /* XXX wait at least 400 usec for all tx queues in one go */ 2264 ixl_flush(sc); 2265 DELAY(500); 2266 2267 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2268 txr = sc->sc_qps[i].qp_txr; 2269 rxr = sc->sc_qps[i].qp_rxr; 2270 2271 mutex_enter(&txr->txr_lock); 2272 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2273 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2274 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2275 mutex_exit(&txr->txr_lock); 2276 2277 mutex_enter(&rxr->rxr_lock); 2278 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2279 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2280 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2281 mutex_exit(&rxr->rxr_lock); 2282 } 2283 2284 /* XXX short wait for all queue disables to settle */ 2285 ixl_flush(sc); 2286 DELAY(50); 2287 2288 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2289 txr = sc->sc_qps[i].qp_txr; 2290 rxr = sc->sc_qps[i].qp_rxr; 2291 2292 mutex_enter(&txr->txr_lock); 2293 if (ixl_txr_disabled(sc, txr) != 0) { 2294 mutex_exit(&txr->txr_lock); 2295 goto die; 2296 } 2297 mutex_exit(&txr->txr_lock); 2298 2299 mutex_enter(&rxr->rxr_lock); 2300 if (ixl_rxr_disabled(sc, rxr) != 0) { 2301 mutex_exit(&rxr->rxr_lock); 2302 goto die; 2303 } 2304 mutex_exit(&rxr->rxr_lock); 2305 } 2306 2307 ixl_stop_rendezvous(sc); 2308 2309 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2310 txr = sc->sc_qps[i].qp_txr; 2311 rxr = sc->sc_qps[i].qp_rxr; 2312 2313 mutex_enter(&txr->txr_lock); 2314 ixl_txr_unconfig(sc, txr); 2315 mutex_exit(&txr->txr_lock); 2316 2317 mutex_enter(&rxr->rxr_lock); 2318 ixl_rxr_unconfig(sc, rxr); 2319 mutex_exit(&rxr->rxr_lock); 2320 2321 ixl_txr_clean(sc, txr); 2322 ixl_rxr_clean(sc, rxr); 2323 } 2324 2325 return; 2326 die: 2327 sc->sc_dead = true; 2328 log(LOG_CRIT, "%s: failed to shut down rings", 2329 device_xname(sc->sc_dev)); 2330 return; 2331 } 2332 2333 static void 2334 ixl_stop(struct ifnet *ifp, int disable) 2335 { 2336 struct ixl_softc *sc = ifp->if_softc; 2337 2338 mutex_enter(&sc->sc_cfg_lock); 2339 ixl_stop_locked(sc); 2340 mutex_exit(&sc->sc_cfg_lock); 2341 } 2342 2343 static int 2344 ixl_queue_pairs_alloc(struct ixl_softc *sc) 2345 { 2346 struct ixl_queue_pair *qp; 2347 unsigned int i; 2348 size_t sz; 2349 2350 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2351 sc->sc_qps = kmem_zalloc(sz, KM_SLEEP); 2352 2353 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2354 qp = &sc->sc_qps[i]; 2355 2356 qp->qp_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 2357 ixl_handle_queue, qp); 2358 if (qp->qp_si == NULL) 2359 goto free; 2360 2361 qp->qp_txr = ixl_txr_alloc(sc, i); 2362 if (qp->qp_txr == NULL) 2363 goto free; 2364 2365 qp->qp_rxr = ixl_rxr_alloc(sc, i); 2366 if (qp->qp_rxr == NULL) 2367 goto free; 2368 2369 qp->qp_sc = sc; 2370 snprintf(qp->qp_name, sizeof(qp->qp_name), 2371 "%s-TXRX%d", device_xname(sc->sc_dev), i); 2372 } 2373 2374 return 0; 2375 free: 2376 if (sc->sc_qps != NULL) { 2377 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2378 qp = &sc->sc_qps[i]; 2379 2380 if (qp->qp_txr != NULL) 2381 ixl_txr_free(sc, qp->qp_txr); 2382 if (qp->qp_rxr != NULL) 2383 ixl_rxr_free(sc, qp->qp_rxr); 2384 if (qp->qp_si != NULL) 2385 softint_disestablish(qp->qp_si); 2386 } 2387 2388 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2389 kmem_free(sc->sc_qps, sz); 2390 sc->sc_qps = NULL; 2391 } 2392 2393 return -1; 2394 } 2395 2396 static void 2397 ixl_queue_pairs_free(struct ixl_softc *sc) 2398 { 2399 struct ixl_queue_pair *qp; 2400 unsigned int i; 2401 size_t sz; 2402 2403 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2404 qp = &sc->sc_qps[i]; 2405 ixl_txr_free(sc, qp->qp_txr); 2406 ixl_rxr_free(sc, qp->qp_rxr); 2407 softint_disestablish(qp->qp_si); 2408 } 2409 2410 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2411 kmem_free(sc->sc_qps, sz); 2412 sc->sc_qps = NULL; 2413 } 2414 2415 static struct ixl_tx_ring * 2416 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2417 { 2418 struct ixl_tx_ring *txr = NULL; 2419 struct ixl_tx_map *maps = NULL, *txm; 2420 unsigned int i; 2421 2422 txr = kmem_zalloc(sizeof(*txr), KM_SLEEP); 2423 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs, 2424 KM_SLEEP); 2425 2426 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2427 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2428 IXL_TX_QUEUE_ALIGN) != 0) 2429 goto free; 2430 2431 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2432 txm = &maps[i]; 2433 2434 if (bus_dmamap_create(sc->sc_dmat, IXL_TX_PKT_MAXSIZE, 2435 IXL_TX_PKT_DESCS, IXL_TX_PKT_MAXSIZE, 0, 2436 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &txm->txm_map) != 0) 2437 goto uncreate; 2438 2439 txm->txm_eop = -1; 2440 txm->txm_m = NULL; 2441 } 2442 2443 txr->txr_cons = txr->txr_prod = 0; 2444 txr->txr_maps = maps; 2445 2446 txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP); 2447 if (txr->txr_intrq == NULL) 2448 goto uncreate; 2449 2450 txr->txr_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 2451 ixl_deferred_transmit, txr); 2452 if (txr->txr_si == NULL) 2453 goto destroy_pcq; 2454 2455 txr->txr_tail = I40E_QTX_TAIL(qid); 2456 txr->txr_qid = qid; 2457 txr->txr_sc = sc; 2458 mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET); 2459 2460 return txr; 2461 2462 destroy_pcq: 2463 pcq_destroy(txr->txr_intrq); 2464 uncreate: 2465 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2466 txm = &maps[i]; 2467 2468 if (txm->txm_map == NULL) 2469 continue; 2470 2471 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2472 } 2473 2474 ixl_dmamem_free(sc, &txr->txr_mem); 2475 free: 2476 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2477 kmem_free(txr, sizeof(*txr)); 2478 2479 return NULL; 2480 } 2481 2482 static void 2483 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2484 { 2485 unsigned int qid; 2486 bus_size_t reg; 2487 uint32_t r; 2488 2489 qid = txr->txr_qid + sc->sc_base_queue; 2490 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2491 qid %= 128; 2492 2493 r = ixl_rd(sc, reg); 2494 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2495 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2496 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2497 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2498 ixl_wr(sc, reg, r); 2499 } 2500 2501 static void 2502 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2503 { 2504 struct ixl_hmc_txq txq; 2505 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2506 void *hmc; 2507 2508 memset(&txq, 0, sizeof(txq)); 2509 txq.head = htole16(txr->txr_cons); 2510 txq.new_context = 1; 2511 txq.base = htole64(IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2512 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2513 txq.qlen = htole16(sc->sc_tx_ring_ndescs); 2514 txq.tphrdesc_ena = 0; 2515 txq.tphrpacket_ena = 0; 2516 txq.tphwdesc_ena = 0; 2517 txq.rdylist = data->qs_handle[0]; 2518 2519 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2520 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2521 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, 2522 __arraycount(ixl_hmc_pack_txq)); 2523 } 2524 2525 static void 2526 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2527 { 2528 void *hmc; 2529 2530 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2531 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2532 txr->txr_cons = txr->txr_prod = 0; 2533 } 2534 2535 static void 2536 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2537 { 2538 struct ixl_tx_map *maps, *txm; 2539 bus_dmamap_t map; 2540 unsigned int i; 2541 2542 maps = txr->txr_maps; 2543 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2544 txm = &maps[i]; 2545 2546 if (txm->txm_m == NULL) 2547 continue; 2548 2549 map = txm->txm_map; 2550 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2551 BUS_DMASYNC_POSTWRITE); 2552 bus_dmamap_unload(sc->sc_dmat, map); 2553 2554 m_freem(txm->txm_m); 2555 txm->txm_m = NULL; 2556 } 2557 } 2558 2559 static int 2560 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2561 { 2562 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2563 uint32_t reg; 2564 int i; 2565 2566 for (i = 0; i < 10; i++) { 2567 reg = ixl_rd(sc, ena); 2568 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2569 return 0; 2570 2571 delaymsec(10); 2572 } 2573 2574 return ETIMEDOUT; 2575 } 2576 2577 static int 2578 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2579 { 2580 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2581 uint32_t reg; 2582 int i; 2583 2584 KASSERT(mutex_owned(&txr->txr_lock)); 2585 2586 for (i = 0; i < 10; i++) { 2587 reg = ixl_rd(sc, ena); 2588 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2589 return 0; 2590 2591 delaymsec(10); 2592 } 2593 2594 return ETIMEDOUT; 2595 } 2596 2597 static void 2598 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2599 { 2600 struct ixl_tx_map *maps, *txm; 2601 struct mbuf *m; 2602 unsigned int i; 2603 2604 softint_disestablish(txr->txr_si); 2605 while ((m = pcq_get(txr->txr_intrq)) != NULL) 2606 m_freem(m); 2607 pcq_destroy(txr->txr_intrq); 2608 2609 maps = txr->txr_maps; 2610 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2611 txm = &maps[i]; 2612 2613 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2614 } 2615 2616 ixl_dmamem_free(sc, &txr->txr_mem); 2617 mutex_destroy(&txr->txr_lock); 2618 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2619 kmem_free(txr, sizeof(*txr)); 2620 } 2621 2622 static inline int 2623 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0, 2624 struct ixl_tx_ring *txr) 2625 { 2626 struct mbuf *m; 2627 int error; 2628 2629 KASSERT(mutex_owned(&txr->txr_lock)); 2630 2631 m = *m0; 2632 2633 error = bus_dmamap_load_mbuf(dmat, map, m, 2634 BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2635 if (error != EFBIG) 2636 return error; 2637 2638 m = m_defrag(m, M_DONTWAIT); 2639 if (m != NULL) { 2640 *m0 = m; 2641 txr->txr_defragged.ev_count++; 2642 2643 error = bus_dmamap_load_mbuf(dmat, map, m, 2644 BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2645 } else { 2646 txr->txr_defrag_failed.ev_count++; 2647 error = ENOBUFS; 2648 } 2649 2650 return error; 2651 } 2652 2653 static inline int 2654 ixl_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd) 2655 { 2656 struct ether_header *eh; 2657 size_t len; 2658 uint64_t cmd; 2659 2660 cmd = 0; 2661 2662 eh = mtod(m, struct ether_header *); 2663 switch (htons(eh->ether_type)) { 2664 case ETHERTYPE_IP: 2665 case ETHERTYPE_IPV6: 2666 len = ETHER_HDR_LEN; 2667 break; 2668 case ETHERTYPE_VLAN: 2669 len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2670 break; 2671 default: 2672 len = 0; 2673 } 2674 cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT); 2675 2676 if (m->m_pkthdr.csum_flags & 2677 (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 2678 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4; 2679 } 2680 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2681 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM; 2682 } 2683 2684 if (m->m_pkthdr.csum_flags & 2685 (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 2686 cmd |= IXL_TX_DESC_CMD_IIPT_IPV6; 2687 } 2688 2689 switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) { 2690 case IXL_TX_DESC_CMD_IIPT_IPV4: 2691 case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM: 2692 len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2693 break; 2694 case IXL_TX_DESC_CMD_IIPT_IPV6: 2695 len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2696 break; 2697 default: 2698 len = 0; 2699 } 2700 cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT); 2701 2702 if (m->m_pkthdr.csum_flags & 2703 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) { 2704 len = sizeof(struct tcphdr); 2705 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2706 } else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) { 2707 len = sizeof(struct udphdr); 2708 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2709 } else { 2710 len = 0; 2711 } 2712 cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT); 2713 2714 *cmd_txd |= cmd; 2715 return 0; 2716 } 2717 2718 static void 2719 ixl_tx_common_locked(struct ifnet *ifp, struct ixl_tx_ring *txr, 2720 bool is_transmit) 2721 { 2722 struct ixl_softc *sc = ifp->if_softc; 2723 struct ixl_tx_desc *ring, *txd; 2724 struct ixl_tx_map *txm; 2725 bus_dmamap_t map; 2726 struct mbuf *m; 2727 uint64_t cmd, cmd_txd; 2728 unsigned int prod, free, last, i; 2729 unsigned int mask; 2730 int post = 0; 2731 2732 KASSERT(mutex_owned(&txr->txr_lock)); 2733 2734 if (!ISSET(ifp->if_flags, IFF_RUNNING) 2735 || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) { 2736 if (!is_transmit) 2737 IFQ_PURGE(&ifp->if_snd); 2738 return; 2739 } 2740 2741 prod = txr->txr_prod; 2742 free = txr->txr_cons; 2743 if (free <= prod) 2744 free += sc->sc_tx_ring_ndescs; 2745 free -= prod; 2746 2747 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2748 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2749 2750 ring = IXL_DMA_KVA(&txr->txr_mem); 2751 mask = sc->sc_tx_ring_ndescs - 1; 2752 last = prod; 2753 cmd = 0; 2754 txd = NULL; 2755 2756 for (;;) { 2757 if (free <= IXL_TX_PKT_DESCS) { 2758 if (!is_transmit) 2759 SET(ifp->if_flags, IFF_OACTIVE); 2760 break; 2761 } 2762 2763 if (is_transmit) 2764 m = pcq_get(txr->txr_intrq); 2765 else 2766 IFQ_DEQUEUE(&ifp->if_snd, m); 2767 2768 if (m == NULL) 2769 break; 2770 2771 txm = &txr->txr_maps[prod]; 2772 map = txm->txm_map; 2773 2774 if (ixl_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) { 2775 if_statinc(ifp, if_oerrors); 2776 m_freem(m); 2777 continue; 2778 } 2779 2780 cmd_txd = 0; 2781 if (m->m_pkthdr.csum_flags & IXL_CSUM_ALL_OFFLOAD) { 2782 ixl_tx_setup_offloads(m, &cmd_txd); 2783 } 2784 2785 if (vlan_has_tag(m)) { 2786 cmd_txd |= (uint64_t)vlan_get_tag(m) << 2787 IXL_TX_DESC_L2TAG1_SHIFT; 2788 cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1; 2789 } 2790 2791 bus_dmamap_sync(sc->sc_dmat, map, 0, 2792 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2793 2794 for (i = 0; i < (unsigned int)map->dm_nsegs; i++) { 2795 txd = &ring[prod]; 2796 2797 cmd = (uint64_t)map->dm_segs[i].ds_len << 2798 IXL_TX_DESC_BSIZE_SHIFT; 2799 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2800 cmd |= cmd_txd; 2801 2802 txd->addr = htole64(map->dm_segs[i].ds_addr); 2803 txd->cmd = htole64(cmd); 2804 2805 last = prod; 2806 2807 prod++; 2808 prod &= mask; 2809 } 2810 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2811 txd->cmd = htole64(cmd); 2812 2813 txm->txm_m = m; 2814 txm->txm_eop = last; 2815 2816 bpf_mtap(ifp, m, BPF_D_OUT); 2817 2818 free -= i; 2819 post = 1; 2820 } 2821 2822 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2823 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2824 2825 if (post) { 2826 txr->txr_prod = prod; 2827 ixl_wr(sc, txr->txr_tail, prod); 2828 } 2829 } 2830 2831 static int 2832 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr, u_int txlimit) 2833 { 2834 struct ifnet *ifp = &sc->sc_ec.ec_if; 2835 struct ixl_tx_desc *ring, *txd; 2836 struct ixl_tx_map *txm; 2837 struct mbuf *m; 2838 bus_dmamap_t map; 2839 unsigned int cons, prod, last; 2840 unsigned int mask; 2841 uint64_t dtype; 2842 int done = 0, more = 0; 2843 2844 KASSERT(mutex_owned(&txr->txr_lock)); 2845 2846 prod = txr->txr_prod; 2847 cons = txr->txr_cons; 2848 2849 if (cons == prod) 2850 return 0; 2851 2852 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2853 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2854 2855 ring = IXL_DMA_KVA(&txr->txr_mem); 2856 mask = sc->sc_tx_ring_ndescs - 1; 2857 2858 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2859 2860 do { 2861 if (txlimit-- <= 0) { 2862 more = 1; 2863 break; 2864 } 2865 2866 txm = &txr->txr_maps[cons]; 2867 last = txm->txm_eop; 2868 txd = &ring[last]; 2869 2870 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2871 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2872 break; 2873 2874 map = txm->txm_map; 2875 2876 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2877 BUS_DMASYNC_POSTWRITE); 2878 bus_dmamap_unload(sc->sc_dmat, map); 2879 2880 m = txm->txm_m; 2881 if (m != NULL) { 2882 if_statinc_ref(nsr, if_opackets); 2883 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2884 if (ISSET(m->m_flags, M_MCAST)) 2885 if_statinc_ref(nsr, if_omcasts); 2886 m_freem(m); 2887 } 2888 2889 txm->txm_m = NULL; 2890 txm->txm_eop = -1; 2891 2892 cons = last + 1; 2893 cons &= mask; 2894 done = 1; 2895 } while (cons != prod); 2896 2897 IF_STAT_PUTREF(ifp); 2898 2899 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2900 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2901 2902 txr->txr_cons = cons; 2903 2904 if (done) { 2905 softint_schedule(txr->txr_si); 2906 if (txr->txr_qid == 0) { 2907 CLR(ifp->if_flags, IFF_OACTIVE); 2908 if_schedule_deferred_start(ifp); 2909 } 2910 } 2911 2912 return more; 2913 } 2914 2915 static void 2916 ixl_start(struct ifnet *ifp) 2917 { 2918 struct ixl_softc *sc; 2919 struct ixl_tx_ring *txr; 2920 2921 sc = ifp->if_softc; 2922 txr = sc->sc_qps[0].qp_txr; 2923 2924 mutex_enter(&txr->txr_lock); 2925 ixl_tx_common_locked(ifp, txr, false); 2926 mutex_exit(&txr->txr_lock); 2927 } 2928 2929 static inline unsigned int 2930 ixl_select_txqueue(struct ixl_softc *sc, struct mbuf *m) 2931 { 2932 u_int cpuid; 2933 2934 cpuid = cpu_index(curcpu()); 2935 2936 return (unsigned int)(cpuid % sc->sc_nqueue_pairs); 2937 } 2938 2939 static int 2940 ixl_transmit(struct ifnet *ifp, struct mbuf *m) 2941 { 2942 struct ixl_softc *sc; 2943 struct ixl_tx_ring *txr; 2944 unsigned int qid; 2945 2946 sc = ifp->if_softc; 2947 qid = ixl_select_txqueue(sc, m); 2948 2949 txr = sc->sc_qps[qid].qp_txr; 2950 2951 if (__predict_false(!pcq_put(txr->txr_intrq, m))) { 2952 mutex_enter(&txr->txr_lock); 2953 txr->txr_pcqdrop.ev_count++; 2954 mutex_exit(&txr->txr_lock); 2955 2956 m_freem(m); 2957 return ENOBUFS; 2958 } 2959 2960 if (mutex_tryenter(&txr->txr_lock)) { 2961 ixl_tx_common_locked(ifp, txr, true); 2962 mutex_exit(&txr->txr_lock); 2963 } else { 2964 kpreempt_disable(); 2965 softint_schedule(txr->txr_si); 2966 kpreempt_enable(); 2967 } 2968 2969 return 0; 2970 } 2971 2972 static void 2973 ixl_deferred_transmit(void *xtxr) 2974 { 2975 struct ixl_tx_ring *txr = xtxr; 2976 struct ixl_softc *sc = txr->txr_sc; 2977 struct ifnet *ifp = &sc->sc_ec.ec_if; 2978 2979 mutex_enter(&txr->txr_lock); 2980 txr->txr_transmitdef.ev_count++; 2981 if (pcq_peek(txr->txr_intrq) != NULL) 2982 ixl_tx_common_locked(ifp, txr, true); 2983 mutex_exit(&txr->txr_lock); 2984 } 2985 2986 static struct ixl_rx_ring * 2987 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 2988 { 2989 struct ixl_rx_ring *rxr = NULL; 2990 struct ixl_rx_map *maps = NULL, *rxm; 2991 unsigned int i; 2992 2993 rxr = kmem_zalloc(sizeof(*rxr), KM_SLEEP); 2994 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_rx_ring_ndescs, 2995 KM_SLEEP); 2996 2997 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 2998 sizeof(struct ixl_rx_rd_desc_32) * sc->sc_rx_ring_ndescs, 2999 IXL_RX_QUEUE_ALIGN) != 0) 3000 goto free; 3001 3002 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3003 rxm = &maps[i]; 3004 3005 if (bus_dmamap_create(sc->sc_dmat, 3006 IXL_MCLBYTES, 1, IXL_MCLBYTES, 0, 3007 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &rxm->rxm_map) != 0) 3008 goto uncreate; 3009 3010 rxm->rxm_m = NULL; 3011 } 3012 3013 rxr->rxr_cons = rxr->rxr_prod = 0; 3014 rxr->rxr_m_head = NULL; 3015 rxr->rxr_m_tail = &rxr->rxr_m_head; 3016 rxr->rxr_maps = maps; 3017 3018 rxr->rxr_tail = I40E_QRX_TAIL(qid); 3019 rxr->rxr_qid = qid; 3020 mutex_init(&rxr->rxr_lock, MUTEX_DEFAULT, IPL_NET); 3021 3022 return rxr; 3023 3024 uncreate: 3025 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3026 rxm = &maps[i]; 3027 3028 if (rxm->rxm_map == NULL) 3029 continue; 3030 3031 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3032 } 3033 3034 ixl_dmamem_free(sc, &rxr->rxr_mem); 3035 free: 3036 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 3037 kmem_free(rxr, sizeof(*rxr)); 3038 3039 return NULL; 3040 } 3041 3042 static void 3043 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3044 { 3045 struct ixl_rx_map *maps, *rxm; 3046 bus_dmamap_t map; 3047 unsigned int i; 3048 3049 maps = rxr->rxr_maps; 3050 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3051 rxm = &maps[i]; 3052 3053 if (rxm->rxm_m == NULL) 3054 continue; 3055 3056 map = rxm->rxm_map; 3057 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3058 BUS_DMASYNC_POSTWRITE); 3059 bus_dmamap_unload(sc->sc_dmat, map); 3060 3061 m_freem(rxm->rxm_m); 3062 rxm->rxm_m = NULL; 3063 } 3064 3065 m_freem(rxr->rxr_m_head); 3066 rxr->rxr_m_head = NULL; 3067 rxr->rxr_m_tail = &rxr->rxr_m_head; 3068 3069 rxr->rxr_prod = rxr->rxr_cons = 0; 3070 } 3071 3072 static int 3073 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3074 { 3075 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3076 uint32_t reg; 3077 int i; 3078 3079 for (i = 0; i < 10; i++) { 3080 reg = ixl_rd(sc, ena); 3081 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3082 return 0; 3083 3084 delaymsec(10); 3085 } 3086 3087 return ETIMEDOUT; 3088 } 3089 3090 static int 3091 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3092 { 3093 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3094 uint32_t reg; 3095 int i; 3096 3097 KASSERT(mutex_owned(&rxr->rxr_lock)); 3098 3099 for (i = 0; i < 10; i++) { 3100 reg = ixl_rd(sc, ena); 3101 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3102 return 0; 3103 3104 delaymsec(10); 3105 } 3106 3107 return ETIMEDOUT; 3108 } 3109 3110 static void 3111 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3112 { 3113 struct ixl_hmc_rxq rxq; 3114 struct ifnet *ifp = &sc->sc_ec.ec_if; 3115 uint16_t rxmax; 3116 void *hmc; 3117 3118 memset(&rxq, 0, sizeof(rxq)); 3119 rxmax = ifp->if_mtu + IXL_MTU_ETHERLEN; 3120 3121 rxq.head = htole16(rxr->rxr_cons); 3122 rxq.base = htole64(IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3123 rxq.qlen = htole16(sc->sc_rx_ring_ndescs); 3124 rxq.dbuff = htole16(IXL_MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3125 rxq.hbuff = 0; 3126 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3127 rxq.dsize = IXL_HMC_RXQ_DSIZE_32; 3128 rxq.crcstrip = 1; 3129 rxq.l2sel = 1; 3130 rxq.showiv = 1; 3131 rxq.rxmax = htole16(rxmax); 3132 rxq.tphrdesc_ena = 0; 3133 rxq.tphwdesc_ena = 0; 3134 rxq.tphdata_ena = 0; 3135 rxq.tphhead_ena = 0; 3136 rxq.lrxqthresh = 0; 3137 rxq.prefena = 1; 3138 3139 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3140 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3141 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, 3142 __arraycount(ixl_hmc_pack_rxq)); 3143 } 3144 3145 static void 3146 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3147 { 3148 void *hmc; 3149 3150 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3151 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3152 rxr->rxr_cons = rxr->rxr_prod = 0; 3153 } 3154 3155 static void 3156 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3157 { 3158 struct ixl_rx_map *maps, *rxm; 3159 unsigned int i; 3160 3161 maps = rxr->rxr_maps; 3162 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3163 rxm = &maps[i]; 3164 3165 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3166 } 3167 3168 ixl_dmamem_free(sc, &rxr->rxr_mem); 3169 mutex_destroy(&rxr->rxr_lock); 3170 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 3171 kmem_free(rxr, sizeof(*rxr)); 3172 } 3173 3174 static inline void 3175 ixl_rx_csum(struct mbuf *m, uint64_t qword) 3176 { 3177 int flags_mask; 3178 3179 if (!ISSET(qword, IXL_RX_DESC_L3L4P)) { 3180 /* No L3 or L4 checksum was calculated */ 3181 return; 3182 } 3183 3184 switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) { 3185 case IXL_RX_DESC_PTYPE_IPV4FRAG: 3186 case IXL_RX_DESC_PTYPE_IPV4: 3187 case IXL_RX_DESC_PTYPE_SCTPV4: 3188 case IXL_RX_DESC_PTYPE_ICMPV4: 3189 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3190 break; 3191 case IXL_RX_DESC_PTYPE_TCPV4: 3192 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3193 flags_mask |= M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD; 3194 break; 3195 case IXL_RX_DESC_PTYPE_UDPV4: 3196 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3197 flags_mask |= M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD; 3198 break; 3199 case IXL_RX_DESC_PTYPE_TCPV6: 3200 flags_mask = M_CSUM_TCPv6 | M_CSUM_TCP_UDP_BAD; 3201 break; 3202 case IXL_RX_DESC_PTYPE_UDPV6: 3203 flags_mask = M_CSUM_UDPv6 | M_CSUM_TCP_UDP_BAD; 3204 break; 3205 default: 3206 flags_mask = 0; 3207 } 3208 3209 m->m_pkthdr.csum_flags |= (flags_mask & (M_CSUM_IPv4 | 3210 M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)); 3211 3212 if (ISSET(qword, IXL_RX_DESC_IPE)) { 3213 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_IPv4_BAD); 3214 } 3215 3216 if (ISSET(qword, IXL_RX_DESC_L4E)) { 3217 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_TCP_UDP_BAD); 3218 } 3219 } 3220 3221 static int 3222 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr, u_int rxlimit) 3223 { 3224 struct ifnet *ifp = &sc->sc_ec.ec_if; 3225 struct ixl_rx_wb_desc_32 *ring, *rxd; 3226 struct ixl_rx_map *rxm; 3227 bus_dmamap_t map; 3228 unsigned int cons, prod; 3229 struct mbuf *m; 3230 uint64_t word, word0; 3231 unsigned int len; 3232 unsigned int mask; 3233 int done = 0, more = 0; 3234 3235 KASSERT(mutex_owned(&rxr->rxr_lock)); 3236 3237 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3238 return 0; 3239 3240 prod = rxr->rxr_prod; 3241 cons = rxr->rxr_cons; 3242 3243 if (cons == prod) 3244 return 0; 3245 3246 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3247 0, IXL_DMA_LEN(&rxr->rxr_mem), 3248 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3249 3250 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3251 mask = sc->sc_rx_ring_ndescs - 1; 3252 3253 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 3254 3255 do { 3256 if (rxlimit-- <= 0) { 3257 more = 1; 3258 break; 3259 } 3260 3261 rxd = &ring[cons]; 3262 3263 word = le64toh(rxd->qword1); 3264 3265 if (!ISSET(word, IXL_RX_DESC_DD)) 3266 break; 3267 3268 rxm = &rxr->rxr_maps[cons]; 3269 3270 map = rxm->rxm_map; 3271 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3272 BUS_DMASYNC_POSTREAD); 3273 bus_dmamap_unload(sc->sc_dmat, map); 3274 3275 m = rxm->rxm_m; 3276 rxm->rxm_m = NULL; 3277 3278 KASSERT(m != NULL); 3279 3280 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3281 m->m_len = len; 3282 m->m_pkthdr.len = 0; 3283 3284 m->m_next = NULL; 3285 *rxr->rxr_m_tail = m; 3286 rxr->rxr_m_tail = &m->m_next; 3287 3288 m = rxr->rxr_m_head; 3289 m->m_pkthdr.len += len; 3290 3291 if (ISSET(word, IXL_RX_DESC_EOP)) { 3292 word0 = le64toh(rxd->qword0); 3293 3294 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 3295 vlan_set_tag(m, 3296 __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK)); 3297 } 3298 3299 if ((ifp->if_capenable & IXL_IFCAP_RXCSUM) != 0) 3300 ixl_rx_csum(m, word); 3301 3302 if (!ISSET(word, 3303 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3304 m_set_rcvif(m, ifp); 3305 if_statinc_ref(nsr, if_ipackets); 3306 if_statadd_ref(nsr, if_ibytes, 3307 m->m_pkthdr.len); 3308 if_percpuq_enqueue(ifp->if_percpuq, m); 3309 } else { 3310 if_statinc_ref(nsr, if_ierrors); 3311 m_freem(m); 3312 } 3313 3314 rxr->rxr_m_head = NULL; 3315 rxr->rxr_m_tail = &rxr->rxr_m_head; 3316 } 3317 3318 cons++; 3319 cons &= mask; 3320 3321 done = 1; 3322 } while (cons != prod); 3323 3324 if (done) { 3325 rxr->rxr_cons = cons; 3326 if (ixl_rxfill(sc, rxr) == -1) 3327 if_statinc_ref(nsr, if_iqdrops); 3328 } 3329 3330 IF_STAT_PUTREF(ifp); 3331 3332 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3333 0, IXL_DMA_LEN(&rxr->rxr_mem), 3334 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3335 3336 return more; 3337 } 3338 3339 static int 3340 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3341 { 3342 struct ixl_rx_rd_desc_32 *ring, *rxd; 3343 struct ixl_rx_map *rxm; 3344 bus_dmamap_t map; 3345 struct mbuf *m; 3346 unsigned int prod; 3347 unsigned int slots; 3348 unsigned int mask; 3349 int post = 0, error = 0; 3350 3351 KASSERT(mutex_owned(&rxr->rxr_lock)); 3352 3353 prod = rxr->rxr_prod; 3354 slots = ixl_rxr_unrefreshed(rxr->rxr_prod, rxr->rxr_cons, 3355 sc->sc_rx_ring_ndescs); 3356 3357 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3358 mask = sc->sc_rx_ring_ndescs - 1; 3359 3360 if (__predict_false(slots <= 0)) 3361 return -1; 3362 3363 do { 3364 rxm = &rxr->rxr_maps[prod]; 3365 3366 MGETHDR(m, M_DONTWAIT, MT_DATA); 3367 if (m == NULL) { 3368 rxr->rxr_mgethdr_failed.ev_count++; 3369 error = -1; 3370 break; 3371 } 3372 3373 MCLGET(m, M_DONTWAIT); 3374 if (!ISSET(m->m_flags, M_EXT)) { 3375 rxr->rxr_mgetcl_failed.ev_count++; 3376 error = -1; 3377 m_freem(m); 3378 break; 3379 } 3380 3381 m->m_len = m->m_pkthdr.len = MCLBYTES; 3382 m_adj(m, ETHER_ALIGN); 3383 3384 map = rxm->rxm_map; 3385 3386 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3387 BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 3388 rxr->rxr_mbuf_load_failed.ev_count++; 3389 error = -1; 3390 m_freem(m); 3391 break; 3392 } 3393 3394 rxm->rxm_m = m; 3395 3396 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3397 BUS_DMASYNC_PREREAD); 3398 3399 rxd = &ring[prod]; 3400 3401 rxd->paddr = htole64(map->dm_segs[0].ds_addr); 3402 rxd->haddr = htole64(0); 3403 3404 prod++; 3405 prod &= mask; 3406 3407 post = 1; 3408 3409 } while (--slots); 3410 3411 if (post) { 3412 rxr->rxr_prod = prod; 3413 ixl_wr(sc, rxr->rxr_tail, prod); 3414 } 3415 3416 return error; 3417 } 3418 3419 static inline int 3420 ixl_handle_queue_common(struct ixl_softc *sc, struct ixl_queue_pair *qp, 3421 u_int txlimit, struct evcnt *txevcnt, 3422 u_int rxlimit, struct evcnt *rxevcnt) 3423 { 3424 struct ixl_tx_ring *txr = qp->qp_txr; 3425 struct ixl_rx_ring *rxr = qp->qp_rxr; 3426 int txmore, rxmore; 3427 int rv; 3428 3429 mutex_enter(&txr->txr_lock); 3430 txevcnt->ev_count++; 3431 txmore = ixl_txeof(sc, txr, txlimit); 3432 mutex_exit(&txr->txr_lock); 3433 3434 mutex_enter(&rxr->rxr_lock); 3435 rxevcnt->ev_count++; 3436 rxmore = ixl_rxeof(sc, rxr, rxlimit); 3437 mutex_exit(&rxr->rxr_lock); 3438 3439 rv = txmore | (rxmore << 1); 3440 3441 return rv; 3442 } 3443 3444 static void 3445 ixl_sched_handle_queue(struct ixl_softc *sc, struct ixl_queue_pair *qp) 3446 { 3447 3448 if (qp->qp_workqueue) 3449 workqueue_enqueue(sc->sc_workq_txrx, &qp->qp_work, NULL); 3450 else 3451 softint_schedule(qp->qp_si); 3452 } 3453 3454 static int 3455 ixl_intr(void *xsc) 3456 { 3457 struct ixl_softc *sc = xsc; 3458 struct ixl_tx_ring *txr; 3459 struct ixl_rx_ring *rxr; 3460 uint32_t icr, rxintr, txintr; 3461 int rv = 0; 3462 unsigned int i; 3463 3464 KASSERT(sc != NULL); 3465 3466 ixl_enable_other_intr(sc); 3467 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3468 3469 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3470 atomic_inc_64(&sc->sc_event_atq.ev_count); 3471 ixl_atq_done(sc); 3472 ixl_work_add(sc->sc_workq, &sc->sc_arq_task); 3473 rv = 1; 3474 } 3475 3476 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3477 atomic_inc_64(&sc->sc_event_link.ev_count); 3478 ixl_work_add(sc->sc_workq, &sc->sc_link_state_task); 3479 rv = 1; 3480 } 3481 3482 rxintr = icr & I40E_INTR_NOTX_RX_MASK; 3483 txintr = icr & I40E_INTR_NOTX_TX_MASK; 3484 3485 if (txintr || rxintr) { 3486 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3487 txr = sc->sc_qps[i].qp_txr; 3488 rxr = sc->sc_qps[i].qp_rxr; 3489 3490 ixl_handle_queue_common(sc, &sc->sc_qps[i], 3491 IXL_TXRX_PROCESS_UNLIMIT, &txr->txr_intr, 3492 IXL_TXRX_PROCESS_UNLIMIT, &rxr->rxr_intr); 3493 } 3494 rv = 1; 3495 } 3496 3497 return rv; 3498 } 3499 3500 static int 3501 ixl_queue_intr(void *xqp) 3502 { 3503 struct ixl_queue_pair *qp = xqp; 3504 struct ixl_tx_ring *txr = qp->qp_txr; 3505 struct ixl_rx_ring *rxr = qp->qp_rxr; 3506 struct ixl_softc *sc = qp->qp_sc; 3507 u_int txlimit, rxlimit; 3508 int more; 3509 3510 txlimit = sc->sc_tx_intr_process_limit; 3511 rxlimit = sc->sc_rx_intr_process_limit; 3512 qp->qp_workqueue = sc->sc_txrx_workqueue; 3513 3514 more = ixl_handle_queue_common(sc, qp, 3515 txlimit, &txr->txr_intr, rxlimit, &rxr->rxr_intr); 3516 3517 if (more != 0) { 3518 ixl_sched_handle_queue(sc, qp); 3519 } else { 3520 /* for ALTQ */ 3521 if (txr->txr_qid == 0) 3522 if_schedule_deferred_start(&sc->sc_ec.ec_if); 3523 softint_schedule(txr->txr_si); 3524 3525 ixl_enable_queue_intr(sc, qp); 3526 } 3527 3528 return 1; 3529 } 3530 3531 static void 3532 ixl_handle_queue_wk(struct work *wk, void *xsc) 3533 { 3534 struct ixl_queue_pair *qp; 3535 3536 qp = container_of(wk, struct ixl_queue_pair, qp_work); 3537 ixl_handle_queue(qp); 3538 } 3539 3540 static void 3541 ixl_handle_queue(void *xqp) 3542 { 3543 struct ixl_queue_pair *qp = xqp; 3544 struct ixl_softc *sc = qp->qp_sc; 3545 struct ixl_tx_ring *txr = qp->qp_txr; 3546 struct ixl_rx_ring *rxr = qp->qp_rxr; 3547 u_int txlimit, rxlimit; 3548 int more; 3549 3550 txlimit = sc->sc_tx_process_limit; 3551 rxlimit = sc->sc_rx_process_limit; 3552 3553 more = ixl_handle_queue_common(sc, qp, 3554 txlimit, &txr->txr_defer, rxlimit, &rxr->rxr_defer); 3555 3556 if (more != 0) 3557 ixl_sched_handle_queue(sc, qp); 3558 else 3559 ixl_enable_queue_intr(sc, qp); 3560 } 3561 3562 static inline void 3563 ixl_print_hmc_error(struct ixl_softc *sc, uint32_t reg) 3564 { 3565 uint32_t hmc_idx, hmc_isvf; 3566 uint32_t hmc_errtype, hmc_objtype, hmc_data; 3567 3568 hmc_idx = reg & I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK; 3569 hmc_idx = hmc_idx >> I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT; 3570 hmc_isvf = reg & I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK; 3571 hmc_isvf = hmc_isvf >> I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT; 3572 hmc_errtype = reg & I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK; 3573 hmc_errtype = hmc_errtype >> I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT; 3574 hmc_objtype = reg & I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK; 3575 hmc_objtype = hmc_objtype >> I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT; 3576 hmc_data = ixl_rd(sc, I40E_PFHMC_ERRORDATA); 3577 3578 device_printf(sc->sc_dev, 3579 "HMC Error (idx=0x%x, isvf=0x%x, err=0x%x, obj=0x%x, data=0x%x)\n", 3580 hmc_idx, hmc_isvf, hmc_errtype, hmc_objtype, hmc_data); 3581 } 3582 3583 static int 3584 ixl_other_intr(void *xsc) 3585 { 3586 struct ixl_softc *sc = xsc; 3587 uint32_t icr, mask, reg; 3588 int rv; 3589 3590 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3591 mask = ixl_rd(sc, I40E_PFINT_ICR0_ENA); 3592 3593 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3594 atomic_inc_64(&sc->sc_event_atq.ev_count); 3595 ixl_atq_done(sc); 3596 ixl_work_add(sc->sc_workq, &sc->sc_arq_task); 3597 rv = 1; 3598 } 3599 3600 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3601 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3602 device_printf(sc->sc_dev, "link stat changed\n"); 3603 3604 atomic_inc_64(&sc->sc_event_link.ev_count); 3605 ixl_work_add(sc->sc_workq, &sc->sc_link_state_task); 3606 rv = 1; 3607 } 3608 3609 if (ISSET(icr, I40E_PFINT_ICR0_GRST_MASK)) { 3610 CLR(mask, I40E_PFINT_ICR0_ENA_GRST_MASK); 3611 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 3612 reg = reg & I40E_GLGEN_RSTAT_RESET_TYPE_MASK; 3613 reg = reg >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; 3614 3615 device_printf(sc->sc_dev, "GRST: %s\n", 3616 reg == I40E_RESET_CORER ? "CORER" : 3617 reg == I40E_RESET_GLOBR ? "GLOBR" : 3618 reg == I40E_RESET_EMPR ? "EMPR" : 3619 "POR"); 3620 } 3621 3622 if (ISSET(icr, I40E_PFINT_ICR0_ECC_ERR_MASK)) 3623 atomic_inc_64(&sc->sc_event_ecc_err.ev_count); 3624 if (ISSET(icr, I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)) 3625 atomic_inc_64(&sc->sc_event_pci_exception.ev_count); 3626 if (ISSET(icr, I40E_PFINT_ICR0_PE_CRITERR_MASK)) 3627 atomic_inc_64(&sc->sc_event_crit_err.ev_count); 3628 3629 if (ISSET(icr, IXL_ICR0_CRIT_ERR_MASK)) { 3630 CLR(mask, IXL_ICR0_CRIT_ERR_MASK); 3631 device_printf(sc->sc_dev, "critical error\n"); 3632 } 3633 3634 if (ISSET(icr, I40E_PFINT_ICR0_HMC_ERR_MASK)) { 3635 reg = ixl_rd(sc, I40E_PFHMC_ERRORINFO); 3636 if (ISSET(reg, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK)) 3637 ixl_print_hmc_error(sc, reg); 3638 ixl_wr(sc, I40E_PFHMC_ERRORINFO, 0); 3639 } 3640 3641 ixl_wr(sc, I40E_PFINT_ICR0_ENA, mask); 3642 ixl_flush(sc); 3643 ixl_enable_other_intr(sc); 3644 return rv; 3645 } 3646 3647 static void 3648 ixl_get_link_status_done(struct ixl_softc *sc, 3649 const struct ixl_aq_desc *iaq) 3650 { 3651 struct ixl_aq_desc iaq_buf; 3652 3653 memcpy(&iaq_buf, iaq, sizeof(iaq_buf)); 3654 3655 /* 3656 * The lock can be released here 3657 * because there is no post processing about ATQ 3658 */ 3659 mutex_exit(&sc->sc_atq_lock); 3660 ixl_link_state_update(sc, &iaq_buf); 3661 mutex_enter(&sc->sc_atq_lock); 3662 } 3663 3664 static void 3665 ixl_get_link_status(void *xsc) 3666 { 3667 struct ixl_softc *sc = xsc; 3668 struct ixl_aq_desc *iaq; 3669 struct ixl_aq_link_param *param; 3670 int error; 3671 3672 mutex_enter(&sc->sc_atq_lock); 3673 3674 iaq = &sc->sc_link_state_atq.iatq_desc; 3675 memset(iaq, 0, sizeof(*iaq)); 3676 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3677 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3678 param->notify = IXL_AQ_LINK_NOTIFY; 3679 3680 error = ixl_atq_exec_locked(sc, &sc->sc_link_state_atq); 3681 ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done); 3682 3683 if (error == 0) { 3684 ixl_get_link_status_done(sc, iaq); 3685 } 3686 3687 mutex_exit(&sc->sc_atq_lock); 3688 } 3689 3690 static void 3691 ixl_link_state_update(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3692 { 3693 struct ifnet *ifp = &sc->sc_ec.ec_if; 3694 int link_state; 3695 3696 mutex_enter(&sc->sc_cfg_lock); 3697 link_state = ixl_set_link_status_locked(sc, iaq); 3698 mutex_exit(&sc->sc_cfg_lock); 3699 3700 if (ifp->if_link_state != link_state) 3701 if_link_state_change(ifp, link_state); 3702 3703 if (link_state != LINK_STATE_DOWN) { 3704 kpreempt_disable(); 3705 if_schedule_deferred_start(ifp); 3706 kpreempt_enable(); 3707 } 3708 } 3709 3710 static void 3711 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq, 3712 const char *msg) 3713 { 3714 char buf[512]; 3715 size_t len; 3716 3717 len = sizeof(buf); 3718 buf[--len] = '\0'; 3719 3720 device_printf(sc->sc_dev, "%s\n", msg); 3721 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags)); 3722 device_printf(sc->sc_dev, "flags %s opcode %04x\n", 3723 buf, le16toh(iaq->iaq_opcode)); 3724 device_printf(sc->sc_dev, "datalen %u retval %u\n", 3725 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval)); 3726 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie); 3727 device_printf(sc->sc_dev, "%08x %08x %08x %08x\n", 3728 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]), 3729 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3])); 3730 } 3731 3732 static void 3733 ixl_arq(void *xsc) 3734 { 3735 struct ixl_softc *sc = xsc; 3736 struct ixl_aq_desc *arq, *iaq; 3737 struct ixl_aq_buf *aqb; 3738 unsigned int cons = sc->sc_arq_cons; 3739 unsigned int prod; 3740 int done = 0; 3741 3742 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3743 sc->sc_aq_regs->arq_head_mask; 3744 3745 if (cons == prod) 3746 goto done; 3747 3748 arq = IXL_DMA_KVA(&sc->sc_arq); 3749 3750 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3751 0, IXL_DMA_LEN(&sc->sc_arq), 3752 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3753 3754 do { 3755 iaq = &arq[cons]; 3756 aqb = sc->sc_arq_live[cons]; 3757 3758 KASSERT(aqb != NULL); 3759 3760 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3761 BUS_DMASYNC_POSTREAD); 3762 3763 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3764 ixl_aq_dump(sc, iaq, "arq event"); 3765 3766 switch (iaq->iaq_opcode) { 3767 case htole16(IXL_AQ_OP_PHY_LINK_STATUS): 3768 ixl_link_state_update(sc, iaq); 3769 break; 3770 } 3771 3772 memset(iaq, 0, sizeof(*iaq)); 3773 sc->sc_arq_live[cons] = NULL; 3774 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3775 3776 cons++; 3777 cons &= IXL_AQ_MASK; 3778 3779 done = 1; 3780 } while (cons != prod); 3781 3782 if (done) { 3783 sc->sc_arq_cons = cons; 3784 ixl_arq_fill(sc); 3785 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3786 0, IXL_DMA_LEN(&sc->sc_arq), 3787 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3788 } 3789 3790 done: 3791 ixl_enable_other_intr(sc); 3792 } 3793 3794 static void 3795 ixl_atq_set(struct ixl_atq *iatq, 3796 void (*fn)(struct ixl_softc *, const struct ixl_aq_desc *)) 3797 { 3798 3799 iatq->iatq_fn = fn; 3800 } 3801 3802 static int 3803 ixl_atq_post_locked(struct ixl_softc *sc, struct ixl_atq *iatq) 3804 { 3805 struct ixl_aq_desc *atq, *slot; 3806 unsigned int prod, cons, prod_next; 3807 3808 /* assert locked */ 3809 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3810 3811 atq = IXL_DMA_KVA(&sc->sc_atq); 3812 prod = sc->sc_atq_prod; 3813 cons = sc->sc_atq_cons; 3814 prod_next = (prod +1) & IXL_AQ_MASK; 3815 3816 if (cons == prod_next) 3817 return ENOMEM; 3818 3819 slot = &atq[prod]; 3820 3821 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3822 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3823 3824 KASSERT(iatq->iatq_fn != NULL); 3825 *slot = iatq->iatq_desc; 3826 slot->iaq_cookie = (uint64_t)((intptr_t)iatq); 3827 3828 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3829 ixl_aq_dump(sc, slot, "atq command"); 3830 3831 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3832 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3833 3834 sc->sc_atq_prod = prod_next; 3835 ixl_wr(sc, sc->sc_aq_regs->atq_tail, sc->sc_atq_prod); 3836 3837 return 0; 3838 } 3839 3840 static void 3841 ixl_atq_done_locked(struct ixl_softc *sc) 3842 { 3843 struct ixl_aq_desc *atq, *slot; 3844 struct ixl_atq *iatq; 3845 unsigned int cons; 3846 unsigned int prod; 3847 3848 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3849 3850 prod = sc->sc_atq_prod; 3851 cons = sc->sc_atq_cons; 3852 3853 if (prod == cons) 3854 return; 3855 3856 atq = IXL_DMA_KVA(&sc->sc_atq); 3857 3858 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3859 0, IXL_DMA_LEN(&sc->sc_atq), 3860 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3861 3862 do { 3863 slot = &atq[cons]; 3864 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3865 break; 3866 3867 iatq = (struct ixl_atq *)((intptr_t)slot->iaq_cookie); 3868 iatq->iatq_desc = *slot; 3869 3870 memset(slot, 0, sizeof(*slot)); 3871 3872 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3873 ixl_aq_dump(sc, &iatq->iatq_desc, "atq response"); 3874 3875 (*iatq->iatq_fn)(sc, &iatq->iatq_desc); 3876 3877 cons++; 3878 cons &= IXL_AQ_MASK; 3879 } while (cons != prod); 3880 3881 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3882 0, IXL_DMA_LEN(&sc->sc_atq), 3883 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3884 3885 sc->sc_atq_cons = cons; 3886 } 3887 3888 static void 3889 ixl_atq_done(struct ixl_softc *sc) 3890 { 3891 3892 mutex_enter(&sc->sc_atq_lock); 3893 ixl_atq_done_locked(sc); 3894 mutex_exit(&sc->sc_atq_lock); 3895 } 3896 3897 static void 3898 ixl_wakeup(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3899 { 3900 3901 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3902 3903 cv_signal(&sc->sc_atq_cv); 3904 } 3905 3906 static int 3907 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq) 3908 { 3909 int error; 3910 3911 mutex_enter(&sc->sc_atq_lock); 3912 error = ixl_atq_exec_locked(sc, iatq); 3913 mutex_exit(&sc->sc_atq_lock); 3914 3915 return error; 3916 } 3917 3918 static int 3919 ixl_atq_exec_locked(struct ixl_softc *sc, struct ixl_atq *iatq) 3920 { 3921 int error; 3922 3923 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3924 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3925 3926 ixl_atq_set(iatq, ixl_wakeup); 3927 3928 error = ixl_atq_post_locked(sc, iatq); 3929 if (error) 3930 return error; 3931 3932 error = cv_timedwait(&sc->sc_atq_cv, &sc->sc_atq_lock, 3933 IXL_ATQ_EXEC_TIMEOUT); 3934 3935 return error; 3936 } 3937 3938 static int 3939 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3940 { 3941 struct ixl_aq_desc *atq, *slot; 3942 unsigned int prod; 3943 unsigned int t = 0; 3944 3945 mutex_enter(&sc->sc_atq_lock); 3946 3947 atq = IXL_DMA_KVA(&sc->sc_atq); 3948 prod = sc->sc_atq_prod; 3949 slot = atq + prod; 3950 3951 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3952 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3953 3954 *slot = *iaq; 3955 slot->iaq_flags |= htole16(IXL_AQ_SI); 3956 3957 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3958 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3959 3960 prod++; 3961 prod &= IXL_AQ_MASK; 3962 sc->sc_atq_prod = prod; 3963 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3964 3965 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3966 delaymsec(1); 3967 3968 if (t++ > tm) { 3969 mutex_exit(&sc->sc_atq_lock); 3970 return ETIMEDOUT; 3971 } 3972 } 3973 3974 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3975 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3976 *iaq = *slot; 3977 memset(slot, 0, sizeof(*slot)); 3978 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3979 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3980 3981 sc->sc_atq_cons = prod; 3982 3983 mutex_exit(&sc->sc_atq_lock); 3984 3985 return 0; 3986 } 3987 3988 static int 3989 ixl_get_version(struct ixl_softc *sc) 3990 { 3991 struct ixl_aq_desc iaq; 3992 uint32_t fwbuild, fwver, apiver; 3993 uint16_t api_maj_ver, api_min_ver; 3994 3995 memset(&iaq, 0, sizeof(iaq)); 3996 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3997 3998 iaq.iaq_retval = le16toh(23); 3999 4000 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 4001 return ETIMEDOUT; 4002 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 4003 return EIO; 4004 4005 fwbuild = le32toh(iaq.iaq_param[1]); 4006 fwver = le32toh(iaq.iaq_param[2]); 4007 apiver = le32toh(iaq.iaq_param[3]); 4008 4009 api_maj_ver = (uint16_t)apiver; 4010 api_min_ver = (uint16_t)(apiver >> 16); 4011 4012 aprint_normal(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 4013 (uint16_t)(fwver >> 16), fwbuild, api_maj_ver, api_min_ver); 4014 4015 if (sc->sc_mac_type == I40E_MAC_X722) { 4016 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK | 4017 IXL_SC_AQ_FLAG_NVMREAD); 4018 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL); 4019 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS); 4020 } 4021 4022 #define IXL_API_VER(maj, min) (((uint32_t)(maj) << 16) | (min)) 4023 if (IXL_API_VER(api_maj_ver, api_min_ver) >= IXL_API_VER(1, 5)) { 4024 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL); 4025 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK); 4026 } 4027 #undef IXL_API_VER 4028 4029 return 0; 4030 } 4031 4032 static int 4033 ixl_get_nvm_version(struct ixl_softc *sc) 4034 { 4035 uint16_t nvmver, cfg_ptr, eetrack_hi, eetrack_lo, oem_hi, oem_lo; 4036 uint32_t eetrack, oem; 4037 uint16_t nvm_maj_ver, nvm_min_ver, oem_build; 4038 uint8_t oem_ver, oem_patch; 4039 4040 nvmver = cfg_ptr = eetrack_hi = eetrack_lo = oem_hi = oem_lo = 0; 4041 ixl_rd16_nvm(sc, I40E_SR_NVM_DEV_STARTER_VERSION, &nvmver); 4042 ixl_rd16_nvm(sc, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 4043 ixl_rd16_nvm(sc, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 4044 ixl_rd16_nvm(sc, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); 4045 ixl_rd16_nvm(sc, cfg_ptr + I40E_NVM_OEM_VER_OFF, &oem_hi); 4046 ixl_rd16_nvm(sc, cfg_ptr + I40E_NVM_OEM_VER_OFF + 1, &oem_lo); 4047 4048 nvm_maj_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_HI_MASK); 4049 nvm_min_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_LO_MASK); 4050 eetrack = ((uint32_t)eetrack_hi << 16) | eetrack_lo; 4051 oem = ((uint32_t)oem_hi << 16) | oem_lo; 4052 oem_ver = __SHIFTOUT(oem, IXL_NVM_OEMVERSION_MASK); 4053 oem_build = __SHIFTOUT(oem, IXL_NVM_OEMBUILD_MASK); 4054 oem_patch = __SHIFTOUT(oem, IXL_NVM_OEMPATCH_MASK); 4055 4056 aprint_normal(" nvm %x.%02x etid %08x oem %d.%d.%d", 4057 nvm_maj_ver, nvm_min_ver, eetrack, 4058 oem_ver, oem_build, oem_patch); 4059 4060 return 0; 4061 } 4062 4063 static int 4064 ixl_pxe_clear(struct ixl_softc *sc) 4065 { 4066 struct ixl_aq_desc iaq; 4067 int rv; 4068 4069 memset(&iaq, 0, sizeof(iaq)); 4070 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 4071 iaq.iaq_param[0] = htole32(0x2); 4072 4073 rv = ixl_atq_poll(sc, &iaq, 250); 4074 4075 ixl_wr(sc, I40E_GLLAN_RCTL_0, 0x1); 4076 4077 if (rv != 0) 4078 return ETIMEDOUT; 4079 4080 switch (iaq.iaq_retval) { 4081 case htole16(IXL_AQ_RC_OK): 4082 case htole16(IXL_AQ_RC_EEXIST): 4083 break; 4084 default: 4085 return EIO; 4086 } 4087 4088 return 0; 4089 } 4090 4091 static int 4092 ixl_lldp_shut(struct ixl_softc *sc) 4093 { 4094 struct ixl_aq_desc iaq; 4095 4096 memset(&iaq, 0, sizeof(iaq)); 4097 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 4098 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 4099 4100 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4101 aprint_error_dev(sc->sc_dev, "STOP LLDP AGENT timeout\n"); 4102 return -1; 4103 } 4104 4105 switch (iaq.iaq_retval) { 4106 case htole16(IXL_AQ_RC_EMODE): 4107 case htole16(IXL_AQ_RC_EPERM): 4108 /* ignore silently */ 4109 default: 4110 break; 4111 } 4112 4113 return 0; 4114 } 4115 4116 static void 4117 ixl_parse_hw_capability(struct ixl_softc *sc, struct ixl_aq_capability *cap) 4118 { 4119 uint16_t id; 4120 uint32_t number, logical_id; 4121 4122 id = le16toh(cap->cap_id); 4123 number = le32toh(cap->number); 4124 logical_id = le32toh(cap->logical_id); 4125 4126 switch (id) { 4127 case IXL_AQ_CAP_RSS: 4128 sc->sc_rss_table_size = number; 4129 sc->sc_rss_table_entry_width = logical_id; 4130 break; 4131 case IXL_AQ_CAP_RXQ: 4132 case IXL_AQ_CAP_TXQ: 4133 sc->sc_nqueue_pairs_device = MIN(number, 4134 sc->sc_nqueue_pairs_device); 4135 break; 4136 } 4137 } 4138 4139 static int 4140 ixl_get_hw_capabilities(struct ixl_softc *sc) 4141 { 4142 struct ixl_dmamem idm; 4143 struct ixl_aq_desc iaq; 4144 struct ixl_aq_capability *caps; 4145 size_t i, ncaps; 4146 bus_size_t caps_size; 4147 uint16_t status; 4148 int rv; 4149 4150 caps_size = sizeof(caps[0]) * 40; 4151 memset(&iaq, 0, sizeof(iaq)); 4152 iaq.iaq_opcode = htole16(IXL_AQ_OP_LIST_FUNC_CAP); 4153 4154 do { 4155 if (ixl_dmamem_alloc(sc, &idm, caps_size, 0) != 0) { 4156 return -1; 4157 } 4158 4159 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4160 (caps_size > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4161 iaq.iaq_datalen = htole16(caps_size); 4162 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4163 4164 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, 4165 IXL_DMA_LEN(&idm), BUS_DMASYNC_PREREAD); 4166 4167 rv = ixl_atq_poll(sc, &iaq, 250); 4168 4169 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, 4170 IXL_DMA_LEN(&idm), BUS_DMASYNC_POSTREAD); 4171 4172 if (rv != 0) { 4173 aprint_error(", HW capabilities timeout\n"); 4174 goto done; 4175 } 4176 4177 status = le16toh(iaq.iaq_retval); 4178 4179 if (status == IXL_AQ_RC_ENOMEM) { 4180 caps_size = le16toh(iaq.iaq_datalen); 4181 ixl_dmamem_free(sc, &idm); 4182 } 4183 } while (status == IXL_AQ_RC_ENOMEM); 4184 4185 if (status != IXL_AQ_RC_OK) { 4186 aprint_error(", HW capabilities error\n"); 4187 goto done; 4188 } 4189 4190 caps = IXL_DMA_KVA(&idm); 4191 ncaps = le16toh(iaq.iaq_param[1]); 4192 4193 for (i = 0; i < ncaps; i++) { 4194 ixl_parse_hw_capability(sc, &caps[i]); 4195 } 4196 4197 done: 4198 ixl_dmamem_free(sc, &idm); 4199 return rv; 4200 } 4201 4202 static int 4203 ixl_get_mac(struct ixl_softc *sc) 4204 { 4205 struct ixl_dmamem idm; 4206 struct ixl_aq_desc iaq; 4207 struct ixl_aq_mac_addresses *addrs; 4208 int rv; 4209 4210 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 4211 aprint_error(", unable to allocate mac addresses\n"); 4212 return -1; 4213 } 4214 4215 memset(&iaq, 0, sizeof(iaq)); 4216 iaq.iaq_flags = htole16(IXL_AQ_BUF); 4217 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 4218 iaq.iaq_datalen = htole16(sizeof(*addrs)); 4219 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4220 4221 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4222 BUS_DMASYNC_PREREAD); 4223 4224 rv = ixl_atq_poll(sc, &iaq, 250); 4225 4226 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4227 BUS_DMASYNC_POSTREAD); 4228 4229 if (rv != 0) { 4230 aprint_error(", MAC ADDRESS READ timeout\n"); 4231 rv = -1; 4232 goto done; 4233 } 4234 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4235 aprint_error(", MAC ADDRESS READ error\n"); 4236 rv = -1; 4237 goto done; 4238 } 4239 4240 addrs = IXL_DMA_KVA(&idm); 4241 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 4242 printf(", port address is not valid\n"); 4243 goto done; 4244 } 4245 4246 memcpy(sc->sc_enaddr, addrs->port, ETHER_ADDR_LEN); 4247 rv = 0; 4248 4249 done: 4250 ixl_dmamem_free(sc, &idm); 4251 return rv; 4252 } 4253 4254 static int 4255 ixl_get_switch_config(struct ixl_softc *sc) 4256 { 4257 struct ixl_dmamem idm; 4258 struct ixl_aq_desc iaq; 4259 struct ixl_aq_switch_config *hdr; 4260 struct ixl_aq_switch_config_element *elms, *elm; 4261 unsigned int nelm, i; 4262 int rv; 4263 4264 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4265 aprint_error_dev(sc->sc_dev, 4266 "unable to allocate switch config buffer\n"); 4267 return -1; 4268 } 4269 4270 memset(&iaq, 0, sizeof(iaq)); 4271 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4272 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4273 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 4274 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 4275 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4276 4277 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4278 BUS_DMASYNC_PREREAD); 4279 4280 rv = ixl_atq_poll(sc, &iaq, 250); 4281 4282 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4283 BUS_DMASYNC_POSTREAD); 4284 4285 if (rv != 0) { 4286 aprint_error_dev(sc->sc_dev, "GET SWITCH CONFIG timeout\n"); 4287 rv = -1; 4288 goto done; 4289 } 4290 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4291 aprint_error_dev(sc->sc_dev, "GET SWITCH CONFIG error\n"); 4292 rv = -1; 4293 goto done; 4294 } 4295 4296 hdr = IXL_DMA_KVA(&idm); 4297 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 4298 4299 nelm = le16toh(hdr->num_reported); 4300 if (nelm < 1) { 4301 aprint_error_dev(sc->sc_dev, "no switch config available\n"); 4302 rv = -1; 4303 goto done; 4304 } 4305 4306 for (i = 0; i < nelm; i++) { 4307 elm = &elms[i]; 4308 4309 aprint_debug_dev(sc->sc_dev, 4310 "type %x revision %u seid %04x\n", 4311 elm->type, elm->revision, le16toh(elm->seid)); 4312 aprint_debug_dev(sc->sc_dev, 4313 "uplink %04x downlink %04x\n", 4314 le16toh(elm->uplink_seid), 4315 le16toh(elm->downlink_seid)); 4316 aprint_debug_dev(sc->sc_dev, 4317 "conntype %x scheduler %04x extra %04x\n", 4318 elm->connection_type, 4319 le16toh(elm->scheduler_id), 4320 le16toh(elm->element_info)); 4321 } 4322 4323 elm = &elms[0]; 4324 4325 sc->sc_uplink_seid = elm->uplink_seid; 4326 sc->sc_downlink_seid = elm->downlink_seid; 4327 sc->sc_seid = elm->seid; 4328 4329 if ((sc->sc_uplink_seid == htole16(0)) != 4330 (sc->sc_downlink_seid == htole16(0))) { 4331 aprint_error_dev(sc->sc_dev, "SEIDs are misconfigured\n"); 4332 rv = -1; 4333 goto done; 4334 } 4335 4336 done: 4337 ixl_dmamem_free(sc, &idm); 4338 return rv; 4339 } 4340 4341 static int 4342 ixl_phy_mask_ints(struct ixl_softc *sc) 4343 { 4344 struct ixl_aq_desc iaq; 4345 4346 memset(&iaq, 0, sizeof(iaq)); 4347 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 4348 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 4349 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 4350 IXL_AQ_PHY_EV_MEDIA_NA)); 4351 4352 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4353 aprint_error_dev(sc->sc_dev, "SET PHY EVENT MASK timeout\n"); 4354 return -1; 4355 } 4356 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4357 aprint_error_dev(sc->sc_dev, "SET PHY EVENT MASK error\n"); 4358 return -1; 4359 } 4360 4361 return 0; 4362 } 4363 4364 static int 4365 ixl_get_phy_abilities(struct ixl_softc *sc,struct ixl_dmamem *idm) 4366 { 4367 struct ixl_aq_desc iaq; 4368 int rv; 4369 4370 memset(&iaq, 0, sizeof(iaq)); 4371 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4372 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4373 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 4374 iaq.iaq_datalen = htole16(IXL_DMA_LEN(idm)); 4375 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 4376 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 4377 4378 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4379 BUS_DMASYNC_PREREAD); 4380 4381 rv = ixl_atq_poll(sc, &iaq, 250); 4382 4383 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4384 BUS_DMASYNC_POSTREAD); 4385 4386 if (rv != 0) 4387 return -1; 4388 4389 return le16toh(iaq.iaq_retval); 4390 } 4391 4392 static int 4393 ixl_get_phy_info(struct ixl_softc *sc) 4394 { 4395 struct ixl_dmamem idm; 4396 struct ixl_aq_phy_abilities *phy; 4397 int rv; 4398 4399 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4400 aprint_error_dev(sc->sc_dev, 4401 "unable to allocate phy abilities buffer\n"); 4402 return -1; 4403 } 4404 4405 rv = ixl_get_phy_abilities(sc, &idm); 4406 switch (rv) { 4407 case -1: 4408 aprint_error_dev(sc->sc_dev, "GET PHY ABILITIES timeout\n"); 4409 goto done; 4410 case IXL_AQ_RC_OK: 4411 break; 4412 case IXL_AQ_RC_EIO: 4413 aprint_error_dev(sc->sc_dev,"unable to query phy types\n"); 4414 goto done; 4415 default: 4416 aprint_error_dev(sc->sc_dev, 4417 "GET PHY ABILITIIES error %u\n", rv); 4418 goto done; 4419 } 4420 4421 phy = IXL_DMA_KVA(&idm); 4422 4423 sc->sc_phy_types = le32toh(phy->phy_type); 4424 sc->sc_phy_types |= (uint64_t)le32toh(phy->phy_type_ext) << 32; 4425 4426 sc->sc_phy_abilities = phy->abilities; 4427 sc->sc_phy_linkspeed = phy->link_speed; 4428 sc->sc_phy_fec_cfg = phy->fec_cfg_curr_mod_ext_info & 4429 (IXL_AQ_ENABLE_FEC_KR | IXL_AQ_ENABLE_FEC_RS | 4430 IXL_AQ_REQUEST_FEC_KR | IXL_AQ_REQUEST_FEC_RS); 4431 sc->sc_eee_cap = phy->eee_capability; 4432 sc->sc_eeer_val = phy->eeer_val; 4433 sc->sc_d3_lpan = phy->d3_lpan; 4434 4435 rv = 0; 4436 4437 done: 4438 ixl_dmamem_free(sc, &idm); 4439 return rv; 4440 } 4441 4442 static int 4443 ixl_set_phy_config(struct ixl_softc *sc, 4444 uint8_t link_speed, uint8_t abilities, bool polling) 4445 { 4446 struct ixl_aq_phy_param *param; 4447 struct ixl_atq iatq; 4448 struct ixl_aq_desc *iaq; 4449 int error; 4450 4451 memset(&iatq, 0, sizeof(iatq)); 4452 4453 iaq = &iatq.iatq_desc; 4454 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_CONFIG); 4455 param = (struct ixl_aq_phy_param *)&iaq->iaq_param; 4456 param->phy_types = htole32((uint32_t)sc->sc_phy_types); 4457 param->phy_type_ext = (uint8_t)(sc->sc_phy_types >> 32); 4458 param->link_speed = link_speed; 4459 param->abilities = abilities | IXL_AQ_PHY_ABILITY_AUTO_LINK; 4460 param->fec_cfg = sc->sc_phy_fec_cfg; 4461 param->eee_capability = sc->sc_eee_cap; 4462 param->eeer_val = sc->sc_eeer_val; 4463 param->d3_lpan = sc->sc_d3_lpan; 4464 4465 if (polling) 4466 error = ixl_atq_poll(sc, iaq, 250); 4467 else 4468 error = ixl_atq_exec(sc, &iatq); 4469 4470 if (error != 0) 4471 return error; 4472 4473 switch (le16toh(iaq->iaq_retval)) { 4474 case IXL_AQ_RC_OK: 4475 break; 4476 case IXL_AQ_RC_EPERM: 4477 return EPERM; 4478 default: 4479 return EIO; 4480 } 4481 4482 return 0; 4483 } 4484 4485 static int 4486 ixl_set_phy_autoselect(struct ixl_softc *sc) 4487 { 4488 uint8_t link_speed, abilities; 4489 4490 link_speed = sc->sc_phy_linkspeed; 4491 abilities = IXL_PHY_ABILITY_LINKUP | IXL_PHY_ABILITY_AUTONEGO; 4492 4493 return ixl_set_phy_config(sc, link_speed, abilities, true); 4494 } 4495 4496 static int 4497 ixl_get_link_status_poll(struct ixl_softc *sc, int *l) 4498 { 4499 struct ixl_aq_desc iaq; 4500 struct ixl_aq_link_param *param; 4501 int link; 4502 4503 memset(&iaq, 0, sizeof(iaq)); 4504 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 4505 param = (struct ixl_aq_link_param *)iaq.iaq_param; 4506 param->notify = IXL_AQ_LINK_NOTIFY; 4507 4508 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4509 return ETIMEDOUT; 4510 } 4511 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4512 return EIO; 4513 } 4514 4515 /* It is unneccessary to hold lock */ 4516 link = ixl_set_link_status_locked(sc, &iaq); 4517 4518 if (l != NULL) 4519 *l = link; 4520 4521 return 0; 4522 } 4523 4524 static int 4525 ixl_get_vsi(struct ixl_softc *sc) 4526 { 4527 struct ixl_dmamem *vsi = &sc->sc_scratch; 4528 struct ixl_aq_desc iaq; 4529 struct ixl_aq_vsi_param *param; 4530 struct ixl_aq_vsi_reply *reply; 4531 struct ixl_aq_vsi_data *data; 4532 int rv; 4533 4534 /* grumble, vsi info isn't "known" at compile time */ 4535 4536 memset(&iaq, 0, sizeof(iaq)); 4537 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4538 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4539 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4540 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi)); 4541 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4542 4543 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4544 param->uplink_seid = sc->sc_seid; 4545 4546 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4547 BUS_DMASYNC_PREREAD); 4548 4549 rv = ixl_atq_poll(sc, &iaq, 250); 4550 4551 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4552 BUS_DMASYNC_POSTREAD); 4553 4554 if (rv != 0) { 4555 return ETIMEDOUT; 4556 } 4557 4558 switch (le16toh(iaq.iaq_retval)) { 4559 case IXL_AQ_RC_OK: 4560 break; 4561 case IXL_AQ_RC_ENOENT: 4562 return ENOENT; 4563 case IXL_AQ_RC_EACCES: 4564 return EACCES; 4565 default: 4566 return EIO; 4567 } 4568 4569 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4570 sc->sc_vsi_number = le16toh(reply->vsi_number); 4571 data = IXL_DMA_KVA(vsi); 4572 sc->sc_vsi_stat_counter_idx = le16toh(data->stat_counter_idx); 4573 4574 return 0; 4575 } 4576 4577 static int 4578 ixl_set_vsi(struct ixl_softc *sc) 4579 { 4580 struct ixl_dmamem *vsi = &sc->sc_scratch; 4581 struct ixl_aq_desc iaq; 4582 struct ixl_aq_vsi_param *param; 4583 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4584 unsigned int qnum; 4585 uint16_t val; 4586 int rv; 4587 4588 qnum = sc->sc_nqueue_pairs - 1; 4589 4590 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4591 IXL_AQ_VSI_VALID_VLAN); 4592 4593 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4594 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4595 data->queue_mapping[0] = htole16(0); 4596 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4597 (qnum << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4598 4599 val = le16toh(data->port_vlan_flags); 4600 CLR(val, IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK); 4601 SET(val, IXL_AQ_VSI_PVLAN_MODE_ALL); 4602 4603 if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWTAGGING)) { 4604 SET(val, IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH); 4605 } else { 4606 SET(val, IXL_AQ_VSI_PVLAN_EMOD_NOTHING); 4607 } 4608 4609 data->port_vlan_flags = htole16(val); 4610 4611 /* grumble, vsi info isn't "known" at compile time */ 4612 4613 memset(&iaq, 0, sizeof(iaq)); 4614 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4615 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4616 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4617 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi)); 4618 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4619 4620 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4621 param->uplink_seid = sc->sc_seid; 4622 4623 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4624 BUS_DMASYNC_PREWRITE); 4625 4626 rv = ixl_atq_poll(sc, &iaq, 250); 4627 4628 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4629 BUS_DMASYNC_POSTWRITE); 4630 4631 if (rv != 0) { 4632 return ETIMEDOUT; 4633 } 4634 4635 switch (le16toh(iaq.iaq_retval)) { 4636 case IXL_AQ_RC_OK: 4637 break; 4638 case IXL_AQ_RC_ENOENT: 4639 return ENOENT; 4640 case IXL_AQ_RC_EACCES: 4641 return EACCES; 4642 default: 4643 return EIO; 4644 } 4645 4646 return 0; 4647 } 4648 4649 static void 4650 ixl_set_filter_control(struct ixl_softc *sc) 4651 { 4652 uint32_t reg; 4653 4654 reg = ixl_rd_rx_csr(sc, I40E_PFQF_CTL_0); 4655 4656 CLR(reg, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 4657 SET(reg, I40E_HASH_LUT_SIZE_128 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT); 4658 4659 SET(reg, I40E_PFQF_CTL_0_FD_ENA_MASK); 4660 SET(reg, I40E_PFQF_CTL_0_ETYPE_ENA_MASK); 4661 SET(reg, I40E_PFQF_CTL_0_MACVLAN_ENA_MASK); 4662 4663 ixl_wr_rx_csr(sc, I40E_PFQF_CTL_0, reg); 4664 } 4665 4666 static inline void 4667 ixl_get_default_rss_key(uint32_t *buf, size_t len) 4668 { 4669 size_t cplen; 4670 uint8_t rss_seed[RSS_KEYSIZE]; 4671 4672 rss_getkey(rss_seed); 4673 memset(buf, 0, len); 4674 4675 cplen = MIN(len, sizeof(rss_seed)); 4676 memcpy(buf, rss_seed, cplen); 4677 } 4678 4679 static int 4680 ixl_set_rss_key(struct ixl_softc *sc, uint8_t *key, size_t keylen) 4681 { 4682 struct ixl_dmamem *idm; 4683 struct ixl_atq iatq; 4684 struct ixl_aq_desc *iaq; 4685 struct ixl_aq_rss_key_param *param; 4686 struct ixl_aq_rss_key_data *data; 4687 size_t len, datalen, stdlen, extlen; 4688 uint16_t vsi_id; 4689 int rv; 4690 4691 memset(&iatq, 0, sizeof(iatq)); 4692 iaq = &iatq.iatq_desc; 4693 idm = &sc->sc_aqbuf; 4694 4695 datalen = sizeof(*data); 4696 4697 /*XXX The buf size has to be less than the size of the register */ 4698 datalen = MIN(IXL_RSS_KEY_SIZE_REG * sizeof(uint32_t), datalen); 4699 4700 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4701 (datalen > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4702 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_KEY); 4703 iaq->iaq_datalen = htole16(datalen); 4704 4705 param = (struct ixl_aq_rss_key_param *)iaq->iaq_param; 4706 vsi_id = (sc->sc_vsi_number << IXL_AQ_RSSKEY_VSI_ID_SHIFT) | 4707 IXL_AQ_RSSKEY_VSI_VALID; 4708 param->vsi_id = htole16(vsi_id); 4709 4710 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 4711 data = IXL_DMA_KVA(idm); 4712 4713 len = MIN(keylen, datalen); 4714 stdlen = MIN(sizeof(data->standard_rss_key), len); 4715 memcpy(data->standard_rss_key, key, stdlen); 4716 len = (len > stdlen) ? (len - stdlen) : 0; 4717 4718 extlen = MIN(sizeof(data->extended_hash_key), len); 4719 extlen = (stdlen < keylen) ? 0 : keylen - stdlen; 4720 memcpy(data->extended_hash_key, key + stdlen, extlen); 4721 4722 ixl_aq_dva(iaq, IXL_DMA_DVA(idm)); 4723 4724 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4725 IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE); 4726 4727 rv = ixl_atq_exec(sc, &iatq); 4728 4729 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4730 IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE); 4731 4732 if (rv != 0) { 4733 return ETIMEDOUT; 4734 } 4735 4736 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) { 4737 return EIO; 4738 } 4739 4740 return 0; 4741 } 4742 4743 static int 4744 ixl_set_rss_lut(struct ixl_softc *sc, uint8_t *lut, size_t lutlen) 4745 { 4746 struct ixl_dmamem *idm; 4747 struct ixl_atq iatq; 4748 struct ixl_aq_desc *iaq; 4749 struct ixl_aq_rss_lut_param *param; 4750 uint16_t vsi_id; 4751 uint8_t *data; 4752 size_t dmalen; 4753 int rv; 4754 4755 memset(&iatq, 0, sizeof(iatq)); 4756 iaq = &iatq.iatq_desc; 4757 idm = &sc->sc_aqbuf; 4758 4759 dmalen = MIN(lutlen, IXL_DMA_LEN(idm)); 4760 4761 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4762 (dmalen > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4763 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_LUT); 4764 iaq->iaq_datalen = htole16(dmalen); 4765 4766 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 4767 data = IXL_DMA_KVA(idm); 4768 memcpy(data, lut, dmalen); 4769 ixl_aq_dva(iaq, IXL_DMA_DVA(idm)); 4770 4771 param = (struct ixl_aq_rss_lut_param *)iaq->iaq_param; 4772 vsi_id = (sc->sc_vsi_number << IXL_AQ_RSSLUT_VSI_ID_SHIFT) | 4773 IXL_AQ_RSSLUT_VSI_VALID; 4774 param->vsi_id = htole16(vsi_id); 4775 param->flags = htole16(IXL_AQ_RSSLUT_TABLE_TYPE_PF << 4776 IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT); 4777 4778 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4779 IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE); 4780 4781 rv = ixl_atq_exec(sc, &iatq); 4782 4783 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4784 IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE); 4785 4786 if (rv != 0) { 4787 return ETIMEDOUT; 4788 } 4789 4790 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) { 4791 return EIO; 4792 } 4793 4794 return 0; 4795 } 4796 4797 static int 4798 ixl_register_rss_key(struct ixl_softc *sc) 4799 { 4800 uint32_t rss_seed[IXL_RSS_KEY_SIZE_REG]; 4801 int rv; 4802 size_t i; 4803 4804 ixl_get_default_rss_key(rss_seed, sizeof(rss_seed)); 4805 4806 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS)){ 4807 rv = ixl_set_rss_key(sc, (uint8_t*)rss_seed, 4808 sizeof(rss_seed)); 4809 } else { 4810 rv = 0; 4811 for (i = 0; i < IXL_RSS_KEY_SIZE_REG; i++) { 4812 ixl_wr_rx_csr(sc, I40E_PFQF_HKEY(i), rss_seed[i]); 4813 } 4814 } 4815 4816 return rv; 4817 } 4818 4819 static void 4820 ixl_register_rss_pctype(struct ixl_softc *sc) 4821 { 4822 uint64_t set_hena = 0; 4823 uint32_t hena0, hena1; 4824 4825 /* 4826 * We use TCP/UDP with IPv4/IPv6 by default. 4827 * Note: the device can not use just IP header in each 4828 * TCP/UDP packets for the RSS hash calculation. 4829 */ 4830 if (sc->sc_mac_type == I40E_MAC_X722) 4831 set_hena = IXL_RSS_HENA_DEFAULT_X722; 4832 else 4833 set_hena = IXL_RSS_HENA_DEFAULT_XL710; 4834 4835 hena0 = ixl_rd_rx_csr(sc, I40E_PFQF_HENA(0)); 4836 hena1 = ixl_rd_rx_csr(sc, I40E_PFQF_HENA(1)); 4837 4838 SET(hena0, set_hena); 4839 SET(hena1, set_hena >> 32); 4840 4841 ixl_wr_rx_csr(sc, I40E_PFQF_HENA(0), hena0); 4842 ixl_wr_rx_csr(sc, I40E_PFQF_HENA(1), hena1); 4843 } 4844 4845 static int 4846 ixl_register_rss_hlut(struct ixl_softc *sc) 4847 { 4848 unsigned int qid; 4849 uint8_t hlut_buf[512], lut_mask; 4850 uint32_t *hluts; 4851 size_t i, hluts_num; 4852 int rv; 4853 4854 lut_mask = (0x01 << sc->sc_rss_table_entry_width) - 1; 4855 4856 for (i = 0; i < sc->sc_rss_table_size; i++) { 4857 qid = i % sc->sc_nqueue_pairs; 4858 hlut_buf[i] = qid & lut_mask; 4859 } 4860 4861 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS)) { 4862 rv = ixl_set_rss_lut(sc, hlut_buf, sizeof(hlut_buf)); 4863 } else { 4864 rv = 0; 4865 hluts = (uint32_t *)hlut_buf; 4866 hluts_num = sc->sc_rss_table_size >> 2; 4867 for (i = 0; i < hluts_num; i++) { 4868 ixl_wr(sc, I40E_PFQF_HLUT(i), hluts[i]); 4869 } 4870 ixl_flush(sc); 4871 } 4872 4873 return rv; 4874 } 4875 4876 static void 4877 ixl_config_rss(struct ixl_softc *sc) 4878 { 4879 4880 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 4881 4882 ixl_register_rss_key(sc); 4883 ixl_register_rss_pctype(sc); 4884 ixl_register_rss_hlut(sc); 4885 } 4886 4887 static const struct ixl_phy_type * 4888 ixl_search_phy_type(uint8_t phy_type) 4889 { 4890 const struct ixl_phy_type *itype; 4891 uint64_t mask; 4892 unsigned int i; 4893 4894 if (phy_type >= 64) 4895 return NULL; 4896 4897 mask = 1ULL << phy_type; 4898 4899 for (i = 0; i < __arraycount(ixl_phy_type_map); i++) { 4900 itype = &ixl_phy_type_map[i]; 4901 4902 if (ISSET(itype->phy_type, mask)) 4903 return itype; 4904 } 4905 4906 return NULL; 4907 } 4908 4909 static uint64_t 4910 ixl_search_link_speed(uint8_t link_speed) 4911 { 4912 const struct ixl_speed_type *type; 4913 unsigned int i; 4914 4915 for (i = 0; i < __arraycount(ixl_speed_type_map); i++) { 4916 type = &ixl_speed_type_map[i]; 4917 4918 if (ISSET(type->dev_speed, link_speed)) 4919 return type->net_speed; 4920 } 4921 4922 return 0; 4923 } 4924 4925 static uint8_t 4926 ixl_search_baudrate(uint64_t baudrate) 4927 { 4928 const struct ixl_speed_type *type; 4929 unsigned int i; 4930 4931 for (i = 0; i < __arraycount(ixl_speed_type_map); i++) { 4932 type = &ixl_speed_type_map[i]; 4933 4934 if (type->net_speed == baudrate) { 4935 return type->dev_speed; 4936 } 4937 } 4938 4939 return 0; 4940 } 4941 4942 static int 4943 ixl_restart_an(struct ixl_softc *sc) 4944 { 4945 struct ixl_aq_desc iaq; 4946 4947 memset(&iaq, 0, sizeof(iaq)); 4948 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4949 iaq.iaq_param[0] = 4950 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4951 4952 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4953 aprint_error_dev(sc->sc_dev, "RESTART AN timeout\n"); 4954 return -1; 4955 } 4956 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4957 aprint_error_dev(sc->sc_dev, "RESTART AN error\n"); 4958 return -1; 4959 } 4960 4961 return 0; 4962 } 4963 4964 static int 4965 ixl_add_macvlan(struct ixl_softc *sc, const uint8_t *macaddr, 4966 uint16_t vlan, uint16_t flags) 4967 { 4968 struct ixl_aq_desc iaq; 4969 struct ixl_aq_add_macvlan *param; 4970 struct ixl_aq_add_macvlan_elem *elem; 4971 4972 memset(&iaq, 0, sizeof(iaq)); 4973 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4974 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4975 iaq.iaq_datalen = htole16(sizeof(*elem)); 4976 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4977 4978 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4979 param->num_addrs = htole16(1); 4980 param->seid0 = htole16(0x8000) | sc->sc_seid; 4981 param->seid1 = 0; 4982 param->seid2 = 0; 4983 4984 elem = IXL_DMA_KVA(&sc->sc_scratch); 4985 memset(elem, 0, sizeof(*elem)); 4986 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4987 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4988 elem->vlan = htole16(vlan); 4989 4990 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4991 return IXL_AQ_RC_EINVAL; 4992 } 4993 4994 switch (le16toh(iaq.iaq_retval)) { 4995 case IXL_AQ_RC_OK: 4996 break; 4997 case IXL_AQ_RC_ENOSPC: 4998 return ENOSPC; 4999 case IXL_AQ_RC_ENOENT: 5000 return ENOENT; 5001 case IXL_AQ_RC_EACCES: 5002 return EACCES; 5003 case IXL_AQ_RC_EEXIST: 5004 return EEXIST; 5005 case IXL_AQ_RC_EINVAL: 5006 return EINVAL; 5007 default: 5008 return EIO; 5009 } 5010 5011 return 0; 5012 } 5013 5014 static int 5015 ixl_remove_macvlan(struct ixl_softc *sc, const uint8_t *macaddr, 5016 uint16_t vlan, uint16_t flags) 5017 { 5018 struct ixl_aq_desc iaq; 5019 struct ixl_aq_remove_macvlan *param; 5020 struct ixl_aq_remove_macvlan_elem *elem; 5021 5022 memset(&iaq, 0, sizeof(iaq)); 5023 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 5024 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 5025 iaq.iaq_datalen = htole16(sizeof(*elem)); 5026 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 5027 5028 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 5029 param->num_addrs = htole16(1); 5030 param->seid0 = htole16(0x8000) | sc->sc_seid; 5031 param->seid1 = 0; 5032 param->seid2 = 0; 5033 5034 elem = IXL_DMA_KVA(&sc->sc_scratch); 5035 memset(elem, 0, sizeof(*elem)); 5036 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 5037 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 5038 elem->vlan = htole16(vlan); 5039 5040 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 5041 return EINVAL; 5042 } 5043 5044 switch (le16toh(iaq.iaq_retval)) { 5045 case IXL_AQ_RC_OK: 5046 break; 5047 case IXL_AQ_RC_ENOENT: 5048 return ENOENT; 5049 case IXL_AQ_RC_EACCES: 5050 return EACCES; 5051 case IXL_AQ_RC_EINVAL: 5052 return EINVAL; 5053 default: 5054 return EIO; 5055 } 5056 5057 return 0; 5058 } 5059 5060 static int 5061 ixl_hmc(struct ixl_softc *sc) 5062 { 5063 struct { 5064 uint32_t count; 5065 uint32_t minsize; 5066 bus_size_t objsiz; 5067 bus_size_t setoff; 5068 bus_size_t setcnt; 5069 } regs[] = { 5070 { 5071 0, 5072 IXL_HMC_TXQ_MINSIZE, 5073 I40E_GLHMC_LANTXOBJSZ, 5074 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 5075 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 5076 }, 5077 { 5078 0, 5079 IXL_HMC_RXQ_MINSIZE, 5080 I40E_GLHMC_LANRXOBJSZ, 5081 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 5082 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 5083 }, 5084 { 5085 0, 5086 0, 5087 I40E_GLHMC_FCOEDDPOBJSZ, 5088 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 5089 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 5090 }, 5091 { 5092 0, 5093 0, 5094 I40E_GLHMC_FCOEFOBJSZ, 5095 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 5096 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 5097 }, 5098 }; 5099 struct ixl_hmc_entry *e; 5100 uint64_t size, dva; 5101 uint8_t *kva; 5102 uint64_t *sdpage; 5103 unsigned int i; 5104 int npages, tables; 5105 uint32_t reg; 5106 5107 CTASSERT(__arraycount(regs) <= __arraycount(sc->sc_hmc_entries)); 5108 5109 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 5110 ixl_rd(sc, I40E_GLHMC_LANQMAX); 5111 5112 size = 0; 5113 for (i = 0; i < __arraycount(regs); i++) { 5114 e = &sc->sc_hmc_entries[i]; 5115 5116 e->hmc_count = regs[i].count; 5117 reg = ixl_rd(sc, regs[i].objsiz); 5118 e->hmc_size = BIT_ULL(0x3F & reg); 5119 e->hmc_base = size; 5120 5121 if ((e->hmc_size * 8) < regs[i].minsize) { 5122 aprint_error_dev(sc->sc_dev, 5123 "kernel hmc entry is too big\n"); 5124 return -1; 5125 } 5126 5127 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 5128 } 5129 size = roundup(size, IXL_HMC_PGSIZE); 5130 npages = size / IXL_HMC_PGSIZE; 5131 5132 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 5133 5134 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 5135 aprint_error_dev(sc->sc_dev, 5136 "unable to allocate hmc pd memory\n"); 5137 return -1; 5138 } 5139 5140 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 5141 IXL_HMC_PGSIZE) != 0) { 5142 aprint_error_dev(sc->sc_dev, 5143 "unable to allocate hmc sd memory\n"); 5144 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 5145 return -1; 5146 } 5147 5148 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 5149 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 5150 5151 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 5152 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 5153 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5154 5155 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 5156 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 5157 memset(sdpage, 0, IXL_DMA_LEN(&sc->sc_hmc_sd)); 5158 5159 for (i = 0; (int)i < npages; i++) { 5160 *sdpage = htole64(dva | IXL_HMC_PDVALID); 5161 sdpage++; 5162 5163 dva += IXL_HMC_PGSIZE; 5164 } 5165 5166 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 5167 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 5168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5169 5170 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 5171 for (i = 0; (int)i < tables; i++) { 5172 uint32_t count; 5173 5174 KASSERT(npages >= 0); 5175 5176 count = ((unsigned int)npages > IXL_HMC_PGS) ? 5177 IXL_HMC_PGS : (unsigned int)npages; 5178 5179 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 5180 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 5181 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 5182 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 5183 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 5184 ixl_wr(sc, I40E_PFHMC_SDCMD, 5185 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 5186 5187 npages -= IXL_HMC_PGS; 5188 dva += IXL_HMC_PGSIZE; 5189 } 5190 5191 for (i = 0; i < __arraycount(regs); i++) { 5192 e = &sc->sc_hmc_entries[i]; 5193 5194 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 5195 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 5196 } 5197 5198 return 0; 5199 } 5200 5201 static void 5202 ixl_hmc_free(struct ixl_softc *sc) 5203 { 5204 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 5205 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 5206 } 5207 5208 static void 5209 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 5210 unsigned int npacking) 5211 { 5212 uint8_t *dst = d; 5213 const uint8_t *src = s; 5214 unsigned int i; 5215 5216 for (i = 0; i < npacking; i++) { 5217 const struct ixl_hmc_pack *pack = &packing[i]; 5218 unsigned int offset = pack->lsb / 8; 5219 unsigned int align = pack->lsb % 8; 5220 const uint8_t *in = src + pack->offset; 5221 uint8_t *out = dst + offset; 5222 int width = pack->width; 5223 unsigned int inbits = 0; 5224 5225 if (align) { 5226 inbits = (*in++) << align; 5227 *out++ |= (inbits & 0xff); 5228 inbits >>= 8; 5229 5230 width -= 8 - align; 5231 } 5232 5233 while (width >= 8) { 5234 inbits |= (*in++) << align; 5235 *out++ = (inbits & 0xff); 5236 inbits >>= 8; 5237 5238 width -= 8; 5239 } 5240 5241 if (width > 0) { 5242 inbits |= (*in) << align; 5243 *out |= (inbits & ((1 << width) - 1)); 5244 } 5245 } 5246 } 5247 5248 static struct ixl_aq_buf * 5249 ixl_aqb_alloc(struct ixl_softc *sc) 5250 { 5251 struct ixl_aq_buf *aqb; 5252 5253 aqb = kmem_alloc(sizeof(*aqb), KM_SLEEP); 5254 5255 aqb->aqb_size = IXL_AQ_BUFLEN; 5256 5257 if (bus_dmamap_create(sc->sc_dmat, aqb->aqb_size, 1, 5258 aqb->aqb_size, 0, 5259 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &aqb->aqb_map) != 0) 5260 goto free; 5261 if (bus_dmamem_alloc(sc->sc_dmat, aqb->aqb_size, 5262 IXL_AQ_ALIGN, 0, &aqb->aqb_seg, 1, &aqb->aqb_nsegs, 5263 BUS_DMA_WAITOK) != 0) 5264 goto destroy; 5265 if (bus_dmamem_map(sc->sc_dmat, &aqb->aqb_seg, aqb->aqb_nsegs, 5266 aqb->aqb_size, &aqb->aqb_data, BUS_DMA_WAITOK) != 0) 5267 goto dma_free; 5268 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 5269 aqb->aqb_size, NULL, BUS_DMA_WAITOK) != 0) 5270 goto unmap; 5271 5272 return aqb; 5273 unmap: 5274 bus_dmamem_unmap(sc->sc_dmat, aqb->aqb_data, aqb->aqb_size); 5275 dma_free: 5276 bus_dmamem_free(sc->sc_dmat, &aqb->aqb_seg, 1); 5277 destroy: 5278 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 5279 free: 5280 kmem_free(aqb, sizeof(*aqb)); 5281 5282 return NULL; 5283 } 5284 5285 static void 5286 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 5287 { 5288 5289 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 5290 bus_dmamem_unmap(sc->sc_dmat, aqb->aqb_data, aqb->aqb_size); 5291 bus_dmamem_free(sc->sc_dmat, &aqb->aqb_seg, 1); 5292 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 5293 kmem_free(aqb, sizeof(*aqb)); 5294 } 5295 5296 static int 5297 ixl_arq_fill(struct ixl_softc *sc) 5298 { 5299 struct ixl_aq_buf *aqb; 5300 struct ixl_aq_desc *arq, *iaq; 5301 unsigned int prod = sc->sc_arq_prod; 5302 unsigned int n; 5303 int post = 0; 5304 5305 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 5306 IXL_AQ_NUM); 5307 arq = IXL_DMA_KVA(&sc->sc_arq); 5308 5309 if (__predict_false(n <= 0)) 5310 return 0; 5311 5312 do { 5313 aqb = sc->sc_arq_live[prod]; 5314 iaq = &arq[prod]; 5315 5316 if (aqb == NULL) { 5317 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 5318 if (aqb != NULL) { 5319 SIMPLEQ_REMOVE(&sc->sc_arq_idle, aqb, 5320 ixl_aq_buf, aqb_entry); 5321 } else if ((aqb = ixl_aqb_alloc(sc)) == NULL) { 5322 break; 5323 } 5324 5325 sc->sc_arq_live[prod] = aqb; 5326 memset(aqb->aqb_data, 0, aqb->aqb_size); 5327 5328 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 5329 aqb->aqb_size, BUS_DMASYNC_PREREAD); 5330 5331 iaq->iaq_flags = htole16(IXL_AQ_BUF | 5332 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? 5333 IXL_AQ_LB : 0)); 5334 iaq->iaq_opcode = 0; 5335 iaq->iaq_datalen = htole16(aqb->aqb_size); 5336 iaq->iaq_retval = 0; 5337 iaq->iaq_cookie = 0; 5338 iaq->iaq_param[0] = 0; 5339 iaq->iaq_param[1] = 0; 5340 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 5341 } 5342 5343 prod++; 5344 prod &= IXL_AQ_MASK; 5345 5346 post = 1; 5347 5348 } while (--n); 5349 5350 if (post) { 5351 sc->sc_arq_prod = prod; 5352 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 5353 } 5354 5355 return post; 5356 } 5357 5358 static void 5359 ixl_arq_unfill(struct ixl_softc *sc) 5360 { 5361 struct ixl_aq_buf *aqb; 5362 unsigned int i; 5363 5364 for (i = 0; i < __arraycount(sc->sc_arq_live); i++) { 5365 aqb = sc->sc_arq_live[i]; 5366 if (aqb == NULL) 5367 continue; 5368 5369 sc->sc_arq_live[i] = NULL; 5370 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 5371 BUS_DMASYNC_POSTREAD); 5372 ixl_aqb_free(sc, aqb); 5373 } 5374 5375 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle)) != NULL) { 5376 SIMPLEQ_REMOVE(&sc->sc_arq_idle, aqb, 5377 ixl_aq_buf, aqb_entry); 5378 ixl_aqb_free(sc, aqb); 5379 } 5380 } 5381 5382 static void 5383 ixl_clear_hw(struct ixl_softc *sc) 5384 { 5385 uint32_t num_queues, base_queue; 5386 uint32_t num_pf_int; 5387 uint32_t num_vf_int; 5388 uint32_t num_vfs; 5389 uint32_t i, j; 5390 uint32_t val; 5391 uint32_t eol = 0x7ff; 5392 5393 /* get number of interrupts, queues, and vfs */ 5394 val = ixl_rd(sc, I40E_GLPCI_CNF2); 5395 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 5396 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 5397 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 5398 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 5399 5400 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 5401 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 5402 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 5403 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 5404 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 5405 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 5406 num_queues = (j - base_queue) + 1; 5407 else 5408 num_queues = 0; 5409 5410 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 5411 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 5412 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 5413 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 5414 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 5415 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 5416 num_vfs = (j - i) + 1; 5417 else 5418 num_vfs = 0; 5419 5420 /* stop all the interrupts */ 5421 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 5422 ixl_flush(sc); 5423 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 5424 for (i = 0; i < num_pf_int - 2; i++) 5425 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 5426 ixl_flush(sc); 5427 5428 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 5429 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5430 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 5431 for (i = 0; i < num_pf_int - 2; i++) 5432 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 5433 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5434 for (i = 0; i < num_vfs; i++) 5435 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 5436 for (i = 0; i < num_vf_int - 2; i++) 5437 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 5438 5439 /* warn the HW of the coming Tx disables */ 5440 for (i = 0; i < num_queues; i++) { 5441 uint32_t abs_queue_idx = base_queue + i; 5442 uint32_t reg_block = 0; 5443 5444 if (abs_queue_idx >= 128) { 5445 reg_block = abs_queue_idx / 128; 5446 abs_queue_idx %= 128; 5447 } 5448 5449 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 5450 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 5451 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 5452 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 5453 5454 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 5455 } 5456 delaymsec(400); 5457 5458 /* stop all the queues */ 5459 for (i = 0; i < num_queues; i++) { 5460 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 5461 ixl_wr(sc, I40E_QTX_ENA(i), 0); 5462 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 5463 ixl_wr(sc, I40E_QRX_ENA(i), 0); 5464 } 5465 5466 /* short wait for all queue disables to settle */ 5467 delaymsec(50); 5468 } 5469 5470 static int 5471 ixl_pf_reset(struct ixl_softc *sc) 5472 { 5473 uint32_t cnt = 0; 5474 uint32_t cnt1 = 0; 5475 uint32_t reg = 0, reg0 = 0; 5476 uint32_t grst_del; 5477 5478 /* 5479 * Poll for Global Reset steady state in case of recent GRST. 5480 * The grst delay value is in 100ms units, and we'll wait a 5481 * couple counts longer to be sure we don't just miss the end. 5482 */ 5483 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 5484 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 5485 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 5486 5487 grst_del = grst_del * 20; 5488 5489 for (cnt = 0; cnt < grst_del; cnt++) { 5490 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 5491 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 5492 break; 5493 delaymsec(100); 5494 } 5495 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5496 aprint_error(", Global reset polling failed to complete\n"); 5497 return -1; 5498 } 5499 5500 /* Now Wait for the FW to be ready */ 5501 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 5502 reg = ixl_rd(sc, I40E_GLNVM_ULD); 5503 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5504 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 5505 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5506 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 5507 break; 5508 5509 delaymsec(10); 5510 } 5511 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5512 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 5513 aprint_error(", wait for FW Reset complete timed out " 5514 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 5515 return -1; 5516 } 5517 5518 /* 5519 * If there was a Global Reset in progress when we got here, 5520 * we don't need to do the PF Reset 5521 */ 5522 if (cnt == 0) { 5523 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5524 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 5525 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 5526 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5527 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 5528 break; 5529 delaymsec(1); 5530 5531 reg0 = ixl_rd(sc, I40E_GLGEN_RSTAT); 5532 if (reg0 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5533 aprint_error(", Core reset upcoming." 5534 " Skipping PF reset reset request\n"); 5535 return -1; 5536 } 5537 } 5538 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 5539 aprint_error(", PF reset polling failed to complete" 5540 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 5541 return -1; 5542 } 5543 } 5544 5545 return 0; 5546 } 5547 5548 static int 5549 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 5550 bus_size_t size, bus_size_t align) 5551 { 5552 ixm->ixm_size = size; 5553 5554 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 5555 ixm->ixm_size, 0, 5556 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 5557 &ixm->ixm_map) != 0) 5558 return 1; 5559 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5560 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5561 BUS_DMA_WAITOK) != 0) 5562 goto destroy; 5563 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5564 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5565 goto free; 5566 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5567 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5568 goto unmap; 5569 5570 memset(ixm->ixm_kva, 0, ixm->ixm_size); 5571 5572 return 0; 5573 unmap: 5574 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5575 free: 5576 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5577 destroy: 5578 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5579 return 1; 5580 } 5581 5582 static void 5583 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5584 { 5585 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5586 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5587 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5588 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5589 } 5590 5591 static int 5592 ixl_setup_vlan_hwfilter(struct ixl_softc *sc) 5593 { 5594 struct ethercom *ec = &sc->sc_ec; 5595 struct vlanid_list *vlanidp; 5596 int rv; 5597 5598 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 5599 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 5600 ixl_remove_macvlan(sc, etherbroadcastaddr, 0, 5601 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 5602 5603 rv = ixl_add_macvlan(sc, sc->sc_enaddr, 0, 5604 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5605 if (rv != 0) 5606 return rv; 5607 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 0, 5608 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5609 if (rv != 0) 5610 return rv; 5611 5612 ETHER_LOCK(ec); 5613 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 5614 rv = ixl_add_macvlan(sc, sc->sc_enaddr, 5615 vlanidp->vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5616 if (rv != 0) 5617 break; 5618 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 5619 vlanidp->vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5620 if (rv != 0) 5621 break; 5622 } 5623 ETHER_UNLOCK(ec); 5624 5625 return rv; 5626 } 5627 5628 static void 5629 ixl_teardown_vlan_hwfilter(struct ixl_softc *sc) 5630 { 5631 struct vlanid_list *vlanidp; 5632 struct ethercom *ec = &sc->sc_ec; 5633 5634 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 5635 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5636 ixl_remove_macvlan(sc, etherbroadcastaddr, 0, 5637 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5638 5639 ETHER_LOCK(ec); 5640 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 5641 ixl_remove_macvlan(sc, sc->sc_enaddr, 5642 vlanidp->vid, IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5643 ixl_remove_macvlan(sc, etherbroadcastaddr, 5644 vlanidp->vid, IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5645 } 5646 ETHER_UNLOCK(ec); 5647 5648 ixl_add_macvlan(sc, sc->sc_enaddr, 0, 5649 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 5650 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 5651 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 5652 } 5653 5654 static int 5655 ixl_update_macvlan(struct ixl_softc *sc) 5656 { 5657 int rv = 0; 5658 int next_ec_capenable = sc->sc_ec.ec_capenable; 5659 5660 if (ISSET(next_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 5661 rv = ixl_setup_vlan_hwfilter(sc); 5662 if (rv != 0) 5663 ixl_teardown_vlan_hwfilter(sc); 5664 } else { 5665 ixl_teardown_vlan_hwfilter(sc); 5666 } 5667 5668 return rv; 5669 } 5670 5671 static int 5672 ixl_ifflags_cb(struct ethercom *ec) 5673 { 5674 struct ifnet *ifp = &ec->ec_if; 5675 struct ixl_softc *sc = ifp->if_softc; 5676 int rv, change; 5677 5678 mutex_enter(&sc->sc_cfg_lock); 5679 5680 change = ec->ec_capenable ^ sc->sc_cur_ec_capenable; 5681 5682 if (ISSET(change, ETHERCAP_VLAN_HWTAGGING)) { 5683 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING; 5684 rv = ENETRESET; 5685 goto out; 5686 } 5687 5688 if (ISSET(change, ETHERCAP_VLAN_HWFILTER)) { 5689 rv = ixl_update_macvlan(sc); 5690 if (rv == 0) { 5691 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER; 5692 } else { 5693 CLR(ec->ec_capenable, ETHERCAP_VLAN_HWFILTER); 5694 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 5695 } 5696 } 5697 5698 rv = ixl_iff(sc); 5699 out: 5700 mutex_exit(&sc->sc_cfg_lock); 5701 5702 return rv; 5703 } 5704 5705 static int 5706 ixl_set_link_status_locked(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 5707 { 5708 const struct ixl_aq_link_status *status; 5709 const struct ixl_phy_type *itype; 5710 5711 uint64_t ifm_active = IFM_ETHER; 5712 uint64_t ifm_status = IFM_AVALID; 5713 int link_state = LINK_STATE_DOWN; 5714 uint64_t baudrate = 0; 5715 5716 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 5717 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) { 5718 ifm_active |= IFM_NONE; 5719 goto done; 5720 } 5721 5722 ifm_active |= IFM_FDX; 5723 ifm_status |= IFM_ACTIVE; 5724 link_state = LINK_STATE_UP; 5725 5726 itype = ixl_search_phy_type(status->phy_type); 5727 if (itype != NULL) 5728 ifm_active |= itype->ifm_type; 5729 5730 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 5731 ifm_active |= IFM_ETH_TXPAUSE; 5732 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 5733 ifm_active |= IFM_ETH_RXPAUSE; 5734 5735 baudrate = ixl_search_link_speed(status->link_speed); 5736 5737 done: 5738 /* sc->sc_cfg_lock held expect during attach */ 5739 sc->sc_media_active = ifm_active; 5740 sc->sc_media_status = ifm_status; 5741 5742 sc->sc_ec.ec_if.if_baudrate = baudrate; 5743 5744 return link_state; 5745 } 5746 5747 static int 5748 ixl_establish_intx(struct ixl_softc *sc) 5749 { 5750 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 5751 pci_intr_handle_t *intr; 5752 char xnamebuf[32]; 5753 char intrbuf[PCI_INTRSTR_LEN]; 5754 char const *intrstr; 5755 5756 KASSERT(sc->sc_nintrs == 1); 5757 5758 intr = &sc->sc_ihp[0]; 5759 5760 intrstr = pci_intr_string(pc, *intr, intrbuf, sizeof(intrbuf)); 5761 snprintf(xnamebuf, sizeof(xnamebuf), "%s:legacy", 5762 device_xname(sc->sc_dev)); 5763 5764 sc->sc_ihs[0] = pci_intr_establish_xname(pc, *intr, IPL_NET, ixl_intr, 5765 sc, xnamebuf); 5766 5767 if (sc->sc_ihs[0] == NULL) { 5768 aprint_error_dev(sc->sc_dev, 5769 "unable to establish interrupt at %s\n", intrstr); 5770 return -1; 5771 } 5772 5773 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 5774 return 0; 5775 } 5776 5777 static int 5778 ixl_establish_msix(struct ixl_softc *sc) 5779 { 5780 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 5781 kcpuset_t *affinity; 5782 unsigned int vector = 0; 5783 unsigned int i; 5784 int affinity_to, r; 5785 char xnamebuf[32]; 5786 char intrbuf[PCI_INTRSTR_LEN]; 5787 char const *intrstr; 5788 5789 kcpuset_create(&affinity, false); 5790 5791 /* the "other" intr is mapped to vector 0 */ 5792 vector = 0; 5793 intrstr = pci_intr_string(pc, sc->sc_ihp[vector], 5794 intrbuf, sizeof(intrbuf)); 5795 snprintf(xnamebuf, sizeof(xnamebuf), "%s others", 5796 device_xname(sc->sc_dev)); 5797 sc->sc_ihs[vector] = pci_intr_establish_xname(pc, 5798 sc->sc_ihp[vector], IPL_NET, ixl_other_intr, 5799 sc, xnamebuf); 5800 if (sc->sc_ihs[vector] == NULL) { 5801 aprint_error_dev(sc->sc_dev, 5802 "unable to establish interrupt at %s\n", intrstr); 5803 goto fail; 5804 } 5805 5806 aprint_normal_dev(sc->sc_dev, "other interrupt at %s", intrstr); 5807 5808 affinity_to = ncpu > (int)sc->sc_nqueue_pairs_max ? 1 : 0; 5809 affinity_to = (affinity_to + sc->sc_nqueue_pairs_max) % ncpu; 5810 5811 kcpuset_zero(affinity); 5812 kcpuset_set(affinity, affinity_to); 5813 r = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 5814 if (r == 0) { 5815 aprint_normal(", affinity to %u", affinity_to); 5816 } 5817 aprint_normal("\n"); 5818 vector++; 5819 5820 sc->sc_msix_vector_queue = vector; 5821 affinity_to = ncpu > (int)sc->sc_nqueue_pairs_max ? 1 : 0; 5822 5823 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 5824 intrstr = pci_intr_string(pc, sc->sc_ihp[vector], 5825 intrbuf, sizeof(intrbuf)); 5826 snprintf(xnamebuf, sizeof(xnamebuf), "%s TXRX%d", 5827 device_xname(sc->sc_dev), i); 5828 5829 sc->sc_ihs[vector] = pci_intr_establish_xname(pc, 5830 sc->sc_ihp[vector], IPL_NET, ixl_queue_intr, 5831 (void *)&sc->sc_qps[i], xnamebuf); 5832 5833 if (sc->sc_ihs[vector] == NULL) { 5834 aprint_error_dev(sc->sc_dev, 5835 "unable to establish interrupt at %s\n", intrstr); 5836 goto fail; 5837 } 5838 5839 aprint_normal_dev(sc->sc_dev, 5840 "for TXRX%d interrupt at %s",i , intrstr); 5841 5842 kcpuset_zero(affinity); 5843 kcpuset_set(affinity, affinity_to); 5844 r = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 5845 if (r == 0) { 5846 aprint_normal(", affinity to %u", affinity_to); 5847 affinity_to = (affinity_to + 1) % ncpu; 5848 } 5849 aprint_normal("\n"); 5850 vector++; 5851 } 5852 5853 kcpuset_destroy(affinity); 5854 5855 return 0; 5856 fail: 5857 for (i = 0; i < vector; i++) { 5858 pci_intr_disestablish(pc, sc->sc_ihs[i]); 5859 } 5860 5861 sc->sc_msix_vector_queue = 0; 5862 sc->sc_msix_vector_queue = 0; 5863 kcpuset_destroy(affinity); 5864 5865 return -1; 5866 } 5867 5868 static void 5869 ixl_config_queue_intr(struct ixl_softc *sc) 5870 { 5871 unsigned int i, vector; 5872 5873 if (sc->sc_intrtype == PCI_INTR_TYPE_MSIX) { 5874 vector = sc->sc_msix_vector_queue; 5875 } else { 5876 vector = I40E_INTR_NOTX_INTR; 5877 5878 ixl_wr(sc, I40E_PFINT_LNKLST0, 5879 (I40E_INTR_NOTX_QUEUE << 5880 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 5881 (I40E_QUEUE_TYPE_RX << 5882 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 5883 } 5884 5885 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 5886 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 0); 5887 ixl_flush(sc); 5888 5889 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 5890 ((i) << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 5891 (I40E_QUEUE_TYPE_RX << 5892 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 5893 5894 ixl_wr(sc, I40E_QINT_RQCTL(i), 5895 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 5896 (I40E_ITR_INDEX_RX << 5897 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 5898 (I40E_INTR_NOTX_RX_QUEUE << 5899 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 5900 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 5901 (I40E_QUEUE_TYPE_TX << 5902 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 5903 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 5904 5905 ixl_wr(sc, I40E_QINT_TQCTL(i), 5906 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 5907 (I40E_ITR_INDEX_TX << 5908 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 5909 (I40E_INTR_NOTX_TX_QUEUE << 5910 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 5911 (I40E_QUEUE_TYPE_EOL << 5912 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 5913 (I40E_QUEUE_TYPE_RX << 5914 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 5915 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 5916 5917 if (sc->sc_intrtype == PCI_INTR_TYPE_MSIX) 5918 vector++; 5919 } 5920 ixl_flush(sc); 5921 5922 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_RX), 0x7a); 5923 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_TX), 0x7a); 5924 ixl_flush(sc); 5925 } 5926 5927 static void 5928 ixl_config_other_intr(struct ixl_softc *sc) 5929 { 5930 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 5931 (void)ixl_rd(sc, I40E_PFINT_ICR0); 5932 5933 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 5934 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 5935 I40E_PFINT_ICR0_ENA_GRST_MASK | 5936 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 5937 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 5938 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | 5939 I40E_PFINT_ICR0_ENA_VFLR_MASK | 5940 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | 5941 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | 5942 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK); 5943 5944 ixl_wr(sc, I40E_PFINT_LNKLST0, 0x7FF); 5945 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_OTHER), 0); 5946 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 5947 (I40E_ITR_INDEX_OTHER << 5948 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)); 5949 ixl_flush(sc); 5950 } 5951 5952 static int 5953 ixl_setup_interrupts(struct ixl_softc *sc) 5954 { 5955 struct pci_attach_args *pa = &sc->sc_pa; 5956 pci_intr_type_t max_type, intr_type; 5957 int counts[PCI_INTR_TYPE_SIZE]; 5958 int error; 5959 unsigned int i; 5960 bool retry; 5961 5962 memset(counts, 0, sizeof(counts)); 5963 max_type = PCI_INTR_TYPE_MSIX; 5964 /* QPs + other interrupt */ 5965 counts[PCI_INTR_TYPE_MSIX] = sc->sc_nqueue_pairs_max + 1; 5966 counts[PCI_INTR_TYPE_INTX] = 1; 5967 5968 if (ixl_param_nomsix) 5969 counts[PCI_INTR_TYPE_MSIX] = 0; 5970 5971 do { 5972 retry = false; 5973 error = pci_intr_alloc(pa, &sc->sc_ihp, counts, max_type); 5974 if (error != 0) { 5975 aprint_error_dev(sc->sc_dev, 5976 "couldn't map interrupt\n"); 5977 break; 5978 } 5979 5980 intr_type = pci_intr_type(pa->pa_pc, sc->sc_ihp[0]); 5981 sc->sc_nintrs = counts[intr_type]; 5982 KASSERT(sc->sc_nintrs > 0); 5983 5984 for (i = 0; i < sc->sc_nintrs; i++) { 5985 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[i], 5986 PCI_INTR_MPSAFE, true); 5987 } 5988 5989 sc->sc_ihs = kmem_alloc(sizeof(sc->sc_ihs[0]) * sc->sc_nintrs, 5990 KM_SLEEP); 5991 5992 if (intr_type == PCI_INTR_TYPE_MSIX) { 5993 error = ixl_establish_msix(sc); 5994 if (error) { 5995 counts[PCI_INTR_TYPE_MSIX] = 0; 5996 retry = true; 5997 } 5998 } else if (intr_type == PCI_INTR_TYPE_INTX) { 5999 error = ixl_establish_intx(sc); 6000 } else { 6001 error = -1; 6002 } 6003 6004 if (error) { 6005 kmem_free(sc->sc_ihs, 6006 sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 6007 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 6008 } else { 6009 sc->sc_intrtype = intr_type; 6010 } 6011 } while (retry); 6012 6013 return error; 6014 } 6015 6016 static void 6017 ixl_teardown_interrupts(struct ixl_softc *sc) 6018 { 6019 struct pci_attach_args *pa = &sc->sc_pa; 6020 unsigned int i; 6021 6022 for (i = 0; i < sc->sc_nintrs; i++) { 6023 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[i]); 6024 } 6025 6026 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 6027 6028 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 6029 sc->sc_ihs = NULL; 6030 sc->sc_nintrs = 0; 6031 } 6032 6033 static int 6034 ixl_setup_stats(struct ixl_softc *sc) 6035 { 6036 struct ixl_queue_pair *qp; 6037 struct ixl_tx_ring *txr; 6038 struct ixl_rx_ring *rxr; 6039 struct ixl_stats_counters *isc; 6040 unsigned int i; 6041 6042 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 6043 qp = &sc->sc_qps[i]; 6044 txr = qp->qp_txr; 6045 rxr = qp->qp_rxr; 6046 6047 evcnt_attach_dynamic(&txr->txr_defragged, EVCNT_TYPE_MISC, 6048 NULL, qp->qp_name, "m_defrag successed"); 6049 evcnt_attach_dynamic(&txr->txr_defrag_failed, EVCNT_TYPE_MISC, 6050 NULL, qp->qp_name, "m_defrag_failed"); 6051 evcnt_attach_dynamic(&txr->txr_pcqdrop, EVCNT_TYPE_MISC, 6052 NULL, qp->qp_name, "Dropped in pcq"); 6053 evcnt_attach_dynamic(&txr->txr_transmitdef, EVCNT_TYPE_MISC, 6054 NULL, qp->qp_name, "Deferred transmit"); 6055 evcnt_attach_dynamic(&txr->txr_intr, EVCNT_TYPE_INTR, 6056 NULL, qp->qp_name, "Interrupt on queue"); 6057 evcnt_attach_dynamic(&txr->txr_defer, EVCNT_TYPE_MISC, 6058 NULL, qp->qp_name, "Handled queue in softint/workqueue"); 6059 6060 evcnt_attach_dynamic(&rxr->rxr_mgethdr_failed, EVCNT_TYPE_MISC, 6061 NULL, qp->qp_name, "MGETHDR failed"); 6062 evcnt_attach_dynamic(&rxr->rxr_mgetcl_failed, EVCNT_TYPE_MISC, 6063 NULL, qp->qp_name, "MCLGET failed"); 6064 evcnt_attach_dynamic(&rxr->rxr_mbuf_load_failed, 6065 EVCNT_TYPE_MISC, NULL, qp->qp_name, 6066 "bus_dmamap_load_mbuf failed"); 6067 evcnt_attach_dynamic(&rxr->rxr_intr, EVCNT_TYPE_INTR, 6068 NULL, qp->qp_name, "Interrupt on queue"); 6069 evcnt_attach_dynamic(&rxr->rxr_defer, EVCNT_TYPE_MISC, 6070 NULL, qp->qp_name, "Handled queue in softint/workqueue"); 6071 } 6072 6073 evcnt_attach_dynamic(&sc->sc_event_atq, EVCNT_TYPE_INTR, 6074 NULL, device_xname(sc->sc_dev), "Interrupt for other events"); 6075 evcnt_attach_dynamic(&sc->sc_event_link, EVCNT_TYPE_MISC, 6076 NULL, device_xname(sc->sc_dev), "Link status event"); 6077 evcnt_attach_dynamic(&sc->sc_event_ecc_err, EVCNT_TYPE_MISC, 6078 NULL, device_xname(sc->sc_dev), "ECC error"); 6079 evcnt_attach_dynamic(&sc->sc_event_pci_exception, EVCNT_TYPE_MISC, 6080 NULL, device_xname(sc->sc_dev), "PCI exception"); 6081 evcnt_attach_dynamic(&sc->sc_event_crit_err, EVCNT_TYPE_MISC, 6082 NULL, device_xname(sc->sc_dev), "Critical error"); 6083 6084 isc = &sc->sc_stats_counters; 6085 evcnt_attach_dynamic(&isc->isc_crc_errors, EVCNT_TYPE_MISC, 6086 NULL, device_xname(sc->sc_dev), "CRC errors"); 6087 evcnt_attach_dynamic(&isc->isc_illegal_bytes, EVCNT_TYPE_MISC, 6088 NULL, device_xname(sc->sc_dev), "Illegal bytes"); 6089 evcnt_attach_dynamic(&isc->isc_mac_local_faults, EVCNT_TYPE_MISC, 6090 NULL, device_xname(sc->sc_dev), "Mac local faults"); 6091 evcnt_attach_dynamic(&isc->isc_mac_remote_faults, EVCNT_TYPE_MISC, 6092 NULL, device_xname(sc->sc_dev), "Mac remote faults"); 6093 evcnt_attach_dynamic(&isc->isc_link_xon_rx, EVCNT_TYPE_MISC, 6094 NULL, device_xname(sc->sc_dev), "Rx xon"); 6095 evcnt_attach_dynamic(&isc->isc_link_xon_tx, EVCNT_TYPE_MISC, 6096 NULL, device_xname(sc->sc_dev), "Tx xon"); 6097 evcnt_attach_dynamic(&isc->isc_link_xoff_rx, EVCNT_TYPE_MISC, 6098 NULL, device_xname(sc->sc_dev), "Rx xoff"); 6099 evcnt_attach_dynamic(&isc->isc_link_xoff_tx, EVCNT_TYPE_MISC, 6100 NULL, device_xname(sc->sc_dev), "Tx xoff"); 6101 evcnt_attach_dynamic(&isc->isc_rx_fragments, EVCNT_TYPE_MISC, 6102 NULL, device_xname(sc->sc_dev), "Rx fragments"); 6103 evcnt_attach_dynamic(&isc->isc_rx_jabber, EVCNT_TYPE_MISC, 6104 NULL, device_xname(sc->sc_dev), "Rx jabber"); 6105 6106 evcnt_attach_dynamic(&isc->isc_rx_size_64, EVCNT_TYPE_MISC, 6107 NULL, device_xname(sc->sc_dev), "Rx size 64"); 6108 evcnt_attach_dynamic(&isc->isc_rx_size_127, EVCNT_TYPE_MISC, 6109 NULL, device_xname(sc->sc_dev), "Rx size 127"); 6110 evcnt_attach_dynamic(&isc->isc_rx_size_255, EVCNT_TYPE_MISC, 6111 NULL, device_xname(sc->sc_dev), "Rx size 255"); 6112 evcnt_attach_dynamic(&isc->isc_rx_size_511, EVCNT_TYPE_MISC, 6113 NULL, device_xname(sc->sc_dev), "Rx size 511"); 6114 evcnt_attach_dynamic(&isc->isc_rx_size_1023, EVCNT_TYPE_MISC, 6115 NULL, device_xname(sc->sc_dev), "Rx size 1023"); 6116 evcnt_attach_dynamic(&isc->isc_rx_size_1522, EVCNT_TYPE_MISC, 6117 NULL, device_xname(sc->sc_dev), "Rx size 1522"); 6118 evcnt_attach_dynamic(&isc->isc_rx_size_big, EVCNT_TYPE_MISC, 6119 NULL, device_xname(sc->sc_dev), "Rx jumbo packets"); 6120 evcnt_attach_dynamic(&isc->isc_rx_undersize, EVCNT_TYPE_MISC, 6121 NULL, device_xname(sc->sc_dev), "Rx under size"); 6122 evcnt_attach_dynamic(&isc->isc_rx_oversize, EVCNT_TYPE_MISC, 6123 NULL, device_xname(sc->sc_dev), "Rx over size"); 6124 6125 evcnt_attach_dynamic(&isc->isc_rx_bytes, EVCNT_TYPE_MISC, 6126 NULL, device_xname(sc->sc_dev), "Rx bytes / port"); 6127 evcnt_attach_dynamic(&isc->isc_rx_discards, EVCNT_TYPE_MISC, 6128 NULL, device_xname(sc->sc_dev), "Rx discards / port"); 6129 evcnt_attach_dynamic(&isc->isc_rx_unicast, EVCNT_TYPE_MISC, 6130 NULL, device_xname(sc->sc_dev), "Rx unicast / port"); 6131 evcnt_attach_dynamic(&isc->isc_rx_multicast, EVCNT_TYPE_MISC, 6132 NULL, device_xname(sc->sc_dev), "Rx multicast / port"); 6133 evcnt_attach_dynamic(&isc->isc_rx_broadcast, EVCNT_TYPE_MISC, 6134 NULL, device_xname(sc->sc_dev), "Rx broadcast / port"); 6135 6136 evcnt_attach_dynamic(&isc->isc_vsi_rx_bytes, EVCNT_TYPE_MISC, 6137 NULL, device_xname(sc->sc_dev), "Rx bytes / vsi"); 6138 evcnt_attach_dynamic(&isc->isc_vsi_rx_discards, EVCNT_TYPE_MISC, 6139 NULL, device_xname(sc->sc_dev), "Rx discard / vsi"); 6140 evcnt_attach_dynamic(&isc->isc_vsi_rx_unicast, EVCNT_TYPE_MISC, 6141 NULL, device_xname(sc->sc_dev), "Rx unicast / vsi"); 6142 evcnt_attach_dynamic(&isc->isc_vsi_rx_multicast, EVCNT_TYPE_MISC, 6143 NULL, device_xname(sc->sc_dev), "Rx multicast / vsi"); 6144 evcnt_attach_dynamic(&isc->isc_vsi_rx_broadcast, EVCNT_TYPE_MISC, 6145 NULL, device_xname(sc->sc_dev), "Rx broadcast / vsi"); 6146 6147 evcnt_attach_dynamic(&isc->isc_tx_size_64, EVCNT_TYPE_MISC, 6148 NULL, device_xname(sc->sc_dev), "Tx size 64"); 6149 evcnt_attach_dynamic(&isc->isc_tx_size_127, EVCNT_TYPE_MISC, 6150 NULL, device_xname(sc->sc_dev), "Tx size 127"); 6151 evcnt_attach_dynamic(&isc->isc_tx_size_255, EVCNT_TYPE_MISC, 6152 NULL, device_xname(sc->sc_dev), "Tx size 255"); 6153 evcnt_attach_dynamic(&isc->isc_tx_size_511, EVCNT_TYPE_MISC, 6154 NULL, device_xname(sc->sc_dev), "Tx size 511"); 6155 evcnt_attach_dynamic(&isc->isc_tx_size_1023, EVCNT_TYPE_MISC, 6156 NULL, device_xname(sc->sc_dev), "Tx size 1023"); 6157 evcnt_attach_dynamic(&isc->isc_tx_size_1522, EVCNT_TYPE_MISC, 6158 NULL, device_xname(sc->sc_dev), "Tx size 1522"); 6159 evcnt_attach_dynamic(&isc->isc_tx_size_big, EVCNT_TYPE_MISC, 6160 NULL, device_xname(sc->sc_dev), "Tx jumbo packets"); 6161 6162 evcnt_attach_dynamic(&isc->isc_tx_bytes, EVCNT_TYPE_MISC, 6163 NULL, device_xname(sc->sc_dev), "Tx bytes / port"); 6164 evcnt_attach_dynamic(&isc->isc_tx_dropped_link_down, EVCNT_TYPE_MISC, 6165 NULL, device_xname(sc->sc_dev), 6166 "Tx dropped due to link down / port"); 6167 evcnt_attach_dynamic(&isc->isc_tx_unicast, EVCNT_TYPE_MISC, 6168 NULL, device_xname(sc->sc_dev), "Tx unicast / port"); 6169 evcnt_attach_dynamic(&isc->isc_tx_multicast, EVCNT_TYPE_MISC, 6170 NULL, device_xname(sc->sc_dev), "Tx multicast / port"); 6171 evcnt_attach_dynamic(&isc->isc_tx_broadcast, EVCNT_TYPE_MISC, 6172 NULL, device_xname(sc->sc_dev), "Tx broadcast / port"); 6173 6174 evcnt_attach_dynamic(&isc->isc_vsi_tx_bytes, EVCNT_TYPE_MISC, 6175 NULL, device_xname(sc->sc_dev), "Tx bytes / vsi"); 6176 evcnt_attach_dynamic(&isc->isc_vsi_tx_errors, EVCNT_TYPE_MISC, 6177 NULL, device_xname(sc->sc_dev), "Tx errors / vsi"); 6178 evcnt_attach_dynamic(&isc->isc_vsi_tx_unicast, EVCNT_TYPE_MISC, 6179 NULL, device_xname(sc->sc_dev), "Tx unicast / vsi"); 6180 evcnt_attach_dynamic(&isc->isc_vsi_tx_multicast, EVCNT_TYPE_MISC, 6181 NULL, device_xname(sc->sc_dev), "Tx multicast / vsi"); 6182 evcnt_attach_dynamic(&isc->isc_vsi_tx_broadcast, EVCNT_TYPE_MISC, 6183 NULL, device_xname(sc->sc_dev), "Tx broadcast / vsi"); 6184 6185 sc->sc_stats_intval = ixl_param_stats_interval; 6186 callout_init(&sc->sc_stats_callout, CALLOUT_MPSAFE); 6187 callout_setfunc(&sc->sc_stats_callout, ixl_stats_callout, sc); 6188 ixl_work_set(&sc->sc_stats_task, ixl_stats_update, sc); 6189 6190 return 0; 6191 } 6192 6193 static void 6194 ixl_teardown_stats(struct ixl_softc *sc) 6195 { 6196 struct ixl_tx_ring *txr; 6197 struct ixl_rx_ring *rxr; 6198 struct ixl_stats_counters *isc; 6199 unsigned int i; 6200 6201 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 6202 txr = sc->sc_qps[i].qp_txr; 6203 rxr = sc->sc_qps[i].qp_rxr; 6204 6205 evcnt_detach(&txr->txr_defragged); 6206 evcnt_detach(&txr->txr_defrag_failed); 6207 evcnt_detach(&txr->txr_pcqdrop); 6208 evcnt_detach(&txr->txr_transmitdef); 6209 evcnt_detach(&txr->txr_intr); 6210 evcnt_detach(&txr->txr_defer); 6211 6212 evcnt_detach(&rxr->rxr_mgethdr_failed); 6213 evcnt_detach(&rxr->rxr_mgetcl_failed); 6214 evcnt_detach(&rxr->rxr_mbuf_load_failed); 6215 evcnt_detach(&rxr->rxr_intr); 6216 evcnt_detach(&rxr->rxr_defer); 6217 } 6218 6219 isc = &sc->sc_stats_counters; 6220 evcnt_detach(&isc->isc_crc_errors); 6221 evcnt_detach(&isc->isc_illegal_bytes); 6222 evcnt_detach(&isc->isc_mac_local_faults); 6223 evcnt_detach(&isc->isc_mac_remote_faults); 6224 evcnt_detach(&isc->isc_link_xon_rx); 6225 evcnt_detach(&isc->isc_link_xon_tx); 6226 evcnt_detach(&isc->isc_link_xoff_rx); 6227 evcnt_detach(&isc->isc_link_xoff_tx); 6228 evcnt_detach(&isc->isc_rx_fragments); 6229 evcnt_detach(&isc->isc_rx_jabber); 6230 evcnt_detach(&isc->isc_rx_bytes); 6231 evcnt_detach(&isc->isc_rx_discards); 6232 evcnt_detach(&isc->isc_rx_unicast); 6233 evcnt_detach(&isc->isc_rx_multicast); 6234 evcnt_detach(&isc->isc_rx_broadcast); 6235 evcnt_detach(&isc->isc_rx_size_64); 6236 evcnt_detach(&isc->isc_rx_size_127); 6237 evcnt_detach(&isc->isc_rx_size_255); 6238 evcnt_detach(&isc->isc_rx_size_511); 6239 evcnt_detach(&isc->isc_rx_size_1023); 6240 evcnt_detach(&isc->isc_rx_size_1522); 6241 evcnt_detach(&isc->isc_rx_size_big); 6242 evcnt_detach(&isc->isc_rx_undersize); 6243 evcnt_detach(&isc->isc_rx_oversize); 6244 evcnt_detach(&isc->isc_tx_bytes); 6245 evcnt_detach(&isc->isc_tx_dropped_link_down); 6246 evcnt_detach(&isc->isc_tx_unicast); 6247 evcnt_detach(&isc->isc_tx_multicast); 6248 evcnt_detach(&isc->isc_tx_broadcast); 6249 evcnt_detach(&isc->isc_tx_size_64); 6250 evcnt_detach(&isc->isc_tx_size_127); 6251 evcnt_detach(&isc->isc_tx_size_255); 6252 evcnt_detach(&isc->isc_tx_size_511); 6253 evcnt_detach(&isc->isc_tx_size_1023); 6254 evcnt_detach(&isc->isc_tx_size_1522); 6255 evcnt_detach(&isc->isc_tx_size_big); 6256 evcnt_detach(&isc->isc_vsi_rx_discards); 6257 evcnt_detach(&isc->isc_vsi_rx_bytes); 6258 evcnt_detach(&isc->isc_vsi_rx_unicast); 6259 evcnt_detach(&isc->isc_vsi_rx_multicast); 6260 evcnt_detach(&isc->isc_vsi_rx_broadcast); 6261 evcnt_detach(&isc->isc_vsi_tx_errors); 6262 evcnt_detach(&isc->isc_vsi_tx_bytes); 6263 evcnt_detach(&isc->isc_vsi_tx_unicast); 6264 evcnt_detach(&isc->isc_vsi_tx_multicast); 6265 evcnt_detach(&isc->isc_vsi_tx_broadcast); 6266 6267 evcnt_detach(&sc->sc_event_atq); 6268 evcnt_detach(&sc->sc_event_link); 6269 evcnt_detach(&sc->sc_event_ecc_err); 6270 evcnt_detach(&sc->sc_event_pci_exception); 6271 evcnt_detach(&sc->sc_event_crit_err); 6272 6273 callout_destroy(&sc->sc_stats_callout); 6274 } 6275 6276 static void 6277 ixl_stats_callout(void *xsc) 6278 { 6279 struct ixl_softc *sc = xsc; 6280 6281 ixl_work_add(sc->sc_workq, &sc->sc_stats_task); 6282 callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval)); 6283 } 6284 6285 static uint64_t 6286 ixl_stat_delta(struct ixl_softc *sc, uint32_t reg_hi, uint32_t reg_lo, 6287 uint64_t *offset, bool has_offset) 6288 { 6289 uint64_t value, delta; 6290 int bitwidth; 6291 6292 bitwidth = reg_hi == 0 ? 32 : 48; 6293 6294 value = ixl_rd(sc, reg_lo); 6295 6296 if (bitwidth > 32) { 6297 value |= ((uint64_t)ixl_rd(sc, reg_hi) << 32); 6298 } 6299 6300 if (__predict_true(has_offset)) { 6301 delta = value; 6302 if (value < *offset) 6303 delta += ((uint64_t)1 << bitwidth); 6304 delta -= *offset; 6305 } else { 6306 delta = 0; 6307 } 6308 atomic_swap_64(offset, value); 6309 6310 return delta; 6311 } 6312 6313 static void 6314 ixl_stats_update(void *xsc) 6315 { 6316 struct ixl_softc *sc = xsc; 6317 struct ixl_stats_counters *isc; 6318 uint64_t delta; 6319 6320 isc = &sc->sc_stats_counters; 6321 6322 /* errors */ 6323 delta = ixl_stat_delta(sc, 6324 0, I40E_GLPRT_CRCERRS(sc->sc_port), 6325 &isc->isc_crc_errors_offset, isc->isc_has_offset); 6326 atomic_add_64(&isc->isc_crc_errors.ev_count, delta); 6327 6328 delta = ixl_stat_delta(sc, 6329 0, I40E_GLPRT_ILLERRC(sc->sc_port), 6330 &isc->isc_illegal_bytes_offset, isc->isc_has_offset); 6331 atomic_add_64(&isc->isc_illegal_bytes.ev_count, delta); 6332 6333 /* rx */ 6334 delta = ixl_stat_delta(sc, 6335 I40E_GLPRT_GORCH(sc->sc_port), I40E_GLPRT_GORCL(sc->sc_port), 6336 &isc->isc_rx_bytes_offset, isc->isc_has_offset); 6337 atomic_add_64(&isc->isc_rx_bytes.ev_count, delta); 6338 6339 delta = ixl_stat_delta(sc, 6340 0, I40E_GLPRT_RDPC(sc->sc_port), 6341 &isc->isc_rx_discards_offset, isc->isc_has_offset); 6342 atomic_add_64(&isc->isc_rx_discards.ev_count, delta); 6343 6344 delta = ixl_stat_delta(sc, 6345 I40E_GLPRT_UPRCH(sc->sc_port), I40E_GLPRT_UPRCL(sc->sc_port), 6346 &isc->isc_rx_unicast_offset, isc->isc_has_offset); 6347 atomic_add_64(&isc->isc_rx_unicast.ev_count, delta); 6348 6349 delta = ixl_stat_delta(sc, 6350 I40E_GLPRT_MPRCH(sc->sc_port), I40E_GLPRT_MPRCL(sc->sc_port), 6351 &isc->isc_rx_multicast_offset, isc->isc_has_offset); 6352 atomic_add_64(&isc->isc_rx_multicast.ev_count, delta); 6353 6354 delta = ixl_stat_delta(sc, 6355 I40E_GLPRT_BPRCH(sc->sc_port), I40E_GLPRT_BPRCL(sc->sc_port), 6356 &isc->isc_rx_broadcast_offset, isc->isc_has_offset); 6357 atomic_add_64(&isc->isc_rx_broadcast.ev_count, delta); 6358 6359 /* Packet size stats rx */ 6360 delta = ixl_stat_delta(sc, 6361 I40E_GLPRT_PRC64H(sc->sc_port), I40E_GLPRT_PRC64L(sc->sc_port), 6362 &isc->isc_rx_size_64_offset, isc->isc_has_offset); 6363 atomic_add_64(&isc->isc_rx_size_64.ev_count, delta); 6364 6365 delta = ixl_stat_delta(sc, 6366 I40E_GLPRT_PRC127H(sc->sc_port), I40E_GLPRT_PRC127L(sc->sc_port), 6367 &isc->isc_rx_size_127_offset, isc->isc_has_offset); 6368 atomic_add_64(&isc->isc_rx_size_127.ev_count, delta); 6369 6370 delta = ixl_stat_delta(sc, 6371 I40E_GLPRT_PRC255H(sc->sc_port), I40E_GLPRT_PRC255L(sc->sc_port), 6372 &isc->isc_rx_size_255_offset, isc->isc_has_offset); 6373 atomic_add_64(&isc->isc_rx_size_255.ev_count, delta); 6374 6375 delta = ixl_stat_delta(sc, 6376 I40E_GLPRT_PRC511H(sc->sc_port), I40E_GLPRT_PRC511L(sc->sc_port), 6377 &isc->isc_rx_size_511_offset, isc->isc_has_offset); 6378 atomic_add_64(&isc->isc_rx_size_511.ev_count, delta); 6379 6380 delta = ixl_stat_delta(sc, 6381 I40E_GLPRT_PRC1023H(sc->sc_port), I40E_GLPRT_PRC1023L(sc->sc_port), 6382 &isc->isc_rx_size_1023_offset, isc->isc_has_offset); 6383 atomic_add_64(&isc->isc_rx_size_1023.ev_count, delta); 6384 6385 delta = ixl_stat_delta(sc, 6386 I40E_GLPRT_PRC1522H(sc->sc_port), I40E_GLPRT_PRC1522L(sc->sc_port), 6387 &isc->isc_rx_size_1522_offset, isc->isc_has_offset); 6388 atomic_add_64(&isc->isc_rx_size_1522.ev_count, delta); 6389 6390 delta = ixl_stat_delta(sc, 6391 I40E_GLPRT_PRC9522H(sc->sc_port), I40E_GLPRT_PRC9522L(sc->sc_port), 6392 &isc->isc_rx_size_big_offset, isc->isc_has_offset); 6393 atomic_add_64(&isc->isc_rx_size_big.ev_count, delta); 6394 6395 delta = ixl_stat_delta(sc, 6396 0, I40E_GLPRT_RUC(sc->sc_port), 6397 &isc->isc_rx_undersize_offset, isc->isc_has_offset); 6398 atomic_add_64(&isc->isc_rx_undersize.ev_count, delta); 6399 6400 delta = ixl_stat_delta(sc, 6401 0, I40E_GLPRT_ROC(sc->sc_port), 6402 &isc->isc_rx_oversize_offset, isc->isc_has_offset); 6403 atomic_add_64(&isc->isc_rx_oversize.ev_count, delta); 6404 6405 /* tx */ 6406 delta = ixl_stat_delta(sc, 6407 I40E_GLPRT_GOTCH(sc->sc_port), I40E_GLPRT_GOTCL(sc->sc_port), 6408 &isc->isc_tx_bytes_offset, isc->isc_has_offset); 6409 atomic_add_64(&isc->isc_tx_bytes.ev_count, delta); 6410 6411 delta = ixl_stat_delta(sc, 6412 0, I40E_GLPRT_TDOLD(sc->sc_port), 6413 &isc->isc_tx_dropped_link_down_offset, isc->isc_has_offset); 6414 atomic_add_64(&isc->isc_tx_dropped_link_down.ev_count, delta); 6415 6416 delta = ixl_stat_delta(sc, 6417 I40E_GLPRT_UPTCH(sc->sc_port), I40E_GLPRT_UPTCL(sc->sc_port), 6418 &isc->isc_tx_unicast_offset, isc->isc_has_offset); 6419 atomic_add_64(&isc->isc_tx_unicast.ev_count, delta); 6420 6421 delta = ixl_stat_delta(sc, 6422 I40E_GLPRT_MPTCH(sc->sc_port), I40E_GLPRT_MPTCL(sc->sc_port), 6423 &isc->isc_tx_multicast_offset, isc->isc_has_offset); 6424 atomic_add_64(&isc->isc_tx_multicast.ev_count, delta); 6425 6426 delta = ixl_stat_delta(sc, 6427 I40E_GLPRT_BPTCH(sc->sc_port), I40E_GLPRT_BPTCL(sc->sc_port), 6428 &isc->isc_tx_broadcast_offset, isc->isc_has_offset); 6429 atomic_add_64(&isc->isc_tx_broadcast.ev_count, delta); 6430 6431 /* Packet size stats tx */ 6432 delta = ixl_stat_delta(sc, 6433 I40E_GLPRT_PTC64L(sc->sc_port), I40E_GLPRT_PTC64L(sc->sc_port), 6434 &isc->isc_tx_size_64_offset, isc->isc_has_offset); 6435 atomic_add_64(&isc->isc_tx_size_64.ev_count, delta); 6436 6437 delta = ixl_stat_delta(sc, 6438 I40E_GLPRT_PTC127H(sc->sc_port), I40E_GLPRT_PTC127L(sc->sc_port), 6439 &isc->isc_tx_size_127_offset, isc->isc_has_offset); 6440 atomic_add_64(&isc->isc_tx_size_127.ev_count, delta); 6441 6442 delta = ixl_stat_delta(sc, 6443 I40E_GLPRT_PTC255H(sc->sc_port), I40E_GLPRT_PTC255L(sc->sc_port), 6444 &isc->isc_tx_size_255_offset, isc->isc_has_offset); 6445 atomic_add_64(&isc->isc_tx_size_255.ev_count, delta); 6446 6447 delta = ixl_stat_delta(sc, 6448 I40E_GLPRT_PTC511H(sc->sc_port), I40E_GLPRT_PTC511L(sc->sc_port), 6449 &isc->isc_tx_size_511_offset, isc->isc_has_offset); 6450 atomic_add_64(&isc->isc_tx_size_511.ev_count, delta); 6451 6452 delta = ixl_stat_delta(sc, 6453 I40E_GLPRT_PTC1023H(sc->sc_port), I40E_GLPRT_PTC1023L(sc->sc_port), 6454 &isc->isc_tx_size_1023_offset, isc->isc_has_offset); 6455 atomic_add_64(&isc->isc_tx_size_1023.ev_count, delta); 6456 6457 delta = ixl_stat_delta(sc, 6458 I40E_GLPRT_PTC1522H(sc->sc_port), I40E_GLPRT_PTC1522L(sc->sc_port), 6459 &isc->isc_tx_size_1522_offset, isc->isc_has_offset); 6460 atomic_add_64(&isc->isc_tx_size_1522.ev_count, delta); 6461 6462 delta = ixl_stat_delta(sc, 6463 I40E_GLPRT_PTC9522H(sc->sc_port), I40E_GLPRT_PTC9522L(sc->sc_port), 6464 &isc->isc_tx_size_big_offset, isc->isc_has_offset); 6465 atomic_add_64(&isc->isc_tx_size_big.ev_count, delta); 6466 6467 /* mac faults */ 6468 delta = ixl_stat_delta(sc, 6469 0, I40E_GLPRT_MLFC(sc->sc_port), 6470 &isc->isc_mac_local_faults_offset, isc->isc_has_offset); 6471 atomic_add_64(&isc->isc_mac_local_faults.ev_count, delta); 6472 6473 delta = ixl_stat_delta(sc, 6474 0, I40E_GLPRT_MRFC(sc->sc_port), 6475 &isc->isc_mac_remote_faults_offset, isc->isc_has_offset); 6476 atomic_add_64(&isc->isc_mac_remote_faults.ev_count, delta); 6477 6478 /* Flow control (LFC) stats */ 6479 delta = ixl_stat_delta(sc, 6480 0, I40E_GLPRT_LXONRXC(sc->sc_port), 6481 &isc->isc_link_xon_rx_offset, isc->isc_has_offset); 6482 atomic_add_64(&isc->isc_link_xon_rx.ev_count, delta); 6483 6484 delta = ixl_stat_delta(sc, 6485 0, I40E_GLPRT_LXONTXC(sc->sc_port), 6486 &isc->isc_link_xon_tx_offset, isc->isc_has_offset); 6487 atomic_add_64(&isc->isc_link_xon_tx.ev_count, delta); 6488 6489 delta = ixl_stat_delta(sc, 6490 0, I40E_GLPRT_LXOFFRXC(sc->sc_port), 6491 &isc->isc_link_xoff_rx_offset, isc->isc_has_offset); 6492 atomic_add_64(&isc->isc_link_xoff_rx.ev_count, delta); 6493 6494 delta = ixl_stat_delta(sc, 6495 0, I40E_GLPRT_LXOFFTXC(sc->sc_port), 6496 &isc->isc_link_xoff_tx_offset, isc->isc_has_offset); 6497 atomic_add_64(&isc->isc_link_xoff_tx.ev_count, delta); 6498 6499 /* fragments */ 6500 delta = ixl_stat_delta(sc, 6501 0, I40E_GLPRT_RFC(sc->sc_port), 6502 &isc->isc_rx_fragments_offset, isc->isc_has_offset); 6503 atomic_add_64(&isc->isc_rx_fragments.ev_count, delta); 6504 6505 delta = ixl_stat_delta(sc, 6506 0, I40E_GLPRT_RJC(sc->sc_port), 6507 &isc->isc_rx_jabber_offset, isc->isc_has_offset); 6508 atomic_add_64(&isc->isc_rx_jabber.ev_count, delta); 6509 6510 /* VSI rx counters */ 6511 delta = ixl_stat_delta(sc, 6512 0, I40E_GLV_RDPC(sc->sc_vsi_stat_counter_idx), 6513 &isc->isc_vsi_rx_discards_offset, isc->isc_has_offset); 6514 atomic_add_64(&isc->isc_vsi_rx_discards.ev_count, delta); 6515 6516 delta = ixl_stat_delta(sc, 6517 I40E_GLV_GORCH(sc->sc_vsi_stat_counter_idx), 6518 I40E_GLV_GORCL(sc->sc_vsi_stat_counter_idx), 6519 &isc->isc_vsi_rx_bytes_offset, isc->isc_has_offset); 6520 atomic_add_64(&isc->isc_vsi_rx_bytes.ev_count, delta); 6521 6522 delta = ixl_stat_delta(sc, 6523 I40E_GLV_UPRCH(sc->sc_vsi_stat_counter_idx), 6524 I40E_GLV_UPRCL(sc->sc_vsi_stat_counter_idx), 6525 &isc->isc_vsi_rx_unicast_offset, isc->isc_has_offset); 6526 atomic_add_64(&isc->isc_vsi_rx_unicast.ev_count, delta); 6527 6528 delta = ixl_stat_delta(sc, 6529 I40E_GLV_MPRCH(sc->sc_vsi_stat_counter_idx), 6530 I40E_GLV_MPRCL(sc->sc_vsi_stat_counter_idx), 6531 &isc->isc_vsi_rx_multicast_offset, isc->isc_has_offset); 6532 atomic_add_64(&isc->isc_vsi_rx_multicast.ev_count, delta); 6533 6534 delta = ixl_stat_delta(sc, 6535 I40E_GLV_BPRCH(sc->sc_vsi_stat_counter_idx), 6536 I40E_GLV_BPRCL(sc->sc_vsi_stat_counter_idx), 6537 &isc->isc_vsi_rx_broadcast_offset, isc->isc_has_offset); 6538 atomic_add_64(&isc->isc_vsi_rx_broadcast.ev_count, delta); 6539 6540 /* VSI tx counters */ 6541 delta = ixl_stat_delta(sc, 6542 0, I40E_GLV_TEPC(sc->sc_vsi_stat_counter_idx), 6543 &isc->isc_vsi_tx_errors_offset, isc->isc_has_offset); 6544 atomic_add_64(&isc->isc_vsi_tx_errors.ev_count, delta); 6545 6546 delta = ixl_stat_delta(sc, 6547 I40E_GLV_GOTCH(sc->sc_vsi_stat_counter_idx), 6548 I40E_GLV_GOTCL(sc->sc_vsi_stat_counter_idx), 6549 &isc->isc_vsi_tx_bytes_offset, isc->isc_has_offset); 6550 atomic_add_64(&isc->isc_vsi_tx_bytes.ev_count, delta); 6551 6552 delta = ixl_stat_delta(sc, 6553 I40E_GLV_UPTCH(sc->sc_vsi_stat_counter_idx), 6554 I40E_GLV_UPTCL(sc->sc_vsi_stat_counter_idx), 6555 &isc->isc_vsi_tx_unicast_offset, isc->isc_has_offset); 6556 atomic_add_64(&isc->isc_vsi_tx_unicast.ev_count, delta); 6557 6558 delta = ixl_stat_delta(sc, 6559 I40E_GLV_MPTCH(sc->sc_vsi_stat_counter_idx), 6560 I40E_GLV_MPTCL(sc->sc_vsi_stat_counter_idx), 6561 &isc->isc_vsi_tx_multicast_offset, isc->isc_has_offset); 6562 atomic_add_64(&isc->isc_vsi_tx_multicast.ev_count, delta); 6563 6564 delta = ixl_stat_delta(sc, 6565 I40E_GLV_BPTCH(sc->sc_vsi_stat_counter_idx), 6566 I40E_GLV_BPTCL(sc->sc_vsi_stat_counter_idx), 6567 &isc->isc_vsi_tx_broadcast_offset, isc->isc_has_offset); 6568 atomic_add_64(&isc->isc_vsi_tx_broadcast.ev_count, delta); 6569 } 6570 6571 static int 6572 ixl_setup_sysctls(struct ixl_softc *sc) 6573 { 6574 const char *devname; 6575 struct sysctllog **log; 6576 const struct sysctlnode *rnode, *rxnode, *txnode; 6577 int error; 6578 6579 log = &sc->sc_sysctllog; 6580 devname = device_xname(sc->sc_dev); 6581 6582 error = sysctl_createv(log, 0, NULL, &rnode, 6583 0, CTLTYPE_NODE, devname, 6584 SYSCTL_DESCR("ixl information and settings"), 6585 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 6586 if (error) 6587 goto out; 6588 6589 error = sysctl_createv(log, 0, &rnode, NULL, 6590 CTLFLAG_READWRITE, CTLTYPE_BOOL, "txrx_workqueue", 6591 SYSCTL_DESCR("Use workqueue for packet processing"), 6592 NULL, 0, &sc->sc_txrx_workqueue, 0, CTL_CREATE, CTL_EOL); 6593 if (error) 6594 goto out; 6595 6596 error = sysctl_createv(log, 0, &rnode, NULL, 6597 CTLFLAG_READONLY, CTLTYPE_INT, "stats_interval", 6598 SYSCTL_DESCR("Statistics collection interval in milliseconds"), 6599 NULL, 0, &sc->sc_stats_intval, 0, CTL_CREATE, CTL_EOL); 6600 6601 error = sysctl_createv(log, 0, &rnode, &rxnode, 6602 0, CTLTYPE_NODE, "rx", 6603 SYSCTL_DESCR("ixl information and settings for Rx"), 6604 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 6605 if (error) 6606 goto out; 6607 6608 error = sysctl_createv(log, 0, &rxnode, NULL, 6609 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 6610 SYSCTL_DESCR("max number of Rx packets" 6611 " to process for interrupt processing"), 6612 NULL, 0, &sc->sc_rx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 6613 if (error) 6614 goto out; 6615 6616 error = sysctl_createv(log, 0, &rxnode, NULL, 6617 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 6618 SYSCTL_DESCR("max number of Rx packets" 6619 " to process for deferred processing"), 6620 NULL, 0, &sc->sc_rx_process_limit, 0, CTL_CREATE, CTL_EOL); 6621 if (error) 6622 goto out; 6623 6624 error = sysctl_createv(log, 0, &rnode, &txnode, 6625 0, CTLTYPE_NODE, "tx", 6626 SYSCTL_DESCR("ixl information and settings for Tx"), 6627 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 6628 if (error) 6629 goto out; 6630 6631 error = sysctl_createv(log, 0, &txnode, NULL, 6632 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 6633 SYSCTL_DESCR("max number of Tx packets" 6634 " to process for interrupt processing"), 6635 NULL, 0, &sc->sc_tx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 6636 if (error) 6637 goto out; 6638 6639 error = sysctl_createv(log, 0, &txnode, NULL, 6640 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 6641 SYSCTL_DESCR("max number of Tx packets" 6642 " to process for deferred processing"), 6643 NULL, 0, &sc->sc_tx_process_limit, 0, CTL_CREATE, CTL_EOL); 6644 if (error) 6645 goto out; 6646 6647 out: 6648 if (error) { 6649 aprint_error_dev(sc->sc_dev, 6650 "unable to create sysctl node\n"); 6651 sysctl_teardown(log); 6652 } 6653 6654 return error; 6655 } 6656 6657 static void 6658 ixl_teardown_sysctls(struct ixl_softc *sc) 6659 { 6660 6661 sysctl_teardown(&sc->sc_sysctllog); 6662 } 6663 6664 static struct workqueue * 6665 ixl_workq_create(const char *name, pri_t prio, int ipl, int flags) 6666 { 6667 struct workqueue *wq; 6668 int error; 6669 6670 error = workqueue_create(&wq, name, ixl_workq_work, NULL, 6671 prio, ipl, flags); 6672 6673 if (error) 6674 return NULL; 6675 6676 return wq; 6677 } 6678 6679 static void 6680 ixl_workq_destroy(struct workqueue *wq) 6681 { 6682 6683 workqueue_destroy(wq); 6684 } 6685 6686 static void 6687 ixl_work_set(struct ixl_work *work, void (*func)(void *), void *arg) 6688 { 6689 6690 memset(work, 0, sizeof(*work)); 6691 work->ixw_func = func; 6692 work->ixw_arg = arg; 6693 } 6694 6695 static void 6696 ixl_work_add(struct workqueue *wq, struct ixl_work *work) 6697 { 6698 if (atomic_cas_uint(&work->ixw_added, 0, 1) != 0) 6699 return; 6700 6701 kpreempt_disable(); 6702 workqueue_enqueue(wq, &work->ixw_cookie, NULL); 6703 kpreempt_enable(); 6704 } 6705 6706 static void 6707 ixl_work_wait(struct workqueue *wq, struct ixl_work *work) 6708 { 6709 6710 workqueue_wait(wq, &work->ixw_cookie); 6711 } 6712 6713 static void 6714 ixl_workq_work(struct work *wk, void *context) 6715 { 6716 struct ixl_work *work; 6717 6718 work = container_of(wk, struct ixl_work, ixw_cookie); 6719 6720 atomic_swap_uint(&work->ixw_added, 0); 6721 work->ixw_func(work->ixw_arg); 6722 } 6723 6724 static int 6725 ixl_rx_ctl_read(struct ixl_softc *sc, uint32_t reg, uint32_t *rv) 6726 { 6727 struct ixl_aq_desc iaq; 6728 6729 memset(&iaq, 0, sizeof(iaq)); 6730 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_READ); 6731 iaq.iaq_param[1] = htole32(reg); 6732 6733 if (ixl_atq_poll(sc, &iaq, 250) != 0) 6734 return ETIMEDOUT; 6735 6736 switch (htole16(iaq.iaq_retval)) { 6737 case IXL_AQ_RC_OK: 6738 /* success */ 6739 break; 6740 case IXL_AQ_RC_EACCES: 6741 return EPERM; 6742 case IXL_AQ_RC_EAGAIN: 6743 return EAGAIN; 6744 default: 6745 return EIO; 6746 } 6747 6748 *rv = htole32(iaq.iaq_param[3]); 6749 return 0; 6750 } 6751 6752 static uint32_t 6753 ixl_rd_rx_csr(struct ixl_softc *sc, uint32_t reg) 6754 { 6755 uint32_t val; 6756 int rv, retry, retry_limit; 6757 6758 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL)) { 6759 retry_limit = 5; 6760 } else { 6761 retry_limit = 0; 6762 } 6763 6764 for (retry = 0; retry < retry_limit; retry++) { 6765 rv = ixl_rx_ctl_read(sc, reg, &val); 6766 if (rv == 0) 6767 return val; 6768 else if (rv == EAGAIN) 6769 delaymsec(1); 6770 else 6771 break; 6772 } 6773 6774 val = ixl_rd(sc, reg); 6775 6776 return val; 6777 } 6778 6779 static int 6780 ixl_rx_ctl_write(struct ixl_softc *sc, uint32_t reg, uint32_t value) 6781 { 6782 struct ixl_aq_desc iaq; 6783 6784 memset(&iaq, 0, sizeof(iaq)); 6785 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_WRITE); 6786 iaq.iaq_param[1] = htole32(reg); 6787 iaq.iaq_param[3] = htole32(value); 6788 6789 if (ixl_atq_poll(sc, &iaq, 250) != 0) 6790 return ETIMEDOUT; 6791 6792 switch (htole16(iaq.iaq_retval)) { 6793 case IXL_AQ_RC_OK: 6794 /* success */ 6795 break; 6796 case IXL_AQ_RC_EACCES: 6797 return EPERM; 6798 case IXL_AQ_RC_EAGAIN: 6799 return EAGAIN; 6800 default: 6801 return EIO; 6802 } 6803 6804 return 0; 6805 } 6806 6807 static void 6808 ixl_wr_rx_csr(struct ixl_softc *sc, uint32_t reg, uint32_t value) 6809 { 6810 int rv, retry, retry_limit; 6811 6812 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL)) { 6813 retry_limit = 5; 6814 } else { 6815 retry_limit = 0; 6816 } 6817 6818 for (retry = 0; retry < retry_limit; retry++) { 6819 rv = ixl_rx_ctl_write(sc, reg, value); 6820 if (rv == 0) 6821 return; 6822 else if (rv == EAGAIN) 6823 delaymsec(1); 6824 else 6825 break; 6826 } 6827 6828 ixl_wr(sc, reg, value); 6829 } 6830 6831 static int 6832 ixl_nvm_lock(struct ixl_softc *sc, char rw) 6833 { 6834 struct ixl_aq_desc iaq; 6835 struct ixl_aq_req_resource_param *param; 6836 int rv; 6837 6838 if (!ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK)) 6839 return 0; 6840 6841 memset(&iaq, 0, sizeof(iaq)); 6842 iaq.iaq_opcode = htole16(IXL_AQ_OP_REQUEST_RESOURCE); 6843 6844 param = (struct ixl_aq_req_resource_param *)&iaq.iaq_param; 6845 param->resource_id = htole16(IXL_AQ_RESOURCE_ID_NVM); 6846 if (rw == 'R') { 6847 param->access_type = htole16(IXL_AQ_RESOURCE_ACCES_READ); 6848 } else { 6849 param->access_type = htole16(IXL_AQ_RESOURCE_ACCES_WRITE); 6850 } 6851 6852 rv = ixl_atq_poll(sc, &iaq, 250); 6853 6854 if (rv != 0) 6855 return ETIMEDOUT; 6856 6857 switch (le16toh(iaq.iaq_retval)) { 6858 case IXL_AQ_RC_OK: 6859 break; 6860 case IXL_AQ_RC_EACCES: 6861 return EACCES; 6862 case IXL_AQ_RC_EBUSY: 6863 return EBUSY; 6864 case IXL_AQ_RC_EPERM: 6865 return EPERM; 6866 } 6867 6868 return 0; 6869 } 6870 6871 static int 6872 ixl_nvm_unlock(struct ixl_softc *sc) 6873 { 6874 struct ixl_aq_desc iaq; 6875 struct ixl_aq_rel_resource_param *param; 6876 int rv; 6877 6878 if (!ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK)) 6879 return 0; 6880 6881 memset(&iaq, 0, sizeof(iaq)); 6882 iaq.iaq_opcode = htole16(IXL_AQ_OP_RELEASE_RESOURCE); 6883 6884 param = (struct ixl_aq_rel_resource_param *)&iaq.iaq_param; 6885 param->resource_id = htole16(IXL_AQ_RESOURCE_ID_NVM); 6886 6887 rv = ixl_atq_poll(sc, &iaq, 250); 6888 6889 if (rv != 0) 6890 return ETIMEDOUT; 6891 6892 switch (le16toh(iaq.iaq_retval)) { 6893 case IXL_AQ_RC_OK: 6894 break; 6895 default: 6896 return EIO; 6897 } 6898 return 0; 6899 } 6900 6901 static int 6902 ixl_srdone_poll(struct ixl_softc *sc) 6903 { 6904 int wait_count; 6905 uint32_t reg; 6906 6907 for (wait_count = 0; wait_count < IXL_SRRD_SRCTL_ATTEMPTS; 6908 wait_count++) { 6909 reg = ixl_rd(sc, I40E_GLNVM_SRCTL); 6910 if (ISSET(reg, I40E_GLNVM_SRCTL_DONE_MASK)) 6911 break; 6912 6913 delaymsec(5); 6914 } 6915 6916 if (wait_count == IXL_SRRD_SRCTL_ATTEMPTS) 6917 return -1; 6918 6919 return 0; 6920 } 6921 6922 static int 6923 ixl_nvm_read_srctl(struct ixl_softc *sc, uint16_t offset, uint16_t *data) 6924 { 6925 uint32_t reg; 6926 6927 if (ixl_srdone_poll(sc) != 0) 6928 return ETIMEDOUT; 6929 6930 reg = ((uint32_t)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 6931 __BIT(I40E_GLNVM_SRCTL_START_SHIFT); 6932 ixl_wr(sc, I40E_GLNVM_SRCTL, reg); 6933 6934 if (ixl_srdone_poll(sc) != 0) { 6935 aprint_debug("NVM read error: couldn't access " 6936 "Shadow RAM address: 0x%x\n", offset); 6937 return ETIMEDOUT; 6938 } 6939 6940 reg = ixl_rd(sc, I40E_GLNVM_SRDATA); 6941 *data = (uint16_t)__SHIFTOUT(reg, I40E_GLNVM_SRDATA_RDDATA_MASK); 6942 6943 return 0; 6944 } 6945 6946 static int 6947 ixl_nvm_read_aq(struct ixl_softc *sc, uint16_t offset_word, 6948 void *data, size_t len) 6949 { 6950 struct ixl_dmamem *idm; 6951 struct ixl_aq_desc iaq; 6952 struct ixl_aq_nvm_param *param; 6953 uint32_t offset_bytes; 6954 int rv; 6955 6956 idm = &sc->sc_aqbuf; 6957 if (len > IXL_DMA_LEN(idm)) 6958 return ENOMEM; 6959 6960 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 6961 memset(&iaq, 0, sizeof(iaq)); 6962 iaq.iaq_opcode = htole16(IXL_AQ_OP_NVM_READ); 6963 iaq.iaq_flags = htole16(IXL_AQ_BUF | 6964 ((len > I40E_AQ_LARGE_BUF) ? IXL_AQ_LB : 0)); 6965 iaq.iaq_datalen = htole16(len); 6966 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 6967 6968 param = (struct ixl_aq_nvm_param *)iaq.iaq_param; 6969 param->command_flags = IXL_AQ_NVM_LAST_CMD; 6970 param->module_pointer = 0; 6971 param->length = htole16(len); 6972 offset_bytes = (uint32_t)offset_word * 2; 6973 offset_bytes &= 0x00FFFFFF; 6974 param->offset = htole32(offset_bytes); 6975 6976 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 6977 BUS_DMASYNC_PREREAD); 6978 6979 rv = ixl_atq_poll(sc, &iaq, 250); 6980 6981 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 6982 BUS_DMASYNC_POSTREAD); 6983 6984 if (rv != 0) { 6985 return ETIMEDOUT; 6986 } 6987 6988 switch (le16toh(iaq.iaq_retval)) { 6989 case IXL_AQ_RC_OK: 6990 break; 6991 case IXL_AQ_RC_EPERM: 6992 return EPERM; 6993 case IXL_AQ_RC_EINVAL: 6994 return EINVAL; 6995 case IXL_AQ_RC_EBUSY: 6996 return EBUSY; 6997 case IXL_AQ_RC_EIO: 6998 default: 6999 return EIO; 7000 } 7001 7002 memcpy(data, IXL_DMA_KVA(idm), len); 7003 7004 return 0; 7005 } 7006 7007 static int 7008 ixl_rd16_nvm(struct ixl_softc *sc, uint16_t offset, uint16_t *data) 7009 { 7010 int error; 7011 uint16_t buf; 7012 7013 error = ixl_nvm_lock(sc, 'R'); 7014 if (error) 7015 return error; 7016 7017 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMREAD)) { 7018 error = ixl_nvm_read_aq(sc, offset, 7019 &buf, sizeof(buf)); 7020 if (error == 0) 7021 *data = le16toh(buf); 7022 } else { 7023 error = ixl_nvm_read_srctl(sc, offset, &buf); 7024 if (error == 0) 7025 *data = buf; 7026 } 7027 7028 ixl_nvm_unlock(sc); 7029 7030 return error; 7031 } 7032 7033 MODULE(MODULE_CLASS_DRIVER, if_ixl, "pci"); 7034 7035 #ifdef _MODULE 7036 #include "ioconf.c" 7037 #endif 7038 7039 #ifdef _MODULE 7040 static void 7041 ixl_parse_modprop(prop_dictionary_t dict) 7042 { 7043 prop_object_t obj; 7044 int64_t val; 7045 uint64_t uval; 7046 7047 if (dict == NULL) 7048 return; 7049 7050 obj = prop_dictionary_get(dict, "nomsix"); 7051 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_BOOL) { 7052 ixl_param_nomsix = prop_bool_true((prop_bool_t)obj); 7053 } 7054 7055 obj = prop_dictionary_get(dict, "stats_interval"); 7056 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7057 val = prop_number_integer_value((prop_number_t)obj); 7058 7059 /* the range has no reason */ 7060 if (100 < val && val < 180000) { 7061 ixl_param_stats_interval = val; 7062 } 7063 } 7064 7065 obj = prop_dictionary_get(dict, "nqps_limit"); 7066 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7067 val = prop_number_integer_value((prop_number_t)obj); 7068 7069 if (val <= INT32_MAX) 7070 ixl_param_nqps_limit = val; 7071 } 7072 7073 obj = prop_dictionary_get(dict, "rx_ndescs"); 7074 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7075 uval = prop_number_unsigned_integer_value((prop_number_t)obj); 7076 7077 if (uval > 8) 7078 ixl_param_rx_ndescs = uval; 7079 } 7080 7081 obj = prop_dictionary_get(dict, "tx_ndescs"); 7082 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7083 uval = prop_number_unsigned_integer_value((prop_number_t)obj); 7084 7085 if (uval > IXL_TX_PKT_DESCS) 7086 ixl_param_tx_ndescs = uval; 7087 } 7088 7089 } 7090 #endif 7091 7092 static int 7093 if_ixl_modcmd(modcmd_t cmd, void *opaque) 7094 { 7095 int error = 0; 7096 7097 #ifdef _MODULE 7098 switch (cmd) { 7099 case MODULE_CMD_INIT: 7100 ixl_parse_modprop((prop_dictionary_t)opaque); 7101 error = config_init_component(cfdriver_ioconf_if_ixl, 7102 cfattach_ioconf_if_ixl, cfdata_ioconf_if_ixl); 7103 break; 7104 case MODULE_CMD_FINI: 7105 error = config_fini_component(cfdriver_ioconf_if_ixl, 7106 cfattach_ioconf_if_ixl, cfdata_ioconf_if_ixl); 7107 break; 7108 default: 7109 error = ENOTTY; 7110 break; 7111 } 7112 #endif 7113 7114 return error; 7115 } 7116
Indexes created Wed Sep 24 05:09:52 GMT 2025