if_ixl.c revision 1.80
1 /* $NetBSD: if_ixl.c,v 1.80 2022/03/31 06:20:14 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg (at) openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 /* 51 * Copyright (c) 2019 Internet Initiative Japan, Inc. 52 * All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 64 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 65 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 66 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 67 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 68 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 69 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 70 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 71 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 72 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 73 * POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: if_ixl.c,v 1.80 2022/03/31 06:20:14 yamaguchi Exp $"); 78 79 #ifdef _KERNEL_OPT 80 #include "opt_net_mpsafe.h" 81 #include "opt_if_ixl.h" 82 #endif 83 84 #include <sys/param.h> 85 #include <sys/types.h> 86 87 #include <sys/bitops.h> 88 #include <sys/cpu.h> 89 #include <sys/device.h> 90 #include <sys/evcnt.h> 91 #include <sys/interrupt.h> 92 #include <sys/kmem.h> 93 #include <sys/module.h> 94 #include <sys/mutex.h> 95 #include <sys/pcq.h> 96 #include <sys/syslog.h> 97 #include <sys/workqueue.h> 98 99 #include <sys/bus.h> 100 101 #include <net/bpf.h> 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_ether.h> 106 #include <net/rss_config.h> 107 108 #include <netinet/tcp.h> /* for struct tcphdr */ 109 #include <netinet/udp.h> /* for struct udphdr */ 110 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/pci/if_ixlreg.h> 115 #include <dev/pci/if_ixlvar.h> 116 117 #include <prop/proplib.h> 118 119 struct ixl_softc; /* defined */ 120 121 #define I40E_PF_RESET_WAIT_COUNT 200 122 #define I40E_AQ_LARGE_BUF 512 123 124 /* bitfields for Tx queue mapping in QTX_CTL */ 125 #define I40E_QTX_CTL_VF_QUEUE 0x0 126 #define I40E_QTX_CTL_VM_QUEUE 0x1 127 #define I40E_QTX_CTL_PF_QUEUE 0x2 128 129 #define I40E_QUEUE_TYPE_EOL 0x7ff 130 #define I40E_INTR_NOTX_QUEUE 0 131 132 #define I40E_QUEUE_TYPE_RX 0x0 133 #define I40E_QUEUE_TYPE_TX 0x1 134 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 135 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 136 137 #define I40E_ITR_INDEX_RX 0x0 138 #define I40E_ITR_INDEX_TX 0x1 139 #define I40E_ITR_INDEX_OTHER 0x2 140 #define I40E_ITR_INDEX_NONE 0x3 141 #define IXL_ITR_RX 0x7a /* 4K intrs/sec */ 142 #define IXL_ITR_TX 0x7a /* 4K intrs/sec */ 143 144 #define I40E_INTR_NOTX_QUEUE 0 145 #define I40E_INTR_NOTX_INTR 0 146 #define I40E_INTR_NOTX_RX_QUEUE 0 147 #define I40E_INTR_NOTX_TX_QUEUE 1 148 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 149 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 150 151 #define I40E_HASH_LUT_SIZE_128 0 152 153 #define IXL_ICR0_CRIT_ERR_MASK \ 154 (I40E_PFINT_ICR0_PCI_EXCEPTION_MASK | \ 155 I40E_PFINT_ICR0_ECC_ERR_MASK | \ 156 I40E_PFINT_ICR0_PE_CRITERR_MASK) 157 158 #define IXL_QUEUE_MAX_XL710 64 159 #define IXL_QUEUE_MAX_X722 128 160 161 #define IXL_TX_PKT_DESCS 8 162 #define IXL_TX_PKT_MAXSIZE (MCLBYTES * IXL_TX_PKT_DESCS) 163 #define IXL_TX_QUEUE_ALIGN 128 164 #define IXL_RX_QUEUE_ALIGN 128 165 166 #define IXL_MCLBYTES (MCLBYTES - ETHER_ALIGN) 167 #define IXL_MTU_ETHERLEN ETHER_HDR_LEN \ 168 + ETHER_CRC_LEN 169 #if 0 170 #define IXL_MAX_MTU (9728 - IXL_MTU_ETHERLEN) 171 #else 172 /* (dbuff * 5) - ETHER_HDR_LEN - ETHER_CRC_LEN */ 173 #define IXL_MAX_MTU (9600 - IXL_MTU_ETHERLEN) 174 #endif 175 #define IXL_MIN_MTU (ETHER_MIN_LEN - ETHER_CRC_LEN) 176 177 #define IXL_PCIREG PCI_MAPREG_START 178 179 #define IXL_ITR0 0x0 180 #define IXL_ITR1 0x1 181 #define IXL_ITR2 0x2 182 #define IXL_NOITR 0x3 183 184 #define IXL_AQ_NUM 256 185 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 186 #define IXL_AQ_ALIGN 64 /* lol */ 187 #define IXL_AQ_BUFLEN 4096 188 189 #define IXL_HMC_ROUNDUP 512 190 #define IXL_HMC_PGSIZE 4096 191 #define IXL_HMC_DVASZ sizeof(uint64_t) 192 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 193 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 194 #define IXL_HMC_PDVALID 1ULL 195 196 #define IXL_ATQ_EXEC_TIMEOUT (10 * hz) 197 198 #define IXL_SRRD_SRCTL_ATTEMPTS 100000 199 200 struct ixl_aq_regs { 201 bus_size_t atq_tail; 202 bus_size_t atq_head; 203 bus_size_t atq_len; 204 bus_size_t atq_bal; 205 bus_size_t atq_bah; 206 207 bus_size_t arq_tail; 208 bus_size_t arq_head; 209 bus_size_t arq_len; 210 bus_size_t arq_bal; 211 bus_size_t arq_bah; 212 213 uint32_t atq_len_enable; 214 uint32_t atq_tail_mask; 215 uint32_t atq_head_mask; 216 217 uint32_t arq_len_enable; 218 uint32_t arq_tail_mask; 219 uint32_t arq_head_mask; 220 }; 221 222 struct ixl_phy_type { 223 uint64_t phy_type; 224 uint64_t ifm_type; 225 }; 226 227 struct ixl_speed_type { 228 uint8_t dev_speed; 229 uint64_t net_speed; 230 }; 231 232 struct ixl_hmc_entry { 233 uint64_t hmc_base; 234 uint32_t hmc_count; 235 uint64_t hmc_size; 236 }; 237 238 enum ixl_hmc_types { 239 IXL_HMC_LAN_TX = 0, 240 IXL_HMC_LAN_RX, 241 IXL_HMC_FCOE_CTX, 242 IXL_HMC_FCOE_FILTER, 243 IXL_HMC_COUNT 244 }; 245 246 struct ixl_hmc_pack { 247 uint16_t offset; 248 uint16_t width; 249 uint16_t lsb; 250 }; 251 252 /* 253 * these hmc objects have weird sizes and alignments, so these are abstract 254 * representations of them that are nice for c to populate. 255 * 256 * the packing code relies on little-endian values being stored in the fields, 257 * no high bits in the fields being set, and the fields must be packed in the 258 * same order as they are in the ctx structure. 259 */ 260 261 struct ixl_hmc_rxq { 262 uint16_t head; 263 uint8_t cpuid; 264 uint64_t base; 265 #define IXL_HMC_RXQ_BASE_UNIT 128 266 uint16_t qlen; 267 uint16_t dbuff; 268 #define IXL_HMC_RXQ_DBUFF_UNIT 128 269 uint8_t hbuff; 270 #define IXL_HMC_RXQ_HBUFF_UNIT 64 271 uint8_t dtype; 272 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 273 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 274 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 275 uint8_t dsize; 276 #define IXL_HMC_RXQ_DSIZE_16 0 277 #define IXL_HMC_RXQ_DSIZE_32 1 278 uint8_t crcstrip; 279 uint8_t fc_ena; 280 uint8_t l2sel; 281 uint8_t hsplit_0; 282 uint8_t hsplit_1; 283 uint8_t showiv; 284 uint16_t rxmax; 285 uint8_t tphrdesc_ena; 286 uint8_t tphwdesc_ena; 287 uint8_t tphdata_ena; 288 uint8_t tphhead_ena; 289 uint8_t lrxqthresh; 290 uint8_t prefena; 291 }; 292 293 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 294 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 295 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 296 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 297 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 298 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 299 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 300 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 301 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 302 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 303 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 304 { offsetof(struct ixl_hmc_rxq, l2sel), 1, 119 }, 305 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 306 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 307 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 308 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 309 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 310 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 311 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 312 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 313 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 314 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 315 }; 316 317 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 318 319 struct ixl_hmc_txq { 320 uint16_t head; 321 uint8_t new_context; 322 uint64_t base; 323 #define IXL_HMC_TXQ_BASE_UNIT 128 324 uint8_t fc_ena; 325 uint8_t timesync_ena; 326 uint8_t fd_ena; 327 uint8_t alt_vlan_ena; 328 uint8_t cpuid; 329 uint16_t thead_wb; 330 uint8_t head_wb_ena; 331 #define IXL_HMC_TXQ_DESC_WB 0 332 #define IXL_HMC_TXQ_HEAD_WB 1 333 uint16_t qlen; 334 uint8_t tphrdesc_ena; 335 uint8_t tphrpacket_ena; 336 uint8_t tphwdesc_ena; 337 uint64_t head_wb_addr; 338 uint32_t crc; 339 uint16_t rdylist; 340 uint8_t rdylist_act; 341 }; 342 343 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 344 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 345 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 346 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 347 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 348 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 349 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 350 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 351 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 352 /* line 1 */ 353 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 354 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 355 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 356 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 357 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 358 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 359 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 360 /* line 7 */ 361 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 362 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 363 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 364 }; 365 366 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 367 368 struct ixl_work { 369 struct work ixw_cookie; 370 void (*ixw_func)(void *); 371 void *ixw_arg; 372 unsigned int ixw_added; 373 }; 374 #define IXL_WORKQUEUE_PRI PRI_SOFTNET 375 376 struct ixl_tx_map { 377 struct mbuf *txm_m; 378 bus_dmamap_t txm_map; 379 unsigned int txm_eop; 380 }; 381 382 struct ixl_tx_ring { 383 kmutex_t txr_lock; 384 struct ixl_softc *txr_sc; 385 386 unsigned int txr_prod; 387 unsigned int txr_cons; 388 389 struct ixl_tx_map *txr_maps; 390 struct ixl_dmamem txr_mem; 391 392 bus_size_t txr_tail; 393 unsigned int txr_qid; 394 pcq_t *txr_intrq; 395 void *txr_si; 396 397 struct evcnt txr_defragged; 398 struct evcnt txr_defrag_failed; 399 struct evcnt txr_pcqdrop; 400 struct evcnt txr_transmitdef; 401 struct evcnt txr_intr; 402 struct evcnt txr_defer; 403 }; 404 405 struct ixl_rx_map { 406 struct mbuf *rxm_m; 407 bus_dmamap_t rxm_map; 408 }; 409 410 struct ixl_rx_ring { 411 kmutex_t rxr_lock; 412 413 unsigned int rxr_prod; 414 unsigned int rxr_cons; 415 416 struct ixl_rx_map *rxr_maps; 417 struct ixl_dmamem rxr_mem; 418 419 struct mbuf *rxr_m_head; 420 struct mbuf **rxr_m_tail; 421 422 bus_size_t rxr_tail; 423 unsigned int rxr_qid; 424 425 struct evcnt rxr_mgethdr_failed; 426 struct evcnt rxr_mgetcl_failed; 427 struct evcnt rxr_mbuf_load_failed; 428 struct evcnt rxr_intr; 429 struct evcnt rxr_defer; 430 }; 431 432 struct ixl_queue_pair { 433 struct ixl_softc *qp_sc; 434 struct ixl_tx_ring *qp_txr; 435 struct ixl_rx_ring *qp_rxr; 436 437 char qp_name[16]; 438 439 void *qp_si; 440 struct work qp_work; 441 bool qp_workqueue; 442 }; 443 444 struct ixl_atq { 445 struct ixl_aq_desc iatq_desc; 446 void (*iatq_fn)(struct ixl_softc *, 447 const struct ixl_aq_desc *); 448 }; 449 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 450 451 struct ixl_product { 452 unsigned int vendor_id; 453 unsigned int product_id; 454 }; 455 456 struct ixl_stats_counters { 457 bool isc_has_offset; 458 struct evcnt isc_crc_errors; 459 uint64_t isc_crc_errors_offset; 460 struct evcnt isc_illegal_bytes; 461 uint64_t isc_illegal_bytes_offset; 462 struct evcnt isc_rx_bytes; 463 uint64_t isc_rx_bytes_offset; 464 struct evcnt isc_rx_discards; 465 uint64_t isc_rx_discards_offset; 466 struct evcnt isc_rx_unicast; 467 uint64_t isc_rx_unicast_offset; 468 struct evcnt isc_rx_multicast; 469 uint64_t isc_rx_multicast_offset; 470 struct evcnt isc_rx_broadcast; 471 uint64_t isc_rx_broadcast_offset; 472 struct evcnt isc_rx_size_64; 473 uint64_t isc_rx_size_64_offset; 474 struct evcnt isc_rx_size_127; 475 uint64_t isc_rx_size_127_offset; 476 struct evcnt isc_rx_size_255; 477 uint64_t isc_rx_size_255_offset; 478 struct evcnt isc_rx_size_511; 479 uint64_t isc_rx_size_511_offset; 480 struct evcnt isc_rx_size_1023; 481 uint64_t isc_rx_size_1023_offset; 482 struct evcnt isc_rx_size_1522; 483 uint64_t isc_rx_size_1522_offset; 484 struct evcnt isc_rx_size_big; 485 uint64_t isc_rx_size_big_offset; 486 struct evcnt isc_rx_undersize; 487 uint64_t isc_rx_undersize_offset; 488 struct evcnt isc_rx_oversize; 489 uint64_t isc_rx_oversize_offset; 490 struct evcnt isc_rx_fragments; 491 uint64_t isc_rx_fragments_offset; 492 struct evcnt isc_rx_jabber; 493 uint64_t isc_rx_jabber_offset; 494 struct evcnt isc_tx_bytes; 495 uint64_t isc_tx_bytes_offset; 496 struct evcnt isc_tx_dropped_link_down; 497 uint64_t isc_tx_dropped_link_down_offset; 498 struct evcnt isc_tx_unicast; 499 uint64_t isc_tx_unicast_offset; 500 struct evcnt isc_tx_multicast; 501 uint64_t isc_tx_multicast_offset; 502 struct evcnt isc_tx_broadcast; 503 uint64_t isc_tx_broadcast_offset; 504 struct evcnt isc_tx_size_64; 505 uint64_t isc_tx_size_64_offset; 506 struct evcnt isc_tx_size_127; 507 uint64_t isc_tx_size_127_offset; 508 struct evcnt isc_tx_size_255; 509 uint64_t isc_tx_size_255_offset; 510 struct evcnt isc_tx_size_511; 511 uint64_t isc_tx_size_511_offset; 512 struct evcnt isc_tx_size_1023; 513 uint64_t isc_tx_size_1023_offset; 514 struct evcnt isc_tx_size_1522; 515 uint64_t isc_tx_size_1522_offset; 516 struct evcnt isc_tx_size_big; 517 uint64_t isc_tx_size_big_offset; 518 struct evcnt isc_mac_local_faults; 519 uint64_t isc_mac_local_faults_offset; 520 struct evcnt isc_mac_remote_faults; 521 uint64_t isc_mac_remote_faults_offset; 522 struct evcnt isc_link_xon_rx; 523 uint64_t isc_link_xon_rx_offset; 524 struct evcnt isc_link_xon_tx; 525 uint64_t isc_link_xon_tx_offset; 526 struct evcnt isc_link_xoff_rx; 527 uint64_t isc_link_xoff_rx_offset; 528 struct evcnt isc_link_xoff_tx; 529 uint64_t isc_link_xoff_tx_offset; 530 struct evcnt isc_vsi_rx_discards; 531 uint64_t isc_vsi_rx_discards_offset; 532 struct evcnt isc_vsi_rx_bytes; 533 uint64_t isc_vsi_rx_bytes_offset; 534 struct evcnt isc_vsi_rx_unicast; 535 uint64_t isc_vsi_rx_unicast_offset; 536 struct evcnt isc_vsi_rx_multicast; 537 uint64_t isc_vsi_rx_multicast_offset; 538 struct evcnt isc_vsi_rx_broadcast; 539 uint64_t isc_vsi_rx_broadcast_offset; 540 struct evcnt isc_vsi_tx_errors; 541 uint64_t isc_vsi_tx_errors_offset; 542 struct evcnt isc_vsi_tx_bytes; 543 uint64_t isc_vsi_tx_bytes_offset; 544 struct evcnt isc_vsi_tx_unicast; 545 uint64_t isc_vsi_tx_unicast_offset; 546 struct evcnt isc_vsi_tx_multicast; 547 uint64_t isc_vsi_tx_multicast_offset; 548 struct evcnt isc_vsi_tx_broadcast; 549 uint64_t isc_vsi_tx_broadcast_offset; 550 }; 551 552 /* 553 * Locking notes: 554 * + a field in ixl_tx_ring is protected by txr_lock (a spin mutex), and 555 * a field in ixl_rx_ring is protected by rxr_lock (a spin mutex). 556 * - more than one lock of them cannot be held at once. 557 * + a field named sc_atq_* in ixl_softc is protected by sc_atq_lock 558 * (a spin mutex). 559 * - the lock cannot held with txr_lock or rxr_lock. 560 * + a field named sc_arq_* is not protected by any lock. 561 * - operations for sc_arq_* is done in one context related to 562 * sc_arq_task. 563 * + other fields in ixl_softc is protected by sc_cfg_lock 564 * (an adaptive mutex) 565 * - It must be held before another lock is held, and It can be 566 * released after the other lock is released. 567 * */ 568 569 struct ixl_softc { 570 device_t sc_dev; 571 struct ethercom sc_ec; 572 bool sc_attached; 573 bool sc_dead; 574 uint32_t sc_port; 575 struct sysctllog *sc_sysctllog; 576 struct workqueue *sc_workq; 577 struct workqueue *sc_workq_txrx; 578 int sc_stats_intval; 579 callout_t sc_stats_callout; 580 struct ixl_work sc_stats_task; 581 struct ixl_stats_counters 582 sc_stats_counters; 583 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 584 struct ifmedia sc_media; 585 uint64_t sc_media_status; 586 uint64_t sc_media_active; 587 uint64_t sc_phy_types; 588 uint8_t sc_phy_abilities; 589 uint8_t sc_phy_linkspeed; 590 uint8_t sc_phy_fec_cfg; 591 uint16_t sc_eee_cap; 592 uint32_t sc_eeer_val; 593 uint8_t sc_d3_lpan; 594 kmutex_t sc_cfg_lock; 595 enum i40e_mac_type sc_mac_type; 596 uint32_t sc_rss_table_size; 597 uint32_t sc_rss_table_entry_width; 598 bool sc_txrx_workqueue; 599 u_int sc_tx_process_limit; 600 u_int sc_rx_process_limit; 601 u_int sc_tx_intr_process_limit; 602 u_int sc_rx_intr_process_limit; 603 604 int sc_cur_ec_capenable; 605 606 struct pci_attach_args sc_pa; 607 pci_intr_handle_t *sc_ihp; 608 void **sc_ihs; 609 unsigned int sc_nintrs; 610 611 bus_dma_tag_t sc_dmat; 612 bus_space_tag_t sc_memt; 613 bus_space_handle_t sc_memh; 614 bus_size_t sc_mems; 615 616 uint8_t sc_pf_id; 617 uint16_t sc_uplink_seid; /* le */ 618 uint16_t sc_downlink_seid; /* le */ 619 uint16_t sc_vsi_number; 620 uint16_t sc_vsi_stat_counter_idx; 621 uint16_t sc_seid; 622 unsigned int sc_base_queue; 623 624 pci_intr_type_t sc_intrtype; 625 unsigned int sc_msix_vector_queue; 626 627 struct ixl_dmamem sc_scratch; 628 struct ixl_dmamem sc_aqbuf; 629 630 const struct ixl_aq_regs * 631 sc_aq_regs; 632 uint32_t sc_aq_flags; 633 #define IXL_SC_AQ_FLAG_RXCTL __BIT(0) 634 #define IXL_SC_AQ_FLAG_NVMLOCK __BIT(1) 635 #define IXL_SC_AQ_FLAG_NVMREAD __BIT(2) 636 #define IXL_SC_AQ_FLAG_RSS __BIT(3) 637 638 kmutex_t sc_atq_lock; 639 kcondvar_t sc_atq_cv; 640 struct ixl_dmamem sc_atq; 641 unsigned int sc_atq_prod; 642 unsigned int sc_atq_cons; 643 644 struct ixl_dmamem sc_arq; 645 struct ixl_work sc_arq_task; 646 struct ixl_aq_bufs sc_arq_idle; 647 struct ixl_aq_buf *sc_arq_live[IXL_AQ_NUM]; 648 unsigned int sc_arq_prod; 649 unsigned int sc_arq_cons; 650 651 struct ixl_work sc_link_state_task; 652 struct ixl_atq sc_link_state_atq; 653 654 struct ixl_dmamem sc_hmc_sd; 655 struct ixl_dmamem sc_hmc_pd; 656 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 657 658 struct if_percpuq *sc_ipq; 659 unsigned int sc_tx_ring_ndescs; 660 unsigned int sc_rx_ring_ndescs; 661 unsigned int sc_nqueue_pairs; 662 unsigned int sc_nqueue_pairs_max; 663 unsigned int sc_nqueue_pairs_device; 664 struct ixl_queue_pair *sc_qps; 665 uint32_t sc_itr_rx; 666 uint32_t sc_itr_tx; 667 668 struct evcnt sc_event_atq; 669 struct evcnt sc_event_link; 670 struct evcnt sc_event_ecc_err; 671 struct evcnt sc_event_pci_exception; 672 struct evcnt sc_event_crit_err; 673 }; 674 675 #define IXL_TXRX_PROCESS_UNLIMIT UINT_MAX 676 #define IXL_TX_PROCESS_LIMIT 256 677 #define IXL_RX_PROCESS_LIMIT 256 678 #define IXL_TX_INTR_PROCESS_LIMIT 256 679 #define IXL_RX_INTR_PROCESS_LIMIT 0U 680 681 #define IXL_IFCAP_RXCSUM (IFCAP_CSUM_IPv4_Rx | \ 682 IFCAP_CSUM_TCPv4_Rx | \ 683 IFCAP_CSUM_UDPv4_Rx | \ 684 IFCAP_CSUM_TCPv6_Rx | \ 685 IFCAP_CSUM_UDPv6_Rx) 686 #define IXL_IFCAP_TXCSUM (IFCAP_CSUM_IPv4_Tx | \ 687 IFCAP_CSUM_TCPv4_Tx | \ 688 IFCAP_CSUM_UDPv4_Tx | \ 689 IFCAP_CSUM_TCPv6_Tx | \ 690 IFCAP_CSUM_UDPv6_Tx) 691 #define IXL_CSUM_ALL_OFFLOAD (M_CSUM_IPv4 | \ 692 M_CSUM_TCPv4 | M_CSUM_TCPv6 | \ 693 M_CSUM_UDPv4 | M_CSUM_UDPv6) 694 695 #define delaymsec(_x) DELAY(1000 * (_x)) 696 #ifdef IXL_DEBUG 697 #define DDPRINTF(sc, fmt, args...) \ 698 do { \ 699 if ((sc) != NULL) { \ 700 device_printf( \ 701 ((struct ixl_softc *)(sc))->sc_dev, \ 702 ""); \ 703 } \ 704 printf("%s:\t" fmt, __func__, ##args); \ 705 } while (0) 706 #else 707 #define DDPRINTF(sc, fmt, args...) __nothing 708 #endif 709 #ifndef IXL_STATS_INTERVAL_MSEC 710 #define IXL_STATS_INTERVAL_MSEC 10000 711 #endif 712 #ifndef IXL_QUEUE_NUM 713 #define IXL_QUEUE_NUM 0 714 #endif 715 716 static bool ixl_param_nomsix = false; 717 static int ixl_param_stats_interval = IXL_STATS_INTERVAL_MSEC; 718 static int ixl_param_nqps_limit = IXL_QUEUE_NUM; 719 static unsigned int ixl_param_tx_ndescs = 512; 720 static unsigned int ixl_param_rx_ndescs = 256; 721 722 static enum i40e_mac_type 723 ixl_mactype(pci_product_id_t); 724 static void ixl_pci_csr_setup(pci_chipset_tag_t, pcitag_t); 725 static void ixl_clear_hw(struct ixl_softc *); 726 static int ixl_pf_reset(struct ixl_softc *); 727 728 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 729 bus_size_t, bus_size_t); 730 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 731 732 static int ixl_arq_fill(struct ixl_softc *); 733 static void ixl_arq_unfill(struct ixl_softc *); 734 735 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 736 unsigned int); 737 static void ixl_atq_set(struct ixl_atq *, 738 void (*)(struct ixl_softc *, const struct ixl_aq_desc *)); 739 static int ixl_atq_post_locked(struct ixl_softc *, struct ixl_atq *); 740 static void ixl_atq_done(struct ixl_softc *); 741 static int ixl_atq_exec(struct ixl_softc *, struct ixl_atq *); 742 static int ixl_atq_exec_locked(struct ixl_softc *, struct ixl_atq *); 743 static int ixl_get_version(struct ixl_softc *); 744 static int ixl_get_nvm_version(struct ixl_softc *); 745 static int ixl_get_hw_capabilities(struct ixl_softc *); 746 static int ixl_pxe_clear(struct ixl_softc *); 747 static int ixl_lldp_shut(struct ixl_softc *); 748 static int ixl_get_mac(struct ixl_softc *); 749 static int ixl_get_switch_config(struct ixl_softc *); 750 static int ixl_phy_mask_ints(struct ixl_softc *); 751 static int ixl_get_phy_info(struct ixl_softc *); 752 static int ixl_set_phy_config(struct ixl_softc *, uint8_t, uint8_t, bool); 753 static int ixl_set_phy_autoselect(struct ixl_softc *); 754 static int ixl_restart_an(struct ixl_softc *); 755 static int ixl_hmc(struct ixl_softc *); 756 static void ixl_hmc_free(struct ixl_softc *); 757 static int ixl_get_vsi(struct ixl_softc *); 758 static int ixl_set_vsi(struct ixl_softc *); 759 static void ixl_set_filter_control(struct ixl_softc *); 760 static void ixl_get_link_status(void *); 761 static int ixl_get_link_status_poll(struct ixl_softc *, int *); 762 static void ixl_get_link_status_done(struct ixl_softc *, 763 const struct ixl_aq_desc *); 764 static int ixl_set_link_status_locked(struct ixl_softc *, 765 const struct ixl_aq_desc *); 766 static uint64_t ixl_search_link_speed(uint8_t); 767 static uint8_t ixl_search_baudrate(uint64_t); 768 static void ixl_config_rss(struct ixl_softc *); 769 static int ixl_add_macvlan(struct ixl_softc *, const uint8_t *, 770 uint16_t, uint16_t); 771 static int ixl_remove_macvlan(struct ixl_softc *, const uint8_t *, 772 uint16_t, uint16_t); 773 static void ixl_arq(void *); 774 static void ixl_hmc_pack(void *, const void *, 775 const struct ixl_hmc_pack *, unsigned int); 776 static uint32_t ixl_rd_rx_csr(struct ixl_softc *, uint32_t); 777 static void ixl_wr_rx_csr(struct ixl_softc *, uint32_t, uint32_t); 778 static int ixl_rd16_nvm(struct ixl_softc *, uint16_t, uint16_t *); 779 780 static int ixl_match(device_t, cfdata_t, void *); 781 static void ixl_attach(device_t, device_t, void *); 782 static int ixl_detach(device_t, int); 783 784 static void ixl_media_add(struct ixl_softc *); 785 static int ixl_media_change(struct ifnet *); 786 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 787 static void ixl_watchdog(struct ifnet *); 788 static int ixl_ioctl(struct ifnet *, u_long, void *); 789 static void ixl_start(struct ifnet *); 790 static int ixl_transmit(struct ifnet *, struct mbuf *); 791 static void ixl_deferred_transmit(void *); 792 static int ixl_intr(void *); 793 static int ixl_queue_intr(void *); 794 static int ixl_other_intr(void *); 795 static void ixl_handle_queue(void *); 796 static void ixl_handle_queue_wk(struct work *, void *); 797 static void ixl_sched_handle_queue(struct ixl_softc *, 798 struct ixl_queue_pair *); 799 static int ixl_init(struct ifnet *); 800 static int ixl_init_locked(struct ixl_softc *); 801 static void ixl_stop(struct ifnet *, int); 802 static void ixl_stop_locked(struct ixl_softc *); 803 static int ixl_iff(struct ixl_softc *); 804 static int ixl_ifflags_cb(struct ethercom *); 805 static int ixl_setup_interrupts(struct ixl_softc *); 806 static int ixl_establish_intx(struct ixl_softc *); 807 static int ixl_establish_msix(struct ixl_softc *); 808 static void ixl_enable_queue_intr(struct ixl_softc *, 809 struct ixl_queue_pair *); 810 static void ixl_disable_queue_intr(struct ixl_softc *, 811 struct ixl_queue_pair *); 812 static void ixl_enable_other_intr(struct ixl_softc *); 813 static void ixl_disable_other_intr(struct ixl_softc *); 814 static void ixl_config_queue_intr(struct ixl_softc *); 815 static void ixl_config_other_intr(struct ixl_softc *); 816 817 static struct ixl_tx_ring * 818 ixl_txr_alloc(struct ixl_softc *, unsigned int); 819 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 820 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 821 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 822 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 823 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 824 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 825 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 826 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *, u_int); 827 828 static struct ixl_rx_ring * 829 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 830 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 831 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 832 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 833 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 834 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 835 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 836 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *, u_int); 837 static int ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 838 839 static struct workqueue * 840 ixl_workq_create(const char *, pri_t, int, int); 841 static void ixl_workq_destroy(struct workqueue *); 842 static int ixl_workqs_teardown(device_t); 843 static void ixl_work_set(struct ixl_work *, void (*)(void *), void *); 844 static void ixl_work_add(struct workqueue *, struct ixl_work *); 845 static void ixl_work_wait(struct workqueue *, struct ixl_work *); 846 static void ixl_workq_work(struct work *, void *); 847 static const struct ixl_product * 848 ixl_lookup(const struct pci_attach_args *pa); 849 static void ixl_link_state_update(struct ixl_softc *, 850 const struct ixl_aq_desc *); 851 static int ixl_vlan_cb(struct ethercom *, uint16_t, bool); 852 static int ixl_setup_vlan_hwfilter(struct ixl_softc *); 853 static void ixl_teardown_vlan_hwfilter(struct ixl_softc *); 854 static int ixl_update_macvlan(struct ixl_softc *); 855 static int ixl_setup_interrupts(struct ixl_softc *); 856 static void ixl_teardown_interrupts(struct ixl_softc *); 857 static int ixl_setup_stats(struct ixl_softc *); 858 static void ixl_teardown_stats(struct ixl_softc *); 859 static void ixl_stats_callout(void *); 860 static void ixl_stats_update(void *); 861 static int ixl_setup_sysctls(struct ixl_softc *); 862 static void ixl_teardown_sysctls(struct ixl_softc *); 863 static int ixl_sysctl_itr_handler(SYSCTLFN_PROTO); 864 static int ixl_queue_pairs_alloc(struct ixl_softc *); 865 static void ixl_queue_pairs_free(struct ixl_softc *); 866 867 static const struct ixl_phy_type ixl_phy_type_map[] = { 868 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 869 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 870 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 871 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 872 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 873 { 1ULL << IXL_PHY_TYPE_XAUI | 874 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 875 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 876 { 1ULL << IXL_PHY_TYPE_XLAUI | 877 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 878 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 879 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 880 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 881 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 882 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 883 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 884 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 885 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 886 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 887 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 888 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 889 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 890 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_TWINAX }, 891 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 892 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 893 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 894 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 895 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 896 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 897 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 898 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 899 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 900 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 901 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_ACC }, 902 { 1ULL << IXL_PHY_TYPE_2500BASE_T_1, IFM_2500_T }, 903 { 1ULL << IXL_PHY_TYPE_5000BASE_T_1, IFM_5000_T }, 904 { 1ULL << IXL_PHY_TYPE_2500BASE_T_2, IFM_2500_T }, 905 { 1ULL << IXL_PHY_TYPE_5000BASE_T_2, IFM_5000_T }, 906 }; 907 908 static const struct ixl_speed_type ixl_speed_type_map[] = { 909 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 910 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 911 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 912 { IXL_AQ_LINK_SPEED_5000MB, IF_Mbps(5000) }, 913 { IXL_AQ_LINK_SPEED_2500MB, IF_Mbps(2500) }, 914 { IXL_AQ_LINK_SPEED_1000MB, IF_Mbps(1000) }, 915 { IXL_AQ_LINK_SPEED_100MB, IF_Mbps(100)}, 916 }; 917 918 static const struct ixl_aq_regs ixl_pf_aq_regs = { 919 .atq_tail = I40E_PF_ATQT, 920 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 921 .atq_head = I40E_PF_ATQH, 922 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 923 .atq_len = I40E_PF_ATQLEN, 924 .atq_bal = I40E_PF_ATQBAL, 925 .atq_bah = I40E_PF_ATQBAH, 926 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 927 928 .arq_tail = I40E_PF_ARQT, 929 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 930 .arq_head = I40E_PF_ARQH, 931 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 932 .arq_len = I40E_PF_ARQLEN, 933 .arq_bal = I40E_PF_ARQBAL, 934 .arq_bah = I40E_PF_ARQBAH, 935 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 936 }; 937 938 #define ixl_rd(_s, _r) \ 939 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 940 #define ixl_wr(_s, _r, _v) \ 941 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 942 #define ixl_barrier(_s, _r, _l, _o) \ 943 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 944 #define ixl_flush(_s) (void)ixl_rd((_s), I40E_GLGEN_STAT) 945 #define ixl_nqueues(_sc) (1 << ((_sc)->sc_nqueue_pairs - 1)) 946 947 CFATTACH_DECL3_NEW(ixl, sizeof(struct ixl_softc), 948 ixl_match, ixl_attach, ixl_detach, NULL, NULL, NULL, 949 DVF_DETACH_SHUTDOWN); 950 951 static const struct ixl_product ixl_products[] = { 952 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_SFP }, 953 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_KX_B }, 954 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_KX_C }, 955 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_A }, 956 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_B }, 957 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_C }, 958 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T_1 }, 959 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_T_2 }, 960 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 961 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 962 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 963 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 964 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28 }, 965 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_KX }, 966 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_QSFP }, 967 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_SFP }, 968 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G_BASET }, 969 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_BASET }, 970 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_I_SFP }, 971 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP }, 972 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BP }, 973 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_V710_5G_T}, 974 /* required last entry */ 975 {0, 0} 976 }; 977 978 static const struct ixl_product * 979 ixl_lookup(const struct pci_attach_args *pa) 980 { 981 const struct ixl_product *ixlp; 982 983 for (ixlp = ixl_products; ixlp->vendor_id != 0; ixlp++) { 984 if (PCI_VENDOR(pa->pa_id) == ixlp->vendor_id && 985 PCI_PRODUCT(pa->pa_id) == ixlp->product_id) 986 return ixlp; 987 } 988 989 return NULL; 990 } 991 992 static int 993 ixl_match(device_t parent, cfdata_t match, void *aux) 994 { 995 const struct pci_attach_args *pa = aux; 996 997 return (ixl_lookup(pa) != NULL) ? 1 : 0; 998 } 999 1000 static void 1001 ixl_attach(device_t parent, device_t self, void *aux) 1002 { 1003 struct ixl_softc *sc; 1004 struct pci_attach_args *pa = aux; 1005 struct ifnet *ifp; 1006 pcireg_t memtype; 1007 uint32_t firstq, port, ari, func; 1008 char xnamebuf[32]; 1009 int tries, rv, link; 1010 1011 sc = device_private(self); 1012 sc->sc_dev = self; 1013 ifp = &sc->sc_ec.ec_if; 1014 1015 sc->sc_pa = *pa; 1016 sc->sc_dmat = (pci_dma64_available(pa)) ? 1017 pa->pa_dmat64 : pa->pa_dmat; 1018 sc->sc_aq_regs = &ixl_pf_aq_regs; 1019 1020 sc->sc_mac_type = ixl_mactype(PCI_PRODUCT(pa->pa_id)); 1021 1022 ixl_pci_csr_setup(pa->pa_pc, pa->pa_tag); 1023 1024 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IXL_PCIREG); 1025 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1026 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 1027 aprint_error(": unable to map registers\n"); 1028 return; 1029 } 1030 1031 mutex_init(&sc->sc_cfg_lock, MUTEX_DEFAULT, IPL_SOFTNET); 1032 1033 firstq = ixl_rd(sc, I40E_PFLAN_QALLOC); 1034 firstq &= I40E_PFLAN_QALLOC_FIRSTQ_MASK; 1035 firstq >>= I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1036 sc->sc_base_queue = firstq; 1037 1038 ixl_clear_hw(sc); 1039 if (ixl_pf_reset(sc) == -1) { 1040 /* error printed by ixl pf_reset */ 1041 goto unmap; 1042 } 1043 1044 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1045 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1046 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1047 sc->sc_port = port; 1048 aprint_normal(": port %u", sc->sc_port); 1049 1050 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1051 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1052 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1053 1054 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1055 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1056 1057 /* initialise the adminq */ 1058 1059 mutex_init(&sc->sc_atq_lock, MUTEX_DEFAULT, IPL_NET); 1060 1061 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1062 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1063 aprint_error("\n" "%s: unable to allocate atq\n", 1064 device_xname(self)); 1065 goto unmap; 1066 } 1067 1068 SIMPLEQ_INIT(&sc->sc_arq_idle); 1069 ixl_work_set(&sc->sc_arq_task, ixl_arq, sc); 1070 sc->sc_arq_cons = 0; 1071 sc->sc_arq_prod = 0; 1072 1073 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1074 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1075 aprint_error("\n" "%s: unable to allocate arq\n", 1076 device_xname(self)); 1077 goto free_atq; 1078 } 1079 1080 if (!ixl_arq_fill(sc)) { 1081 aprint_error("\n" "%s: unable to fill arq descriptors\n", 1082 device_xname(self)); 1083 goto free_arq; 1084 } 1085 1086 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1087 0, IXL_DMA_LEN(&sc->sc_atq), 1088 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1089 1090 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1091 0, IXL_DMA_LEN(&sc->sc_arq), 1092 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1093 1094 for (tries = 0; tries < 10; tries++) { 1095 sc->sc_atq_cons = 0; 1096 sc->sc_atq_prod = 0; 1097 1098 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1099 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1100 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1101 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1102 1103 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1104 1105 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1106 ixl_dmamem_lo(&sc->sc_atq)); 1107 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1108 ixl_dmamem_hi(&sc->sc_atq)); 1109 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1110 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1111 1112 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1113 ixl_dmamem_lo(&sc->sc_arq)); 1114 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1115 ixl_dmamem_hi(&sc->sc_arq)); 1116 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1117 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1118 1119 rv = ixl_get_version(sc); 1120 if (rv == 0) 1121 break; 1122 if (rv != ETIMEDOUT) { 1123 aprint_error(", unable to get firmware version\n"); 1124 goto shutdown; 1125 } 1126 1127 delaymsec(100); 1128 } 1129 1130 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1131 1132 if (ixl_dmamem_alloc(sc, &sc->sc_aqbuf, IXL_AQ_BUFLEN, 0) != 0) { 1133 aprint_error_dev(self, ", unable to allocate nvm buffer\n"); 1134 goto shutdown; 1135 } 1136 1137 ixl_get_nvm_version(sc); 1138 1139 if (sc->sc_mac_type == I40E_MAC_X722) 1140 sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_X722; 1141 else 1142 sc->sc_nqueue_pairs_device = IXL_QUEUE_MAX_XL710; 1143 1144 rv = ixl_get_hw_capabilities(sc); 1145 if (rv != 0) { 1146 aprint_error(", GET HW CAPABILITIES %s\n", 1147 rv == ETIMEDOUT ? "timeout" : "error"); 1148 goto free_aqbuf; 1149 } 1150 1151 sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_device, ncpu); 1152 if (ixl_param_nqps_limit > 0) { 1153 sc->sc_nqueue_pairs_max = MIN((int)sc->sc_nqueue_pairs_max, 1154 ixl_param_nqps_limit); 1155 } 1156 1157 sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max; 1158 sc->sc_tx_ring_ndescs = ixl_param_tx_ndescs; 1159 sc->sc_rx_ring_ndescs = ixl_param_rx_ndescs; 1160 1161 KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_rx_ring_ndescs); 1162 KASSERT(IXL_TXRX_PROCESS_UNLIMIT > sc->sc_tx_ring_ndescs); 1163 KASSERT(sc->sc_rx_ring_ndescs == 1164 (1U << (fls32(sc->sc_rx_ring_ndescs) - 1))); 1165 KASSERT(sc->sc_tx_ring_ndescs == 1166 (1U << (fls32(sc->sc_tx_ring_ndescs) - 1))); 1167 1168 if (ixl_get_mac(sc) != 0) { 1169 /* error printed by ixl_get_mac */ 1170 goto free_aqbuf; 1171 } 1172 1173 aprint_normal("\n"); 1174 aprint_naive("\n"); 1175 1176 aprint_normal_dev(self, "Ethernet address %s\n", 1177 ether_sprintf(sc->sc_enaddr)); 1178 1179 rv = ixl_pxe_clear(sc); 1180 if (rv != 0) { 1181 aprint_debug_dev(self, "CLEAR PXE MODE %s\n", 1182 rv == ETIMEDOUT ? "timeout" : "error"); 1183 } 1184 1185 ixl_set_filter_control(sc); 1186 1187 if (ixl_hmc(sc) != 0) { 1188 /* error printed by ixl_hmc */ 1189 goto free_aqbuf; 1190 } 1191 1192 if (ixl_lldp_shut(sc) != 0) { 1193 /* error printed by ixl_lldp_shut */ 1194 goto free_hmc; 1195 } 1196 1197 if (ixl_phy_mask_ints(sc) != 0) { 1198 /* error printed by ixl_phy_mask_ints */ 1199 goto free_hmc; 1200 } 1201 1202 if (ixl_restart_an(sc) != 0) { 1203 /* error printed by ixl_restart_an */ 1204 goto free_hmc; 1205 } 1206 1207 if (ixl_get_switch_config(sc) != 0) { 1208 /* error printed by ixl_get_switch_config */ 1209 goto free_hmc; 1210 } 1211 1212 rv = ixl_get_link_status_poll(sc, NULL); 1213 if (rv != 0) { 1214 aprint_error_dev(self, "GET LINK STATUS %s\n", 1215 rv == ETIMEDOUT ? "timeout" : "error"); 1216 goto free_hmc; 1217 } 1218 1219 /* 1220 * The FW often returns EIO in "Get PHY Abilities" command 1221 * if there is no delay 1222 */ 1223 DELAY(500); 1224 if (ixl_get_phy_info(sc) != 0) { 1225 /* error printed by ixl_get_phy_info */ 1226 goto free_hmc; 1227 } 1228 1229 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1230 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1231 aprint_error_dev(self, "unable to allocate scratch buffer\n"); 1232 goto free_hmc; 1233 } 1234 1235 rv = ixl_get_vsi(sc); 1236 if (rv != 0) { 1237 aprint_error_dev(self, "GET VSI %s %d\n", 1238 rv == ETIMEDOUT ? "timeout" : "error", rv); 1239 goto free_scratch; 1240 } 1241 1242 rv = ixl_set_vsi(sc); 1243 if (rv != 0) { 1244 aprint_error_dev(self, "UPDATE VSI error %s %d\n", 1245 rv == ETIMEDOUT ? "timeout" : "error", rv); 1246 goto free_scratch; 1247 } 1248 1249 if (ixl_queue_pairs_alloc(sc) != 0) { 1250 /* error printed by ixl_queue_pairs_alloc */ 1251 goto free_scratch; 1252 } 1253 1254 if (ixl_setup_interrupts(sc) != 0) { 1255 /* error printed by ixl_setup_interrupts */ 1256 goto free_queue_pairs; 1257 } 1258 1259 if (ixl_setup_stats(sc) != 0) { 1260 aprint_error_dev(self, "failed to setup event counters\n"); 1261 goto teardown_intrs; 1262 } 1263 1264 if (ixl_setup_sysctls(sc) != 0) { 1265 /* error printed by ixl_setup_sysctls */ 1266 goto teardown_stats; 1267 } 1268 1269 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_cfg", device_xname(self)); 1270 sc->sc_workq = ixl_workq_create(xnamebuf, IXL_WORKQUEUE_PRI, 1271 IPL_NET, WQ_MPSAFE); 1272 if (sc->sc_workq == NULL) 1273 goto teardown_sysctls; 1274 1275 snprintf(xnamebuf, sizeof(xnamebuf), "%s_wq_txrx", device_xname(self)); 1276 rv = workqueue_create(&sc->sc_workq_txrx, xnamebuf, ixl_handle_queue_wk, 1277 sc, IXL_WORKQUEUE_PRI, IPL_NET, WQ_PERCPU | WQ_MPSAFE); 1278 if (rv != 0) { 1279 sc->sc_workq_txrx = NULL; 1280 goto teardown_wqs; 1281 } 1282 1283 snprintf(xnamebuf, sizeof(xnamebuf), "%s_atq_cv", device_xname(self)); 1284 cv_init(&sc->sc_atq_cv, xnamebuf); 1285 1286 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1287 1288 ifp->if_softc = sc; 1289 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1290 ifp->if_extflags = IFEF_MPSAFE; 1291 ifp->if_ioctl = ixl_ioctl; 1292 ifp->if_start = ixl_start; 1293 ifp->if_transmit = ixl_transmit; 1294 ifp->if_watchdog = ixl_watchdog; 1295 ifp->if_init = ixl_init; 1296 ifp->if_stop = ixl_stop; 1297 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1298 IFQ_SET_READY(&ifp->if_snd); 1299 ifp->if_capabilities |= IXL_IFCAP_RXCSUM; 1300 ifp->if_capabilities |= IXL_IFCAP_TXCSUM; 1301 #if 0 1302 ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6; 1303 #endif 1304 ether_set_vlan_cb(&sc->sc_ec, ixl_vlan_cb); 1305 sc->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1306 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1307 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWFILTER; 1308 1309 sc->sc_ec.ec_capenable = sc->sc_ec.ec_capabilities; 1310 /* Disable VLAN_HWFILTER by default */ 1311 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1312 1313 sc->sc_cur_ec_capenable = sc->sc_ec.ec_capenable; 1314 1315 sc->sc_ec.ec_ifmedia = &sc->sc_media; 1316 ifmedia_init_with_lock(&sc->sc_media, IFM_IMASK, ixl_media_change, 1317 ixl_media_status, &sc->sc_cfg_lock); 1318 1319 ixl_media_add(sc); 1320 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1321 if (ISSET(sc->sc_phy_abilities, 1322 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) { 1323 ifmedia_add(&sc->sc_media, 1324 IFM_ETHER | IFM_AUTO | IFM_FLOW, 0, NULL); 1325 } 1326 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_NONE, 0, NULL); 1327 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1328 1329 if_initialize(ifp); 1330 1331 sc->sc_ipq = if_percpuq_create(ifp); 1332 if_deferred_start_init(ifp, NULL); 1333 ether_ifattach(ifp, sc->sc_enaddr); 1334 ether_set_ifflags_cb(&sc->sc_ec, ixl_ifflags_cb); 1335 1336 rv = ixl_get_link_status_poll(sc, &link); 1337 if (rv != 0) 1338 link = LINK_STATE_UNKNOWN; 1339 if_link_state_change(ifp, link); 1340 1341 ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done); 1342 ixl_work_set(&sc->sc_link_state_task, ixl_get_link_status, sc); 1343 1344 ixl_config_other_intr(sc); 1345 ixl_enable_other_intr(sc); 1346 1347 ixl_set_phy_autoselect(sc); 1348 1349 /* remove default mac filter and replace it so we can see vlans */ 1350 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 0); 1351 if (rv != ENOENT) { 1352 aprint_debug_dev(self, 1353 "unable to remove macvlan %u\n", rv); 1354 } 1355 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 1356 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1357 if (rv != ENOENT) { 1358 aprint_debug_dev(self, 1359 "unable to remove macvlan, ignore vlan %u\n", rv); 1360 } 1361 1362 if (ixl_update_macvlan(sc) != 0) { 1363 aprint_debug_dev(self, 1364 "couldn't enable vlan hardware filter\n"); 1365 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 1366 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 1367 } 1368 1369 sc->sc_txrx_workqueue = true; 1370 sc->sc_tx_process_limit = IXL_TX_PROCESS_LIMIT; 1371 sc->sc_rx_process_limit = IXL_RX_PROCESS_LIMIT; 1372 sc->sc_tx_intr_process_limit = IXL_TX_INTR_PROCESS_LIMIT; 1373 sc->sc_rx_intr_process_limit = IXL_RX_INTR_PROCESS_LIMIT; 1374 1375 ixl_stats_update(sc); 1376 sc->sc_stats_counters.isc_has_offset = true; 1377 1378 if (pmf_device_register(self, NULL, NULL) != true) 1379 aprint_debug_dev(self, "couldn't establish power handler\n"); 1380 sc->sc_itr_rx = IXL_ITR_RX; 1381 sc->sc_itr_tx = IXL_ITR_TX; 1382 sc->sc_attached = true; 1383 if_register(ifp); 1384 1385 return; 1386 1387 teardown_wqs: 1388 config_finalize_register(self, ixl_workqs_teardown); 1389 teardown_sysctls: 1390 ixl_teardown_sysctls(sc); 1391 teardown_stats: 1392 ixl_teardown_stats(sc); 1393 teardown_intrs: 1394 ixl_teardown_interrupts(sc); 1395 free_queue_pairs: 1396 ixl_queue_pairs_free(sc); 1397 free_scratch: 1398 ixl_dmamem_free(sc, &sc->sc_scratch); 1399 free_hmc: 1400 ixl_hmc_free(sc); 1401 free_aqbuf: 1402 ixl_dmamem_free(sc, &sc->sc_aqbuf); 1403 shutdown: 1404 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1405 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1406 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1407 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1408 1409 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1410 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1411 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1412 1413 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1414 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1415 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1416 1417 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1418 0, IXL_DMA_LEN(&sc->sc_arq), 1419 BUS_DMASYNC_POSTREAD); 1420 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1421 0, IXL_DMA_LEN(&sc->sc_atq), 1422 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1423 1424 ixl_arq_unfill(sc); 1425 free_arq: 1426 ixl_dmamem_free(sc, &sc->sc_arq); 1427 free_atq: 1428 ixl_dmamem_free(sc, &sc->sc_atq); 1429 unmap: 1430 mutex_destroy(&sc->sc_atq_lock); 1431 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1432 mutex_destroy(&sc->sc_cfg_lock); 1433 sc->sc_mems = 0; 1434 1435 sc->sc_attached = false; 1436 } 1437 1438 static int 1439 ixl_detach(device_t self, int flags) 1440 { 1441 struct ixl_softc *sc = device_private(self); 1442 struct ifnet *ifp = &sc->sc_ec.ec_if; 1443 1444 if (!sc->sc_attached) 1445 return 0; 1446 1447 ixl_stop(ifp, 1); 1448 1449 ixl_disable_other_intr(sc); 1450 1451 callout_halt(&sc->sc_stats_callout, NULL); 1452 ixl_work_wait(sc->sc_workq, &sc->sc_stats_task); 1453 1454 /* wait for ATQ handler */ 1455 mutex_enter(&sc->sc_atq_lock); 1456 mutex_exit(&sc->sc_atq_lock); 1457 1458 ixl_work_wait(sc->sc_workq, &sc->sc_arq_task); 1459 ixl_work_wait(sc->sc_workq, &sc->sc_link_state_task); 1460 1461 if (sc->sc_workq != NULL) { 1462 ixl_workq_destroy(sc->sc_workq); 1463 sc->sc_workq = NULL; 1464 } 1465 1466 if (sc->sc_workq_txrx != NULL) { 1467 workqueue_destroy(sc->sc_workq_txrx); 1468 sc->sc_workq_txrx = NULL; 1469 } 1470 1471 if_percpuq_destroy(sc->sc_ipq); 1472 ether_ifdetach(ifp); 1473 if_detach(ifp); 1474 ifmedia_fini(&sc->sc_media); 1475 1476 ixl_teardown_interrupts(sc); 1477 ixl_teardown_stats(sc); 1478 ixl_teardown_sysctls(sc); 1479 1480 ixl_queue_pairs_free(sc); 1481 1482 ixl_dmamem_free(sc, &sc->sc_scratch); 1483 ixl_hmc_free(sc); 1484 1485 /* shutdown */ 1486 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1487 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1488 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1489 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1490 1491 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 1492 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 1493 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 1494 1495 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 1496 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 1497 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 1498 1499 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1500 0, IXL_DMA_LEN(&sc->sc_arq), 1501 BUS_DMASYNC_POSTREAD); 1502 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1503 0, IXL_DMA_LEN(&sc->sc_atq), 1504 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1505 1506 ixl_arq_unfill(sc); 1507 1508 ixl_dmamem_free(sc, &sc->sc_arq); 1509 ixl_dmamem_free(sc, &sc->sc_atq); 1510 ixl_dmamem_free(sc, &sc->sc_aqbuf); 1511 1512 cv_destroy(&sc->sc_atq_cv); 1513 mutex_destroy(&sc->sc_atq_lock); 1514 1515 if (sc->sc_mems != 0) { 1516 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 1517 sc->sc_mems = 0; 1518 } 1519 1520 mutex_destroy(&sc->sc_cfg_lock); 1521 1522 return 0; 1523 } 1524 1525 static int 1526 ixl_workqs_teardown(device_t self) 1527 { 1528 struct ixl_softc *sc = device_private(self); 1529 1530 if (sc->sc_workq != NULL) { 1531 ixl_workq_destroy(sc->sc_workq); 1532 sc->sc_workq = NULL; 1533 } 1534 1535 if (sc->sc_workq_txrx != NULL) { 1536 workqueue_destroy(sc->sc_workq_txrx); 1537 sc->sc_workq_txrx = NULL; 1538 } 1539 1540 return 0; 1541 } 1542 1543 static int 1544 ixl_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 1545 { 1546 struct ifnet *ifp = &ec->ec_if; 1547 struct ixl_softc *sc = ifp->if_softc; 1548 int rv; 1549 1550 if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 1551 return 0; 1552 } 1553 1554 if (set) { 1555 rv = ixl_add_macvlan(sc, sc->sc_enaddr, vid, 1556 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 1557 if (rv == 0) { 1558 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 1559 vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 1560 } 1561 } else { 1562 rv = ixl_remove_macvlan(sc, sc->sc_enaddr, vid, 1563 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 1564 (void)ixl_remove_macvlan(sc, etherbroadcastaddr, vid, 1565 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 1566 } 1567 1568 return rv; 1569 } 1570 1571 static void 1572 ixl_media_add(struct ixl_softc *sc) 1573 { 1574 struct ifmedia *ifm = &sc->sc_media; 1575 const struct ixl_phy_type *itype; 1576 unsigned int i; 1577 bool flow; 1578 1579 if (ISSET(sc->sc_phy_abilities, 1580 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX))) { 1581 flow = true; 1582 } else { 1583 flow = false; 1584 } 1585 1586 for (i = 0; i < __arraycount(ixl_phy_type_map); i++) { 1587 itype = &ixl_phy_type_map[i]; 1588 1589 if (ISSET(sc->sc_phy_types, itype->phy_type)) { 1590 ifmedia_add(ifm, 1591 IFM_ETHER | IFM_FDX | itype->ifm_type, 0, NULL); 1592 1593 if (flow) { 1594 ifmedia_add(ifm, 1595 IFM_ETHER | IFM_FDX | IFM_FLOW | 1596 itype->ifm_type, 0, NULL); 1597 } 1598 1599 if (itype->ifm_type != IFM_100_TX) 1600 continue; 1601 1602 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 1603 0, NULL); 1604 if (flow) { 1605 ifmedia_add(ifm, 1606 IFM_ETHER | IFM_FLOW | itype->ifm_type, 1607 0, NULL); 1608 } 1609 } 1610 } 1611 } 1612 1613 static void 1614 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1615 { 1616 struct ixl_softc *sc = ifp->if_softc; 1617 1618 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1619 1620 ifmr->ifm_status = sc->sc_media_status; 1621 ifmr->ifm_active = sc->sc_media_active; 1622 } 1623 1624 static int 1625 ixl_media_change(struct ifnet *ifp) 1626 { 1627 struct ixl_softc *sc = ifp->if_softc; 1628 struct ifmedia *ifm = &sc->sc_media; 1629 uint64_t ifm_active = sc->sc_media_active; 1630 uint8_t link_speed, abilities; 1631 1632 switch (IFM_SUBTYPE(ifm_active)) { 1633 case IFM_1000_SGMII: 1634 case IFM_1000_KX: 1635 case IFM_10G_KX4: 1636 case IFM_10G_KR: 1637 case IFM_40G_KR4: 1638 case IFM_20G_KR2: 1639 case IFM_25G_KR: 1640 /* backplanes */ 1641 return EINVAL; 1642 } 1643 1644 abilities = IXL_PHY_ABILITY_AUTONEGO | IXL_PHY_ABILITY_LINKUP; 1645 1646 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1647 case IFM_AUTO: 1648 link_speed = sc->sc_phy_linkspeed; 1649 break; 1650 case IFM_NONE: 1651 link_speed = 0; 1652 CLR(abilities, IXL_PHY_ABILITY_LINKUP); 1653 break; 1654 default: 1655 link_speed = ixl_search_baudrate( 1656 ifmedia_baudrate(ifm->ifm_media)); 1657 } 1658 1659 if (ISSET(abilities, IXL_PHY_ABILITY_LINKUP)) { 1660 if (ISSET(link_speed, sc->sc_phy_linkspeed) == 0) 1661 return EINVAL; 1662 } 1663 1664 if (ifm->ifm_media & IFM_FLOW) { 1665 abilities |= sc->sc_phy_abilities & 1666 (IXL_PHY_ABILITY_PAUSE_TX | IXL_PHY_ABILITY_PAUSE_RX); 1667 } 1668 1669 return ixl_set_phy_config(sc, link_speed, abilities, false); 1670 } 1671 1672 static void 1673 ixl_watchdog(struct ifnet *ifp) 1674 { 1675 1676 } 1677 1678 static void 1679 ixl_del_all_multiaddr(struct ixl_softc *sc) 1680 { 1681 struct ethercom *ec = &sc->sc_ec; 1682 struct ether_multi *enm; 1683 struct ether_multistep step; 1684 1685 ETHER_LOCK(ec); 1686 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1687 ETHER_NEXT_MULTI(step, enm)) { 1688 ixl_remove_macvlan(sc, enm->enm_addrlo, 0, 1689 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1690 } 1691 ETHER_UNLOCK(ec); 1692 } 1693 1694 static int 1695 ixl_add_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1696 { 1697 struct ifnet *ifp = &sc->sc_ec.ec_if; 1698 int rv; 1699 1700 if (ISSET(ifp->if_flags, IFF_ALLMULTI)) 1701 return 0; 1702 1703 if (memcmp(addrlo, addrhi, ETHER_ADDR_LEN) != 0) { 1704 ixl_del_all_multiaddr(sc); 1705 SET(ifp->if_flags, IFF_ALLMULTI); 1706 return ENETRESET; 1707 } 1708 1709 /* multicast address can not use VLAN HWFILTER */ 1710 rv = ixl_add_macvlan(sc, addrlo, 0, 1711 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1712 1713 if (rv == ENOSPC) { 1714 ixl_del_all_multiaddr(sc); 1715 SET(ifp->if_flags, IFF_ALLMULTI); 1716 return ENETRESET; 1717 } 1718 1719 return rv; 1720 } 1721 1722 static int 1723 ixl_del_multi(struct ixl_softc *sc, uint8_t *addrlo, uint8_t *addrhi) 1724 { 1725 struct ifnet *ifp = &sc->sc_ec.ec_if; 1726 struct ethercom *ec = &sc->sc_ec; 1727 struct ether_multi *enm, *enm_last; 1728 struct ether_multistep step; 1729 int error, rv = 0; 1730 1731 if (!ISSET(ifp->if_flags, IFF_ALLMULTI)) { 1732 ixl_remove_macvlan(sc, addrlo, 0, 1733 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1734 return 0; 1735 } 1736 1737 ETHER_LOCK(ec); 1738 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1739 ETHER_NEXT_MULTI(step, enm)) { 1740 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1741 ETHER_ADDR_LEN) != 0) { 1742 goto out; 1743 } 1744 } 1745 1746 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1747 ETHER_NEXT_MULTI(step, enm)) { 1748 error = ixl_add_macvlan(sc, enm->enm_addrlo, 0, 1749 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1750 if (error != 0) 1751 break; 1752 } 1753 1754 if (enm != NULL) { 1755 enm_last = enm; 1756 for (ETHER_FIRST_MULTI(step, ec, enm); enm != NULL; 1757 ETHER_NEXT_MULTI(step, enm)) { 1758 if (enm == enm_last) 1759 break; 1760 1761 ixl_remove_macvlan(sc, enm->enm_addrlo, 0, 1762 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1763 } 1764 } else { 1765 CLR(ifp->if_flags, IFF_ALLMULTI); 1766 rv = ENETRESET; 1767 } 1768 1769 out: 1770 ETHER_UNLOCK(ec); 1771 return rv; 1772 } 1773 1774 static int 1775 ixl_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1776 { 1777 struct ifreq *ifr = (struct ifreq *)data; 1778 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 1779 const struct sockaddr *sa; 1780 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 1781 int s, error = 0; 1782 unsigned int nmtu; 1783 1784 switch (cmd) { 1785 case SIOCSIFMTU: 1786 nmtu = ifr->ifr_mtu; 1787 1788 if (nmtu < IXL_MIN_MTU || nmtu > IXL_MAX_MTU) { 1789 error = EINVAL; 1790 break; 1791 } 1792 if (ifp->if_mtu != nmtu) { 1793 s = splnet(); 1794 error = ether_ioctl(ifp, cmd, data); 1795 splx(s); 1796 if (error == ENETRESET) 1797 error = ixl_init(ifp); 1798 } 1799 break; 1800 case SIOCADDMULTI: 1801 sa = ifreq_getaddr(SIOCADDMULTI, ifr); 1802 if (ether_addmulti(sa, &sc->sc_ec) == ENETRESET) { 1803 error = ether_multiaddr(sa, addrlo, addrhi); 1804 if (error != 0) 1805 return error; 1806 1807 error = ixl_add_multi(sc, addrlo, addrhi); 1808 if (error != 0 && error != ENETRESET) { 1809 ether_delmulti(sa, &sc->sc_ec); 1810 error = EIO; 1811 } 1812 } 1813 break; 1814 1815 case SIOCDELMULTI: 1816 sa = ifreq_getaddr(SIOCDELMULTI, ifr); 1817 if (ether_delmulti(sa, &sc->sc_ec) == ENETRESET) { 1818 error = ether_multiaddr(sa, addrlo, addrhi); 1819 if (error != 0) 1820 return error; 1821 1822 error = ixl_del_multi(sc, addrlo, addrhi); 1823 } 1824 break; 1825 1826 default: 1827 s = splnet(); 1828 error = ether_ioctl(ifp, cmd, data); 1829 splx(s); 1830 } 1831 1832 if (error == ENETRESET) 1833 error = ixl_iff(sc); 1834 1835 return error; 1836 } 1837 1838 static enum i40e_mac_type 1839 ixl_mactype(pci_product_id_t id) 1840 { 1841 1842 switch (id) { 1843 case PCI_PRODUCT_INTEL_XL710_SFP: 1844 case PCI_PRODUCT_INTEL_XL710_KX_B: 1845 case PCI_PRODUCT_INTEL_XL710_KX_C: 1846 case PCI_PRODUCT_INTEL_XL710_QSFP_A: 1847 case PCI_PRODUCT_INTEL_XL710_QSFP_B: 1848 case PCI_PRODUCT_INTEL_XL710_QSFP_C: 1849 case PCI_PRODUCT_INTEL_X710_10G_T_1: 1850 case PCI_PRODUCT_INTEL_X710_10G_T_2: 1851 case PCI_PRODUCT_INTEL_XL710_20G_BP_1: 1852 case PCI_PRODUCT_INTEL_XL710_20G_BP_2: 1853 case PCI_PRODUCT_INTEL_X710_T4_10G: 1854 case PCI_PRODUCT_INTEL_XXV710_25G_BP: 1855 case PCI_PRODUCT_INTEL_XXV710_25G_SFP28: 1856 case PCI_PRODUCT_INTEL_X710_10G_SFP: 1857 case PCI_PRODUCT_INTEL_X710_10G_BP: 1858 return I40E_MAC_XL710; 1859 1860 case PCI_PRODUCT_INTEL_X722_KX: 1861 case PCI_PRODUCT_INTEL_X722_QSFP: 1862 case PCI_PRODUCT_INTEL_X722_SFP: 1863 case PCI_PRODUCT_INTEL_X722_1G_BASET: 1864 case PCI_PRODUCT_INTEL_X722_10G_BASET: 1865 case PCI_PRODUCT_INTEL_X722_I_SFP: 1866 return I40E_MAC_X722; 1867 } 1868 1869 return I40E_MAC_GENERIC; 1870 } 1871 1872 static void 1873 ixl_pci_csr_setup(pci_chipset_tag_t pc, pcitag_t tag) 1874 { 1875 pcireg_t csr; 1876 1877 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1878 csr |= (PCI_COMMAND_MASTER_ENABLE | 1879 PCI_COMMAND_MEM_ENABLE); 1880 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 1881 } 1882 1883 static inline void * 1884 ixl_hmc_kva(struct ixl_softc *sc, enum ixl_hmc_types type, unsigned int i) 1885 { 1886 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 1887 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 1888 1889 if (i >= e->hmc_count) 1890 return NULL; 1891 1892 kva += e->hmc_base; 1893 kva += i * e->hmc_size; 1894 1895 return kva; 1896 } 1897 1898 static inline size_t 1899 ixl_hmc_len(struct ixl_softc *sc, enum ixl_hmc_types type) 1900 { 1901 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 1902 1903 return e->hmc_size; 1904 } 1905 1906 static void 1907 ixl_enable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp) 1908 { 1909 struct ixl_rx_ring *rxr = qp->qp_rxr; 1910 1911 ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid), 1912 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1913 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1914 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1915 ixl_flush(sc); 1916 } 1917 1918 static void 1919 ixl_disable_queue_intr(struct ixl_softc *sc, struct ixl_queue_pair *qp) 1920 { 1921 struct ixl_rx_ring *rxr = qp->qp_rxr; 1922 1923 ixl_wr(sc, I40E_PFINT_DYN_CTLN(rxr->rxr_qid), 1924 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1925 ixl_flush(sc); 1926 } 1927 1928 static void 1929 ixl_enable_other_intr(struct ixl_softc *sc) 1930 { 1931 1932 ixl_wr(sc, I40E_PFINT_DYN_CTL0, 1933 I40E_PFINT_DYN_CTL0_INTENA_MASK | 1934 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 1935 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)); 1936 ixl_flush(sc); 1937 } 1938 1939 static void 1940 ixl_disable_other_intr(struct ixl_softc *sc) 1941 { 1942 1943 ixl_wr(sc, I40E_PFINT_DYN_CTL0, 1944 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)); 1945 ixl_flush(sc); 1946 } 1947 1948 static int 1949 ixl_reinit(struct ixl_softc *sc) 1950 { 1951 struct ixl_rx_ring *rxr; 1952 struct ixl_tx_ring *txr; 1953 unsigned int i; 1954 uint32_t reg; 1955 1956 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 1957 1958 if (ixl_get_vsi(sc) != 0) 1959 return EIO; 1960 1961 if (ixl_set_vsi(sc) != 0) 1962 return EIO; 1963 1964 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1965 txr = sc->sc_qps[i].qp_txr; 1966 rxr = sc->sc_qps[i].qp_rxr; 1967 1968 ixl_txr_config(sc, txr); 1969 ixl_rxr_config(sc, rxr); 1970 } 1971 1972 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 1973 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_PREWRITE); 1974 1975 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 1976 txr = sc->sc_qps[i].qp_txr; 1977 rxr = sc->sc_qps[i].qp_rxr; 1978 1979 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 1980 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 1981 ixl_flush(sc); 1982 1983 ixl_wr(sc, txr->txr_tail, txr->txr_prod); 1984 ixl_wr(sc, rxr->rxr_tail, rxr->rxr_prod); 1985 1986 /* ixl_rxfill() needs lock held */ 1987 mutex_enter(&rxr->rxr_lock); 1988 ixl_rxfill(sc, rxr); 1989 mutex_exit(&rxr->rxr_lock); 1990 1991 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 1992 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 1993 ixl_wr(sc, I40E_QRX_ENA(i), reg); 1994 if (ixl_rxr_enabled(sc, rxr) != 0) 1995 goto stop; 1996 1997 ixl_txr_qdis(sc, txr, 1); 1998 1999 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2000 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2001 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2002 2003 if (ixl_txr_enabled(sc, txr) != 0) 2004 goto stop; 2005 } 2006 2007 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2008 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE); 2009 2010 return 0; 2011 2012 stop: 2013 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 2014 0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE); 2015 2016 return ETIMEDOUT; 2017 } 2018 2019 static int 2020 ixl_init_locked(struct ixl_softc *sc) 2021 { 2022 struct ifnet *ifp = &sc->sc_ec.ec_if; 2023 unsigned int i; 2024 int error, eccap_change; 2025 2026 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2027 2028 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2029 ixl_stop_locked(sc); 2030 2031 if (sc->sc_dead) { 2032 return ENXIO; 2033 } 2034 2035 eccap_change = sc->sc_ec.ec_capenable ^ sc->sc_cur_ec_capenable; 2036 if (ISSET(eccap_change, ETHERCAP_VLAN_HWTAGGING)) 2037 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING; 2038 2039 if (ISSET(eccap_change, ETHERCAP_VLAN_HWFILTER)) { 2040 if (ixl_update_macvlan(sc) == 0) { 2041 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER; 2042 } else { 2043 CLR(sc->sc_ec.ec_capenable, ETHERCAP_VLAN_HWFILTER); 2044 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 2045 } 2046 } 2047 2048 if (sc->sc_intrtype != PCI_INTR_TYPE_MSIX) 2049 sc->sc_nqueue_pairs = 1; 2050 else 2051 sc->sc_nqueue_pairs = sc->sc_nqueue_pairs_max; 2052 2053 error = ixl_reinit(sc); 2054 if (error) { 2055 ixl_stop_locked(sc); 2056 return error; 2057 } 2058 2059 SET(ifp->if_flags, IFF_RUNNING); 2060 CLR(ifp->if_flags, IFF_OACTIVE); 2061 2062 ixl_config_rss(sc); 2063 ixl_config_queue_intr(sc); 2064 2065 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2066 ixl_enable_queue_intr(sc, &sc->sc_qps[i]); 2067 } 2068 2069 error = ixl_iff(sc); 2070 if (error) { 2071 ixl_stop_locked(sc); 2072 return error; 2073 } 2074 2075 callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval)); 2076 2077 return 0; 2078 } 2079 2080 static int 2081 ixl_init(struct ifnet *ifp) 2082 { 2083 struct ixl_softc *sc = ifp->if_softc; 2084 int error; 2085 2086 mutex_enter(&sc->sc_cfg_lock); 2087 error = ixl_init_locked(sc); 2088 mutex_exit(&sc->sc_cfg_lock); 2089 2090 if (error == 0) 2091 (void)ixl_get_link_status(sc); 2092 2093 return error; 2094 } 2095 2096 static int 2097 ixl_iff(struct ixl_softc *sc) 2098 { 2099 struct ifnet *ifp = &sc->sc_ec.ec_if; 2100 struct ixl_atq iatq; 2101 struct ixl_aq_desc *iaq; 2102 struct ixl_aq_vsi_promisc_param *param; 2103 uint16_t flag_add, flag_del; 2104 int error; 2105 2106 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2107 return 0; 2108 2109 memset(&iatq, 0, sizeof(iatq)); 2110 2111 iaq = &iatq.iatq_desc; 2112 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2113 2114 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2115 param->flags = htole16(0); 2116 2117 if (!ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER) 2118 || ISSET(ifp->if_flags, IFF_PROMISC)) { 2119 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2120 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2121 } 2122 2123 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2124 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2125 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2126 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2127 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2128 } 2129 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2130 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2131 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2132 param->seid = sc->sc_seid; 2133 2134 error = ixl_atq_exec(sc, &iatq); 2135 if (error) 2136 return error; 2137 2138 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2139 return EIO; 2140 2141 if (memcmp(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN) != 0) { 2142 if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 2143 flag_add = IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH; 2144 flag_del = IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH; 2145 } else { 2146 flag_add = IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN; 2147 flag_del = IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN; 2148 } 2149 2150 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, flag_del); 2151 2152 memcpy(sc->sc_enaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 2153 ixl_add_macvlan(sc, sc->sc_enaddr, 0, flag_add); 2154 } 2155 return 0; 2156 } 2157 2158 static void 2159 ixl_stop_locked(struct ixl_softc *sc) 2160 { 2161 struct ifnet *ifp = &sc->sc_ec.ec_if; 2162 struct ixl_rx_ring *rxr; 2163 struct ixl_tx_ring *txr; 2164 unsigned int i; 2165 uint32_t reg; 2166 2167 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 2168 2169 CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE); 2170 callout_stop(&sc->sc_stats_callout); 2171 2172 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2173 txr = sc->sc_qps[i].qp_txr; 2174 rxr = sc->sc_qps[i].qp_rxr; 2175 2176 ixl_disable_queue_intr(sc, &sc->sc_qps[i]); 2177 2178 mutex_enter(&txr->txr_lock); 2179 ixl_txr_qdis(sc, txr, 0); 2180 mutex_exit(&txr->txr_lock); 2181 } 2182 2183 /* XXX wait at least 400 usec for all tx queues in one go */ 2184 ixl_flush(sc); 2185 DELAY(500); 2186 2187 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2188 txr = sc->sc_qps[i].qp_txr; 2189 rxr = sc->sc_qps[i].qp_rxr; 2190 2191 mutex_enter(&txr->txr_lock); 2192 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2193 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2194 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2195 mutex_exit(&txr->txr_lock); 2196 2197 mutex_enter(&rxr->rxr_lock); 2198 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2199 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2200 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2201 mutex_exit(&rxr->rxr_lock); 2202 } 2203 2204 /* XXX short wait for all queue disables to settle */ 2205 ixl_flush(sc); 2206 DELAY(50); 2207 2208 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2209 txr = sc->sc_qps[i].qp_txr; 2210 rxr = sc->sc_qps[i].qp_rxr; 2211 2212 mutex_enter(&txr->txr_lock); 2213 if (ixl_txr_disabled(sc, txr) != 0) { 2214 mutex_exit(&txr->txr_lock); 2215 goto die; 2216 } 2217 mutex_exit(&txr->txr_lock); 2218 2219 mutex_enter(&rxr->rxr_lock); 2220 if (ixl_rxr_disabled(sc, rxr) != 0) { 2221 mutex_exit(&rxr->rxr_lock); 2222 goto die; 2223 } 2224 mutex_exit(&rxr->rxr_lock); 2225 } 2226 2227 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2228 sc->sc_qps[i].qp_workqueue = false; 2229 workqueue_wait(sc->sc_workq_txrx, 2230 &sc->sc_qps[i].qp_work); 2231 } 2232 2233 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 2234 txr = sc->sc_qps[i].qp_txr; 2235 rxr = sc->sc_qps[i].qp_rxr; 2236 2237 mutex_enter(&txr->txr_lock); 2238 ixl_txr_unconfig(sc, txr); 2239 mutex_exit(&txr->txr_lock); 2240 2241 mutex_enter(&rxr->rxr_lock); 2242 ixl_rxr_unconfig(sc, rxr); 2243 mutex_exit(&rxr->rxr_lock); 2244 2245 ixl_txr_clean(sc, txr); 2246 ixl_rxr_clean(sc, rxr); 2247 } 2248 2249 return; 2250 die: 2251 sc->sc_dead = true; 2252 log(LOG_CRIT, "%s: failed to shut down rings", 2253 device_xname(sc->sc_dev)); 2254 return; 2255 } 2256 2257 static void 2258 ixl_stop(struct ifnet *ifp, int disable) 2259 { 2260 struct ixl_softc *sc = ifp->if_softc; 2261 2262 mutex_enter(&sc->sc_cfg_lock); 2263 ixl_stop_locked(sc); 2264 mutex_exit(&sc->sc_cfg_lock); 2265 } 2266 2267 static int 2268 ixl_queue_pairs_alloc(struct ixl_softc *sc) 2269 { 2270 struct ixl_queue_pair *qp; 2271 unsigned int i; 2272 size_t sz; 2273 2274 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2275 sc->sc_qps = kmem_zalloc(sz, KM_SLEEP); 2276 2277 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2278 qp = &sc->sc_qps[i]; 2279 2280 qp->qp_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 2281 ixl_handle_queue, qp); 2282 if (qp->qp_si == NULL) 2283 goto free; 2284 2285 qp->qp_txr = ixl_txr_alloc(sc, i); 2286 if (qp->qp_txr == NULL) 2287 goto free; 2288 2289 qp->qp_rxr = ixl_rxr_alloc(sc, i); 2290 if (qp->qp_rxr == NULL) 2291 goto free; 2292 2293 qp->qp_sc = sc; 2294 snprintf(qp->qp_name, sizeof(qp->qp_name), 2295 "%s-TXRX%d", device_xname(sc->sc_dev), i); 2296 } 2297 2298 return 0; 2299 free: 2300 if (sc->sc_qps != NULL) { 2301 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2302 qp = &sc->sc_qps[i]; 2303 2304 if (qp->qp_txr != NULL) 2305 ixl_txr_free(sc, qp->qp_txr); 2306 if (qp->qp_rxr != NULL) 2307 ixl_rxr_free(sc, qp->qp_rxr); 2308 if (qp->qp_si != NULL) 2309 softint_disestablish(qp->qp_si); 2310 } 2311 2312 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2313 kmem_free(sc->sc_qps, sz); 2314 sc->sc_qps = NULL; 2315 } 2316 2317 return -1; 2318 } 2319 2320 static void 2321 ixl_queue_pairs_free(struct ixl_softc *sc) 2322 { 2323 struct ixl_queue_pair *qp; 2324 unsigned int i; 2325 size_t sz; 2326 2327 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 2328 qp = &sc->sc_qps[i]; 2329 ixl_txr_free(sc, qp->qp_txr); 2330 ixl_rxr_free(sc, qp->qp_rxr); 2331 softint_disestablish(qp->qp_si); 2332 } 2333 2334 sz = sizeof(sc->sc_qps[0]) * sc->sc_nqueue_pairs_max; 2335 kmem_free(sc->sc_qps, sz); 2336 sc->sc_qps = NULL; 2337 } 2338 2339 static struct ixl_tx_ring * 2340 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2341 { 2342 struct ixl_tx_ring *txr = NULL; 2343 struct ixl_tx_map *maps = NULL, *txm; 2344 unsigned int i; 2345 2346 txr = kmem_zalloc(sizeof(*txr), KM_SLEEP); 2347 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_tx_ring_ndescs, 2348 KM_SLEEP); 2349 2350 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2351 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2352 IXL_TX_QUEUE_ALIGN) != 0) 2353 goto free; 2354 2355 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2356 txm = &maps[i]; 2357 2358 if (bus_dmamap_create(sc->sc_dmat, IXL_TX_PKT_MAXSIZE, 2359 IXL_TX_PKT_DESCS, IXL_TX_PKT_MAXSIZE, 0, 2360 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &txm->txm_map) != 0) 2361 goto uncreate; 2362 2363 txm->txm_eop = -1; 2364 txm->txm_m = NULL; 2365 } 2366 2367 txr->txr_cons = txr->txr_prod = 0; 2368 txr->txr_maps = maps; 2369 2370 txr->txr_intrq = pcq_create(sc->sc_tx_ring_ndescs, KM_NOSLEEP); 2371 if (txr->txr_intrq == NULL) 2372 goto uncreate; 2373 2374 txr->txr_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 2375 ixl_deferred_transmit, txr); 2376 if (txr->txr_si == NULL) 2377 goto destroy_pcq; 2378 2379 txr->txr_tail = I40E_QTX_TAIL(qid); 2380 txr->txr_qid = qid; 2381 txr->txr_sc = sc; 2382 mutex_init(&txr->txr_lock, MUTEX_DEFAULT, IPL_NET); 2383 2384 return txr; 2385 2386 destroy_pcq: 2387 pcq_destroy(txr->txr_intrq); 2388 uncreate: 2389 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2390 txm = &maps[i]; 2391 2392 if (txm->txm_map == NULL) 2393 continue; 2394 2395 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2396 } 2397 2398 ixl_dmamem_free(sc, &txr->txr_mem); 2399 free: 2400 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2401 kmem_free(txr, sizeof(*txr)); 2402 2403 return NULL; 2404 } 2405 2406 static void 2407 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2408 { 2409 unsigned int qid; 2410 bus_size_t reg; 2411 uint32_t r; 2412 2413 qid = txr->txr_qid + sc->sc_base_queue; 2414 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2415 qid %= 128; 2416 2417 r = ixl_rd(sc, reg); 2418 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2419 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2420 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2421 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2422 ixl_wr(sc, reg, r); 2423 } 2424 2425 static void 2426 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2427 { 2428 struct ixl_hmc_txq txq; 2429 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2430 void *hmc; 2431 2432 memset(&txq, 0, sizeof(txq)); 2433 txq.head = htole16(txr->txr_cons); 2434 txq.new_context = 1; 2435 txq.base = htole64(IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2436 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2437 txq.qlen = htole16(sc->sc_tx_ring_ndescs); 2438 txq.tphrdesc_ena = 0; 2439 txq.tphrpacket_ena = 0; 2440 txq.tphwdesc_ena = 0; 2441 txq.rdylist = data->qs_handle[0]; 2442 2443 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2444 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2445 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, 2446 __arraycount(ixl_hmc_pack_txq)); 2447 } 2448 2449 static void 2450 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2451 { 2452 void *hmc; 2453 2454 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2455 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2456 txr->txr_cons = txr->txr_prod = 0; 2457 } 2458 2459 static void 2460 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2461 { 2462 struct ixl_tx_map *maps, *txm; 2463 bus_dmamap_t map; 2464 unsigned int i; 2465 2466 maps = txr->txr_maps; 2467 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2468 txm = &maps[i]; 2469 2470 if (txm->txm_m == NULL) 2471 continue; 2472 2473 map = txm->txm_map; 2474 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2475 BUS_DMASYNC_POSTWRITE); 2476 bus_dmamap_unload(sc->sc_dmat, map); 2477 2478 m_freem(txm->txm_m); 2479 txm->txm_m = NULL; 2480 } 2481 } 2482 2483 static int 2484 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2485 { 2486 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2487 uint32_t reg; 2488 int i; 2489 2490 for (i = 0; i < 10; i++) { 2491 reg = ixl_rd(sc, ena); 2492 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2493 return 0; 2494 2495 delaymsec(10); 2496 } 2497 2498 return ETIMEDOUT; 2499 } 2500 2501 static int 2502 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2503 { 2504 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2505 uint32_t reg; 2506 int i; 2507 2508 KASSERT(mutex_owned(&txr->txr_lock)); 2509 2510 for (i = 0; i < 10; i++) { 2511 reg = ixl_rd(sc, ena); 2512 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2513 return 0; 2514 2515 delaymsec(10); 2516 } 2517 2518 return ETIMEDOUT; 2519 } 2520 2521 static void 2522 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2523 { 2524 struct ixl_tx_map *maps, *txm; 2525 struct mbuf *m; 2526 unsigned int i; 2527 2528 softint_disestablish(txr->txr_si); 2529 while ((m = pcq_get(txr->txr_intrq)) != NULL) 2530 m_freem(m); 2531 pcq_destroy(txr->txr_intrq); 2532 2533 maps = txr->txr_maps; 2534 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2535 txm = &maps[i]; 2536 2537 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2538 } 2539 2540 ixl_dmamem_free(sc, &txr->txr_mem); 2541 mutex_destroy(&txr->txr_lock); 2542 kmem_free(maps, sizeof(maps[0]) * sc->sc_tx_ring_ndescs); 2543 kmem_free(txr, sizeof(*txr)); 2544 } 2545 2546 static inline int 2547 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf **m0, 2548 struct ixl_tx_ring *txr) 2549 { 2550 struct mbuf *m; 2551 int error; 2552 2553 KASSERT(mutex_owned(&txr->txr_lock)); 2554 2555 m = *m0; 2556 2557 error = bus_dmamap_load_mbuf(dmat, map, m, 2558 BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2559 if (error != EFBIG) 2560 return error; 2561 2562 m = m_defrag(m, M_DONTWAIT); 2563 if (m != NULL) { 2564 *m0 = m; 2565 txr->txr_defragged.ev_count++; 2566 2567 error = bus_dmamap_load_mbuf(dmat, map, m, 2568 BUS_DMA_STREAMING | BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2569 } else { 2570 txr->txr_defrag_failed.ev_count++; 2571 error = ENOBUFS; 2572 } 2573 2574 return error; 2575 } 2576 2577 static inline int 2578 ixl_tx_setup_offloads(struct mbuf *m, uint64_t *cmd_txd) 2579 { 2580 struct ether_header *eh; 2581 size_t len; 2582 uint64_t cmd; 2583 2584 cmd = 0; 2585 2586 eh = mtod(m, struct ether_header *); 2587 switch (htons(eh->ether_type)) { 2588 case ETHERTYPE_IP: 2589 case ETHERTYPE_IPV6: 2590 len = ETHER_HDR_LEN; 2591 break; 2592 case ETHERTYPE_VLAN: 2593 len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2594 break; 2595 default: 2596 len = 0; 2597 } 2598 cmd |= ((len >> 1) << IXL_TX_DESC_MACLEN_SHIFT); 2599 2600 if (m->m_pkthdr.csum_flags & 2601 (M_CSUM_TSOv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 2602 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4; 2603 } 2604 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2605 cmd |= IXL_TX_DESC_CMD_IIPT_IPV4_CSUM; 2606 } 2607 2608 if (m->m_pkthdr.csum_flags & 2609 (M_CSUM_TSOv6 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 2610 cmd |= IXL_TX_DESC_CMD_IIPT_IPV6; 2611 } 2612 2613 switch (cmd & IXL_TX_DESC_CMD_IIPT_MASK) { 2614 case IXL_TX_DESC_CMD_IIPT_IPV4: 2615 case IXL_TX_DESC_CMD_IIPT_IPV4_CSUM: 2616 len = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2617 break; 2618 case IXL_TX_DESC_CMD_IIPT_IPV6: 2619 len = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2620 break; 2621 default: 2622 len = 0; 2623 } 2624 cmd |= ((len >> 2) << IXL_TX_DESC_IPLEN_SHIFT); 2625 2626 if (m->m_pkthdr.csum_flags & 2627 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | M_CSUM_TCPv4 | M_CSUM_TCPv6)) { 2628 len = sizeof(struct tcphdr); 2629 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_TCP; 2630 } else if (m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) { 2631 len = sizeof(struct udphdr); 2632 cmd |= IXL_TX_DESC_CMD_L4T_EOFT_UDP; 2633 } else { 2634 len = 0; 2635 } 2636 cmd |= ((len >> 2) << IXL_TX_DESC_L4LEN_SHIFT); 2637 2638 *cmd_txd |= cmd; 2639 return 0; 2640 } 2641 2642 static void 2643 ixl_tx_common_locked(struct ifnet *ifp, struct ixl_tx_ring *txr, 2644 bool is_transmit) 2645 { 2646 struct ixl_softc *sc = ifp->if_softc; 2647 struct ixl_tx_desc *ring, *txd; 2648 struct ixl_tx_map *txm; 2649 bus_dmamap_t map; 2650 struct mbuf *m; 2651 uint64_t cmd, cmd_txd; 2652 unsigned int prod, free, last, i; 2653 unsigned int mask; 2654 int post = 0; 2655 2656 KASSERT(mutex_owned(&txr->txr_lock)); 2657 2658 if (!ISSET(ifp->if_flags, IFF_RUNNING) 2659 || (!is_transmit && ISSET(ifp->if_flags, IFF_OACTIVE))) { 2660 if (!is_transmit) 2661 IFQ_PURGE(&ifp->if_snd); 2662 return; 2663 } 2664 2665 prod = txr->txr_prod; 2666 free = txr->txr_cons; 2667 if (free <= prod) 2668 free += sc->sc_tx_ring_ndescs; 2669 free -= prod; 2670 2671 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2672 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2673 2674 ring = IXL_DMA_KVA(&txr->txr_mem); 2675 mask = sc->sc_tx_ring_ndescs - 1; 2676 last = prod; 2677 cmd = 0; 2678 txd = NULL; 2679 2680 for (;;) { 2681 if (free <= IXL_TX_PKT_DESCS) { 2682 if (!is_transmit) 2683 SET(ifp->if_flags, IFF_OACTIVE); 2684 break; 2685 } 2686 2687 if (is_transmit) 2688 m = pcq_get(txr->txr_intrq); 2689 else 2690 IFQ_DEQUEUE(&ifp->if_snd, m); 2691 2692 if (m == NULL) 2693 break; 2694 2695 txm = &txr->txr_maps[prod]; 2696 map = txm->txm_map; 2697 2698 if (ixl_load_mbuf(sc->sc_dmat, map, &m, txr) != 0) { 2699 if_statinc(ifp, if_oerrors); 2700 m_freem(m); 2701 continue; 2702 } 2703 2704 cmd_txd = 0; 2705 if (m->m_pkthdr.csum_flags & IXL_CSUM_ALL_OFFLOAD) { 2706 ixl_tx_setup_offloads(m, &cmd_txd); 2707 } 2708 2709 if (vlan_has_tag(m)) { 2710 cmd_txd |= (uint64_t)vlan_get_tag(m) << 2711 IXL_TX_DESC_L2TAG1_SHIFT; 2712 cmd_txd |= IXL_TX_DESC_CMD_IL2TAG1; 2713 } 2714 2715 bus_dmamap_sync(sc->sc_dmat, map, 0, 2716 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2717 2718 for (i = 0; i < (unsigned int)map->dm_nsegs; i++) { 2719 txd = &ring[prod]; 2720 2721 cmd = (uint64_t)map->dm_segs[i].ds_len << 2722 IXL_TX_DESC_BSIZE_SHIFT; 2723 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2724 cmd |= cmd_txd; 2725 2726 txd->addr = htole64(map->dm_segs[i].ds_addr); 2727 txd->cmd = htole64(cmd); 2728 2729 last = prod; 2730 2731 prod++; 2732 prod &= mask; 2733 } 2734 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2735 txd->cmd = htole64(cmd); 2736 2737 txm->txm_m = m; 2738 txm->txm_eop = last; 2739 2740 bpf_mtap(ifp, m, BPF_D_OUT); 2741 2742 free -= i; 2743 post = 1; 2744 } 2745 2746 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2747 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2748 2749 if (post) { 2750 txr->txr_prod = prod; 2751 ixl_wr(sc, txr->txr_tail, prod); 2752 } 2753 } 2754 2755 static int 2756 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr, u_int txlimit) 2757 { 2758 struct ifnet *ifp = &sc->sc_ec.ec_if; 2759 struct ixl_tx_desc *ring, *txd; 2760 struct ixl_tx_map *txm; 2761 struct mbuf *m; 2762 bus_dmamap_t map; 2763 unsigned int cons, prod, last; 2764 unsigned int mask; 2765 uint64_t dtype; 2766 int done = 0, more = 0; 2767 2768 KASSERT(mutex_owned(&txr->txr_lock)); 2769 2770 prod = txr->txr_prod; 2771 cons = txr->txr_cons; 2772 2773 if (cons == prod) 2774 return 0; 2775 2776 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2777 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2778 2779 ring = IXL_DMA_KVA(&txr->txr_mem); 2780 mask = sc->sc_tx_ring_ndescs - 1; 2781 2782 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2783 2784 do { 2785 if (txlimit-- <= 0) { 2786 more = 1; 2787 break; 2788 } 2789 2790 txm = &txr->txr_maps[cons]; 2791 last = txm->txm_eop; 2792 txd = &ring[last]; 2793 2794 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2795 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2796 break; 2797 2798 map = txm->txm_map; 2799 2800 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2801 BUS_DMASYNC_POSTWRITE); 2802 bus_dmamap_unload(sc->sc_dmat, map); 2803 2804 m = txm->txm_m; 2805 if (m != NULL) { 2806 if_statinc_ref(nsr, if_opackets); 2807 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2808 if (ISSET(m->m_flags, M_MCAST)) 2809 if_statinc_ref(nsr, if_omcasts); 2810 m_freem(m); 2811 } 2812 2813 txm->txm_m = NULL; 2814 txm->txm_eop = -1; 2815 2816 cons = last + 1; 2817 cons &= mask; 2818 done = 1; 2819 } while (cons != prod); 2820 2821 IF_STAT_PUTREF(ifp); 2822 2823 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2824 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2825 2826 txr->txr_cons = cons; 2827 2828 if (done) { 2829 softint_schedule(txr->txr_si); 2830 if (txr->txr_qid == 0) { 2831 CLR(ifp->if_flags, IFF_OACTIVE); 2832 if_schedule_deferred_start(ifp); 2833 } 2834 } 2835 2836 return more; 2837 } 2838 2839 static void 2840 ixl_start(struct ifnet *ifp) 2841 { 2842 struct ixl_softc *sc; 2843 struct ixl_tx_ring *txr; 2844 2845 sc = ifp->if_softc; 2846 txr = sc->sc_qps[0].qp_txr; 2847 2848 mutex_enter(&txr->txr_lock); 2849 ixl_tx_common_locked(ifp, txr, false); 2850 mutex_exit(&txr->txr_lock); 2851 } 2852 2853 static inline unsigned int 2854 ixl_select_txqueue(struct ixl_softc *sc, struct mbuf *m) 2855 { 2856 u_int cpuid; 2857 2858 cpuid = cpu_index(curcpu()); 2859 2860 return (unsigned int)(cpuid % sc->sc_nqueue_pairs); 2861 } 2862 2863 static int 2864 ixl_transmit(struct ifnet *ifp, struct mbuf *m) 2865 { 2866 struct ixl_softc *sc; 2867 struct ixl_tx_ring *txr; 2868 unsigned int qid; 2869 2870 sc = ifp->if_softc; 2871 qid = ixl_select_txqueue(sc, m); 2872 2873 txr = sc->sc_qps[qid].qp_txr; 2874 2875 if (__predict_false(!pcq_put(txr->txr_intrq, m))) { 2876 mutex_enter(&txr->txr_lock); 2877 txr->txr_pcqdrop.ev_count++; 2878 mutex_exit(&txr->txr_lock); 2879 2880 m_freem(m); 2881 return ENOBUFS; 2882 } 2883 2884 if (mutex_tryenter(&txr->txr_lock)) { 2885 ixl_tx_common_locked(ifp, txr, true); 2886 mutex_exit(&txr->txr_lock); 2887 } else { 2888 kpreempt_disable(); 2889 softint_schedule(txr->txr_si); 2890 kpreempt_enable(); 2891 } 2892 2893 return 0; 2894 } 2895 2896 static void 2897 ixl_deferred_transmit(void *xtxr) 2898 { 2899 struct ixl_tx_ring *txr = xtxr; 2900 struct ixl_softc *sc = txr->txr_sc; 2901 struct ifnet *ifp = &sc->sc_ec.ec_if; 2902 2903 mutex_enter(&txr->txr_lock); 2904 txr->txr_transmitdef.ev_count++; 2905 if (pcq_peek(txr->txr_intrq) != NULL) 2906 ixl_tx_common_locked(ifp, txr, true); 2907 mutex_exit(&txr->txr_lock); 2908 } 2909 2910 static struct ixl_rx_ring * 2911 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 2912 { 2913 struct ixl_rx_ring *rxr = NULL; 2914 struct ixl_rx_map *maps = NULL, *rxm; 2915 unsigned int i; 2916 2917 rxr = kmem_zalloc(sizeof(*rxr), KM_SLEEP); 2918 maps = kmem_zalloc(sizeof(maps[0]) * sc->sc_rx_ring_ndescs, 2919 KM_SLEEP); 2920 2921 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 2922 sizeof(struct ixl_rx_rd_desc_32) * sc->sc_rx_ring_ndescs, 2923 IXL_RX_QUEUE_ALIGN) != 0) 2924 goto free; 2925 2926 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2927 rxm = &maps[i]; 2928 2929 if (bus_dmamap_create(sc->sc_dmat, 2930 IXL_MCLBYTES, 1, IXL_MCLBYTES, 0, 2931 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &rxm->rxm_map) != 0) 2932 goto uncreate; 2933 2934 rxm->rxm_m = NULL; 2935 } 2936 2937 rxr->rxr_cons = rxr->rxr_prod = 0; 2938 rxr->rxr_m_head = NULL; 2939 rxr->rxr_m_tail = &rxr->rxr_m_head; 2940 rxr->rxr_maps = maps; 2941 2942 rxr->rxr_tail = I40E_QRX_TAIL(qid); 2943 rxr->rxr_qid = qid; 2944 mutex_init(&rxr->rxr_lock, MUTEX_DEFAULT, IPL_NET); 2945 2946 return rxr; 2947 2948 uncreate: 2949 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2950 rxm = &maps[i]; 2951 2952 if (rxm->rxm_map == NULL) 2953 continue; 2954 2955 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 2956 } 2957 2958 ixl_dmamem_free(sc, &rxr->rxr_mem); 2959 free: 2960 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 2961 kmem_free(rxr, sizeof(*rxr)); 2962 2963 return NULL; 2964 } 2965 2966 static void 2967 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 2968 { 2969 struct ixl_rx_map *maps, *rxm; 2970 bus_dmamap_t map; 2971 unsigned int i; 2972 2973 maps = rxr->rxr_maps; 2974 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2975 rxm = &maps[i]; 2976 2977 if (rxm->rxm_m == NULL) 2978 continue; 2979 2980 map = rxm->rxm_map; 2981 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2982 BUS_DMASYNC_POSTWRITE); 2983 bus_dmamap_unload(sc->sc_dmat, map); 2984 2985 m_freem(rxm->rxm_m); 2986 rxm->rxm_m = NULL; 2987 } 2988 2989 m_freem(rxr->rxr_m_head); 2990 rxr->rxr_m_head = NULL; 2991 rxr->rxr_m_tail = &rxr->rxr_m_head; 2992 2993 rxr->rxr_prod = rxr->rxr_cons = 0; 2994 } 2995 2996 static int 2997 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 2998 { 2999 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3000 uint32_t reg; 3001 int i; 3002 3003 for (i = 0; i < 10; i++) { 3004 reg = ixl_rd(sc, ena); 3005 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3006 return 0; 3007 3008 delaymsec(10); 3009 } 3010 3011 return ETIMEDOUT; 3012 } 3013 3014 static int 3015 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3016 { 3017 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3018 uint32_t reg; 3019 int i; 3020 3021 KASSERT(mutex_owned(&rxr->rxr_lock)); 3022 3023 for (i = 0; i < 10; i++) { 3024 reg = ixl_rd(sc, ena); 3025 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3026 return 0; 3027 3028 delaymsec(10); 3029 } 3030 3031 return ETIMEDOUT; 3032 } 3033 3034 static void 3035 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3036 { 3037 struct ixl_hmc_rxq rxq; 3038 struct ifnet *ifp = &sc->sc_ec.ec_if; 3039 uint16_t rxmax; 3040 void *hmc; 3041 3042 memset(&rxq, 0, sizeof(rxq)); 3043 rxmax = ifp->if_mtu + IXL_MTU_ETHERLEN; 3044 3045 rxq.head = htole16(rxr->rxr_cons); 3046 rxq.base = htole64(IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3047 rxq.qlen = htole16(sc->sc_rx_ring_ndescs); 3048 rxq.dbuff = htole16(IXL_MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3049 rxq.hbuff = 0; 3050 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3051 rxq.dsize = IXL_HMC_RXQ_DSIZE_32; 3052 rxq.crcstrip = 1; 3053 rxq.l2sel = 1; 3054 rxq.showiv = 1; 3055 rxq.rxmax = htole16(rxmax); 3056 rxq.tphrdesc_ena = 0; 3057 rxq.tphwdesc_ena = 0; 3058 rxq.tphdata_ena = 0; 3059 rxq.tphhead_ena = 0; 3060 rxq.lrxqthresh = 0; 3061 rxq.prefena = 1; 3062 3063 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3064 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3065 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, 3066 __arraycount(ixl_hmc_pack_rxq)); 3067 } 3068 3069 static void 3070 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3071 { 3072 void *hmc; 3073 3074 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3075 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3076 rxr->rxr_cons = rxr->rxr_prod = 0; 3077 } 3078 3079 static void 3080 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3081 { 3082 struct ixl_rx_map *maps, *rxm; 3083 unsigned int i; 3084 3085 maps = rxr->rxr_maps; 3086 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3087 rxm = &maps[i]; 3088 3089 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3090 } 3091 3092 ixl_dmamem_free(sc, &rxr->rxr_mem); 3093 mutex_destroy(&rxr->rxr_lock); 3094 kmem_free(maps, sizeof(maps[0]) * sc->sc_rx_ring_ndescs); 3095 kmem_free(rxr, sizeof(*rxr)); 3096 } 3097 3098 static inline void 3099 ixl_rx_csum(struct mbuf *m, uint64_t qword) 3100 { 3101 int flags_mask; 3102 3103 if (!ISSET(qword, IXL_RX_DESC_L3L4P)) { 3104 /* No L3 or L4 checksum was calculated */ 3105 return; 3106 } 3107 3108 switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) { 3109 case IXL_RX_DESC_PTYPE_IPV4FRAG: 3110 case IXL_RX_DESC_PTYPE_IPV4: 3111 case IXL_RX_DESC_PTYPE_SCTPV4: 3112 case IXL_RX_DESC_PTYPE_ICMPV4: 3113 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3114 break; 3115 case IXL_RX_DESC_PTYPE_TCPV4: 3116 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3117 flags_mask |= M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD; 3118 break; 3119 case IXL_RX_DESC_PTYPE_UDPV4: 3120 flags_mask = M_CSUM_IPv4 | M_CSUM_IPv4_BAD; 3121 flags_mask |= M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD; 3122 break; 3123 case IXL_RX_DESC_PTYPE_TCPV6: 3124 flags_mask = M_CSUM_TCPv6 | M_CSUM_TCP_UDP_BAD; 3125 break; 3126 case IXL_RX_DESC_PTYPE_UDPV6: 3127 flags_mask = M_CSUM_UDPv6 | M_CSUM_TCP_UDP_BAD; 3128 break; 3129 default: 3130 flags_mask = 0; 3131 } 3132 3133 m->m_pkthdr.csum_flags |= (flags_mask & (M_CSUM_IPv4 | 3134 M_CSUM_TCPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv4 | M_CSUM_UDPv6)); 3135 3136 if (ISSET(qword, IXL_RX_DESC_IPE)) { 3137 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_IPv4_BAD); 3138 } 3139 3140 if (ISSET(qword, IXL_RX_DESC_L4E)) { 3141 m->m_pkthdr.csum_flags |= (flags_mask & M_CSUM_TCP_UDP_BAD); 3142 } 3143 } 3144 3145 static int 3146 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr, u_int rxlimit) 3147 { 3148 struct ifnet *ifp = &sc->sc_ec.ec_if; 3149 struct ixl_rx_wb_desc_32 *ring, *rxd; 3150 struct ixl_rx_map *rxm; 3151 bus_dmamap_t map; 3152 unsigned int cons, prod; 3153 struct mbuf *m; 3154 uint64_t word, word0; 3155 unsigned int len; 3156 unsigned int mask; 3157 int done = 0, more = 0; 3158 3159 KASSERT(mutex_owned(&rxr->rxr_lock)); 3160 3161 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3162 return 0; 3163 3164 prod = rxr->rxr_prod; 3165 cons = rxr->rxr_cons; 3166 3167 if (cons == prod) 3168 return 0; 3169 3170 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3171 0, IXL_DMA_LEN(&rxr->rxr_mem), 3172 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3173 3174 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3175 mask = sc->sc_rx_ring_ndescs - 1; 3176 3177 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 3178 3179 do { 3180 if (rxlimit-- <= 0) { 3181 more = 1; 3182 break; 3183 } 3184 3185 rxd = &ring[cons]; 3186 3187 word = le64toh(rxd->qword1); 3188 3189 if (!ISSET(word, IXL_RX_DESC_DD)) 3190 break; 3191 3192 rxm = &rxr->rxr_maps[cons]; 3193 3194 map = rxm->rxm_map; 3195 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3196 BUS_DMASYNC_POSTREAD); 3197 bus_dmamap_unload(sc->sc_dmat, map); 3198 3199 m = rxm->rxm_m; 3200 rxm->rxm_m = NULL; 3201 3202 KASSERT(m != NULL); 3203 3204 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3205 m->m_len = len; 3206 m->m_pkthdr.len = 0; 3207 3208 m->m_next = NULL; 3209 *rxr->rxr_m_tail = m; 3210 rxr->rxr_m_tail = &m->m_next; 3211 3212 m = rxr->rxr_m_head; 3213 m->m_pkthdr.len += len; 3214 3215 if (ISSET(word, IXL_RX_DESC_EOP)) { 3216 word0 = le64toh(rxd->qword0); 3217 3218 if (ISSET(word, IXL_RX_DESC_L2TAG1P)) { 3219 vlan_set_tag(m, 3220 __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK)); 3221 } 3222 3223 if ((ifp->if_capenable & IXL_IFCAP_RXCSUM) != 0) 3224 ixl_rx_csum(m, word); 3225 3226 if (!ISSET(word, 3227 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3228 m_set_rcvif(m, ifp); 3229 if_statinc_ref(nsr, if_ipackets); 3230 if_statadd_ref(nsr, if_ibytes, 3231 m->m_pkthdr.len); 3232 if_percpuq_enqueue(sc->sc_ipq, m); 3233 } else { 3234 if_statinc_ref(nsr, if_ierrors); 3235 m_freem(m); 3236 } 3237 3238 rxr->rxr_m_head = NULL; 3239 rxr->rxr_m_tail = &rxr->rxr_m_head; 3240 } 3241 3242 cons++; 3243 cons &= mask; 3244 3245 done = 1; 3246 } while (cons != prod); 3247 3248 if (done) { 3249 rxr->rxr_cons = cons; 3250 if (ixl_rxfill(sc, rxr) == -1) 3251 if_statinc_ref(nsr, if_iqdrops); 3252 } 3253 3254 IF_STAT_PUTREF(ifp); 3255 3256 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3257 0, IXL_DMA_LEN(&rxr->rxr_mem), 3258 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3259 3260 return more; 3261 } 3262 3263 static int 3264 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3265 { 3266 struct ixl_rx_rd_desc_32 *ring, *rxd; 3267 struct ixl_rx_map *rxm; 3268 bus_dmamap_t map; 3269 struct mbuf *m; 3270 unsigned int prod; 3271 unsigned int slots; 3272 unsigned int mask; 3273 int post = 0, error = 0; 3274 3275 KASSERT(mutex_owned(&rxr->rxr_lock)); 3276 3277 prod = rxr->rxr_prod; 3278 slots = ixl_rxr_unrefreshed(rxr->rxr_prod, rxr->rxr_cons, 3279 sc->sc_rx_ring_ndescs); 3280 3281 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3282 mask = sc->sc_rx_ring_ndescs - 1; 3283 3284 if (__predict_false(slots <= 0)) 3285 return -1; 3286 3287 do { 3288 rxm = &rxr->rxr_maps[prod]; 3289 3290 MGETHDR(m, M_DONTWAIT, MT_DATA); 3291 if (m == NULL) { 3292 rxr->rxr_mgethdr_failed.ev_count++; 3293 error = -1; 3294 break; 3295 } 3296 3297 MCLGET(m, M_DONTWAIT); 3298 if (!ISSET(m->m_flags, M_EXT)) { 3299 rxr->rxr_mgetcl_failed.ev_count++; 3300 error = -1; 3301 m_freem(m); 3302 break; 3303 } 3304 3305 m->m_len = m->m_pkthdr.len = MCLBYTES; 3306 m_adj(m, ETHER_ALIGN); 3307 3308 map = rxm->rxm_map; 3309 3310 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3311 BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 3312 rxr->rxr_mbuf_load_failed.ev_count++; 3313 error = -1; 3314 m_freem(m); 3315 break; 3316 } 3317 3318 rxm->rxm_m = m; 3319 3320 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3321 BUS_DMASYNC_PREREAD); 3322 3323 rxd = &ring[prod]; 3324 3325 rxd->paddr = htole64(map->dm_segs[0].ds_addr); 3326 rxd->haddr = htole64(0); 3327 3328 prod++; 3329 prod &= mask; 3330 3331 post = 1; 3332 3333 } while (--slots); 3334 3335 if (post) { 3336 rxr->rxr_prod = prod; 3337 ixl_wr(sc, rxr->rxr_tail, prod); 3338 } 3339 3340 return error; 3341 } 3342 3343 static inline int 3344 ixl_handle_queue_common(struct ixl_softc *sc, struct ixl_queue_pair *qp, 3345 u_int txlimit, struct evcnt *txevcnt, 3346 u_int rxlimit, struct evcnt *rxevcnt) 3347 { 3348 struct ixl_tx_ring *txr = qp->qp_txr; 3349 struct ixl_rx_ring *rxr = qp->qp_rxr; 3350 int txmore, rxmore; 3351 int rv; 3352 3353 mutex_enter(&txr->txr_lock); 3354 txevcnt->ev_count++; 3355 txmore = ixl_txeof(sc, txr, txlimit); 3356 mutex_exit(&txr->txr_lock); 3357 3358 mutex_enter(&rxr->rxr_lock); 3359 rxevcnt->ev_count++; 3360 rxmore = ixl_rxeof(sc, rxr, rxlimit); 3361 mutex_exit(&rxr->rxr_lock); 3362 3363 rv = txmore | (rxmore << 1); 3364 3365 return rv; 3366 } 3367 3368 static void 3369 ixl_sched_handle_queue(struct ixl_softc *sc, struct ixl_queue_pair *qp) 3370 { 3371 3372 if (qp->qp_workqueue) 3373 workqueue_enqueue(sc->sc_workq_txrx, &qp->qp_work, NULL); 3374 else 3375 softint_schedule(qp->qp_si); 3376 } 3377 3378 static int 3379 ixl_intr(void *xsc) 3380 { 3381 struct ixl_softc *sc = xsc; 3382 struct ixl_tx_ring *txr; 3383 struct ixl_rx_ring *rxr; 3384 uint32_t icr, rxintr, txintr; 3385 int rv = 0; 3386 unsigned int i; 3387 3388 KASSERT(sc != NULL); 3389 3390 ixl_enable_other_intr(sc); 3391 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3392 3393 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3394 atomic_inc_64(&sc->sc_event_atq.ev_count); 3395 ixl_atq_done(sc); 3396 ixl_work_add(sc->sc_workq, &sc->sc_arq_task); 3397 rv = 1; 3398 } 3399 3400 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3401 atomic_inc_64(&sc->sc_event_link.ev_count); 3402 ixl_work_add(sc->sc_workq, &sc->sc_link_state_task); 3403 rv = 1; 3404 } 3405 3406 rxintr = icr & I40E_INTR_NOTX_RX_MASK; 3407 txintr = icr & I40E_INTR_NOTX_TX_MASK; 3408 3409 if (txintr || rxintr) { 3410 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 3411 txr = sc->sc_qps[i].qp_txr; 3412 rxr = sc->sc_qps[i].qp_rxr; 3413 3414 ixl_handle_queue_common(sc, &sc->sc_qps[i], 3415 IXL_TXRX_PROCESS_UNLIMIT, &txr->txr_intr, 3416 IXL_TXRX_PROCESS_UNLIMIT, &rxr->rxr_intr); 3417 } 3418 rv = 1; 3419 } 3420 3421 return rv; 3422 } 3423 3424 static int 3425 ixl_queue_intr(void *xqp) 3426 { 3427 struct ixl_queue_pair *qp = xqp; 3428 struct ixl_tx_ring *txr = qp->qp_txr; 3429 struct ixl_rx_ring *rxr = qp->qp_rxr; 3430 struct ixl_softc *sc = qp->qp_sc; 3431 u_int txlimit, rxlimit; 3432 int more; 3433 3434 txlimit = sc->sc_tx_intr_process_limit; 3435 rxlimit = sc->sc_rx_intr_process_limit; 3436 qp->qp_workqueue = sc->sc_txrx_workqueue; 3437 3438 more = ixl_handle_queue_common(sc, qp, 3439 txlimit, &txr->txr_intr, rxlimit, &rxr->rxr_intr); 3440 3441 if (more != 0) { 3442 ixl_sched_handle_queue(sc, qp); 3443 } else { 3444 /* for ALTQ */ 3445 if (txr->txr_qid == 0) 3446 if_schedule_deferred_start(&sc->sc_ec.ec_if); 3447 softint_schedule(txr->txr_si); 3448 3449 ixl_enable_queue_intr(sc, qp); 3450 } 3451 3452 return 1; 3453 } 3454 3455 static void 3456 ixl_handle_queue_wk(struct work *wk, void *xsc) 3457 { 3458 struct ixl_queue_pair *qp; 3459 3460 qp = container_of(wk, struct ixl_queue_pair, qp_work); 3461 ixl_handle_queue(qp); 3462 } 3463 3464 static void 3465 ixl_handle_queue(void *xqp) 3466 { 3467 struct ixl_queue_pair *qp = xqp; 3468 struct ixl_softc *sc = qp->qp_sc; 3469 struct ixl_tx_ring *txr = qp->qp_txr; 3470 struct ixl_rx_ring *rxr = qp->qp_rxr; 3471 u_int txlimit, rxlimit; 3472 int more; 3473 3474 txlimit = sc->sc_tx_process_limit; 3475 rxlimit = sc->sc_rx_process_limit; 3476 3477 more = ixl_handle_queue_common(sc, qp, 3478 txlimit, &txr->txr_defer, rxlimit, &rxr->rxr_defer); 3479 3480 if (more != 0) 3481 ixl_sched_handle_queue(sc, qp); 3482 else 3483 ixl_enable_queue_intr(sc, qp); 3484 } 3485 3486 static inline void 3487 ixl_print_hmc_error(struct ixl_softc *sc, uint32_t reg) 3488 { 3489 uint32_t hmc_idx, hmc_isvf; 3490 uint32_t hmc_errtype, hmc_objtype, hmc_data; 3491 3492 hmc_idx = reg & I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK; 3493 hmc_idx = hmc_idx >> I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT; 3494 hmc_isvf = reg & I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK; 3495 hmc_isvf = hmc_isvf >> I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT; 3496 hmc_errtype = reg & I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK; 3497 hmc_errtype = hmc_errtype >> I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT; 3498 hmc_objtype = reg & I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK; 3499 hmc_objtype = hmc_objtype >> I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT; 3500 hmc_data = ixl_rd(sc, I40E_PFHMC_ERRORDATA); 3501 3502 device_printf(sc->sc_dev, 3503 "HMC Error (idx=0x%x, isvf=0x%x, err=0x%x, obj=0x%x, data=0x%x)\n", 3504 hmc_idx, hmc_isvf, hmc_errtype, hmc_objtype, hmc_data); 3505 } 3506 3507 static int 3508 ixl_other_intr(void *xsc) 3509 { 3510 struct ixl_softc *sc = xsc; 3511 uint32_t icr, mask, reg; 3512 int rv; 3513 3514 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3515 mask = ixl_rd(sc, I40E_PFINT_ICR0_ENA); 3516 3517 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3518 atomic_inc_64(&sc->sc_event_atq.ev_count); 3519 ixl_atq_done(sc); 3520 ixl_work_add(sc->sc_workq, &sc->sc_arq_task); 3521 rv = 1; 3522 } 3523 3524 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3525 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3526 device_printf(sc->sc_dev, "link stat changed\n"); 3527 3528 atomic_inc_64(&sc->sc_event_link.ev_count); 3529 ixl_work_add(sc->sc_workq, &sc->sc_link_state_task); 3530 rv = 1; 3531 } 3532 3533 if (ISSET(icr, I40E_PFINT_ICR0_GRST_MASK)) { 3534 CLR(mask, I40E_PFINT_ICR0_ENA_GRST_MASK); 3535 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 3536 reg = reg & I40E_GLGEN_RSTAT_RESET_TYPE_MASK; 3537 reg = reg >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; 3538 3539 device_printf(sc->sc_dev, "GRST: %s\n", 3540 reg == I40E_RESET_CORER ? "CORER" : 3541 reg == I40E_RESET_GLOBR ? "GLOBR" : 3542 reg == I40E_RESET_EMPR ? "EMPR" : 3543 "POR"); 3544 } 3545 3546 if (ISSET(icr, I40E_PFINT_ICR0_ECC_ERR_MASK)) 3547 atomic_inc_64(&sc->sc_event_ecc_err.ev_count); 3548 if (ISSET(icr, I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)) 3549 atomic_inc_64(&sc->sc_event_pci_exception.ev_count); 3550 if (ISSET(icr, I40E_PFINT_ICR0_PE_CRITERR_MASK)) 3551 atomic_inc_64(&sc->sc_event_crit_err.ev_count); 3552 3553 if (ISSET(icr, IXL_ICR0_CRIT_ERR_MASK)) { 3554 CLR(mask, IXL_ICR0_CRIT_ERR_MASK); 3555 device_printf(sc->sc_dev, "critical error\n"); 3556 } 3557 3558 if (ISSET(icr, I40E_PFINT_ICR0_HMC_ERR_MASK)) { 3559 reg = ixl_rd(sc, I40E_PFHMC_ERRORINFO); 3560 if (ISSET(reg, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK)) 3561 ixl_print_hmc_error(sc, reg); 3562 ixl_wr(sc, I40E_PFHMC_ERRORINFO, 0); 3563 } 3564 3565 ixl_wr(sc, I40E_PFINT_ICR0_ENA, mask); 3566 ixl_flush(sc); 3567 ixl_enable_other_intr(sc); 3568 return rv; 3569 } 3570 3571 static void 3572 ixl_get_link_status_done(struct ixl_softc *sc, 3573 const struct ixl_aq_desc *iaq) 3574 { 3575 struct ixl_aq_desc iaq_buf; 3576 3577 memcpy(&iaq_buf, iaq, sizeof(iaq_buf)); 3578 3579 /* 3580 * The lock can be released here 3581 * because there is no post processing about ATQ 3582 */ 3583 mutex_exit(&sc->sc_atq_lock); 3584 ixl_link_state_update(sc, &iaq_buf); 3585 mutex_enter(&sc->sc_atq_lock); 3586 } 3587 3588 static void 3589 ixl_get_link_status(void *xsc) 3590 { 3591 struct ixl_softc *sc = xsc; 3592 struct ixl_aq_desc *iaq; 3593 struct ixl_aq_link_param *param; 3594 int error; 3595 3596 mutex_enter(&sc->sc_atq_lock); 3597 3598 iaq = &sc->sc_link_state_atq.iatq_desc; 3599 memset(iaq, 0, sizeof(*iaq)); 3600 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3601 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3602 param->notify = IXL_AQ_LINK_NOTIFY; 3603 3604 error = ixl_atq_exec_locked(sc, &sc->sc_link_state_atq); 3605 ixl_atq_set(&sc->sc_link_state_atq, ixl_get_link_status_done); 3606 3607 if (error == 0) { 3608 ixl_get_link_status_done(sc, iaq); 3609 } 3610 3611 mutex_exit(&sc->sc_atq_lock); 3612 } 3613 3614 static void 3615 ixl_link_state_update(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3616 { 3617 struct ifnet *ifp = &sc->sc_ec.ec_if; 3618 int link_state; 3619 3620 mutex_enter(&sc->sc_cfg_lock); 3621 link_state = ixl_set_link_status_locked(sc, iaq); 3622 mutex_exit(&sc->sc_cfg_lock); 3623 3624 if (ifp->if_link_state != link_state) 3625 if_link_state_change(ifp, link_state); 3626 3627 if (link_state != LINK_STATE_DOWN) { 3628 kpreempt_disable(); 3629 if_schedule_deferred_start(ifp); 3630 kpreempt_enable(); 3631 } 3632 } 3633 3634 static void 3635 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq, 3636 const char *msg) 3637 { 3638 char buf[512]; 3639 size_t len; 3640 3641 len = sizeof(buf); 3642 buf[--len] = '\0'; 3643 3644 device_printf(sc->sc_dev, "%s\n", msg); 3645 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags)); 3646 device_printf(sc->sc_dev, "flags %s opcode %04x\n", 3647 buf, le16toh(iaq->iaq_opcode)); 3648 device_printf(sc->sc_dev, "datalen %u retval %u\n", 3649 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval)); 3650 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie); 3651 device_printf(sc->sc_dev, "%08x %08x %08x %08x\n", 3652 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]), 3653 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3])); 3654 } 3655 3656 static void 3657 ixl_arq(void *xsc) 3658 { 3659 struct ixl_softc *sc = xsc; 3660 struct ixl_aq_desc *arq, *iaq; 3661 struct ixl_aq_buf *aqb; 3662 unsigned int cons = sc->sc_arq_cons; 3663 unsigned int prod; 3664 int done = 0; 3665 3666 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3667 sc->sc_aq_regs->arq_head_mask; 3668 3669 if (cons == prod) 3670 goto done; 3671 3672 arq = IXL_DMA_KVA(&sc->sc_arq); 3673 3674 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3675 0, IXL_DMA_LEN(&sc->sc_arq), 3676 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3677 3678 do { 3679 iaq = &arq[cons]; 3680 aqb = sc->sc_arq_live[cons]; 3681 3682 KASSERT(aqb != NULL); 3683 3684 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3685 BUS_DMASYNC_POSTREAD); 3686 3687 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3688 ixl_aq_dump(sc, iaq, "arq event"); 3689 3690 switch (iaq->iaq_opcode) { 3691 case htole16(IXL_AQ_OP_PHY_LINK_STATUS): 3692 ixl_link_state_update(sc, iaq); 3693 break; 3694 } 3695 3696 memset(iaq, 0, sizeof(*iaq)); 3697 sc->sc_arq_live[cons] = NULL; 3698 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3699 3700 cons++; 3701 cons &= IXL_AQ_MASK; 3702 3703 done = 1; 3704 } while (cons != prod); 3705 3706 if (done) { 3707 sc->sc_arq_cons = cons; 3708 ixl_arq_fill(sc); 3709 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3710 0, IXL_DMA_LEN(&sc->sc_arq), 3711 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3712 } 3713 3714 done: 3715 ixl_enable_other_intr(sc); 3716 } 3717 3718 static void 3719 ixl_atq_set(struct ixl_atq *iatq, 3720 void (*fn)(struct ixl_softc *, const struct ixl_aq_desc *)) 3721 { 3722 3723 iatq->iatq_fn = fn; 3724 } 3725 3726 static int 3727 ixl_atq_post_locked(struct ixl_softc *sc, struct ixl_atq *iatq) 3728 { 3729 struct ixl_aq_desc *atq, *slot; 3730 unsigned int prod, cons, prod_next; 3731 3732 /* assert locked */ 3733 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3734 3735 atq = IXL_DMA_KVA(&sc->sc_atq); 3736 prod = sc->sc_atq_prod; 3737 cons = sc->sc_atq_cons; 3738 prod_next = (prod +1) & IXL_AQ_MASK; 3739 3740 if (cons == prod_next) 3741 return ENOMEM; 3742 3743 slot = &atq[prod]; 3744 3745 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3746 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3747 3748 KASSERT(iatq->iatq_fn != NULL); 3749 *slot = iatq->iatq_desc; 3750 slot->iaq_cookie = (uint64_t)((intptr_t)iatq); 3751 3752 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3753 ixl_aq_dump(sc, slot, "atq command"); 3754 3755 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3756 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3757 3758 sc->sc_atq_prod = prod_next; 3759 ixl_wr(sc, sc->sc_aq_regs->atq_tail, sc->sc_atq_prod); 3760 3761 return 0; 3762 } 3763 3764 static void 3765 ixl_atq_done_locked(struct ixl_softc *sc) 3766 { 3767 struct ixl_aq_desc *atq, *slot; 3768 struct ixl_atq *iatq; 3769 unsigned int cons; 3770 unsigned int prod; 3771 3772 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3773 3774 prod = sc->sc_atq_prod; 3775 cons = sc->sc_atq_cons; 3776 3777 if (prod == cons) 3778 return; 3779 3780 atq = IXL_DMA_KVA(&sc->sc_atq); 3781 3782 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3783 0, IXL_DMA_LEN(&sc->sc_atq), 3784 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3785 3786 do { 3787 slot = &atq[cons]; 3788 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3789 break; 3790 3791 iatq = (struct ixl_atq *)((intptr_t)slot->iaq_cookie); 3792 iatq->iatq_desc = *slot; 3793 3794 memset(slot, 0, sizeof(*slot)); 3795 3796 if (ISSET(sc->sc_ec.ec_if.if_flags, IFF_DEBUG)) 3797 ixl_aq_dump(sc, &iatq->iatq_desc, "atq response"); 3798 3799 (*iatq->iatq_fn)(sc, &iatq->iatq_desc); 3800 3801 cons++; 3802 cons &= IXL_AQ_MASK; 3803 } while (cons != prod); 3804 3805 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3806 0, IXL_DMA_LEN(&sc->sc_atq), 3807 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3808 3809 sc->sc_atq_cons = cons; 3810 } 3811 3812 static void 3813 ixl_atq_done(struct ixl_softc *sc) 3814 { 3815 3816 mutex_enter(&sc->sc_atq_lock); 3817 ixl_atq_done_locked(sc); 3818 mutex_exit(&sc->sc_atq_lock); 3819 } 3820 3821 static void 3822 ixl_wakeup(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3823 { 3824 3825 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3826 3827 cv_signal(&sc->sc_atq_cv); 3828 } 3829 3830 static int 3831 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq) 3832 { 3833 int error; 3834 3835 mutex_enter(&sc->sc_atq_lock); 3836 error = ixl_atq_exec_locked(sc, iatq); 3837 mutex_exit(&sc->sc_atq_lock); 3838 3839 return error; 3840 } 3841 3842 static int 3843 ixl_atq_exec_locked(struct ixl_softc *sc, struct ixl_atq *iatq) 3844 { 3845 int error; 3846 3847 KASSERT(mutex_owned(&sc->sc_atq_lock)); 3848 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3849 3850 ixl_atq_set(iatq, ixl_wakeup); 3851 3852 error = ixl_atq_post_locked(sc, iatq); 3853 if (error) 3854 return error; 3855 3856 error = cv_timedwait(&sc->sc_atq_cv, &sc->sc_atq_lock, 3857 IXL_ATQ_EXEC_TIMEOUT); 3858 3859 return error; 3860 } 3861 3862 static int 3863 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3864 { 3865 struct ixl_aq_desc *atq, *slot; 3866 unsigned int prod; 3867 unsigned int t = 0; 3868 3869 mutex_enter(&sc->sc_atq_lock); 3870 3871 atq = IXL_DMA_KVA(&sc->sc_atq); 3872 prod = sc->sc_atq_prod; 3873 slot = atq + prod; 3874 3875 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3876 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3877 3878 *slot = *iaq; 3879 slot->iaq_flags |= htole16(IXL_AQ_SI); 3880 3881 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3882 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3883 3884 prod++; 3885 prod &= IXL_AQ_MASK; 3886 sc->sc_atq_prod = prod; 3887 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3888 3889 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3890 delaymsec(1); 3891 3892 if (t++ > tm) { 3893 mutex_exit(&sc->sc_atq_lock); 3894 return ETIMEDOUT; 3895 } 3896 } 3897 3898 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3899 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3900 *iaq = *slot; 3901 memset(slot, 0, sizeof(*slot)); 3902 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3903 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3904 3905 sc->sc_atq_cons = prod; 3906 3907 mutex_exit(&sc->sc_atq_lock); 3908 3909 return 0; 3910 } 3911 3912 static int 3913 ixl_get_version(struct ixl_softc *sc) 3914 { 3915 struct ixl_aq_desc iaq; 3916 uint32_t fwbuild, fwver, apiver; 3917 uint16_t api_maj_ver, api_min_ver; 3918 3919 memset(&iaq, 0, sizeof(iaq)); 3920 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3921 3922 iaq.iaq_retval = le16toh(23); 3923 3924 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 3925 return ETIMEDOUT; 3926 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 3927 return EIO; 3928 3929 fwbuild = le32toh(iaq.iaq_param[1]); 3930 fwver = le32toh(iaq.iaq_param[2]); 3931 apiver = le32toh(iaq.iaq_param[3]); 3932 3933 api_maj_ver = (uint16_t)apiver; 3934 api_min_ver = (uint16_t)(apiver >> 16); 3935 3936 aprint_normal(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 3937 (uint16_t)(fwver >> 16), fwbuild, api_maj_ver, api_min_ver); 3938 3939 if (sc->sc_mac_type == I40E_MAC_X722) { 3940 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK | 3941 IXL_SC_AQ_FLAG_NVMREAD); 3942 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL); 3943 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS); 3944 } 3945 3946 #define IXL_API_VER(maj, min) (((uint32_t)(maj) << 16) | (min)) 3947 if (IXL_API_VER(api_maj_ver, api_min_ver) >= IXL_API_VER(1, 5)) { 3948 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL); 3949 SET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK); 3950 } 3951 #undef IXL_API_VER 3952 3953 return 0; 3954 } 3955 3956 static int 3957 ixl_get_nvm_version(struct ixl_softc *sc) 3958 { 3959 uint16_t nvmver, cfg_ptr, eetrack_hi, eetrack_lo, oem_hi, oem_lo; 3960 uint32_t eetrack, oem; 3961 uint16_t nvm_maj_ver, nvm_min_ver, oem_build; 3962 uint8_t oem_ver, oem_patch; 3963 3964 nvmver = cfg_ptr = eetrack_hi = eetrack_lo = oem_hi = oem_lo = 0; 3965 ixl_rd16_nvm(sc, I40E_SR_NVM_DEV_STARTER_VERSION, &nvmver); 3966 ixl_rd16_nvm(sc, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 3967 ixl_rd16_nvm(sc, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 3968 ixl_rd16_nvm(sc, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); 3969 ixl_rd16_nvm(sc, cfg_ptr + I40E_NVM_OEM_VER_OFF, &oem_hi); 3970 ixl_rd16_nvm(sc, cfg_ptr + I40E_NVM_OEM_VER_OFF + 1, &oem_lo); 3971 3972 nvm_maj_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_HI_MASK); 3973 nvm_min_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_LO_MASK); 3974 eetrack = ((uint32_t)eetrack_hi << 16) | eetrack_lo; 3975 oem = ((uint32_t)oem_hi << 16) | oem_lo; 3976 oem_ver = __SHIFTOUT(oem, IXL_NVM_OEMVERSION_MASK); 3977 oem_build = __SHIFTOUT(oem, IXL_NVM_OEMBUILD_MASK); 3978 oem_patch = __SHIFTOUT(oem, IXL_NVM_OEMPATCH_MASK); 3979 3980 aprint_normal(" nvm %x.%02x etid %08x oem %d.%d.%d", 3981 nvm_maj_ver, nvm_min_ver, eetrack, 3982 oem_ver, oem_build, oem_patch); 3983 3984 return 0; 3985 } 3986 3987 static int 3988 ixl_pxe_clear(struct ixl_softc *sc) 3989 { 3990 struct ixl_aq_desc iaq; 3991 int rv; 3992 3993 memset(&iaq, 0, sizeof(iaq)); 3994 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 3995 iaq.iaq_param[0] = htole32(0x2); 3996 3997 rv = ixl_atq_poll(sc, &iaq, 250); 3998 3999 ixl_wr(sc, I40E_GLLAN_RCTL_0, 0x1); 4000 4001 if (rv != 0) 4002 return ETIMEDOUT; 4003 4004 switch (iaq.iaq_retval) { 4005 case htole16(IXL_AQ_RC_OK): 4006 case htole16(IXL_AQ_RC_EEXIST): 4007 break; 4008 default: 4009 return EIO; 4010 } 4011 4012 return 0; 4013 } 4014 4015 static int 4016 ixl_lldp_shut(struct ixl_softc *sc) 4017 { 4018 struct ixl_aq_desc iaq; 4019 4020 memset(&iaq, 0, sizeof(iaq)); 4021 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 4022 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 4023 4024 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4025 aprint_error_dev(sc->sc_dev, "STOP LLDP AGENT timeout\n"); 4026 return -1; 4027 } 4028 4029 switch (iaq.iaq_retval) { 4030 case htole16(IXL_AQ_RC_EMODE): 4031 case htole16(IXL_AQ_RC_EPERM): 4032 /* ignore silently */ 4033 default: 4034 break; 4035 } 4036 4037 return 0; 4038 } 4039 4040 static void 4041 ixl_parse_hw_capability(struct ixl_softc *sc, struct ixl_aq_capability *cap) 4042 { 4043 uint16_t id; 4044 uint32_t number, logical_id; 4045 4046 id = le16toh(cap->cap_id); 4047 number = le32toh(cap->number); 4048 logical_id = le32toh(cap->logical_id); 4049 4050 switch (id) { 4051 case IXL_AQ_CAP_RSS: 4052 sc->sc_rss_table_size = number; 4053 sc->sc_rss_table_entry_width = logical_id; 4054 break; 4055 case IXL_AQ_CAP_RXQ: 4056 case IXL_AQ_CAP_TXQ: 4057 sc->sc_nqueue_pairs_device = MIN(number, 4058 sc->sc_nqueue_pairs_device); 4059 break; 4060 } 4061 } 4062 4063 static int 4064 ixl_get_hw_capabilities(struct ixl_softc *sc) 4065 { 4066 struct ixl_dmamem idm; 4067 struct ixl_aq_desc iaq; 4068 struct ixl_aq_capability *caps; 4069 size_t i, ncaps; 4070 bus_size_t caps_size; 4071 uint16_t status; 4072 int rv; 4073 4074 caps_size = sizeof(caps[0]) * 40; 4075 memset(&iaq, 0, sizeof(iaq)); 4076 iaq.iaq_opcode = htole16(IXL_AQ_OP_LIST_FUNC_CAP); 4077 4078 do { 4079 if (ixl_dmamem_alloc(sc, &idm, caps_size, 0) != 0) { 4080 return -1; 4081 } 4082 4083 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4084 (caps_size > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4085 iaq.iaq_datalen = htole16(caps_size); 4086 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4087 4088 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, 4089 IXL_DMA_LEN(&idm), BUS_DMASYNC_PREREAD); 4090 4091 rv = ixl_atq_poll(sc, &iaq, 250); 4092 4093 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, 4094 IXL_DMA_LEN(&idm), BUS_DMASYNC_POSTREAD); 4095 4096 if (rv != 0) { 4097 aprint_error(", HW capabilities timeout\n"); 4098 goto done; 4099 } 4100 4101 status = le16toh(iaq.iaq_retval); 4102 4103 if (status == IXL_AQ_RC_ENOMEM) { 4104 caps_size = le16toh(iaq.iaq_datalen); 4105 ixl_dmamem_free(sc, &idm); 4106 } 4107 } while (status == IXL_AQ_RC_ENOMEM); 4108 4109 if (status != IXL_AQ_RC_OK) { 4110 aprint_error(", HW capabilities error\n"); 4111 goto done; 4112 } 4113 4114 caps = IXL_DMA_KVA(&idm); 4115 ncaps = le16toh(iaq.iaq_param[1]); 4116 4117 for (i = 0; i < ncaps; i++) { 4118 ixl_parse_hw_capability(sc, &caps[i]); 4119 } 4120 4121 done: 4122 ixl_dmamem_free(sc, &idm); 4123 return rv; 4124 } 4125 4126 static int 4127 ixl_get_mac(struct ixl_softc *sc) 4128 { 4129 struct ixl_dmamem idm; 4130 struct ixl_aq_desc iaq; 4131 struct ixl_aq_mac_addresses *addrs; 4132 int rv; 4133 4134 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 4135 aprint_error(", unable to allocate mac addresses\n"); 4136 return -1; 4137 } 4138 4139 memset(&iaq, 0, sizeof(iaq)); 4140 iaq.iaq_flags = htole16(IXL_AQ_BUF); 4141 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 4142 iaq.iaq_datalen = htole16(sizeof(*addrs)); 4143 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4144 4145 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4146 BUS_DMASYNC_PREREAD); 4147 4148 rv = ixl_atq_poll(sc, &iaq, 250); 4149 4150 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4151 BUS_DMASYNC_POSTREAD); 4152 4153 if (rv != 0) { 4154 aprint_error(", MAC ADDRESS READ timeout\n"); 4155 rv = -1; 4156 goto done; 4157 } 4158 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4159 aprint_error(", MAC ADDRESS READ error\n"); 4160 rv = -1; 4161 goto done; 4162 } 4163 4164 addrs = IXL_DMA_KVA(&idm); 4165 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 4166 printf(", port address is not valid\n"); 4167 goto done; 4168 } 4169 4170 memcpy(sc->sc_enaddr, addrs->port, ETHER_ADDR_LEN); 4171 rv = 0; 4172 4173 done: 4174 ixl_dmamem_free(sc, &idm); 4175 return rv; 4176 } 4177 4178 static int 4179 ixl_get_switch_config(struct ixl_softc *sc) 4180 { 4181 struct ixl_dmamem idm; 4182 struct ixl_aq_desc iaq; 4183 struct ixl_aq_switch_config *hdr; 4184 struct ixl_aq_switch_config_element *elms, *elm; 4185 unsigned int nelm, i; 4186 int rv; 4187 4188 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4189 aprint_error_dev(sc->sc_dev, 4190 "unable to allocate switch config buffer\n"); 4191 return -1; 4192 } 4193 4194 memset(&iaq, 0, sizeof(iaq)); 4195 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4196 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4197 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 4198 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 4199 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 4200 4201 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4202 BUS_DMASYNC_PREREAD); 4203 4204 rv = ixl_atq_poll(sc, &iaq, 250); 4205 4206 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 4207 BUS_DMASYNC_POSTREAD); 4208 4209 if (rv != 0) { 4210 aprint_error_dev(sc->sc_dev, "GET SWITCH CONFIG timeout\n"); 4211 rv = -1; 4212 goto done; 4213 } 4214 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4215 aprint_error_dev(sc->sc_dev, "GET SWITCH CONFIG error\n"); 4216 rv = -1; 4217 goto done; 4218 } 4219 4220 hdr = IXL_DMA_KVA(&idm); 4221 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 4222 4223 nelm = le16toh(hdr->num_reported); 4224 if (nelm < 1) { 4225 aprint_error_dev(sc->sc_dev, "no switch config available\n"); 4226 rv = -1; 4227 goto done; 4228 } 4229 4230 for (i = 0; i < nelm; i++) { 4231 elm = &elms[i]; 4232 4233 aprint_debug_dev(sc->sc_dev, 4234 "type %x revision %u seid %04x\n", 4235 elm->type, elm->revision, le16toh(elm->seid)); 4236 aprint_debug_dev(sc->sc_dev, 4237 "uplink %04x downlink %04x\n", 4238 le16toh(elm->uplink_seid), 4239 le16toh(elm->downlink_seid)); 4240 aprint_debug_dev(sc->sc_dev, 4241 "conntype %x scheduler %04x extra %04x\n", 4242 elm->connection_type, 4243 le16toh(elm->scheduler_id), 4244 le16toh(elm->element_info)); 4245 } 4246 4247 elm = &elms[0]; 4248 4249 sc->sc_uplink_seid = elm->uplink_seid; 4250 sc->sc_downlink_seid = elm->downlink_seid; 4251 sc->sc_seid = elm->seid; 4252 4253 if ((sc->sc_uplink_seid == htole16(0)) != 4254 (sc->sc_downlink_seid == htole16(0))) { 4255 aprint_error_dev(sc->sc_dev, "SEIDs are misconfigured\n"); 4256 rv = -1; 4257 goto done; 4258 } 4259 4260 done: 4261 ixl_dmamem_free(sc, &idm); 4262 return rv; 4263 } 4264 4265 static int 4266 ixl_phy_mask_ints(struct ixl_softc *sc) 4267 { 4268 struct ixl_aq_desc iaq; 4269 4270 memset(&iaq, 0, sizeof(iaq)); 4271 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 4272 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 4273 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 4274 IXL_AQ_PHY_EV_MEDIA_NA)); 4275 4276 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4277 aprint_error_dev(sc->sc_dev, "SET PHY EVENT MASK timeout\n"); 4278 return -1; 4279 } 4280 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4281 aprint_error_dev(sc->sc_dev, "SET PHY EVENT MASK error\n"); 4282 return -1; 4283 } 4284 4285 return 0; 4286 } 4287 4288 static int 4289 ixl_get_phy_abilities(struct ixl_softc *sc, struct ixl_dmamem *idm) 4290 { 4291 struct ixl_aq_desc iaq; 4292 int rv; 4293 4294 memset(&iaq, 0, sizeof(iaq)); 4295 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4296 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4297 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 4298 iaq.iaq_datalen = htole16(IXL_DMA_LEN(idm)); 4299 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 4300 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 4301 4302 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4303 BUS_DMASYNC_PREREAD); 4304 4305 rv = ixl_atq_poll(sc, &iaq, 250); 4306 4307 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 4308 BUS_DMASYNC_POSTREAD); 4309 4310 if (rv != 0) 4311 return -1; 4312 4313 return le16toh(iaq.iaq_retval); 4314 } 4315 4316 static int 4317 ixl_get_phy_info(struct ixl_softc *sc) 4318 { 4319 struct ixl_dmamem idm; 4320 struct ixl_aq_phy_abilities *phy; 4321 int rv; 4322 4323 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 4324 aprint_error_dev(sc->sc_dev, 4325 "unable to allocate phy abilities buffer\n"); 4326 return -1; 4327 } 4328 4329 rv = ixl_get_phy_abilities(sc, &idm); 4330 switch (rv) { 4331 case -1: 4332 aprint_error_dev(sc->sc_dev, "GET PHY ABILITIES timeout\n"); 4333 goto done; 4334 case IXL_AQ_RC_OK: 4335 break; 4336 case IXL_AQ_RC_EIO: 4337 aprint_error_dev(sc->sc_dev,"unable to query phy types\n"); 4338 goto done; 4339 default: 4340 aprint_error_dev(sc->sc_dev, 4341 "GET PHY ABILITIIES error %u\n", rv); 4342 goto done; 4343 } 4344 4345 phy = IXL_DMA_KVA(&idm); 4346 4347 sc->sc_phy_types = le32toh(phy->phy_type); 4348 sc->sc_phy_types |= (uint64_t)le32toh(phy->phy_type_ext) << 32; 4349 4350 sc->sc_phy_abilities = phy->abilities; 4351 sc->sc_phy_linkspeed = phy->link_speed; 4352 sc->sc_phy_fec_cfg = phy->fec_cfg_curr_mod_ext_info & 4353 (IXL_AQ_ENABLE_FEC_KR | IXL_AQ_ENABLE_FEC_RS | 4354 IXL_AQ_REQUEST_FEC_KR | IXL_AQ_REQUEST_FEC_RS); 4355 sc->sc_eee_cap = phy->eee_capability; 4356 sc->sc_eeer_val = phy->eeer_val; 4357 sc->sc_d3_lpan = phy->d3_lpan; 4358 4359 rv = 0; 4360 4361 done: 4362 ixl_dmamem_free(sc, &idm); 4363 return rv; 4364 } 4365 4366 static int 4367 ixl_set_phy_config(struct ixl_softc *sc, 4368 uint8_t link_speed, uint8_t abilities, bool polling) 4369 { 4370 struct ixl_aq_phy_param *param; 4371 struct ixl_atq iatq; 4372 struct ixl_aq_desc *iaq; 4373 int error; 4374 4375 memset(&iatq, 0, sizeof(iatq)); 4376 4377 iaq = &iatq.iatq_desc; 4378 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_CONFIG); 4379 param = (struct ixl_aq_phy_param *)&iaq->iaq_param; 4380 param->phy_types = htole32((uint32_t)sc->sc_phy_types); 4381 param->phy_type_ext = (uint8_t)(sc->sc_phy_types >> 32); 4382 param->link_speed = link_speed; 4383 param->abilities = abilities | IXL_AQ_PHY_ABILITY_AUTO_LINK; 4384 param->fec_cfg = sc->sc_phy_fec_cfg; 4385 param->eee_capability = sc->sc_eee_cap; 4386 param->eeer_val = sc->sc_eeer_val; 4387 param->d3_lpan = sc->sc_d3_lpan; 4388 4389 if (polling) 4390 error = ixl_atq_poll(sc, iaq, 250); 4391 else 4392 error = ixl_atq_exec(sc, &iatq); 4393 4394 if (error != 0) 4395 return error; 4396 4397 switch (le16toh(iaq->iaq_retval)) { 4398 case IXL_AQ_RC_OK: 4399 break; 4400 case IXL_AQ_RC_EPERM: 4401 return EPERM; 4402 default: 4403 return EIO; 4404 } 4405 4406 return 0; 4407 } 4408 4409 static int 4410 ixl_set_phy_autoselect(struct ixl_softc *sc) 4411 { 4412 uint8_t link_speed, abilities; 4413 4414 link_speed = sc->sc_phy_linkspeed; 4415 abilities = IXL_PHY_ABILITY_LINKUP | IXL_PHY_ABILITY_AUTONEGO; 4416 4417 return ixl_set_phy_config(sc, link_speed, abilities, true); 4418 } 4419 4420 static int 4421 ixl_get_link_status_poll(struct ixl_softc *sc, int *l) 4422 { 4423 struct ixl_aq_desc iaq; 4424 struct ixl_aq_link_param *param; 4425 int link; 4426 4427 memset(&iaq, 0, sizeof(iaq)); 4428 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 4429 param = (struct ixl_aq_link_param *)iaq.iaq_param; 4430 param->notify = IXL_AQ_LINK_NOTIFY; 4431 4432 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4433 return ETIMEDOUT; 4434 } 4435 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4436 return EIO; 4437 } 4438 4439 /* It is unneccessary to hold lock */ 4440 link = ixl_set_link_status_locked(sc, &iaq); 4441 4442 if (l != NULL) 4443 *l = link; 4444 4445 return 0; 4446 } 4447 4448 static int 4449 ixl_get_vsi(struct ixl_softc *sc) 4450 { 4451 struct ixl_dmamem *vsi = &sc->sc_scratch; 4452 struct ixl_aq_desc iaq; 4453 struct ixl_aq_vsi_param *param; 4454 struct ixl_aq_vsi_reply *reply; 4455 struct ixl_aq_vsi_data *data; 4456 int rv; 4457 4458 /* grumble, vsi info isn't "known" at compile time */ 4459 4460 memset(&iaq, 0, sizeof(iaq)); 4461 iaq.iaq_flags = htole16(IXL_AQ_BUF | 4462 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4463 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4464 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi)); 4465 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4466 4467 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4468 param->uplink_seid = sc->sc_seid; 4469 4470 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4471 BUS_DMASYNC_PREREAD); 4472 4473 rv = ixl_atq_poll(sc, &iaq, 250); 4474 4475 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4476 BUS_DMASYNC_POSTREAD); 4477 4478 if (rv != 0) { 4479 return ETIMEDOUT; 4480 } 4481 4482 switch (le16toh(iaq.iaq_retval)) { 4483 case IXL_AQ_RC_OK: 4484 break; 4485 case IXL_AQ_RC_ENOENT: 4486 return ENOENT; 4487 case IXL_AQ_RC_EACCES: 4488 return EACCES; 4489 default: 4490 return EIO; 4491 } 4492 4493 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4494 sc->sc_vsi_number = le16toh(reply->vsi_number); 4495 data = IXL_DMA_KVA(vsi); 4496 sc->sc_vsi_stat_counter_idx = le16toh(data->stat_counter_idx); 4497 4498 return 0; 4499 } 4500 4501 static int 4502 ixl_set_vsi(struct ixl_softc *sc) 4503 { 4504 struct ixl_dmamem *vsi = &sc->sc_scratch; 4505 struct ixl_aq_desc iaq; 4506 struct ixl_aq_vsi_param *param; 4507 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4508 unsigned int qnum; 4509 uint16_t val; 4510 int rv; 4511 4512 qnum = sc->sc_nqueue_pairs - 1; 4513 4514 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4515 IXL_AQ_VSI_VALID_VLAN); 4516 4517 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4518 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4519 data->queue_mapping[0] = htole16(0); 4520 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4521 (qnum << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4522 4523 val = le16toh(data->port_vlan_flags); 4524 CLR(val, IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK); 4525 SET(val, IXL_AQ_VSI_PVLAN_MODE_ALL); 4526 4527 if (ISSET(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWTAGGING)) { 4528 SET(val, IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH); 4529 } else { 4530 SET(val, IXL_AQ_VSI_PVLAN_EMOD_NOTHING); 4531 } 4532 4533 data->port_vlan_flags = htole16(val); 4534 4535 /* grumble, vsi info isn't "known" at compile time */ 4536 4537 memset(&iaq, 0, sizeof(iaq)); 4538 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4539 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4540 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4541 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi)); 4542 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4543 4544 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4545 param->uplink_seid = sc->sc_seid; 4546 4547 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4548 BUS_DMASYNC_PREWRITE); 4549 4550 rv = ixl_atq_poll(sc, &iaq, 250); 4551 4552 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4553 BUS_DMASYNC_POSTWRITE); 4554 4555 if (rv != 0) { 4556 return ETIMEDOUT; 4557 } 4558 4559 switch (le16toh(iaq.iaq_retval)) { 4560 case IXL_AQ_RC_OK: 4561 break; 4562 case IXL_AQ_RC_ENOENT: 4563 return ENOENT; 4564 case IXL_AQ_RC_EACCES: 4565 return EACCES; 4566 default: 4567 return EIO; 4568 } 4569 4570 return 0; 4571 } 4572 4573 static void 4574 ixl_set_filter_control(struct ixl_softc *sc) 4575 { 4576 uint32_t reg; 4577 4578 reg = ixl_rd_rx_csr(sc, I40E_PFQF_CTL_0); 4579 4580 CLR(reg, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 4581 SET(reg, I40E_HASH_LUT_SIZE_128 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT); 4582 4583 SET(reg, I40E_PFQF_CTL_0_FD_ENA_MASK); 4584 SET(reg, I40E_PFQF_CTL_0_ETYPE_ENA_MASK); 4585 SET(reg, I40E_PFQF_CTL_0_MACVLAN_ENA_MASK); 4586 4587 ixl_wr_rx_csr(sc, I40E_PFQF_CTL_0, reg); 4588 } 4589 4590 static inline void 4591 ixl_get_default_rss_key(uint32_t *buf, size_t len) 4592 { 4593 size_t cplen; 4594 uint8_t rss_seed[RSS_KEYSIZE]; 4595 4596 rss_getkey(rss_seed); 4597 memset(buf, 0, len); 4598 4599 cplen = MIN(len, sizeof(rss_seed)); 4600 memcpy(buf, rss_seed, cplen); 4601 } 4602 4603 static int 4604 ixl_set_rss_key(struct ixl_softc *sc, uint8_t *key, size_t keylen) 4605 { 4606 struct ixl_dmamem *idm; 4607 struct ixl_atq iatq; 4608 struct ixl_aq_desc *iaq; 4609 struct ixl_aq_rss_key_param *param; 4610 struct ixl_aq_rss_key_data *data; 4611 size_t len, datalen, stdlen, extlen; 4612 uint16_t vsi_id; 4613 int rv; 4614 4615 memset(&iatq, 0, sizeof(iatq)); 4616 iaq = &iatq.iatq_desc; 4617 idm = &sc->sc_aqbuf; 4618 4619 datalen = sizeof(*data); 4620 4621 /*XXX The buf size has to be less than the size of the register */ 4622 datalen = MIN(IXL_RSS_KEY_SIZE_REG * sizeof(uint32_t), datalen); 4623 4624 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4625 (datalen > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4626 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_KEY); 4627 iaq->iaq_datalen = htole16(datalen); 4628 4629 param = (struct ixl_aq_rss_key_param *)iaq->iaq_param; 4630 vsi_id = (sc->sc_vsi_number << IXL_AQ_RSSKEY_VSI_ID_SHIFT) | 4631 IXL_AQ_RSSKEY_VSI_VALID; 4632 param->vsi_id = htole16(vsi_id); 4633 4634 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 4635 data = IXL_DMA_KVA(idm); 4636 4637 len = MIN(keylen, datalen); 4638 stdlen = MIN(sizeof(data->standard_rss_key), len); 4639 memcpy(data->standard_rss_key, key, stdlen); 4640 len = (len > stdlen) ? (len - stdlen) : 0; 4641 4642 extlen = MIN(sizeof(data->extended_hash_key), len); 4643 extlen = (stdlen < keylen) ? 0 : keylen - stdlen; 4644 memcpy(data->extended_hash_key, key + stdlen, extlen); 4645 4646 ixl_aq_dva(iaq, IXL_DMA_DVA(idm)); 4647 4648 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4649 IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE); 4650 4651 rv = ixl_atq_exec(sc, &iatq); 4652 4653 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4654 IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE); 4655 4656 if (rv != 0) { 4657 return ETIMEDOUT; 4658 } 4659 4660 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) { 4661 return EIO; 4662 } 4663 4664 return 0; 4665 } 4666 4667 static int 4668 ixl_set_rss_lut(struct ixl_softc *sc, uint8_t *lut, size_t lutlen) 4669 { 4670 struct ixl_dmamem *idm; 4671 struct ixl_atq iatq; 4672 struct ixl_aq_desc *iaq; 4673 struct ixl_aq_rss_lut_param *param; 4674 uint16_t vsi_id; 4675 uint8_t *data; 4676 size_t dmalen; 4677 int rv; 4678 4679 memset(&iatq, 0, sizeof(iatq)); 4680 iaq = &iatq.iatq_desc; 4681 idm = &sc->sc_aqbuf; 4682 4683 dmalen = MIN(lutlen, IXL_DMA_LEN(idm)); 4684 4685 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD | 4686 (dmalen > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4687 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_LUT); 4688 iaq->iaq_datalen = htole16(dmalen); 4689 4690 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 4691 data = IXL_DMA_KVA(idm); 4692 memcpy(data, lut, dmalen); 4693 ixl_aq_dva(iaq, IXL_DMA_DVA(idm)); 4694 4695 param = (struct ixl_aq_rss_lut_param *)iaq->iaq_param; 4696 vsi_id = (sc->sc_vsi_number << IXL_AQ_RSSLUT_VSI_ID_SHIFT) | 4697 IXL_AQ_RSSLUT_VSI_VALID; 4698 param->vsi_id = htole16(vsi_id); 4699 param->flags = htole16(IXL_AQ_RSSLUT_TABLE_TYPE_PF << 4700 IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT); 4701 4702 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4703 IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE); 4704 4705 rv = ixl_atq_exec(sc, &iatq); 4706 4707 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, 4708 IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE); 4709 4710 if (rv != 0) { 4711 return ETIMEDOUT; 4712 } 4713 4714 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) { 4715 return EIO; 4716 } 4717 4718 return 0; 4719 } 4720 4721 static int 4722 ixl_register_rss_key(struct ixl_softc *sc) 4723 { 4724 uint32_t rss_seed[IXL_RSS_KEY_SIZE_REG]; 4725 int rv; 4726 size_t i; 4727 4728 ixl_get_default_rss_key(rss_seed, sizeof(rss_seed)); 4729 4730 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS)) { 4731 rv = ixl_set_rss_key(sc, (uint8_t*)rss_seed, 4732 sizeof(rss_seed)); 4733 } else { 4734 rv = 0; 4735 for (i = 0; i < IXL_RSS_KEY_SIZE_REG; i++) { 4736 ixl_wr_rx_csr(sc, I40E_PFQF_HKEY(i), rss_seed[i]); 4737 } 4738 } 4739 4740 return rv; 4741 } 4742 4743 static void 4744 ixl_register_rss_pctype(struct ixl_softc *sc) 4745 { 4746 uint64_t set_hena = 0; 4747 uint32_t hena0, hena1; 4748 4749 /* 4750 * We use TCP/UDP with IPv4/IPv6 by default. 4751 * Note: the device can not use just IP header in each 4752 * TCP/UDP packets for the RSS hash calculation. 4753 */ 4754 if (sc->sc_mac_type == I40E_MAC_X722) 4755 set_hena = IXL_RSS_HENA_DEFAULT_X722; 4756 else 4757 set_hena = IXL_RSS_HENA_DEFAULT_XL710; 4758 4759 hena0 = ixl_rd_rx_csr(sc, I40E_PFQF_HENA(0)); 4760 hena1 = ixl_rd_rx_csr(sc, I40E_PFQF_HENA(1)); 4761 4762 SET(hena0, set_hena); 4763 SET(hena1, set_hena >> 32); 4764 4765 ixl_wr_rx_csr(sc, I40E_PFQF_HENA(0), hena0); 4766 ixl_wr_rx_csr(sc, I40E_PFQF_HENA(1), hena1); 4767 } 4768 4769 static int 4770 ixl_register_rss_hlut(struct ixl_softc *sc) 4771 { 4772 unsigned int qid; 4773 uint8_t hlut_buf[512], lut_mask; 4774 uint32_t *hluts; 4775 size_t i, hluts_num; 4776 int rv; 4777 4778 lut_mask = (0x01 << sc->sc_rss_table_entry_width) - 1; 4779 4780 for (i = 0; i < sc->sc_rss_table_size; i++) { 4781 qid = i % sc->sc_nqueue_pairs; 4782 hlut_buf[i] = qid & lut_mask; 4783 } 4784 4785 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RSS)) { 4786 rv = ixl_set_rss_lut(sc, hlut_buf, sizeof(hlut_buf)); 4787 } else { 4788 rv = 0; 4789 hluts = (uint32_t *)hlut_buf; 4790 hluts_num = sc->sc_rss_table_size >> 2; 4791 for (i = 0; i < hluts_num; i++) { 4792 ixl_wr(sc, I40E_PFQF_HLUT(i), hluts[i]); 4793 } 4794 ixl_flush(sc); 4795 } 4796 4797 return rv; 4798 } 4799 4800 static void 4801 ixl_config_rss(struct ixl_softc *sc) 4802 { 4803 4804 KASSERT(mutex_owned(&sc->sc_cfg_lock)); 4805 4806 ixl_register_rss_key(sc); 4807 ixl_register_rss_pctype(sc); 4808 ixl_register_rss_hlut(sc); 4809 } 4810 4811 static const struct ixl_phy_type * 4812 ixl_search_phy_type(uint8_t phy_type) 4813 { 4814 const struct ixl_phy_type *itype; 4815 uint64_t mask; 4816 unsigned int i; 4817 4818 if (phy_type >= 64) 4819 return NULL; 4820 4821 mask = 1ULL << phy_type; 4822 4823 for (i = 0; i < __arraycount(ixl_phy_type_map); i++) { 4824 itype = &ixl_phy_type_map[i]; 4825 4826 if (ISSET(itype->phy_type, mask)) 4827 return itype; 4828 } 4829 4830 return NULL; 4831 } 4832 4833 static uint64_t 4834 ixl_search_link_speed(uint8_t link_speed) 4835 { 4836 const struct ixl_speed_type *type; 4837 unsigned int i; 4838 4839 for (i = 0; i < __arraycount(ixl_speed_type_map); i++) { 4840 type = &ixl_speed_type_map[i]; 4841 4842 if (ISSET(type->dev_speed, link_speed)) 4843 return type->net_speed; 4844 } 4845 4846 return 0; 4847 } 4848 4849 static uint8_t 4850 ixl_search_baudrate(uint64_t baudrate) 4851 { 4852 const struct ixl_speed_type *type; 4853 unsigned int i; 4854 4855 for (i = 0; i < __arraycount(ixl_speed_type_map); i++) { 4856 type = &ixl_speed_type_map[i]; 4857 4858 if (type->net_speed == baudrate) { 4859 return type->dev_speed; 4860 } 4861 } 4862 4863 return 0; 4864 } 4865 4866 static int 4867 ixl_restart_an(struct ixl_softc *sc) 4868 { 4869 struct ixl_aq_desc iaq; 4870 4871 memset(&iaq, 0, sizeof(iaq)); 4872 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4873 iaq.iaq_param[0] = 4874 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4875 4876 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4877 aprint_error_dev(sc->sc_dev, "RESTART AN timeout\n"); 4878 return -1; 4879 } 4880 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4881 aprint_error_dev(sc->sc_dev, "RESTART AN error\n"); 4882 return -1; 4883 } 4884 4885 return 0; 4886 } 4887 4888 static int 4889 ixl_add_macvlan(struct ixl_softc *sc, const uint8_t *macaddr, 4890 uint16_t vlan, uint16_t flags) 4891 { 4892 struct ixl_aq_desc iaq; 4893 struct ixl_aq_add_macvlan *param; 4894 struct ixl_aq_add_macvlan_elem *elem; 4895 4896 memset(&iaq, 0, sizeof(iaq)); 4897 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4898 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4899 iaq.iaq_datalen = htole16(sizeof(*elem)); 4900 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4901 4902 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4903 param->num_addrs = htole16(1); 4904 param->seid0 = htole16(0x8000) | sc->sc_seid; 4905 param->seid1 = 0; 4906 param->seid2 = 0; 4907 4908 elem = IXL_DMA_KVA(&sc->sc_scratch); 4909 memset(elem, 0, sizeof(*elem)); 4910 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4911 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4912 elem->vlan = htole16(vlan); 4913 4914 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4915 return IXL_AQ_RC_EINVAL; 4916 } 4917 4918 switch (le16toh(iaq.iaq_retval)) { 4919 case IXL_AQ_RC_OK: 4920 break; 4921 case IXL_AQ_RC_ENOSPC: 4922 return ENOSPC; 4923 case IXL_AQ_RC_ENOENT: 4924 return ENOENT; 4925 case IXL_AQ_RC_EACCES: 4926 return EACCES; 4927 case IXL_AQ_RC_EEXIST: 4928 return EEXIST; 4929 case IXL_AQ_RC_EINVAL: 4930 return EINVAL; 4931 default: 4932 return EIO; 4933 } 4934 4935 return 0; 4936 } 4937 4938 static int 4939 ixl_remove_macvlan(struct ixl_softc *sc, const uint8_t *macaddr, 4940 uint16_t vlan, uint16_t flags) 4941 { 4942 struct ixl_aq_desc iaq; 4943 struct ixl_aq_remove_macvlan *param; 4944 struct ixl_aq_remove_macvlan_elem *elem; 4945 4946 memset(&iaq, 0, sizeof(iaq)); 4947 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4948 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 4949 iaq.iaq_datalen = htole16(sizeof(*elem)); 4950 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4951 4952 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 4953 param->num_addrs = htole16(1); 4954 param->seid0 = htole16(0x8000) | sc->sc_seid; 4955 param->seid1 = 0; 4956 param->seid2 = 0; 4957 4958 elem = IXL_DMA_KVA(&sc->sc_scratch); 4959 memset(elem, 0, sizeof(*elem)); 4960 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4961 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 4962 elem->vlan = htole16(vlan); 4963 4964 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4965 return EINVAL; 4966 } 4967 4968 switch (le16toh(iaq.iaq_retval)) { 4969 case IXL_AQ_RC_OK: 4970 break; 4971 case IXL_AQ_RC_ENOENT: 4972 return ENOENT; 4973 case IXL_AQ_RC_EACCES: 4974 return EACCES; 4975 case IXL_AQ_RC_EINVAL: 4976 return EINVAL; 4977 default: 4978 return EIO; 4979 } 4980 4981 return 0; 4982 } 4983 4984 static int 4985 ixl_hmc(struct ixl_softc *sc) 4986 { 4987 struct { 4988 uint32_t count; 4989 uint32_t minsize; 4990 bus_size_t objsiz; 4991 bus_size_t setoff; 4992 bus_size_t setcnt; 4993 } regs[] = { 4994 { 4995 0, 4996 IXL_HMC_TXQ_MINSIZE, 4997 I40E_GLHMC_LANTXOBJSZ, 4998 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 4999 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 5000 }, 5001 { 5002 0, 5003 IXL_HMC_RXQ_MINSIZE, 5004 I40E_GLHMC_LANRXOBJSZ, 5005 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 5006 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 5007 }, 5008 { 5009 0, 5010 0, 5011 I40E_GLHMC_FCOEDDPOBJSZ, 5012 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 5013 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 5014 }, 5015 { 5016 0, 5017 0, 5018 I40E_GLHMC_FCOEFOBJSZ, 5019 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 5020 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 5021 }, 5022 }; 5023 struct ixl_hmc_entry *e; 5024 uint64_t size, dva; 5025 uint8_t *kva; 5026 uint64_t *sdpage; 5027 unsigned int i; 5028 int npages, tables; 5029 uint32_t reg; 5030 5031 CTASSERT(__arraycount(regs) <= __arraycount(sc->sc_hmc_entries)); 5032 5033 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 5034 ixl_rd(sc, I40E_GLHMC_LANQMAX); 5035 5036 size = 0; 5037 for (i = 0; i < __arraycount(regs); i++) { 5038 e = &sc->sc_hmc_entries[i]; 5039 5040 e->hmc_count = regs[i].count; 5041 reg = ixl_rd(sc, regs[i].objsiz); 5042 e->hmc_size = IXL_BIT_ULL(0x3F & reg); 5043 e->hmc_base = size; 5044 5045 if ((e->hmc_size * 8) < regs[i].minsize) { 5046 aprint_error_dev(sc->sc_dev, 5047 "kernel hmc entry is too big\n"); 5048 return -1; 5049 } 5050 5051 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 5052 } 5053 size = roundup(size, IXL_HMC_PGSIZE); 5054 npages = size / IXL_HMC_PGSIZE; 5055 5056 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 5057 5058 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 5059 aprint_error_dev(sc->sc_dev, 5060 "unable to allocate hmc pd memory\n"); 5061 return -1; 5062 } 5063 5064 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 5065 IXL_HMC_PGSIZE) != 0) { 5066 aprint_error_dev(sc->sc_dev, 5067 "unable to allocate hmc sd memory\n"); 5068 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 5069 return -1; 5070 } 5071 5072 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 5073 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 5074 5075 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 5076 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 5077 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5078 5079 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 5080 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 5081 memset(sdpage, 0, IXL_DMA_LEN(&sc->sc_hmc_sd)); 5082 5083 for (i = 0; (int)i < npages; i++) { 5084 *sdpage = htole64(dva | IXL_HMC_PDVALID); 5085 sdpage++; 5086 5087 dva += IXL_HMC_PGSIZE; 5088 } 5089 5090 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 5091 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 5092 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5093 5094 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 5095 for (i = 0; (int)i < tables; i++) { 5096 uint32_t count; 5097 5098 KASSERT(npages >= 0); 5099 5100 count = ((unsigned int)npages > IXL_HMC_PGS) ? 5101 IXL_HMC_PGS : (unsigned int)npages; 5102 5103 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 5104 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 5105 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 5106 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 5107 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 5108 ixl_wr(sc, I40E_PFHMC_SDCMD, 5109 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 5110 5111 npages -= IXL_HMC_PGS; 5112 dva += IXL_HMC_PGSIZE; 5113 } 5114 5115 for (i = 0; i < __arraycount(regs); i++) { 5116 e = &sc->sc_hmc_entries[i]; 5117 5118 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 5119 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 5120 } 5121 5122 return 0; 5123 } 5124 5125 static void 5126 ixl_hmc_free(struct ixl_softc *sc) 5127 { 5128 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 5129 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 5130 } 5131 5132 static void 5133 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 5134 unsigned int npacking) 5135 { 5136 uint8_t *dst = d; 5137 const uint8_t *src = s; 5138 unsigned int i; 5139 5140 for (i = 0; i < npacking; i++) { 5141 const struct ixl_hmc_pack *pack = &packing[i]; 5142 unsigned int offset = pack->lsb / 8; 5143 unsigned int align = pack->lsb % 8; 5144 const uint8_t *in = src + pack->offset; 5145 uint8_t *out = dst + offset; 5146 int width = pack->width; 5147 unsigned int inbits = 0; 5148 5149 if (align) { 5150 inbits = (*in++) << align; 5151 *out++ |= (inbits & 0xff); 5152 inbits >>= 8; 5153 5154 width -= 8 - align; 5155 } 5156 5157 while (width >= 8) { 5158 inbits |= (*in++) << align; 5159 *out++ = (inbits & 0xff); 5160 inbits >>= 8; 5161 5162 width -= 8; 5163 } 5164 5165 if (width > 0) { 5166 inbits |= (*in) << align; 5167 *out |= (inbits & ((1 << width) - 1)); 5168 } 5169 } 5170 } 5171 5172 static struct ixl_aq_buf * 5173 ixl_aqb_alloc(struct ixl_softc *sc) 5174 { 5175 struct ixl_aq_buf *aqb; 5176 5177 aqb = kmem_alloc(sizeof(*aqb), KM_SLEEP); 5178 5179 aqb->aqb_size = IXL_AQ_BUFLEN; 5180 5181 if (bus_dmamap_create(sc->sc_dmat, aqb->aqb_size, 1, 5182 aqb->aqb_size, 0, 5183 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &aqb->aqb_map) != 0) 5184 goto free; 5185 if (bus_dmamem_alloc(sc->sc_dmat, aqb->aqb_size, 5186 IXL_AQ_ALIGN, 0, &aqb->aqb_seg, 1, &aqb->aqb_nsegs, 5187 BUS_DMA_WAITOK) != 0) 5188 goto destroy; 5189 if (bus_dmamem_map(sc->sc_dmat, &aqb->aqb_seg, aqb->aqb_nsegs, 5190 aqb->aqb_size, &aqb->aqb_data, BUS_DMA_WAITOK) != 0) 5191 goto dma_free; 5192 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 5193 aqb->aqb_size, NULL, BUS_DMA_WAITOK) != 0) 5194 goto unmap; 5195 5196 return aqb; 5197 unmap: 5198 bus_dmamem_unmap(sc->sc_dmat, aqb->aqb_data, aqb->aqb_size); 5199 dma_free: 5200 bus_dmamem_free(sc->sc_dmat, &aqb->aqb_seg, 1); 5201 destroy: 5202 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 5203 free: 5204 kmem_free(aqb, sizeof(*aqb)); 5205 5206 return NULL; 5207 } 5208 5209 static void 5210 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 5211 { 5212 5213 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 5214 bus_dmamem_unmap(sc->sc_dmat, aqb->aqb_data, aqb->aqb_size); 5215 bus_dmamem_free(sc->sc_dmat, &aqb->aqb_seg, 1); 5216 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 5217 kmem_free(aqb, sizeof(*aqb)); 5218 } 5219 5220 static int 5221 ixl_arq_fill(struct ixl_softc *sc) 5222 { 5223 struct ixl_aq_buf *aqb; 5224 struct ixl_aq_desc *arq, *iaq; 5225 unsigned int prod = sc->sc_arq_prod; 5226 unsigned int n; 5227 int post = 0; 5228 5229 n = ixl_rxr_unrefreshed(sc->sc_arq_prod, sc->sc_arq_cons, 5230 IXL_AQ_NUM); 5231 arq = IXL_DMA_KVA(&sc->sc_arq); 5232 5233 if (__predict_false(n <= 0)) 5234 return 0; 5235 5236 do { 5237 aqb = sc->sc_arq_live[prod]; 5238 iaq = &arq[prod]; 5239 5240 if (aqb == NULL) { 5241 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 5242 if (aqb != NULL) { 5243 SIMPLEQ_REMOVE(&sc->sc_arq_idle, aqb, 5244 ixl_aq_buf, aqb_entry); 5245 } else if ((aqb = ixl_aqb_alloc(sc)) == NULL) { 5246 break; 5247 } 5248 5249 sc->sc_arq_live[prod] = aqb; 5250 memset(aqb->aqb_data, 0, aqb->aqb_size); 5251 5252 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, 5253 aqb->aqb_size, BUS_DMASYNC_PREREAD); 5254 5255 iaq->iaq_flags = htole16(IXL_AQ_BUF | 5256 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? 5257 IXL_AQ_LB : 0)); 5258 iaq->iaq_opcode = 0; 5259 iaq->iaq_datalen = htole16(aqb->aqb_size); 5260 iaq->iaq_retval = 0; 5261 iaq->iaq_cookie = 0; 5262 iaq->iaq_param[0] = 0; 5263 iaq->iaq_param[1] = 0; 5264 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 5265 } 5266 5267 prod++; 5268 prod &= IXL_AQ_MASK; 5269 5270 post = 1; 5271 5272 } while (--n); 5273 5274 if (post) { 5275 sc->sc_arq_prod = prod; 5276 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 5277 } 5278 5279 return post; 5280 } 5281 5282 static void 5283 ixl_arq_unfill(struct ixl_softc *sc) 5284 { 5285 struct ixl_aq_buf *aqb; 5286 unsigned int i; 5287 5288 for (i = 0; i < __arraycount(sc->sc_arq_live); i++) { 5289 aqb = sc->sc_arq_live[i]; 5290 if (aqb == NULL) 5291 continue; 5292 5293 sc->sc_arq_live[i] = NULL; 5294 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, aqb->aqb_size, 5295 BUS_DMASYNC_POSTREAD); 5296 ixl_aqb_free(sc, aqb); 5297 } 5298 5299 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle)) != NULL) { 5300 SIMPLEQ_REMOVE(&sc->sc_arq_idle, aqb, 5301 ixl_aq_buf, aqb_entry); 5302 ixl_aqb_free(sc, aqb); 5303 } 5304 } 5305 5306 static void 5307 ixl_clear_hw(struct ixl_softc *sc) 5308 { 5309 uint32_t num_queues, base_queue; 5310 uint32_t num_pf_int; 5311 uint32_t num_vf_int; 5312 uint32_t num_vfs; 5313 uint32_t i, j; 5314 uint32_t val; 5315 uint32_t eol = 0x7ff; 5316 5317 /* get number of interrupts, queues, and vfs */ 5318 val = ixl_rd(sc, I40E_GLPCI_CNF2); 5319 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 5320 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 5321 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 5322 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 5323 5324 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 5325 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 5326 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 5327 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 5328 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 5329 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 5330 num_queues = (j - base_queue) + 1; 5331 else 5332 num_queues = 0; 5333 5334 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 5335 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 5336 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 5337 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 5338 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 5339 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 5340 num_vfs = (j - i) + 1; 5341 else 5342 num_vfs = 0; 5343 5344 /* stop all the interrupts */ 5345 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 5346 ixl_flush(sc); 5347 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 5348 for (i = 0; i < num_pf_int - 2; i++) 5349 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 5350 ixl_flush(sc); 5351 5352 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 5353 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5354 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 5355 for (i = 0; i < num_pf_int - 2; i++) 5356 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 5357 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5358 for (i = 0; i < num_vfs; i++) 5359 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 5360 for (i = 0; i < num_vf_int - 2; i++) 5361 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 5362 5363 /* warn the HW of the coming Tx disables */ 5364 for (i = 0; i < num_queues; i++) { 5365 uint32_t abs_queue_idx = base_queue + i; 5366 uint32_t reg_block = 0; 5367 5368 if (abs_queue_idx >= 128) { 5369 reg_block = abs_queue_idx / 128; 5370 abs_queue_idx %= 128; 5371 } 5372 5373 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 5374 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 5375 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 5376 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 5377 5378 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 5379 } 5380 delaymsec(400); 5381 5382 /* stop all the queues */ 5383 for (i = 0; i < num_queues; i++) { 5384 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 5385 ixl_wr(sc, I40E_QTX_ENA(i), 0); 5386 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 5387 ixl_wr(sc, I40E_QRX_ENA(i), 0); 5388 } 5389 5390 /* short wait for all queue disables to settle */ 5391 delaymsec(50); 5392 } 5393 5394 static int 5395 ixl_pf_reset(struct ixl_softc *sc) 5396 { 5397 uint32_t cnt = 0; 5398 uint32_t cnt1 = 0; 5399 uint32_t reg = 0, reg0 = 0; 5400 uint32_t grst_del; 5401 5402 /* 5403 * Poll for Global Reset steady state in case of recent GRST. 5404 * The grst delay value is in 100ms units, and we'll wait a 5405 * couple counts longer to be sure we don't just miss the end. 5406 */ 5407 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 5408 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 5409 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 5410 5411 grst_del = grst_del * 20; 5412 5413 for (cnt = 0; cnt < grst_del; cnt++) { 5414 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 5415 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 5416 break; 5417 delaymsec(100); 5418 } 5419 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5420 aprint_error(", Global reset polling failed to complete\n"); 5421 return -1; 5422 } 5423 5424 /* Now Wait for the FW to be ready */ 5425 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 5426 reg = ixl_rd(sc, I40E_GLNVM_ULD); 5427 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5428 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 5429 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5430 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 5431 break; 5432 5433 delaymsec(10); 5434 } 5435 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 5436 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 5437 aprint_error(", wait for FW Reset complete timed out " 5438 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 5439 return -1; 5440 } 5441 5442 /* 5443 * If there was a Global Reset in progress when we got here, 5444 * we don't need to do the PF Reset 5445 */ 5446 if (cnt == 0) { 5447 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5448 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 5449 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 5450 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 5451 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 5452 break; 5453 delaymsec(1); 5454 5455 reg0 = ixl_rd(sc, I40E_GLGEN_RSTAT); 5456 if (reg0 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 5457 aprint_error(", Core reset upcoming." 5458 " Skipping PF reset reset request\n"); 5459 return -1; 5460 } 5461 } 5462 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 5463 aprint_error(", PF reset polling failed to complete" 5464 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 5465 return -1; 5466 } 5467 } 5468 5469 return 0; 5470 } 5471 5472 static int 5473 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 5474 bus_size_t size, bus_size_t align) 5475 { 5476 ixm->ixm_size = size; 5477 5478 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 5479 ixm->ixm_size, 0, 5480 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 5481 &ixm->ixm_map) != 0) 5482 return 1; 5483 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5484 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5485 BUS_DMA_WAITOK) != 0) 5486 goto destroy; 5487 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5488 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5489 goto free; 5490 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5491 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5492 goto unmap; 5493 5494 memset(ixm->ixm_kva, 0, ixm->ixm_size); 5495 5496 return 0; 5497 unmap: 5498 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5499 free: 5500 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5501 destroy: 5502 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5503 return 1; 5504 } 5505 5506 static void 5507 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5508 { 5509 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5510 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5511 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5512 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5513 } 5514 5515 static int 5516 ixl_setup_vlan_hwfilter(struct ixl_softc *sc) 5517 { 5518 struct ethercom *ec = &sc->sc_ec; 5519 struct vlanid_list *vlanidp; 5520 int rv; 5521 5522 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 5523 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 5524 ixl_remove_macvlan(sc, etherbroadcastaddr, 0, 5525 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 5526 5527 rv = ixl_add_macvlan(sc, sc->sc_enaddr, 0, 5528 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5529 if (rv != 0) 5530 return rv; 5531 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 0, 5532 IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5533 if (rv != 0) 5534 return rv; 5535 5536 ETHER_LOCK(ec); 5537 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 5538 rv = ixl_add_macvlan(sc, sc->sc_enaddr, 5539 vlanidp->vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5540 if (rv != 0) 5541 break; 5542 rv = ixl_add_macvlan(sc, etherbroadcastaddr, 5543 vlanidp->vid, IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH); 5544 if (rv != 0) 5545 break; 5546 } 5547 ETHER_UNLOCK(ec); 5548 5549 return rv; 5550 } 5551 5552 static void 5553 ixl_teardown_vlan_hwfilter(struct ixl_softc *sc) 5554 { 5555 struct vlanid_list *vlanidp; 5556 struct ethercom *ec = &sc->sc_ec; 5557 5558 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 5559 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5560 ixl_remove_macvlan(sc, etherbroadcastaddr, 0, 5561 IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5562 5563 ETHER_LOCK(ec); 5564 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 5565 ixl_remove_macvlan(sc, sc->sc_enaddr, 5566 vlanidp->vid, IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5567 ixl_remove_macvlan(sc, etherbroadcastaddr, 5568 vlanidp->vid, IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH); 5569 } 5570 ETHER_UNLOCK(ec); 5571 5572 ixl_add_macvlan(sc, sc->sc_enaddr, 0, 5573 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 5574 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 5575 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 5576 } 5577 5578 static int 5579 ixl_update_macvlan(struct ixl_softc *sc) 5580 { 5581 int rv = 0; 5582 int next_ec_capenable = sc->sc_ec.ec_capenable; 5583 5584 if (ISSET(next_ec_capenable, ETHERCAP_VLAN_HWFILTER)) { 5585 rv = ixl_setup_vlan_hwfilter(sc); 5586 if (rv != 0) 5587 ixl_teardown_vlan_hwfilter(sc); 5588 } else { 5589 ixl_teardown_vlan_hwfilter(sc); 5590 } 5591 5592 return rv; 5593 } 5594 5595 static int 5596 ixl_ifflags_cb(struct ethercom *ec) 5597 { 5598 struct ifnet *ifp = &ec->ec_if; 5599 struct ixl_softc *sc = ifp->if_softc; 5600 int rv, change; 5601 5602 mutex_enter(&sc->sc_cfg_lock); 5603 5604 change = ec->ec_capenable ^ sc->sc_cur_ec_capenable; 5605 5606 if (ISSET(change, ETHERCAP_VLAN_HWTAGGING)) { 5607 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWTAGGING; 5608 rv = ENETRESET; 5609 goto out; 5610 } 5611 5612 if (ISSET(change, ETHERCAP_VLAN_HWFILTER)) { 5613 rv = ixl_update_macvlan(sc); 5614 if (rv == 0) { 5615 sc->sc_cur_ec_capenable ^= ETHERCAP_VLAN_HWFILTER; 5616 } else { 5617 CLR(ec->ec_capenable, ETHERCAP_VLAN_HWFILTER); 5618 CLR(sc->sc_cur_ec_capenable, ETHERCAP_VLAN_HWFILTER); 5619 } 5620 } 5621 5622 rv = ixl_iff(sc); 5623 out: 5624 mutex_exit(&sc->sc_cfg_lock); 5625 5626 return rv; 5627 } 5628 5629 static int 5630 ixl_set_link_status_locked(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 5631 { 5632 const struct ixl_aq_link_status *status; 5633 const struct ixl_phy_type *itype; 5634 5635 uint64_t ifm_active = IFM_ETHER; 5636 uint64_t ifm_status = IFM_AVALID; 5637 int link_state = LINK_STATE_DOWN; 5638 uint64_t baudrate = 0; 5639 5640 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 5641 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) { 5642 ifm_active |= IFM_NONE; 5643 goto done; 5644 } 5645 5646 ifm_active |= IFM_FDX; 5647 ifm_status |= IFM_ACTIVE; 5648 link_state = LINK_STATE_UP; 5649 5650 itype = ixl_search_phy_type(status->phy_type); 5651 if (itype != NULL) 5652 ifm_active |= itype->ifm_type; 5653 5654 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 5655 ifm_active |= IFM_ETH_TXPAUSE; 5656 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 5657 ifm_active |= IFM_ETH_RXPAUSE; 5658 5659 baudrate = ixl_search_link_speed(status->link_speed); 5660 5661 done: 5662 /* sc->sc_cfg_lock held expect during attach */ 5663 sc->sc_media_active = ifm_active; 5664 sc->sc_media_status = ifm_status; 5665 5666 sc->sc_ec.ec_if.if_baudrate = baudrate; 5667 5668 return link_state; 5669 } 5670 5671 static int 5672 ixl_establish_intx(struct ixl_softc *sc) 5673 { 5674 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 5675 pci_intr_handle_t *intr; 5676 char xnamebuf[32]; 5677 char intrbuf[PCI_INTRSTR_LEN]; 5678 char const *intrstr; 5679 5680 KASSERT(sc->sc_nintrs == 1); 5681 5682 intr = &sc->sc_ihp[0]; 5683 5684 intrstr = pci_intr_string(pc, *intr, intrbuf, sizeof(intrbuf)); 5685 snprintf(xnamebuf, sizeof(xnamebuf), "%s:legacy", 5686 device_xname(sc->sc_dev)); 5687 5688 sc->sc_ihs[0] = pci_intr_establish_xname(pc, *intr, IPL_NET, ixl_intr, 5689 sc, xnamebuf); 5690 5691 if (sc->sc_ihs[0] == NULL) { 5692 aprint_error_dev(sc->sc_dev, 5693 "unable to establish interrupt at %s\n", intrstr); 5694 return -1; 5695 } 5696 5697 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 5698 return 0; 5699 } 5700 5701 static int 5702 ixl_establish_msix(struct ixl_softc *sc) 5703 { 5704 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 5705 kcpuset_t *affinity; 5706 unsigned int vector = 0; 5707 unsigned int i; 5708 int affinity_to, r; 5709 char xnamebuf[32]; 5710 char intrbuf[PCI_INTRSTR_LEN]; 5711 char const *intrstr; 5712 5713 kcpuset_create(&affinity, false); 5714 5715 /* the "other" intr is mapped to vector 0 */ 5716 vector = 0; 5717 intrstr = pci_intr_string(pc, sc->sc_ihp[vector], 5718 intrbuf, sizeof(intrbuf)); 5719 snprintf(xnamebuf, sizeof(xnamebuf), "%s others", 5720 device_xname(sc->sc_dev)); 5721 sc->sc_ihs[vector] = pci_intr_establish_xname(pc, 5722 sc->sc_ihp[vector], IPL_NET, ixl_other_intr, 5723 sc, xnamebuf); 5724 if (sc->sc_ihs[vector] == NULL) { 5725 aprint_error_dev(sc->sc_dev, 5726 "unable to establish interrupt at %s\n", intrstr); 5727 goto fail; 5728 } 5729 5730 aprint_normal_dev(sc->sc_dev, "other interrupt at %s", intrstr); 5731 5732 affinity_to = ncpu > (int)sc->sc_nqueue_pairs_max ? 1 : 0; 5733 affinity_to = (affinity_to + sc->sc_nqueue_pairs_max) % ncpu; 5734 5735 kcpuset_zero(affinity); 5736 kcpuset_set(affinity, affinity_to); 5737 r = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 5738 if (r == 0) { 5739 aprint_normal(", affinity to %u", affinity_to); 5740 } 5741 aprint_normal("\n"); 5742 vector++; 5743 5744 sc->sc_msix_vector_queue = vector; 5745 affinity_to = ncpu > (int)sc->sc_nqueue_pairs_max ? 1 : 0; 5746 5747 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 5748 intrstr = pci_intr_string(pc, sc->sc_ihp[vector], 5749 intrbuf, sizeof(intrbuf)); 5750 snprintf(xnamebuf, sizeof(xnamebuf), "%s TXRX%d", 5751 device_xname(sc->sc_dev), i); 5752 5753 sc->sc_ihs[vector] = pci_intr_establish_xname(pc, 5754 sc->sc_ihp[vector], IPL_NET, ixl_queue_intr, 5755 (void *)&sc->sc_qps[i], xnamebuf); 5756 5757 if (sc->sc_ihs[vector] == NULL) { 5758 aprint_error_dev(sc->sc_dev, 5759 "unable to establish interrupt at %s\n", intrstr); 5760 goto fail; 5761 } 5762 5763 aprint_normal_dev(sc->sc_dev, 5764 "for TXRX%d interrupt at %s", i, intrstr); 5765 5766 kcpuset_zero(affinity); 5767 kcpuset_set(affinity, affinity_to); 5768 r = interrupt_distribute(sc->sc_ihs[vector], affinity, NULL); 5769 if (r == 0) { 5770 aprint_normal(", affinity to %u", affinity_to); 5771 affinity_to = (affinity_to + 1) % ncpu; 5772 } 5773 aprint_normal("\n"); 5774 vector++; 5775 } 5776 5777 kcpuset_destroy(affinity); 5778 5779 return 0; 5780 fail: 5781 for (i = 0; i < vector; i++) { 5782 pci_intr_disestablish(pc, sc->sc_ihs[i]); 5783 } 5784 5785 sc->sc_msix_vector_queue = 0; 5786 sc->sc_msix_vector_queue = 0; 5787 kcpuset_destroy(affinity); 5788 5789 return -1; 5790 } 5791 5792 static void 5793 ixl_config_queue_intr(struct ixl_softc *sc) 5794 { 5795 unsigned int i, vector; 5796 5797 if (sc->sc_intrtype == PCI_INTR_TYPE_MSIX) { 5798 vector = sc->sc_msix_vector_queue; 5799 } else { 5800 vector = I40E_INTR_NOTX_INTR; 5801 5802 ixl_wr(sc, I40E_PFINT_LNKLST0, 5803 (I40E_INTR_NOTX_QUEUE << 5804 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 5805 (I40E_QUEUE_TYPE_RX << 5806 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 5807 } 5808 5809 for (i = 0; i < sc->sc_nqueue_pairs; i++) { 5810 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 0); 5811 ixl_flush(sc); 5812 5813 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 5814 ((i) << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 5815 (I40E_QUEUE_TYPE_RX << 5816 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 5817 5818 ixl_wr(sc, I40E_QINT_RQCTL(i), 5819 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 5820 (I40E_ITR_INDEX_RX << 5821 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 5822 (I40E_INTR_NOTX_RX_QUEUE << 5823 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 5824 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 5825 (I40E_QUEUE_TYPE_TX << 5826 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 5827 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 5828 5829 ixl_wr(sc, I40E_QINT_TQCTL(i), 5830 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 5831 (I40E_ITR_INDEX_TX << 5832 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 5833 (I40E_INTR_NOTX_TX_QUEUE << 5834 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 5835 (I40E_QUEUE_TYPE_EOL << 5836 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 5837 (I40E_QUEUE_TYPE_RX << 5838 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 5839 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 5840 5841 if (sc->sc_intrtype == PCI_INTR_TYPE_MSIX) { 5842 ixl_wr(sc, I40E_PFINT_ITRN(I40E_ITR_INDEX_RX, i), 5843 sc->sc_itr_rx); 5844 ixl_wr(sc, I40E_PFINT_ITRN(I40E_ITR_INDEX_TX, i), 5845 sc->sc_itr_tx); 5846 vector++; 5847 } 5848 } 5849 ixl_flush(sc); 5850 5851 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_RX), sc->sc_itr_rx); 5852 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_TX), sc->sc_itr_tx); 5853 ixl_flush(sc); 5854 } 5855 5856 static void 5857 ixl_config_other_intr(struct ixl_softc *sc) 5858 { 5859 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 5860 (void)ixl_rd(sc, I40E_PFINT_ICR0); 5861 5862 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 5863 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 5864 I40E_PFINT_ICR0_ENA_GRST_MASK | 5865 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 5866 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 5867 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | 5868 I40E_PFINT_ICR0_ENA_VFLR_MASK | 5869 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | 5870 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | 5871 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK); 5872 5873 ixl_wr(sc, I40E_PFINT_LNKLST0, 0x7FF); 5874 ixl_wr(sc, I40E_PFINT_ITR0(I40E_ITR_INDEX_OTHER), 0); 5875 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 5876 (I40E_ITR_INDEX_OTHER << 5877 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)); 5878 ixl_flush(sc); 5879 } 5880 5881 static int 5882 ixl_setup_interrupts(struct ixl_softc *sc) 5883 { 5884 struct pci_attach_args *pa = &sc->sc_pa; 5885 pci_intr_type_t max_type, intr_type; 5886 int counts[PCI_INTR_TYPE_SIZE]; 5887 int error; 5888 unsigned int i; 5889 bool retry; 5890 5891 memset(counts, 0, sizeof(counts)); 5892 max_type = PCI_INTR_TYPE_MSIX; 5893 /* QPs + other interrupt */ 5894 counts[PCI_INTR_TYPE_MSIX] = sc->sc_nqueue_pairs_max + 1; 5895 counts[PCI_INTR_TYPE_INTX] = 1; 5896 5897 if (ixl_param_nomsix) 5898 counts[PCI_INTR_TYPE_MSIX] = 0; 5899 5900 do { 5901 retry = false; 5902 error = pci_intr_alloc(pa, &sc->sc_ihp, counts, max_type); 5903 if (error != 0) { 5904 aprint_error_dev(sc->sc_dev, 5905 "couldn't map interrupt\n"); 5906 break; 5907 } 5908 5909 intr_type = pci_intr_type(pa->pa_pc, sc->sc_ihp[0]); 5910 sc->sc_nintrs = counts[intr_type]; 5911 KASSERT(sc->sc_nintrs > 0); 5912 5913 for (i = 0; i < sc->sc_nintrs; i++) { 5914 pci_intr_setattr(pa->pa_pc, &sc->sc_ihp[i], 5915 PCI_INTR_MPSAFE, true); 5916 } 5917 5918 sc->sc_ihs = kmem_zalloc(sizeof(sc->sc_ihs[0]) * sc->sc_nintrs, 5919 KM_SLEEP); 5920 5921 if (intr_type == PCI_INTR_TYPE_MSIX) { 5922 error = ixl_establish_msix(sc); 5923 if (error) { 5924 counts[PCI_INTR_TYPE_MSIX] = 0; 5925 retry = true; 5926 } 5927 } else if (intr_type == PCI_INTR_TYPE_INTX) { 5928 error = ixl_establish_intx(sc); 5929 } else { 5930 error = -1; 5931 } 5932 5933 if (error) { 5934 kmem_free(sc->sc_ihs, 5935 sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 5936 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 5937 } else { 5938 sc->sc_intrtype = intr_type; 5939 } 5940 } while (retry); 5941 5942 return error; 5943 } 5944 5945 static void 5946 ixl_teardown_interrupts(struct ixl_softc *sc) 5947 { 5948 struct pci_attach_args *pa = &sc->sc_pa; 5949 unsigned int i; 5950 5951 for (i = 0; i < sc->sc_nintrs; i++) { 5952 pci_intr_disestablish(pa->pa_pc, sc->sc_ihs[i]); 5953 } 5954 5955 pci_intr_release(pa->pa_pc, sc->sc_ihp, sc->sc_nintrs); 5956 5957 kmem_free(sc->sc_ihs, sizeof(sc->sc_ihs[0]) * sc->sc_nintrs); 5958 sc->sc_ihs = NULL; 5959 sc->sc_nintrs = 0; 5960 } 5961 5962 static int 5963 ixl_setup_stats(struct ixl_softc *sc) 5964 { 5965 struct ixl_queue_pair *qp; 5966 struct ixl_tx_ring *txr; 5967 struct ixl_rx_ring *rxr; 5968 struct ixl_stats_counters *isc; 5969 unsigned int i; 5970 5971 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 5972 qp = &sc->sc_qps[i]; 5973 txr = qp->qp_txr; 5974 rxr = qp->qp_rxr; 5975 5976 evcnt_attach_dynamic(&txr->txr_defragged, EVCNT_TYPE_MISC, 5977 NULL, qp->qp_name, "m_defrag successed"); 5978 evcnt_attach_dynamic(&txr->txr_defrag_failed, EVCNT_TYPE_MISC, 5979 NULL, qp->qp_name, "m_defrag_failed"); 5980 evcnt_attach_dynamic(&txr->txr_pcqdrop, EVCNT_TYPE_MISC, 5981 NULL, qp->qp_name, "Dropped in pcq"); 5982 evcnt_attach_dynamic(&txr->txr_transmitdef, EVCNT_TYPE_MISC, 5983 NULL, qp->qp_name, "Deferred transmit"); 5984 evcnt_attach_dynamic(&txr->txr_intr, EVCNT_TYPE_INTR, 5985 NULL, qp->qp_name, "Interrupt on queue"); 5986 evcnt_attach_dynamic(&txr->txr_defer, EVCNT_TYPE_MISC, 5987 NULL, qp->qp_name, "Handled queue in softint/workqueue"); 5988 5989 evcnt_attach_dynamic(&rxr->rxr_mgethdr_failed, EVCNT_TYPE_MISC, 5990 NULL, qp->qp_name, "MGETHDR failed"); 5991 evcnt_attach_dynamic(&rxr->rxr_mgetcl_failed, EVCNT_TYPE_MISC, 5992 NULL, qp->qp_name, "MCLGET failed"); 5993 evcnt_attach_dynamic(&rxr->rxr_mbuf_load_failed, 5994 EVCNT_TYPE_MISC, NULL, qp->qp_name, 5995 "bus_dmamap_load_mbuf failed"); 5996 evcnt_attach_dynamic(&rxr->rxr_intr, EVCNT_TYPE_INTR, 5997 NULL, qp->qp_name, "Interrupt on queue"); 5998 evcnt_attach_dynamic(&rxr->rxr_defer, EVCNT_TYPE_MISC, 5999 NULL, qp->qp_name, "Handled queue in softint/workqueue"); 6000 } 6001 6002 evcnt_attach_dynamic(&sc->sc_event_atq, EVCNT_TYPE_INTR, 6003 NULL, device_xname(sc->sc_dev), "Interrupt for other events"); 6004 evcnt_attach_dynamic(&sc->sc_event_link, EVCNT_TYPE_MISC, 6005 NULL, device_xname(sc->sc_dev), "Link status event"); 6006 evcnt_attach_dynamic(&sc->sc_event_ecc_err, EVCNT_TYPE_MISC, 6007 NULL, device_xname(sc->sc_dev), "ECC error"); 6008 evcnt_attach_dynamic(&sc->sc_event_pci_exception, EVCNT_TYPE_MISC, 6009 NULL, device_xname(sc->sc_dev), "PCI exception"); 6010 evcnt_attach_dynamic(&sc->sc_event_crit_err, EVCNT_TYPE_MISC, 6011 NULL, device_xname(sc->sc_dev), "Critical error"); 6012 6013 isc = &sc->sc_stats_counters; 6014 evcnt_attach_dynamic(&isc->isc_crc_errors, EVCNT_TYPE_MISC, 6015 NULL, device_xname(sc->sc_dev), "CRC errors"); 6016 evcnt_attach_dynamic(&isc->isc_illegal_bytes, EVCNT_TYPE_MISC, 6017 NULL, device_xname(sc->sc_dev), "Illegal bytes"); 6018 evcnt_attach_dynamic(&isc->isc_mac_local_faults, EVCNT_TYPE_MISC, 6019 NULL, device_xname(sc->sc_dev), "Mac local faults"); 6020 evcnt_attach_dynamic(&isc->isc_mac_remote_faults, EVCNT_TYPE_MISC, 6021 NULL, device_xname(sc->sc_dev), "Mac remote faults"); 6022 evcnt_attach_dynamic(&isc->isc_link_xon_rx, EVCNT_TYPE_MISC, 6023 NULL, device_xname(sc->sc_dev), "Rx xon"); 6024 evcnt_attach_dynamic(&isc->isc_link_xon_tx, EVCNT_TYPE_MISC, 6025 NULL, device_xname(sc->sc_dev), "Tx xon"); 6026 evcnt_attach_dynamic(&isc->isc_link_xoff_rx, EVCNT_TYPE_MISC, 6027 NULL, device_xname(sc->sc_dev), "Rx xoff"); 6028 evcnt_attach_dynamic(&isc->isc_link_xoff_tx, EVCNT_TYPE_MISC, 6029 NULL, device_xname(sc->sc_dev), "Tx xoff"); 6030 evcnt_attach_dynamic(&isc->isc_rx_fragments, EVCNT_TYPE_MISC, 6031 NULL, device_xname(sc->sc_dev), "Rx fragments"); 6032 evcnt_attach_dynamic(&isc->isc_rx_jabber, EVCNT_TYPE_MISC, 6033 NULL, device_xname(sc->sc_dev), "Rx jabber"); 6034 6035 evcnt_attach_dynamic(&isc->isc_rx_size_64, EVCNT_TYPE_MISC, 6036 NULL, device_xname(sc->sc_dev), "Rx size 64"); 6037 evcnt_attach_dynamic(&isc->isc_rx_size_127, EVCNT_TYPE_MISC, 6038 NULL, device_xname(sc->sc_dev), "Rx size 127"); 6039 evcnt_attach_dynamic(&isc->isc_rx_size_255, EVCNT_TYPE_MISC, 6040 NULL, device_xname(sc->sc_dev), "Rx size 255"); 6041 evcnt_attach_dynamic(&isc->isc_rx_size_511, EVCNT_TYPE_MISC, 6042 NULL, device_xname(sc->sc_dev), "Rx size 511"); 6043 evcnt_attach_dynamic(&isc->isc_rx_size_1023, EVCNT_TYPE_MISC, 6044 NULL, device_xname(sc->sc_dev), "Rx size 1023"); 6045 evcnt_attach_dynamic(&isc->isc_rx_size_1522, EVCNT_TYPE_MISC, 6046 NULL, device_xname(sc->sc_dev), "Rx size 1522"); 6047 evcnt_attach_dynamic(&isc->isc_rx_size_big, EVCNT_TYPE_MISC, 6048 NULL, device_xname(sc->sc_dev), "Rx jumbo packets"); 6049 evcnt_attach_dynamic(&isc->isc_rx_undersize, EVCNT_TYPE_MISC, 6050 NULL, device_xname(sc->sc_dev), "Rx under size"); 6051 evcnt_attach_dynamic(&isc->isc_rx_oversize, EVCNT_TYPE_MISC, 6052 NULL, device_xname(sc->sc_dev), "Rx over size"); 6053 6054 evcnt_attach_dynamic(&isc->isc_rx_bytes, EVCNT_TYPE_MISC, 6055 NULL, device_xname(sc->sc_dev), "Rx bytes / port"); 6056 evcnt_attach_dynamic(&isc->isc_rx_discards, EVCNT_TYPE_MISC, 6057 NULL, device_xname(sc->sc_dev), "Rx discards / port"); 6058 evcnt_attach_dynamic(&isc->isc_rx_unicast, EVCNT_TYPE_MISC, 6059 NULL, device_xname(sc->sc_dev), "Rx unicast / port"); 6060 evcnt_attach_dynamic(&isc->isc_rx_multicast, EVCNT_TYPE_MISC, 6061 NULL, device_xname(sc->sc_dev), "Rx multicast / port"); 6062 evcnt_attach_dynamic(&isc->isc_rx_broadcast, EVCNT_TYPE_MISC, 6063 NULL, device_xname(sc->sc_dev), "Rx broadcast / port"); 6064 6065 evcnt_attach_dynamic(&isc->isc_vsi_rx_bytes, EVCNT_TYPE_MISC, 6066 NULL, device_xname(sc->sc_dev), "Rx bytes / vsi"); 6067 evcnt_attach_dynamic(&isc->isc_vsi_rx_discards, EVCNT_TYPE_MISC, 6068 NULL, device_xname(sc->sc_dev), "Rx discard / vsi"); 6069 evcnt_attach_dynamic(&isc->isc_vsi_rx_unicast, EVCNT_TYPE_MISC, 6070 NULL, device_xname(sc->sc_dev), "Rx unicast / vsi"); 6071 evcnt_attach_dynamic(&isc->isc_vsi_rx_multicast, EVCNT_TYPE_MISC, 6072 NULL, device_xname(sc->sc_dev), "Rx multicast / vsi"); 6073 evcnt_attach_dynamic(&isc->isc_vsi_rx_broadcast, EVCNT_TYPE_MISC, 6074 NULL, device_xname(sc->sc_dev), "Rx broadcast / vsi"); 6075 6076 evcnt_attach_dynamic(&isc->isc_tx_size_64, EVCNT_TYPE_MISC, 6077 NULL, device_xname(sc->sc_dev), "Tx size 64"); 6078 evcnt_attach_dynamic(&isc->isc_tx_size_127, EVCNT_TYPE_MISC, 6079 NULL, device_xname(sc->sc_dev), "Tx size 127"); 6080 evcnt_attach_dynamic(&isc->isc_tx_size_255, EVCNT_TYPE_MISC, 6081 NULL, device_xname(sc->sc_dev), "Tx size 255"); 6082 evcnt_attach_dynamic(&isc->isc_tx_size_511, EVCNT_TYPE_MISC, 6083 NULL, device_xname(sc->sc_dev), "Tx size 511"); 6084 evcnt_attach_dynamic(&isc->isc_tx_size_1023, EVCNT_TYPE_MISC, 6085 NULL, device_xname(sc->sc_dev), "Tx size 1023"); 6086 evcnt_attach_dynamic(&isc->isc_tx_size_1522, EVCNT_TYPE_MISC, 6087 NULL, device_xname(sc->sc_dev), "Tx size 1522"); 6088 evcnt_attach_dynamic(&isc->isc_tx_size_big, EVCNT_TYPE_MISC, 6089 NULL, device_xname(sc->sc_dev), "Tx jumbo packets"); 6090 6091 evcnt_attach_dynamic(&isc->isc_tx_bytes, EVCNT_TYPE_MISC, 6092 NULL, device_xname(sc->sc_dev), "Tx bytes / port"); 6093 evcnt_attach_dynamic(&isc->isc_tx_dropped_link_down, EVCNT_TYPE_MISC, 6094 NULL, device_xname(sc->sc_dev), 6095 "Tx dropped due to link down / port"); 6096 evcnt_attach_dynamic(&isc->isc_tx_unicast, EVCNT_TYPE_MISC, 6097 NULL, device_xname(sc->sc_dev), "Tx unicast / port"); 6098 evcnt_attach_dynamic(&isc->isc_tx_multicast, EVCNT_TYPE_MISC, 6099 NULL, device_xname(sc->sc_dev), "Tx multicast / port"); 6100 evcnt_attach_dynamic(&isc->isc_tx_broadcast, EVCNT_TYPE_MISC, 6101 NULL, device_xname(sc->sc_dev), "Tx broadcast / port"); 6102 6103 evcnt_attach_dynamic(&isc->isc_vsi_tx_bytes, EVCNT_TYPE_MISC, 6104 NULL, device_xname(sc->sc_dev), "Tx bytes / vsi"); 6105 evcnt_attach_dynamic(&isc->isc_vsi_tx_errors, EVCNT_TYPE_MISC, 6106 NULL, device_xname(sc->sc_dev), "Tx errors / vsi"); 6107 evcnt_attach_dynamic(&isc->isc_vsi_tx_unicast, EVCNT_TYPE_MISC, 6108 NULL, device_xname(sc->sc_dev), "Tx unicast / vsi"); 6109 evcnt_attach_dynamic(&isc->isc_vsi_tx_multicast, EVCNT_TYPE_MISC, 6110 NULL, device_xname(sc->sc_dev), "Tx multicast / vsi"); 6111 evcnt_attach_dynamic(&isc->isc_vsi_tx_broadcast, EVCNT_TYPE_MISC, 6112 NULL, device_xname(sc->sc_dev), "Tx broadcast / vsi"); 6113 6114 sc->sc_stats_intval = ixl_param_stats_interval; 6115 callout_init(&sc->sc_stats_callout, CALLOUT_MPSAFE); 6116 callout_setfunc(&sc->sc_stats_callout, ixl_stats_callout, sc); 6117 ixl_work_set(&sc->sc_stats_task, ixl_stats_update, sc); 6118 6119 return 0; 6120 } 6121 6122 static void 6123 ixl_teardown_stats(struct ixl_softc *sc) 6124 { 6125 struct ixl_tx_ring *txr; 6126 struct ixl_rx_ring *rxr; 6127 struct ixl_stats_counters *isc; 6128 unsigned int i; 6129 6130 for (i = 0; i < sc->sc_nqueue_pairs_max; i++) { 6131 txr = sc->sc_qps[i].qp_txr; 6132 rxr = sc->sc_qps[i].qp_rxr; 6133 6134 evcnt_detach(&txr->txr_defragged); 6135 evcnt_detach(&txr->txr_defrag_failed); 6136 evcnt_detach(&txr->txr_pcqdrop); 6137 evcnt_detach(&txr->txr_transmitdef); 6138 evcnt_detach(&txr->txr_intr); 6139 evcnt_detach(&txr->txr_defer); 6140 6141 evcnt_detach(&rxr->rxr_mgethdr_failed); 6142 evcnt_detach(&rxr->rxr_mgetcl_failed); 6143 evcnt_detach(&rxr->rxr_mbuf_load_failed); 6144 evcnt_detach(&rxr->rxr_intr); 6145 evcnt_detach(&rxr->rxr_defer); 6146 } 6147 6148 isc = &sc->sc_stats_counters; 6149 evcnt_detach(&isc->isc_crc_errors); 6150 evcnt_detach(&isc->isc_illegal_bytes); 6151 evcnt_detach(&isc->isc_mac_local_faults); 6152 evcnt_detach(&isc->isc_mac_remote_faults); 6153 evcnt_detach(&isc->isc_link_xon_rx); 6154 evcnt_detach(&isc->isc_link_xon_tx); 6155 evcnt_detach(&isc->isc_link_xoff_rx); 6156 evcnt_detach(&isc->isc_link_xoff_tx); 6157 evcnt_detach(&isc->isc_rx_fragments); 6158 evcnt_detach(&isc->isc_rx_jabber); 6159 evcnt_detach(&isc->isc_rx_bytes); 6160 evcnt_detach(&isc->isc_rx_discards); 6161 evcnt_detach(&isc->isc_rx_unicast); 6162 evcnt_detach(&isc->isc_rx_multicast); 6163 evcnt_detach(&isc->isc_rx_broadcast); 6164 evcnt_detach(&isc->isc_rx_size_64); 6165 evcnt_detach(&isc->isc_rx_size_127); 6166 evcnt_detach(&isc->isc_rx_size_255); 6167 evcnt_detach(&isc->isc_rx_size_511); 6168 evcnt_detach(&isc->isc_rx_size_1023); 6169 evcnt_detach(&isc->isc_rx_size_1522); 6170 evcnt_detach(&isc->isc_rx_size_big); 6171 evcnt_detach(&isc->isc_rx_undersize); 6172 evcnt_detach(&isc->isc_rx_oversize); 6173 evcnt_detach(&isc->isc_tx_bytes); 6174 evcnt_detach(&isc->isc_tx_dropped_link_down); 6175 evcnt_detach(&isc->isc_tx_unicast); 6176 evcnt_detach(&isc->isc_tx_multicast); 6177 evcnt_detach(&isc->isc_tx_broadcast); 6178 evcnt_detach(&isc->isc_tx_size_64); 6179 evcnt_detach(&isc->isc_tx_size_127); 6180 evcnt_detach(&isc->isc_tx_size_255); 6181 evcnt_detach(&isc->isc_tx_size_511); 6182 evcnt_detach(&isc->isc_tx_size_1023); 6183 evcnt_detach(&isc->isc_tx_size_1522); 6184 evcnt_detach(&isc->isc_tx_size_big); 6185 evcnt_detach(&isc->isc_vsi_rx_discards); 6186 evcnt_detach(&isc->isc_vsi_rx_bytes); 6187 evcnt_detach(&isc->isc_vsi_rx_unicast); 6188 evcnt_detach(&isc->isc_vsi_rx_multicast); 6189 evcnt_detach(&isc->isc_vsi_rx_broadcast); 6190 evcnt_detach(&isc->isc_vsi_tx_errors); 6191 evcnt_detach(&isc->isc_vsi_tx_bytes); 6192 evcnt_detach(&isc->isc_vsi_tx_unicast); 6193 evcnt_detach(&isc->isc_vsi_tx_multicast); 6194 evcnt_detach(&isc->isc_vsi_tx_broadcast); 6195 6196 evcnt_detach(&sc->sc_event_atq); 6197 evcnt_detach(&sc->sc_event_link); 6198 evcnt_detach(&sc->sc_event_ecc_err); 6199 evcnt_detach(&sc->sc_event_pci_exception); 6200 evcnt_detach(&sc->sc_event_crit_err); 6201 6202 callout_destroy(&sc->sc_stats_callout); 6203 } 6204 6205 static void 6206 ixl_stats_callout(void *xsc) 6207 { 6208 struct ixl_softc *sc = xsc; 6209 6210 ixl_work_add(sc->sc_workq, &sc->sc_stats_task); 6211 callout_schedule(&sc->sc_stats_callout, mstohz(sc->sc_stats_intval)); 6212 } 6213 6214 static uint64_t 6215 ixl_stat_delta(struct ixl_softc *sc, uint32_t reg_hi, uint32_t reg_lo, 6216 uint64_t *offset, bool has_offset) 6217 { 6218 uint64_t value, delta; 6219 int bitwidth; 6220 6221 bitwidth = reg_hi == 0 ? 32 : 48; 6222 6223 value = ixl_rd(sc, reg_lo); 6224 6225 if (bitwidth > 32) { 6226 value |= ((uint64_t)ixl_rd(sc, reg_hi) << 32); 6227 } 6228 6229 if (__predict_true(has_offset)) { 6230 delta = value; 6231 if (value < *offset) 6232 delta += ((uint64_t)1 << bitwidth); 6233 delta -= *offset; 6234 } else { 6235 delta = 0; 6236 } 6237 atomic_swap_64(offset, value); 6238 6239 return delta; 6240 } 6241 6242 static void 6243 ixl_stats_update(void *xsc) 6244 { 6245 struct ixl_softc *sc = xsc; 6246 struct ixl_stats_counters *isc; 6247 uint64_t delta; 6248 6249 isc = &sc->sc_stats_counters; 6250 6251 /* errors */ 6252 delta = ixl_stat_delta(sc, 6253 0, I40E_GLPRT_CRCERRS(sc->sc_port), 6254 &isc->isc_crc_errors_offset, isc->isc_has_offset); 6255 atomic_add_64(&isc->isc_crc_errors.ev_count, delta); 6256 6257 delta = ixl_stat_delta(sc, 6258 0, I40E_GLPRT_ILLERRC(sc->sc_port), 6259 &isc->isc_illegal_bytes_offset, isc->isc_has_offset); 6260 atomic_add_64(&isc->isc_illegal_bytes.ev_count, delta); 6261 6262 /* rx */ 6263 delta = ixl_stat_delta(sc, 6264 I40E_GLPRT_GORCH(sc->sc_port), I40E_GLPRT_GORCL(sc->sc_port), 6265 &isc->isc_rx_bytes_offset, isc->isc_has_offset); 6266 atomic_add_64(&isc->isc_rx_bytes.ev_count, delta); 6267 6268 delta = ixl_stat_delta(sc, 6269 0, I40E_GLPRT_RDPC(sc->sc_port), 6270 &isc->isc_rx_discards_offset, isc->isc_has_offset); 6271 atomic_add_64(&isc->isc_rx_discards.ev_count, delta); 6272 6273 delta = ixl_stat_delta(sc, 6274 I40E_GLPRT_UPRCH(sc->sc_port), I40E_GLPRT_UPRCL(sc->sc_port), 6275 &isc->isc_rx_unicast_offset, isc->isc_has_offset); 6276 atomic_add_64(&isc->isc_rx_unicast.ev_count, delta); 6277 6278 delta = ixl_stat_delta(sc, 6279 I40E_GLPRT_MPRCH(sc->sc_port), I40E_GLPRT_MPRCL(sc->sc_port), 6280 &isc->isc_rx_multicast_offset, isc->isc_has_offset); 6281 atomic_add_64(&isc->isc_rx_multicast.ev_count, delta); 6282 6283 delta = ixl_stat_delta(sc, 6284 I40E_GLPRT_BPRCH(sc->sc_port), I40E_GLPRT_BPRCL(sc->sc_port), 6285 &isc->isc_rx_broadcast_offset, isc->isc_has_offset); 6286 atomic_add_64(&isc->isc_rx_broadcast.ev_count, delta); 6287 6288 /* Packet size stats rx */ 6289 delta = ixl_stat_delta(sc, 6290 I40E_GLPRT_PRC64H(sc->sc_port), I40E_GLPRT_PRC64L(sc->sc_port), 6291 &isc->isc_rx_size_64_offset, isc->isc_has_offset); 6292 atomic_add_64(&isc->isc_rx_size_64.ev_count, delta); 6293 6294 delta = ixl_stat_delta(sc, 6295 I40E_GLPRT_PRC127H(sc->sc_port), I40E_GLPRT_PRC127L(sc->sc_port), 6296 &isc->isc_rx_size_127_offset, isc->isc_has_offset); 6297 atomic_add_64(&isc->isc_rx_size_127.ev_count, delta); 6298 6299 delta = ixl_stat_delta(sc, 6300 I40E_GLPRT_PRC255H(sc->sc_port), I40E_GLPRT_PRC255L(sc->sc_port), 6301 &isc->isc_rx_size_255_offset, isc->isc_has_offset); 6302 atomic_add_64(&isc->isc_rx_size_255.ev_count, delta); 6303 6304 delta = ixl_stat_delta(sc, 6305 I40E_GLPRT_PRC511H(sc->sc_port), I40E_GLPRT_PRC511L(sc->sc_port), 6306 &isc->isc_rx_size_511_offset, isc->isc_has_offset); 6307 atomic_add_64(&isc->isc_rx_size_511.ev_count, delta); 6308 6309 delta = ixl_stat_delta(sc, 6310 I40E_GLPRT_PRC1023H(sc->sc_port), I40E_GLPRT_PRC1023L(sc->sc_port), 6311 &isc->isc_rx_size_1023_offset, isc->isc_has_offset); 6312 atomic_add_64(&isc->isc_rx_size_1023.ev_count, delta); 6313 6314 delta = ixl_stat_delta(sc, 6315 I40E_GLPRT_PRC1522H(sc->sc_port), I40E_GLPRT_PRC1522L(sc->sc_port), 6316 &isc->isc_rx_size_1522_offset, isc->isc_has_offset); 6317 atomic_add_64(&isc->isc_rx_size_1522.ev_count, delta); 6318 6319 delta = ixl_stat_delta(sc, 6320 I40E_GLPRT_PRC9522H(sc->sc_port), I40E_GLPRT_PRC9522L(sc->sc_port), 6321 &isc->isc_rx_size_big_offset, isc->isc_has_offset); 6322 atomic_add_64(&isc->isc_rx_size_big.ev_count, delta); 6323 6324 delta = ixl_stat_delta(sc, 6325 0, I40E_GLPRT_RUC(sc->sc_port), 6326 &isc->isc_rx_undersize_offset, isc->isc_has_offset); 6327 atomic_add_64(&isc->isc_rx_undersize.ev_count, delta); 6328 6329 delta = ixl_stat_delta(sc, 6330 0, I40E_GLPRT_ROC(sc->sc_port), 6331 &isc->isc_rx_oversize_offset, isc->isc_has_offset); 6332 atomic_add_64(&isc->isc_rx_oversize.ev_count, delta); 6333 6334 /* tx */ 6335 delta = ixl_stat_delta(sc, 6336 I40E_GLPRT_GOTCH(sc->sc_port), I40E_GLPRT_GOTCL(sc->sc_port), 6337 &isc->isc_tx_bytes_offset, isc->isc_has_offset); 6338 atomic_add_64(&isc->isc_tx_bytes.ev_count, delta); 6339 6340 delta = ixl_stat_delta(sc, 6341 0, I40E_GLPRT_TDOLD(sc->sc_port), 6342 &isc->isc_tx_dropped_link_down_offset, isc->isc_has_offset); 6343 atomic_add_64(&isc->isc_tx_dropped_link_down.ev_count, delta); 6344 6345 delta = ixl_stat_delta(sc, 6346 I40E_GLPRT_UPTCH(sc->sc_port), I40E_GLPRT_UPTCL(sc->sc_port), 6347 &isc->isc_tx_unicast_offset, isc->isc_has_offset); 6348 atomic_add_64(&isc->isc_tx_unicast.ev_count, delta); 6349 6350 delta = ixl_stat_delta(sc, 6351 I40E_GLPRT_MPTCH(sc->sc_port), I40E_GLPRT_MPTCL(sc->sc_port), 6352 &isc->isc_tx_multicast_offset, isc->isc_has_offset); 6353 atomic_add_64(&isc->isc_tx_multicast.ev_count, delta); 6354 6355 delta = ixl_stat_delta(sc, 6356 I40E_GLPRT_BPTCH(sc->sc_port), I40E_GLPRT_BPTCL(sc->sc_port), 6357 &isc->isc_tx_broadcast_offset, isc->isc_has_offset); 6358 atomic_add_64(&isc->isc_tx_broadcast.ev_count, delta); 6359 6360 /* Packet size stats tx */ 6361 delta = ixl_stat_delta(sc, 6362 I40E_GLPRT_PTC64L(sc->sc_port), I40E_GLPRT_PTC64L(sc->sc_port), 6363 &isc->isc_tx_size_64_offset, isc->isc_has_offset); 6364 atomic_add_64(&isc->isc_tx_size_64.ev_count, delta); 6365 6366 delta = ixl_stat_delta(sc, 6367 I40E_GLPRT_PTC127H(sc->sc_port), I40E_GLPRT_PTC127L(sc->sc_port), 6368 &isc->isc_tx_size_127_offset, isc->isc_has_offset); 6369 atomic_add_64(&isc->isc_tx_size_127.ev_count, delta); 6370 6371 delta = ixl_stat_delta(sc, 6372 I40E_GLPRT_PTC255H(sc->sc_port), I40E_GLPRT_PTC255L(sc->sc_port), 6373 &isc->isc_tx_size_255_offset, isc->isc_has_offset); 6374 atomic_add_64(&isc->isc_tx_size_255.ev_count, delta); 6375 6376 delta = ixl_stat_delta(sc, 6377 I40E_GLPRT_PTC511H(sc->sc_port), I40E_GLPRT_PTC511L(sc->sc_port), 6378 &isc->isc_tx_size_511_offset, isc->isc_has_offset); 6379 atomic_add_64(&isc->isc_tx_size_511.ev_count, delta); 6380 6381 delta = ixl_stat_delta(sc, 6382 I40E_GLPRT_PTC1023H(sc->sc_port), I40E_GLPRT_PTC1023L(sc->sc_port), 6383 &isc->isc_tx_size_1023_offset, isc->isc_has_offset); 6384 atomic_add_64(&isc->isc_tx_size_1023.ev_count, delta); 6385 6386 delta = ixl_stat_delta(sc, 6387 I40E_GLPRT_PTC1522H(sc->sc_port), I40E_GLPRT_PTC1522L(sc->sc_port), 6388 &isc->isc_tx_size_1522_offset, isc->isc_has_offset); 6389 atomic_add_64(&isc->isc_tx_size_1522.ev_count, delta); 6390 6391 delta = ixl_stat_delta(sc, 6392 I40E_GLPRT_PTC9522H(sc->sc_port), I40E_GLPRT_PTC9522L(sc->sc_port), 6393 &isc->isc_tx_size_big_offset, isc->isc_has_offset); 6394 atomic_add_64(&isc->isc_tx_size_big.ev_count, delta); 6395 6396 /* mac faults */ 6397 delta = ixl_stat_delta(sc, 6398 0, I40E_GLPRT_MLFC(sc->sc_port), 6399 &isc->isc_mac_local_faults_offset, isc->isc_has_offset); 6400 atomic_add_64(&isc->isc_mac_local_faults.ev_count, delta); 6401 6402 delta = ixl_stat_delta(sc, 6403 0, I40E_GLPRT_MRFC(sc->sc_port), 6404 &isc->isc_mac_remote_faults_offset, isc->isc_has_offset); 6405 atomic_add_64(&isc->isc_mac_remote_faults.ev_count, delta); 6406 6407 /* Flow control (LFC) stats */ 6408 delta = ixl_stat_delta(sc, 6409 0, I40E_GLPRT_LXONRXC(sc->sc_port), 6410 &isc->isc_link_xon_rx_offset, isc->isc_has_offset); 6411 atomic_add_64(&isc->isc_link_xon_rx.ev_count, delta); 6412 6413 delta = ixl_stat_delta(sc, 6414 0, I40E_GLPRT_LXONTXC(sc->sc_port), 6415 &isc->isc_link_xon_tx_offset, isc->isc_has_offset); 6416 atomic_add_64(&isc->isc_link_xon_tx.ev_count, delta); 6417 6418 delta = ixl_stat_delta(sc, 6419 0, I40E_GLPRT_LXOFFRXC(sc->sc_port), 6420 &isc->isc_link_xoff_rx_offset, isc->isc_has_offset); 6421 atomic_add_64(&isc->isc_link_xoff_rx.ev_count, delta); 6422 6423 delta = ixl_stat_delta(sc, 6424 0, I40E_GLPRT_LXOFFTXC(sc->sc_port), 6425 &isc->isc_link_xoff_tx_offset, isc->isc_has_offset); 6426 atomic_add_64(&isc->isc_link_xoff_tx.ev_count, delta); 6427 6428 /* fragments */ 6429 delta = ixl_stat_delta(sc, 6430 0, I40E_GLPRT_RFC(sc->sc_port), 6431 &isc->isc_rx_fragments_offset, isc->isc_has_offset); 6432 atomic_add_64(&isc->isc_rx_fragments.ev_count, delta); 6433 6434 delta = ixl_stat_delta(sc, 6435 0, I40E_GLPRT_RJC(sc->sc_port), 6436 &isc->isc_rx_jabber_offset, isc->isc_has_offset); 6437 atomic_add_64(&isc->isc_rx_jabber.ev_count, delta); 6438 6439 /* VSI rx counters */ 6440 delta = ixl_stat_delta(sc, 6441 0, I40E_GLV_RDPC(sc->sc_vsi_stat_counter_idx), 6442 &isc->isc_vsi_rx_discards_offset, isc->isc_has_offset); 6443 atomic_add_64(&isc->isc_vsi_rx_discards.ev_count, delta); 6444 6445 delta = ixl_stat_delta(sc, 6446 I40E_GLV_GORCH(sc->sc_vsi_stat_counter_idx), 6447 I40E_GLV_GORCL(sc->sc_vsi_stat_counter_idx), 6448 &isc->isc_vsi_rx_bytes_offset, isc->isc_has_offset); 6449 atomic_add_64(&isc->isc_vsi_rx_bytes.ev_count, delta); 6450 6451 delta = ixl_stat_delta(sc, 6452 I40E_GLV_UPRCH(sc->sc_vsi_stat_counter_idx), 6453 I40E_GLV_UPRCL(sc->sc_vsi_stat_counter_idx), 6454 &isc->isc_vsi_rx_unicast_offset, isc->isc_has_offset); 6455 atomic_add_64(&isc->isc_vsi_rx_unicast.ev_count, delta); 6456 6457 delta = ixl_stat_delta(sc, 6458 I40E_GLV_MPRCH(sc->sc_vsi_stat_counter_idx), 6459 I40E_GLV_MPRCL(sc->sc_vsi_stat_counter_idx), 6460 &isc->isc_vsi_rx_multicast_offset, isc->isc_has_offset); 6461 atomic_add_64(&isc->isc_vsi_rx_multicast.ev_count, delta); 6462 6463 delta = ixl_stat_delta(sc, 6464 I40E_GLV_BPRCH(sc->sc_vsi_stat_counter_idx), 6465 I40E_GLV_BPRCL(sc->sc_vsi_stat_counter_idx), 6466 &isc->isc_vsi_rx_broadcast_offset, isc->isc_has_offset); 6467 atomic_add_64(&isc->isc_vsi_rx_broadcast.ev_count, delta); 6468 6469 /* VSI tx counters */ 6470 delta = ixl_stat_delta(sc, 6471 0, I40E_GLV_TEPC(sc->sc_vsi_stat_counter_idx), 6472 &isc->isc_vsi_tx_errors_offset, isc->isc_has_offset); 6473 atomic_add_64(&isc->isc_vsi_tx_errors.ev_count, delta); 6474 6475 delta = ixl_stat_delta(sc, 6476 I40E_GLV_GOTCH(sc->sc_vsi_stat_counter_idx), 6477 I40E_GLV_GOTCL(sc->sc_vsi_stat_counter_idx), 6478 &isc->isc_vsi_tx_bytes_offset, isc->isc_has_offset); 6479 atomic_add_64(&isc->isc_vsi_tx_bytes.ev_count, delta); 6480 6481 delta = ixl_stat_delta(sc, 6482 I40E_GLV_UPTCH(sc->sc_vsi_stat_counter_idx), 6483 I40E_GLV_UPTCL(sc->sc_vsi_stat_counter_idx), 6484 &isc->isc_vsi_tx_unicast_offset, isc->isc_has_offset); 6485 atomic_add_64(&isc->isc_vsi_tx_unicast.ev_count, delta); 6486 6487 delta = ixl_stat_delta(sc, 6488 I40E_GLV_MPTCH(sc->sc_vsi_stat_counter_idx), 6489 I40E_GLV_MPTCL(sc->sc_vsi_stat_counter_idx), 6490 &isc->isc_vsi_tx_multicast_offset, isc->isc_has_offset); 6491 atomic_add_64(&isc->isc_vsi_tx_multicast.ev_count, delta); 6492 6493 delta = ixl_stat_delta(sc, 6494 I40E_GLV_BPTCH(sc->sc_vsi_stat_counter_idx), 6495 I40E_GLV_BPTCL(sc->sc_vsi_stat_counter_idx), 6496 &isc->isc_vsi_tx_broadcast_offset, isc->isc_has_offset); 6497 atomic_add_64(&isc->isc_vsi_tx_broadcast.ev_count, delta); 6498 } 6499 6500 static int 6501 ixl_setup_sysctls(struct ixl_softc *sc) 6502 { 6503 const char *devname; 6504 struct sysctllog **log; 6505 const struct sysctlnode *rnode, *rxnode, *txnode; 6506 int error; 6507 6508 log = &sc->sc_sysctllog; 6509 devname = device_xname(sc->sc_dev); 6510 6511 error = sysctl_createv(log, 0, NULL, &rnode, 6512 0, CTLTYPE_NODE, devname, 6513 SYSCTL_DESCR("ixl information and settings"), 6514 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 6515 if (error) 6516 goto out; 6517 6518 error = sysctl_createv(log, 0, &rnode, NULL, 6519 CTLFLAG_READWRITE, CTLTYPE_BOOL, "txrx_workqueue", 6520 SYSCTL_DESCR("Use workqueue for packet processing"), 6521 NULL, 0, &sc->sc_txrx_workqueue, 0, CTL_CREATE, CTL_EOL); 6522 if (error) 6523 goto out; 6524 6525 error = sysctl_createv(log, 0, &rnode, NULL, 6526 CTLFLAG_READONLY, CTLTYPE_INT, "stats_interval", 6527 SYSCTL_DESCR("Statistics collection interval in milliseconds"), 6528 NULL, 0, &sc->sc_stats_intval, 0, CTL_CREATE, CTL_EOL); 6529 6530 error = sysctl_createv(log, 0, &rnode, &rxnode, 6531 0, CTLTYPE_NODE, "rx", 6532 SYSCTL_DESCR("ixl information and settings for Rx"), 6533 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 6534 if (error) 6535 goto out; 6536 6537 error = sysctl_createv(log, 0, &rxnode, NULL, 6538 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 6539 SYSCTL_DESCR("Interrupt Throttling"), 6540 ixl_sysctl_itr_handler, 0, 6541 (void *)sc, 0, CTL_CREATE, CTL_EOL); 6542 if (error) 6543 goto out; 6544 6545 error = sysctl_createv(log, 0, &rxnode, NULL, 6546 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 6547 SYSCTL_DESCR("the number of rx descriptors"), 6548 NULL, 0, &sc->sc_rx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 6549 if (error) 6550 goto out; 6551 6552 error = sysctl_createv(log, 0, &rxnode, NULL, 6553 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 6554 SYSCTL_DESCR("max number of Rx packets" 6555 " to process for interrupt processing"), 6556 NULL, 0, &sc->sc_rx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 6557 if (error) 6558 goto out; 6559 6560 error = sysctl_createv(log, 0, &rxnode, NULL, 6561 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 6562 SYSCTL_DESCR("max number of Rx packets" 6563 " to process for deferred processing"), 6564 NULL, 0, &sc->sc_rx_process_limit, 0, CTL_CREATE, CTL_EOL); 6565 if (error) 6566 goto out; 6567 6568 error = sysctl_createv(log, 0, &rnode, &txnode, 6569 0, CTLTYPE_NODE, "tx", 6570 SYSCTL_DESCR("ixl information and settings for Tx"), 6571 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 6572 if (error) 6573 goto out; 6574 6575 error = sysctl_createv(log, 0, &txnode, NULL, 6576 CTLFLAG_READWRITE, CTLTYPE_INT, "itr", 6577 SYSCTL_DESCR("Interrupt Throttling"), 6578 ixl_sysctl_itr_handler, 0, 6579 (void *)sc, 0, CTL_CREATE, CTL_EOL); 6580 if (error) 6581 goto out; 6582 6583 error = sysctl_createv(log, 0, &txnode, NULL, 6584 CTLFLAG_READONLY, CTLTYPE_INT, "descriptor_num", 6585 SYSCTL_DESCR("the number of tx descriptors"), 6586 NULL, 0, &sc->sc_tx_ring_ndescs, 0, CTL_CREATE, CTL_EOL); 6587 if (error) 6588 goto out; 6589 6590 error = sysctl_createv(log, 0, &txnode, NULL, 6591 CTLFLAG_READWRITE, CTLTYPE_INT, "intr_process_limit", 6592 SYSCTL_DESCR("max number of Tx packets" 6593 " to process for interrupt processing"), 6594 NULL, 0, &sc->sc_tx_intr_process_limit, 0, CTL_CREATE, CTL_EOL); 6595 if (error) 6596 goto out; 6597 6598 error = sysctl_createv(log, 0, &txnode, NULL, 6599 CTLFLAG_READWRITE, CTLTYPE_INT, "process_limit", 6600 SYSCTL_DESCR("max number of Tx packets" 6601 " to process for deferred processing"), 6602 NULL, 0, &sc->sc_tx_process_limit, 0, CTL_CREATE, CTL_EOL); 6603 if (error) 6604 goto out; 6605 6606 out: 6607 if (error) { 6608 aprint_error_dev(sc->sc_dev, 6609 "unable to create sysctl node\n"); 6610 sysctl_teardown(log); 6611 } 6612 6613 return error; 6614 } 6615 6616 static void 6617 ixl_teardown_sysctls(struct ixl_softc *sc) 6618 { 6619 6620 sysctl_teardown(&sc->sc_sysctllog); 6621 } 6622 6623 static bool 6624 ixl_sysctlnode_is_rx(struct sysctlnode *node) 6625 { 6626 6627 if (strstr(node->sysctl_parent->sysctl_name, "rx") != NULL) 6628 return true; 6629 6630 return false; 6631 } 6632 6633 static int 6634 ixl_sysctl_itr_handler(SYSCTLFN_ARGS) 6635 { 6636 struct sysctlnode node = *rnode; 6637 struct ixl_softc *sc = (struct ixl_softc *)node.sysctl_data; 6638 struct ifnet *ifp = &sc->sc_ec.ec_if; 6639 uint32_t newitr, *itrptr; 6640 int error; 6641 6642 if (ixl_sysctlnode_is_rx(&node)) { 6643 itrptr = &sc->sc_itr_rx; 6644 } else { 6645 itrptr = &sc->sc_itr_tx; 6646 } 6647 6648 newitr = *itrptr; 6649 node.sysctl_data = &newitr; 6650 node.sysctl_size = sizeof(newitr); 6651 6652 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 6653 6654 if (error || newp == NULL) 6655 return error; 6656 6657 /* ITRs are applied in ixl_init() for simple implementaion */ 6658 if (ISSET(ifp->if_flags, IFF_RUNNING)) 6659 return EBUSY; 6660 6661 if (newitr > 0x07ff) 6662 return EINVAL; 6663 6664 *itrptr = newitr; 6665 6666 return 0; 6667 } 6668 6669 static struct workqueue * 6670 ixl_workq_create(const char *name, pri_t prio, int ipl, int flags) 6671 { 6672 struct workqueue *wq; 6673 int error; 6674 6675 error = workqueue_create(&wq, name, ixl_workq_work, NULL, 6676 prio, ipl, flags); 6677 6678 if (error) 6679 return NULL; 6680 6681 return wq; 6682 } 6683 6684 static void 6685 ixl_workq_destroy(struct workqueue *wq) 6686 { 6687 6688 workqueue_destroy(wq); 6689 } 6690 6691 static void 6692 ixl_work_set(struct ixl_work *work, void (*func)(void *), void *arg) 6693 { 6694 6695 memset(work, 0, sizeof(*work)); 6696 work->ixw_func = func; 6697 work->ixw_arg = arg; 6698 } 6699 6700 static void 6701 ixl_work_add(struct workqueue *wq, struct ixl_work *work) 6702 { 6703 if (atomic_cas_uint(&work->ixw_added, 0, 1) != 0) 6704 return; 6705 6706 kpreempt_disable(); 6707 workqueue_enqueue(wq, &work->ixw_cookie, NULL); 6708 kpreempt_enable(); 6709 } 6710 6711 static void 6712 ixl_work_wait(struct workqueue *wq, struct ixl_work *work) 6713 { 6714 6715 workqueue_wait(wq, &work->ixw_cookie); 6716 } 6717 6718 static void 6719 ixl_workq_work(struct work *wk, void *context) 6720 { 6721 struct ixl_work *work; 6722 6723 work = container_of(wk, struct ixl_work, ixw_cookie); 6724 6725 atomic_swap_uint(&work->ixw_added, 0); 6726 work->ixw_func(work->ixw_arg); 6727 } 6728 6729 static int 6730 ixl_rx_ctl_read(struct ixl_softc *sc, uint32_t reg, uint32_t *rv) 6731 { 6732 struct ixl_aq_desc iaq; 6733 6734 memset(&iaq, 0, sizeof(iaq)); 6735 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_READ); 6736 iaq.iaq_param[1] = htole32(reg); 6737 6738 if (ixl_atq_poll(sc, &iaq, 250) != 0) 6739 return ETIMEDOUT; 6740 6741 switch (htole16(iaq.iaq_retval)) { 6742 case IXL_AQ_RC_OK: 6743 /* success */ 6744 break; 6745 case IXL_AQ_RC_EACCES: 6746 return EPERM; 6747 case IXL_AQ_RC_EAGAIN: 6748 return EAGAIN; 6749 default: 6750 return EIO; 6751 } 6752 6753 *rv = htole32(iaq.iaq_param[3]); 6754 return 0; 6755 } 6756 6757 static uint32_t 6758 ixl_rd_rx_csr(struct ixl_softc *sc, uint32_t reg) 6759 { 6760 uint32_t val; 6761 int rv, retry, retry_limit; 6762 6763 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL)) { 6764 retry_limit = 5; 6765 } else { 6766 retry_limit = 0; 6767 } 6768 6769 for (retry = 0; retry < retry_limit; retry++) { 6770 rv = ixl_rx_ctl_read(sc, reg, &val); 6771 if (rv == 0) 6772 return val; 6773 else if (rv == EAGAIN) 6774 delaymsec(1); 6775 else 6776 break; 6777 } 6778 6779 val = ixl_rd(sc, reg); 6780 6781 return val; 6782 } 6783 6784 static int 6785 ixl_rx_ctl_write(struct ixl_softc *sc, uint32_t reg, uint32_t value) 6786 { 6787 struct ixl_aq_desc iaq; 6788 6789 memset(&iaq, 0, sizeof(iaq)); 6790 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_WRITE); 6791 iaq.iaq_param[1] = htole32(reg); 6792 iaq.iaq_param[3] = htole32(value); 6793 6794 if (ixl_atq_poll(sc, &iaq, 250) != 0) 6795 return ETIMEDOUT; 6796 6797 switch (htole16(iaq.iaq_retval)) { 6798 case IXL_AQ_RC_OK: 6799 /* success */ 6800 break; 6801 case IXL_AQ_RC_EACCES: 6802 return EPERM; 6803 case IXL_AQ_RC_EAGAIN: 6804 return EAGAIN; 6805 default: 6806 return EIO; 6807 } 6808 6809 return 0; 6810 } 6811 6812 static void 6813 ixl_wr_rx_csr(struct ixl_softc *sc, uint32_t reg, uint32_t value) 6814 { 6815 int rv, retry, retry_limit; 6816 6817 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_RXCTL)) { 6818 retry_limit = 5; 6819 } else { 6820 retry_limit = 0; 6821 } 6822 6823 for (retry = 0; retry < retry_limit; retry++) { 6824 rv = ixl_rx_ctl_write(sc, reg, value); 6825 if (rv == 0) 6826 return; 6827 else if (rv == EAGAIN) 6828 delaymsec(1); 6829 else 6830 break; 6831 } 6832 6833 ixl_wr(sc, reg, value); 6834 } 6835 6836 static int 6837 ixl_nvm_lock(struct ixl_softc *sc, char rw) 6838 { 6839 struct ixl_aq_desc iaq; 6840 struct ixl_aq_req_resource_param *param; 6841 int rv; 6842 6843 if (!ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK)) 6844 return 0; 6845 6846 memset(&iaq, 0, sizeof(iaq)); 6847 iaq.iaq_opcode = htole16(IXL_AQ_OP_REQUEST_RESOURCE); 6848 6849 param = (struct ixl_aq_req_resource_param *)&iaq.iaq_param; 6850 param->resource_id = htole16(IXL_AQ_RESOURCE_ID_NVM); 6851 if (rw == 'R') { 6852 param->access_type = htole16(IXL_AQ_RESOURCE_ACCES_READ); 6853 } else { 6854 param->access_type = htole16(IXL_AQ_RESOURCE_ACCES_WRITE); 6855 } 6856 6857 rv = ixl_atq_poll(sc, &iaq, 250); 6858 6859 if (rv != 0) 6860 return ETIMEDOUT; 6861 6862 switch (le16toh(iaq.iaq_retval)) { 6863 case IXL_AQ_RC_OK: 6864 break; 6865 case IXL_AQ_RC_EACCES: 6866 return EACCES; 6867 case IXL_AQ_RC_EBUSY: 6868 return EBUSY; 6869 case IXL_AQ_RC_EPERM: 6870 return EPERM; 6871 } 6872 6873 return 0; 6874 } 6875 6876 static int 6877 ixl_nvm_unlock(struct ixl_softc *sc) 6878 { 6879 struct ixl_aq_desc iaq; 6880 struct ixl_aq_rel_resource_param *param; 6881 int rv; 6882 6883 if (!ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMLOCK)) 6884 return 0; 6885 6886 memset(&iaq, 0, sizeof(iaq)); 6887 iaq.iaq_opcode = htole16(IXL_AQ_OP_RELEASE_RESOURCE); 6888 6889 param = (struct ixl_aq_rel_resource_param *)&iaq.iaq_param; 6890 param->resource_id = htole16(IXL_AQ_RESOURCE_ID_NVM); 6891 6892 rv = ixl_atq_poll(sc, &iaq, 250); 6893 6894 if (rv != 0) 6895 return ETIMEDOUT; 6896 6897 switch (le16toh(iaq.iaq_retval)) { 6898 case IXL_AQ_RC_OK: 6899 break; 6900 default: 6901 return EIO; 6902 } 6903 return 0; 6904 } 6905 6906 static int 6907 ixl_srdone_poll(struct ixl_softc *sc) 6908 { 6909 int wait_count; 6910 uint32_t reg; 6911 6912 for (wait_count = 0; wait_count < IXL_SRRD_SRCTL_ATTEMPTS; 6913 wait_count++) { 6914 reg = ixl_rd(sc, I40E_GLNVM_SRCTL); 6915 if (ISSET(reg, I40E_GLNVM_SRCTL_DONE_MASK)) 6916 break; 6917 6918 delaymsec(5); 6919 } 6920 6921 if (wait_count == IXL_SRRD_SRCTL_ATTEMPTS) 6922 return -1; 6923 6924 return 0; 6925 } 6926 6927 static int 6928 ixl_nvm_read_srctl(struct ixl_softc *sc, uint16_t offset, uint16_t *data) 6929 { 6930 uint32_t reg; 6931 6932 if (ixl_srdone_poll(sc) != 0) 6933 return ETIMEDOUT; 6934 6935 reg = ((uint32_t)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 6936 __BIT(I40E_GLNVM_SRCTL_START_SHIFT); 6937 ixl_wr(sc, I40E_GLNVM_SRCTL, reg); 6938 6939 if (ixl_srdone_poll(sc) != 0) { 6940 aprint_debug("NVM read error: couldn't access " 6941 "Shadow RAM address: 0x%x\n", offset); 6942 return ETIMEDOUT; 6943 } 6944 6945 reg = ixl_rd(sc, I40E_GLNVM_SRDATA); 6946 *data = (uint16_t)__SHIFTOUT(reg, I40E_GLNVM_SRDATA_RDDATA_MASK); 6947 6948 return 0; 6949 } 6950 6951 static int 6952 ixl_nvm_read_aq(struct ixl_softc *sc, uint16_t offset_word, 6953 void *data, size_t len) 6954 { 6955 struct ixl_dmamem *idm; 6956 struct ixl_aq_desc iaq; 6957 struct ixl_aq_nvm_param *param; 6958 uint32_t offset_bytes; 6959 int rv; 6960 6961 idm = &sc->sc_aqbuf; 6962 if (len > IXL_DMA_LEN(idm)) 6963 return ENOMEM; 6964 6965 memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm)); 6966 memset(&iaq, 0, sizeof(iaq)); 6967 iaq.iaq_opcode = htole16(IXL_AQ_OP_NVM_READ); 6968 iaq.iaq_flags = htole16(IXL_AQ_BUF | 6969 ((len > I40E_AQ_LARGE_BUF) ? IXL_AQ_LB : 0)); 6970 iaq.iaq_datalen = htole16(len); 6971 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 6972 6973 param = (struct ixl_aq_nvm_param *)iaq.iaq_param; 6974 param->command_flags = IXL_AQ_NVM_LAST_CMD; 6975 param->module_pointer = 0; 6976 param->length = htole16(len); 6977 offset_bytes = (uint32_t)offset_word * 2; 6978 offset_bytes &= 0x00FFFFFF; 6979 param->offset = htole32(offset_bytes); 6980 6981 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 6982 BUS_DMASYNC_PREREAD); 6983 6984 rv = ixl_atq_poll(sc, &iaq, 250); 6985 6986 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 6987 BUS_DMASYNC_POSTREAD); 6988 6989 if (rv != 0) { 6990 return ETIMEDOUT; 6991 } 6992 6993 switch (le16toh(iaq.iaq_retval)) { 6994 case IXL_AQ_RC_OK: 6995 break; 6996 case IXL_AQ_RC_EPERM: 6997 return EPERM; 6998 case IXL_AQ_RC_EINVAL: 6999 return EINVAL; 7000 case IXL_AQ_RC_EBUSY: 7001 return EBUSY; 7002 case IXL_AQ_RC_EIO: 7003 default: 7004 return EIO; 7005 } 7006 7007 memcpy(data, IXL_DMA_KVA(idm), len); 7008 7009 return 0; 7010 } 7011 7012 static int 7013 ixl_rd16_nvm(struct ixl_softc *sc, uint16_t offset, uint16_t *data) 7014 { 7015 int error; 7016 uint16_t buf; 7017 7018 error = ixl_nvm_lock(sc, 'R'); 7019 if (error) 7020 return error; 7021 7022 if (ISSET(sc->sc_aq_flags, IXL_SC_AQ_FLAG_NVMREAD)) { 7023 error = ixl_nvm_read_aq(sc, offset, 7024 &buf, sizeof(buf)); 7025 if (error == 0) 7026 *data = le16toh(buf); 7027 } else { 7028 error = ixl_nvm_read_srctl(sc, offset, &buf); 7029 if (error == 0) 7030 *data = buf; 7031 } 7032 7033 ixl_nvm_unlock(sc); 7034 7035 return error; 7036 } 7037 7038 MODULE(MODULE_CLASS_DRIVER, if_ixl, "pci"); 7039 7040 #ifdef _MODULE 7041 #include "ioconf.c" 7042 #endif 7043 7044 #ifdef _MODULE 7045 static void 7046 ixl_parse_modprop(prop_dictionary_t dict) 7047 { 7048 prop_object_t obj; 7049 int64_t val; 7050 uint64_t uval; 7051 7052 if (dict == NULL) 7053 return; 7054 7055 obj = prop_dictionary_get(dict, "nomsix"); 7056 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_BOOL) { 7057 ixl_param_nomsix = prop_bool_true((prop_bool_t)obj); 7058 } 7059 7060 obj = prop_dictionary_get(dict, "stats_interval"); 7061 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7062 val = prop_number_signed_value((prop_number_t)obj); 7063 7064 /* the range has no reason */ 7065 if (100 < val && val < 180000) { 7066 ixl_param_stats_interval = val; 7067 } 7068 } 7069 7070 obj = prop_dictionary_get(dict, "nqps_limit"); 7071 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7072 val = prop_number_signed_value((prop_number_t)obj); 7073 7074 if (val <= INT32_MAX) 7075 ixl_param_nqps_limit = val; 7076 } 7077 7078 obj = prop_dictionary_get(dict, "rx_ndescs"); 7079 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7080 uval = prop_number_unsigned_integer_value((prop_number_t)obj); 7081 7082 if (uval > 8) 7083 ixl_param_rx_ndescs = uval; 7084 } 7085 7086 obj = prop_dictionary_get(dict, "tx_ndescs"); 7087 if (obj != NULL && prop_object_type(obj) == PROP_TYPE_NUMBER) { 7088 uval = prop_number_unsigned_integer_value((prop_number_t)obj); 7089 7090 if (uval > IXL_TX_PKT_DESCS) 7091 ixl_param_tx_ndescs = uval; 7092 } 7093 7094 } 7095 #endif 7096 7097 static int 7098 if_ixl_modcmd(modcmd_t cmd, void *opaque) 7099 { 7100 int error = 0; 7101 7102 #ifdef _MODULE 7103 switch (cmd) { 7104 case MODULE_CMD_INIT: 7105 ixl_parse_modprop((prop_dictionary_t)opaque); 7106 error = config_init_component(cfdriver_ioconf_if_ixl, 7107 cfattach_ioconf_if_ixl, cfdata_ioconf_if_ixl); 7108 break; 7109 case MODULE_CMD_FINI: 7110 error = config_fini_component(cfdriver_ioconf_if_ixl, 7111 cfattach_ioconf_if_ixl, cfdata_ioconf_if_ixl); 7112 break; 7113 default: 7114 error = ENOTTY; 7115 break; 7116 } 7117 #endif 7118 7119 return error; 7120 } 7121
Indexes created Fri Oct 17 03:10:13 GMT 2025