if_jmereg.h revision 1.2.2.2
1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.3 2008/09/22 06:17:21 yongari Exp $ 28 */ 29 30 #ifndef _IF_JMEREG_H 31 #define _IF_JMEREG_H 32 33 /* 34 * JMC250 PCI revisions 35 */ 36 #define DEVICEREVID_JMC250_A0 0x00 37 #define DEVICEREVID_JMC250_A2 0x11 38 39 /* 40 * JMC260 PCI revisions 41 */ 42 #define DEVICEREVID_JMC260_A0 0x00 43 44 /* JMC250 PCI configuration register. */ 45 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 46 47 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 48 49 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 50 51 #define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 52 53 #define JME_PCI_EROM 0x30 54 55 #define JME_PCI_DBG 0x9C 56 57 #define JME_PCI_SPI 0xB0 58 59 #define SPI_ENB 0x00000010 60 #define SPI_SO_STATUS 0x00000008 61 #define SPI_SI_CTRL 0x00000004 62 #define SPI_SCK_CTRL 0x00000002 63 #define SPI_CS_N_CTRL 0x00000001 64 65 #define JME_PCI_PHYCFG0 0xC0 66 67 #define JME_PCI_PHYCFG1 0xC4 68 69 #define JME_PCI_PHYCFG2 0xC8 70 71 #define JME_PCI_PHYCFG3 0xCC 72 73 #define JME_PCI_PIPECTL1 0xD0 74 75 #define JME_PCI_PIPECTL2 0xD4 76 77 /* PCIe link error/status. */ 78 #define JME_PCI_LES 0xD8 79 80 /* propeietary register 0. */ 81 #define JME_PCI_PE0 0xE0 82 #define PE0_SPI_EXIST 0x00200000 83 #define PE0_PME_D0 0x00100000 84 #define PE0_PME_D3H 0x00080000 85 #define PE0_PME_SPI_PAD 0x00040000 86 #define PE0_MASK_ASPM 0x00020000 87 #define PE0_EEPROM_RW_DIS 0x00008000 88 #define PE0_PCI_INTA 0x00001000 89 #define PE0_PCI_INTB 0x00002000 90 #define PE0_PCI_INTC 0x00003000 91 #define PE0_PCI_INTD 0x00004000 92 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 93 #define PE0_MSIX_SIZE_8 0x00000700 94 #define PE0_MSIX_SIZE_7 0x00000600 95 #define PE0_MSIX_SIZE_6 0x00000500 96 #define PE0_MSIX_SIZE_5 0x00000400 97 #define PE0_MSIX_SIZE_4 0x00000300 98 #define PE0_MSIX_SIZE_3 0x00000200 99 #define PE0_MSIX_SIZE_2 0x00000100 100 #define PE0_MSIX_SIZE_1 0x00000000 101 #define PE0_MSIX_SIZE_DEF 0x00000700 102 #define PE0_MSIX_CAP_DIS 0x00000080 103 #define PE0_MSI_PVMC_ENB 0x00000040 104 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 105 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 106 #define PE0_PM_AUXC_MASK 0x00000007 107 #define PE0_PM_AUXC_DEF 0x00000007 108 109 #define JME_PCI_PE1 0xE4 110 111 #define JME_PCI_PHYTEST 0xF8 112 113 #define JME_PCI_GPR 0xFC 114 115 /* 116 * JMC Register Map. 117 * ----------------------------------------------------------------------- 118 * Register Size IO space Memory space 119 * ----------------------------------------------------------------------- 120 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 121 * BAR1 + 0x7F BAR0 + 0x7F 122 * ----------------------------------------------------------------------- 123 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 124 * BAR2 + 0x7F BAR0 + 0x47F 125 * ----------------------------------------------------------------------- 126 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 127 * BAR2 + 0xfF BAR0 + 0x87F 128 * ----------------------------------------------------------------------- 129 * We use bus_space_subregion() to get handle for the 3 different 130 * register space. Register address are relative to the base of each 131 * region. 132 */ 133 134 /* Tx control and status. */ 135 #define JME_TXCSR 0x0000 136 #define TXCSR_QWEIGHT_MASK 0x0F000000 137 #define TXCSR_QWEIGHT_SHIFT 24 138 #define TXCSR_TXQ_SEL_MASK 0x00070000 139 #define TXCSR_TXQ_SEL_SHIFT 16 140 #define TXCSR_TXQ_START 0x00000001 141 #define TXCSR_TXQ_START_SHIFT 8 142 #define TXCSR_FIFO_THRESH_4QW 0x00000000 143 #define TXCSR_FIFO_THRESH_8QW 0x00000040 144 #define TXCSR_FIFO_THRESH_12QW 0x00000080 145 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 146 #define TXCSR_DMA_SIZE_64 0x00000000 147 #define TXCSR_DMA_SIZE_128 0x00000010 148 #define TXCSR_DMA_SIZE_256 0x00000020 149 #define TXCSR_DMA_SIZE_512 0x00000030 150 #define TXCSR_DMA_BURST 0x00000004 151 #define TXCSR_TX_SUSPEND 0x00000002 152 #define TXCSR_TX_ENB 0x00000001 153 #define TXCSR_TXQ0 0 154 #define TXCSR_TXQ1 1 155 #define TXCSR_TXQ2 2 156 #define TXCSR_TXQ3 3 157 #define TXCSR_TXQ4 4 158 #define TXCSR_TXQ5 5 159 #define TXCSR_TXQ6 6 160 #define TXCSR_TXQ7 7 161 #define TXCSR_TXQ_WEIGHT(x) \ 162 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 163 #define TXCSR_TXQ_WEIGHT_MIN 0 164 #define TXCSR_TXQ_WEIGHT_MAX 15 165 #define TXCSR_TXQ_N_SEL(x) \ 166 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 167 #define TXCSR_TXQ_N_START(x) \ 168 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 169 170 /* Tx queue descriptor base address. 16bytes alignment required. */ 171 #define JME_TXDBA_LO 0x0004 172 #define JME_TXDBA_HI 0x0008 173 174 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 175 #define JME_TXQDC 0x000C 176 #define TXQDC_MASK 0x0000007F0 177 178 /* Tx queue next descriptor address. */ 179 #define JME_TXNDA 0x0010 180 #define TXNDA_ADDR_MASK 0xFFFFFFF0 181 #define TXNDA_DESC_EMPTY 0x00000008 182 #define TXNDA_DESC_VALID 0x00000004 183 #define TXNDA_DESC_WAIT 0x00000002 184 #define TXNDA_DESC_FETCH 0x00000001 185 186 /* Tx MAC control ans status. */ 187 #define JME_TXMAC 0x0014 188 #define TXMAC_IFG2_MASK 0xC0000000 189 #define TXMAC_IFG2_DEFAULT 0x40000000 190 #define TXMAC_IFG1_MASK 0x30000000 191 #define TXMAC_IFG1_DEFAULT 0x20000000 192 #define TXMAC_THRESH_1_PKT 0x00000300 193 #define TXMAC_THRESH_1_2_PKT 0x00000200 194 #define TXMAC_THRESH_1_4_PKT 0x00000100 195 #define TXMAC_THRESH_1_8_PKT 0x00000000 196 #define TXMAC_FRAME_BURST 0x00000080 197 #define TXMAC_CARRIER_EXT 0x00000040 198 #define TXMAC_IFG_ENB 0x00000020 199 #define TXMAC_BACKOFF 0x00000010 200 #define TXMAC_CARRIER_SENSE 0x00000008 201 #define TXMAC_COLL_ENB 0x00000004 202 #define TXMAC_CRC_ENB 0x00000002 203 #define TXMAC_PAD_ENB 0x00000001 204 205 /* Tx pause frame control. */ 206 #define JME_TXPFC 0x0018 207 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 208 #define TXPFC_VLAN_TAG_SHIFT 16 209 #define TXPFC_VLAN_ENB 0x00008000 210 #define TXPFC_PAUSE_ENB 0x00000001 211 212 /* Tx timer/retry at half duplex. */ 213 #define JME_TXTRHD 0x001C 214 #define TXTRHD_RT_PERIOD_ENB 0x80000000 215 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 216 #define TXTRHD_RT_PERIOD_SHIFT 8 217 #define TXTRHD_RT_LIMIT_ENB 0x00000080 218 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 219 #define TXTRHD_RT_LIMIT_SHIFT 0 220 #define TXTRHD_RT_PERIOD_DEFAULT 8192 221 #define TXTRHD_RT_LIMIT_DEFAULT 8 222 223 /* Rx control & status. */ 224 #define JME_RXCSR 0x0020 225 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 226 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 227 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 228 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 229 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 230 #define RXCSR_FIFO_THRESH_16QW 0x00000000 231 #define RXCSR_FIFO_THRESH_32QW 0x04000000 232 #define RXCSR_FIFO_THRESH_64QW 0x08000000 233 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 234 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 235 #define RXCSR_DMA_SIZE_16 0x00000000 236 #define RXCSR_DMA_SIZE_32 0x01000000 237 #define RXCSR_DMA_SIZE_64 0x02000000 238 #define RXCSR_DMA_SIZE_128 0x03000000 239 #define RXCSR_RXQ_SEL_MASK 0x00030000 240 #define RXCSR_RXQ_SEL_SHIFT 16 241 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 242 #define RXCSR_DESC_RT_GAP_SHIFT 12 243 #define RXCSR_DESC_RT_GAP_256 0x00000000 244 #define RXCSR_DESC_RT_GAP_512 0x00001000 245 #define RXCSR_DESC_RT_GAP_1024 0x00002000 246 #define RXCSR_DESC_RT_GAP_2048 0x00003000 247 #define RXCSR_DESC_RT_GAP_4096 0x00004000 248 #define RXCSR_DESC_RT_GAP_8192 0x00005000 249 #define RXCSR_DESC_RT_GAP_16384 0x00006000 250 #define RXCSR_DESC_RT_GAP_32768 0x00007000 251 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 252 #define RXCSR_DESC_RT_CNT_SHIFT 8 253 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 254 #define RXCSR_PASS_MAGIC_PKT 0x00000020 255 #define RXCSR_PASS_RUNT_PKT 0x00000010 256 #define RXCSR_PASS_BAD_PKT 0x00000008 257 #define RXCSR_RXQ_START 0x00000004 258 #define RXCSR_RX_SUSPEND 0x00000002 259 #define RXCSR_RX_ENB 0x00000001 260 261 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 262 #define RXCSR_RXQ0 0 263 #define RXCSR_RXQ1 1 264 #define RXCSR_RXQ2 2 265 #define RXCSR_RXQ3 3 266 #define RXCSR_DESC_RT_CNT(x) \ 267 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 268 #define RXCSR_DESC_RT_CNT_DEFAULT 32 269 270 /* Rx queue descriptor base address. 16bytes alignment needed. */ 271 #define JME_RXDBA_LO 0x0024 272 #define JME_RXDBA_HI 0x0028 273 274 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 275 #define JME_RXQDC 0x002C 276 #define RXQDC_MASK 0x0000007F0 277 278 /* Rx queue next descriptor address. */ 279 #define JME_RXNDA 0x0030 280 #define RXNDA_ADDR_MASK 0xFFFFFFF0 281 #define RXNDA_DESC_EMPTY 0x00000008 282 #define RXNDA_DESC_VALID 0x00000004 283 #define RXNDA_DESC_WAIT 0x00000002 284 #define RXNDA_DESC_FETCH 0x00000001 285 286 /* Rx MAC control and status. */ 287 #define JME_RXMAC 0x0034 288 #define RXMAC_RSS_UNICAST 0x00000000 289 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 290 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 291 #define RXMAC_RSS_ALLFRAME 0x00030000 292 #define RXMAC_PROMISC 0x00000800 293 #define RXMAC_BROADCAST 0x00000400 294 #define RXMAC_MULTICAST 0x00000200 295 #define RXMAC_UNICAST 0x00000100 296 #define RXMAC_ALLMULTI 0x00000080 297 #define RXMAC_MULTICAST_FILTER 0x00000040 298 #define RXMAC_COLL_DET_ENB 0x00000020 299 #define RXMAC_FC_ENB 0x00000008 300 #define RXMAC_VLAN_ENB 0x00000004 301 #define RXMAC_PAD_10BYTES 0x00000002 302 #define RXMAC_CSUM_ENB 0x00000001 303 304 /* Rx unicast MAC address. */ 305 #define JME_PAR0 0x0038 306 #define JME_PAR1 0x003C 307 308 /* Rx multicast address hash table. */ 309 #define JME_MAR0 0x0040 310 #define JME_MAR1 0x0044 311 312 /* Wakeup frame output data port. */ 313 #define JME_WFODP 0x0048 314 315 /* Wakeup frame output interface. */ 316 #define JME_WFOI 0x004C 317 #define WFOI_MASK_0_31 0x00000000 318 #define WFOI_MASK_31_63 0x00000010 319 #define WFOI_MASK_64_95 0x00000020 320 #define WFOI_MASK_96_127 0x00000030 321 #define WFOI_MASK_SEL 0x00000008 322 #define WFOI_CRC_SEL 0x00000000 323 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 324 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 325 326 /* Station management interface. */ 327 #define JME_SMI 0x0050 328 #define SMI_DATA_MASK 0xFFFF0000 329 #define SMI_DATA_SHIFT 16 330 #define SMI_REG_ADDR_MASK 0x0000F800 331 #define SMI_REG_ADDR_SHIFT 11 332 #define SMI_PHY_ADDR_MASK 0x000007C0 333 #define SMI_PHY_ADDR_SHIFT 6 334 #define SMI_OP_WRITE 0x00000020 335 #define SMI_OP_READ 0x00000000 336 #define SMI_OP_EXECUTE 0x00000010 337 #define SMI_MDIO 0x00000008 338 #define SMI_MDOE 0x00000004 339 #define SMI_MDC 0x00000002 340 #define SMI_MDEN 0x00000001 341 #define SMI_REG_ADDR(x) \ 342 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 343 #define SMI_PHY_ADDR(x) \ 344 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 345 346 /* Global host control. */ 347 #define JME_GHC 0x0054 348 #define GHC_LOOPBACK 0x80000000 349 #define GHC_RESET 0x40000000 350 #define GHC_FULL_DUPLEX 0x00000040 351 #define GHC_SPEED_UNKNOWN 0x00000000 352 #define GHC_SPEED_10 0x00000010 353 #define GHC_SPEED_100 0x00000020 354 #define GHC_SPEED_1000 0x00000030 355 #define GHC_SPEED_MASK 0x00000030 356 #define GHC_LINK_OFF 0x00000004 357 #define GHC_LINK_ON 0x00000002 358 #define GHC_LINK_STAT_POLLING 0x00000001 359 360 /* Power management control and status. */ 361 #define JME_PMCS 0x0060 362 #define PMCS_WAKEUP_FRAME_7 0x80000000 363 #define PMCS_WAKEUP_FRAME_6 0x40000000 364 #define PMCS_WAKEUP_FRAME_5 0x20000000 365 #define PMCS_WAKEUP_FRAME_4 0x10000000 366 #define PMCS_WAKEUP_FRAME_3 0x08000000 367 #define PMCS_WAKEUP_FRAME_2 0x04000000 368 #define PMCS_WAKEUP_FRAME_1 0x02000000 369 #define PMCS_WAKEUP_FRAME_0 0x01000000 370 #define PMCS_LINK_FAIL 0x00040000 371 #define PMCS_LINK_RISING 0x00020000 372 #define PMCS_MAGIC_FRAME 0x00010000 373 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 374 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 375 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 376 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 377 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 378 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 379 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 380 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 381 #define PMCS_LINK_FAIL_ENB 0x00000004 382 #define PMCS_LINK_RISING_ENB 0x00000002 383 #define PMCS_MAGIC_FRAME_ENB 0x00000001 384 #define PMCS_WOL_ENB_MASK 0x0000FFFF 385 386 387 #define JME_PHY_EEPROM_BASE_MEMOFF 0x0400 388 #define JME_PHY_EEPROM_BASE_IOOFF 0x0000 389 #define JME_PHY_EEPROM_SIZE 0x0080 390 /* Giga PHY & EEPROM registers. */ 391 #define JME_PHY_EEPROM_BASE_ADDR 0x00 392 393 #define JME_GIGAR0LO 0x00 394 #define JME_GIGAR0HI 0x04 395 #define JME_GIGARALO 0x08 396 #define JME_GIGARAHI 0x0C 397 #define JME_GIGARBLO 0x10 398 #define JME_GIGARBHI 0x14 399 #define JME_GIGARCLO 0x18 400 #define JME_GIGARCHI 0x1C 401 #define JME_GIGARDLO 0x20 402 #define JME_GIGARDHI 0x24 403 404 /* BIST status and control. */ 405 #define JME_GIGACSR 0x28 406 #define GIGACSR_STATUS 0x40000000 407 #define GIGACSR_CTRL_MASK 0x30000000 408 #define GIGACSR_CTRL_DEFAULT 0x30000000 409 #define GIGACSR_TX_CLK_MASK 0x0F000000 410 #define GIGACSR_RX_CLK_MASK 0x00F00000 411 #define GIGACSR_TX_CLK_INV 0x00080000 412 #define GIGACSR_RX_CLK_INV 0x00040000 413 #define GIGACSR_PHY_RST 0x00010000 414 #define GIGACSR_IRQ_N_O 0x00001000 415 #define GIGACSR_BIST_OK 0x00000200 416 #define GIGACSR_BIST_DONE 0x00000100 417 #define GIGACSR_BIST_LED_ENB 0x00000010 418 #define GIGACSR_BIST_MASK 0x00000003 419 420 /* PHY Link Status. */ 421 #define JME_LNKSTS 0x30 422 #define LINKSTS_SPEED_10 0x00000000 423 #define LINKSTS_SPEED_100 0x00004000 424 #define LINKSTS_SPEED_1000 0x00008000 425 #define LINKSTS_FULL_DUPLEX 0x00002000 426 #define LINKSTS_PAGE_RCVD 0x00001000 427 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 428 #define LINKSTS_UP 0x00000400 429 #define LINKSTS_ANEG_COMP 0x00000200 430 #define LINKSTS_MDI_CROSSOVR 0x00000040 431 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 432 #define LINKSTS_LPAR_PAUSE 0x00000001 433 434 /* SMB control and status. */ 435 #define JME_SMBCSR 0x40 436 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 437 #define SMBCSR_WR_DATA_NACK 0x00040000 438 #define SMBCSR_CMD_NACK 0x00020000 439 #define SMBCSR_RELOAD 0x00010000 440 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 441 #define SMBCSR_SCL_STAT 0x00000080 442 #define SMBCSR_SDA_STAT 0x00000040 443 #define SMBCSR_EEPROM_PRESENT 0x00000020 444 #define SMBCSR_INIT_LD_DONE 0x00000010 445 #define SMBCSR_HW_BUSY_MASK 0x0000000F 446 #define SMBCSR_HW_IDLE 0x00000000 447 448 /* SMB interface. */ 449 #define JME_SMBINTF 0x44 450 #define SMBINTF_RD_DATA_MASK 0xFF000000 451 #define SMBINTF_RD_DATA_SHIFT 24 452 #define SMBINTF_WR_DATA_MASK 0x00FF0000 453 #define SMBINTF_WR_DATA_SHIFT 16 454 #define SMBINTF_ADDR_MASK 0x0000FF00 455 #define SMBINTF_ADDR_SHIFT 8 456 #define SMBINTF_RD 0x00000020 457 #define SMBINTF_WR 0x00000000 458 #define SMBINTF_CMD_TRIGGER 0x00000010 459 #define SMBINTF_BUSY 0x00000010 460 #define SMBINTF_FAST_MODE 0x00000008 461 #define SMBINTF_GPIO_SCL 0x00000004 462 #define SMBINTF_GPIO_SDA 0x00000002 463 #define SMBINTF_GPIO_ENB 0x00000001 464 465 #define JME_EEPROM_SIG0 0x55 466 #define JME_EEPROM_SIG1 0xAA 467 #define JME_EEPROM_DESC_BYTES 3 468 #define JME_EEPROM_DESC_END 0x80 469 #define JME_EEPROM_FUNC_MASK 0x70 470 #define JME_EEPROM_FUNC_SHIFT 4 471 #define JME_EEPROM_PAGE_MASK 0x0F 472 #define JME_EEPROM_PAGE_SHIFT 0 473 474 #define JME_EEPROM_FUNC0 0 475 /* PCI configuration space. */ 476 #define JME_EEPROM_PAGE_BAR0 0 477 /* 128 bytes I/O window. */ 478 #define JME_EEPROM_PAGE_BAR1 1 479 /* 256 bytes I/O window. */ 480 #define JME_EEPROM_PAGE_BAR2 2 481 482 #define JME_EEPROM_END 0xFF 483 484 #define JME_EEPROM_MKDESC(f, p) \ 485 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 486 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 487 488 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 489 #define JME_EEPINTF 0x48 490 #define EEPINTF_DATA_MASK 0xFFFF0000 491 #define EEPINTF_DATA_SHIFT 16 492 #define EEPINTF_ADDR_MASK 0x0000FC00 493 #define EEPINTF_ADDR_SHIFT 10 494 #define EEPRINTF_OP_MASK 0x00000300 495 #define EEPINTF_OP_EXECUTE 0x00000080 496 #define EEPINTF_DATA_OUT 0x00000008 497 #define EEPINTF_DATA_IN 0x00000004 498 #define EEPINTF_CLK 0x00000002 499 #define EEPINTF_SEL 0x00000001 500 501 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 502 #define JME_EEPCSR 0x4C 503 #define EEPCSR_EEPROM_RELOAD 0x00000002 504 #define EEPCSR_EEPROM_PRESENT 0x00000001 505 506 /* Misc registers. */ 507 #define JME_MISC_BASE_MEMOFF 0x800 508 #define JME_MISC_BASE_IOOFF 0x080 509 #define JME_MISC_SIZE 0x080 510 511 /* Timer control and status. */ 512 #define JME_TMCSR 0x00 513 #define TMCSR_SW_INTR 0x80000000 514 #define TMCSR_TIMER_INTR 0x10000000 515 #define TMCSR_TIMER_ENB 0x01000000 516 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 517 518 /* GPIO control and status. */ 519 #define JME_GPIO 0x04 520 #define GPIO_4_SPI_IN 0x80000000 521 #define GPIO_3_SPI_IN 0x40000000 522 #define GPIO_4_SPI_OUT 0x20000000 523 #define GPIO_4_SPI_OUT_ENB 0x10000000 524 #define GPIO_3_SPI_OUT 0x08000000 525 #define GPIO_3_SPI_OUT_ENB 0x04000000 526 #define GPIO_3_4_LED 0x00000000 527 #define GPIO_3_4_GPIO 0x02000000 528 #define GPIO_2_CLKREQN_IN 0x00100000 529 #define GPIO_2_CLKREQN_OUT 0x00040000 530 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 531 #define GPIO_1_LED42_IN 0x00001000 532 #define GPIO_1_LED42_OUT 0x00000400 533 #define GPIO_1_LED42_OUT_ENB 0x00000200 534 #define GPIO_1_LED42_ENB 0x00000100 535 #define GPIO_0_SDA_IN 0x00000010 536 #define GPIO_0_SDA_OUT 0x00000004 537 #define GPIO_0_SDA_OUT_ENB 0x00000002 538 #define GPIO_0_SDA_ENB 0x00000001 539 540 /* General purpose register 0. */ 541 #define JME_GPREG0 0x08 542 #define GPREG0_SH_POST_DW7_DIS 0x80000000 543 #define GPREG0_SH_POST_DW6_DIS 0x40000000 544 #define GPREG0_SH_POST_DW5_DIS 0x20000000 545 #define GPREG0_SH_POST_DW4_DIS 0x10000000 546 #define GPREG0_SH_POST_DW3_DIS 0x08000000 547 #define GPREG0_SH_POST_DW2_DIS 0x04000000 548 #define GPREG0_SH_POST_DW1_DIS 0x02000000 549 #define GPREG0_SH_POST_DW0_DIS 0x01000000 550 #define GPREG0_DMA_RD_REQ_8 0x00000000 551 #define GPREG0_DMA_RD_REQ_6 0x00100000 552 #define GPREG0_DMA_RD_REQ_5 0x00200000 553 #define GPREG0_DMA_RD_REQ_4 0x00300000 554 #define GPREG0_POST_DW0_ENB 0x00040000 555 #define GPREG0_PCC_CLR_DIS 0x00020000 556 #define GPREG0_FORCE_SCL_OUT 0x00010000 557 #define GPREG0_DL_RSTB_DIS 0x00008000 558 #define GPREG0_STICKY_RESET 0x00004000 559 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 560 #define GPREG0_LINK_CHG_POLL 0x00001000 561 #define GPREG0_LINK_CHG_DIRECT 0x00000000 562 #define GPREG0_MSI_GEN_SEL 0x00000800 563 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 564 #define GPREG0_PCC_UNIT_16US 0x00000000 565 #define GPREG0_PCC_UNIT_256US 0x00000100 566 #define GPREG0_PCC_UNIT_US 0x00000200 567 #define GPREG0_PCC_UNIT_MS 0x00000300 568 #define GPREG0_PCC_UNIT_MASK 0x00000300 569 #define GPREG0_INTR_EVENT_ENB 0x00000080 570 #define GPREG0_PME_ENB 0x00000020 571 #define GPREG0_PHY_ADDR_MASK 0x0000001F 572 #define GPREG0_PHY_ADDR_SHIFT 0 573 #define GPREG0_PHY_ADDR 1 574 575 /* General purpose register 1. */ 576 #define JME_GPREG1 0x0C 577 #define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 578 #define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 579 #define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 580 #define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 581 #define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 582 #define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 583 #define GPREG1_INTDLY_MASK 0x00000007 584 585 /* MSIX entry number of interrupt source. */ 586 #define JME_MSINUM_BASE 0x10 587 #define JME_MSINUM_END 0x1F 588 #define MSINUM_MASK 0x7FFFFFFF 589 #define MSINUM_ENTRY_MASK 7 590 #define MSINUM_REG_INDEX(x) ((x) / 8) 591 #define MSINUM_INTR_SOURCE(x, y) \ 592 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 593 #define MSINUM_NUM_INTR_SOURCE 32 594 595 /* Interrupt event status. */ 596 #define JME_INTR_STATUS 0x20 597 #define INTR_SW 0x80000000 598 #define INTR_TIMER 0x40000000 599 #define INTR_LINKCHG 0x20000000 600 #define INTR_PAUSE 0x10000000 601 #define INTR_MAGIC_PKT 0x08000000 602 #define INTR_WAKEUP_PKT 0x04000000 603 #define INTR_RXQ0_COAL_TO 0x02000000 604 #define INTR_RXQ1_COAL_TO 0x01000000 605 #define INTR_RXQ2_COAL_TO 0x00800000 606 #define INTR_RXQ3_COAL_TO 0x00400000 607 #define INTR_TXQ_COAL_TO 0x00200000 608 #define INTR_RXQ0_COAL 0x00100000 609 #define INTR_RXQ1_COAL 0x00080000 610 #define INTR_RXQ2_COAL 0x00040000 611 #define INTR_RXQ3_COAL 0x00020000 612 #define INTR_TXQ_COAL 0x00010000 613 #define INTR_RXQ3_DESC_EMPTY 0x00008000 614 #define INTR_RXQ2_DESC_EMPTY 0x00004000 615 #define INTR_RXQ1_DESC_EMPTY 0x00002000 616 #define INTR_RXQ0_DESC_EMPTY 0x00001000 617 #define INTR_RXQ3_COMP 0x00000800 618 #define INTR_RXQ2_COMP 0x00000400 619 #define INTR_RXQ1_COMP 0x00000200 620 #define INTR_RXQ0_COMP 0x00000100 621 #define INTR_TXQ7_COMP 0x00000080 622 #define INTR_TXQ6_COMP 0x00000040 623 #define INTR_TXQ5_COMP 0x00000020 624 #define INTR_TXQ4_COMP 0x00000010 625 #define INTR_TXQ3_COMP 0x00000008 626 #define INTR_TXQ2_COMP 0x00000004 627 #define INTR_TXQ1_COMP 0x00000002 628 #define INTR_TXQ0_COMP 0x00000001 629 630 #define INTR_RXQ_COAL_TO \ 631 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 632 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 633 634 #define INTR_RXQ_COAL \ 635 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 636 INTR_RXQ3_COAL) 637 638 #define INTR_RXQ_COMP \ 639 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 640 INTR_RXQ3_COMP) 641 642 #define INTR_RXQ_DESC_EMPTY \ 643 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 644 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 645 646 #define INTR_RXQ_COMP \ 647 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 648 INTR_RXQ3_COMP) 649 650 #define INTR_TXQ_COMP \ 651 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 652 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 653 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 654 655 #define JME_INTRS_ENABLE \ 656 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 657 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 658 659 #define JME_INTRS_CHECK (JME_INTRS_ENABLE | INTR_TXQ_COMP | INTR_RXQ_COMP) 660 661 662 #define N_INTR_SW 31 663 #define N_INTR_TIMER 30 664 #define N_INTR_LINKCHG 29 665 #define N_INTR_PAUSE 28 666 #define N_INTR_MAGIC_PKT 27 667 #define N_INTR_WAKEUP_PKT 26 668 #define N_INTR_RXQ0_COAL_TO 25 669 #define N_INTR_RXQ1_COAL_TO 24 670 #define N_INTR_RXQ2_COAL_TO 23 671 #define N_INTR_RXQ3_COAL_TO 22 672 #define N_INTR_TXQ_COAL_TO 21 673 #define N_INTR_RXQ0_COAL 20 674 #define N_INTR_RXQ1_COAL 19 675 #define N_INTR_RXQ2_COAL 18 676 #define N_INTR_RXQ3_COAL 17 677 #define N_INTR_TXQ_COAL 16 678 #define N_INTR_RXQ3_DESC_EMPTY 15 679 #define N_INTR_RXQ2_DESC_EMPTY 14 680 #define N_INTR_RXQ1_DESC_EMPTY 13 681 #define N_INTR_RXQ0_DESC_EMPTY 12 682 #define N_INTR_RXQ3_COMP 11 683 #define N_INTR_RXQ2_COMP 10 684 #define N_INTR_RXQ1_COMP 9 685 #define N_INTR_RXQ0_COMP 8 686 #define N_INTR_TXQ7_COMP 7 687 #define N_INTR_TXQ6_COMP 6 688 #define N_INTR_TXQ5_COMP 5 689 #define N_INTR_TXQ4_COMP 4 690 #define N_INTR_TXQ3_COMP 3 691 #define N_INTR_TXQ2_COMP 2 692 #define N_INTR_TXQ1_COMP 1 693 #define N_INTR_TXQ0_COMP 0 694 695 /* Interrupt request status. */ 696 #define JME_INTR_REQ_STATUS 0x24 697 698 /* Interrupt enable - setting port. */ 699 #define JME_INTR_MASK_SET 0x28 700 701 /* Interrupt enable - clearing port. */ 702 #define JME_INTR_MASK_CLR 0x2C 703 704 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 705 #define JME_PCCRX0 0x30 706 #define JME_PCCRX1 0x34 707 #define JME_PCCRX2 0x38 708 #define JME_PCCRX3 0x3C 709 #define PCCRX_COAL_TO_MASK 0xFFFF0000 710 #define PCCRX_COAL_TO_SHIFT 16 711 #define PCCRX_COAL_PKT_MASK 0x0000FF00 712 #define PCCRX_COAL_PKT_SHIFT 8 713 714 #define PCCRX_COAL_TO_MIN 1 715 #define PCCRX_COAL_TO_DEFAULT 100 716 #define PCCRX_COAL_TO_MAX 65535 717 718 #define PCCRX_COAL_PKT_MIN 1 719 #define PCCRX_COAL_PKT_DEFAULT 128 720 #define PCCRX_COAL_PKT_MAX 255 721 722 /* Packet completion coalescing control of Tx queue. */ 723 #define JME_PCCTX 0x40 724 #define PCCTX_COAL_TO_MASK 0xFFFF0000 725 #define PCCTX_COAL_TO_SHIFT 16 726 #define PCCTX_COAL_PKT_MASK 0x0000FF00 727 #define PCCTX_COAL_PKT_SHIFT 8 728 #define PCCTX_COAL_TXQ7 0x00000080 729 #define PCCTX_COAL_TXQ6 0x00000040 730 #define PCCTX_COAL_TXQ5 0x00000020 731 #define PCCTX_COAL_TXQ4 0x00000010 732 #define PCCTX_COAL_TXQ3 0x00000008 733 #define PCCTX_COAL_TXQ2 0x00000004 734 #define PCCTX_COAL_TXQ1 0x00000002 735 #define PCCTX_COAL_TXQ0 0x00000001 736 737 #define PCCTX_COAL_TO_MIN 1 738 #define PCCTX_COAL_TO_DEFAULT 100 739 #define PCCTX_COAL_TO_MAX 65535 740 741 #define PCCTX_COAL_PKT_MIN 1 742 #define PCCTX_COAL_PKT_DEFAULT 128 743 #define PCCTX_COAL_PKT_MAX 255 744 745 /* Chip mode and FPGA version. */ 746 #define JME_CHIPMODE 0x44 747 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 748 #define CHIPMODE_FPGA_REV_SHIFT 16 749 #define CHIPMODE_NOT_FPGA 0 750 #define CHIPMODE_REV_MASK 0x0000FF00 751 #define CHIPMODE_REV_SHIFT 8 752 #define CHIPMODE_MODE_48P 0x0000000C 753 #define CHIPMODE_MODE_64P 0x00000004 754 #define CHIPMODE_MODE_128P_MAC 0x00000003 755 #define CHIPMODE_MODE_128P_DBG 0x00000002 756 #define CHIPMODE_MODE_128P_PHY 0x00000000 757 758 /* Shadow status base address high/low. */ 759 #define JME_SHBASE_ADDR_HI 0x48 760 #define JME_SHBASE_ADDR_LO 0x4C 761 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 762 #define SHBASE_POST_FORCE 0x00000002 763 #define SHBASE_POST_ENB 0x00000001 764 765 /* Timer 1 and 2. */ 766 #define JME_TIMER1 0x70 767 #define JME_TIMER2 0x74 768 #define TIMER_ENB 0x01000000 769 #define TIMER_CNT_MASK 0x00FFFFFF 770 #define TIMER_CNT_SHIFT 0 771 #define TIMER_UNIT 1024 /* 1024us */ 772 773 /* Aggresive power mode control. */ 774 #define JME_APMC 0x7C 775 #define APMC_PCIE_SDOWN_STAT 0x80000000 776 #define APMC_PCIE_SDOWN_ENB 0x40000000 777 #define APMC_PSEUDO_HOT_PLUG 0x20000000 778 #define APMC_EXT_PLUGIN_ENB 0x04000000 779 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 780 #define APMC_DIS_SRAM 0x00000004 781 #define APMC_DIS_CLKPM 0x00000002 782 #define APMC_DIS_CLKTX 0x00000001 783 784 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 785 #define JME_PCCSRX_BASE 0x80 786 #define JME_PCCSRX_END 0x8F 787 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 788 #define PCCSRX_TO_MASK 0xFFFF0000 789 #define PCCSRX_TO_SHIFT 16 790 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 791 #define PCCSRX_PKT_CNT_SHIFT 8 792 793 /* Packet completion coalesing status of Tx queue. */ 794 #define JME_PCCSTX 0x90 795 #define PCCSTX_TO_MASK 0xFFFF0000 796 #define PCCSTX_TO_SHIFT 16 797 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 798 #define PCCSTX_PKT_CNT_SHIFT 8 799 800 /* Tx queues empty indicator. */ 801 #define JME_TXQEMPTY 0x94 802 #define TXQEMPTY_TXQ7 0x00000080 803 #define TXQEMPTY_TXQ6 0x00000040 804 #define TXQEMPTY_TXQ5 0x00000020 805 #define TXQEMPTY_TXQ4 0x00000010 806 #define TXQEMPTY_TXQ3 0x00000008 807 #define TXQEMPTY_TXQ2 0x00000004 808 #define TXQEMPTY_TXQ1 0x00000002 809 #define TXQEMPTY_TXQ0 0x00000001 810 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 811 812 /* RSS control registers. */ 813 #define JME_RSS_BASE 0x0C00 814 815 #define JME_RSSC 0x0C00 816 #define RSSC_HASH_LEN_MASK 0x0000E000 817 #define RSSC_HASH_64_ENTRY 0x0000A000 818 #define RSSC_HASH_128_ENTRY 0x0000E000 819 #define RSSC_HASH_NONE 0x00001000 820 #define RSSC_HASH_IPV6 0x00000800 821 #define RSSC_HASH_IPV4 0x00000400 822 #define RSSC_HASH_IPV6_TCP 0x00000200 823 #define RSSC_HASH_IPV4_TCP 0x00000100 824 #define RSSC_NCPU_MASK 0x000000F8 825 #define RSSC_NCPU_SHIFT 3 826 #define RSSC_DIS_RSS 0x00000000 827 #define RSSC_2RXQ_ENB 0x00000001 828 #define RSSS_4RXQ_ENB 0x00000002 829 830 /* CPU vector. */ 831 #define JME_RSSCPU 0x0C04 832 #define RSSCPU_N_SEL(x) ((1 << (x)) 833 834 /* RSS Hash value. */ 835 #define JME_RSSHASH 0x0C10 836 837 #define JME_RSSHASH_STAT 0x0C14 838 839 #define JME_RSS_RDATA0 0x0C18 840 841 #define JME_RSS_RDATA1 0x0C1C 842 843 /* RSS secret key. */ 844 #define JME_RSSKEY_BASE 0x0C40 845 #define JME_RSSKEY_LAST 0x0C64 846 #define JME_RSSKEY_END 0x0C67 847 #define HASHKEY_NBYTES 40 848 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 849 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 850 851 /* RSS indirection table entries. */ 852 #define JME_RSSTBL_BASE 0x0C80 853 #define JME_RSSTBL_END 0x0CFF 854 #define RSSTBL_NENTRY 128 855 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 856 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 857 858 /* MSI-X table. */ 859 #define JME_MSIX_BASE_ADDR 0x2000 860 861 #define JME_MSIX_BASE 0x2000 862 #define JME_MSIX_END 0x207F 863 #define JME_MSIX_NENTRY 8 864 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 865 #define MSIX_ADDR_HI_OFF 0x00 866 #define MSIX_ADDR_LO_OFF 0x04 867 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 868 #define MSIX_DATA_OFF 0x08 869 #define MSIX_VECTOR_OFF 0x0C 870 #define MSIX_VECTOR_RSVD 0x80000000 871 #define MSIX_VECTOR_DIS 0x00000001 872 873 /* MSI-X PBA. */ 874 #define JME_MSIX_PBA_BASE_ADDR 0x3000 875 876 #define JME_MSIX_PBA 0x3000 877 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 878 #define MSIX_PBA_RSVD_SHIFT 8 879 #define MSIX_PBA_PEND_MASK 0x000000FF 880 #define MSIX_PBA_PEND_SHIFT 0 881 #define MSIX_PBA_PEND_ENTRY7 0x00000080 882 #define MSIX_PBA_PEND_ENTRY6 0x00000040 883 #define MSIX_PBA_PEND_ENTRY5 0x00000020 884 #define MSIX_PBA_PEND_ENTRY4 0x00000010 885 #define MSIX_PBA_PEND_ENTRY3 0x00000008 886 #define MSIX_PBA_PEND_ENTRY2 0x00000004 887 #define MSIX_PBA_PEND_ENTRY1 0x00000002 888 #define MSIX_PBA_PEND_ENTRY0 0x00000001 889 890 #define JME_PHY_OUI 0x001B8C 891 #define JME_PHY_MODEL 0x21 892 #define JME_PHY_REV 0x01 893 #define JME_PHY_ADDR 1 894 895 /* JMC250 shadow status block. */ 896 struct jme_ssb { 897 uint32_t dw0; 898 uint32_t dw1; 899 uint32_t dw2; 900 uint32_t dw3; 901 uint32_t dw4; 902 uint32_t dw5; 903 uint32_t dw6; 904 uint32_t dw7; 905 }; 906 907 /* JMC250 descriptor structures. */ 908 struct jme_desc { 909 uint32_t flags; 910 uint32_t buflen; 911 uint32_t addr_hi; 912 uint32_t addr_lo; 913 }; 914 915 #define JME_TD_OWN 0x80000000 916 #define JME_TD_INTR 0x40000000 917 #define JME_TD_64BIT 0x20000000 918 #define JME_TD_TCPCSUM 0x10000000 919 #define JME_TD_UDPCSUM 0x08000000 920 #define JME_TD_IPCSUM 0x04000000 921 #define JME_TD_TSO 0x02000000 922 #define JME_TD_VLAN_TAG 0x01000000 923 #define JME_TD_VLAN_MASK 0x0000FFFF 924 925 #define JME_TD_MSS_MASK 0xFFFC0000 926 #define JME_TD_MSS_SHIFT 18 927 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 928 #define JME_TD_BUF_LEN_SHIFT 0 929 930 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 931 #define JME_TD_FRAME_LEN_SHIFT 0 932 933 /* 934 * Only the first Tx descriptor of a packet is updated 935 * after packet transmission. 936 */ 937 #define JME_TD_TMOUT 0x20000000 938 #define JME_TD_RETRY_EXP 0x10000000 939 #define JME_TD_COLLISION 0x08000000 940 #define JME_TD_UNDERRUN 0x04000000 941 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 942 #define JME_TD_EHDR_SIZE_SHIFT 0 943 944 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 945 #define JME_TD_SEG_CNT_SHIFT 16 946 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 947 #define JME_TD_RETRY_CNT_SHIFT 0 948 949 #define JME_RD_OWN 0x80000000 950 #define JME_RD_INTR 0x40000000 951 #define JME_RD_64BIT 0x20000000 952 953 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 954 #define JME_RD_BUF_LEN_SHIFT 0 955 956 /* 957 * Only the first Rx descriptor of a packet is updated 958 * after packet reception. 959 */ 960 #define JME_RD_MORE_FRAG 0x20000000 961 #define JME_RD_TCP 0x10000000 962 #define JME_RD_UDP 0x08000000 963 #define JME_RD_IPCSUM 0x04000000 964 #define JME_RD_TCPCSUM 0x02000000 965 #define JME_RD_UDPCSUM 0x01000000 966 #define JME_RD_VLAN_TAG 0x00800000 967 #define JME_RD_IPV4 0x00400000 968 #define JME_RD_IPV6 0x00200000 969 #define JME_RD_PAUSE 0x00100000 970 #define JME_RD_MAGIC 0x00080000 971 #define JME_RD_WAKEUP 0x00040000 972 #define JME_RD_BCAST 0x00030000 973 #define JME_RD_MCAST 0x00020000 974 #define JME_RD_UCAST 0x00010000 975 #define JME_RD_VLAN_MASK 0x0000FFFF 976 #define JME_RD_VLAN_SHIFT 0 977 #define JME_RD_TCPV4 (JME_RD_IPV4|JME_RD_TCP) 978 #define JME_RD_UDPV4 (JME_RD_IPV4|JME_RD_UDP) 979 #define JME_RD_TCPV6 (JME_RD_IPV6|JME_RD_TCP) 980 #define JME_RD_UDPV6 (JME_RD_IPV6|JME_RD_UDP) 981 982 #define JME_RD_VALID 0x80000000 983 #define JME_RD_CNT_MASK 0x7F000000 984 #define JME_RD_CNT_SHIFT 24 985 #define JME_RD_GIANT 0x00800000 986 #define JME_RD_GMII_ERR 0x00400000 987 #define JME_RD_NBL_RCVD 0x00200000 988 #define JME_RD_COLL 0x00100000 989 #define JME_RD_ABORT 0x00080000 990 #define JME_RD_RUNT 0x00040000 991 #define JME_RD_FIFO_OVRN 0x00020000 992 #define JME_RD_CRC_ERR 0x00010000 993 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 994 995 #define JME_RX_ERR_STAT \ 996 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 997 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 998 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 999 1000 #define JME_RD_ERR_MASK 0x00FF0000 1001 #define JME_RD_ERR_SHIFT 16 1002 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1003 #define JME_RX_ERR_BITS "\20" \ 1004 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1005 "\5COLL\6NBLRCVD\7GMIIERR\10" 1006 1007 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1008 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1009 #define JME_RX_PAD_BYTES 10 1010 1011 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1012 1013 #define JME_RD_RSS_HASH_MASK 0x00003F00 1014 #define JME_RD_RSS_HASH_SHIFT 8 1015 #define JME_RD_RSS_HASH_NONE 0x00000000 1016 #define JME_RD_RSS_HASH_IPV4 0x00000100 1017 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1018 #define JME_RD_RSS_HASH_IPV6 0x00000400 1019 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1020 #define JME_RD_HASH_FN_NONE 0x00000000 1021 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1022 1023 #define JME_MAX_TX_LEN 65535 1024 #define JME_MAX_RX_LEN 65535 1025 1026 #define JME_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 1027 #define JME_ADDR_HI(x) ((uint64_t) (x) >> 32) 1028 1029 /* 1030 * JMC250 can't handle Tx checksum offload/TSO if frame length 1031 * is larger than its FIFO size(2K). It's also good idea to not 1032 * use jumbo frame if hardware is running at half-duplex media. 1033 * Because the jumbo frame may not fit into the Tx FIFO, 1034 * collisions make hardware fetch frame from host memory with 1035 * DMA again which in turn slows down Tx performance 1036 * significantly. 1037 */ 1038 #define JME_TX_FIFO_SIZE 2000 1039 /* 1040 * JMC250 has just 4K Rx FIFO. To support jumbo frame that is 1041 * larger than 4K bytes in length, Rx FIFO threshold should be 1042 * adjusted to minimize Rx FIFO overrun. 1043 */ 1044 #define JME_RX_FIFO_SIZE 4000 1045 1046 #endif 1047
Indexes created Tue Oct 28 07:09:57 GMT 2025