if_jmereg.h revision 1.4
1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.3 2008/09/22 06:17:21 yongari Exp $ 28 */ 29 30 #ifndef _IF_JMEREG_H 31 #define _IF_JMEREG_H 32 33 /* 34 * JMC250 PCI revisions 35 */ 36 #define DEVICEREVID_JMC250_A0 0x00 37 #define DEVICEREVID_JMC250_A2 0x11 38 39 /* 40 * JMC260 PCI revisions 41 */ 42 #define DEVICEREVID_JMC260_A0 0x00 43 44 /* JMC250 PCI configuration register. */ 45 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 46 47 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 48 49 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 50 51 #define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 52 53 #define JME_PCI_EROM 0x30 54 55 #define JME_PCI_DBG 0x9C 56 57 #define JME_PCI_SPI 0xB0 58 59 #define SPI_ENB 0x00000010 60 #define SPI_SO_STATUS 0x00000008 61 #define SPI_SI_CTRL 0x00000004 62 #define SPI_SCK_CTRL 0x00000002 63 #define SPI_CS_N_CTRL 0x00000001 64 65 #define JME_EFUSE_CTL1 0xB8 66 #define EFUSE_CTL1_DATA_MASK 0xF0000000 67 #define EFUSE_CTL1_EXECUTE 0x08000000 68 #define EFUSE_CTL1_CMD_AUTOLOAD 0x02000000 69 #define EFUSE_CTL1_CMD_READ 0x04000000 70 #define EFUSE_CTL1_CMD_BLOW 0x06000000 71 #define EFUSE_CTL1_CMD_MASK 0x06000000 72 #define EFUSE_CTL1_AUTOLOAD_ERR 0x00010000 73 #define EFUSE_CTL1_BYTE_SEL_MASK 0x0000FF00 74 #define EFUSE_CTL1_BIT_SEL_MASK 0x00000070 75 #define EFUSE_CTL1_AUTOLAOD_DONE 0x00000001 76 77 #define JME_EFUSE_CTL2 0xBC 78 #define EFUSE_CTL2_RESET 0x00008000 79 80 #define JME_PCI_PHYCFG0 0xC0 81 82 #define JME_PCI_PHYCFG1 0xC4 83 84 #define JME_PCI_PHYCFG2 0xC8 85 86 #define JME_PCI_PHYCFG3 0xCC 87 88 #define JME_PCI_PIPECTL1 0xD0 89 90 #define JME_PCI_PIPECTL2 0xD4 91 92 /* PCIe link error/status. */ 93 #define JME_PCI_LES 0xD8 94 95 /* propeietary register 0. */ 96 #define JME_PCI_PE0 0xE0 97 #define PE0_SPI_EXIST 0x00200000 98 #define PE0_PME_D0 0x00100000 99 #define PE0_PME_D3H 0x00080000 100 #define PE0_PME_SPI_PAD 0x00040000 101 #define PE0_MASK_ASPM 0x00020000 102 #define PE0_EEPROM_RW_DIS 0x00008000 103 #define PE0_PCI_INTA 0x00001000 104 #define PE0_PCI_INTB 0x00002000 105 #define PE0_PCI_INTC 0x00003000 106 #define PE0_PCI_INTD 0x00004000 107 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 108 #define PE0_MSIX_SIZE_8 0x00000700 109 #define PE0_MSIX_SIZE_7 0x00000600 110 #define PE0_MSIX_SIZE_6 0x00000500 111 #define PE0_MSIX_SIZE_5 0x00000400 112 #define PE0_MSIX_SIZE_4 0x00000300 113 #define PE0_MSIX_SIZE_3 0x00000200 114 #define PE0_MSIX_SIZE_2 0x00000100 115 #define PE0_MSIX_SIZE_1 0x00000000 116 #define PE0_MSIX_SIZE_DEF 0x00000700 117 #define PE0_MSIX_CAP_DIS 0x00000080 118 #define PE0_MSI_PVMC_ENB 0x00000040 119 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 120 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 121 #define PE0_PM_AUXC_MASK 0x00000007 122 #define PE0_PM_AUXC_DEF 0x00000007 123 124 #define JME_PCI_PE1 0xE4 125 126 #define JME_PCI_PHYTEST 0xF8 127 128 #define JME_PCI_GPR 0xFC 129 130 /* 131 * JMC Register Map. 132 * ----------------------------------------------------------------------- 133 * Register Size IO space Memory space 134 * ----------------------------------------------------------------------- 135 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 136 * BAR1 + 0x7F BAR0 + 0x7F 137 * ----------------------------------------------------------------------- 138 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 139 * BAR2 + 0x7F BAR0 + 0x47F 140 * ----------------------------------------------------------------------- 141 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 142 * BAR2 + 0xfF BAR0 + 0x87F 143 * ----------------------------------------------------------------------- 144 * We use bus_space_subregion() to get handle for the 3 different 145 * register space. Register address are relative to the base of each 146 * region. 147 */ 148 149 /* Tx control and status. */ 150 #define JME_TXCSR 0x0000 151 #define TXCSR_QWEIGHT_MASK 0x0F000000 152 #define TXCSR_QWEIGHT_SHIFT 24 153 #define TXCSR_TXQ_SEL_MASK 0x00070000 154 #define TXCSR_TXQ_SEL_SHIFT 16 155 #define TXCSR_TXQ_START 0x00000001 156 #define TXCSR_TXQ_START_SHIFT 8 157 #define TXCSR_FIFO_THRESH_4QW 0x00000000 158 #define TXCSR_FIFO_THRESH_8QW 0x00000040 159 #define TXCSR_FIFO_THRESH_12QW 0x00000080 160 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 161 #define TXCSR_DMA_SIZE_64 0x00000000 162 #define TXCSR_DMA_SIZE_128 0x00000010 163 #define TXCSR_DMA_SIZE_256 0x00000020 164 #define TXCSR_DMA_SIZE_512 0x00000030 165 #define TXCSR_DMA_BURST 0x00000004 166 #define TXCSR_TX_SUSPEND 0x00000002 167 #define TXCSR_TX_ENB 0x00000001 168 #define TXCSR_TXQ0 0 169 #define TXCSR_TXQ1 1 170 #define TXCSR_TXQ2 2 171 #define TXCSR_TXQ3 3 172 #define TXCSR_TXQ4 4 173 #define TXCSR_TXQ5 5 174 #define TXCSR_TXQ6 6 175 #define TXCSR_TXQ7 7 176 #define TXCSR_TXQ_WEIGHT(x) \ 177 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 178 #define TXCSR_TXQ_WEIGHT_MIN 0 179 #define TXCSR_TXQ_WEIGHT_MAX 15 180 #define TXCSR_TXQ_N_SEL(x) \ 181 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 182 #define TXCSR_TXQ_N_START(x) \ 183 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 184 185 /* Tx queue descriptor base address. 16bytes alignment required. */ 186 #define JME_TXDBA_LO 0x0004 187 #define JME_TXDBA_HI 0x0008 188 189 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 190 #define JME_TXQDC 0x000C 191 #define TXQDC_MASK 0x0000007F0 192 193 /* Tx queue next descriptor address. */ 194 #define JME_TXNDA 0x0010 195 #define TXNDA_ADDR_MASK 0xFFFFFFF0 196 #define TXNDA_DESC_EMPTY 0x00000008 197 #define TXNDA_DESC_VALID 0x00000004 198 #define TXNDA_DESC_WAIT 0x00000002 199 #define TXNDA_DESC_FETCH 0x00000001 200 201 /* Tx MAC control ans status. */ 202 #define JME_TXMAC 0x0014 203 #define TXMAC_IFG2_MASK 0xC0000000 204 #define TXMAC_IFG2_DEFAULT 0x40000000 205 #define TXMAC_IFG1_MASK 0x30000000 206 #define TXMAC_IFG1_DEFAULT 0x20000000 207 #define TXMAC_THRESH_1_PKT 0x00000300 208 #define TXMAC_THRESH_1_2_PKT 0x00000200 209 #define TXMAC_THRESH_1_4_PKT 0x00000100 210 #define TXMAC_THRESH_1_8_PKT 0x00000000 211 #define TXMAC_FRAME_BURST 0x00000080 212 #define TXMAC_CARRIER_EXT 0x00000040 213 #define TXMAC_IFG_ENB 0x00000020 214 #define TXMAC_BACKOFF 0x00000010 215 #define TXMAC_CARRIER_SENSE 0x00000008 216 #define TXMAC_COLL_ENB 0x00000004 217 #define TXMAC_CRC_ENB 0x00000002 218 #define TXMAC_PAD_ENB 0x00000001 219 220 /* Tx pause frame control. */ 221 #define JME_TXPFC 0x0018 222 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 223 #define TXPFC_VLAN_TAG_SHIFT 16 224 #define TXPFC_VLAN_ENB 0x00008000 225 #define TXPFC_PAUSE_ENB 0x00000001 226 227 /* Tx timer/retry at half duplex. */ 228 #define JME_TXTRHD 0x001C 229 #define TXTRHD_RT_PERIOD_ENB 0x80000000 230 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 231 #define TXTRHD_RT_PERIOD_SHIFT 8 232 #define TXTRHD_RT_LIMIT_ENB 0x00000080 233 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 234 #define TXTRHD_RT_LIMIT_SHIFT 0 235 #define TXTRHD_RT_PERIOD_DEFAULT 8192 236 #define TXTRHD_RT_LIMIT_DEFAULT 8 237 238 /* Rx control & status. */ 239 #define JME_RXCSR 0x0020 240 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 241 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 242 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 243 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 244 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 245 #define RXCSR_FIFO_THRESH_16QW 0x00000000 246 #define RXCSR_FIFO_THRESH_32QW 0x04000000 247 #define RXCSR_FIFO_THRESH_64QW 0x08000000 248 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 249 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 250 #define RXCSR_DMA_SIZE_16 0x00000000 251 #define RXCSR_DMA_SIZE_32 0x01000000 252 #define RXCSR_DMA_SIZE_64 0x02000000 253 #define RXCSR_DMA_SIZE_128 0x03000000 254 #define RXCSR_RXQ_SEL_MASK 0x00030000 255 #define RXCSR_RXQ_SEL_SHIFT 16 256 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 257 #define RXCSR_DESC_RT_GAP_SHIFT 12 258 #define RXCSR_DESC_RT_GAP_256 0x00000000 259 #define RXCSR_DESC_RT_GAP_512 0x00001000 260 #define RXCSR_DESC_RT_GAP_1024 0x00002000 261 #define RXCSR_DESC_RT_GAP_2048 0x00003000 262 #define RXCSR_DESC_RT_GAP_4096 0x00004000 263 #define RXCSR_DESC_RT_GAP_8192 0x00005000 264 #define RXCSR_DESC_RT_GAP_16384 0x00006000 265 #define RXCSR_DESC_RT_GAP_32768 0x00007000 266 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 267 #define RXCSR_DESC_RT_CNT_SHIFT 8 268 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 269 #define RXCSR_PASS_MAGIC_PKT 0x00000020 270 #define RXCSR_PASS_RUNT_PKT 0x00000010 271 #define RXCSR_PASS_BAD_PKT 0x00000008 272 #define RXCSR_RXQ_START 0x00000004 273 #define RXCSR_RX_SUSPEND 0x00000002 274 #define RXCSR_RX_ENB 0x00000001 275 276 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 277 #define RXCSR_RXQ0 0 278 #define RXCSR_RXQ1 1 279 #define RXCSR_RXQ2 2 280 #define RXCSR_RXQ3 3 281 #define RXCSR_DESC_RT_CNT(x) \ 282 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 283 #define RXCSR_DESC_RT_CNT_DEFAULT 32 284 285 /* Rx queue descriptor base address. 16bytes alignment needed. */ 286 #define JME_RXDBA_LO 0x0024 287 #define JME_RXDBA_HI 0x0028 288 289 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 290 #define JME_RXQDC 0x002C 291 #define RXQDC_MASK 0x0000007F0 292 293 /* Rx queue next descriptor address. */ 294 #define JME_RXNDA 0x0030 295 #define RXNDA_ADDR_MASK 0xFFFFFFF0 296 #define RXNDA_DESC_EMPTY 0x00000008 297 #define RXNDA_DESC_VALID 0x00000004 298 #define RXNDA_DESC_WAIT 0x00000002 299 #define RXNDA_DESC_FETCH 0x00000001 300 301 /* Rx MAC control and status. */ 302 #define JME_RXMAC 0x0034 303 #define RXMAC_RSS_UNICAST 0x00000000 304 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 305 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 306 #define RXMAC_RSS_ALLFRAME 0x00030000 307 #define RXMAC_PROMISC 0x00000800 308 #define RXMAC_BROADCAST 0x00000400 309 #define RXMAC_MULTICAST 0x00000200 310 #define RXMAC_UNICAST 0x00000100 311 #define RXMAC_ALLMULTI 0x00000080 312 #define RXMAC_MULTICAST_FILTER 0x00000040 313 #define RXMAC_COLL_DET_ENB 0x00000020 314 #define RXMAC_FC_ENB 0x00000008 315 #define RXMAC_VLAN_ENB 0x00000004 316 #define RXMAC_PAD_10BYTES 0x00000002 317 #define RXMAC_CSUM_ENB 0x00000001 318 319 /* Rx unicast MAC address. */ 320 #define JME_PAR0 0x0038 321 #define JME_PAR1 0x003C 322 323 /* Rx multicast address hash table. */ 324 #define JME_MAR0 0x0040 325 #define JME_MAR1 0x0044 326 327 /* Wakeup frame output data port. */ 328 #define JME_WFODP 0x0048 329 330 /* Wakeup frame output interface. */ 331 #define JME_WFOI 0x004C 332 #define WFOI_MASK_0_31 0x00000000 333 #define WFOI_MASK_31_63 0x00000010 334 #define WFOI_MASK_64_95 0x00000020 335 #define WFOI_MASK_96_127 0x00000030 336 #define WFOI_MASK_SEL 0x00000008 337 #define WFOI_CRC_SEL 0x00000000 338 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 339 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 340 341 /* Station management interface. */ 342 #define JME_SMI 0x0050 343 #define SMI_DATA_MASK 0xFFFF0000 344 #define SMI_DATA_SHIFT 16 345 #define SMI_REG_ADDR_MASK 0x0000F800 346 #define SMI_REG_ADDR_SHIFT 11 347 #define SMI_PHY_ADDR_MASK 0x000007C0 348 #define SMI_PHY_ADDR_SHIFT 6 349 #define SMI_OP_WRITE 0x00000020 350 #define SMI_OP_READ 0x00000000 351 #define SMI_OP_EXECUTE 0x00000010 352 #define SMI_MDIO 0x00000008 353 #define SMI_MDOE 0x00000004 354 #define SMI_MDC 0x00000002 355 #define SMI_MDEN 0x00000001 356 #define SMI_REG_ADDR(x) \ 357 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 358 #define SMI_PHY_ADDR(x) \ 359 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 360 361 /* Global host control. */ 362 #define JME_GHC 0x0054 363 #define GHC_LOOPBACK 0x80000000 364 #define GHC_RESET 0x40000000 365 #define GHC_CLKSRC_10_100 0x00a00000 366 #define GHC_CLKSRC_1000 0x00500000 367 #define GHC_CLKSRC_MASK 0x00f00000 368 #define GHC_FULL_DUPLEX 0x00000040 369 #define GHC_SPEED_UNKNOWN 0x00000000 370 #define GHC_SPEED_10 0x00000010 371 #define GHC_SPEED_100 0x00000020 372 #define GHC_SPEED_1000 0x00000030 373 #define GHC_SPEED_MASK 0x00000030 374 #define GHC_LINK_OFF 0x00000004 375 #define GHC_LINK_ON 0x00000002 376 #define GHC_LINK_STAT_POLLING 0x00000001 377 378 /* Power management control and status. */ 379 #define JME_PMCS 0x0060 380 #define PMCS_WAKEUP_FRAME_7 0x80000000 381 #define PMCS_WAKEUP_FRAME_6 0x40000000 382 #define PMCS_WAKEUP_FRAME_5 0x20000000 383 #define PMCS_WAKEUP_FRAME_4 0x10000000 384 #define PMCS_WAKEUP_FRAME_3 0x08000000 385 #define PMCS_WAKEUP_FRAME_2 0x04000000 386 #define PMCS_WAKEUP_FRAME_1 0x02000000 387 #define PMCS_WAKEUP_FRAME_0 0x01000000 388 #define PMCS_LINK_FAIL 0x00040000 389 #define PMCS_LINK_RISING 0x00020000 390 #define PMCS_MAGIC_FRAME 0x00010000 391 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 392 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 393 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 394 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 395 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 396 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 397 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 398 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 399 #define PMCS_LINK_FAIL_ENB 0x00000004 400 #define PMCS_LINK_RISING_ENB 0x00000002 401 #define PMCS_MAGIC_FRAME_ENB 0x00000001 402 #define PMCS_WOL_ENB_MASK 0x0000FFFF 403 404 405 #define JME_PHY_EEPROM_BASE_MEMOFF 0x0400 406 #define JME_PHY_EEPROM_BASE_IOOFF 0x0000 407 #define JME_PHY_EEPROM_SIZE 0x0080 408 /* Giga PHY & EEPROM registers. */ 409 #define JME_PHY_EEPROM_BASE_ADDR 0x00 410 411 #define JME_GIGAR0LO 0x00 412 #define JME_GIGAR0HI 0x04 413 #define JME_GIGARALO 0x08 414 #define JME_GIGARAHI 0x0C 415 #define JME_GIGARBLO 0x10 416 #define JME_GIGARBHI 0x14 417 #define JME_GIGARCLO 0x18 418 #define JME_GIGARCHI 0x1C 419 #define JME_GIGARDLO 0x20 420 #define JME_GIGARDHI 0x24 421 422 /* BIST status and control. */ 423 #define JME_GIGACSR 0x28 424 #define GIGACSR_STATUS 0x40000000 425 #define GIGACSR_CTRL_MASK 0x30000000 426 #define GIGACSR_CTRL_DEFAULT 0x30000000 427 #define GIGACSR_TX_CLK_MASK 0x0F000000 428 #define GIGACSR_RX_CLK_MASK 0x00F00000 429 #define GIGACSR_TX_CLK_INV 0x00080000 430 #define GIGACSR_RX_CLK_INV 0x00040000 431 #define GIGACSR_PHY_RST 0x00010000 432 #define GIGACSR_IRQ_N_O 0x00001000 433 #define GIGACSR_BIST_OK 0x00000200 434 #define GIGACSR_BIST_DONE 0x00000100 435 #define GIGACSR_BIST_LED_ENB 0x00000010 436 #define GIGACSR_BIST_MASK 0x00000003 437 438 /* PHY Link Status. */ 439 #define JME_LNKSTS 0x30 440 #define LINKSTS_SPEED_10 0x00000000 441 #define LINKSTS_SPEED_100 0x00004000 442 #define LINKSTS_SPEED_1000 0x00008000 443 #define LINKSTS_FULL_DUPLEX 0x00002000 444 #define LINKSTS_PAGE_RCVD 0x00001000 445 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 446 #define LINKSTS_UP 0x00000400 447 #define LINKSTS_ANEG_COMP 0x00000200 448 #define LINKSTS_MDI_CROSSOVR 0x00000040 449 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 450 #define LINKSTS_LPAR_PAUSE 0x00000001 451 452 /* SMB control and status. */ 453 #define JME_SMBCSR 0x40 454 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 455 #define SMBCSR_WR_DATA_NACK 0x00040000 456 #define SMBCSR_CMD_NACK 0x00020000 457 #define SMBCSR_RELOAD 0x00010000 458 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 459 #define SMBCSR_SCL_STAT 0x00000080 460 #define SMBCSR_SDA_STAT 0x00000040 461 #define SMBCSR_EEPROM_PRESENT 0x00000020 462 #define SMBCSR_INIT_LD_DONE 0x00000010 463 #define SMBCSR_HW_BUSY_MASK 0x0000000F 464 #define SMBCSR_HW_IDLE 0x00000000 465 466 /* SMB interface. */ 467 #define JME_SMBINTF 0x44 468 #define SMBINTF_RD_DATA_MASK 0xFF000000 469 #define SMBINTF_RD_DATA_SHIFT 24 470 #define SMBINTF_WR_DATA_MASK 0x00FF0000 471 #define SMBINTF_WR_DATA_SHIFT 16 472 #define SMBINTF_ADDR_MASK 0x0000FF00 473 #define SMBINTF_ADDR_SHIFT 8 474 #define SMBINTF_RD 0x00000020 475 #define SMBINTF_WR 0x00000000 476 #define SMBINTF_CMD_TRIGGER 0x00000010 477 #define SMBINTF_BUSY 0x00000010 478 #define SMBINTF_FAST_MODE 0x00000008 479 #define SMBINTF_GPIO_SCL 0x00000004 480 #define SMBINTF_GPIO_SDA 0x00000002 481 #define SMBINTF_GPIO_ENB 0x00000001 482 483 #define JME_EEPROM_SIG0 0x55 484 #define JME_EEPROM_SIG1 0xAA 485 #define JME_EEPROM_DESC_BYTES 3 486 #define JME_EEPROM_DESC_END 0x80 487 #define JME_EEPROM_FUNC_MASK 0x70 488 #define JME_EEPROM_FUNC_SHIFT 4 489 #define JME_EEPROM_PAGE_MASK 0x0F 490 #define JME_EEPROM_PAGE_SHIFT 0 491 492 #define JME_EEPROM_FUNC0 0 493 /* PCI configuration space. */ 494 #define JME_EEPROM_PAGE_BAR0 0 495 /* 128 bytes I/O window. */ 496 #define JME_EEPROM_PAGE_BAR1 1 497 /* 256 bytes I/O window. */ 498 #define JME_EEPROM_PAGE_BAR2 2 499 500 #define JME_EEPROM_END 0xFF 501 502 #define JME_EEPROM_MKDESC(f, p) \ 503 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 504 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 505 506 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 507 #define JME_EEPINTF 0x48 508 #define EEPINTF_DATA_MASK 0xFFFF0000 509 #define EEPINTF_DATA_SHIFT 16 510 #define EEPINTF_ADDR_MASK 0x0000FC00 511 #define EEPINTF_ADDR_SHIFT 10 512 #define EEPRINTF_OP_MASK 0x00000300 513 #define EEPINTF_OP_EXECUTE 0x00000080 514 #define EEPINTF_DATA_OUT 0x00000008 515 #define EEPINTF_DATA_IN 0x00000004 516 #define EEPINTF_CLK 0x00000002 517 #define EEPINTF_SEL 0x00000001 518 519 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 520 #define JME_EEPCSR 0x4C 521 #define EEPCSR_EEPROM_RELOAD 0x00000002 522 #define EEPCSR_EEPROM_PRESENT 0x00000001 523 524 /* Misc registers. */ 525 #define JME_MISC_BASE_MEMOFF 0x800 526 #define JME_MISC_BASE_IOOFF 0x080 527 #define JME_MISC_SIZE 0x080 528 529 /* Timer control and status. */ 530 #define JME_TMCSR 0x00 531 #define TMCSR_SW_INTR 0x80000000 532 #define TMCSR_TIMER_INTR 0x10000000 533 #define TMCSR_TIMER_ENB 0x01000000 534 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 535 536 /* GPIO control and status. */ 537 #define JME_GPIO 0x04 538 #define GPIO_4_SPI_IN 0x80000000 539 #define GPIO_3_SPI_IN 0x40000000 540 #define GPIO_4_SPI_OUT 0x20000000 541 #define GPIO_4_SPI_OUT_ENB 0x10000000 542 #define GPIO_3_SPI_OUT 0x08000000 543 #define GPIO_3_SPI_OUT_ENB 0x04000000 544 #define GPIO_3_4_LED 0x00000000 545 #define GPIO_3_4_GPIO 0x02000000 546 #define GPIO_2_CLKREQN_IN 0x00100000 547 #define GPIO_2_CLKREQN_OUT 0x00040000 548 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 549 #define GPIO_1_LED42_IN 0x00001000 550 #define GPIO_1_LED42_OUT 0x00000400 551 #define GPIO_1_LED42_OUT_ENB 0x00000200 552 #define GPIO_1_LED42_ENB 0x00000100 553 #define GPIO_0_SDA_IN 0x00000010 554 #define GPIO_0_SDA_OUT 0x00000004 555 #define GPIO_0_SDA_OUT_ENB 0x00000002 556 #define GPIO_0_SDA_ENB 0x00000001 557 558 /* General purpose register 0. */ 559 #define JME_GPREG0 0x08 560 #define GPREG0_SH_POST_DW7_DIS 0x80000000 561 #define GPREG0_SH_POST_DW6_DIS 0x40000000 562 #define GPREG0_SH_POST_DW5_DIS 0x20000000 563 #define GPREG0_SH_POST_DW4_DIS 0x10000000 564 #define GPREG0_SH_POST_DW3_DIS 0x08000000 565 #define GPREG0_SH_POST_DW2_DIS 0x04000000 566 #define GPREG0_SH_POST_DW1_DIS 0x02000000 567 #define GPREG0_SH_POST_DW0_DIS 0x01000000 568 #define GPREG0_DMA_RD_REQ_8 0x00000000 569 #define GPREG0_DMA_RD_REQ_6 0x00100000 570 #define GPREG0_DMA_RD_REQ_5 0x00200000 571 #define GPREG0_DMA_RD_REQ_4 0x00300000 572 #define GPREG0_POST_DW0_ENB 0x00040000 573 #define GPREG0_PCC_CLR_DIS 0x00020000 574 #define GPREG0_FORCE_SCL_OUT 0x00010000 575 #define GPREG0_DL_RSTB_DIS 0x00008000 576 #define GPREG0_STICKY_RESET 0x00004000 577 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 578 #define GPREG0_LINK_CHG_POLL 0x00001000 579 #define GPREG0_LINK_CHG_DIRECT 0x00000000 580 #define GPREG0_MSI_GEN_SEL 0x00000800 581 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 582 #define GPREG0_PCC_UNIT_16US 0x00000000 583 #define GPREG0_PCC_UNIT_256US 0x00000100 584 #define GPREG0_PCC_UNIT_US 0x00000200 585 #define GPREG0_PCC_UNIT_MS 0x00000300 586 #define GPREG0_PCC_UNIT_MASK 0x00000300 587 #define GPREG0_INTR_EVENT_ENB 0x00000080 588 #define GPREG0_PME_ENB 0x00000020 589 #define GPREG0_PHY_ADDR_MASK 0x0000001F 590 #define GPREG0_PHY_ADDR_SHIFT 0 591 #define GPREG0_PHY_ADDR 1 592 593 /* General purpose register 1. */ 594 #define JME_GPREG1 0x0C 595 #define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 596 #define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 597 #define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 598 #define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 599 #define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 600 #define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 601 #define GPREG1_INTDLY_MASK 0x00000007 602 603 /* MSIX entry number of interrupt source. */ 604 #define JME_MSINUM_BASE 0x10 605 #define JME_MSINUM_END 0x1F 606 #define MSINUM_MASK 0x7FFFFFFF 607 #define MSINUM_ENTRY_MASK 7 608 #define MSINUM_REG_INDEX(x) ((x) / 8) 609 #define MSINUM_INTR_SOURCE(x, y) \ 610 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 611 #define MSINUM_NUM_INTR_SOURCE 32 612 613 /* Interrupt event status. */ 614 #define JME_INTR_STATUS 0x20 615 #define INTR_SW 0x80000000 616 #define INTR_TIMER 0x40000000 617 #define INTR_LINKCHG 0x20000000 618 #define INTR_PAUSE 0x10000000 619 #define INTR_MAGIC_PKT 0x08000000 620 #define INTR_WAKEUP_PKT 0x04000000 621 #define INTR_RXQ0_COAL_TO 0x02000000 622 #define INTR_RXQ1_COAL_TO 0x01000000 623 #define INTR_RXQ2_COAL_TO 0x00800000 624 #define INTR_RXQ3_COAL_TO 0x00400000 625 #define INTR_TXQ_COAL_TO 0x00200000 626 #define INTR_RXQ0_COAL 0x00100000 627 #define INTR_RXQ1_COAL 0x00080000 628 #define INTR_RXQ2_COAL 0x00040000 629 #define INTR_RXQ3_COAL 0x00020000 630 #define INTR_TXQ_COAL 0x00010000 631 #define INTR_RXQ3_DESC_EMPTY 0x00008000 632 #define INTR_RXQ2_DESC_EMPTY 0x00004000 633 #define INTR_RXQ1_DESC_EMPTY 0x00002000 634 #define INTR_RXQ0_DESC_EMPTY 0x00001000 635 #define INTR_RXQ3_COMP 0x00000800 636 #define INTR_RXQ2_COMP 0x00000400 637 #define INTR_RXQ1_COMP 0x00000200 638 #define INTR_RXQ0_COMP 0x00000100 639 #define INTR_TXQ7_COMP 0x00000080 640 #define INTR_TXQ6_COMP 0x00000040 641 #define INTR_TXQ5_COMP 0x00000020 642 #define INTR_TXQ4_COMP 0x00000010 643 #define INTR_TXQ3_COMP 0x00000008 644 #define INTR_TXQ2_COMP 0x00000004 645 #define INTR_TXQ1_COMP 0x00000002 646 #define INTR_TXQ0_COMP 0x00000001 647 648 #define INTR_RXQ_COAL_TO \ 649 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 650 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 651 652 #define INTR_RXQ_COAL \ 653 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 654 INTR_RXQ3_COAL) 655 656 #define INTR_RXQ_COMP \ 657 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 658 INTR_RXQ3_COMP) 659 660 #define INTR_RXQ_DESC_EMPTY \ 661 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 662 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 663 664 #define INTR_RXQ_COMP \ 665 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 666 INTR_RXQ3_COMP) 667 668 #define INTR_TXQ_COMP \ 669 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 670 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 671 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 672 673 #define JME_INTRS_ENABLE \ 674 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 675 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 676 677 #define JME_INTRS_CHECK (JME_INTRS_ENABLE | INTR_TXQ_COMP | INTR_RXQ_COMP) 678 679 680 #define N_INTR_SW 31 681 #define N_INTR_TIMER 30 682 #define N_INTR_LINKCHG 29 683 #define N_INTR_PAUSE 28 684 #define N_INTR_MAGIC_PKT 27 685 #define N_INTR_WAKEUP_PKT 26 686 #define N_INTR_RXQ0_COAL_TO 25 687 #define N_INTR_RXQ1_COAL_TO 24 688 #define N_INTR_RXQ2_COAL_TO 23 689 #define N_INTR_RXQ3_COAL_TO 22 690 #define N_INTR_TXQ_COAL_TO 21 691 #define N_INTR_RXQ0_COAL 20 692 #define N_INTR_RXQ1_COAL 19 693 #define N_INTR_RXQ2_COAL 18 694 #define N_INTR_RXQ3_COAL 17 695 #define N_INTR_TXQ_COAL 16 696 #define N_INTR_RXQ3_DESC_EMPTY 15 697 #define N_INTR_RXQ2_DESC_EMPTY 14 698 #define N_INTR_RXQ1_DESC_EMPTY 13 699 #define N_INTR_RXQ0_DESC_EMPTY 12 700 #define N_INTR_RXQ3_COMP 11 701 #define N_INTR_RXQ2_COMP 10 702 #define N_INTR_RXQ1_COMP 9 703 #define N_INTR_RXQ0_COMP 8 704 #define N_INTR_TXQ7_COMP 7 705 #define N_INTR_TXQ6_COMP 6 706 #define N_INTR_TXQ5_COMP 5 707 #define N_INTR_TXQ4_COMP 4 708 #define N_INTR_TXQ3_COMP 3 709 #define N_INTR_TXQ2_COMP 2 710 #define N_INTR_TXQ1_COMP 1 711 #define N_INTR_TXQ0_COMP 0 712 713 /* Interrupt request status. */ 714 #define JME_INTR_REQ_STATUS 0x24 715 716 /* Interrupt enable - setting port. */ 717 #define JME_INTR_MASK_SET 0x28 718 719 /* Interrupt enable - clearing port. */ 720 #define JME_INTR_MASK_CLR 0x2C 721 722 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 723 #define JME_PCCRX0 0x30 724 #define JME_PCCRX1 0x34 725 #define JME_PCCRX2 0x38 726 #define JME_PCCRX3 0x3C 727 #define PCCRX_COAL_TO_MASK 0xFFFF0000 728 #define PCCRX_COAL_TO_SHIFT 16 729 #define PCCRX_COAL_PKT_MASK 0x0000FF00 730 #define PCCRX_COAL_PKT_SHIFT 8 731 732 #define PCCRX_COAL_TO_MIN 1 733 #define PCCRX_COAL_TO_DEFAULT 100 734 #define PCCRX_COAL_TO_MAX 65535 735 736 #define PCCRX_COAL_PKT_MIN 1 737 #define PCCRX_COAL_PKT_DEFAULT 128 738 #define PCCRX_COAL_PKT_MAX 255 739 740 /* Packet completion coalescing control of Tx queue. */ 741 #define JME_PCCTX 0x40 742 #define PCCTX_COAL_TO_MASK 0xFFFF0000 743 #define PCCTX_COAL_TO_SHIFT 16 744 #define PCCTX_COAL_PKT_MASK 0x0000FF00 745 #define PCCTX_COAL_PKT_SHIFT 8 746 #define PCCTX_COAL_TXQ7 0x00000080 747 #define PCCTX_COAL_TXQ6 0x00000040 748 #define PCCTX_COAL_TXQ5 0x00000020 749 #define PCCTX_COAL_TXQ4 0x00000010 750 #define PCCTX_COAL_TXQ3 0x00000008 751 #define PCCTX_COAL_TXQ2 0x00000004 752 #define PCCTX_COAL_TXQ1 0x00000002 753 #define PCCTX_COAL_TXQ0 0x00000001 754 755 #define PCCTX_COAL_TO_MIN 1 756 #define PCCTX_COAL_TO_DEFAULT 100 757 #define PCCTX_COAL_TO_MAX 65535 758 759 #define PCCTX_COAL_PKT_MIN 1 760 #define PCCTX_COAL_PKT_DEFAULT 128 761 #define PCCTX_COAL_PKT_MAX 255 762 763 /* Chip mode and FPGA version. */ 764 #define JME_CHIPMODE 0x44 765 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 766 #define CHIPMODE_FPGA_REV_SHIFT 16 767 #define CHIPMODE_NOT_FPGA 0 768 #define CHIPMODE_REV_MASK 0x0000FF00 769 #define CHIPMODE_REV_SHIFT 8 770 #define CHIPMODE_MODE_48P 0x0000000C 771 #define CHIPMODE_MODE_64P 0x00000004 772 #define CHIPMODE_MODE_128P_MAC 0x00000003 773 #define CHIPMODE_MODE_128P_DBG 0x00000002 774 #define CHIPMODE_MODE_128P_PHY 0x00000000 775 /* Chip full mask revision. */ 776 #define CHIPMODE_REVFM(x) ((x) & 0x0F) 777 /* Chip ECO revision. */ 778 #define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) 779 780 /* Shadow status base address high/low. */ 781 #define JME_SHBASE_ADDR_HI 0x48 782 #define JME_SHBASE_ADDR_LO 0x4C 783 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 784 #define SHBASE_POST_FORCE 0x00000002 785 #define SHBASE_POST_ENB 0x00000001 786 787 /* Timer 1 and 2. */ 788 #define JME_TIMER1 0x70 789 #define JME_TIMER2 0x74 790 #define TIMER_ENB 0x01000000 791 #define TIMER_CNT_MASK 0x00FFFFFF 792 #define TIMER_CNT_SHIFT 0 793 #define TIMER_UNIT 1024 /* 1024us */ 794 795 /* Aggresive power mode control. */ 796 #define JME_APMC 0x7C 797 #define APMC_PCIE_SDOWN_STAT 0x80000000 798 #define APMC_PCIE_SDOWN_ENB 0x40000000 799 #define APMC_PSEUDO_HOT_PLUG 0x20000000 800 #define APMC_EXT_PLUGIN_ENB 0x04000000 801 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 802 #define APMC_DIS_SRAM 0x00000004 803 #define APMC_DIS_CLKPM 0x00000002 804 #define APMC_DIS_CLKTX 0x00000001 805 806 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 807 #define JME_PCCSRX_BASE 0x80 808 #define JME_PCCSRX_END 0x8F 809 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 810 #define PCCSRX_TO_MASK 0xFFFF0000 811 #define PCCSRX_TO_SHIFT 16 812 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 813 #define PCCSRX_PKT_CNT_SHIFT 8 814 815 /* Packet completion coalesing status of Tx queue. */ 816 #define JME_PCCSTX 0x90 817 #define PCCSTX_TO_MASK 0xFFFF0000 818 #define PCCSTX_TO_SHIFT 16 819 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 820 #define PCCSTX_PKT_CNT_SHIFT 8 821 822 /* Tx queues empty indicator. */ 823 #define JME_TXQEMPTY 0x94 824 #define TXQEMPTY_TXQ7 0x00000080 825 #define TXQEMPTY_TXQ6 0x00000040 826 #define TXQEMPTY_TXQ5 0x00000020 827 #define TXQEMPTY_TXQ4 0x00000010 828 #define TXQEMPTY_TXQ3 0x00000008 829 #define TXQEMPTY_TXQ2 0x00000004 830 #define TXQEMPTY_TXQ1 0x00000002 831 #define TXQEMPTY_TXQ0 0x00000001 832 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 833 834 /* RSS control registers. */ 835 #define JME_RSS_BASE 0x0C00 836 837 #define JME_RSSC 0x0C00 838 #define RSSC_HASH_LEN_MASK 0x0000E000 839 #define RSSC_HASH_64_ENTRY 0x0000A000 840 #define RSSC_HASH_128_ENTRY 0x0000E000 841 #define RSSC_HASH_NONE 0x00001000 842 #define RSSC_HASH_IPV6 0x00000800 843 #define RSSC_HASH_IPV4 0x00000400 844 #define RSSC_HASH_IPV6_TCP 0x00000200 845 #define RSSC_HASH_IPV4_TCP 0x00000100 846 #define RSSC_NCPU_MASK 0x000000F8 847 #define RSSC_NCPU_SHIFT 3 848 #define RSSC_DIS_RSS 0x00000000 849 #define RSSC_2RXQ_ENB 0x00000001 850 #define RSSS_4RXQ_ENB 0x00000002 851 852 /* CPU vector. */ 853 #define JME_RSSCPU 0x0C04 854 #define RSSCPU_N_SEL(x) ((1 << (x)) 855 856 /* RSS Hash value. */ 857 #define JME_RSSHASH 0x0C10 858 859 #define JME_RSSHASH_STAT 0x0C14 860 861 #define JME_RSS_RDATA0 0x0C18 862 863 #define JME_RSS_RDATA1 0x0C1C 864 865 /* RSS secret key. */ 866 #define JME_RSSKEY_BASE 0x0C40 867 #define JME_RSSKEY_LAST 0x0C64 868 #define JME_RSSKEY_END 0x0C67 869 #define HASHKEY_NBYTES 40 870 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 871 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 872 873 /* RSS indirection table entries. */ 874 #define JME_RSSTBL_BASE 0x0C80 875 #define JME_RSSTBL_END 0x0CFF 876 #define RSSTBL_NENTRY 128 877 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 878 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 879 880 /* MSI-X table. */ 881 #define JME_MSIX_BASE_ADDR 0x2000 882 883 #define JME_MSIX_BASE 0x2000 884 #define JME_MSIX_END 0x207F 885 #define JME_MSIX_NENTRY 8 886 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 887 #define MSIX_ADDR_HI_OFF 0x00 888 #define MSIX_ADDR_LO_OFF 0x04 889 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 890 #define MSIX_DATA_OFF 0x08 891 #define MSIX_VECTOR_OFF 0x0C 892 #define MSIX_VECTOR_RSVD 0x80000000 893 #define MSIX_VECTOR_DIS 0x00000001 894 895 /* MSI-X PBA. */ 896 #define JME_MSIX_PBA_BASE_ADDR 0x3000 897 898 #define JME_MSIX_PBA 0x3000 899 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 900 #define MSIX_PBA_RSVD_SHIFT 8 901 #define MSIX_PBA_PEND_MASK 0x000000FF 902 #define MSIX_PBA_PEND_SHIFT 0 903 #define MSIX_PBA_PEND_ENTRY7 0x00000080 904 #define MSIX_PBA_PEND_ENTRY6 0x00000040 905 #define MSIX_PBA_PEND_ENTRY5 0x00000020 906 #define MSIX_PBA_PEND_ENTRY4 0x00000010 907 #define MSIX_PBA_PEND_ENTRY3 0x00000008 908 #define MSIX_PBA_PEND_ENTRY2 0x00000004 909 #define MSIX_PBA_PEND_ENTRY1 0x00000002 910 #define MSIX_PBA_PEND_ENTRY0 0x00000001 911 912 #define JME_PHY_OUI 0x001B8C 913 #define JME_PHY_MODEL 0x21 914 #define JME_PHY_REV 0x01 915 #define JME_PHY_ADDR 1 916 917 /* JMC250 shadow status block. */ 918 struct jme_ssb { 919 uint32_t dw0; 920 uint32_t dw1; 921 uint32_t dw2; 922 uint32_t dw3; 923 uint32_t dw4; 924 uint32_t dw5; 925 uint32_t dw6; 926 uint32_t dw7; 927 }; 928 929 /* JMC250 descriptor structures. */ 930 struct jme_desc { 931 uint32_t flags; 932 uint32_t buflen; 933 uint32_t addr_hi; 934 uint32_t addr_lo; 935 }; 936 937 #define JME_TD_OWN 0x80000000 938 #define JME_TD_INTR 0x40000000 939 #define JME_TD_64BIT 0x20000000 940 #define JME_TD_TCPCSUM 0x10000000 941 #define JME_TD_UDPCSUM 0x08000000 942 #define JME_TD_IPCSUM 0x04000000 943 #define JME_TD_TSO 0x02000000 944 #define JME_TD_VLAN_TAG 0x01000000 945 #define JME_TD_VLAN_MASK 0x0000FFFF 946 947 #define JME_TD_MSS_MASK 0xFFFC0000 948 #define JME_TD_MSS_SHIFT 18 949 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 950 #define JME_TD_BUF_LEN_SHIFT 0 951 952 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 953 #define JME_TD_FRAME_LEN_SHIFT 0 954 955 /* 956 * Only the first Tx descriptor of a packet is updated 957 * after packet transmission. 958 */ 959 #define JME_TD_TMOUT 0x20000000 960 #define JME_TD_RETRY_EXP 0x10000000 961 #define JME_TD_COLLISION 0x08000000 962 #define JME_TD_UNDERRUN 0x04000000 963 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 964 #define JME_TD_EHDR_SIZE_SHIFT 0 965 966 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 967 #define JME_TD_SEG_CNT_SHIFT 16 968 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 969 #define JME_TD_RETRY_CNT_SHIFT 0 970 971 #define JME_RD_OWN 0x80000000 972 #define JME_RD_INTR 0x40000000 973 #define JME_RD_64BIT 0x20000000 974 975 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 976 #define JME_RD_BUF_LEN_SHIFT 0 977 978 /* 979 * Only the first Rx descriptor of a packet is updated 980 * after packet reception. 981 */ 982 #define JME_RD_MORE_FRAG 0x20000000 983 #define JME_RD_TCP 0x10000000 984 #define JME_RD_UDP 0x08000000 985 #define JME_RD_IPCSUM 0x04000000 986 #define JME_RD_TCPCSUM 0x02000000 987 #define JME_RD_UDPCSUM 0x01000000 988 #define JME_RD_VLAN_TAG 0x00800000 989 #define JME_RD_IPV4 0x00400000 990 #define JME_RD_IPV6 0x00200000 991 #define JME_RD_PAUSE 0x00100000 992 #define JME_RD_MAGIC 0x00080000 993 #define JME_RD_WAKEUP 0x00040000 994 #define JME_RD_BCAST 0x00030000 995 #define JME_RD_MCAST 0x00020000 996 #define JME_RD_UCAST 0x00010000 997 #define JME_RD_VLAN_MASK 0x0000FFFF 998 #define JME_RD_VLAN_SHIFT 0 999 #define JME_RD_TCPV4 (JME_RD_IPV4|JME_RD_TCP) 1000 #define JME_RD_UDPV4 (JME_RD_IPV4|JME_RD_UDP) 1001 #define JME_RD_TCPV6 (JME_RD_IPV6|JME_RD_TCP) 1002 #define JME_RD_UDPV6 (JME_RD_IPV6|JME_RD_UDP) 1003 1004 #define JME_RD_VALID 0x80000000 1005 #define JME_RD_CNT_MASK 0x7F000000 1006 #define JME_RD_CNT_SHIFT 24 1007 #define JME_RD_GIANT 0x00800000 1008 #define JME_RD_GMII_ERR 0x00400000 1009 #define JME_RD_NBL_RCVD 0x00200000 1010 #define JME_RD_COLL 0x00100000 1011 #define JME_RD_ABORT 0x00080000 1012 #define JME_RD_RUNT 0x00040000 1013 #define JME_RD_FIFO_OVRN 0x00020000 1014 #define JME_RD_CRC_ERR 0x00010000 1015 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 1016 1017 #define JME_RX_ERR_STAT \ 1018 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1019 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1020 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1021 1022 #define JME_RD_ERR_MASK 0x00FF0000 1023 #define JME_RD_ERR_SHIFT 16 1024 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1025 #define JME_RX_ERR_BITS "\20" \ 1026 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1027 "\5COLL\6NBLRCVD\7GMIIERR\10" 1028 1029 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1030 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1031 #define JME_RX_PAD_BYTES 10 1032 1033 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1034 1035 #define JME_RD_RSS_HASH_MASK 0x00003F00 1036 #define JME_RD_RSS_HASH_SHIFT 8 1037 #define JME_RD_RSS_HASH_NONE 0x00000000 1038 #define JME_RD_RSS_HASH_IPV4 0x00000100 1039 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1040 #define JME_RD_RSS_HASH_IPV6 0x00000400 1041 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1042 #define JME_RD_HASH_FN_NONE 0x00000000 1043 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1044 1045 #define JME_MAX_TX_LEN 65535 1046 #define JME_MAX_RX_LEN 65535 1047 1048 #define JME_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 1049 #define JME_ADDR_HI(x) ((uint64_t) (x) >> 32) 1050 1051 /* 1052 * JMC250 can't handle Tx checksum offload/TSO if frame length 1053 * is larger than its FIFO size(2K). It's also good idea to not 1054 * use jumbo frame if hardware is running at half-duplex media. 1055 * Because the jumbo frame may not fit into the Tx FIFO, 1056 * collisions make hardware fetch frame from host memory with 1057 * DMA again which in turn slows down Tx performance 1058 * significantly. 1059 */ 1060 #define JME_TX_FIFO_SIZE 2000 1061 /* 1062 * JMC250 has just 4K Rx FIFO. To support jumbo frame that is 1063 * larger than 4K bytes in length, Rx FIFO threshold should be 1064 * adjusted to minimize Rx FIFO overrun. 1065 */ 1066 #define JME_RX_FIFO_SIZE 4000 1067 1068 #endif 1069
Indexes created Tue Oct 28 07:09:57 GMT 2025