if_kse.c revision 1.1.10.2
1 1.1.10.2 rpaulo /* $NetBSD: if_kse.c,v 1.1.10.2 2006/09/09 02:52:17 rpaulo Exp $ */ 2 1.1.10.2 rpaulo 3 1.1.10.2 rpaulo /* 4 1.1.10.2 rpaulo * Copyright (c) 2006 Tohru Nishimura 5 1.1.10.2 rpaulo * 6 1.1.10.2 rpaulo * Redistribution and use in source and binary forms, with or without 7 1.1.10.2 rpaulo * modification, are permitted provided that the following conditions 8 1.1.10.2 rpaulo * are met: 9 1.1.10.2 rpaulo * 1. Redistributions of source code must retain the above copyright 10 1.1.10.2 rpaulo * notice, this list of conditions and the following disclaimer. 11 1.1.10.2 rpaulo * 2. Redistributions in binary form must reproduce the above copyright 12 1.1.10.2 rpaulo * notice, this list of conditions and the following disclaimer in the 13 1.1.10.2 rpaulo * documentation and/or other materials provided with the distribution. 14 1.1.10.2 rpaulo * 3. All advertising materials mentioning features or use of this software 15 1.1.10.2 rpaulo * must display the following acknowledgement: 16 1.1.10.2 rpaulo * This product includes software developed by Tohru Nishimura. 17 1.1.10.2 rpaulo * 4. The name of the author may not be used to endorse or promote products 18 1.1.10.2 rpaulo * derived from this software without specific prior written permission. 19 1.1.10.2 rpaulo * 20 1.1.10.2 rpaulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.1.10.2 rpaulo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.1.10.2 rpaulo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.1.10.2 rpaulo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.1.10.2 rpaulo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.1.10.2 rpaulo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.1.10.2 rpaulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.1.10.2 rpaulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.1.10.2 rpaulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.1.10.2 rpaulo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.1.10.2 rpaulo */ 31 1.1.10.2 rpaulo 32 1.1.10.2 rpaulo #include <sys/cdefs.h> 33 1.1.10.2 rpaulo __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.1.10.2 2006/09/09 02:52:17 rpaulo Exp $"); 34 1.1.10.2 rpaulo 35 1.1.10.2 rpaulo #include "bpfilter.h" 36 1.1.10.2 rpaulo 37 1.1.10.2 rpaulo #include <sys/param.h> 38 1.1.10.2 rpaulo #include <sys/systm.h> 39 1.1.10.2 rpaulo #include <sys/callout.h> 40 1.1.10.2 rpaulo #include <sys/mbuf.h> 41 1.1.10.2 rpaulo #include <sys/malloc.h> 42 1.1.10.2 rpaulo #include <sys/kernel.h> 43 1.1.10.2 rpaulo #include <sys/ioctl.h> 44 1.1.10.2 rpaulo #include <sys/errno.h> 45 1.1.10.2 rpaulo #include <sys/device.h> 46 1.1.10.2 rpaulo #include <sys/queue.h> 47 1.1.10.2 rpaulo 48 1.1.10.2 rpaulo #include <machine/endian.h> 49 1.1.10.2 rpaulo #include <machine/bus.h> 50 1.1.10.2 rpaulo #include <machine/intr.h> 51 1.1.10.2 rpaulo 52 1.1.10.2 rpaulo #include <net/if.h> 53 1.1.10.2 rpaulo #include <net/if_media.h> 54 1.1.10.2 rpaulo #include <net/if_dl.h> 55 1.1.10.2 rpaulo #include <net/if_ether.h> 56 1.1.10.2 rpaulo 57 1.1.10.2 rpaulo #if NBPFILTER > 0 58 1.1.10.2 rpaulo #include <net/bpf.h> 59 1.1.10.2 rpaulo #endif 60 1.1.10.2 rpaulo 61 1.1.10.2 rpaulo #include <dev/pci/pcivar.h> 62 1.1.10.2 rpaulo #include <dev/pci/pcireg.h> 63 1.1.10.2 rpaulo #include <dev/pci/pcidevs.h> 64 1.1.10.2 rpaulo 65 1.1.10.2 rpaulo #define CSR_READ_4(sc, off) \ 66 1.1.10.2 rpaulo bus_space_read_4(sc->sc_st, sc->sc_sh, off) 67 1.1.10.2 rpaulo #define CSR_WRITE_4(sc, off, val) \ 68 1.1.10.2 rpaulo bus_space_write_4(sc->sc_st, sc->sc_sh, off, val) 69 1.1.10.2 rpaulo #define CSR_READ_2(sc, off) \ 70 1.1.10.2 rpaulo bus_space_read_2(sc->sc_st, sc->sc_sh, off) 71 1.1.10.2 rpaulo #define CSR_WRITE_2(sc, off, val) \ 72 1.1.10.2 rpaulo bus_space_write_2(sc->sc_st, sc->sc_sh, off, val) 73 1.1.10.2 rpaulo 74 1.1.10.2 rpaulo #define MDTXC 0x000 /* DMA transmit control */ 75 1.1.10.2 rpaulo #define MDRXC 0x004 /* DMA receive control */ 76 1.1.10.2 rpaulo #define MDTSC 0x008 /* DMA transmit start */ 77 1.1.10.2 rpaulo #define MDRSC 0x00c /* DMA receive start */ 78 1.1.10.2 rpaulo #define TDLB 0x010 /* transmit descriptor list base */ 79 1.1.10.2 rpaulo #define RDLB 0x014 /* receive descriptor list base */ 80 1.1.10.2 rpaulo #define INTEN 0x028 /* interrupt enable */ 81 1.1.10.2 rpaulo #define INTST 0x02c /* interrupt status */ 82 1.1.10.2 rpaulo #define MARL 0x200 /* MAC address low */ 83 1.1.10.2 rpaulo #define MARM 0x202 /* MAC address middle */ 84 1.1.10.2 rpaulo #define MARH 0x204 /* MAC address high */ 85 1.1.10.2 rpaulo #define GRR 0x216 /* global reset */ 86 1.1.10.2 rpaulo #define CIDR 0x400 /* chip ID and enable */ 87 1.1.10.2 rpaulo #define CGCR 0x40a /* chip global control */ 88 1.1.10.2 rpaulo #define P1CR4 0x512 /* port 1 control 4 */ 89 1.1.10.2 rpaulo #define P1SR 0x514 /* port 1 status */ 90 1.1.10.2 rpaulo 91 1.1.10.2 rpaulo #define TXC_BS_MSK 0x3f000000 /* burst size */ 92 1.1.10.2 rpaulo #define TXC_BS_SFT (24) /* 1,2,4,8,16,32 or 0 for unlimited */ 93 1.1.10.2 rpaulo #define TXC_UCG (1U<<18) /* generate UDP checksum */ 94 1.1.10.2 rpaulo #define TXC_TCG (1U<<17) /* generate TCP checksum */ 95 1.1.10.2 rpaulo #define TXC_ICG (1U<<16) /* generate IP checksum */ 96 1.1.10.2 rpaulo #define TXC_FCE (1U<<9) /* enable flowcontrol */ 97 1.1.10.2 rpaulo #define TXC_EP (1U<<2) /* enable automatic padding */ 98 1.1.10.2 rpaulo #define TXC_AC (1U<<1) /* add CRC to frame */ 99 1.1.10.2 rpaulo #define TXC_TEN (1) /* enable DMA to run */ 100 1.1.10.2 rpaulo 101 1.1.10.2 rpaulo #define RXC_BS_MSK 0x3f000000 /* burst size */ 102 1.1.10.2 rpaulo #define RXC_BS_SFT (24) /* 1,2,4,8,16,32 or 0 for unlimited */ 103 1.1.10.2 rpaulo #define RXC_UCG (1U<<18) /* run UDP checksum */ 104 1.1.10.2 rpaulo #define RXC_TCG (1U<<17) /* run TDP checksum */ 105 1.1.10.2 rpaulo #define RXC_ICG (1U<<16) /* run IP checksum */ 106 1.1.10.2 rpaulo #define RXC_FCE (1U<<9) /* enable flowcontrol */ 107 1.1.10.2 rpaulo #define RXC_RB (1U<<6) /* receive broadcast frame */ 108 1.1.10.2 rpaulo #define RXC_RM (1U<<5) /* receive multicast frame */ 109 1.1.10.2 rpaulo #define RXC_RU (1U<<4) /* receive unicast frame */ 110 1.1.10.2 rpaulo #define RXC_RE (1U<<3) /* accept error frame */ 111 1.1.10.2 rpaulo #define RXC_RA (1U<<2) /* receive all frame */ 112 1.1.10.2 rpaulo #define RXC_MA (1U<<1) /* receive through hash filter */ 113 1.1.10.2 rpaulo #define RXC_REN (1) /* enable DMA to run */ 114 1.1.10.2 rpaulo 115 1.1.10.2 rpaulo #define INT_DMLCS (1U<<31) /* link status change */ 116 1.1.10.2 rpaulo #define INT_DMTS (1U<<30) /* sending desc. has posted Tx done */ 117 1.1.10.2 rpaulo #define INT_DMRS (1U<<29) /* frame was received */ 118 1.1.10.2 rpaulo #define INT_DMRBUS (1U<<27) /* Rx descriptor pool is full */ 119 1.1.10.2 rpaulo 120 1.1.10.2 rpaulo #define T0_OWN (1U<<31) /* desc is ready to Tx */ 121 1.1.10.2 rpaulo 122 1.1.10.2 rpaulo #define R0_OWN (1U<<31) /* desc is empty */ 123 1.1.10.2 rpaulo #define R0_FS (1U<<30) /* first segment of frame */ 124 1.1.10.2 rpaulo #define R0_LS (1U<<29) /* last segment of frame */ 125 1.1.10.2 rpaulo #define R0_IPE (1U<<28) /* IP checksum error */ 126 1.1.10.2 rpaulo #define R0_TCPE (1U<<27) /* TCP checksum error */ 127 1.1.10.2 rpaulo #define R0_UDPE (1U<<26) /* UDP checksum error */ 128 1.1.10.2 rpaulo #define R0_ES (1U<<25) /* error summary */ 129 1.1.10.2 rpaulo #define R0_MF (1U<<24) /* multicast frame */ 130 1.1.10.2 rpaulo #define R0_RE (1U<<19) /* framing error */ 131 1.1.10.2 rpaulo #define R0_TL (1U<<18) /* too long frame */ 132 1.1.10.2 rpaulo #define R0_RF (1U<<17) /* damaged runt frame */ 133 1.1.10.2 rpaulo #define R0_CE (1U<<16) /* CRC error */ 134 1.1.10.2 rpaulo #define R0_FT (1U<<15) /* frame type */ 135 1.1.10.2 rpaulo #define R0_FL_MASK 0x7ff /* frame length 10:0 */ 136 1.1.10.2 rpaulo 137 1.1.10.2 rpaulo #define T1_IC (1U<<31) /* post interrupt on complete */ 138 1.1.10.2 rpaulo #define T1_FS (1U<<30) /* first segment of frame */ 139 1.1.10.2 rpaulo #define T1_LS (1U<<29) /* last segment of frame */ 140 1.1.10.2 rpaulo #define T1_IPCKG (1U<<28) /* generate IP checksum */ 141 1.1.10.2 rpaulo #define T1_TCPCKG (1U<<27) /* generate TCP checksum */ 142 1.1.10.2 rpaulo #define T1_UDPCKG (1U<<26) /* generate UDP checksum */ 143 1.1.10.2 rpaulo #define T1_TER (1U<<25) /* end of ring */ 144 1.1.10.2 rpaulo #define T1_TBS_MASK 0x7ff /* segment size 10:0 */ 145 1.1.10.2 rpaulo 146 1.1.10.2 rpaulo #define R1_RER (1U<<25) /* end of ring */ 147 1.1.10.2 rpaulo #define R1_RBS_MASK 0x7ff /* segment size 10:0 */ 148 1.1.10.2 rpaulo 149 1.1.10.2 rpaulo #define KSE_NTXSEGS 16 150 1.1.10.2 rpaulo #define KSE_TXQUEUELEN 64 151 1.1.10.2 rpaulo #define KSE_TXQUEUELEN_MASK (KSE_TXQUEUELEN - 1) 152 1.1.10.2 rpaulo #define KSE_TXQUEUE_GC (KSE_TXQUEUELEN / 4) 153 1.1.10.2 rpaulo #define KSE_NTXDESC 256 154 1.1.10.2 rpaulo #define KSE_NTXDESC_MASK (KSE_NTXDESC - 1) 155 1.1.10.2 rpaulo #define KSE_NEXTTX(x) (((x) + 1) & KSE_NTXDESC_MASK) 156 1.1.10.2 rpaulo #define KSE_NEXTTXS(x) (((x) + 1) & KSE_TXQUEUELEN_MASK) 157 1.1.10.2 rpaulo 158 1.1.10.2 rpaulo #define KSE_NRXDESC 64 159 1.1.10.2 rpaulo #define KSE_NRXDESC_MASK (KSE_NRXDESC - 1) 160 1.1.10.2 rpaulo #define KSE_NEXTRX(x) (((x) + 1) & KSE_NRXDESC_MASK) 161 1.1.10.2 rpaulo 162 1.1.10.2 rpaulo struct tdes { 163 1.1.10.2 rpaulo unsigned t0, t1, t2, t3; 164 1.1.10.2 rpaulo }; 165 1.1.10.2 rpaulo 166 1.1.10.2 rpaulo struct rdes { 167 1.1.10.2 rpaulo unsigned r0, r1, r2, r3; 168 1.1.10.2 rpaulo }; 169 1.1.10.2 rpaulo 170 1.1.10.2 rpaulo struct kse_control_data { 171 1.1.10.2 rpaulo struct tdes kcd_txdescs[KSE_NTXDESC]; 172 1.1.10.2 rpaulo struct rdes kcd_rxdescs[KSE_NRXDESC]; 173 1.1.10.2 rpaulo }; 174 1.1.10.2 rpaulo #define KSE_CDOFF(x) offsetof(struct kse_control_data, x) 175 1.1.10.2 rpaulo #define KSE_CDTXOFF(x) KSE_CDOFF(kcd_txdescs[(x)]) 176 1.1.10.2 rpaulo #define KSE_CDRXOFF(x) KSE_CDOFF(kcd_rxdescs[(x)]) 177 1.1.10.2 rpaulo 178 1.1.10.2 rpaulo struct kse_txsoft { 179 1.1.10.2 rpaulo struct mbuf *txs_mbuf; /* head of our mbuf chain */ 180 1.1.10.2 rpaulo bus_dmamap_t txs_dmamap; /* our DMA map */ 181 1.1.10.2 rpaulo int txs_firstdesc; /* first descriptor in packet */ 182 1.1.10.2 rpaulo int txs_lastdesc; /* last descriptor in packet */ 183 1.1.10.2 rpaulo int txs_ndesc; /* # of descriptors used */ 184 1.1.10.2 rpaulo }; 185 1.1.10.2 rpaulo 186 1.1.10.2 rpaulo struct kse_rxsoft { 187 1.1.10.2 rpaulo struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 188 1.1.10.2 rpaulo bus_dmamap_t rxs_dmamap; /* our DMA map */ 189 1.1.10.2 rpaulo }; 190 1.1.10.2 rpaulo 191 1.1.10.2 rpaulo struct kse_softc { 192 1.1.10.2 rpaulo struct device sc_dev; /* generic device information */ 193 1.1.10.2 rpaulo bus_space_tag_t sc_st; /* bus space tag */ 194 1.1.10.2 rpaulo bus_space_handle_t sc_sh; /* bus space handle */ 195 1.1.10.2 rpaulo bus_dma_tag_t sc_dmat; /* bus DMA tag */ 196 1.1.10.2 rpaulo struct ethercom sc_ethercom; /* Ethernet common data */ 197 1.1.10.2 rpaulo void *sc_ih; /* interrupt cookie */ 198 1.1.10.2 rpaulo 199 1.1.10.2 rpaulo struct ifmedia sc_media; /* ifmedia information */ 200 1.1.10.2 rpaulo int sc_media_status; /* PHY */ 201 1.1.10.2 rpaulo unsigned sc_media_active; /* PHY */ 202 1.1.10.2 rpaulo struct callout sc_callout; /* tick callout */ 203 1.1.10.2 rpaulo 204 1.1.10.2 rpaulo bus_dmamap_t sc_cddmamap; /* control data DMA map */ 205 1.1.10.2 rpaulo #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 206 1.1.10.2 rpaulo 207 1.1.10.2 rpaulo struct kse_control_data *sc_control_data; 208 1.1.10.2 rpaulo #define sc_txdescs sc_control_data->kcd_txdescs 209 1.1.10.2 rpaulo #define sc_rxdescs sc_control_data->kcd_rxdescs 210 1.1.10.2 rpaulo 211 1.1.10.2 rpaulo struct kse_txsoft sc_txsoft[KSE_TXQUEUELEN]; 212 1.1.10.2 rpaulo struct kse_rxsoft sc_rxsoft[KSE_NRXDESC]; 213 1.1.10.2 rpaulo int sc_txfree; /* number of free Tx descriptors */ 214 1.1.10.2 rpaulo int sc_txnext; /* next ready Tx descriptor */ 215 1.1.10.2 rpaulo int sc_txsfree; /* number of free Tx jobs */ 216 1.1.10.2 rpaulo int sc_txsnext; /* next ready Tx job */ 217 1.1.10.2 rpaulo int sc_txsdirty; /* dirty Tx jobs */ 218 1.1.10.2 rpaulo int sc_rxptr; /* next ready Rx descriptor/descsoft */ 219 1.1.10.2 rpaulo 220 1.1.10.2 rpaulo unsigned sc_txc, sc_rxc; 221 1.1.10.2 rpaulo unsigned sc_t1csum, sc_mcsum; 222 1.1.10.2 rpaulo unsigned sc_chip; 223 1.1.10.2 rpaulo }; 224 1.1.10.2 rpaulo 225 1.1.10.2 rpaulo #define KSE_CDTXADDR(sc, x) ((sc)->sc_cddma + KSE_CDTXOFF((x))) 226 1.1.10.2 rpaulo #define KSE_CDRXADDR(sc, x) ((sc)->sc_cddma + KSE_CDRXOFF((x))) 227 1.1.10.2 rpaulo 228 1.1.10.2 rpaulo #define KSE_CDTXSYNC(sc, x, n, ops) \ 229 1.1.10.2 rpaulo do { \ 230 1.1.10.2 rpaulo int __x, __n; \ 231 1.1.10.2 rpaulo \ 232 1.1.10.2 rpaulo __x = (x); \ 233 1.1.10.2 rpaulo __n = (n); \ 234 1.1.10.2 rpaulo \ 235 1.1.10.2 rpaulo /* If it will wrap around, sync to the end of the ring. */ \ 236 1.1.10.2 rpaulo if ((__x + __n) > KSE_NTXDESC) { \ 237 1.1.10.2 rpaulo bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 238 1.1.10.2 rpaulo KSE_CDTXOFF(__x), sizeof(struct tdes) * \ 239 1.1.10.2 rpaulo (KSE_NTXDESC - __x), (ops)); \ 240 1.1.10.2 rpaulo __n -= (KSE_NTXDESC - __x); \ 241 1.1.10.2 rpaulo __x = 0; \ 242 1.1.10.2 rpaulo } \ 243 1.1.10.2 rpaulo \ 244 1.1.10.2 rpaulo /* Now sync whatever is left. */ \ 245 1.1.10.2 rpaulo bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 246 1.1.10.2 rpaulo KSE_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 247 1.1.10.2 rpaulo } while (/*CONSTCOND*/0) 248 1.1.10.2 rpaulo 249 1.1.10.2 rpaulo #define KSE_CDRXSYNC(sc, x, ops) \ 250 1.1.10.2 rpaulo do { \ 251 1.1.10.2 rpaulo bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 252 1.1.10.2 rpaulo KSE_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 253 1.1.10.2 rpaulo } while (/*CONSTCOND*/0) 254 1.1.10.2 rpaulo 255 1.1.10.2 rpaulo #define KSE_INIT_RXDESC(sc, x) \ 256 1.1.10.2 rpaulo do { \ 257 1.1.10.2 rpaulo struct kse_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 258 1.1.10.2 rpaulo struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 259 1.1.10.2 rpaulo struct mbuf *__m = __rxs->rxs_mbuf; \ 260 1.1.10.2 rpaulo \ 261 1.1.10.2 rpaulo /* \ 262 1.1.10.2 rpaulo * Note: may be able to scoot the packet forward 2 bytes for \ 263 1.1.10.2 rpaulo * the alignment. Unclear KS8842 Rx DMA really mandates to have \ 264 1.1.10.2 rpaulo * 32-bit buffer boundary. Tx DMA has no alignment limitation. \ 265 1.1.10.2 rpaulo */ \ 266 1.1.10.2 rpaulo __m->m_data = __m->m_ext.ext_buf; \ 267 1.1.10.2 rpaulo __rxd->r2 = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 268 1.1.10.2 rpaulo __rxd->r1 = R1_RBS_MASK /* __m->m_ext.ext_size */; \ 269 1.1.10.2 rpaulo __rxd->r0 = R0_OWN; \ 270 1.1.10.2 rpaulo KSE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 271 1.1.10.2 rpaulo } while (/*CONSTCOND*/0) 272 1.1.10.2 rpaulo 273 1.1.10.2 rpaulo unsigned kse_burstsize = 16; /* DMA burst length tuning knob */ 274 1.1.10.2 rpaulo 275 1.1.10.2 rpaulo #ifdef KSEDIAGNOSTIC 276 1.1.10.2 rpaulo unsigned kse_monitor_rxintr; /* fragmented UDP csum HW bug hook */ 277 1.1.10.2 rpaulo #endif 278 1.1.10.2 rpaulo 279 1.1.10.2 rpaulo static int kse_match(struct device *, struct cfdata *, void *); 280 1.1.10.2 rpaulo static void kse_attach(struct device *, struct device *, void *); 281 1.1.10.2 rpaulo 282 1.1.10.2 rpaulo CFATTACH_DECL(kse, sizeof(struct kse_softc), 283 1.1.10.2 rpaulo kse_match, kse_attach, NULL, NULL); 284 1.1.10.2 rpaulo 285 1.1.10.2 rpaulo static int kse_ioctl(struct ifnet *, u_long, caddr_t); 286 1.1.10.2 rpaulo static void kse_start(struct ifnet *); 287 1.1.10.2 rpaulo static void kse_watchdog(struct ifnet *); 288 1.1.10.2 rpaulo static int kse_init(struct ifnet *); 289 1.1.10.2 rpaulo static void kse_stop(struct ifnet *, int); 290 1.1.10.2 rpaulo static void kse_reset(struct kse_softc *); 291 1.1.10.2 rpaulo static void kse_set_filter(struct kse_softc *); 292 1.1.10.2 rpaulo static int add_rxbuf(struct kse_softc *, int); 293 1.1.10.2 rpaulo static void rxdrain(struct kse_softc *); 294 1.1.10.2 rpaulo static int kse_intr(void *); 295 1.1.10.2 rpaulo static void rxintr(struct kse_softc *); 296 1.1.10.2 rpaulo static void txreap(struct kse_softc *); 297 1.1.10.2 rpaulo static void lnkchg(struct kse_softc *); 298 1.1.10.2 rpaulo static int ifmedia_upd(struct ifnet *); 299 1.1.10.2 rpaulo static void ifmedia_sts(struct ifnet *, struct ifmediareq *); 300 1.1.10.2 rpaulo static void phy_tick(void *); 301 1.1.10.2 rpaulo 302 1.1.10.2 rpaulo static int 303 1.1.10.2 rpaulo kse_match(struct device *parent, struct cfdata *match, void *aux) 304 1.1.10.2 rpaulo { 305 1.1.10.2 rpaulo struct pci_attach_args *pa = (struct pci_attach_args *)aux; 306 1.1.10.2 rpaulo 307 1.1.10.2 rpaulo if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_MICREL && 308 1.1.10.2 rpaulo (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MICREL_KSZ8842 || 309 1.1.10.2 rpaulo PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MICREL_KSZ8841) && 310 1.1.10.2 rpaulo PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 311 1.1.10.2 rpaulo return 1; 312 1.1.10.2 rpaulo 313 1.1.10.2 rpaulo return 0; 314 1.1.10.2 rpaulo } 315 1.1.10.2 rpaulo 316 1.1.10.2 rpaulo static void 317 1.1.10.2 rpaulo kse_attach(struct device *parent, struct device *self, void *aux) 318 1.1.10.2 rpaulo { 319 1.1.10.2 rpaulo struct kse_softc *sc = (struct kse_softc *)self; 320 1.1.10.2 rpaulo struct pci_attach_args *pa = aux; 321 1.1.10.2 rpaulo pci_chipset_tag_t pc = pa->pa_pc; 322 1.1.10.2 rpaulo pci_intr_handle_t ih; 323 1.1.10.2 rpaulo const char *intrstr; 324 1.1.10.2 rpaulo struct ifnet *ifp; 325 1.1.10.2 rpaulo uint8_t enaddr[ETHER_ADDR_LEN]; 326 1.1.10.2 rpaulo bus_dma_segment_t seg; 327 1.1.10.2 rpaulo int error, i, nseg; 328 1.1.10.2 rpaulo pcireg_t pmode; 329 1.1.10.2 rpaulo int pmreg; 330 1.1.10.2 rpaulo 331 1.1.10.2 rpaulo if (pci_mapreg_map(pa, 0x10, 332 1.1.10.2 rpaulo PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 333 1.1.10.2 rpaulo 0, &sc->sc_st, &sc->sc_sh, NULL, NULL) != 0) { 334 1.1.10.2 rpaulo printf(": unable to map device registers\n"); 335 1.1.10.2 rpaulo return; 336 1.1.10.2 rpaulo } 337 1.1.10.2 rpaulo 338 1.1.10.2 rpaulo sc->sc_dmat = pa->pa_dmat; 339 1.1.10.2 rpaulo 340 1.1.10.2 rpaulo /* Make sure bus mastering is enabled. */ 341 1.1.10.2 rpaulo pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 342 1.1.10.2 rpaulo pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 343 1.1.10.2 rpaulo PCI_COMMAND_MASTER_ENABLE); 344 1.1.10.2 rpaulo 345 1.1.10.2 rpaulo /* Get it out of power save mode, if needed. */ 346 1.1.10.2 rpaulo if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 347 1.1.10.2 rpaulo pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 348 1.1.10.2 rpaulo PCI_PMCSR_STATE_MASK; 349 1.1.10.2 rpaulo if (pmode == PCI_PMCSR_STATE_D3) { 350 1.1.10.2 rpaulo /* 351 1.1.10.2 rpaulo * The card has lost all configuration data in 352 1.1.10.2 rpaulo * this state, so punt. 353 1.1.10.2 rpaulo */ 354 1.1.10.2 rpaulo printf("%s: unable to wake from power state D3\n", 355 1.1.10.2 rpaulo sc->sc_dev.dv_xname); 356 1.1.10.2 rpaulo return; 357 1.1.10.2 rpaulo } 358 1.1.10.2 rpaulo if (pmode != PCI_PMCSR_STATE_D0) { 359 1.1.10.2 rpaulo printf("%s: waking up from power date D%d\n", 360 1.1.10.2 rpaulo sc->sc_dev.dv_xname, pmode); 361 1.1.10.2 rpaulo pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 362 1.1.10.2 rpaulo PCI_PMCSR_STATE_D0); 363 1.1.10.2 rpaulo } 364 1.1.10.2 rpaulo } 365 1.1.10.2 rpaulo 366 1.1.10.2 rpaulo sc->sc_chip = PCI_PRODUCT(pa->pa_id); 367 1.1.10.2 rpaulo printf(": Micrel KSZ%04x Ethernet (rev. 0x%02x)\n", 368 1.1.10.2 rpaulo sc->sc_chip, PCI_REVISION(pa->pa_class)); 369 1.1.10.2 rpaulo 370 1.1.10.2 rpaulo /* 371 1.1.10.2 rpaulo * Read the Ethernet address from the EEPROM. 372 1.1.10.2 rpaulo */ 373 1.1.10.2 rpaulo i = CSR_READ_2(sc, MARL); 374 1.1.10.2 rpaulo enaddr[5] = i; enaddr[4] = i >> 8; 375 1.1.10.2 rpaulo i = CSR_READ_2(sc, MARM); 376 1.1.10.2 rpaulo enaddr[3] = i; enaddr[2] = i >> 8; 377 1.1.10.2 rpaulo i = CSR_READ_2(sc, MARH); 378 1.1.10.2 rpaulo enaddr[1] = i; enaddr[0] = i >> 8; 379 1.1.10.2 rpaulo printf("%s: Ethernet address: %s\n", 380 1.1.10.2 rpaulo sc->sc_dev.dv_xname, ether_sprintf(enaddr)); 381 1.1.10.2 rpaulo 382 1.1.10.2 rpaulo /* 383 1.1.10.2 rpaulo * Enable chip function. 384 1.1.10.2 rpaulo */ 385 1.1.10.2 rpaulo CSR_WRITE_2(sc, CIDR, 1); 386 1.1.10.2 rpaulo 387 1.1.10.2 rpaulo /* 388 1.1.10.2 rpaulo * Map and establish our interrupt. 389 1.1.10.2 rpaulo */ 390 1.1.10.2 rpaulo if (pci_intr_map(pa, &ih)) { 391 1.1.10.2 rpaulo printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 392 1.1.10.2 rpaulo return; 393 1.1.10.2 rpaulo } 394 1.1.10.2 rpaulo intrstr = pci_intr_string(pc, ih); 395 1.1.10.2 rpaulo sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, kse_intr, sc); 396 1.1.10.2 rpaulo if (sc->sc_ih == NULL) { 397 1.1.10.2 rpaulo printf("%s: unable to establish interrupt", 398 1.1.10.2 rpaulo sc->sc_dev.dv_xname); 399 1.1.10.2 rpaulo if (intrstr != NULL) 400 1.1.10.2 rpaulo printf(" at %s", intrstr); 401 1.1.10.2 rpaulo printf("\n"); 402 1.1.10.2 rpaulo return; 403 1.1.10.2 rpaulo } 404 1.1.10.2 rpaulo printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 405 1.1.10.2 rpaulo 406 1.1.10.2 rpaulo /* 407 1.1.10.2 rpaulo * Allocate the control data structures, and create and load the 408 1.1.10.2 rpaulo * DMA map for it. 409 1.1.10.2 rpaulo */ 410 1.1.10.2 rpaulo error = bus_dmamem_alloc(sc->sc_dmat, 411 1.1.10.2 rpaulo sizeof(struct kse_control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 412 1.1.10.2 rpaulo if (error != 0) { 413 1.1.10.2 rpaulo printf("%s: unable to allocate control data, error = %d\n", 414 1.1.10.2 rpaulo sc->sc_dev.dv_xname, error); 415 1.1.10.2 rpaulo goto fail_0; 416 1.1.10.2 rpaulo } 417 1.1.10.2 rpaulo error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 418 1.1.10.2 rpaulo sizeof(struct kse_control_data), (caddr_t *)&sc->sc_control_data, 419 1.1.10.2 rpaulo BUS_DMA_COHERENT); 420 1.1.10.2 rpaulo if (error != 0) { 421 1.1.10.2 rpaulo printf("%s: unable to map control data, error = %d\n", 422 1.1.10.2 rpaulo sc->sc_dev.dv_xname, error); 423 1.1.10.2 rpaulo goto fail_1; 424 1.1.10.2 rpaulo } 425 1.1.10.2 rpaulo error = bus_dmamap_create(sc->sc_dmat, 426 1.1.10.2 rpaulo sizeof(struct kse_control_data), 1, 427 1.1.10.2 rpaulo sizeof(struct kse_control_data), 0, 0, &sc->sc_cddmamap); 428 1.1.10.2 rpaulo if (error != 0) { 429 1.1.10.2 rpaulo printf("%s: unable to create control data DMA map, " 430 1.1.10.2 rpaulo "error = %d\n", sc->sc_dev.dv_xname, error); 431 1.1.10.2 rpaulo goto fail_2; 432 1.1.10.2 rpaulo } 433 1.1.10.2 rpaulo error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 434 1.1.10.2 rpaulo sc->sc_control_data, sizeof(struct kse_control_data), NULL, 0); 435 1.1.10.2 rpaulo if (error != 0) { 436 1.1.10.2 rpaulo printf("%s: unable to load control data DMA map, error = %d\n", 437 1.1.10.2 rpaulo sc->sc_dev.dv_xname, error); 438 1.1.10.2 rpaulo goto fail_3; 439 1.1.10.2 rpaulo } 440 1.1.10.2 rpaulo for (i = 0; i < KSE_TXQUEUELEN; i++) { 441 1.1.10.2 rpaulo if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 442 1.1.10.2 rpaulo KSE_NTXSEGS, MCLBYTES, 0, 0, 443 1.1.10.2 rpaulo &sc->sc_txsoft[i].txs_dmamap)) != 0) { 444 1.1.10.2 rpaulo printf("%s: unable to create tx DMA map %d, " 445 1.1.10.2 rpaulo "error = %d\n", sc->sc_dev.dv_xname, i, error); 446 1.1.10.2 rpaulo goto fail_4; 447 1.1.10.2 rpaulo } 448 1.1.10.2 rpaulo } 449 1.1.10.2 rpaulo for (i = 0; i < KSE_NRXDESC; i++) { 450 1.1.10.2 rpaulo if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 451 1.1.10.2 rpaulo 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 452 1.1.10.2 rpaulo printf("%s: unable to create rx DMA map %d, " 453 1.1.10.2 rpaulo "error = %d\n", sc->sc_dev.dv_xname, i, error); 454 1.1.10.2 rpaulo goto fail_5; 455 1.1.10.2 rpaulo } 456 1.1.10.2 rpaulo sc->sc_rxsoft[i].rxs_mbuf = NULL; 457 1.1.10.2 rpaulo } 458 1.1.10.2 rpaulo 459 1.1.10.2 rpaulo callout_init(&sc->sc_callout); 460 1.1.10.2 rpaulo 461 1.1.10.2 rpaulo ifmedia_init(&sc->sc_media, 0, ifmedia_upd, ifmedia_sts); 462 1.1.10.2 rpaulo ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T, 0, NULL); 463 1.1.10.2 rpaulo ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 464 1.1.10.2 rpaulo ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX, 0, NULL); 465 1.1.10.2 rpaulo ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 466 1.1.10.2 rpaulo ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL); 467 1.1.10.2 rpaulo ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 468 1.1.10.2 rpaulo 469 1.1.10.2 rpaulo printf("%s: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto\n", 470 1.1.10.2 rpaulo sc->sc_dev.dv_xname); 471 1.1.10.2 rpaulo 472 1.1.10.2 rpaulo ifp = &sc->sc_ethercom.ec_if; 473 1.1.10.2 rpaulo strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 474 1.1.10.2 rpaulo ifp->if_softc = sc; 475 1.1.10.2 rpaulo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 476 1.1.10.2 rpaulo ifp->if_ioctl = kse_ioctl; 477 1.1.10.2 rpaulo ifp->if_start = kse_start; 478 1.1.10.2 rpaulo ifp->if_watchdog = kse_watchdog; 479 1.1.10.2 rpaulo ifp->if_init = kse_init; 480 1.1.10.2 rpaulo ifp->if_stop = kse_stop; 481 1.1.10.2 rpaulo IFQ_SET_READY(&ifp->if_snd); 482 1.1.10.2 rpaulo 483 1.1.10.2 rpaulo /* 484 1.1.10.2 rpaulo * KSZ8842 can handle 802.1Q VLAN-sized frames, 485 1.1.10.2 rpaulo * can do IPv4, TCPv4, and UDPv4 checksums in hardware. 486 1.1.10.2 rpaulo */ 487 1.1.10.2 rpaulo sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 488 1.1.10.2 rpaulo ifp->if_capabilities |= 489 1.1.10.2 rpaulo IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 490 1.1.10.2 rpaulo IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 491 1.1.10.2 rpaulo IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 492 1.1.10.2 rpaulo 493 1.1.10.2 rpaulo if_attach(ifp); 494 1.1.10.2 rpaulo ether_ifattach(ifp, enaddr); 495 1.1.10.2 rpaulo return; 496 1.1.10.2 rpaulo 497 1.1.10.2 rpaulo fail_5: 498 1.1.10.2 rpaulo for (i = 0; i < KSE_NRXDESC; i++) { 499 1.1.10.2 rpaulo if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 500 1.1.10.2 rpaulo bus_dmamap_destroy(sc->sc_dmat, 501 1.1.10.2 rpaulo sc->sc_rxsoft[i].rxs_dmamap); 502 1.1.10.2 rpaulo } 503 1.1.10.2 rpaulo fail_4: 504 1.1.10.2 rpaulo for (i = 0; i < KSE_TXQUEUELEN; i++) { 505 1.1.10.2 rpaulo if (sc->sc_txsoft[i].txs_dmamap != NULL) 506 1.1.10.2 rpaulo bus_dmamap_destroy(sc->sc_dmat, 507 1.1.10.2 rpaulo sc->sc_txsoft[i].txs_dmamap); 508 1.1.10.2 rpaulo } 509 1.1.10.2 rpaulo bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 510 1.1.10.2 rpaulo fail_3: 511 1.1.10.2 rpaulo bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 512 1.1.10.2 rpaulo fail_2: 513 1.1.10.2 rpaulo bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 514 1.1.10.2 rpaulo sizeof(struct kse_control_data)); 515 1.1.10.2 rpaulo fail_1: 516 1.1.10.2 rpaulo bus_dmamem_free(sc->sc_dmat, &seg, nseg); 517 1.1.10.2 rpaulo fail_0: 518 1.1.10.2 rpaulo return; 519 1.1.10.2 rpaulo } 520 1.1.10.2 rpaulo 521 1.1.10.2 rpaulo static int 522 1.1.10.2 rpaulo kse_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 523 1.1.10.2 rpaulo { 524 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 525 1.1.10.2 rpaulo struct ifreq *ifr = (struct ifreq *)data; 526 1.1.10.2 rpaulo int s, error; 527 1.1.10.2 rpaulo 528 1.1.10.2 rpaulo s = splnet(); 529 1.1.10.2 rpaulo 530 1.1.10.2 rpaulo switch (cmd) { 531 1.1.10.2 rpaulo case SIOCSIFMEDIA: 532 1.1.10.2 rpaulo case SIOCGIFMEDIA: 533 1.1.10.2 rpaulo error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 534 1.1.10.2 rpaulo break; 535 1.1.10.2 rpaulo 536 1.1.10.2 rpaulo default: 537 1.1.10.2 rpaulo error = ether_ioctl(ifp, cmd, data); 538 1.1.10.2 rpaulo if (cmd == ENETRESET) { 539 1.1.10.2 rpaulo /* 540 1.1.10.2 rpaulo * Multicast list has changed; set the hardware filter 541 1.1.10.2 rpaulo * accordingly. 542 1.1.10.2 rpaulo */ 543 1.1.10.2 rpaulo kse_set_filter(sc); 544 1.1.10.2 rpaulo error = 0; 545 1.1.10.2 rpaulo } 546 1.1.10.2 rpaulo break; 547 1.1.10.2 rpaulo } 548 1.1.10.2 rpaulo 549 1.1.10.2 rpaulo kse_start(ifp); 550 1.1.10.2 rpaulo 551 1.1.10.2 rpaulo splx(s); 552 1.1.10.2 rpaulo return error; 553 1.1.10.2 rpaulo } 554 1.1.10.2 rpaulo 555 1.1.10.2 rpaulo #define KSE_INTRS (INT_DMLCS|INT_DMTS|INT_DMRS|INT_DMRBUS) 556 1.1.10.2 rpaulo 557 1.1.10.2 rpaulo static int 558 1.1.10.2 rpaulo kse_init(struct ifnet *ifp) 559 1.1.10.2 rpaulo { 560 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 561 1.1.10.2 rpaulo unsigned paddr; 562 1.1.10.2 rpaulo int i, error = 0; 563 1.1.10.2 rpaulo 564 1.1.10.2 rpaulo /* cancel pending I/O */ 565 1.1.10.2 rpaulo kse_stop(ifp, 0); 566 1.1.10.2 rpaulo 567 1.1.10.2 rpaulo /* reset all registers but PCI configuration */ 568 1.1.10.2 rpaulo kse_reset(sc); 569 1.1.10.2 rpaulo 570 1.1.10.2 rpaulo /* craft Tx descriptor ring */ 571 1.1.10.2 rpaulo memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 572 1.1.10.2 rpaulo for (i = 0, paddr = KSE_CDTXADDR(sc, 1); i < KSE_NTXDESC - 1; i++) { 573 1.1.10.2 rpaulo sc->sc_txdescs[i].t3 = paddr; 574 1.1.10.2 rpaulo paddr += sizeof(struct tdes); 575 1.1.10.2 rpaulo } 576 1.1.10.2 rpaulo sc->sc_txdescs[KSE_NTXDESC - 1].t3 = KSE_CDTXADDR(sc, 0); 577 1.1.10.2 rpaulo KSE_CDTXSYNC(sc, 0, KSE_NTXDESC, 578 1.1.10.2 rpaulo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 579 1.1.10.2 rpaulo sc->sc_txfree = KSE_NTXDESC; 580 1.1.10.2 rpaulo sc->sc_txnext = 0; 581 1.1.10.2 rpaulo 582 1.1.10.2 rpaulo for (i = 0; i < KSE_TXQUEUELEN; i++) 583 1.1.10.2 rpaulo sc->sc_txsoft[i].txs_mbuf = NULL; 584 1.1.10.2 rpaulo sc->sc_txsfree = KSE_TXQUEUELEN; 585 1.1.10.2 rpaulo sc->sc_txsnext = 0; 586 1.1.10.2 rpaulo sc->sc_txsdirty = 0; 587 1.1.10.2 rpaulo 588 1.1.10.2 rpaulo /* craft Rx descriptor ring */ 589 1.1.10.2 rpaulo memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 590 1.1.10.2 rpaulo for (i = 0, paddr = KSE_CDRXADDR(sc, 1); i < KSE_NRXDESC - 1; i++) { 591 1.1.10.2 rpaulo sc->sc_rxdescs[i].r3 = paddr; 592 1.1.10.2 rpaulo paddr += sizeof(struct rdes); 593 1.1.10.2 rpaulo } 594 1.1.10.2 rpaulo sc->sc_rxdescs[KSE_NRXDESC - 1].r3 = KSE_CDRXADDR(sc, 0); 595 1.1.10.2 rpaulo for (i = 0; i < KSE_NRXDESC; i++) { 596 1.1.10.2 rpaulo if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 597 1.1.10.2 rpaulo if ((error = add_rxbuf(sc, i)) != 0) { 598 1.1.10.2 rpaulo printf("%s: unable to allocate or map rx " 599 1.1.10.2 rpaulo "buffer %d, error = %d\n", 600 1.1.10.2 rpaulo sc->sc_dev.dv_xname, i, error); 601 1.1.10.2 rpaulo rxdrain(sc); 602 1.1.10.2 rpaulo goto out; 603 1.1.10.2 rpaulo } 604 1.1.10.2 rpaulo } 605 1.1.10.2 rpaulo else 606 1.1.10.2 rpaulo KSE_INIT_RXDESC(sc, i); 607 1.1.10.2 rpaulo } 608 1.1.10.2 rpaulo sc->sc_rxptr = 0; 609 1.1.10.2 rpaulo 610 1.1.10.2 rpaulo /* hand Tx/Rx rings to HW */ 611 1.1.10.2 rpaulo CSR_WRITE_4(sc, TDLB, KSE_CDTXADDR(sc, 0)); 612 1.1.10.2 rpaulo CSR_WRITE_4(sc, RDLB, KSE_CDRXADDR(sc, 0)); 613 1.1.10.2 rpaulo 614 1.1.10.2 rpaulo sc->sc_txc = TXC_TEN | TXC_EP | TXC_AC | TXC_FCE; 615 1.1.10.2 rpaulo sc->sc_rxc = RXC_REN | RXC_RU | RXC_FCE; 616 1.1.10.2 rpaulo if (ifp->if_flags & IFF_PROMISC) 617 1.1.10.2 rpaulo sc->sc_rxc |= RXC_RA; 618 1.1.10.2 rpaulo if (ifp->if_flags & IFF_BROADCAST) 619 1.1.10.2 rpaulo sc->sc_rxc |= RXC_RB; 620 1.1.10.2 rpaulo 621 1.1.10.2 rpaulo sc->sc_t1csum = sc->sc_mcsum = 0; 622 1.1.10.2 rpaulo if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) { 623 1.1.10.2 rpaulo sc->sc_rxc |= RXC_ICG; 624 1.1.10.2 rpaulo sc->sc_mcsum |= M_CSUM_IPv4; 625 1.1.10.2 rpaulo } 626 1.1.10.2 rpaulo if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) { 627 1.1.10.2 rpaulo sc->sc_txc |= TXC_ICG; 628 1.1.10.2 rpaulo sc->sc_t1csum |= T1_IPCKG; 629 1.1.10.2 rpaulo } 630 1.1.10.2 rpaulo if (ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) { 631 1.1.10.2 rpaulo sc->sc_rxc |= RXC_TCG; 632 1.1.10.2 rpaulo sc->sc_mcsum |= M_CSUM_TCPv4; 633 1.1.10.2 rpaulo } 634 1.1.10.2 rpaulo if (ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) { 635 1.1.10.2 rpaulo sc->sc_txc |= TXC_TCG; 636 1.1.10.2 rpaulo sc->sc_t1csum |= T1_TCPCKG; 637 1.1.10.2 rpaulo } 638 1.1.10.2 rpaulo if (ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) { 639 1.1.10.2 rpaulo sc->sc_rxc |= RXC_UCG; 640 1.1.10.2 rpaulo sc->sc_mcsum |= M_CSUM_UDPv4; 641 1.1.10.2 rpaulo } 642 1.1.10.2 rpaulo if (ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) { 643 1.1.10.2 rpaulo sc->sc_txc |= TXC_UCG; 644 1.1.10.2 rpaulo sc->sc_t1csum |= T1_UDPCKG; 645 1.1.10.2 rpaulo } 646 1.1.10.2 rpaulo sc->sc_txc |= (kse_burstsize << TXC_BS_SFT); 647 1.1.10.2 rpaulo sc->sc_rxc |= (kse_burstsize << RXC_BS_SFT); 648 1.1.10.2 rpaulo 649 1.1.10.2 rpaulo /* set current media */ 650 1.1.10.2 rpaulo (void)ifmedia_upd(ifp); 651 1.1.10.2 rpaulo 652 1.1.10.2 rpaulo /* enable transmitter and receiver */ 653 1.1.10.2 rpaulo CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 654 1.1.10.2 rpaulo CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); 655 1.1.10.2 rpaulo CSR_WRITE_4(sc, MDRSC, 1); 656 1.1.10.2 rpaulo 657 1.1.10.2 rpaulo /* enable interrupts */ 658 1.1.10.2 rpaulo CSR_WRITE_4(sc, INTST, ~0); 659 1.1.10.2 rpaulo CSR_WRITE_4(sc, INTEN, KSE_INTRS); 660 1.1.10.2 rpaulo 661 1.1.10.2 rpaulo ifp->if_flags |= IFF_RUNNING; 662 1.1.10.2 rpaulo ifp->if_flags &= ~IFF_OACTIVE; 663 1.1.10.2 rpaulo 664 1.1.10.2 rpaulo /* start one second timer */ 665 1.1.10.2 rpaulo callout_reset(&sc->sc_callout, hz, phy_tick, sc); 666 1.1.10.2 rpaulo 667 1.1.10.2 rpaulo out: 668 1.1.10.2 rpaulo if (error) { 669 1.1.10.2 rpaulo ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 670 1.1.10.2 rpaulo ifp->if_timer = 0; 671 1.1.10.2 rpaulo printf("%s: interface not running\n", sc->sc_dev.dv_xname); 672 1.1.10.2 rpaulo } 673 1.1.10.2 rpaulo return error; 674 1.1.10.2 rpaulo } 675 1.1.10.2 rpaulo 676 1.1.10.2 rpaulo static void 677 1.1.10.2 rpaulo kse_stop(struct ifnet *ifp, int disable) 678 1.1.10.2 rpaulo { 679 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 680 1.1.10.2 rpaulo struct kse_txsoft *txs; 681 1.1.10.2 rpaulo int i; 682 1.1.10.2 rpaulo 683 1.1.10.2 rpaulo callout_stop(&sc->sc_callout); 684 1.1.10.2 rpaulo 685 1.1.10.2 rpaulo sc->sc_txc &= ~TXC_TEN; 686 1.1.10.2 rpaulo sc->sc_rxc &= ~RXC_REN; 687 1.1.10.2 rpaulo CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 688 1.1.10.2 rpaulo CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); 689 1.1.10.2 rpaulo 690 1.1.10.2 rpaulo for (i = 0; i < KSE_TXQUEUELEN; i++) { 691 1.1.10.2 rpaulo txs = &sc->sc_txsoft[i]; 692 1.1.10.2 rpaulo if (txs->txs_mbuf != NULL) { 693 1.1.10.2 rpaulo bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 694 1.1.10.2 rpaulo m_freem(txs->txs_mbuf); 695 1.1.10.2 rpaulo txs->txs_mbuf = NULL; 696 1.1.10.2 rpaulo } 697 1.1.10.2 rpaulo } 698 1.1.10.2 rpaulo 699 1.1.10.2 rpaulo if (disable) 700 1.1.10.2 rpaulo rxdrain(sc); 701 1.1.10.2 rpaulo 702 1.1.10.2 rpaulo ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 703 1.1.10.2 rpaulo ifp->if_timer = 0; 704 1.1.10.2 rpaulo } 705 1.1.10.2 rpaulo 706 1.1.10.2 rpaulo static void 707 1.1.10.2 rpaulo kse_reset(struct kse_softc *sc) 708 1.1.10.2 rpaulo { 709 1.1.10.2 rpaulo 710 1.1.10.2 rpaulo CSR_WRITE_2(sc, GRR, 1); 711 1.1.10.2 rpaulo delay(1000); /* PDF does not mention the delay amount */ 712 1.1.10.2 rpaulo CSR_WRITE_2(sc, GRR, 0); 713 1.1.10.2 rpaulo 714 1.1.10.2 rpaulo CSR_WRITE_2(sc, CIDR, 1); 715 1.1.10.2 rpaulo } 716 1.1.10.2 rpaulo 717 1.1.10.2 rpaulo static void 718 1.1.10.2 rpaulo kse_watchdog(struct ifnet *ifp) 719 1.1.10.2 rpaulo { 720 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 721 1.1.10.2 rpaulo 722 1.1.10.2 rpaulo /* 723 1.1.10.2 rpaulo * Since we're not interrupting every packet, sweep 724 1.1.10.2 rpaulo * up before we report an error. 725 1.1.10.2 rpaulo */ 726 1.1.10.2 rpaulo txreap(sc); 727 1.1.10.2 rpaulo 728 1.1.10.2 rpaulo if (sc->sc_txfree != KSE_NTXDESC) { 729 1.1.10.2 rpaulo printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 730 1.1.10.2 rpaulo sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 731 1.1.10.2 rpaulo sc->sc_txnext); 732 1.1.10.2 rpaulo ifp->if_oerrors++; 733 1.1.10.2 rpaulo 734 1.1.10.2 rpaulo /* Reset the interface. */ 735 1.1.10.2 rpaulo kse_init(ifp); 736 1.1.10.2 rpaulo } 737 1.1.10.2 rpaulo else if (ifp->if_flags & IFF_DEBUG) 738 1.1.10.2 rpaulo printf("%s: recovered from device timeout\n", 739 1.1.10.2 rpaulo sc->sc_dev.dv_xname); 740 1.1.10.2 rpaulo 741 1.1.10.2 rpaulo /* Try to get more packets going. */ 742 1.1.10.2 rpaulo kse_start(ifp); 743 1.1.10.2 rpaulo } 744 1.1.10.2 rpaulo 745 1.1.10.2 rpaulo static void 746 1.1.10.2 rpaulo kse_start(struct ifnet *ifp) 747 1.1.10.2 rpaulo { 748 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 749 1.1.10.2 rpaulo struct mbuf *m0; 750 1.1.10.2 rpaulo struct kse_txsoft *txs; 751 1.1.10.2 rpaulo bus_dmamap_t dmamap; 752 1.1.10.2 rpaulo int error, nexttx, lasttx, ofree, seg; 753 1.1.10.2 rpaulo 754 1.1.10.2 rpaulo lasttx = -1; 755 1.1.10.2 rpaulo 756 1.1.10.2 rpaulo if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 757 1.1.10.2 rpaulo return; 758 1.1.10.2 rpaulo 759 1.1.10.2 rpaulo /* 760 1.1.10.2 rpaulo * Remember the previous number of free descriptors. 761 1.1.10.2 rpaulo */ 762 1.1.10.2 rpaulo ofree = sc->sc_txfree; 763 1.1.10.2 rpaulo 764 1.1.10.2 rpaulo /* 765 1.1.10.2 rpaulo * Loop through the send queue, setting up transmit descriptors 766 1.1.10.2 rpaulo * until we drain the queue, or use up all available transmit 767 1.1.10.2 rpaulo * descriptors. 768 1.1.10.2 rpaulo */ 769 1.1.10.2 rpaulo for (;;) { 770 1.1.10.2 rpaulo IFQ_POLL(&ifp->if_snd, m0); 771 1.1.10.2 rpaulo if (m0 == NULL) 772 1.1.10.2 rpaulo break; 773 1.1.10.2 rpaulo 774 1.1.10.2 rpaulo if (sc->sc_txsfree < KSE_TXQUEUE_GC) { 775 1.1.10.2 rpaulo txreap(sc); 776 1.1.10.2 rpaulo if (sc->sc_txsfree == 0) 777 1.1.10.2 rpaulo break; 778 1.1.10.2 rpaulo } 779 1.1.10.2 rpaulo txs = &sc->sc_txsoft[sc->sc_txsnext]; 780 1.1.10.2 rpaulo dmamap = txs->txs_dmamap; 781 1.1.10.2 rpaulo 782 1.1.10.2 rpaulo error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 783 1.1.10.2 rpaulo BUS_DMA_WRITE|BUS_DMA_NOWAIT); 784 1.1.10.2 rpaulo if (error) { 785 1.1.10.2 rpaulo if (error == EFBIG) { 786 1.1.10.2 rpaulo printf("%s: Tx packet consumes too many " 787 1.1.10.2 rpaulo "DMA segments, dropping...\n", 788 1.1.10.2 rpaulo sc->sc_dev.dv_xname); 789 1.1.10.2 rpaulo IFQ_DEQUEUE(&ifp->if_snd, m0); 790 1.1.10.2 rpaulo m_freem(m0); 791 1.1.10.2 rpaulo continue; 792 1.1.10.2 rpaulo } 793 1.1.10.2 rpaulo /* Short on resources, just stop for now. */ 794 1.1.10.2 rpaulo break; 795 1.1.10.2 rpaulo } 796 1.1.10.2 rpaulo 797 1.1.10.2 rpaulo if (dmamap->dm_nsegs > sc->sc_txfree) { 798 1.1.10.2 rpaulo /* 799 1.1.10.2 rpaulo * Not enough free descriptors to transmit this 800 1.1.10.2 rpaulo * packet. We haven't committed anything yet, 801 1.1.10.2 rpaulo * so just unload the DMA map, put the packet 802 1.1.10.2 rpaulo * back on the queue, and punt. Notify the upper 803 1.1.10.2 rpaulo * layer that there are not more slots left. 804 1.1.10.2 rpaulo */ 805 1.1.10.2 rpaulo ifp->if_flags |= IFF_OACTIVE; 806 1.1.10.2 rpaulo bus_dmamap_unload(sc->sc_dmat, dmamap); 807 1.1.10.2 rpaulo break; 808 1.1.10.2 rpaulo } 809 1.1.10.2 rpaulo 810 1.1.10.2 rpaulo IFQ_DEQUEUE(&ifp->if_snd, m0); 811 1.1.10.2 rpaulo 812 1.1.10.2 rpaulo /* 813 1.1.10.2 rpaulo * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 814 1.1.10.2 rpaulo */ 815 1.1.10.2 rpaulo 816 1.1.10.2 rpaulo bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 817 1.1.10.2 rpaulo BUS_DMASYNC_PREWRITE); 818 1.1.10.2 rpaulo 819 1.1.10.2 rpaulo for (nexttx = sc->sc_txnext, seg = 0; 820 1.1.10.2 rpaulo seg < dmamap->dm_nsegs; 821 1.1.10.2 rpaulo seg++, nexttx = KSE_NEXTTX(nexttx)) { 822 1.1.10.2 rpaulo struct tdes *tdes = &sc->sc_txdescs[nexttx]; 823 1.1.10.2 rpaulo /* 824 1.1.10.2 rpaulo * If this is the first descriptor we're 825 1.1.10.2 rpaulo * enqueueing, don't set the OWN bit just 826 1.1.10.2 rpaulo * yet. That could cause a race condition. 827 1.1.10.2 rpaulo * We'll do it below. 828 1.1.10.2 rpaulo */ 829 1.1.10.2 rpaulo tdes->t2 = dmamap->dm_segs[seg].ds_addr; 830 1.1.10.2 rpaulo tdes->t1 = sc->sc_t1csum 831 1.1.10.2 rpaulo | (dmamap->dm_segs[seg].ds_len & T1_TBS_MASK); 832 1.1.10.2 rpaulo if (nexttx != sc->sc_txnext) 833 1.1.10.2 rpaulo tdes->t0 = T0_OWN; 834 1.1.10.2 rpaulo lasttx = nexttx; 835 1.1.10.2 rpaulo } 836 1.1.10.2 rpaulo #if 0 837 1.1.10.2 rpaulo /* 838 1.1.10.2 rpaulo * T1_IC bit could schedule Tx frame done interrupt here, 839 1.1.10.2 rpaulo * but this driver takes a "shoot away" Tx strategy. 840 1.1.10.2 rpaulo */ 841 1.1.10.2 rpaulo #else 842 1.1.10.2 rpaulo { 843 1.1.10.2 rpaulo /* 844 1.1.10.2 rpaulo * Outgoing NFS mbuf must be unloaded when Tx completed. 845 1.1.10.2 rpaulo * Without T1_IC NFS mbuf is left unack'ed for excessive 846 1.1.10.2 rpaulo * time and NFS stops to proceed until kse_watchdog() 847 1.1.10.2 rpaulo * calls txreap() to reclaim the unack'ed mbuf. 848 1.1.10.2 rpaulo * It's painful to tranverse every mbuf chain to determine 849 1.1.10.2 rpaulo * whether someone is waiting for Tx completion. 850 1.1.10.2 rpaulo */ 851 1.1.10.2 rpaulo struct mbuf *m = m0; 852 1.1.10.2 rpaulo do { 853 1.1.10.2 rpaulo if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 854 1.1.10.2 rpaulo sc->sc_txdescs[lasttx].t1 |= T1_IC; 855 1.1.10.2 rpaulo break; 856 1.1.10.2 rpaulo } 857 1.1.10.2 rpaulo } while ((m = m->m_next) != NULL); 858 1.1.10.2 rpaulo } 859 1.1.10.2 rpaulo #endif 860 1.1.10.2 rpaulo 861 1.1.10.2 rpaulo /* write last T0_OWN bit of the 1st segment */ 862 1.1.10.2 rpaulo sc->sc_txdescs[lasttx].t1 |= T1_LS; 863 1.1.10.2 rpaulo sc->sc_txdescs[sc->sc_txnext].t1 |= T1_FS; 864 1.1.10.2 rpaulo sc->sc_txdescs[sc->sc_txnext].t0 = T0_OWN; 865 1.1.10.2 rpaulo KSE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 866 1.1.10.2 rpaulo BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 867 1.1.10.2 rpaulo 868 1.1.10.2 rpaulo /* tell DMA start transmit */ 869 1.1.10.2 rpaulo CSR_WRITE_4(sc, MDTSC, 1); 870 1.1.10.2 rpaulo 871 1.1.10.2 rpaulo txs->txs_mbuf = m0; 872 1.1.10.2 rpaulo txs->txs_firstdesc = sc->sc_txnext; 873 1.1.10.2 rpaulo txs->txs_lastdesc = lasttx; 874 1.1.10.2 rpaulo txs->txs_ndesc = dmamap->dm_nsegs; 875 1.1.10.2 rpaulo 876 1.1.10.2 rpaulo sc->sc_txfree -= txs->txs_ndesc; 877 1.1.10.2 rpaulo sc->sc_txnext = nexttx; 878 1.1.10.2 rpaulo sc->sc_txsfree--; 879 1.1.10.2 rpaulo sc->sc_txsnext = KSE_NEXTTXS(sc->sc_txsnext); 880 1.1.10.2 rpaulo #if NBPFILTER > 0 881 1.1.10.2 rpaulo /* 882 1.1.10.2 rpaulo * Pass the packet to any BPF listeners. 883 1.1.10.2 rpaulo */ 884 1.1.10.2 rpaulo if (ifp->if_bpf) 885 1.1.10.2 rpaulo bpf_mtap(ifp->if_bpf, m0); 886 1.1.10.2 rpaulo #endif /* NBPFILTER > 0 */ 887 1.1.10.2 rpaulo } 888 1.1.10.2 rpaulo 889 1.1.10.2 rpaulo if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 890 1.1.10.2 rpaulo /* No more slots left; notify upper layer. */ 891 1.1.10.2 rpaulo ifp->if_flags |= IFF_OACTIVE; 892 1.1.10.2 rpaulo } 893 1.1.10.2 rpaulo if (sc->sc_txfree != ofree) { 894 1.1.10.2 rpaulo /* Set a watchdog timer in case the chip flakes out. */ 895 1.1.10.2 rpaulo ifp->if_timer = 5; 896 1.1.10.2 rpaulo } 897 1.1.10.2 rpaulo } 898 1.1.10.2 rpaulo 899 1.1.10.2 rpaulo static void 900 1.1.10.2 rpaulo kse_set_filter(struct kse_softc *sc) 901 1.1.10.2 rpaulo { 902 1.1.10.2 rpaulo #if 0 /* later */ 903 1.1.10.2 rpaulo struct ether_multistep step; 904 1.1.10.2 rpaulo struct ether_multi *enm; 905 1.1.10.2 rpaulo struct ifnet *ifp = &sc->sc_ethercom.ec_if; 906 1.1.10.2 rpaulo int cnt = 0; 907 1.1.10.2 rpaulo 908 1.1.10.2 rpaulo ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 909 1.1.10.2 rpaulo while (enm != NULL) { 910 1.1.10.2 rpaulo if (memcmp(enm->enm_addrlo, 911 1.1.10.2 rpaulo enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 912 1.1.10.2 rpaulo ; 913 1.1.10.2 rpaulo } 914 1.1.10.2 rpaulo ETHER_NEXT_MULTI(step, enm); 915 1.1.10.2 rpaulo cnt++; 916 1.1.10.2 rpaulo } 917 1.1.10.2 rpaulo return; 918 1.1.10.2 rpaulo #endif 919 1.1.10.2 rpaulo } 920 1.1.10.2 rpaulo 921 1.1.10.2 rpaulo static int 922 1.1.10.2 rpaulo add_rxbuf(struct kse_softc *sc, int idx) 923 1.1.10.2 rpaulo { 924 1.1.10.2 rpaulo struct kse_rxsoft *rxs = &sc->sc_rxsoft[idx]; 925 1.1.10.2 rpaulo struct mbuf *m; 926 1.1.10.2 rpaulo int error; 927 1.1.10.2 rpaulo 928 1.1.10.2 rpaulo MGETHDR(m, M_DONTWAIT, MT_DATA); 929 1.1.10.2 rpaulo if (m == NULL) 930 1.1.10.2 rpaulo return ENOBUFS; 931 1.1.10.2 rpaulo 932 1.1.10.2 rpaulo MCLGET(m, M_DONTWAIT); 933 1.1.10.2 rpaulo if ((m->m_flags & M_EXT) == 0) { 934 1.1.10.2 rpaulo m_freem(m); 935 1.1.10.2 rpaulo return ENOBUFS; 936 1.1.10.2 rpaulo } 937 1.1.10.2 rpaulo 938 1.1.10.2 rpaulo if (rxs->rxs_mbuf != NULL) 939 1.1.10.2 rpaulo bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 940 1.1.10.2 rpaulo 941 1.1.10.2 rpaulo rxs->rxs_mbuf = m; 942 1.1.10.2 rpaulo 943 1.1.10.2 rpaulo error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 944 1.1.10.2 rpaulo m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 945 1.1.10.2 rpaulo if (error) { 946 1.1.10.2 rpaulo printf("%s: can't load rx DMA map %d, error = %d\n", 947 1.1.10.2 rpaulo sc->sc_dev.dv_xname, idx, error); 948 1.1.10.2 rpaulo panic("kse_add_rxbuf"); 949 1.1.10.2 rpaulo } 950 1.1.10.2 rpaulo 951 1.1.10.2 rpaulo bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 952 1.1.10.2 rpaulo rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 953 1.1.10.2 rpaulo 954 1.1.10.2 rpaulo KSE_INIT_RXDESC(sc, idx); 955 1.1.10.2 rpaulo 956 1.1.10.2 rpaulo return 0; 957 1.1.10.2 rpaulo } 958 1.1.10.2 rpaulo 959 1.1.10.2 rpaulo static void 960 1.1.10.2 rpaulo rxdrain(struct kse_softc *sc) 961 1.1.10.2 rpaulo { 962 1.1.10.2 rpaulo struct kse_rxsoft *rxs; 963 1.1.10.2 rpaulo int i; 964 1.1.10.2 rpaulo 965 1.1.10.2 rpaulo for (i = 0; i < KSE_NRXDESC; i++) { 966 1.1.10.2 rpaulo rxs = &sc->sc_rxsoft[i]; 967 1.1.10.2 rpaulo if (rxs->rxs_mbuf != NULL) { 968 1.1.10.2 rpaulo bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 969 1.1.10.2 rpaulo m_freem(rxs->rxs_mbuf); 970 1.1.10.2 rpaulo rxs->rxs_mbuf = NULL; 971 1.1.10.2 rpaulo } 972 1.1.10.2 rpaulo } 973 1.1.10.2 rpaulo } 974 1.1.10.2 rpaulo 975 1.1.10.2 rpaulo static int 976 1.1.10.2 rpaulo kse_intr(void *arg) 977 1.1.10.2 rpaulo { 978 1.1.10.2 rpaulo struct kse_softc *sc = arg; 979 1.1.10.2 rpaulo unsigned isr; 980 1.1.10.2 rpaulo 981 1.1.10.2 rpaulo if ((isr = CSR_READ_4(sc, INTST)) == 0) 982 1.1.10.2 rpaulo return 0; 983 1.1.10.2 rpaulo 984 1.1.10.2 rpaulo if (isr & INT_DMRS) 985 1.1.10.2 rpaulo rxintr(sc); 986 1.1.10.2 rpaulo if (isr & INT_DMTS) 987 1.1.10.2 rpaulo txreap(sc); 988 1.1.10.2 rpaulo if (isr & INT_DMLCS) 989 1.1.10.2 rpaulo lnkchg(sc); 990 1.1.10.2 rpaulo if (isr & INT_DMRBUS) 991 1.1.10.2 rpaulo printf("%s: Rx descriptor full\n", sc->sc_dev.dv_xname); 992 1.1.10.2 rpaulo 993 1.1.10.2 rpaulo CSR_WRITE_4(sc, INTST, isr); 994 1.1.10.2 rpaulo return 1; 995 1.1.10.2 rpaulo } 996 1.1.10.2 rpaulo 997 1.1.10.2 rpaulo static void 998 1.1.10.2 rpaulo rxintr(struct kse_softc *sc) 999 1.1.10.2 rpaulo { 1000 1.1.10.2 rpaulo struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1001 1.1.10.2 rpaulo struct kse_rxsoft *rxs; 1002 1.1.10.2 rpaulo struct mbuf *m; 1003 1.1.10.2 rpaulo unsigned rxstat; 1004 1.1.10.2 rpaulo int i, len; 1005 1.1.10.2 rpaulo 1006 1.1.10.2 rpaulo for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = KSE_NEXTRX(i)) { 1007 1.1.10.2 rpaulo rxs = &sc->sc_rxsoft[i]; 1008 1.1.10.2 rpaulo 1009 1.1.10.2 rpaulo KSE_CDRXSYNC(sc, i, 1010 1.1.10.2 rpaulo BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1011 1.1.10.2 rpaulo 1012 1.1.10.2 rpaulo rxstat = sc->sc_rxdescs[i].r0; 1013 1.1.10.2 rpaulo 1014 1.1.10.2 rpaulo if (rxstat & R0_OWN) /* desc is left empty */ 1015 1.1.10.2 rpaulo break; 1016 1.1.10.2 rpaulo 1017 1.1.10.2 rpaulo /* R0_FS|R0_LS must have been marked for this desc */ 1018 1.1.10.2 rpaulo 1019 1.1.10.2 rpaulo if (rxstat & R0_ES) { 1020 1.1.10.2 rpaulo ifp->if_ierrors++; 1021 1.1.10.2 rpaulo #define PRINTERR(bit, str) \ 1022 1.1.10.2 rpaulo if (rxstat & (bit)) \ 1023 1.1.10.2 rpaulo printf("%s: receive error: %s\n", \ 1024 1.1.10.2 rpaulo sc->sc_dev.dv_xname, str) 1025 1.1.10.2 rpaulo PRINTERR(R0_TL, "frame too long"); 1026 1.1.10.2 rpaulo PRINTERR(R0_RF, "runt frame"); 1027 1.1.10.2 rpaulo PRINTERR(R0_CE, "bad FCS"); 1028 1.1.10.2 rpaulo #undef PRINTERR 1029 1.1.10.2 rpaulo KSE_INIT_RXDESC(sc, i); 1030 1.1.10.2 rpaulo continue; 1031 1.1.10.2 rpaulo } 1032 1.1.10.2 rpaulo 1033 1.1.10.2 rpaulo /* HW errata; frame might be too small or too large */ 1034 1.1.10.2 rpaulo 1035 1.1.10.2 rpaulo bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1036 1.1.10.2 rpaulo rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1037 1.1.10.2 rpaulo 1038 1.1.10.2 rpaulo len = rxstat & R0_FL_MASK; 1039 1.1.10.2 rpaulo m = rxs->rxs_mbuf; 1040 1.1.10.2 rpaulo 1041 1.1.10.2 rpaulo if (add_rxbuf(sc, i) != 0) { 1042 1.1.10.2 rpaulo ifp->if_ierrors++; 1043 1.1.10.2 rpaulo KSE_INIT_RXDESC(sc, i); 1044 1.1.10.2 rpaulo bus_dmamap_sync(sc->sc_dmat, 1045 1.1.10.2 rpaulo rxs->rxs_dmamap, 0, 1046 1.1.10.2 rpaulo rxs->rxs_dmamap->dm_mapsize, 1047 1.1.10.2 rpaulo BUS_DMASYNC_PREREAD); 1048 1.1.10.2 rpaulo continue; 1049 1.1.10.2 rpaulo } 1050 1.1.10.2 rpaulo 1051 1.1.10.2 rpaulo ifp->if_ipackets++; 1052 1.1.10.2 rpaulo m->m_flags |= M_HASFCS; 1053 1.1.10.2 rpaulo m->m_pkthdr.rcvif = ifp; 1054 1.1.10.2 rpaulo m->m_pkthdr.len = m->m_len = len; 1055 1.1.10.2 rpaulo 1056 1.1.10.2 rpaulo if (sc->sc_mcsum) { 1057 1.1.10.2 rpaulo m->m_pkthdr.csum_flags |= sc->sc_mcsum; 1058 1.1.10.2 rpaulo if (rxstat & R0_IPE) 1059 1.1.10.2 rpaulo m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1060 1.1.10.2 rpaulo if (rxstat & (R0_TCPE | R0_UDPE)) 1061 1.1.10.2 rpaulo m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1062 1.1.10.2 rpaulo } 1063 1.1.10.2 rpaulo #if NBPFILTER > 0 1064 1.1.10.2 rpaulo if (ifp->if_bpf) 1065 1.1.10.2 rpaulo bpf_mtap(ifp->if_bpf, m); 1066 1.1.10.2 rpaulo #endif /* NBPFILTER > 0 */ 1067 1.1.10.2 rpaulo (*ifp->if_input)(ifp, m); 1068 1.1.10.2 rpaulo #ifdef KSEDIAGNOSTIC 1069 1.1.10.2 rpaulo if (kse_monitor_rxintr > 0) { 1070 1.1.10.2 rpaulo printf("m stat %x data %p len %d\n", 1071 1.1.10.2 rpaulo rxstat, m->m_data, m->m_len); 1072 1.1.10.2 rpaulo } 1073 1.1.10.2 rpaulo #endif 1074 1.1.10.2 rpaulo } 1075 1.1.10.2 rpaulo sc->sc_rxptr = i; 1076 1.1.10.2 rpaulo } 1077 1.1.10.2 rpaulo 1078 1.1.10.2 rpaulo static void 1079 1.1.10.2 rpaulo txreap(struct kse_softc *sc) 1080 1.1.10.2 rpaulo { 1081 1.1.10.2 rpaulo struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1082 1.1.10.2 rpaulo struct kse_txsoft *txs; 1083 1.1.10.2 rpaulo unsigned txstat; 1084 1.1.10.2 rpaulo int i; 1085 1.1.10.2 rpaulo 1086 1.1.10.2 rpaulo ifp->if_flags &= ~IFF_OACTIVE; 1087 1.1.10.2 rpaulo 1088 1.1.10.2 rpaulo for (i = sc->sc_txsdirty; sc->sc_txsfree != KSE_TXQUEUELEN; 1089 1.1.10.2 rpaulo i = KSE_NEXTTXS(i), sc->sc_txsfree++) { 1090 1.1.10.2 rpaulo txs = &sc->sc_txsoft[i]; 1091 1.1.10.2 rpaulo 1092 1.1.10.2 rpaulo KSE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1093 1.1.10.2 rpaulo BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1094 1.1.10.2 rpaulo 1095 1.1.10.2 rpaulo txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1096 1.1.10.2 rpaulo 1097 1.1.10.2 rpaulo if (txstat & T0_OWN) /* desc is still in use */ 1098 1.1.10.2 rpaulo break; 1099 1.1.10.2 rpaulo 1100 1.1.10.2 rpaulo /* there is no way to tell transmission status per frame */ 1101 1.1.10.2 rpaulo 1102 1.1.10.2 rpaulo ifp->if_opackets++; 1103 1.1.10.2 rpaulo 1104 1.1.10.2 rpaulo sc->sc_txfree += txs->txs_ndesc; 1105 1.1.10.2 rpaulo bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1106 1.1.10.2 rpaulo 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1107 1.1.10.2 rpaulo bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1108 1.1.10.2 rpaulo m_freem(txs->txs_mbuf); 1109 1.1.10.2 rpaulo txs->txs_mbuf = NULL; 1110 1.1.10.2 rpaulo } 1111 1.1.10.2 rpaulo sc->sc_txsdirty = i; 1112 1.1.10.2 rpaulo if (sc->sc_txsfree == KSE_TXQUEUELEN) 1113 1.1.10.2 rpaulo ifp->if_timer = 0; 1114 1.1.10.2 rpaulo } 1115 1.1.10.2 rpaulo 1116 1.1.10.2 rpaulo static void 1117 1.1.10.2 rpaulo lnkchg(struct kse_softc *sc) 1118 1.1.10.2 rpaulo { 1119 1.1.10.2 rpaulo struct ifmediareq ifmr; 1120 1.1.10.2 rpaulo 1121 1.1.10.2 rpaulo #if 0 /* rambling link status */ 1122 1.1.10.2 rpaulo printf("%s: link %s\n", sc->sc_dev.dv_xname, 1123 1.1.10.2 rpaulo (CSR_READ_2(sc, P1SR) & (1U << 5)) ? "up" : "down"); 1124 1.1.10.2 rpaulo #endif 1125 1.1.10.2 rpaulo ifmedia_sts(&sc->sc_ethercom.ec_if, &ifmr); 1126 1.1.10.2 rpaulo } 1127 1.1.10.2 rpaulo 1128 1.1.10.2 rpaulo static int 1129 1.1.10.2 rpaulo ifmedia_upd(struct ifnet *ifp) 1130 1.1.10.2 rpaulo { 1131 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 1132 1.1.10.2 rpaulo struct ifmedia *ifm = &sc->sc_media; 1133 1.1.10.2 rpaulo unsigned ctl; 1134 1.1.10.2 rpaulo 1135 1.1.10.2 rpaulo ctl = 0; 1136 1.1.10.2 rpaulo if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1137 1.1.10.2 rpaulo ctl |= (1U << 13); /* restart AN */ 1138 1.1.10.2 rpaulo ctl |= (1U << 7); /* enable AN */ 1139 1.1.10.2 rpaulo ctl |= (1U << 4); /* advertise flow control pause */ 1140 1.1.10.2 rpaulo ctl |= (1U << 3) | (1U << 2) | (1U << 1) | (1U << 0); 1141 1.1.10.2 rpaulo } 1142 1.1.10.2 rpaulo else { 1143 1.1.10.2 rpaulo if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 1144 1.1.10.2 rpaulo ctl |= (1U << 6); 1145 1.1.10.2 rpaulo if (ifm->ifm_media & IFM_FDX) 1146 1.1.10.2 rpaulo ctl |= (1U << 5); 1147 1.1.10.2 rpaulo } 1148 1.1.10.2 rpaulo CSR_WRITE_2(sc, P1CR4, ctl); 1149 1.1.10.2 rpaulo 1150 1.1.10.2 rpaulo sc->sc_media_active = IFM_NONE; 1151 1.1.10.2 rpaulo sc->sc_media_status = IFM_AVALID; 1152 1.1.10.2 rpaulo 1153 1.1.10.2 rpaulo return 0; 1154 1.1.10.2 rpaulo } 1155 1.1.10.2 rpaulo 1156 1.1.10.2 rpaulo static void 1157 1.1.10.2 rpaulo ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1158 1.1.10.2 rpaulo { 1159 1.1.10.2 rpaulo struct kse_softc *sc = ifp->if_softc; 1160 1.1.10.2 rpaulo struct ifmedia *ifm = &sc->sc_media; 1161 1.1.10.2 rpaulo unsigned ctl, sts, result; 1162 1.1.10.2 rpaulo 1163 1.1.10.2 rpaulo ifmr->ifm_status = IFM_AVALID; 1164 1.1.10.2 rpaulo ifmr->ifm_active = IFM_ETHER; 1165 1.1.10.2 rpaulo 1166 1.1.10.2 rpaulo ctl = CSR_READ_2(sc, P1CR4); 1167 1.1.10.2 rpaulo sts = CSR_READ_2(sc, P1SR); 1168 1.1.10.2 rpaulo if ((sts & (1U << 5)) == 0) { 1169 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_NONE; 1170 1.1.10.2 rpaulo goto out; /* link is down */ 1171 1.1.10.2 rpaulo } 1172 1.1.10.2 rpaulo ifmr->ifm_status |= IFM_ACTIVE; 1173 1.1.10.2 rpaulo if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1174 1.1.10.2 rpaulo if ((sts & (1U << 6)) == 0) { 1175 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_NONE; 1176 1.1.10.2 rpaulo goto out; /* negotiation in progress */ 1177 1.1.10.2 rpaulo } 1178 1.1.10.2 rpaulo result = ctl & sts & 017; 1179 1.1.10.2 rpaulo if (result & (1U << 3)) 1180 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1181 1.1.10.2 rpaulo else if (result & (1U << 2)) 1182 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_100_TX; 1183 1.1.10.2 rpaulo else if (result & (1U << 1)) 1184 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1185 1.1.10.2 rpaulo else if (result & (1U << 0)) 1186 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_10_T; 1187 1.1.10.2 rpaulo else 1188 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_NONE; 1189 1.1.10.2 rpaulo if (ctl & (1U << 4)) 1190 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 1191 1.1.10.2 rpaulo if (sts & (1U << 4)) 1192 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 1193 1.1.10.2 rpaulo } 1194 1.1.10.2 rpaulo else { 1195 1.1.10.2 rpaulo ifmr->ifm_active |= (sts & (1U << 10)) ? IFM_100_TX : IFM_10_T; 1196 1.1.10.2 rpaulo if (sts & (1U << 9)) 1197 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_FDX; 1198 1.1.10.2 rpaulo if (sts & (1U << 12)) 1199 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 1200 1.1.10.2 rpaulo if (sts & (1U << 11)) 1201 1.1.10.2 rpaulo ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 1202 1.1.10.2 rpaulo } 1203 1.1.10.2 rpaulo 1204 1.1.10.2 rpaulo out: 1205 1.1.10.2 rpaulo sc->sc_media_status = ifmr->ifm_status; 1206 1.1.10.2 rpaulo sc->sc_media_active = ifmr->ifm_active; 1207 1.1.10.2 rpaulo } 1208 1.1.10.2 rpaulo 1209 1.1.10.2 rpaulo static void 1210 1.1.10.2 rpaulo phy_tick(void *arg) 1211 1.1.10.2 rpaulo { 1212 1.1.10.2 rpaulo struct kse_softc *sc = arg; 1213 1.1.10.2 rpaulo struct ifmediareq ifmr; 1214 1.1.10.2 rpaulo int s; 1215 1.1.10.2 rpaulo 1216 1.1.10.2 rpaulo s = splnet(); 1217 1.1.10.2 rpaulo ifmedia_sts(&sc->sc_ethercom.ec_if, &ifmr); 1218 1.1.10.2 rpaulo splx(s); 1219 1.1.10.2 rpaulo 1220 1.1.10.2 rpaulo callout_reset(&sc->sc_callout, hz, phy_tick, sc); 1221 1.1.10.2 rpaulo } 1222
Indexes created Tue Oct 21 08:09:48 GMT 2025