if_kse.c revision 1.6
1 /* $NetBSD: if_kse.c,v 1.6 2007/10/14 11:49:39 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Tohru Nishimura 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tohru Nishimura. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_kse.c,v 1.6 2007/10/14 11:49:39 nisimura Exp $"); 34 35 #include "bpfilter.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/callout.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/ioctl.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/queue.h> 47 48 #include <machine/endian.h> 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <net/if.h> 53 #include <net/if_media.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 57 #if NBPFILTER > 0 58 #include <net/bpf.h> 59 #endif 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #define CSR_READ_4(sc, off) \ 66 bus_space_read_4(sc->sc_st, sc->sc_sh, off) 67 #define CSR_WRITE_4(sc, off, val) \ 68 bus_space_write_4(sc->sc_st, sc->sc_sh, off, val) 69 #define CSR_READ_2(sc, off) \ 70 bus_space_read_2(sc->sc_st, sc->sc_sh, off) 71 #define CSR_WRITE_2(sc, off, val) \ 72 bus_space_write_2(sc->sc_st, sc->sc_sh, off, val) 73 74 #define MDTXC 0x000 /* DMA transmit control */ 75 #define MDRXC 0x004 /* DMA receive control */ 76 #define MDTSC 0x008 /* DMA transmit start */ 77 #define MDRSC 0x00c /* DMA receive start */ 78 #define TDLB 0x010 /* transmit descriptor list base */ 79 #define RDLB 0x014 /* receive descriptor list base */ 80 #define INTEN 0x028 /* interrupt enable */ 81 #define INTST 0x02c /* interrupt status */ 82 #define MTR0 0x100 /* multicast table 31:0 */ 83 #define MTR1 0x104 /* multicast table 63:32 */ 84 #define MARL 0x200 /* MAC address low */ 85 #define MARM 0x202 /* MAC address middle */ 86 #define MARH 0x204 /* MAC address high */ 87 #define GRR 0x216 /* global reset */ 88 #define CIDR 0x400 /* chip ID and enable */ 89 #define CGCR 0x40a /* chip global control */ 90 #define P1CR4 0x512 /* port 1 control 4 */ 91 #define P1SR 0x514 /* port 1 status */ 92 93 #define TXC_BS_MSK 0x3f000000 /* burst size */ 94 #define TXC_BS_SFT (24) /* 1,2,4,8,16,32 or 0 for unlimited */ 95 #define TXC_UCG (1U<<18) /* generate UDP checksum */ 96 #define TXC_TCG (1U<<17) /* generate TCP checksum */ 97 #define TXC_ICG (1U<<16) /* generate IP checksum */ 98 #define TXC_FCE (1U<<9) /* enable flowcontrol */ 99 #define TXC_EP (1U<<2) /* enable automatic padding */ 100 #define TXC_AC (1U<<1) /* add CRC to frame */ 101 #define TXC_TEN (1) /* enable DMA to run */ 102 103 #define RXC_BS_MSK 0x3f000000 /* burst size */ 104 #define RXC_BS_SFT (24) /* 1,2,4,8,16,32 or 0 for unlimited */ 105 #define RXC_IHAE (1U<<19) /* IP header alignment enable */ 106 #define RXC_UCC (1U<<18) /* run UDP checksum */ 107 #define RXC_TCC (1U<<17) /* run TDP checksum */ 108 #define RXC_ICC (1U<<16) /* run IP checksum */ 109 #define RXC_FCE (1U<<9) /* enable flowcontrol */ 110 #define RXC_RB (1U<<6) /* receive broadcast frame */ 111 #define RXC_RM (1U<<5) /* receive multicast frame */ 112 #define RXC_RU (1U<<4) /* receive unicast frame */ 113 #define RXC_RE (1U<<3) /* accept error frame */ 114 #define RXC_RA (1U<<2) /* receive all frame */ 115 #define RXC_MHTE (1U<<1) /* use multicast hash table */ 116 #define RXC_REN (1) /* enable DMA to run */ 117 118 #define INT_DMLCS (1U<<31) /* link status change */ 119 #define INT_DMTS (1U<<30) /* sending desc. has posted Tx done */ 120 #define INT_DMRS (1U<<29) /* frame was received */ 121 #define INT_DMRBUS (1U<<27) /* Rx descriptor pool is full */ 122 123 #define T0_OWN (1U<<31) /* desc is ready to Tx */ 124 125 #define R0_OWN (1U<<31) /* desc is empty */ 126 #define R0_FS (1U<<30) /* first segment of frame */ 127 #define R0_LS (1U<<29) /* last segment of frame */ 128 #define R0_IPE (1U<<28) /* IP checksum error */ 129 #define R0_TCPE (1U<<27) /* TCP checksum error */ 130 #define R0_UDPE (1U<<26) /* UDP checksum error */ 131 #define R0_ES (1U<<25) /* error summary */ 132 #define R0_MF (1U<<24) /* multicast frame */ 133 #define R0_SPN 0x00300000 /* 21:20 switch port 1/2 */ 134 #define R0_ALIGN 0x00300000 /* 21:20 (KSZ8692P) Rx align amount */ 135 #define R0_RE (1U<<19) /* MII reported error */ 136 #define R0_TL (1U<<18) /* frame too long, beyond 1518 */ 137 #define R0_RF (1U<<17) /* damaged runt frame */ 138 #define R0_CE (1U<<16) /* CRC error */ 139 #define R0_FT (1U<<15) /* frame type */ 140 #define R0_FL_MASK 0x7ff /* frame length 10:0 */ 141 142 #define T1_IC (1U<<31) /* post interrupt on complete */ 143 #define T1_FS (1U<<30) /* first segment of frame */ 144 #define T1_LS (1U<<29) /* last segment of frame */ 145 #define T1_IPCKG (1U<<28) /* generate IP checksum */ 146 #define T1_TCPCKG (1U<<27) /* generate TCP checksum */ 147 #define T1_UDPCKG (1U<<26) /* generate UDP checksum */ 148 #define T1_TER (1U<<25) /* end of ring */ 149 #define T1_SPN 0x00300000 /* 21:20 switch port 1/2 */ 150 #define T1_TBS_MASK 0x7ff /* segment size 10:0 */ 151 152 #define R1_RER (1U<<25) /* end of ring */ 153 #define R1_RBS_MASK 0x7fd /* segment size 10:0 */ 154 155 #define KSE_NTXSEGS 16 156 #define KSE_TXQUEUELEN 64 157 #define KSE_TXQUEUELEN_MASK (KSE_TXQUEUELEN - 1) 158 #define KSE_TXQUEUE_GC (KSE_TXQUEUELEN / 4) 159 #define KSE_NTXDESC 256 160 #define KSE_NTXDESC_MASK (KSE_NTXDESC - 1) 161 #define KSE_NEXTTX(x) (((x) + 1) & KSE_NTXDESC_MASK) 162 #define KSE_NEXTTXS(x) (((x) + 1) & KSE_TXQUEUELEN_MASK) 163 164 #define KSE_NRXDESC 64 165 #define KSE_NRXDESC_MASK (KSE_NRXDESC - 1) 166 #define KSE_NEXTRX(x) (((x) + 1) & KSE_NRXDESC_MASK) 167 168 struct tdes { 169 uint32_t t0, t1, t2, t3; 170 }; 171 172 struct rdes { 173 uint32_t r0, r1, r2, r3; 174 }; 175 176 struct kse_control_data { 177 struct tdes kcd_txdescs[KSE_NTXDESC]; 178 struct rdes kcd_rxdescs[KSE_NRXDESC]; 179 }; 180 #define KSE_CDOFF(x) offsetof(struct kse_control_data, x) 181 #define KSE_CDTXOFF(x) KSE_CDOFF(kcd_txdescs[(x)]) 182 #define KSE_CDRXOFF(x) KSE_CDOFF(kcd_rxdescs[(x)]) 183 184 struct kse_txsoft { 185 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 186 bus_dmamap_t txs_dmamap; /* our DMA map */ 187 int txs_firstdesc; /* first descriptor in packet */ 188 int txs_lastdesc; /* last descriptor in packet */ 189 int txs_ndesc; /* # of descriptors used */ 190 }; 191 192 struct kse_rxsoft { 193 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 194 bus_dmamap_t rxs_dmamap; /* our DMA map */ 195 }; 196 197 struct kse_softc { 198 struct device sc_dev; /* generic device information */ 199 bus_space_tag_t sc_st; /* bus space tag */ 200 bus_space_handle_t sc_sh; /* bus space handle */ 201 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 202 struct ethercom sc_ethercom; /* Ethernet common data */ 203 void *sc_ih; /* interrupt cookie */ 204 205 struct ifmedia sc_media; /* ifmedia information */ 206 int sc_media_status; /* PHY */ 207 int sc_media_active; /* PHY */ 208 callout_t sc_callout; /* tick callout */ 209 210 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 211 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 212 213 struct kse_control_data *sc_control_data; 214 #define sc_txdescs sc_control_data->kcd_txdescs 215 #define sc_rxdescs sc_control_data->kcd_rxdescs 216 217 struct kse_txsoft sc_txsoft[KSE_TXQUEUELEN]; 218 struct kse_rxsoft sc_rxsoft[KSE_NRXDESC]; 219 int sc_txfree; /* number of free Tx descriptors */ 220 int sc_txnext; /* next ready Tx descriptor */ 221 int sc_txsfree; /* number of free Tx jobs */ 222 int sc_txsnext; /* next ready Tx job */ 223 int sc_txsdirty; /* dirty Tx jobs */ 224 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 225 226 uint32_t sc_txc, sc_rxc; 227 uint32_t sc_t1csum; 228 int sc_mcsum; 229 uint32_t sc_chip; 230 }; 231 232 #define KSE_CDTXADDR(sc, x) ((sc)->sc_cddma + KSE_CDTXOFF((x))) 233 #define KSE_CDRXADDR(sc, x) ((sc)->sc_cddma + KSE_CDRXOFF((x))) 234 235 #define KSE_CDTXSYNC(sc, x, n, ops) \ 236 do { \ 237 int __x, __n; \ 238 \ 239 __x = (x); \ 240 __n = (n); \ 241 \ 242 /* If it will wrap around, sync to the end of the ring. */ \ 243 if ((__x + __n) > KSE_NTXDESC) { \ 244 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 245 KSE_CDTXOFF(__x), sizeof(struct tdes) * \ 246 (KSE_NTXDESC - __x), (ops)); \ 247 __n -= (KSE_NTXDESC - __x); \ 248 __x = 0; \ 249 } \ 250 \ 251 /* Now sync whatever is left. */ \ 252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 253 KSE_CDTXOFF(__x), sizeof(struct tdes) * __n, (ops)); \ 254 } while (/*CONSTCOND*/0) 255 256 #define KSE_CDRXSYNC(sc, x, ops) \ 257 do { \ 258 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 259 KSE_CDRXOFF((x)), sizeof(struct rdes), (ops)); \ 260 } while (/*CONSTCOND*/0) 261 262 #define KSE_INIT_RXDESC(sc, x) \ 263 do { \ 264 struct kse_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 265 struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 266 struct mbuf *__m = __rxs->rxs_mbuf; \ 267 \ 268 __m->m_data = __m->m_ext.ext_buf; \ 269 __rxd->r2 = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \ 270 __rxd->r1 = R1_RBS_MASK /* __m->m_ext.ext_size */; \ 271 __rxd->r0 = R0_OWN; \ 272 KSE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 273 } while (/*CONSTCOND*/0) 274 275 u_int kse_burstsize = 16; /* DMA burst length tuning knob */ 276 277 #ifdef KSEDIAGNOSTIC 278 u_int kse_monitor_rxintr; /* fragmented UDP csum HW bug hook */ 279 #endif 280 281 static int kse_match(struct device *, struct cfdata *, void *); 282 static void kse_attach(struct device *, struct device *, void *); 283 284 CFATTACH_DECL(kse, sizeof(struct kse_softc), 285 kse_match, kse_attach, NULL, NULL); 286 287 static int kse_ioctl(struct ifnet *, u_long, void *); 288 static void kse_start(struct ifnet *); 289 static void kse_watchdog(struct ifnet *); 290 static int kse_init(struct ifnet *); 291 static void kse_stop(struct ifnet *, int); 292 static void kse_reset(struct kse_softc *); 293 static void kse_set_filter(struct kse_softc *); 294 static int add_rxbuf(struct kse_softc *, int); 295 static void rxdrain(struct kse_softc *); 296 static int kse_intr(void *); 297 static void rxintr(struct kse_softc *); 298 static void txreap(struct kse_softc *); 299 static void lnkchg(struct kse_softc *); 300 static int ifmedia_upd(struct ifnet *); 301 static void ifmedia_sts(struct ifnet *, struct ifmediareq *); 302 static void phy_tick(void *); 303 304 static int 305 kse_match(struct device *parent, struct cfdata *match, void *aux) 306 { 307 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 308 309 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_MICREL && 310 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MICREL_KSZ8842 || 311 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MICREL_KSZ8841) && 312 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 313 return 1; 314 315 return 0; 316 } 317 318 static void 319 kse_attach(struct device *parent, struct device *self, void *aux) 320 { 321 struct kse_softc *sc = (struct kse_softc *)self; 322 struct pci_attach_args *pa = aux; 323 pci_chipset_tag_t pc = pa->pa_pc; 324 pci_intr_handle_t ih; 325 const char *intrstr; 326 struct ifnet *ifp; 327 uint8_t enaddr[ETHER_ADDR_LEN]; 328 bus_dma_segment_t seg; 329 int error, i, nseg; 330 pcireg_t pmode; 331 int pmreg; 332 333 if (pci_mapreg_map(pa, 0x10, 334 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 335 0, &sc->sc_st, &sc->sc_sh, NULL, NULL) != 0) { 336 printf(": unable to map device registers\n"); 337 return; 338 } 339 340 sc->sc_dmat = pa->pa_dmat; 341 342 /* Make sure bus mastering is enabled. */ 343 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 344 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 345 PCI_COMMAND_MASTER_ENABLE); 346 347 /* Get it out of power save mode, if needed. */ 348 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 349 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 350 PCI_PMCSR_STATE_MASK; 351 if (pmode == PCI_PMCSR_STATE_D3) { 352 /* 353 * The card has lost all configuration data in 354 * this state, so punt. 355 */ 356 printf("%s: unable to wake from power state D3\n", 357 sc->sc_dev.dv_xname); 358 return; 359 } 360 if (pmode != PCI_PMCSR_STATE_D0) { 361 printf("%s: waking up from power date D%d\n", 362 sc->sc_dev.dv_xname, pmode); 363 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 364 PCI_PMCSR_STATE_D0); 365 } 366 } 367 368 sc->sc_chip = PCI_PRODUCT(pa->pa_id); 369 printf(": Micrel KSZ%04x Ethernet (rev. 0x%02x)\n", 370 sc->sc_chip, PCI_REVISION(pa->pa_class)); 371 372 /* 373 * Read the Ethernet address from the EEPROM. 374 */ 375 i = CSR_READ_2(sc, MARL); 376 enaddr[5] = i; enaddr[4] = i >> 8; 377 i = CSR_READ_2(sc, MARM); 378 enaddr[3] = i; enaddr[2] = i >> 8; 379 i = CSR_READ_2(sc, MARH); 380 enaddr[1] = i; enaddr[0] = i >> 8; 381 printf("%s: Ethernet address: %s\n", 382 sc->sc_dev.dv_xname, ether_sprintf(enaddr)); 383 384 /* 385 * Enable chip function. 386 */ 387 CSR_WRITE_2(sc, CIDR, 1); 388 389 /* 390 * Map and establish our interrupt. 391 */ 392 if (pci_intr_map(pa, &ih)) { 393 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 394 return; 395 } 396 intrstr = pci_intr_string(pc, ih); 397 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, kse_intr, sc); 398 if (sc->sc_ih == NULL) { 399 printf("%s: unable to establish interrupt", 400 sc->sc_dev.dv_xname); 401 if (intrstr != NULL) 402 printf(" at %s", intrstr); 403 printf("\n"); 404 return; 405 } 406 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 407 408 /* 409 * Allocate the control data structures, and create and load the 410 * DMA map for it. 411 */ 412 error = bus_dmamem_alloc(sc->sc_dmat, 413 sizeof(struct kse_control_data), PAGE_SIZE, 0, &seg, 1, &nseg, 0); 414 if (error != 0) { 415 printf("%s: unable to allocate control data, error = %d\n", 416 sc->sc_dev.dv_xname, error); 417 goto fail_0; 418 } 419 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 420 sizeof(struct kse_control_data), (void **)&sc->sc_control_data, 421 BUS_DMA_COHERENT); 422 if (error != 0) { 423 printf("%s: unable to map control data, error = %d\n", 424 sc->sc_dev.dv_xname, error); 425 goto fail_1; 426 } 427 error = bus_dmamap_create(sc->sc_dmat, 428 sizeof(struct kse_control_data), 1, 429 sizeof(struct kse_control_data), 0, 0, &sc->sc_cddmamap); 430 if (error != 0) { 431 printf("%s: unable to create control data DMA map, " 432 "error = %d\n", sc->sc_dev.dv_xname, error); 433 goto fail_2; 434 } 435 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 436 sc->sc_control_data, sizeof(struct kse_control_data), NULL, 0); 437 if (error != 0) { 438 printf("%s: unable to load control data DMA map, error = %d\n", 439 sc->sc_dev.dv_xname, error); 440 goto fail_3; 441 } 442 for (i = 0; i < KSE_TXQUEUELEN; i++) { 443 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 444 KSE_NTXSEGS, MCLBYTES, 0, 0, 445 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 446 printf("%s: unable to create tx DMA map %d, " 447 "error = %d\n", sc->sc_dev.dv_xname, i, error); 448 goto fail_4; 449 } 450 } 451 for (i = 0; i < KSE_NRXDESC; i++) { 452 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 453 1, MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 454 printf("%s: unable to create rx DMA map %d, " 455 "error = %d\n", sc->sc_dev.dv_xname, i, error); 456 goto fail_5; 457 } 458 sc->sc_rxsoft[i].rxs_mbuf = NULL; 459 } 460 461 callout_init(&sc->sc_callout, 0); 462 463 ifmedia_init(&sc->sc_media, 0, ifmedia_upd, ifmedia_sts); 464 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T, 0, NULL); 465 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 466 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX, 0, NULL); 467 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 468 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL); 469 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 470 471 printf("%s: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto\n", 472 sc->sc_dev.dv_xname); 473 474 ifp = &sc->sc_ethercom.ec_if; 475 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 476 ifp->if_softc = sc; 477 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 478 ifp->if_ioctl = kse_ioctl; 479 ifp->if_start = kse_start; 480 ifp->if_watchdog = kse_watchdog; 481 ifp->if_init = kse_init; 482 ifp->if_stop = kse_stop; 483 IFQ_SET_READY(&ifp->if_snd); 484 485 /* 486 * KSZ8842 can handle 802.1Q VLAN-sized frames, 487 * can do IPv4, TCPv4, and UDPv4 checksums in hardware. 488 */ 489 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 490 ifp->if_capabilities |= 491 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 492 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 493 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 494 495 if_attach(ifp); 496 ether_ifattach(ifp, enaddr); 497 return; 498 499 fail_5: 500 for (i = 0; i < KSE_NRXDESC; i++) { 501 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 502 bus_dmamap_destroy(sc->sc_dmat, 503 sc->sc_rxsoft[i].rxs_dmamap); 504 } 505 fail_4: 506 for (i = 0; i < KSE_TXQUEUELEN; i++) { 507 if (sc->sc_txsoft[i].txs_dmamap != NULL) 508 bus_dmamap_destroy(sc->sc_dmat, 509 sc->sc_txsoft[i].txs_dmamap); 510 } 511 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 512 fail_3: 513 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 514 fail_2: 515 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 516 sizeof(struct kse_control_data)); 517 fail_1: 518 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 519 fail_0: 520 return; 521 } 522 523 static int 524 kse_ioctl(struct ifnet *ifp, u_long cmd, void *data) 525 { 526 struct kse_softc *sc = ifp->if_softc; 527 struct ifreq *ifr = (struct ifreq *)data; 528 int s, error; 529 530 s = splnet(); 531 532 switch (cmd) { 533 case SIOCSIFMEDIA: 534 case SIOCGIFMEDIA: 535 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 536 break; 537 538 default: 539 error = ether_ioctl(ifp, cmd, data); 540 if (cmd == ENETRESET) { 541 /* 542 * Multicast list has changed; set the hardware filter 543 * accordingly. 544 */ 545 if (ifp->if_flags & IFF_RUNNING) 546 kse_set_filter(sc); 547 error = 0; 548 } 549 break; 550 } 551 552 kse_start(ifp); 553 554 splx(s); 555 return error; 556 } 557 558 #define KSE_INTRS (INT_DMLCS|INT_DMTS|INT_DMRS|INT_DMRBUS) 559 560 static int 561 kse_init(struct ifnet *ifp) 562 { 563 struct kse_softc *sc = ifp->if_softc; 564 uint32_t paddr; 565 int i, error = 0; 566 567 /* cancel pending I/O */ 568 kse_stop(ifp, 0); 569 570 /* reset all registers but PCI configuration */ 571 kse_reset(sc); 572 573 /* craft Tx descriptor ring */ 574 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 575 for (i = 0, paddr = KSE_CDTXADDR(sc, 1); i < KSE_NTXDESC - 1; i++) { 576 sc->sc_txdescs[i].t3 = paddr; 577 paddr += sizeof(struct tdes); 578 } 579 sc->sc_txdescs[KSE_NTXDESC - 1].t3 = KSE_CDTXADDR(sc, 0); 580 KSE_CDTXSYNC(sc, 0, KSE_NTXDESC, 581 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 582 sc->sc_txfree = KSE_NTXDESC; 583 sc->sc_txnext = 0; 584 585 for (i = 0; i < KSE_TXQUEUELEN; i++) 586 sc->sc_txsoft[i].txs_mbuf = NULL; 587 sc->sc_txsfree = KSE_TXQUEUELEN; 588 sc->sc_txsnext = 0; 589 sc->sc_txsdirty = 0; 590 591 /* craft Rx descriptor ring */ 592 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 593 for (i = 0, paddr = KSE_CDRXADDR(sc, 1); i < KSE_NRXDESC - 1; i++) { 594 sc->sc_rxdescs[i].r3 = paddr; 595 paddr += sizeof(struct rdes); 596 } 597 sc->sc_rxdescs[KSE_NRXDESC - 1].r3 = KSE_CDRXADDR(sc, 0); 598 for (i = 0; i < KSE_NRXDESC; i++) { 599 if (sc->sc_rxsoft[i].rxs_mbuf == NULL) { 600 if ((error = add_rxbuf(sc, i)) != 0) { 601 printf("%s: unable to allocate or map rx " 602 "buffer %d, error = %d\n", 603 sc->sc_dev.dv_xname, i, error); 604 rxdrain(sc); 605 goto out; 606 } 607 } 608 else 609 KSE_INIT_RXDESC(sc, i); 610 } 611 sc->sc_rxptr = 0; 612 613 /* hand Tx/Rx rings to HW */ 614 CSR_WRITE_4(sc, TDLB, KSE_CDTXADDR(sc, 0)); 615 CSR_WRITE_4(sc, RDLB, KSE_CDRXADDR(sc, 0)); 616 617 sc->sc_txc = TXC_TEN | TXC_EP | TXC_AC | TXC_FCE; 618 sc->sc_rxc = RXC_REN | RXC_RU | RXC_FCE; 619 if (ifp->if_flags & IFF_PROMISC) 620 sc->sc_rxc |= RXC_RA; 621 if (ifp->if_flags & IFF_BROADCAST) 622 sc->sc_rxc |= RXC_RB; 623 sc->sc_t1csum = sc->sc_mcsum = 0; 624 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) { 625 sc->sc_rxc |= RXC_ICC; 626 sc->sc_mcsum |= M_CSUM_IPv4; 627 } 628 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) { 629 sc->sc_txc |= TXC_ICG; 630 sc->sc_t1csum |= T1_IPCKG; 631 } 632 if (ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) { 633 sc->sc_rxc |= RXC_TCC; 634 sc->sc_mcsum |= M_CSUM_TCPv4; 635 } 636 if (ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) { 637 sc->sc_txc |= TXC_TCG; 638 sc->sc_t1csum |= T1_TCPCKG; 639 } 640 if (ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) { 641 sc->sc_rxc |= RXC_UCC; 642 sc->sc_mcsum |= M_CSUM_UDPv4; 643 } 644 if (ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) { 645 sc->sc_txc |= TXC_UCG; 646 sc->sc_t1csum |= T1_UDPCKG; 647 } 648 sc->sc_txc |= (kse_burstsize << TXC_BS_SFT); 649 sc->sc_rxc |= (kse_burstsize << RXC_BS_SFT); 650 651 /* build multicast hash filter if necessary */ 652 kse_set_filter(sc); 653 654 /* set current media */ 655 (void)ifmedia_upd(ifp); 656 657 /* enable transmitter and receiver */ 658 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 659 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); 660 CSR_WRITE_4(sc, MDRSC, 1); 661 662 /* enable interrupts */ 663 CSR_WRITE_4(sc, INTST, ~0); 664 CSR_WRITE_4(sc, INTEN, KSE_INTRS); 665 666 ifp->if_flags |= IFF_RUNNING; 667 ifp->if_flags &= ~IFF_OACTIVE; 668 669 /* start one second timer */ 670 callout_reset(&sc->sc_callout, hz, phy_tick, sc); 671 672 out: 673 if (error) { 674 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 675 ifp->if_timer = 0; 676 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 677 } 678 return error; 679 } 680 681 static void 682 kse_stop(struct ifnet *ifp, int disable) 683 { 684 struct kse_softc *sc = ifp->if_softc; 685 struct kse_txsoft *txs; 686 int i; 687 688 callout_stop(&sc->sc_callout); 689 690 sc->sc_txc &= ~TXC_TEN; 691 sc->sc_rxc &= ~RXC_REN; 692 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 693 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); 694 695 for (i = 0; i < KSE_TXQUEUELEN; i++) { 696 txs = &sc->sc_txsoft[i]; 697 if (txs->txs_mbuf != NULL) { 698 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 699 m_freem(txs->txs_mbuf); 700 txs->txs_mbuf = NULL; 701 } 702 } 703 704 if (disable) 705 rxdrain(sc); 706 707 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 708 ifp->if_timer = 0; 709 } 710 711 static void 712 kse_reset(struct kse_softc *sc) 713 { 714 715 CSR_WRITE_2(sc, GRR, 1); 716 delay(1000); /* PDF does not mention the delay amount */ 717 CSR_WRITE_2(sc, GRR, 0); 718 719 CSR_WRITE_2(sc, CIDR, 1); 720 } 721 722 static void 723 kse_watchdog(struct ifnet *ifp) 724 { 725 struct kse_softc *sc = ifp->if_softc; 726 727 /* 728 * Since we're not interrupting every packet, sweep 729 * up before we report an error. 730 */ 731 txreap(sc); 732 733 if (sc->sc_txfree != KSE_NTXDESC) { 734 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 735 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 736 sc->sc_txnext); 737 ifp->if_oerrors++; 738 739 /* Reset the interface. */ 740 kse_init(ifp); 741 } 742 else if (ifp->if_flags & IFF_DEBUG) 743 printf("%s: recovered from device timeout\n", 744 sc->sc_dev.dv_xname); 745 746 /* Try to get more packets going. */ 747 kse_start(ifp); 748 } 749 750 static void 751 kse_start(struct ifnet *ifp) 752 { 753 struct kse_softc *sc = ifp->if_softc; 754 struct mbuf *m0; 755 struct kse_txsoft *txs; 756 bus_dmamap_t dmamap; 757 int error, nexttx, lasttx, ofree, seg; 758 uint32_t tdes0; 759 760 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 761 return; 762 763 /* 764 * Remember the previous number of free descriptors. 765 */ 766 ofree = sc->sc_txfree; 767 768 /* 769 * Loop through the send queue, setting up transmit descriptors 770 * until we drain the queue, or use up all available transmit 771 * descriptors. 772 */ 773 for (;;) { 774 IFQ_POLL(&ifp->if_snd, m0); 775 if (m0 == NULL) 776 break; 777 778 if (sc->sc_txsfree < KSE_TXQUEUE_GC) { 779 txreap(sc); 780 if (sc->sc_txsfree == 0) 781 break; 782 } 783 txs = &sc->sc_txsoft[sc->sc_txsnext]; 784 dmamap = txs->txs_dmamap; 785 786 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 787 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 788 if (error) { 789 if (error == EFBIG) { 790 printf("%s: Tx packet consumes too many " 791 "DMA segments, dropping...\n", 792 sc->sc_dev.dv_xname); 793 IFQ_DEQUEUE(&ifp->if_snd, m0); 794 m_freem(m0); 795 continue; 796 } 797 /* Short on resources, just stop for now. */ 798 break; 799 } 800 801 if (dmamap->dm_nsegs > sc->sc_txfree) { 802 /* 803 * Not enough free descriptors to transmit this 804 * packet. We haven't committed anything yet, 805 * so just unload the DMA map, put the packet 806 * back on the queue, and punt. Notify the upper 807 * layer that there are not more slots left. 808 */ 809 ifp->if_flags |= IFF_OACTIVE; 810 bus_dmamap_unload(sc->sc_dmat, dmamap); 811 break; 812 } 813 814 IFQ_DEQUEUE(&ifp->if_snd, m0); 815 816 /* 817 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 818 */ 819 820 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 821 BUS_DMASYNC_PREWRITE); 822 823 lasttx = -1; tdes0 = 0; 824 for (nexttx = sc->sc_txnext, seg = 0; 825 seg < dmamap->dm_nsegs; 826 seg++, nexttx = KSE_NEXTTX(nexttx)) { 827 struct tdes *tdes = &sc->sc_txdescs[nexttx]; 828 /* 829 * If this is the first descriptor we're 830 * enqueueing, don't set the OWN bit just 831 * yet. That could cause a race condition. 832 * We'll do it below. 833 */ 834 tdes->t2 = dmamap->dm_segs[seg].ds_addr; 835 tdes->t1 = sc->sc_t1csum 836 | (dmamap->dm_segs[seg].ds_len & T1_TBS_MASK); 837 tdes->t0 = tdes0; 838 tdes0 |= T0_OWN; 839 lasttx = nexttx; 840 } 841 #if 0 842 /* 843 * T1_IC bit could schedule Tx frame done interrupt here, 844 * but this driver takes a "shoot away" Tx strategy. 845 */ 846 #else 847 { 848 /* 849 * Outgoing NFS mbuf must be unloaded when Tx completed. 850 * Without T1_IC NFS mbuf is left unack'ed for excessive 851 * time and NFS stops to proceed until kse_watchdog() 852 * calls txreap() to reclaim the unack'ed mbuf. 853 * It's painful to traverse every mbuf chain to determine 854 * whether someone is waiting for Tx completion. 855 */ 856 struct mbuf *m = m0; 857 do { 858 if ((m->m_flags & M_EXT) && m->m_ext.ext_free) { 859 sc->sc_txdescs[lasttx].t1 |= T1_IC; 860 break; 861 } 862 } while ((m = m->m_next) != NULL); 863 } 864 #endif 865 866 /* write last T0_OWN bit of the 1st segment */ 867 sc->sc_txdescs[lasttx].t1 |= T1_LS; 868 sc->sc_txdescs[sc->sc_txnext].t1 |= T1_FS; 869 sc->sc_txdescs[sc->sc_txnext].t0 = T0_OWN; 870 KSE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 871 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 872 873 /* tell DMA start transmit */ 874 CSR_WRITE_4(sc, MDTSC, 1); 875 876 txs->txs_mbuf = m0; 877 txs->txs_firstdesc = sc->sc_txnext; 878 txs->txs_lastdesc = lasttx; 879 txs->txs_ndesc = dmamap->dm_nsegs; 880 881 sc->sc_txfree -= txs->txs_ndesc; 882 sc->sc_txnext = nexttx; 883 sc->sc_txsfree--; 884 sc->sc_txsnext = KSE_NEXTTXS(sc->sc_txsnext); 885 #if NBPFILTER > 0 886 /* 887 * Pass the packet to any BPF listeners. 888 */ 889 if (ifp->if_bpf) 890 bpf_mtap(ifp->if_bpf, m0); 891 #endif /* NBPFILTER > 0 */ 892 } 893 894 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 895 /* No more slots left; notify upper layer. */ 896 ifp->if_flags |= IFF_OACTIVE; 897 } 898 if (sc->sc_txfree != ofree) { 899 /* Set a watchdog timer in case the chip flakes out. */ 900 ifp->if_timer = 5; 901 } 902 } 903 904 static void 905 kse_set_filter(struct kse_softc *sc) 906 { 907 struct ether_multistep step; 908 struct ether_multi *enm; 909 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 910 uint32_t h, hashes[2]; 911 912 sc->sc_rxc &= ~(RXC_MHTE | RXC_RM); 913 ifp->if_flags &= ~IFF_ALLMULTI; 914 if (ifp->if_flags & IFF_PROMISC) 915 return; 916 917 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 918 if (enm == NULL) 919 return; 920 hashes[0] = hashes[1] = 0; 921 do { 922 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 923 /* 924 * We must listen to a range of multicast addresses. 925 * For now, just accept all multicasts, rather than 926 * trying to set only those filter bits needed to match 927 * the range. (At this time, the only use of address 928 * ranges is for IP multicast routing, for which the 929 * range is big enough to require all bits set.) 930 */ 931 goto allmulti; 932 } 933 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 934 hashes[h >> 5] |= 1 << (h & 0x1f); 935 ETHER_NEXT_MULTI(step, enm); 936 } while (enm != NULL); 937 sc->sc_rxc |= RXC_MHTE; 938 CSR_WRITE_4(sc, MTR0, hashes[0]); 939 CSR_WRITE_4(sc, MTR1, hashes[1]); 940 return; 941 allmulti: 942 sc->sc_rxc |= RXC_RM; 943 ifp->if_flags |= IFF_ALLMULTI; 944 } 945 946 static int 947 add_rxbuf(struct kse_softc *sc, int idx) 948 { 949 struct kse_rxsoft *rxs = &sc->sc_rxsoft[idx]; 950 struct mbuf *m; 951 int error; 952 953 MGETHDR(m, M_DONTWAIT, MT_DATA); 954 if (m == NULL) 955 return ENOBUFS; 956 957 MCLGET(m, M_DONTWAIT); 958 if ((m->m_flags & M_EXT) == 0) { 959 m_freem(m); 960 return ENOBUFS; 961 } 962 963 if (rxs->rxs_mbuf != NULL) 964 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 965 966 rxs->rxs_mbuf = m; 967 968 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 969 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 970 if (error) { 971 printf("%s: can't load rx DMA map %d, error = %d\n", 972 sc->sc_dev.dv_xname, idx, error); 973 panic("kse_add_rxbuf"); 974 } 975 976 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 977 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 978 979 KSE_INIT_RXDESC(sc, idx); 980 981 return 0; 982 } 983 984 static void 985 rxdrain(struct kse_softc *sc) 986 { 987 struct kse_rxsoft *rxs; 988 int i; 989 990 for (i = 0; i < KSE_NRXDESC; i++) { 991 rxs = &sc->sc_rxsoft[i]; 992 if (rxs->rxs_mbuf != NULL) { 993 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 994 m_freem(rxs->rxs_mbuf); 995 rxs->rxs_mbuf = NULL; 996 } 997 } 998 } 999 1000 static int 1001 kse_intr(void *arg) 1002 { 1003 struct kse_softc *sc = arg; 1004 uint32_t isr; 1005 1006 if ((isr = CSR_READ_4(sc, INTST)) == 0) 1007 return 0; 1008 1009 if (isr & INT_DMRS) 1010 rxintr(sc); 1011 if (isr & INT_DMTS) 1012 txreap(sc); 1013 if (isr & INT_DMLCS) 1014 lnkchg(sc); 1015 if (isr & INT_DMRBUS) 1016 printf("%s: Rx descriptor full\n", sc->sc_dev.dv_xname); 1017 1018 CSR_WRITE_4(sc, INTST, isr); 1019 return 1; 1020 } 1021 1022 static void 1023 rxintr(struct kse_softc *sc) 1024 { 1025 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1026 struct kse_rxsoft *rxs; 1027 struct mbuf *m; 1028 uint32_t rxstat; 1029 int i, len; 1030 1031 for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = KSE_NEXTRX(i)) { 1032 rxs = &sc->sc_rxsoft[i]; 1033 1034 KSE_CDRXSYNC(sc, i, 1035 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1036 1037 rxstat = sc->sc_rxdescs[i].r0; 1038 1039 if (rxstat & R0_OWN) /* desc is left empty */ 1040 break; 1041 1042 /* R0_FS|R0_LS must have been marked for this desc */ 1043 1044 if (rxstat & R0_ES) { 1045 ifp->if_ierrors++; 1046 #define PRINTERR(bit, str) \ 1047 if (rxstat & (bit)) \ 1048 printf("%s: receive error: %s\n", \ 1049 sc->sc_dev.dv_xname, str) 1050 PRINTERR(R0_TL, "frame too long"); 1051 PRINTERR(R0_RF, "runt frame"); 1052 PRINTERR(R0_CE, "bad FCS"); 1053 #undef PRINTERR 1054 KSE_INIT_RXDESC(sc, i); 1055 continue; 1056 } 1057 1058 /* HW errata; frame might be too small or too large */ 1059 1060 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1061 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1062 1063 len = rxstat & R0_FL_MASK; 1064 len -= ETHER_CRC_LEN; /* trim CRC off */ 1065 m = rxs->rxs_mbuf; 1066 1067 if (add_rxbuf(sc, i) != 0) { 1068 ifp->if_ierrors++; 1069 KSE_INIT_RXDESC(sc, i); 1070 bus_dmamap_sync(sc->sc_dmat, 1071 rxs->rxs_dmamap, 0, 1072 rxs->rxs_dmamap->dm_mapsize, 1073 BUS_DMASYNC_PREREAD); 1074 continue; 1075 } 1076 1077 ifp->if_ipackets++; 1078 m->m_pkthdr.rcvif = ifp; 1079 m->m_pkthdr.len = m->m_len = len; 1080 1081 if (sc->sc_mcsum) { 1082 m->m_pkthdr.csum_flags |= sc->sc_mcsum; 1083 if (rxstat & R0_IPE) 1084 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1085 if (rxstat & (R0_TCPE | R0_UDPE)) 1086 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1087 } 1088 #if NBPFILTER > 0 1089 if (ifp->if_bpf) 1090 bpf_mtap(ifp->if_bpf, m); 1091 #endif /* NBPFILTER > 0 */ 1092 (*ifp->if_input)(ifp, m); 1093 #ifdef KSEDIAGNOSTIC 1094 if (kse_monitor_rxintr > 0) { 1095 printf("m stat %x data %p len %d\n", 1096 rxstat, m->m_data, m->m_len); 1097 } 1098 #endif 1099 } 1100 sc->sc_rxptr = i; 1101 } 1102 1103 static void 1104 txreap(struct kse_softc *sc) 1105 { 1106 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1107 struct kse_txsoft *txs; 1108 uint32_t txstat; 1109 int i; 1110 1111 ifp->if_flags &= ~IFF_OACTIVE; 1112 1113 for (i = sc->sc_txsdirty; sc->sc_txsfree != KSE_TXQUEUELEN; 1114 i = KSE_NEXTTXS(i), sc->sc_txsfree++) { 1115 txs = &sc->sc_txsoft[i]; 1116 1117 KSE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1118 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1119 1120 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; 1121 1122 if (txstat & T0_OWN) /* desc is still in use */ 1123 break; 1124 1125 /* there is no way to tell transmission status per frame */ 1126 1127 ifp->if_opackets++; 1128 1129 sc->sc_txfree += txs->txs_ndesc; 1130 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1131 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1132 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1133 m_freem(txs->txs_mbuf); 1134 txs->txs_mbuf = NULL; 1135 } 1136 sc->sc_txsdirty = i; 1137 if (sc->sc_txsfree == KSE_TXQUEUELEN) 1138 ifp->if_timer = 0; 1139 } 1140 1141 static void 1142 lnkchg(struct kse_softc *sc) 1143 { 1144 struct ifmediareq ifmr; 1145 1146 #if 0 /* rambling link status */ 1147 printf("%s: link %s\n", sc->sc_dev.dv_xname, 1148 (CSR_READ_2(sc, P1SR) & (1U << 5)) ? "up" : "down"); 1149 #endif 1150 ifmedia_sts(&sc->sc_ethercom.ec_if, &ifmr); 1151 } 1152 1153 static int 1154 ifmedia_upd(struct ifnet *ifp) 1155 { 1156 struct kse_softc *sc = ifp->if_softc; 1157 struct ifmedia *ifm = &sc->sc_media; 1158 uint16_t ctl; 1159 1160 ctl = 0; 1161 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1162 ctl |= (1U << 13); /* restart AN */ 1163 ctl |= (1U << 7); /* enable AN */ 1164 ctl |= (1U << 4); /* advertise flow control pause */ 1165 ctl |= (1U << 3) | (1U << 2) | (1U << 1) | (1U << 0); 1166 } 1167 else { 1168 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 1169 ctl |= (1U << 6); 1170 if (ifm->ifm_media & IFM_FDX) 1171 ctl |= (1U << 5); 1172 } 1173 CSR_WRITE_2(sc, P1CR4, ctl); 1174 1175 sc->sc_media_active = IFM_NONE; 1176 sc->sc_media_status = IFM_AVALID; 1177 1178 return 0; 1179 } 1180 1181 static void 1182 ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1183 { 1184 struct kse_softc *sc = ifp->if_softc; 1185 struct ifmedia *ifm = &sc->sc_media; 1186 uint16_t ctl, sts, result; 1187 1188 ifmr->ifm_status = IFM_AVALID; 1189 ifmr->ifm_active = IFM_ETHER; 1190 1191 ctl = CSR_READ_2(sc, P1CR4); 1192 sts = CSR_READ_2(sc, P1SR); 1193 if ((sts & (1U << 5)) == 0) { 1194 ifmr->ifm_active |= IFM_NONE; 1195 goto out; /* link is down */ 1196 } 1197 ifmr->ifm_status |= IFM_ACTIVE; 1198 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1199 if ((sts & (1U << 6)) == 0) { 1200 ifmr->ifm_active |= IFM_NONE; 1201 goto out; /* negotiation in progress */ 1202 } 1203 result = ctl & sts & 017; 1204 if (result & (1U << 3)) 1205 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1206 else if (result & (1U << 2)) 1207 ifmr->ifm_active |= IFM_100_TX; 1208 else if (result & (1U << 1)) 1209 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1210 else if (result & (1U << 0)) 1211 ifmr->ifm_active |= IFM_10_T; 1212 else 1213 ifmr->ifm_active |= IFM_NONE; 1214 if (ctl & (1U << 4)) 1215 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 1216 if (sts & (1U << 4)) 1217 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 1218 } 1219 else { 1220 ifmr->ifm_active |= (sts & (1U << 10)) ? IFM_100_TX : IFM_10_T; 1221 if (sts & (1U << 9)) 1222 ifmr->ifm_active |= IFM_FDX; 1223 if (sts & (1U << 12)) 1224 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 1225 if (sts & (1U << 11)) 1226 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 1227 } 1228 1229 out: 1230 sc->sc_media_status = ifmr->ifm_status; 1231 sc->sc_media_active = ifmr->ifm_active; 1232 } 1233 1234 static void 1235 phy_tick(void *arg) 1236 { 1237 struct kse_softc *sc = arg; 1238 struct ifmediareq ifmr; 1239 int s; 1240 1241 s = splnet(); 1242 ifmedia_sts(&sc->sc_ethercom.ec_if, &ifmr); 1243 splx(s); 1244 1245 callout_reset(&sc->sc_callout, hz, phy_tick, sc); 1246 } 1247
Indexes created Tue Sep 30 07:10:03 GMT 2025