if_lii.c revision 1.2.2.2
1 1.2.2.2 mjf /* $NetBSD: if_lii.c,v 1.2.2.2 2008/04/03 12:42:50 mjf Exp $ */ 2 1.2.2.2 mjf 3 1.2.2.2 mjf /* 4 1.2.2.2 mjf * Copyright (c) 2008 The NetBSD Foundation. 5 1.2.2.2 mjf * All rights reserved. 6 1.2.2.2 mjf * 7 1.2.2.2 mjf * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 mjf * modification, are permitted provided that the following conditions 9 1.2.2.2 mjf * are met: 10 1.2.2.2 mjf * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 mjf * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 mjf * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 mjf * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 mjf * documentation and/or other materials provided with the distribution. 15 1.2.2.2 mjf * 3. Neither the name of The NetBSD Foundation nor the names of its 16 1.2.2.2 mjf * contributors may be used to endorse or promote products derived 17 1.2.2.2 mjf * from this software without specific prior written permission. 18 1.2.2.2 mjf * 19 1.2.2.2 mjf * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 mjf * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 mjf * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 mjf * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 mjf * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 mjf * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 mjf * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 mjf * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 mjf * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 mjf * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 mjf * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 mjf */ 31 1.2.2.2 mjf 32 1.2.2.2 mjf /* 33 1.2.2.2 mjf * Driver for Attansic/Atheros's L2 Fast Ethernet controller 34 1.2.2.2 mjf */ 35 1.2.2.2 mjf 36 1.2.2.2 mjf #include <sys/cdefs.h> 37 1.2.2.2 mjf __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.2.2.2 2008/04/03 12:42:50 mjf Exp $"); 38 1.2.2.2 mjf 39 1.2.2.2 mjf #include "bpfilter.h" 40 1.2.2.2 mjf 41 1.2.2.2 mjf #include <sys/param.h> 42 1.2.2.2 mjf #include <sys/systm.h> 43 1.2.2.2 mjf #include <sys/types.h> 44 1.2.2.2 mjf #include <sys/device.h> 45 1.2.2.2 mjf #include <sys/endian.h> 46 1.2.2.2 mjf #include <sys/kernel.h> 47 1.2.2.2 mjf #include <sys/sockio.h> 48 1.2.2.2 mjf 49 1.2.2.2 mjf #include <net/if.h> 50 1.2.2.2 mjf #include <net/if_media.h> 51 1.2.2.2 mjf #include <net/if_ether.h> 52 1.2.2.2 mjf 53 1.2.2.2 mjf #if NBPFILTER > 0 54 1.2.2.2 mjf #include <net/bpf.h> 55 1.2.2.2 mjf #endif 56 1.2.2.2 mjf 57 1.2.2.2 mjf #include <dev/mii/mii.h> 58 1.2.2.2 mjf #include <dev/mii/miivar.h> 59 1.2.2.2 mjf 60 1.2.2.2 mjf #include <dev/pci/pcireg.h> 61 1.2.2.2 mjf #include <dev/pci/pcivar.h> 62 1.2.2.2 mjf #include <dev/pci/pcidevs.h> 63 1.2.2.2 mjf 64 1.2.2.2 mjf #include <dev/pci/if_liireg.h> 65 1.2.2.2 mjf 66 1.2.2.2 mjf /* #define LII_DEBUG */ 67 1.2.2.2 mjf #ifdef LII_DEBUG 68 1.2.2.2 mjf #define DPRINTF(x) printf x 69 1.2.2.2 mjf #else 70 1.2.2.2 mjf #define DPRINTF(x) 71 1.2.2.2 mjf #endif 72 1.2.2.2 mjf 73 1.2.2.2 mjf struct lii_softc { 74 1.2.2.2 mjf device_t sc_dev; 75 1.2.2.2 mjf pci_chipset_tag_t sc_pc; 76 1.2.2.2 mjf pcitag_t sc_tag; 77 1.2.2.2 mjf 78 1.2.2.2 mjf bus_space_tag_t sc_mmiot; 79 1.2.2.2 mjf bus_space_handle_t sc_mmioh; 80 1.2.2.2 mjf 81 1.2.2.2 mjf /* 82 1.2.2.2 mjf * We allocate a big chunk of DMA-safe memory for all data exchanges. 83 1.2.2.2 mjf * It is unfortunate that this chip doesn't seem to do scatter-gather. 84 1.2.2.2 mjf */ 85 1.2.2.2 mjf bus_dma_tag_t sc_dmat; 86 1.2.2.2 mjf bus_dmamap_t sc_ringmap; 87 1.2.2.2 mjf bus_dma_segment_t sc_ringseg; 88 1.2.2.2 mjf 89 1.2.2.2 mjf uint8_t *sc_ring; /* the whole area */ 90 1.2.2.2 mjf size_t sc_ringsize; 91 1.2.2.2 mjf 92 1.2.2.2 mjf struct rx_pkt *sc_rxp; /* the part used for RX */ 93 1.2.2.2 mjf struct tx_pkt_status *sc_txs; /* the parts used for TX */ 94 1.2.2.2 mjf bus_addr_t sc_txsp; 95 1.2.2.2 mjf char *sc_txdbase; 96 1.2.2.2 mjf bus_addr_t sc_txdp; 97 1.2.2.2 mjf 98 1.2.2.2 mjf unsigned int sc_rxcur; 99 1.2.2.2 mjf /* the active area is [ack; cur[ */ 100 1.2.2.2 mjf int sc_txs_cur; 101 1.2.2.2 mjf int sc_txs_ack; 102 1.2.2.2 mjf int sc_txd_cur; 103 1.2.2.2 mjf int sc_txd_ack; 104 1.2.2.2 mjf bool sc_free_tx_slots; 105 1.2.2.2 mjf 106 1.2.2.2 mjf void *sc_ih; 107 1.2.2.2 mjf 108 1.2.2.2 mjf struct ethercom sc_ec; 109 1.2.2.2 mjf struct mii_data sc_mii; 110 1.2.2.2 mjf callout_t sc_tick_ch; 111 1.2.2.2 mjf uint8_t sc_eaddr[ETHER_ADDR_LEN]; 112 1.2.2.2 mjf 113 1.2.2.2 mjf int (*sc_memread)(struct lii_softc *, uint32_t, 114 1.2.2.2 mjf uint32_t *); 115 1.2.2.2 mjf }; 116 1.2.2.2 mjf 117 1.2.2.2 mjf static int lii_match(device_t, cfdata_t, void *); 118 1.2.2.2 mjf static void lii_attach(device_t, device_t, void *); 119 1.2.2.2 mjf 120 1.2.2.2 mjf static int lii_reset(struct lii_softc *); 121 1.2.2.2 mjf static bool lii_eeprom_present(struct lii_softc *); 122 1.2.2.2 mjf static int lii_read_macaddr(struct lii_softc *, uint8_t *); 123 1.2.2.2 mjf static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 124 1.2.2.2 mjf static void lii_spi_configure(struct lii_softc *); 125 1.2.2.2 mjf static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 126 1.2.2.2 mjf static void lii_setmulti(struct lii_softc *); 127 1.2.2.2 mjf static void lii_tick(void *); 128 1.2.2.2 mjf 129 1.2.2.2 mjf static int lii_alloc_rings(struct lii_softc *); 130 1.2.2.2 mjf static int lii_free_tx_space(struct lii_softc *); 131 1.2.2.2 mjf 132 1.2.2.2 mjf static int lii_mii_readreg(device_t, int, int); 133 1.2.2.2 mjf static void lii_mii_writereg(device_t, int, int, int); 134 1.2.2.2 mjf static void lii_mii_statchg(device_t); 135 1.2.2.2 mjf 136 1.2.2.2 mjf static int lii_media_change(struct ifnet *); 137 1.2.2.2 mjf static void lii_media_status(struct ifnet *, struct ifmediareq *); 138 1.2.2.2 mjf 139 1.2.2.2 mjf static int lii_init(struct ifnet *); 140 1.2.2.2 mjf static void lii_start(struct ifnet *); 141 1.2.2.2 mjf static void lii_stop(struct ifnet *, int); 142 1.2.2.2 mjf static void lii_watchdog(struct ifnet *); 143 1.2.2.2 mjf static int lii_ioctl(struct ifnet *, u_long, void *); 144 1.2.2.2 mjf 145 1.2.2.2 mjf static int lii_intr(void *); 146 1.2.2.2 mjf static void lii_rxintr(struct lii_softc *); 147 1.2.2.2 mjf static void lii_txintr(struct lii_softc *); 148 1.2.2.2 mjf 149 1.2.2.2 mjf CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), 150 1.2.2.2 mjf lii_match, lii_attach, NULL, NULL); 151 1.2.2.2 mjf 152 1.2.2.2 mjf /* #define LII_DEBUG_REGS */ 153 1.2.2.2 mjf #ifndef LII_DEBUG_REGS 154 1.2.2.2 mjf #define AT_READ_4(sc,reg) \ 155 1.2.2.2 mjf bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 156 1.2.2.2 mjf #define AT_READ_2(sc,reg) \ 157 1.2.2.2 mjf bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 158 1.2.2.2 mjf #define AT_READ_1(sc,reg) \ 159 1.2.2.2 mjf bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 160 1.2.2.2 mjf #define AT_WRITE_4(sc,reg,val) \ 161 1.2.2.2 mjf bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 162 1.2.2.2 mjf #define AT_WRITE_2(sc,reg,val) \ 163 1.2.2.2 mjf bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 164 1.2.2.2 mjf #define AT_WRITE_1(sc,reg,val) \ 165 1.2.2.2 mjf bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 166 1.2.2.2 mjf #else 167 1.2.2.2 mjf static inline uint32_t 168 1.2.2.2 mjf AT_READ_4(struct lii_softc *sc, bus_size_t reg) 169 1.2.2.2 mjf { 170 1.2.2.2 mjf uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); 171 1.2.2.2 mjf printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r); 172 1.2.2.2 mjf return r; 173 1.2.2.2 mjf } 174 1.2.2.2 mjf 175 1.2.2.2 mjf static inline uint16_t 176 1.2.2.2 mjf AT_READ_2(struct lii_softc *sc, bus_size_t reg) 177 1.2.2.2 mjf { 178 1.2.2.2 mjf uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); 179 1.2.2.2 mjf printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r); 180 1.2.2.2 mjf return r; 181 1.2.2.2 mjf } 182 1.2.2.2 mjf 183 1.2.2.2 mjf static inline uint8_t 184 1.2.2.2 mjf AT_READ_1(struct lii_softc *sc, bus_size_t reg) 185 1.2.2.2 mjf { 186 1.2.2.2 mjf uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); 187 1.2.2.2 mjf printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r); 188 1.2.2.2 mjf return r; 189 1.2.2.2 mjf } 190 1.2.2.2 mjf 191 1.2.2.2 mjf static inline void 192 1.2.2.2 mjf AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) 193 1.2.2.2 mjf { 194 1.2.2.2 mjf printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val); 195 1.2.2.2 mjf bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); 196 1.2.2.2 mjf } 197 1.2.2.2 mjf 198 1.2.2.2 mjf static inline void 199 1.2.2.2 mjf AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) 200 1.2.2.2 mjf { 201 1.2.2.2 mjf printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val); 202 1.2.2.2 mjf bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); 203 1.2.2.2 mjf } 204 1.2.2.2 mjf 205 1.2.2.2 mjf static inline void 206 1.2.2.2 mjf AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) 207 1.2.2.2 mjf { 208 1.2.2.2 mjf printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val); 209 1.2.2.2 mjf bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); 210 1.2.2.2 mjf } 211 1.2.2.2 mjf #endif 212 1.2.2.2 mjf 213 1.2.2.2 mjf /* 214 1.2.2.2 mjf * Those are the default Linux parameters. 215 1.2.2.2 mjf */ 216 1.2.2.2 mjf 217 1.2.2.2 mjf #define AT_TXD_NUM 64 218 1.2.2.2 mjf #define AT_TXD_BUFFER_SIZE 8192 219 1.2.2.2 mjf #define AT_RXD_NUM 64 220 1.2.2.2 mjf 221 1.2.2.2 mjf /* 222 1.2.2.2 mjf * Assuming (you know what that word makes of you) the chunk of memory 223 1.2.2.2 mjf * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the 224 1.2.2.2 mjf * first 120 bytes of it, so that the space for the packets, and not the 225 1.2.2.2 mjf * whole descriptors themselves, are on a 128-byte boundary. 226 1.2.2.2 mjf */ 227 1.2.2.2 mjf 228 1.2.2.2 mjf #define AT_RXD_PADDING 120 229 1.2.2.2 mjf 230 1.2.2.2 mjf static int 231 1.2.2.2 mjf lii_match(device_t parent, cfdata_t cfmatch, void *aux) 232 1.2.2.2 mjf { 233 1.2.2.2 mjf struct pci_attach_args *pa = aux; 234 1.2.2.2 mjf 235 1.2.2.2 mjf return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 236 1.2.2.2 mjf PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); 237 1.2.2.2 mjf } 238 1.2.2.2 mjf 239 1.2.2.2 mjf static void 240 1.2.2.2 mjf lii_attach(device_t parent, device_t self, void *aux) 241 1.2.2.2 mjf { 242 1.2.2.2 mjf struct lii_softc *sc = device_private(self); 243 1.2.2.2 mjf struct pci_attach_args *pa = aux; 244 1.2.2.2 mjf uint8_t eaddr[ETHER_ADDR_LEN]; 245 1.2.2.2 mjf struct ifnet *ifp = &sc->sc_ec.ec_if; 246 1.2.2.2 mjf pci_intr_handle_t ih; 247 1.2.2.2 mjf const char *intrstr; 248 1.2.2.2 mjf pcireg_t cmd; 249 1.2.2.2 mjf 250 1.2.2.2 mjf aprint_naive("\n"); 251 1.2.2.2 mjf aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n"); 252 1.2.2.2 mjf 253 1.2.2.2 mjf sc->sc_dev = self; 254 1.2.2.2 mjf sc->sc_pc = pa->pa_pc; 255 1.2.2.2 mjf sc->sc_tag = pa->pa_tag; 256 1.2.2.2 mjf sc->sc_dmat = pa->pa_dmat; 257 1.2.2.2 mjf 258 1.2.2.2 mjf cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 259 1.2.2.2 mjf cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 260 1.2.2.2 mjf cmd &= ~PCI_COMMAND_IO_ENABLE; 261 1.2.2.2 mjf pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); 262 1.2.2.2 mjf 263 1.2.2.2 mjf switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { 264 1.2.2.2 mjf case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 265 1.2.2.2 mjf case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 266 1.2.2.2 mjf case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 267 1.2.2.2 mjf break; 268 1.2.2.2 mjf default: 269 1.2.2.2 mjf aprint_error_dev(self, "invalid base address register\n"); 270 1.2.2.2 mjf break; 271 1.2.2.2 mjf } 272 1.2.2.2 mjf if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, 273 1.2.2.2 mjf &sc->sc_mmiot, &sc->sc_mmioh, NULL, NULL) != 0) { 274 1.2.2.2 mjf aprint_error_dev(self, "failed to map registers\n"); 275 1.2.2.2 mjf return; 276 1.2.2.2 mjf } 277 1.2.2.2 mjf 278 1.2.2.2 mjf if (lii_reset(sc)) 279 1.2.2.2 mjf return; 280 1.2.2.2 mjf 281 1.2.2.2 mjf lii_spi_configure(sc); 282 1.2.2.2 mjf 283 1.2.2.2 mjf if (lii_eeprom_present(sc)) 284 1.2.2.2 mjf sc->sc_memread = lii_eeprom_read; 285 1.2.2.2 mjf else 286 1.2.2.2 mjf sc->sc_memread = lii_spi_read; 287 1.2.2.2 mjf 288 1.2.2.2 mjf if (lii_read_macaddr(sc, eaddr)) 289 1.2.2.2 mjf return; 290 1.2.2.2 mjf memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); 291 1.2.2.2 mjf 292 1.2.2.2 mjf aprint_normal_dev(self, "Ethernet address %s\n", 293 1.2.2.2 mjf ether_sprintf(eaddr)); 294 1.2.2.2 mjf 295 1.2.2.2 mjf if (pci_intr_map(pa, &ih) != 0) { 296 1.2.2.2 mjf aprint_error_dev(self, "failed to map interrupt\n"); 297 1.2.2.2 mjf return; 298 1.2.2.2 mjf } 299 1.2.2.2 mjf intrstr = pci_intr_string(sc->sc_pc, ih); 300 1.2.2.2 mjf sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); 301 1.2.2.2 mjf if (sc->sc_ih == NULL) { 302 1.2.2.2 mjf aprint_error_dev(self, "failed to establish interrupt"); 303 1.2.2.2 mjf if (intrstr != NULL) 304 1.2.2.2 mjf aprint_error(" at %s", intrstr); 305 1.2.2.2 mjf aprint_error("\n"); 306 1.2.2.2 mjf return; 307 1.2.2.2 mjf } 308 1.2.2.2 mjf aprint_normal_dev(self, "interrupting at %s\n", intrstr); 309 1.2.2.2 mjf 310 1.2.2.2 mjf if (lii_alloc_rings(sc)) { 311 1.2.2.2 mjf pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 312 1.2.2.2 mjf return; 313 1.2.2.2 mjf } 314 1.2.2.2 mjf 315 1.2.2.2 mjf callout_init(&sc->sc_tick_ch, 0); 316 1.2.2.2 mjf callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); 317 1.2.2.2 mjf 318 1.2.2.2 mjf sc->sc_mii.mii_ifp = ifp; 319 1.2.2.2 mjf sc->sc_mii.mii_readreg = lii_mii_readreg; 320 1.2.2.2 mjf sc->sc_mii.mii_writereg = lii_mii_writereg; 321 1.2.2.2 mjf sc->sc_mii.mii_statchg = lii_mii_statchg; 322 1.2.2.2 mjf ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 323 1.2.2.2 mjf lii_media_status); 324 1.2.2.2 mjf mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 325 1.2.2.2 mjf MII_OFFSET_ANY, 0); 326 1.2.2.2 mjf ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 327 1.2.2.2 mjf 328 1.2.2.2 mjf strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 329 1.2.2.2 mjf ifp->if_softc = sc; 330 1.2.2.2 mjf ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 1.2.2.2 mjf ifp->if_ioctl = lii_ioctl; 332 1.2.2.2 mjf ifp->if_start = lii_start; 333 1.2.2.2 mjf ifp->if_watchdog = lii_watchdog; 334 1.2.2.2 mjf ifp->if_init = lii_init; 335 1.2.2.2 mjf ifp->if_stop = lii_stop; 336 1.2.2.2 mjf IFQ_SET_READY(&ifp->if_snd); 337 1.2.2.2 mjf 338 1.2.2.2 mjf /* 339 1.2.2.2 mjf * While the device does support HW VLAN tagging, there is no 340 1.2.2.2 mjf * real point using that feature. 341 1.2.2.2 mjf */ 342 1.2.2.2 mjf sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 343 1.2.2.2 mjf 344 1.2.2.2 mjf if_attach(ifp); 345 1.2.2.2 mjf ether_ifattach(ifp, eaddr); 346 1.2.2.2 mjf 347 1.2.2.2 mjf if (!pmf_device_register(self, NULL, NULL)) 348 1.2.2.2 mjf aprint_error_dev(self, "couldn't establish power handler\n"); 349 1.2.2.2 mjf else 350 1.2.2.2 mjf pmf_class_network_register(self, ifp); 351 1.2.2.2 mjf 352 1.2.2.2 mjf return; 353 1.2.2.2 mjf } 354 1.2.2.2 mjf 355 1.2.2.2 mjf static int 356 1.2.2.2 mjf lii_reset(struct lii_softc *sc) 357 1.2.2.2 mjf { 358 1.2.2.2 mjf int i; 359 1.2.2.2 mjf 360 1.2.2.2 mjf DPRINTF(("lii_reset\n")); 361 1.2.2.2 mjf 362 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); 363 1.2.2.2 mjf DELAY(1000); 364 1.2.2.2 mjf 365 1.2.2.2 mjf for (i = 0; i < 10; ++i) { 366 1.2.2.2 mjf if (AT_READ_4(sc, ATL2_BIS) == 0) 367 1.2.2.2 mjf break; 368 1.2.2.2 mjf DELAY(1000); 369 1.2.2.2 mjf } 370 1.2.2.2 mjf 371 1.2.2.2 mjf if (i == 10) { 372 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "reset failed\n"); 373 1.2.2.2 mjf return 1; 374 1.2.2.2 mjf } 375 1.2.2.2 mjf 376 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); 377 1.2.2.2 mjf DELAY(10); 378 1.2.2.2 mjf 379 1.2.2.2 mjf /* Init PCI-Express module */ 380 1.2.2.2 mjf /* Magic Numbers Warning */ 381 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); 382 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); 383 1.2.2.2 mjf 384 1.2.2.2 mjf return 0; 385 1.2.2.2 mjf } 386 1.2.2.2 mjf 387 1.2.2.2 mjf static bool 388 1.2.2.2 mjf lii_eeprom_present(struct lii_softc *sc) 389 1.2.2.2 mjf { 390 1.2.2.2 mjf /* 391 1.2.2.2 mjf * The Linux driver does this, but then it has a very weird way of 392 1.2.2.2 mjf * checking whether the PCI configuration space exposes the Vital 393 1.2.2.2 mjf * Product Data capability, so maybe it's not really needed. 394 1.2.2.2 mjf */ 395 1.2.2.2 mjf 396 1.2.2.2 mjf #ifdef weirdloonix 397 1.2.2.2 mjf uint32_t val; 398 1.2.2.2 mjf 399 1.2.2.2 mjf val = AT_READ_4(sc, ATL2_SFC); 400 1.2.2.2 mjf if (val & SFC_EN_VPD) 401 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); 402 1.2.2.2 mjf #endif 403 1.2.2.2 mjf 404 1.2.2.2 mjf return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 405 1.2.2.2 mjf NULL, NULL) == 1; 406 1.2.2.2 mjf } 407 1.2.2.2 mjf 408 1.2.2.2 mjf static int 409 1.2.2.2 mjf lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 410 1.2.2.2 mjf { 411 1.2.2.2 mjf int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 412 1.2.2.2 mjf 413 1.2.2.2 mjf DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val)); 414 1.2.2.2 mjf 415 1.2.2.2 mjf return r; 416 1.2.2.2 mjf } 417 1.2.2.2 mjf 418 1.2.2.2 mjf static void 419 1.2.2.2 mjf lii_spi_configure(struct lii_softc *sc) 420 1.2.2.2 mjf { 421 1.2.2.2 mjf /* 422 1.2.2.2 mjf * We don't offer a way to configure the SPI Flash vendor parameter, so 423 1.2.2.2 mjf * the table is given for reference 424 1.2.2.2 mjf */ 425 1.2.2.2 mjf static const struct lii_spi_flash_vendor { 426 1.2.2.2 mjf const char *sfv_name; 427 1.2.2.2 mjf const uint8_t sfv_opcodes[9]; 428 1.2.2.2 mjf } lii_sfv[] = { 429 1.2.2.2 mjf { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 430 1.2.2.2 mjf { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 431 1.2.2.2 mjf { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 432 1.2.2.2 mjf }; 433 1.2.2.2 mjf #define SF_OPCODE_WRSR 0 434 1.2.2.2 mjf #define SF_OPCODE_READ 1 435 1.2.2.2 mjf #define SF_OPCODE_PRGM 2 436 1.2.2.2 mjf #define SF_OPCODE_WREN 3 437 1.2.2.2 mjf #define SF_OPCODE_WRDI 4 438 1.2.2.2 mjf #define SF_OPCODE_RDSR 5 439 1.2.2.2 mjf #define SF_OPCODE_RDID 6 440 1.2.2.2 mjf #define SF_OPCODE_SECT_ER 7 441 1.2.2.2 mjf #define SF_OPCODE_CHIP_ER 8 442 1.2.2.2 mjf 443 1.2.2.2 mjf #define SF_DEFAULT_VENDOR 0 444 1.2.2.2 mjf static const uint8_t vendor = SF_DEFAULT_VENDOR; 445 1.2.2.2 mjf 446 1.2.2.2 mjf /* 447 1.2.2.2 mjf * Why isn't WRDI used? Heck if I know. 448 1.2.2.2 mjf */ 449 1.2.2.2 mjf 450 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_WRSR, 451 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 452 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_READ, 453 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 454 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, 455 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 456 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_WREN, 457 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 458 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_RDSR, 459 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 460 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_RDID, 461 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 462 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, 463 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 464 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, 465 1.2.2.2 mjf lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 466 1.2.2.2 mjf } 467 1.2.2.2 mjf 468 1.2.2.2 mjf #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 469 1.2.2.2 mjf ( (((cssetup) & SFC_CS_SETUP_MASK) \ 470 1.2.2.2 mjf << SFC_CS_SETUP_SHIFT) \ 471 1.2.2.2 mjf | (((clkhi) & SFC_CLK_HI_MASK) \ 472 1.2.2.2 mjf << SFC_CLK_HI_SHIFT) \ 473 1.2.2.2 mjf | (((clklo) & SFC_CLK_LO_MASK) \ 474 1.2.2.2 mjf << SFC_CLK_LO_SHIFT) \ 475 1.2.2.2 mjf | (((cshold) & SFC_CS_HOLD_MASK) \ 476 1.2.2.2 mjf << SFC_CS_HOLD_SHIFT) \ 477 1.2.2.2 mjf | (((cshi) & SFC_CS_HI_MASK) \ 478 1.2.2.2 mjf << SFC_CS_HI_SHIFT) \ 479 1.2.2.2 mjf | (((ins) & SFC_INS_MASK) \ 480 1.2.2.2 mjf << SFC_INS_SHIFT)) 481 1.2.2.2 mjf 482 1.2.2.2 mjf /* Magic settings from the Linux driver */ 483 1.2.2.2 mjf 484 1.2.2.2 mjf #define CUSTOM_SPI_CS_SETUP 2 485 1.2.2.2 mjf #define CUSTOM_SPI_CLK_HI 2 486 1.2.2.2 mjf #define CUSTOM_SPI_CLK_LO 2 487 1.2.2.2 mjf #define CUSTOM_SPI_CS_HOLD 2 488 1.2.2.2 mjf #define CUSTOM_SPI_CS_HI 3 489 1.2.2.2 mjf 490 1.2.2.2 mjf static int 491 1.2.2.2 mjf lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 492 1.2.2.2 mjf { 493 1.2.2.2 mjf uint32_t v; 494 1.2.2.2 mjf int i; 495 1.2.2.2 mjf 496 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SF_DATA, 0); 497 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SF_ADDR, reg); 498 1.2.2.2 mjf 499 1.2.2.2 mjf v = SFC_WAIT_READY | 500 1.2.2.2 mjf MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 501 1.2.2.2 mjf CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 502 1.2.2.2 mjf 503 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SFC, v); 504 1.2.2.2 mjf v |= SFC_START; 505 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SFC, v); 506 1.2.2.2 mjf 507 1.2.2.2 mjf for (i = 0; i < 10; ++i) { 508 1.2.2.2 mjf DELAY(1000); 509 1.2.2.2 mjf if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) 510 1.2.2.2 mjf break; 511 1.2.2.2 mjf } 512 1.2.2.2 mjf if (i == 10) 513 1.2.2.2 mjf return EBUSY; 514 1.2.2.2 mjf 515 1.2.2.2 mjf *val = AT_READ_4(sc, ATL2_SF_DATA); 516 1.2.2.2 mjf return 0; 517 1.2.2.2 mjf } 518 1.2.2.2 mjf 519 1.2.2.2 mjf static int 520 1.2.2.2 mjf lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 521 1.2.2.2 mjf { 522 1.2.2.2 mjf uint32_t offset = 0x100; 523 1.2.2.2 mjf uint32_t val, val1, addr0 = 0, addr1 = 0; 524 1.2.2.2 mjf uint8_t found = 0; 525 1.2.2.2 mjf 526 1.2.2.2 mjf while ((*sc->sc_memread)(sc, offset, &val) == 0) { 527 1.2.2.2 mjf offset += 4; 528 1.2.2.2 mjf 529 1.2.2.2 mjf /* Each chunk of data starts with a signature */ 530 1.2.2.2 mjf if ((val & 0xff) != 0x5a) 531 1.2.2.2 mjf break; 532 1.2.2.2 mjf if ((*sc->sc_memread)(sc, offset, &val1)) 533 1.2.2.2 mjf break; 534 1.2.2.2 mjf 535 1.2.2.2 mjf offset += 4; 536 1.2.2.2 mjf 537 1.2.2.2 mjf val >>= 16; 538 1.2.2.2 mjf switch (val) { 539 1.2.2.2 mjf case ATL2_MAC_ADDR_0: 540 1.2.2.2 mjf addr0 = val1; 541 1.2.2.2 mjf ++found; 542 1.2.2.2 mjf break; 543 1.2.2.2 mjf case ATL2_MAC_ADDR_1: 544 1.2.2.2 mjf addr1 = val1; 545 1.2.2.2 mjf ++found; 546 1.2.2.2 mjf break; 547 1.2.2.2 mjf default: 548 1.2.2.2 mjf continue; 549 1.2.2.2 mjf } 550 1.2.2.2 mjf } 551 1.2.2.2 mjf 552 1.2.2.2 mjf if (found < 2) { 553 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "error reading MAC address\n"); 554 1.2.2.2 mjf return 1; 555 1.2.2.2 mjf } 556 1.2.2.2 mjf 557 1.2.2.2 mjf addr0 = htole32(addr0); 558 1.2.2.2 mjf addr1 = htole32(addr1); 559 1.2.2.2 mjf 560 1.2.2.2 mjf if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 561 1.2.2.2 mjf (addr0 == 0 && (addr1 & 0xffff) == 0)) { 562 1.2.2.2 mjf addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); 563 1.2.2.2 mjf addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); 564 1.2.2.2 mjf } 565 1.2.2.2 mjf 566 1.2.2.2 mjf ea[0] = (addr1 & 0x0000ff00) >> 8; 567 1.2.2.2 mjf ea[1] = (addr1 & 0x000000ff); 568 1.2.2.2 mjf ea[2] = (addr0 & 0xff000000) >> 24; 569 1.2.2.2 mjf ea[3] = (addr0 & 0x00ff0000) >> 16; 570 1.2.2.2 mjf ea[4] = (addr0 & 0x0000ff00) >> 8; 571 1.2.2.2 mjf ea[5] = (addr0 & 0x000000ff); 572 1.2.2.2 mjf 573 1.2.2.2 mjf return 0; 574 1.2.2.2 mjf } 575 1.2.2.2 mjf 576 1.2.2.2 mjf static int 577 1.2.2.2 mjf lii_mii_readreg(device_t dev, int phy, int reg) 578 1.2.2.2 mjf { 579 1.2.2.2 mjf struct lii_softc *sc = device_private(dev); 580 1.2.2.2 mjf uint32_t val; 581 1.2.2.2 mjf int i; 582 1.2.2.2 mjf 583 1.2.2.2 mjf val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 584 1.2.2.2 mjf 585 1.2.2.2 mjf val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 586 1.2.2.2 mjf val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 587 1.2.2.2 mjf 588 1.2.2.2 mjf val |= MDIOC_READ; 589 1.2.2.2 mjf 590 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MDIOC, val); 591 1.2.2.2 mjf 592 1.2.2.2 mjf for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 593 1.2.2.2 mjf DELAY(2); 594 1.2.2.2 mjf val = AT_READ_4(sc, ATL2_MDIOC); 595 1.2.2.2 mjf if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 596 1.2.2.2 mjf break; 597 1.2.2.2 mjf } 598 1.2.2.2 mjf 599 1.2.2.2 mjf if (i == MDIO_WAIT_TIMES) 600 1.2.2.2 mjf aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy, 601 1.2.2.2 mjf reg); 602 1.2.2.2 mjf 603 1.2.2.2 mjf return (val & 0x0000ffff); 604 1.2.2.2 mjf } 605 1.2.2.2 mjf 606 1.2.2.2 mjf static void 607 1.2.2.2 mjf lii_mii_writereg(device_t dev, int phy, int reg, int data) 608 1.2.2.2 mjf { 609 1.2.2.2 mjf struct lii_softc *sc = device_private(dev); 610 1.2.2.2 mjf uint32_t val; 611 1.2.2.2 mjf int i; 612 1.2.2.2 mjf 613 1.2.2.2 mjf val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 614 1.2.2.2 mjf val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 615 1.2.2.2 mjf 616 1.2.2.2 mjf val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 617 1.2.2.2 mjf val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 618 1.2.2.2 mjf 619 1.2.2.2 mjf /* val |= MDIOC_WRITE; */ 620 1.2.2.2 mjf 621 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MDIOC, val); 622 1.2.2.2 mjf 623 1.2.2.2 mjf for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 624 1.2.2.2 mjf DELAY(2); 625 1.2.2.2 mjf val = AT_READ_4(sc, ATL2_MDIOC); 626 1.2.2.2 mjf if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 627 1.2.2.2 mjf break; 628 1.2.2.2 mjf } 629 1.2.2.2 mjf 630 1.2.2.2 mjf if (i == MDIO_WAIT_TIMES) 631 1.2.2.2 mjf aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy, 632 1.2.2.2 mjf reg); 633 1.2.2.2 mjf } 634 1.2.2.2 mjf 635 1.2.2.2 mjf static void 636 1.2.2.2 mjf lii_mii_statchg(device_t dev) 637 1.2.2.2 mjf { 638 1.2.2.2 mjf struct lii_softc *sc = device_private(dev); 639 1.2.2.2 mjf uint32_t val; 640 1.2.2.2 mjf 641 1.2.2.2 mjf DPRINTF(("lii_mii_statchg\n")); 642 1.2.2.2 mjf 643 1.2.2.2 mjf val = AT_READ_4(sc, ATL2_MACC); 644 1.2.2.2 mjf 645 1.2.2.2 mjf if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 646 1.2.2.2 mjf val |= MACC_FDX; 647 1.2.2.2 mjf else 648 1.2.2.2 mjf val &= ~MACC_FDX; 649 1.2.2.2 mjf 650 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MACC, val); 651 1.2.2.2 mjf } 652 1.2.2.2 mjf 653 1.2.2.2 mjf static int 654 1.2.2.2 mjf lii_media_change(struct ifnet *ifp) 655 1.2.2.2 mjf { 656 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 657 1.2.2.2 mjf 658 1.2.2.2 mjf DPRINTF(("lii_media_change\n")); 659 1.2.2.2 mjf 660 1.2.2.2 mjf if (ifp->if_flags & IFF_UP) 661 1.2.2.2 mjf mii_mediachg(&sc->sc_mii); 662 1.2.2.2 mjf return 0; 663 1.2.2.2 mjf } 664 1.2.2.2 mjf 665 1.2.2.2 mjf static void 666 1.2.2.2 mjf lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 667 1.2.2.2 mjf { 668 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 669 1.2.2.2 mjf 670 1.2.2.2 mjf DPRINTF(("lii_media_status\n")); 671 1.2.2.2 mjf 672 1.2.2.2 mjf mii_pollstat(&sc->sc_mii); 673 1.2.2.2 mjf imr->ifm_status = sc->sc_mii.mii_media_status; 674 1.2.2.2 mjf imr->ifm_active = sc->sc_mii.mii_media_active; 675 1.2.2.2 mjf } 676 1.2.2.2 mjf 677 1.2.2.2 mjf static int 678 1.2.2.2 mjf lii_init(struct ifnet *ifp) 679 1.2.2.2 mjf { 680 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 681 1.2.2.2 mjf uint32_t val; 682 1.2.2.2 mjf int error; 683 1.2.2.2 mjf 684 1.2.2.2 mjf DPRINTF(("lii_init\n")); 685 1.2.2.2 mjf 686 1.2.2.2 mjf lii_stop(ifp, 0); 687 1.2.2.2 mjf 688 1.2.2.2 mjf memset(sc->sc_ring, 0, sc->sc_ringsize); 689 1.2.2.2 mjf 690 1.2.2.2 mjf /* Disable all interrupts */ 691 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); 692 1.2.2.2 mjf 693 1.2.2.2 mjf /* XXX endianness */ 694 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MAC_ADDR_0, 695 1.2.2.2 mjf sc->sc_eaddr[2] << 24 | 696 1.2.2.2 mjf sc->sc_eaddr[3] << 16 | 697 1.2.2.2 mjf sc->sc_eaddr[4] << 8 | 698 1.2.2.2 mjf sc->sc_eaddr[5]); 699 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MAC_ADDR_1, 700 1.2.2.2 mjf sc->sc_eaddr[0] << 8 | 701 1.2.2.2 mjf sc->sc_eaddr[1]); 702 1.2.2.2 mjf 703 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); 704 1.2.2.2 mjf /* XXX 705 1.2.2.2 mjf sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 706 1.2.2.2 mjf */ 707 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, 708 1.2.2.2 mjf (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 709 1.2.2.2 mjf + AT_RXD_PADDING); 710 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, 711 1.2.2.2 mjf sc->sc_txsp & 0xffffffff); 712 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, 713 1.2.2.2 mjf sc->sc_txdp & 0xffffffff); 714 1.2.2.2 mjf 715 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 716 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); 717 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); 718 1.2.2.2 mjf 719 1.2.2.2 mjf /* 720 1.2.2.2 mjf * Inter Paket Gap Time = 0x60 (IPGT) 721 1.2.2.2 mjf * Minimum inter-frame gap for RX = 0x50 (MIFG) 722 1.2.2.2 mjf * 64-bit Carrier-Sense window = 0x40 (IPGR1) 723 1.2.2.2 mjf * 96-bit IPG window = 0x60 (IPGR2) 724 1.2.2.2 mjf */ 725 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); 726 1.2.2.2 mjf 727 1.2.2.2 mjf /* 728 1.2.2.2 mjf * Collision window = 0x37 (LCOL) 729 1.2.2.2 mjf * Maximum # of retrans = 0xf (RETRY) 730 1.2.2.2 mjf * Maximum binary expansion # = 0xa (ABEBT) 731 1.2.2.2 mjf * IPG to start jam = 0x7 (JAMIPG) 732 1.2.2.2 mjf */ 733 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | 734 1.2.2.2 mjf MHDC_EXC_DEF_EN); 735 1.2.2.2 mjf 736 1.2.2.2 mjf /* 100 means 200us */ 737 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_IMTIV, 100); 738 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); 739 1.2.2.2 mjf 740 1.2.2.2 mjf /* 500000 means 100ms */ 741 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_IALTIV, 50000); 742 1.2.2.2 mjf 743 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN 744 1.2.2.2 mjf + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 745 1.2.2.2 mjf 746 1.2.2.2 mjf /* unit unknown for TX cur-through threshold */ 747 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); 748 1.2.2.2 mjf 749 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 750 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); 751 1.2.2.2 mjf 752 1.2.2.2 mjf sc->sc_rxcur = 0; 753 1.2.2.2 mjf sc->sc_txs_cur = sc->sc_txs_ack = 0; 754 1.2.2.2 mjf sc->sc_txd_cur = sc->sc_txd_ack = 0; 755 1.2.2.2 mjf sc->sc_free_tx_slots = true; 756 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); 757 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 758 1.2.2.2 mjf 759 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); 760 1.2.2.2 mjf AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); 761 1.2.2.2 mjf 762 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); 763 1.2.2.2 mjf 764 1.2.2.2 mjf error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); 765 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); 766 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_ISR, 0); 767 1.2.2.2 mjf if (error) { 768 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "init failed\n"); 769 1.2.2.2 mjf goto out; 770 1.2.2.2 mjf } 771 1.2.2.2 mjf 772 1.2.2.2 mjf lii_setmulti(sc); 773 1.2.2.2 mjf 774 1.2.2.2 mjf val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; 775 1.2.2.2 mjf 776 1.2.2.2 mjf val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 777 1.2.2.2 mjf MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 778 1.2.2.2 mjf MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 779 1.2.2.2 mjf 780 1.2.2.2 mjf if (ifp->if_flags & IFF_PROMISC) 781 1.2.2.2 mjf val |= MACC_PROMISC_EN; 782 1.2.2.2 mjf else if (ifp->if_flags & IFF_ALLMULTI) 783 1.2.2.2 mjf val |= MACC_ALLMULTI_EN; 784 1.2.2.2 mjf 785 1.2.2.2 mjf val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 786 1.2.2.2 mjf val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 787 1.2.2.2 mjf 788 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MACC, val); 789 1.2.2.2 mjf 790 1.2.2.2 mjf mii_mediachg(&sc->sc_mii); 791 1.2.2.2 mjf 792 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); 793 1.2.2.2 mjf 794 1.2.2.2 mjf callout_schedule(&sc->sc_tick_ch, hz); 795 1.2.2.2 mjf 796 1.2.2.2 mjf ifp->if_flags |= IFF_RUNNING; 797 1.2.2.2 mjf ifp->if_flags &= ~IFF_OACTIVE; 798 1.2.2.2 mjf 799 1.2.2.2 mjf out: 800 1.2.2.2 mjf return error; 801 1.2.2.2 mjf } 802 1.2.2.2 mjf 803 1.2.2.2 mjf static void 804 1.2.2.2 mjf lii_tx_put(struct lii_softc *sc, struct mbuf *m) 805 1.2.2.2 mjf { 806 1.2.2.2 mjf int left; 807 1.2.2.2 mjf struct tx_pkt_header *tph = 808 1.2.2.2 mjf (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 809 1.2.2.2 mjf 810 1.2.2.2 mjf memset(tph, 0, sizeof *tph); 811 1.2.2.2 mjf tph->txph_size = m->m_pkthdr.len; 812 1.2.2.2 mjf 813 1.2.2.2 mjf sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 814 1.2.2.2 mjf 815 1.2.2.2 mjf /* 816 1.2.2.2 mjf * We already know we have enough space, so if there is a part of the 817 1.2.2.2 mjf * space ahead of txd_cur that is active, it doesn't matter because 818 1.2.2.2 mjf * left will be large enough even without it. 819 1.2.2.2 mjf */ 820 1.2.2.2 mjf left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 821 1.2.2.2 mjf 822 1.2.2.2 mjf if (left > m->m_pkthdr.len) { 823 1.2.2.2 mjf m_copydata(m, 0, m->m_pkthdr.len, 824 1.2.2.2 mjf sc->sc_txdbase + sc->sc_txd_cur); 825 1.2.2.2 mjf sc->sc_txd_cur += m->m_pkthdr.len; 826 1.2.2.2 mjf } else { 827 1.2.2.2 mjf m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 828 1.2.2.2 mjf m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 829 1.2.2.2 mjf sc->sc_txd_cur = m->m_pkthdr.len - left; 830 1.2.2.2 mjf } 831 1.2.2.2 mjf 832 1.2.2.2 mjf /* Round to a 32-bit boundary */ 833 1.2.2.2 mjf sc->sc_txd_cur = (sc->sc_txd_cur + 3) & ~3; 834 1.2.2.2 mjf if (sc->sc_txd_cur == sc->sc_txd_ack) 835 1.2.2.2 mjf sc->sc_free_tx_slots = false; 836 1.2.2.2 mjf } 837 1.2.2.2 mjf 838 1.2.2.2 mjf static int 839 1.2.2.2 mjf lii_free_tx_space(struct lii_softc *sc) 840 1.2.2.2 mjf { 841 1.2.2.2 mjf int space; 842 1.2.2.2 mjf 843 1.2.2.2 mjf if (sc->sc_txd_cur >= sc->sc_txd_ack) 844 1.2.2.2 mjf space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 845 1.2.2.2 mjf sc->sc_txd_ack; 846 1.2.2.2 mjf else 847 1.2.2.2 mjf space = sc->sc_txd_ack - sc->sc_txd_cur; 848 1.2.2.2 mjf 849 1.2.2.2 mjf /* Account for the tx_pkt_header */ 850 1.2.2.2 mjf return (space - 4); 851 1.2.2.2 mjf } 852 1.2.2.2 mjf 853 1.2.2.2 mjf static void 854 1.2.2.2 mjf lii_start(struct ifnet *ifp) 855 1.2.2.2 mjf { 856 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 857 1.2.2.2 mjf struct mbuf *m0; 858 1.2.2.2 mjf 859 1.2.2.2 mjf DPRINTF(("lii_start\n")); 860 1.2.2.2 mjf 861 1.2.2.2 mjf if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 862 1.2.2.2 mjf return; 863 1.2.2.2 mjf 864 1.2.2.2 mjf for (;;) { 865 1.2.2.2 mjf IFQ_POLL(&ifp->if_snd, m0); 866 1.2.2.2 mjf if (m0 == NULL) 867 1.2.2.2 mjf break; 868 1.2.2.2 mjf 869 1.2.2.2 mjf if (!sc->sc_free_tx_slots || 870 1.2.2.2 mjf lii_free_tx_space(sc) < m0->m_pkthdr.len) { 871 1.2.2.2 mjf ifp->if_flags |= IFF_OACTIVE; 872 1.2.2.2 mjf break; 873 1.2.2.2 mjf } 874 1.2.2.2 mjf 875 1.2.2.2 mjf lii_tx_put(sc, m0); 876 1.2.2.2 mjf 877 1.2.2.2 mjf DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 878 1.2.2.2 mjf 879 1.2.2.2 mjf sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 880 1.2.2.2 mjf sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 881 1.2.2.2 mjf if (sc->sc_txs_cur == sc->sc_txs_ack) 882 1.2.2.2 mjf sc->sc_free_tx_slots = false; 883 1.2.2.2 mjf 884 1.2.2.2 mjf AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 885 1.2.2.2 mjf 886 1.2.2.2 mjf IFQ_DEQUEUE(&ifp->if_snd, m0); 887 1.2.2.2 mjf 888 1.2.2.2 mjf #if NBPFILTER > 0 889 1.2.2.2 mjf if (ifp->if_bpf != NULL) 890 1.2.2.2 mjf bpf_mtap(ifp->if_bpf, m0); 891 1.2.2.2 mjf #endif 892 1.2.2.2 mjf m_freem(m0); 893 1.2.2.2 mjf } 894 1.2.2.2 mjf } 895 1.2.2.2 mjf 896 1.2.2.2 mjf static void 897 1.2.2.2 mjf lii_stop(struct ifnet *ifp, int disable) 898 1.2.2.2 mjf { 899 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 900 1.2.2.2 mjf 901 1.2.2.2 mjf callout_stop(&sc->sc_tick_ch); 902 1.2.2.2 mjf 903 1.2.2.2 mjf ifp->if_timer = 0; 904 1.2.2.2 mjf ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 905 1.2.2.2 mjf 906 1.2.2.2 mjf mii_down(&sc->sc_mii); 907 1.2.2.2 mjf 908 1.2.2.2 mjf lii_reset(sc); 909 1.2.2.2 mjf 910 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_IMR, 0); 911 1.2.2.2 mjf } 912 1.2.2.2 mjf 913 1.2.2.2 mjf static int 914 1.2.2.2 mjf lii_intr(void *v) 915 1.2.2.2 mjf { 916 1.2.2.2 mjf struct lii_softc *sc = v; 917 1.2.2.2 mjf uint32_t status; 918 1.2.2.2 mjf 919 1.2.2.2 mjf status = AT_READ_4(sc, ATL2_ISR); 920 1.2.2.2 mjf if (status == 0) 921 1.2.2.2 mjf return 0; 922 1.2.2.2 mjf 923 1.2.2.2 mjf DPRINTF(("lii_intr (%x)\n", status)); 924 1.2.2.2 mjf 925 1.2.2.2 mjf /* Clear the interrupt and disable them */ 926 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); 927 1.2.2.2 mjf 928 1.2.2.2 mjf if (status & (ISR_PHY | ISR_MANUAL)) { 929 1.2.2.2 mjf /* Ack PHY interrupt. Magic register */ 930 1.2.2.2 mjf if (status & ISR_PHY) 931 1.2.2.2 mjf (void)lii_mii_readreg(sc->sc_dev, 1, 19); 932 1.2.2.2 mjf mii_mediachg(&sc->sc_mii); 933 1.2.2.2 mjf } 934 1.2.2.2 mjf 935 1.2.2.2 mjf if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 936 1.2.2.2 mjf lii_init(&sc->sc_ec.ec_if); 937 1.2.2.2 mjf return 1; 938 1.2.2.2 mjf } 939 1.2.2.2 mjf 940 1.2.2.2 mjf if (status & ISR_RX_EVENT) { 941 1.2.2.2 mjf #ifdef LII_DEBUG 942 1.2.2.2 mjf if (!(status & ISR_RS_UPDATE)) 943 1.2.2.2 mjf printf("rxintr %08x\n", status); 944 1.2.2.2 mjf #endif 945 1.2.2.2 mjf lii_rxintr(sc); 946 1.2.2.2 mjf } 947 1.2.2.2 mjf 948 1.2.2.2 mjf if (status & ISR_TX_EVENT) 949 1.2.2.2 mjf lii_txintr(sc); 950 1.2.2.2 mjf 951 1.2.2.2 mjf /* Re-enable interrupts */ 952 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_ISR, 0); 953 1.2.2.2 mjf 954 1.2.2.2 mjf return 1; 955 1.2.2.2 mjf } 956 1.2.2.2 mjf 957 1.2.2.2 mjf static void 958 1.2.2.2 mjf lii_rxintr(struct lii_softc *sc) 959 1.2.2.2 mjf { 960 1.2.2.2 mjf struct ifnet *ifp = &sc->sc_ec.ec_if; 961 1.2.2.2 mjf struct rx_pkt *rxp; 962 1.2.2.2 mjf struct mbuf *m; 963 1.2.2.2 mjf uint16_t size; 964 1.2.2.2 mjf 965 1.2.2.2 mjf DPRINTF(("lii_rxintr\n")); 966 1.2.2.2 mjf 967 1.2.2.2 mjf for (;;) { 968 1.2.2.2 mjf rxp = &sc->sc_rxp[sc->sc_rxcur]; 969 1.2.2.2 mjf if (rxp->rxp_update == 0) 970 1.2.2.2 mjf break; 971 1.2.2.2 mjf 972 1.2.2.2 mjf DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 973 1.2.2.2 mjf rxp->rxp_size, rxp->rxp_flags)); 974 1.2.2.2 mjf sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 975 1.2.2.2 mjf rxp->rxp_update = 0; 976 1.2.2.2 mjf if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { 977 1.2.2.2 mjf ++ifp->if_ierrors; 978 1.2.2.2 mjf continue; 979 1.2.2.2 mjf } 980 1.2.2.2 mjf 981 1.2.2.2 mjf MGETHDR(m, M_DONTWAIT, MT_DATA); 982 1.2.2.2 mjf if (m == NULL) { 983 1.2.2.2 mjf ++ifp->if_ierrors; 984 1.2.2.2 mjf continue; 985 1.2.2.2 mjf } 986 1.2.2.2 mjf size = rxp->rxp_size - ETHER_CRC_LEN; 987 1.2.2.2 mjf if (size > MHLEN) { 988 1.2.2.2 mjf MCLGET(m, M_DONTWAIT); 989 1.2.2.2 mjf if ((m->m_flags & M_EXT) == 0) { 990 1.2.2.2 mjf m_freem(m); 991 1.2.2.2 mjf ++ifp->if_ierrors; 992 1.2.2.2 mjf continue; 993 1.2.2.2 mjf } 994 1.2.2.2 mjf } 995 1.2.2.2 mjf 996 1.2.2.2 mjf m->m_pkthdr.rcvif = ifp; 997 1.2.2.2 mjf /* Copy the packet withhout the FCS */ 998 1.2.2.2 mjf m->m_pkthdr.len = m->m_len = size; 999 1.2.2.2 mjf memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 1000 1.2.2.2 mjf ++ifp->if_ipackets; 1001 1.2.2.2 mjf 1002 1.2.2.2 mjf #if NBPFILTER > 0 1003 1.2.2.2 mjf if (ifp->if_bpf) 1004 1.2.2.2 mjf bpf_mtap(ifp->if_bpf, m); 1005 1.2.2.2 mjf #endif 1006 1.2.2.2 mjf 1007 1.2.2.2 mjf (*ifp->if_input)(ifp, m); 1008 1.2.2.2 mjf } 1009 1.2.2.2 mjf 1010 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 1011 1.2.2.2 mjf } 1012 1.2.2.2 mjf 1013 1.2.2.2 mjf static void 1014 1.2.2.2 mjf lii_txintr(struct lii_softc *sc) 1015 1.2.2.2 mjf { 1016 1.2.2.2 mjf struct ifnet *ifp = &sc->sc_ec.ec_if; 1017 1.2.2.2 mjf struct tx_pkt_status *txs; 1018 1.2.2.2 mjf struct tx_pkt_header *txph; 1019 1.2.2.2 mjf 1020 1.2.2.2 mjf DPRINTF(("lii_txintr\n")); 1021 1.2.2.2 mjf 1022 1.2.2.2 mjf for (;;) { 1023 1.2.2.2 mjf txs = &sc->sc_txs[sc->sc_txs_ack]; 1024 1.2.2.2 mjf if (txs->txps_update == 0) 1025 1.2.2.2 mjf break; 1026 1.2.2.2 mjf DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 1027 1.2.2.2 mjf sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 1028 1.2.2.2 mjf sc->sc_free_tx_slots = true; 1029 1.2.2.2 mjf 1030 1.2.2.2 mjf txs->txps_update = 0; 1031 1.2.2.2 mjf 1032 1.2.2.2 mjf txph = (struct tx_pkt_header *) 1033 1.2.2.2 mjf (sc->sc_txdbase + sc->sc_txd_ack); 1034 1.2.2.2 mjf 1035 1.2.2.2 mjf if (txph->txph_size != txs->txps_size) 1036 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, 1037 1.2.2.2 mjf "mismatched status and packet\n"); 1038 1.2.2.2 mjf /* 1039 1.2.2.2 mjf * Move ack by the packet size, taking the packet header in 1040 1.2.2.2 mjf * account and round to the next 32-bit boundary 1041 1.2.2.2 mjf * (7 = sizeof(header) + 3) 1042 1.2.2.2 mjf */ 1043 1.2.2.2 mjf sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 1044 1.2.2.2 mjf sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 1045 1.2.2.2 mjf 1046 1.2.2.2 mjf if (txs->txps_flags & ATL2_TXF_SUCCESS) 1047 1.2.2.2 mjf ++ifp->if_opackets; 1048 1.2.2.2 mjf else 1049 1.2.2.2 mjf ++ifp->if_oerrors; 1050 1.2.2.2 mjf ifp->if_flags &= ~IFF_OACTIVE; 1051 1.2.2.2 mjf } 1052 1.2.2.2 mjf 1053 1.2.2.2 mjf if (sc->sc_free_tx_slots) 1054 1.2.2.2 mjf lii_start(ifp); 1055 1.2.2.2 mjf } 1056 1.2.2.2 mjf 1057 1.2.2.2 mjf static int 1058 1.2.2.2 mjf lii_alloc_rings(struct lii_softc *sc) 1059 1.2.2.2 mjf { 1060 1.2.2.2 mjf int nsegs; 1061 1.2.2.2 mjf bus_size_t bs; 1062 1.2.2.2 mjf 1063 1.2.2.2 mjf /* 1064 1.2.2.2 mjf * We need a big chunk of DMA-friendly memory because descriptors 1065 1.2.2.2 mjf * are not separate from data on that crappy hardware, which means 1066 1.2.2.2 mjf * we'll have to copy data from and to that memory zone to and from 1067 1.2.2.2 mjf * the mbufs. 1068 1.2.2.2 mjf * 1069 1.2.2.2 mjf * How lame is that? Using the default values from the Linux driver, 1070 1.2.2.2 mjf * we allocate space for receiving up to 64 full-size Ethernet frames, 1071 1.2.2.2 mjf * and only 8kb for transmitting up to 64 Ethernet frames. 1072 1.2.2.2 mjf */ 1073 1.2.2.2 mjf 1074 1.2.2.2 mjf sc->sc_ringsize = bs = AT_RXD_PADDING 1075 1.2.2.2 mjf + AT_RXD_NUM * sizeof(struct rx_pkt) 1076 1.2.2.2 mjf + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1077 1.2.2.2 mjf + AT_TXD_BUFFER_SIZE; 1078 1.2.2.2 mjf 1079 1.2.2.2 mjf if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1080 1.2.2.2 mjf BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1081 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n"); 1082 1.2.2.2 mjf return 1; 1083 1.2.2.2 mjf } 1084 1.2.2.2 mjf 1085 1.2.2.2 mjf if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1086 1.2.2.2 mjf &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1087 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n"); 1088 1.2.2.2 mjf goto fail; 1089 1.2.2.2 mjf } 1090 1.2.2.2 mjf 1091 1.2.2.2 mjf if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1092 1.2.2.2 mjf (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1093 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n"); 1094 1.2.2.2 mjf goto fail1; 1095 1.2.2.2 mjf } 1096 1.2.2.2 mjf 1097 1.2.2.2 mjf if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1098 1.2.2.2 mjf bs, NULL, BUS_DMA_NOWAIT) != 0) { 1099 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n"); 1100 1.2.2.2 mjf goto fail2; 1101 1.2.2.2 mjf } 1102 1.2.2.2 mjf 1103 1.2.2.2 mjf sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1104 1.2.2.2 mjf sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1105 1.2.2.2 mjf + AT_RXD_NUM * sizeof(struct rx_pkt)); 1106 1.2.2.2 mjf sc->sc_txdbase = ((char *)sc->sc_txs) 1107 1.2.2.2 mjf + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1108 1.2.2.2 mjf sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1109 1.2.2.2 mjf + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1110 1.2.2.2 mjf sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1111 1.2.2.2 mjf + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1112 1.2.2.2 mjf 1113 1.2.2.2 mjf return 0; 1114 1.2.2.2 mjf 1115 1.2.2.2 mjf fail2: 1116 1.2.2.2 mjf bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1117 1.2.2.2 mjf fail1: 1118 1.2.2.2 mjf bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1119 1.2.2.2 mjf fail: 1120 1.2.2.2 mjf bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1121 1.2.2.2 mjf return 1; 1122 1.2.2.2 mjf } 1123 1.2.2.2 mjf 1124 1.2.2.2 mjf static void 1125 1.2.2.2 mjf lii_watchdog(struct ifnet *ifp) 1126 1.2.2.2 mjf { 1127 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 1128 1.2.2.2 mjf 1129 1.2.2.2 mjf aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1130 1.2.2.2 mjf ++ifp->if_oerrors; 1131 1.2.2.2 mjf lii_init(ifp); 1132 1.2.2.2 mjf } 1133 1.2.2.2 mjf 1134 1.2.2.2 mjf static int 1135 1.2.2.2 mjf lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1136 1.2.2.2 mjf { 1137 1.2.2.2 mjf struct lii_softc *sc = ifp->if_softc; 1138 1.2.2.2 mjf int s, error; 1139 1.2.2.2 mjf 1140 1.2.2.2 mjf s = splnet(); 1141 1.2.2.2 mjf 1142 1.2.2.2 mjf switch(cmd) { 1143 1.2.2.2 mjf case SIOCADDMULTI: 1144 1.2.2.2 mjf case SIOCDELMULTI: 1145 1.2.2.2 mjf if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1146 1.2.2.2 mjf if (ifp->if_flags & IFF_RUNNING) 1147 1.2.2.2 mjf lii_setmulti(sc); 1148 1.2.2.2 mjf error = 0; 1149 1.2.2.2 mjf } 1150 1.2.2.2 mjf break; 1151 1.2.2.2 mjf case SIOCSIFMEDIA: 1152 1.2.2.2 mjf case SIOCGIFMEDIA: 1153 1.2.2.2 mjf error = ifmedia_ioctl(ifp, (struct ifreq *)data, 1154 1.2.2.2 mjf &sc->sc_mii.mii_media, cmd); 1155 1.2.2.2 mjf break; 1156 1.2.2.2 mjf default: 1157 1.2.2.2 mjf error = ether_ioctl(ifp, cmd, data); 1158 1.2.2.2 mjf if (error == ENETRESET) { 1159 1.2.2.2 mjf if (ifp->if_flags & IFF_RUNNING) 1160 1.2.2.2 mjf lii_setmulti(sc); 1161 1.2.2.2 mjf error = 0; 1162 1.2.2.2 mjf } 1163 1.2.2.2 mjf break; 1164 1.2.2.2 mjf } 1165 1.2.2.2 mjf 1166 1.2.2.2 mjf splx(s); 1167 1.2.2.2 mjf 1168 1.2.2.2 mjf return error; 1169 1.2.2.2 mjf } 1170 1.2.2.2 mjf 1171 1.2.2.2 mjf static void 1172 1.2.2.2 mjf lii_setmulti(struct lii_softc *sc) 1173 1.2.2.2 mjf { 1174 1.2.2.2 mjf struct ethercom *ec = &sc->sc_ec; 1175 1.2.2.2 mjf struct ifnet *ifp = &ec->ec_if; 1176 1.2.2.2 mjf uint32_t mht0 = 0, mht1 = 0, crc; 1177 1.2.2.2 mjf struct ether_multi *enm; 1178 1.2.2.2 mjf struct ether_multistep step; 1179 1.2.2.2 mjf 1180 1.2.2.2 mjf /* Clear multicast hash table */ 1181 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MHT, 0); 1182 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MHT + 4, 0); 1183 1.2.2.2 mjf 1184 1.2.2.2 mjf ifp->if_flags &= ~IFF_ALLMULTI; 1185 1.2.2.2 mjf 1186 1.2.2.2 mjf ETHER_FIRST_MULTI(step, ec, enm); 1187 1.2.2.2 mjf while (enm != NULL) { 1188 1.2.2.2 mjf if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1189 1.2.2.2 mjf ifp->if_flags |= IFF_ALLMULTI; 1190 1.2.2.2 mjf mht0 = mht1 = 0; 1191 1.2.2.2 mjf goto alldone; 1192 1.2.2.2 mjf } 1193 1.2.2.2 mjf 1194 1.2.2.2 mjf crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1195 1.2.2.2 mjf 1196 1.2.2.2 mjf if (crc & (1 << 31)) 1197 1.2.2.2 mjf mht1 |= (1 << (crc & 0x0000001f)); 1198 1.2.2.2 mjf else 1199 1.2.2.2 mjf mht0 |= (1 << (crc & 0x0000001f)); 1200 1.2.2.2 mjf 1201 1.2.2.2 mjf ETHER_NEXT_MULTI(step, enm); 1202 1.2.2.2 mjf } 1203 1.2.2.2 mjf 1204 1.2.2.2 mjf alldone: 1205 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MHT, mht0); 1206 1.2.2.2 mjf AT_WRITE_4(sc, ATL2_MHT+4, mht1); 1207 1.2.2.2 mjf } 1208 1.2.2.2 mjf 1209 1.2.2.2 mjf static void 1210 1.2.2.2 mjf lii_tick(void *v) 1211 1.2.2.2 mjf { 1212 1.2.2.2 mjf struct lii_softc *sc = v; 1213 1.2.2.2 mjf int s; 1214 1.2.2.2 mjf 1215 1.2.2.2 mjf s = splnet(); 1216 1.2.2.2 mjf mii_tick(&sc->sc_mii); 1217 1.2.2.2 mjf splx(s); 1218 1.2.2.2 mjf 1219 1.2.2.2 mjf callout_schedule(&sc->sc_tick_ch, hz); 1220 1.2.2.2 mjf } 1221
Indexes created Mon Oct 20 03:09:53 GMT 2025