if_lii.c revision 1.5.4.1 1 /* $NetBSD: if_lii.c,v 1.5.4.1 2011/05/20 19:19:57 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 2008 The NetBSD Foundation.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.5.4.1 2011/05/20 19:19:57 bouyer Exp $");
35
36 #include "bpfilter.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/types.h>
41 #include <sys/device.h>
42 #include <sys/endian.h>
43 #include <sys/kernel.h>
44 #include <sys/sockio.h>
45
46 #include <net/if.h>
47 #include <net/if_media.h>
48 #include <net/if_ether.h>
49
50 #if NBPFILTER > 0
51 #include <net/bpf.h>
52 #endif
53
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
56
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcivar.h>
59 #include <dev/pci/pcidevs.h>
60
61 #include <dev/pci/if_liireg.h>
62
63 /* #define LII_DEBUG */
64 #ifdef LII_DEBUG
65 #define DPRINTF(x) printf x
66 #else
67 #define DPRINTF(x)
68 #endif
69
70 struct lii_softc {
71 device_t sc_dev;
72 pci_chipset_tag_t sc_pc;
73 pcitag_t sc_tag;
74
75 bus_space_tag_t sc_mmiot;
76 bus_space_handle_t sc_mmioh;
77
78 /*
79 * We allocate a big chunk of DMA-safe memory for all data exchanges.
80 * It is unfortunate that this chip doesn't seem to do scatter-gather.
81 */
82 bus_dma_tag_t sc_dmat;
83 bus_dmamap_t sc_ringmap;
84 bus_dma_segment_t sc_ringseg;
85
86 uint8_t *sc_ring; /* the whole area */
87 size_t sc_ringsize;
88
89 struct rx_pkt *sc_rxp; /* the part used for RX */
90 struct tx_pkt_status *sc_txs; /* the parts used for TX */
91 bus_addr_t sc_txsp;
92 char *sc_txdbase;
93 bus_addr_t sc_txdp;
94
95 unsigned int sc_rxcur;
96 /* the active area is [ack; cur[ */
97 int sc_txs_cur;
98 int sc_txs_ack;
99 int sc_txd_cur;
100 int sc_txd_ack;
101 bool sc_free_tx_slots;
102
103 void *sc_ih;
104
105 struct ethercom sc_ec;
106 struct mii_data sc_mii;
107 callout_t sc_tick_ch;
108 uint8_t sc_eaddr[ETHER_ADDR_LEN];
109
110 int (*sc_memread)(struct lii_softc *, uint32_t,
111 uint32_t *);
112 };
113
114 static int lii_match(device_t, cfdata_t, void *);
115 static void lii_attach(device_t, device_t, void *);
116
117 static int lii_reset(struct lii_softc *);
118 static bool lii_eeprom_present(struct lii_softc *);
119 static int lii_read_macaddr(struct lii_softc *, uint8_t *);
120 static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *);
121 static void lii_spi_configure(struct lii_softc *);
122 static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *);
123 static void lii_setmulti(struct lii_softc *);
124 static void lii_tick(void *);
125
126 static int lii_alloc_rings(struct lii_softc *);
127 static int lii_free_tx_space(struct lii_softc *);
128
129 static int lii_mii_readreg(device_t, int, int);
130 static void lii_mii_writereg(device_t, int, int, int);
131 static void lii_mii_statchg(device_t);
132
133 static int lii_media_change(struct ifnet *);
134 static void lii_media_status(struct ifnet *, struct ifmediareq *);
135
136 static int lii_init(struct ifnet *);
137 static void lii_start(struct ifnet *);
138 static void lii_stop(struct ifnet *, int);
139 static void lii_watchdog(struct ifnet *);
140 static int lii_ioctl(struct ifnet *, u_long, void *);
141
142 static int lii_intr(void *);
143 static void lii_rxintr(struct lii_softc *);
144 static void lii_txintr(struct lii_softc *);
145
146 CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc),
147 lii_match, lii_attach, NULL, NULL);
148
149 /* #define LII_DEBUG_REGS */
150 #ifndef LII_DEBUG_REGS
151 #define AT_READ_4(sc,reg) \
152 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
153 #define AT_READ_2(sc,reg) \
154 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
155 #define AT_READ_1(sc,reg) \
156 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
157 #define AT_WRITE_4(sc,reg,val) \
158 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
159 #define AT_WRITE_2(sc,reg,val) \
160 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
161 #define AT_WRITE_1(sc,reg,val) \
162 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
163 #else
164 static inline uint32_t
165 AT_READ_4(struct lii_softc *sc, bus_size_t reg)
166 {
167 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
168 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r);
169 return r;
170 }
171
172 static inline uint16_t
173 AT_READ_2(struct lii_softc *sc, bus_size_t reg)
174 {
175 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg);
176 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r);
177 return r;
178 }
179
180 static inline uint8_t
181 AT_READ_1(struct lii_softc *sc, bus_size_t reg)
182 {
183 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg);
184 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r);
185 return r;
186 }
187
188 static inline void
189 AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val)
190 {
191 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val);
192 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val);
193 }
194
195 static inline void
196 AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val)
197 {
198 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val);
199 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val);
200 }
201
202 static inline void
203 AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val)
204 {
205 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val);
206 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val);
207 }
208 #endif
209
210 /*
211 * Those are the default Linux parameters.
212 */
213
214 #define AT_TXD_NUM 64
215 #define AT_TXD_BUFFER_SIZE 8192
216 #define AT_RXD_NUM 64
217
218 /*
219 * Assuming (you know what that word makes of you) the chunk of memory
220 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the
221 * first 120 bytes of it, so that the space for the packets, and not the
222 * whole descriptors themselves, are on a 128-byte boundary.
223 */
224
225 #define AT_RXD_PADDING 120
226
227 static int
228 lii_match(device_t parent, cfdata_t cfmatch, void *aux)
229 {
230 struct pci_attach_args *pa = aux;
231
232 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC &&
233 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100);
234 }
235
236 static void
237 lii_attach(device_t parent, device_t self, void *aux)
238 {
239 struct lii_softc *sc = device_private(self);
240 struct pci_attach_args *pa = aux;
241 uint8_t eaddr[ETHER_ADDR_LEN];
242 struct ifnet *ifp = &sc->sc_ec.ec_if;
243 pci_intr_handle_t ih;
244 const char *intrstr;
245 pcireg_t cmd;
246
247 aprint_naive("\n");
248 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n");
249
250 sc->sc_dev = self;
251 sc->sc_pc = pa->pa_pc;
252 sc->sc_tag = pa->pa_tag;
253 sc->sc_dmat = pa->pa_dmat;
254
255 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
256 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
257 cmd &= ~PCI_COMMAND_IO_ENABLE;
258 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd);
259
260 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) {
261 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
262 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M:
263 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
264 break;
265 default:
266 aprint_error_dev(self, "invalid base address register\n");
267 break;
268 }
269 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0,
270 &sc->sc_mmiot, &sc->sc_mmioh, NULL, NULL) != 0) {
271 aprint_error_dev(self, "failed to map registers\n");
272 return;
273 }
274
275 if (lii_reset(sc))
276 return;
277
278 lii_spi_configure(sc);
279
280 if (lii_eeprom_present(sc))
281 sc->sc_memread = lii_eeprom_read;
282 else
283 sc->sc_memread = lii_spi_read;
284
285 if (lii_read_macaddr(sc, eaddr))
286 return;
287 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN);
288
289 aprint_normal_dev(self, "Ethernet address %s\n",
290 ether_sprintf(eaddr));
291
292 if (pci_intr_map(pa, &ih) != 0) {
293 aprint_error_dev(self, "failed to map interrupt\n");
294 return;
295 }
296 intrstr = pci_intr_string(sc->sc_pc, ih);
297 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc);
298 if (sc->sc_ih == NULL) {
299 aprint_error_dev(self, "failed to establish interrupt");
300 if (intrstr != NULL)
301 aprint_error(" at %s", intrstr);
302 aprint_error("\n");
303 return;
304 }
305 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
306
307 if (lii_alloc_rings(sc)) {
308 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
309 return;
310 }
311
312 callout_init(&sc->sc_tick_ch, 0);
313 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc);
314
315 sc->sc_mii.mii_ifp = ifp;
316 sc->sc_mii.mii_readreg = lii_mii_readreg;
317 sc->sc_mii.mii_writereg = lii_mii_writereg;
318 sc->sc_mii.mii_statchg = lii_mii_statchg;
319 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change,
320 lii_media_status);
321 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
322 MII_OFFSET_ANY, 0);
323 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
324
325 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
326 ifp->if_softc = sc;
327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
328 ifp->if_ioctl = lii_ioctl;
329 ifp->if_start = lii_start;
330 ifp->if_watchdog = lii_watchdog;
331 ifp->if_init = lii_init;
332 ifp->if_stop = lii_stop;
333 IFQ_SET_READY(&ifp->if_snd);
334
335 /*
336 * While the device does support HW VLAN tagging, there is no
337 * real point using that feature.
338 */
339 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
340
341 if_attach(ifp);
342 ether_ifattach(ifp, eaddr);
343
344 if (!pmf_device_register(self, NULL, NULL))
345 aprint_error_dev(self, "couldn't establish power handler\n");
346 else
347 pmf_class_network_register(self, ifp);
348
349 return;
350 }
351
352 static int
353 lii_reset(struct lii_softc *sc)
354 {
355 int i;
356
357 DPRINTF(("lii_reset\n"));
358
359 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST);
360 DELAY(1000);
361
362 for (i = 0; i < 10; ++i) {
363 if (AT_READ_4(sc, ATL2_BIS) == 0)
364 break;
365 DELAY(1000);
366 }
367
368 if (i == 10) {
369 aprint_error_dev(sc->sc_dev, "reset failed\n");
370 return 1;
371 }
372
373 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE);
374 DELAY(10);
375
376 /* Init PCI-Express module */
377 /* Magic Numbers Warning */
378 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF);
379 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF);
380
381 return 0;
382 }
383
384 static bool
385 lii_eeprom_present(struct lii_softc *sc)
386 {
387 /*
388 * The Linux driver does this, but then it has a very weird way of
389 * checking whether the PCI configuration space exposes the Vital
390 * Product Data capability, so maybe it's not really needed.
391 */
392
393 #ifdef weirdloonix
394 uint32_t val;
395
396 val = AT_READ_4(sc, ATL2_SFC);
397 if (val & SFC_EN_VPD)
398 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD));
399 #endif
400
401 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD,
402 NULL, NULL) == 1;
403 }
404
405 static int
406 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
407 {
408 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val);
409
410 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val));
411
412 return r;
413 }
414
415 static void
416 lii_spi_configure(struct lii_softc *sc)
417 {
418 /*
419 * We don't offer a way to configure the SPI Flash vendor parameter, so
420 * the table is given for reference
421 */
422 static const struct lii_spi_flash_vendor {
423 const char *sfv_name;
424 const uint8_t sfv_opcodes[9];
425 } lii_sfv[] = {
426 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } },
427 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } },
428 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } },
429 };
430 #define SF_OPCODE_WRSR 0
431 #define SF_OPCODE_READ 1
432 #define SF_OPCODE_PRGM 2
433 #define SF_OPCODE_WREN 3
434 #define SF_OPCODE_WRDI 4
435 #define SF_OPCODE_RDSR 5
436 #define SF_OPCODE_RDID 6
437 #define SF_OPCODE_SECT_ER 7
438 #define SF_OPCODE_CHIP_ER 8
439
440 #define SF_DEFAULT_VENDOR 0
441 static const uint8_t vendor = SF_DEFAULT_VENDOR;
442
443 /*
444 * Why isn't WRDI used? Heck if I know.
445 */
446
447 AT_WRITE_1(sc, ATL2_SFOP_WRSR,
448 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]);
449 AT_WRITE_1(sc, ATL2_SFOP_READ,
450 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]);
451 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM,
452 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]);
453 AT_WRITE_1(sc, ATL2_SFOP_WREN,
454 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]);
455 AT_WRITE_1(sc, ATL2_SFOP_RDSR,
456 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]);
457 AT_WRITE_1(sc, ATL2_SFOP_RDID,
458 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]);
459 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE,
460 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]);
461 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE,
462 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]);
463 }
464
465 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \
466 ( (((cssetup) & SFC_CS_SETUP_MASK) \
467 << SFC_CS_SETUP_SHIFT) \
468 | (((clkhi) & SFC_CLK_HI_MASK) \
469 << SFC_CLK_HI_SHIFT) \
470 | (((clklo) & SFC_CLK_LO_MASK) \
471 << SFC_CLK_LO_SHIFT) \
472 | (((cshold) & SFC_CS_HOLD_MASK) \
473 << SFC_CS_HOLD_SHIFT) \
474 | (((cshi) & SFC_CS_HI_MASK) \
475 << SFC_CS_HI_SHIFT) \
476 | (((ins) & SFC_INS_MASK) \
477 << SFC_INS_SHIFT))
478
479 /* Magic settings from the Linux driver */
480
481 #define CUSTOM_SPI_CS_SETUP 2
482 #define CUSTOM_SPI_CLK_HI 2
483 #define CUSTOM_SPI_CLK_LO 2
484 #define CUSTOM_SPI_CS_HOLD 2
485 #define CUSTOM_SPI_CS_HI 3
486
487 static int
488 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
489 {
490 uint32_t v;
491 int i;
492
493 AT_WRITE_4(sc, ATL2_SF_DATA, 0);
494 AT_WRITE_4(sc, ATL2_SF_ADDR, reg);
495
496 v = SFC_WAIT_READY |
497 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI,
498 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1);
499
500 AT_WRITE_4(sc, ATL2_SFC, v);
501 v |= SFC_START;
502 AT_WRITE_4(sc, ATL2_SFC, v);
503
504 for (i = 0; i < 10; ++i) {
505 DELAY(1000);
506 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START))
507 break;
508 }
509 if (i == 10)
510 return EBUSY;
511
512 *val = AT_READ_4(sc, ATL2_SF_DATA);
513 return 0;
514 }
515
516 static int
517 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea)
518 {
519 uint32_t offset = 0x100;
520 uint32_t val, val1, addr0 = 0, addr1 = 0;
521 uint8_t found = 0;
522
523 while ((*sc->sc_memread)(sc, offset, &val) == 0) {
524 offset += 4;
525
526 /* Each chunk of data starts with a signature */
527 if ((val & 0xff) != 0x5a)
528 break;
529 if ((*sc->sc_memread)(sc, offset, &val1))
530 break;
531
532 offset += 4;
533
534 val >>= 16;
535 switch (val) {
536 case ATL2_MAC_ADDR_0:
537 addr0 = val1;
538 ++found;
539 break;
540 case ATL2_MAC_ADDR_1:
541 addr1 = val1;
542 ++found;
543 break;
544 default:
545 continue;
546 }
547 }
548
549 if (found < 2) {
550 /* Make sure we try the BIOS method before giving up */
551 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0));
552 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1));
553 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) ||
554 (addr0 == 0 && (addr1 & 0xffff) == 0)) {
555 aprint_error_dev(sc->sc_dev,
556 "error reading MAC address\n");
557 return 1;
558 }
559 } else {
560 addr0 = htole32(addr0);
561 addr1 = htole32(addr1);
562 }
563
564 ea[0] = (addr1 & 0x0000ff00) >> 8;
565 ea[1] = (addr1 & 0x000000ff);
566 ea[2] = (addr0 & 0xff000000) >> 24;
567 ea[3] = (addr0 & 0x00ff0000) >> 16;
568 ea[4] = (addr0 & 0x0000ff00) >> 8;
569 ea[5] = (addr0 & 0x000000ff);
570
571 return 0;
572 }
573
574 static int
575 lii_mii_readreg(device_t dev, int phy, int reg)
576 {
577 struct lii_softc *sc = device_private(dev);
578 uint32_t val;
579 int i;
580
581 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
582
583 val |= MDIOC_START | MDIOC_SUP_PREAMBLE;
584 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
585
586 val |= MDIOC_READ;
587
588 AT_WRITE_4(sc, ATL2_MDIOC, val);
589
590 for (i = 0; i < MDIO_WAIT_TIMES; ++i) {
591 DELAY(2);
592 val = AT_READ_4(sc, ATL2_MDIOC);
593 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0)
594 break;
595 }
596
597 if (i == MDIO_WAIT_TIMES)
598 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy,
599 reg);
600
601 return (val & 0x0000ffff);
602 }
603
604 static void
605 lii_mii_writereg(device_t dev, int phy, int reg, int data)
606 {
607 struct lii_softc *sc = device_private(dev);
608 uint32_t val;
609 int i;
610
611 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
612 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT;
613
614 val |= MDIOC_START | MDIOC_SUP_PREAMBLE;
615 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
616
617 /* val |= MDIOC_WRITE; */
618
619 AT_WRITE_4(sc, ATL2_MDIOC, val);
620
621 for (i = 0; i < MDIO_WAIT_TIMES; ++i) {
622 DELAY(2);
623 val = AT_READ_4(sc, ATL2_MDIOC);
624 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0)
625 break;
626 }
627
628 if (i == MDIO_WAIT_TIMES)
629 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy,
630 reg);
631 }
632
633 static void
634 lii_mii_statchg(device_t dev)
635 {
636 struct lii_softc *sc = device_private(dev);
637 uint32_t val;
638
639 DPRINTF(("lii_mii_statchg\n"));
640
641 val = AT_READ_4(sc, ATL2_MACC);
642
643 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX)
644 val |= MACC_FDX;
645 else
646 val &= ~MACC_FDX;
647
648 AT_WRITE_4(sc, ATL2_MACC, val);
649 }
650
651 static int
652 lii_media_change(struct ifnet *ifp)
653 {
654 struct lii_softc *sc = ifp->if_softc;
655
656 DPRINTF(("lii_media_change\n"));
657
658 if (ifp->if_flags & IFF_UP)
659 mii_mediachg(&sc->sc_mii);
660 return 0;
661 }
662
663 static void
664 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr)
665 {
666 struct lii_softc *sc = ifp->if_softc;
667
668 DPRINTF(("lii_media_status\n"));
669
670 mii_pollstat(&sc->sc_mii);
671 imr->ifm_status = sc->sc_mii.mii_media_status;
672 imr->ifm_active = sc->sc_mii.mii_media_active;
673 }
674
675 static int
676 lii_init(struct ifnet *ifp)
677 {
678 struct lii_softc *sc = ifp->if_softc;
679 uint32_t val;
680 int error;
681
682 DPRINTF(("lii_init\n"));
683
684 lii_stop(ifp, 0);
685
686 memset(sc->sc_ring, 0, sc->sc_ringsize);
687
688 /* Disable all interrupts */
689 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff);
690
691 /* XXX endianness */
692 AT_WRITE_4(sc, ATL2_MAC_ADDR_0,
693 sc->sc_eaddr[2] << 24 |
694 sc->sc_eaddr[3] << 16 |
695 sc->sc_eaddr[4] << 8 |
696 sc->sc_eaddr[5]);
697 AT_WRITE_4(sc, ATL2_MAC_ADDR_1,
698 sc->sc_eaddr[0] << 8 |
699 sc->sc_eaddr[1]);
700
701 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0);
702 /* XXX
703 sc->sc_ringmap->dm_segs[0].ds_addr >> 32);
704 */
705 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO,
706 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff)
707 + AT_RXD_PADDING);
708 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO,
709 sc->sc_txsp & 0xffffffff);
710 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO,
711 sc->sc_txdp & 0xffffffff);
712
713 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4);
714 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM);
715 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM);
716
717 /*
718 * Inter Paket Gap Time = 0x60 (IPGT)
719 * Minimum inter-frame gap for RX = 0x50 (MIFG)
720 * 64-bit Carrier-Sense window = 0x40 (IPGR1)
721 * 96-bit IPG window = 0x60 (IPGR2)
722 */
723 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060);
724
725 /*
726 * Collision window = 0x37 (LCOL)
727 * Maximum # of retrans = 0xf (RETRY)
728 * Maximum binary expansion # = 0xa (ABEBT)
729 * IPG to start jam = 0x7 (JAMIPG)
730 */
731 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 |
732 MHDC_EXC_DEF_EN);
733
734 /* 100 means 200us */
735 AT_WRITE_2(sc, ATL2_IMTIV, 100);
736 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN);
737
738 /* 500000 means 100ms */
739 AT_WRITE_2(sc, ATL2_IALTIV, 50000);
740
741 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN
742 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
743
744 /* unit unknown for TX cur-through threshold */
745 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177);
746
747 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8);
748 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12);
749
750 sc->sc_rxcur = 0;
751 sc->sc_txs_cur = sc->sc_txs_ack = 0;
752 sc->sc_txd_cur = sc->sc_txd_ack = 0;
753 sc->sc_free_tx_slots = true;
754 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur);
755 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
756
757 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN);
758 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN);
759
760 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT);
761
762 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0);
763 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff);
764 AT_WRITE_4(sc, ATL2_ISR, 0);
765 if (error) {
766 aprint_error_dev(sc->sc_dev, "init failed\n");
767 goto out;
768 }
769
770 lii_setmulti(sc);
771
772 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX;
773
774 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY |
775 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN |
776 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN;
777
778 if (ifp->if_flags & IFF_PROMISC)
779 val |= MACC_PROMISC_EN;
780 else if (ifp->if_flags & IFF_ALLMULTI)
781 val |= MACC_ALLMULTI_EN;
782
783 val |= 7 << MACC_PREAMBLE_LEN_SHIFT;
784 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT;
785
786 AT_WRITE_4(sc, ATL2_MACC, val);
787
788 mii_mediachg(&sc->sc_mii);
789
790 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK);
791
792 callout_schedule(&sc->sc_tick_ch, hz);
793
794 ifp->if_flags |= IFF_RUNNING;
795 ifp->if_flags &= ~IFF_OACTIVE;
796
797 out:
798 return error;
799 }
800
801 static void
802 lii_tx_put(struct lii_softc *sc, struct mbuf *m)
803 {
804 int left;
805 struct tx_pkt_header *tph =
806 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur);
807
808 memset(tph, 0, sizeof *tph);
809 tph->txph_size = m->m_pkthdr.len;
810
811 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE;
812
813 /*
814 * We already know we have enough space, so if there is a part of the
815 * space ahead of txd_cur that is active, it doesn't matter because
816 * left will be large enough even without it.
817 */
818 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur;
819
820 if (left > m->m_pkthdr.len) {
821 m_copydata(m, 0, m->m_pkthdr.len,
822 sc->sc_txdbase + sc->sc_txd_cur);
823 sc->sc_txd_cur += m->m_pkthdr.len;
824 } else {
825 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur);
826 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase);
827 sc->sc_txd_cur = m->m_pkthdr.len - left;
828 }
829
830 /* Round to a 32-bit boundary */
831 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE;
832 if (sc->sc_txd_cur == sc->sc_txd_ack)
833 sc->sc_free_tx_slots = false;
834 }
835
836 static int
837 lii_free_tx_space(struct lii_softc *sc)
838 {
839 int space;
840
841 if (sc->sc_txd_cur >= sc->sc_txd_ack)
842 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) +
843 sc->sc_txd_ack;
844 else
845 space = sc->sc_txd_ack - sc->sc_txd_cur;
846
847 /* Account for the tx_pkt_header */
848 return (space - 4);
849 }
850
851 static void
852 lii_start(struct ifnet *ifp)
853 {
854 struct lii_softc *sc = ifp->if_softc;
855 struct mbuf *m0;
856
857 DPRINTF(("lii_start\n"));
858
859 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
860 return;
861
862 for (;;) {
863 IFQ_POLL(&ifp->if_snd, m0);
864 if (m0 == NULL)
865 break;
866
867 if (!sc->sc_free_tx_slots ||
868 lii_free_tx_space(sc) < m0->m_pkthdr.len) {
869 ifp->if_flags |= IFF_OACTIVE;
870 break;
871 }
872
873 lii_tx_put(sc, m0);
874
875 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur));
876
877 sc->sc_txs[sc->sc_txs_cur].txps_update = 0;
878 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM;
879 if (sc->sc_txs_cur == sc->sc_txs_ack)
880 sc->sc_free_tx_slots = false;
881
882 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4);
883
884 IFQ_DEQUEUE(&ifp->if_snd, m0);
885
886 #if NBPFILTER > 0
887 if (ifp->if_bpf != NULL)
888 bpf_mtap(ifp->if_bpf, m0);
889 #endif
890 m_freem(m0);
891 }
892 }
893
894 static void
895 lii_stop(struct ifnet *ifp, int disable)
896 {
897 struct lii_softc *sc = ifp->if_softc;
898
899 callout_stop(&sc->sc_tick_ch);
900
901 ifp->if_timer = 0;
902 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
903
904 mii_down(&sc->sc_mii);
905
906 lii_reset(sc);
907
908 AT_WRITE_4(sc, ATL2_IMR, 0);
909 }
910
911 static int
912 lii_intr(void *v)
913 {
914 struct lii_softc *sc = v;
915 uint32_t status;
916
917 status = AT_READ_4(sc, ATL2_ISR);
918 if (status == 0)
919 return 0;
920
921 DPRINTF(("lii_intr (%x)\n", status));
922
923 /* Clear the interrupt and disable them */
924 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT);
925
926 if (status & (ISR_PHY | ISR_MANUAL)) {
927 /* Ack PHY interrupt. Magic register */
928 if (status & ISR_PHY)
929 (void)lii_mii_readreg(sc->sc_dev, 1, 19);
930 mii_mediachg(&sc->sc_mii);
931 }
932
933 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) {
934 lii_init(&sc->sc_ec.ec_if);
935 return 1;
936 }
937
938 if (status & ISR_RX_EVENT) {
939 #ifdef LII_DEBUG
940 if (!(status & ISR_RS_UPDATE))
941 printf("rxintr %08x\n", status);
942 #endif
943 lii_rxintr(sc);
944 }
945
946 if (status & ISR_TX_EVENT)
947 lii_txintr(sc);
948
949 /* Re-enable interrupts */
950 AT_WRITE_4(sc, ATL2_ISR, 0);
951
952 return 1;
953 }
954
955 static void
956 lii_rxintr(struct lii_softc *sc)
957 {
958 struct ifnet *ifp = &sc->sc_ec.ec_if;
959 struct rx_pkt *rxp;
960 struct mbuf *m;
961 uint16_t size;
962
963 DPRINTF(("lii_rxintr\n"));
964
965 for (;;) {
966 rxp = &sc->sc_rxp[sc->sc_rxcur];
967 if (rxp->rxp_update == 0)
968 break;
969
970 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur,
971 rxp->rxp_size, rxp->rxp_flags));
972 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM;
973 rxp->rxp_update = 0;
974 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) {
975 ++ifp->if_ierrors;
976 continue;
977 }
978
979 MGETHDR(m, M_DONTWAIT, MT_DATA);
980 if (m == NULL) {
981 ++ifp->if_ierrors;
982 continue;
983 }
984 size = rxp->rxp_size - ETHER_CRC_LEN;
985 if (size > MHLEN) {
986 MCLGET(m, M_DONTWAIT);
987 if ((m->m_flags & M_EXT) == 0) {
988 m_freem(m);
989 ++ifp->if_ierrors;
990 continue;
991 }
992 }
993
994 m->m_pkthdr.rcvif = ifp;
995 /* Copy the packet withhout the FCS */
996 m->m_pkthdr.len = m->m_len = size;
997 memcpy(mtod(m, void *), &rxp->rxp_data[0], size);
998 ++ifp->if_ipackets;
999
1000 #if NBPFILTER > 0
1001 if (ifp->if_bpf)
1002 bpf_mtap(ifp->if_bpf, m);
1003 #endif
1004
1005 (*ifp->if_input)(ifp, m);
1006 }
1007
1008 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
1009 }
1010
1011 static void
1012 lii_txintr(struct lii_softc *sc)
1013 {
1014 struct ifnet *ifp = &sc->sc_ec.ec_if;
1015 struct tx_pkt_status *txs;
1016 struct tx_pkt_header *txph;
1017
1018 DPRINTF(("lii_txintr\n"));
1019
1020 for (;;) {
1021 txs = &sc->sc_txs[sc->sc_txs_ack];
1022 if (txs->txps_update == 0)
1023 break;
1024 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack));
1025 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM;
1026 sc->sc_free_tx_slots = true;
1027
1028 txs->txps_update = 0;
1029
1030 txph = (struct tx_pkt_header *)
1031 (sc->sc_txdbase + sc->sc_txd_ack);
1032
1033 if (txph->txph_size != txs->txps_size)
1034 aprint_error_dev(sc->sc_dev,
1035 "mismatched status and packet\n");
1036 /*
1037 * Move ack by the packet size, taking the packet header in
1038 * account and round to the next 32-bit boundary
1039 * (7 = sizeof(header) + 3)
1040 */
1041 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3;
1042 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE;
1043
1044 if (txs->txps_flags & ATL2_TXF_SUCCESS)
1045 ++ifp->if_opackets;
1046 else
1047 ++ifp->if_oerrors;
1048 ifp->if_flags &= ~IFF_OACTIVE;
1049 }
1050
1051 if (sc->sc_free_tx_slots)
1052 lii_start(ifp);
1053 }
1054
1055 static int
1056 lii_alloc_rings(struct lii_softc *sc)
1057 {
1058 int nsegs;
1059 bus_size_t bs;
1060
1061 /*
1062 * We need a big chunk of DMA-friendly memory because descriptors
1063 * are not separate from data on that crappy hardware, which means
1064 * we'll have to copy data from and to that memory zone to and from
1065 * the mbufs.
1066 *
1067 * How lame is that? Using the default values from the Linux driver,
1068 * we allocate space for receiving up to 64 full-size Ethernet frames,
1069 * and only 8kb for transmitting up to 64 Ethernet frames.
1070 */
1071
1072 sc->sc_ringsize = bs = AT_RXD_PADDING
1073 + AT_RXD_NUM * sizeof(struct rx_pkt)
1074 + AT_TXD_NUM * sizeof(struct tx_pkt_status)
1075 + AT_TXD_BUFFER_SIZE;
1076
1077 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30),
1078 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) {
1079 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n");
1080 return 1;
1081 }
1082
1083 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30),
1084 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) {
1085 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n");
1086 goto fail;
1087 }
1088
1089 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs,
1090 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) {
1091 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n");
1092 goto fail1;
1093 }
1094
1095 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring,
1096 bs, NULL, BUS_DMA_NOWAIT) != 0) {
1097 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n");
1098 goto fail2;
1099 }
1100
1101 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING);
1102 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING
1103 + AT_RXD_NUM * sizeof(struct rx_pkt));
1104 sc->sc_txdbase = ((char *)sc->sc_txs)
1105 + AT_TXD_NUM * sizeof(struct tx_pkt_status);
1106 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr
1107 + ((char *)sc->sc_txs - (char *)sc->sc_ring);
1108 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr
1109 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring);
1110
1111 return 0;
1112
1113 fail2:
1114 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs);
1115 fail1:
1116 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs);
1117 fail:
1118 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap);
1119 return 1;
1120 }
1121
1122 static void
1123 lii_watchdog(struct ifnet *ifp)
1124 {
1125 struct lii_softc *sc = ifp->if_softc;
1126
1127 aprint_error_dev(sc->sc_dev, "watchdog timeout\n");
1128 ++ifp->if_oerrors;
1129 lii_init(ifp);
1130 }
1131
1132 static int
1133 lii_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1134 {
1135 struct lii_softc *sc = ifp->if_softc;
1136 int s, error;
1137
1138 s = splnet();
1139
1140 switch(cmd) {
1141 case SIOCADDMULTI:
1142 case SIOCDELMULTI:
1143 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
1144 if (ifp->if_flags & IFF_RUNNING)
1145 lii_setmulti(sc);
1146 error = 0;
1147 }
1148 break;
1149 case SIOCSIFMEDIA:
1150 case SIOCGIFMEDIA:
1151 error = ifmedia_ioctl(ifp, (struct ifreq *)data,
1152 &sc->sc_mii.mii_media, cmd);
1153 break;
1154 default:
1155 error = ether_ioctl(ifp, cmd, data);
1156 if (error == ENETRESET) {
1157 if (ifp->if_flags & IFF_RUNNING)
1158 lii_setmulti(sc);
1159 error = 0;
1160 }
1161 break;
1162 }
1163
1164 splx(s);
1165
1166 return error;
1167 }
1168
1169 static void
1170 lii_setmulti(struct lii_softc *sc)
1171 {
1172 struct ethercom *ec = &sc->sc_ec;
1173 struct ifnet *ifp = &ec->ec_if;
1174 uint32_t mht0 = 0, mht1 = 0, crc;
1175 struct ether_multi *enm;
1176 struct ether_multistep step;
1177
1178 /* Clear multicast hash table */
1179 AT_WRITE_4(sc, ATL2_MHT, 0);
1180 AT_WRITE_4(sc, ATL2_MHT + 4, 0);
1181
1182 ifp->if_flags &= ~IFF_ALLMULTI;
1183
1184 ETHER_FIRST_MULTI(step, ec, enm);
1185 while (enm != NULL) {
1186 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1187 ifp->if_flags |= IFF_ALLMULTI;
1188 mht0 = mht1 = 0;
1189 goto alldone;
1190 }
1191
1192 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
1193
1194 if (crc & (1 << 31))
1195 mht1 |= (1 << ((crc >> 26) & 0x0000001f));
1196 else
1197 mht0 |= (1 << ((crc >> 26) & 0x0000001f));
1198
1199 ETHER_NEXT_MULTI(step, enm);
1200 }
1201
1202 alldone:
1203 AT_WRITE_4(sc, ATL2_MHT, mht0);
1204 AT_WRITE_4(sc, ATL2_MHT+4, mht1);
1205 }
1206
1207 static void
1208 lii_tick(void *v)
1209 {
1210 struct lii_softc *sc = v;
1211 int s;
1212
1213 s = splnet();
1214 mii_tick(&sc->sc_mii);
1215 splx(s);
1216
1217 callout_schedule(&sc->sc_tick_ch, hz);
1218 }
1219