1 1.2 martin /* $NetBSD: if_liireg.h,v 1.2 2008/04/29 06:53:03 martin Exp $ */ 2 1.1 cube 3 1.1 cube /* 4 1.1 cube * Copyright (c) 2008 The NetBSD Foundation. 5 1.1 cube * All rights reserved. 6 1.1 cube * 7 1.1 cube * Redistribution and use in source and binary forms, with or without 8 1.1 cube * modification, are permitted provided that the following conditions 9 1.1 cube * are met: 10 1.1 cube * 1. Redistributions of source code must retain the above copyright 11 1.1 cube * notice, this list of conditions and the following disclaimer. 12 1.1 cube * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 cube * notice, this list of conditions and the following disclaimer in the 14 1.1 cube * documentation and/or other materials provided with the distribution. 15 1.1 cube * 16 1.1 cube * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 1.1 cube * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.1 cube * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1 cube * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 1.1 cube * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.1 cube * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.1 cube * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.1 cube * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.1 cube * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.1 cube * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1 cube * POSSIBILITY OF SUCH DAMAGE. 27 1.1 cube */ 28 1.1 cube 29 1.1 cube /* 30 1.1 cube * PCI configuration space seems to be mapped in the first 0x100 bytes of 31 1.1 cube * the register area. 32 1.1 cube */ 33 1.1 cube 34 1.1 cube /* SPI Flash Control register */ 35 1.1 cube #define ATL2_SFC 0x0200 36 1.1 cube #define SFC_STS_NON_RDY 0x00000001 37 1.1 cube #define SFC_STS_WEN 0x00000002 38 1.1 cube #define SFC_STS_WPEN 0x00000080 39 1.1 cube #define SFC_DEV_STS_MASK 0x000000ff 40 1.1 cube #define SFC_DEV_STS_SHIFT 0 41 1.1 cube #define SFC_INS_MASK 0x07 42 1.1 cube #define SFC_INS_SHIFT 8 43 1.1 cube #define SFC_START 0x00000800 44 1.1 cube #define SFC_EN_VPD 0x00002000 45 1.1 cube #define SFC_LDSTART 0x00008000 46 1.1 cube #define SFC_CS_HI_MASK 0x03 47 1.1 cube #define SFC_CS_HI_SHIFT 16 48 1.1 cube #define SFC_CS_HOLD_MASK 0x03 49 1.1 cube #define SFC_CS_HOLD_SHIFT 18 50 1.1 cube #define SFC_CLK_LO_MASK 0x03 51 1.1 cube #define SFC_CLK_LO_SHIFT 20 52 1.1 cube #define SFC_CLK_HI_MASK 0x03 53 1.1 cube #define SFC_CLK_HI_SHIFT 22 54 1.1 cube #define SFC_CS_SETUP_MASK 0x03 55 1.1 cube #define SFC_CS_SETUP_SHIFT 24 56 1.1 cube #define SFC_EROMPGSZ_MASK 0x03 57 1.1 cube #define SFC_EROMPGSZ_SHIFT 26 58 1.1 cube #define SFC_WAIT_READY 0x10000000 59 1.1 cube 60 1.1 cube /* SPI Flash Address register */ 61 1.1 cube #define ATL2_SF_ADDR 0x0204 62 1.1 cube 63 1.1 cube /* SPI Flash Data register */ 64 1.1 cube #define ATL2_SF_DATA 0x0208 65 1.1 cube 66 1.1 cube /* SPI Flash Configuration register */ 67 1.1 cube #define ATL2_SFCF 0x020c 68 1.1 cube #define SFCF_LD_ADDR_MASK 0x00ffffff 69 1.1 cube #define SFCF_LD_ADDR_SHIFT 0 70 1.1 cube #define SFCF_VPD_ADDR_MASK 0x03 71 1.1 cube #define SFCF_VPD_ADDR_SHIFT 24 72 1.1 cube #define SFCF_LD_EXISTS 0x04000000 73 1.1 cube 74 1.1 cube /* SPI Flash op codes programmation registers */ 75 1.1 cube #define ATL2_SFOP_PROGRAM 0x0210 76 1.1 cube #define ATL2_SFOP_SC_ERASE 0x0211 77 1.1 cube #define ATL2_SFOP_CHIP_ERASE 0x0212 78 1.1 cube #define ATL2_SFOP_RDID 0x0213 79 1.1 cube #define ATL2_SFOP_WREN 0x0214 80 1.1 cube #define ATL2_SFOP_RDSR 0x0215 81 1.1 cube #define ATL2_SFOP_WRSR 0x0216 82 1.1 cube #define ATL2_SFOP_READ 0x0217 83 1.1 cube 84 1.1 cube /* TWSI Control register, whatever that is */ 85 1.1 cube #define ATL2_TWSIC 0x0218 86 1.1 cube #define TWSIC_LD_OFFSET_MASK 0x000000ff 87 1.1 cube #define TWSIC_LD_OFFSET_SHIFT 0 88 1.1 cube #define TWSIC_LD_SLV_ADDR_MASK 0x07 89 1.1 cube #define TWSIC_LD_SLV_ADDR_SHIFT 8 90 1.1 cube #define TWSIC_SW_LDSTART 0x00000800 91 1.1 cube #define TWSIC_HW_LDSTART 0x00001000 92 1.1 cube #define TWSIC_SMB_SLV_ADDR_MASK 0x7F 93 1.1 cube #define TWSIC_SMB_SLV_ADDR_SHIFT 15 94 1.1 cube #define TWSIC_LD_EXIST 0x00400000 95 1.1 cube #define TWSIC_READ_FREQ_SEL_MASK 0x03 96 1.1 cube #define TWSIC_READ_FREQ_SEL_SHIFT 23 97 1.1 cube #define TWSIC_FREQ_SEL_100K 0 98 1.1 cube #define TWSIC_FREQ_SEL_200K 1 99 1.1 cube #define TWSIC_FREQ_SEL_300K 2 100 1.1 cube #define TWSIC_FREQ_SEL_400K 3 101 1.1 cube #define TWSIC_WRITE_FREQ_SEL_MASK 0x03 102 1.1 cube #define TWSIC_WRITE_FREQ_SEL_SHIFT 24 103 1.1 cube 104 1.1 cube /* PCI-Express Device Misc. Control register? (size unknown) */ 105 1.1 cube #define ATL2_PCEDMC 0x021c 106 1.1 cube #define PCEDMC_RETRY_BUFDIS 0x01 107 1.1 cube #define PCEDMC_EXT_PIPE 0x02 108 1.1 cube #define PCEDMC_SPIROM_EXISTS 0x04 109 1.1 cube #define PCEDMC_SERDES_ENDIAN 0x08 110 1.1 cube #define PCEDMC_SERDES_SEL_DIN 0x10 111 1.1 cube 112 1.1 cube /* PCI-Express PHY Miscellaneous register (size unknown) */ 113 1.1 cube #define ATL2_PCEPM 0x1000 114 1.1 cube #define PCEPM_FORCE_RCV_DET 0x04 115 1.1 cube 116 1.1 cube /* PCI-Express DLL TX Control register */ 117 1.1 cube #define ATL2_PCEDTXC 0x1104 118 1.1 cube #define PCEDTX_SEL_NOR_CLK 0x00000400 119 1.1 cube #define PCEDTX_DEF 0x00000568 120 1.1 cube 121 1.1 cube /* PCI-Express-related register (LTSSM test mode) */ 122 1.1 cube #define ATL2_PCELTM 0x12fc 123 1.1 cube #define PCELTM_DEF 0x00006500 124 1.1 cube 125 1.1 cube /* Selene Master Control register */ 126 1.1 cube #define ATL2_SMC 0x1400 127 1.1 cube #define SMC_SOFT_RST 0x00000001 128 1.1 cube #define SMC_MTIMER_EN 0x00000002 129 1.1 cube #define SMC_ITIMER_EN 0x00000004 130 1.1 cube #define SMC_MANUAL_INT 0x00000008 131 1.1 cube #define SMC_REV_NUM_MASK 0xff 132 1.1 cube #define SMC_REV_NUM_SHIFT 16 133 1.1 cube #define SMC_DEV_ID_MASK 0xff 134 1.1 cube #define SMC_DEV_ID_SHIFT 24 135 1.1 cube 136 1.1 cube /* Timer Initial Value register */ 137 1.1 cube #define ATL2_TIV 0x1404 138 1.1 cube 139 1.1 cube /* IRQ Moderator Timer Initial Value register */ 140 1.1 cube #define ATL2_IMTIV 0x1408 141 1.1 cube 142 1.1 cube /* PHY Control register */ 143 1.1 cube #define ATL2_PHYC 0x140c 144 1.1 cube #define PHYC_ENABLE 0x0001 145 1.1 cube 146 1.1 cube /* IRQ Anti-Lost Timer Initial Value register 147 1.1 cube --> Time allowed for software to clear the interrupt */ 148 1.1 cube #define ATL2_IALTIV 0x140e 149 1.1 cube 150 1.1 cube /* Block Idle Status register 151 1.1 cube --> Bit set if matching state machine is not idle */ 152 1.1 cube #define ATL2_BIS 0x1410 153 1.1 cube #define BIS_RXMAC 0x00000001 154 1.1 cube #define BIS_TXMAC 0x00000002 155 1.1 cube #define BIS_DMAR 0x00000004 156 1.1 cube #define BIS_DMAW 0x00000008 157 1.1 cube 158 1.1 cube /* MDIO Control register */ 159 1.1 cube #define ATL2_MDIOC 0x1414 160 1.1 cube #define MDIOC_DATA_MASK 0x0000ffff 161 1.1 cube #define MDIOC_DATA_SHIFT 0 162 1.1 cube #define MDIOC_REG_MASK 0x1f 163 1.1 cube #define MDIOC_REG_SHIFT 16 164 1.1 cube #define MDIOC_WRITE 0x00000000 165 1.1 cube #define MDIOC_READ 0x00200000 166 1.1 cube #define MDIOC_SUP_PREAMBLE 0x00400000 167 1.1 cube #define MDIOC_START 0x00800000 168 1.1 cube #define MDIOC_CLK_SEL_MASK 0x07 169 1.1 cube #define MDIOC_CLK_SEL_SHIFT 24 170 1.1 cube #define MDIOC_CLK_25_4 0 171 1.1 cube #define MDIOC_CLK_25_6 2 172 1.1 cube #define MDIOC_CLK_25_8 3 173 1.1 cube #define MDIOC_CLK_25_10 4 174 1.1 cube #define MDIOC_CLK_25_14 5 175 1.1 cube #define MDIOC_CLK_25_20 6 176 1.1 cube #define MDIOC_CLK_25_28 7 177 1.1 cube #define MDIOC_BUSY 0x08000000 178 1.1 cube /* Time to wait for MDIO, waiting for 2us in-between */ 179 1.1 cube #define MDIO_WAIT_TIMES 10 180 1.1 cube 181 1.1 cube /* SerDes Lock Detect Control and Status register */ 182 1.1 cube #define ATL2_SERDES 0x1424 183 1.1 cube #define SERDES_LOCK_DETECT 0x01 184 1.1 cube #define SERDES_LOCK_DETECT_EN 0x02 185 1.1 cube 186 1.1 cube /* MAC Control register */ 187 1.1 cube #define ATL2_MACC 0x1480 188 1.1 cube #define MACC_TX_EN 0x00000001 189 1.1 cube #define MACC_RX_EN 0x00000002 190 1.1 cube #define MACC_TX_FLOW_EN 0x00000004 191 1.1 cube #define MACC_RX_FLOW_EN 0x00000008 192 1.1 cube #define MACC_LOOPBACK 0x00000010 193 1.1 cube #define MACC_FDX 0x00000020 194 1.1 cube #define MACC_ADD_CRC 0x00000040 195 1.1 cube #define MACC_PAD 0x00000080 196 1.1 cube #define MACC_PREAMBLE_LEN_MASK 0x0f 197 1.1 cube #define MACC_PREAMBLE_LEN_SHIFT 10 198 1.1 cube #define MACC_STRIP_VLAN 0x00004000 199 1.1 cube #define MACC_PROMISC_EN 0x00008000 200 1.1 cube #define MACC_DBG_TX_BKPRESSURE 0x00100000 201 1.1 cube #define MACC_ALLMULTI_EN 0x02000000 202 1.1 cube #define MACC_BCAST_EN 0x04000000 203 1.1 cube #define MACC_MACLP_CLK_PHY 0x08000000 204 1.1 cube #define MACC_HDX_LEFT_BUF_MASK 0x0f 205 1.1 cube #define MACC_HDX_LEFT_BUF_SHIFT 28 206 1.1 cube 207 1.1 cube /* MAC IPG/IFG Control register */ 208 1.1 cube #define ATL2_MIPFG 0x1484 209 1.1 cube #define MIPFG_IPGT_MASK 0x0000007f 210 1.1 cube #define MIPFG_IPGT_SHIFT 0 211 1.1 cube #define MIPFG_MIFG_MASK 0xff 212 1.1 cube #define MIPFG_MIFG_SHIFT 8 213 1.1 cube #define MIPFG_IPGR1_MASK 0x7f 214 1.1 cube #define MIPFG_IPGR1_SHIFT 16 215 1.1 cube #define MIPFG_IPGR2_MASK 0x7f 216 1.1 cube #define MIPFG_IPGR2_SHIFT 24 217 1.1 cube 218 1.1 cube /* MAC Address registers */ 219 1.1 cube #define ATL2_MAC_ADDR_0 0x1488 220 1.1 cube #define ATL2_MAC_ADDR_1 0x148c 221 1.1 cube 222 1.1 cube /* Multicast Hash Table register */ 223 1.1 cube #define ATL2_MHT 0x1490 224 1.1 cube 225 1.1 cube /* MAC Half-Duplex Control register */ 226 1.1 cube #define ATL2_MHDC 0x1498 227 1.1 cube #define MHDC_LCOL_MASK 0x000003ff 228 1.1 cube #define MHDC_LCOL_SHIFT 0 229 1.1 cube #define MHDC_RETRY_MASK 0x0f 230 1.1 cube #define MHDC_RETRY_SHIFT 12 231 1.1 cube #define MHDC_EXC_DEF_EN 0x00010000 232 1.1 cube #define MHDC_NO_BACK_C 0x00020000 233 1.1 cube #define MHDC_NO_BACK_P 0x00040000 234 1.1 cube #define MHDC_ABEDE 0x00080000 235 1.1 cube #define MHDC_ABEBT_MASK 0x0f 236 1.1 cube #define MHDC_ABEBT_SHIFT 20 237 1.1 cube #define MHDC_JAMIPG_MASK 0x0f 238 1.1 cube #define MHDC_JAMIPG_SHIFT 24 239 1.1 cube 240 1.1 cube /* MTU Control register */ 241 1.1 cube #define ATL2_MTU 0x149c 242 1.1 cube 243 1.1 cube /* WOL Control register */ 244 1.1 cube #define ATL2_WOLC 245 1.1 cube #define WOLC_PATTERN_EN 0x00000001 246 1.1 cube #define WOLC_PATTERN_PME_EN 0x00000002 247 1.1 cube #define WOLC_MAGIC_EN 0x00000004 248 1.1 cube #define WOLC_MAGIC_PME_EN 0x00000008 249 1.1 cube #define WOLC_LINK_CHG_EN 0x00000010 250 1.1 cube #define WOLC_LINK_CHG_PME_EN 0x00000020 251 1.1 cube #define WOLC_PATTERN_ST 0x00000100 252 1.1 cube #define WOLC_MAGIC_ST 0x00000200 253 1.1 cube #define WOLC_LINK_CHG_ST 0x00000400 254 1.1 cube #define WOLC_PT0_EN 0x00010000 255 1.1 cube #define WOLC_PT1_EN 0x00020000 256 1.1 cube #define WOLC_PT2_EN 0x00040000 257 1.1 cube #define WOLC_PT3_EN 0x00080000 258 1.1 cube #define WOLC_PT4_EN 0x00100000 259 1.1 cube #define WOLC_PT0_MATCH 0x01000000 260 1.1 cube #define WOLC_PT1_MATCH 0x02000000 261 1.1 cube #define WOLC_PT2_MATCH 0x04000000 262 1.1 cube #define WOLC_PT3_MATCH 0x08000000 263 1.1 cube #define WOLC_PT4_MATCH 0x10000000 264 1.1 cube 265 1.1 cube /* Internal SRAM Partition register */ 266 1.1 cube #define ATL2_SRAM_TXRAM_END 0x1500 267 1.1 cube #define ATL2_SRAM_RXRAM_END 0x1502 268 1.1 cube 269 1.1 cube /* Descriptor Control registers */ 270 1.1 cube #define ATL2_DESC_BASE_ADDR_HI 0x1540 271 1.1 cube #define ATL2_TXD_BASE_ADDR_LO 0x1544 272 1.1 cube #define ATL2_TXD_BUFFER_SIZE 0x1548 273 1.1 cube #define ATL2_TXS_BASE_ADDR_LO 0x154c 274 1.1 cube #define ATL2_TXS_NUM_ENTRIES 0x1550 275 1.1 cube #define ATL2_RXD_BASE_ADDR_LO 0x1554 276 1.1 cube #define ATL2_RXD_NUM_ENTRIES 0x1558 277 1.1 cube 278 1.1 cube /* DMAR Control register */ 279 1.1 cube #define ATL2_DMAR 0x1580 280 1.1 cube #define DMAR_EN 0x01 281 1.1 cube 282 1.1 cube /* TX Cur-Through Control register */ 283 1.1 cube #define ATL2_TX_CUT_THRESH 0x1590 284 1.1 cube 285 1.1 cube /* DMAW Control register */ 286 1.1 cube #define ATL2_DMAW 0x15a0 287 1.1 cube #define DMAW_EN 0x01 288 1.1 cube 289 1.1 cube /* Flow Control registers */ 290 1.1 cube #define ATL2_PAUSE_ON_TH 0x15a8 291 1.1 cube #define ATL2_PAUSE_OFF_TH 0x15aa 292 1.1 cube 293 1.1 cube /* Mailbox registers */ 294 1.1 cube #define ATL2_MB_TXD_WR_IDX 0x15f0 295 1.1 cube #define ATL2_MB_RXD_RD_IDX 0x15f4 296 1.1 cube 297 1.1 cube /* Interrupt Status register */ 298 1.1 cube #define ATL2_ISR 0x1600 299 1.1 cube #define ISR_TIMER 0x00000001 300 1.1 cube #define ISR_MANUAL 0x00000002 301 1.1 cube #define ISR_RXF_OV 0x00000004 302 1.1 cube #define ISR_TXF_UR 0x00000008 303 1.1 cube #define ISR_TXS_OV 0x00000010 304 1.1 cube #define ISR_RXS_OV 0x00000020 305 1.1 cube #define ISR_LINK_CHG 0x00000040 306 1.1 cube #define ISR_HOST_TXD_UR 0x00000080 307 1.1 cube #define ISR_HOST_RXD_OV 0x00000100 308 1.1 cube #define ISR_DMAR_TO_RST 0x00000200 309 1.1 cube #define ISR_DMAW_TO_RST 0x00000400 310 1.1 cube #define ISR_PHY 0x00000800 311 1.1 cube #define ISR_TS_UPDATE 0x00010000 312 1.1 cube #define ISR_RS_UPDATE 0x00020000 313 1.1 cube #define ISR_TX_EARLY 0x00040000 314 1.1 cube #define ISR_UR_DETECTED 0x01000000 315 1.1 cube #define ISR_FERR_DETECTED 0x02000000 316 1.1 cube #define ISR_NFERR_DETECTED 0x04000000 317 1.1 cube #define ISR_CERR_DETECTED 0x08000000 318 1.1 cube #define ISR_PHY_LINKDOWN 0x10000000 319 1.1 cube #define ISR_DIS_INT 0x80000000 320 1.1 cube 321 1.1 cube #define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \ 322 1.1 cube ISR_HOST_TXD_UR | ISR_TS_UPDATE | \ 323 1.1 cube ISR_TX_EARLY) 324 1.1 cube #define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \ 325 1.1 cube ISR_HOST_RXD_OV | ISR_RS_UPDATE) 326 1.1 cube 327 1.1 cube /* Interrupt Mask register */ 328 1.1 cube #define ATL2_IMR 0x1604 329 1.1 cube #define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \ 330 1.1 cube ISR_PHY | ISR_PHY_LINKDOWN | \ 331 1.1 cube ISR_TS_UPDATE | ISR_RS_UPDATE | \ 332 1.1 cube ISR_MANUAL) 333 1.1 cube 334 1.1 cube /* MAC RX Statistics registers */ 335 1.1 cube #define ATL2_STS_RX_PAUSE 0x1700 336 1.1 cube #define ATL2_STS_RXD_OV 0x1704 337 1.1 cube #define ATL2_STS_RXS_OV 0x1708 338 1.1 cube #define ATL2_STS_RX_FILTER 0x170c 339 1.1 cube 340 1.1 cube struct tx_pkt_header { 341 1.1 cube uint16_t txph_size; 342 1.1 cube #define ATL2_TXH_ADD_VLAN_TAG 0x8000 343 1.1 cube uint16_t txph_vlan; 344 1.1 cube } __packed; 345 1.1 cube 346 1.1 cube struct tx_pkt_status { 347 1.1 cube uint16_t txps_size; 348 1.1 cube uint16_t txps_flags :15; 349 1.1 cube #define ATL2_TXF_SUCCESS 0x0001 350 1.1 cube #define ATL2_TXF_BCAST 0x0002 351 1.1 cube #define ATL2_TXF_MCAST 0x0004 352 1.1 cube #define ATL2_TXF_PAUSE 0x0008 353 1.1 cube #define ATL2_TXF_CTRL 0x0010 354 1.1 cube #define ATL2_TXF_DEFER 0x0020 355 1.1 cube #define ATL2_TXF_EXC_DEFER 0x0040 356 1.1 cube #define ATL2_TXF_SINGLE_COL 0x0080 357 1.1 cube #define ATL2_TXF_MULTI_COL 0x0100 358 1.1 cube #define ATL2_TXF_LATE_COL 0x0200 359 1.1 cube #define ATL2_TXF_ABORT_COL 0x0400 360 1.1 cube #define ATL2_TXF_UNDERRUN 0x0800 361 1.1 cube uint16_t txps_update:1; 362 1.1 cube } __packed; 363 1.1 cube 364 1.1 cube struct rx_pkt { 365 1.1 cube uint16_t rxp_size; 366 1.1 cube uint16_t rxp_flags :15; 367 1.1 cube #define ATL2_RXF_SUCCESS 0x0001 368 1.1 cube #define ATL2_RXF_BCAST 0x0002 369 1.1 cube #define ATL2_RXF_MCAST 0x0004 370 1.1 cube #define ATL2_RXF_PAUSE 0x0008 371 1.1 cube #define ATL2_RXF_CTRL 0x0010 372 1.1 cube #define ATL2_RXF_CRC 0x0020 373 1.1 cube #define ATL2_RXF_CODE 0x0040 374 1.1 cube #define ATL2_RXF_RUNT 0x0080 375 1.1 cube #define ATL2_RXF_FRAG 0x0100 376 1.1 cube #define ATL2_RXF_TRUNC 0x0200 377 1.1 cube #define ATL2_RXF_ALIGN 0x0400 378 1.1 cube #define ATL2_RXF_VLAN 0x0800 379 1.1 cube uint16_t rxp_update:1; 380 1.1 cube uint16_t rxp_vlan; 381 1.1 cube uint16_t __pad; 382 1.1 cube uint8_t rxp_data[1528]; 383 1.1 cube } __packed; 384
Indexes created Mon Sep 22 10:09:38 GMT 2025