if_liireg.h revision 1.1
1 /* $NetBSD: if_liireg.h,v 1.1 2008/03/29 00:16:26 cube Exp $ */ 2 3 /* 4 * Copyright (c) 2008 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of The NetBSD Foundation nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PCI configuration space seems to be mapped in the first 0x100 bytes of 34 * the register area. 35 */ 36 37 /* SPI Flash Control register */ 38 #define ATL2_SFC 0x0200 39 #define SFC_STS_NON_RDY 0x00000001 40 #define SFC_STS_WEN 0x00000002 41 #define SFC_STS_WPEN 0x00000080 42 #define SFC_DEV_STS_MASK 0x000000ff 43 #define SFC_DEV_STS_SHIFT 0 44 #define SFC_INS_MASK 0x07 45 #define SFC_INS_SHIFT 8 46 #define SFC_START 0x00000800 47 #define SFC_EN_VPD 0x00002000 48 #define SFC_LDSTART 0x00008000 49 #define SFC_CS_HI_MASK 0x03 50 #define SFC_CS_HI_SHIFT 16 51 #define SFC_CS_HOLD_MASK 0x03 52 #define SFC_CS_HOLD_SHIFT 18 53 #define SFC_CLK_LO_MASK 0x03 54 #define SFC_CLK_LO_SHIFT 20 55 #define SFC_CLK_HI_MASK 0x03 56 #define SFC_CLK_HI_SHIFT 22 57 #define SFC_CS_SETUP_MASK 0x03 58 #define SFC_CS_SETUP_SHIFT 24 59 #define SFC_EROMPGSZ_MASK 0x03 60 #define SFC_EROMPGSZ_SHIFT 26 61 #define SFC_WAIT_READY 0x10000000 62 63 /* SPI Flash Address register */ 64 #define ATL2_SF_ADDR 0x0204 65 66 /* SPI Flash Data register */ 67 #define ATL2_SF_DATA 0x0208 68 69 /* SPI Flash Configuration register */ 70 #define ATL2_SFCF 0x020c 71 #define SFCF_LD_ADDR_MASK 0x00ffffff 72 #define SFCF_LD_ADDR_SHIFT 0 73 #define SFCF_VPD_ADDR_MASK 0x03 74 #define SFCF_VPD_ADDR_SHIFT 24 75 #define SFCF_LD_EXISTS 0x04000000 76 77 /* SPI Flash op codes programmation registers */ 78 #define ATL2_SFOP_PROGRAM 0x0210 79 #define ATL2_SFOP_SC_ERASE 0x0211 80 #define ATL2_SFOP_CHIP_ERASE 0x0212 81 #define ATL2_SFOP_RDID 0x0213 82 #define ATL2_SFOP_WREN 0x0214 83 #define ATL2_SFOP_RDSR 0x0215 84 #define ATL2_SFOP_WRSR 0x0216 85 #define ATL2_SFOP_READ 0x0217 86 87 /* TWSI Control register, whatever that is */ 88 #define ATL2_TWSIC 0x0218 89 #define TWSIC_LD_OFFSET_MASK 0x000000ff 90 #define TWSIC_LD_OFFSET_SHIFT 0 91 #define TWSIC_LD_SLV_ADDR_MASK 0x07 92 #define TWSIC_LD_SLV_ADDR_SHIFT 8 93 #define TWSIC_SW_LDSTART 0x00000800 94 #define TWSIC_HW_LDSTART 0x00001000 95 #define TWSIC_SMB_SLV_ADDR_MASK 0x7F 96 #define TWSIC_SMB_SLV_ADDR_SHIFT 15 97 #define TWSIC_LD_EXIST 0x00400000 98 #define TWSIC_READ_FREQ_SEL_MASK 0x03 99 #define TWSIC_READ_FREQ_SEL_SHIFT 23 100 #define TWSIC_FREQ_SEL_100K 0 101 #define TWSIC_FREQ_SEL_200K 1 102 #define TWSIC_FREQ_SEL_300K 2 103 #define TWSIC_FREQ_SEL_400K 3 104 #define TWSIC_WRITE_FREQ_SEL_MASK 0x03 105 #define TWSIC_WRITE_FREQ_SEL_SHIFT 24 106 107 /* PCI-Express Device Misc. Control register? (size unknown) */ 108 #define ATL2_PCEDMC 0x021c 109 #define PCEDMC_RETRY_BUFDIS 0x01 110 #define PCEDMC_EXT_PIPE 0x02 111 #define PCEDMC_SPIROM_EXISTS 0x04 112 #define PCEDMC_SERDES_ENDIAN 0x08 113 #define PCEDMC_SERDES_SEL_DIN 0x10 114 115 /* PCI-Express PHY Miscellaneous register (size unknown) */ 116 #define ATL2_PCEPM 0x1000 117 #define PCEPM_FORCE_RCV_DET 0x04 118 119 /* PCI-Express DLL TX Control register */ 120 #define ATL2_PCEDTXC 0x1104 121 #define PCEDTX_SEL_NOR_CLK 0x00000400 122 #define PCEDTX_DEF 0x00000568 123 124 /* PCI-Express-related register (LTSSM test mode) */ 125 #define ATL2_PCELTM 0x12fc 126 #define PCELTM_DEF 0x00006500 127 128 /* Selene Master Control register */ 129 #define ATL2_SMC 0x1400 130 #define SMC_SOFT_RST 0x00000001 131 #define SMC_MTIMER_EN 0x00000002 132 #define SMC_ITIMER_EN 0x00000004 133 #define SMC_MANUAL_INT 0x00000008 134 #define SMC_REV_NUM_MASK 0xff 135 #define SMC_REV_NUM_SHIFT 16 136 #define SMC_DEV_ID_MASK 0xff 137 #define SMC_DEV_ID_SHIFT 24 138 139 /* Timer Initial Value register */ 140 #define ATL2_TIV 0x1404 141 142 /* IRQ Moderator Timer Initial Value register */ 143 #define ATL2_IMTIV 0x1408 144 145 /* PHY Control register */ 146 #define ATL2_PHYC 0x140c 147 #define PHYC_ENABLE 0x0001 148 149 /* IRQ Anti-Lost Timer Initial Value register 150 --> Time allowed for software to clear the interrupt */ 151 #define ATL2_IALTIV 0x140e 152 153 /* Block Idle Status register 154 --> Bit set if matching state machine is not idle */ 155 #define ATL2_BIS 0x1410 156 #define BIS_RXMAC 0x00000001 157 #define BIS_TXMAC 0x00000002 158 #define BIS_DMAR 0x00000004 159 #define BIS_DMAW 0x00000008 160 161 /* MDIO Control register */ 162 #define ATL2_MDIOC 0x1414 163 #define MDIOC_DATA_MASK 0x0000ffff 164 #define MDIOC_DATA_SHIFT 0 165 #define MDIOC_REG_MASK 0x1f 166 #define MDIOC_REG_SHIFT 16 167 #define MDIOC_WRITE 0x00000000 168 #define MDIOC_READ 0x00200000 169 #define MDIOC_SUP_PREAMBLE 0x00400000 170 #define MDIOC_START 0x00800000 171 #define MDIOC_CLK_SEL_MASK 0x07 172 #define MDIOC_CLK_SEL_SHIFT 24 173 #define MDIOC_CLK_25_4 0 174 #define MDIOC_CLK_25_6 2 175 #define MDIOC_CLK_25_8 3 176 #define MDIOC_CLK_25_10 4 177 #define MDIOC_CLK_25_14 5 178 #define MDIOC_CLK_25_20 6 179 #define MDIOC_CLK_25_28 7 180 #define MDIOC_BUSY 0x08000000 181 /* Time to wait for MDIO, waiting for 2us in-between */ 182 #define MDIO_WAIT_TIMES 10 183 184 /* SerDes Lock Detect Control and Status register */ 185 #define ATL2_SERDES 0x1424 186 #define SERDES_LOCK_DETECT 0x01 187 #define SERDES_LOCK_DETECT_EN 0x02 188 189 /* MAC Control register */ 190 #define ATL2_MACC 0x1480 191 #define MACC_TX_EN 0x00000001 192 #define MACC_RX_EN 0x00000002 193 #define MACC_TX_FLOW_EN 0x00000004 194 #define MACC_RX_FLOW_EN 0x00000008 195 #define MACC_LOOPBACK 0x00000010 196 #define MACC_FDX 0x00000020 197 #define MACC_ADD_CRC 0x00000040 198 #define MACC_PAD 0x00000080 199 #define MACC_PREAMBLE_LEN_MASK 0x0f 200 #define MACC_PREAMBLE_LEN_SHIFT 10 201 #define MACC_STRIP_VLAN 0x00004000 202 #define MACC_PROMISC_EN 0x00008000 203 #define MACC_DBG_TX_BKPRESSURE 0x00100000 204 #define MACC_ALLMULTI_EN 0x02000000 205 #define MACC_BCAST_EN 0x04000000 206 #define MACC_MACLP_CLK_PHY 0x08000000 207 #define MACC_HDX_LEFT_BUF_MASK 0x0f 208 #define MACC_HDX_LEFT_BUF_SHIFT 28 209 210 /* MAC IPG/IFG Control register */ 211 #define ATL2_MIPFG 0x1484 212 #define MIPFG_IPGT_MASK 0x0000007f 213 #define MIPFG_IPGT_SHIFT 0 214 #define MIPFG_MIFG_MASK 0xff 215 #define MIPFG_MIFG_SHIFT 8 216 #define MIPFG_IPGR1_MASK 0x7f 217 #define MIPFG_IPGR1_SHIFT 16 218 #define MIPFG_IPGR2_MASK 0x7f 219 #define MIPFG_IPGR2_SHIFT 24 220 221 /* MAC Address registers */ 222 #define ATL2_MAC_ADDR_0 0x1488 223 #define ATL2_MAC_ADDR_1 0x148c 224 225 /* Multicast Hash Table register */ 226 #define ATL2_MHT 0x1490 227 228 /* MAC Half-Duplex Control register */ 229 #define ATL2_MHDC 0x1498 230 #define MHDC_LCOL_MASK 0x000003ff 231 #define MHDC_LCOL_SHIFT 0 232 #define MHDC_RETRY_MASK 0x0f 233 #define MHDC_RETRY_SHIFT 12 234 #define MHDC_EXC_DEF_EN 0x00010000 235 #define MHDC_NO_BACK_C 0x00020000 236 #define MHDC_NO_BACK_P 0x00040000 237 #define MHDC_ABEDE 0x00080000 238 #define MHDC_ABEBT_MASK 0x0f 239 #define MHDC_ABEBT_SHIFT 20 240 #define MHDC_JAMIPG_MASK 0x0f 241 #define MHDC_JAMIPG_SHIFT 24 242 243 /* MTU Control register */ 244 #define ATL2_MTU 0x149c 245 246 /* WOL Control register */ 247 #define ATL2_WOLC 248 #define WOLC_PATTERN_EN 0x00000001 249 #define WOLC_PATTERN_PME_EN 0x00000002 250 #define WOLC_MAGIC_EN 0x00000004 251 #define WOLC_MAGIC_PME_EN 0x00000008 252 #define WOLC_LINK_CHG_EN 0x00000010 253 #define WOLC_LINK_CHG_PME_EN 0x00000020 254 #define WOLC_PATTERN_ST 0x00000100 255 #define WOLC_MAGIC_ST 0x00000200 256 #define WOLC_LINK_CHG_ST 0x00000400 257 #define WOLC_PT0_EN 0x00010000 258 #define WOLC_PT1_EN 0x00020000 259 #define WOLC_PT2_EN 0x00040000 260 #define WOLC_PT3_EN 0x00080000 261 #define WOLC_PT4_EN 0x00100000 262 #define WOLC_PT0_MATCH 0x01000000 263 #define WOLC_PT1_MATCH 0x02000000 264 #define WOLC_PT2_MATCH 0x04000000 265 #define WOLC_PT3_MATCH 0x08000000 266 #define WOLC_PT4_MATCH 0x10000000 267 268 /* Internal SRAM Partition register */ 269 #define ATL2_SRAM_TXRAM_END 0x1500 270 #define ATL2_SRAM_RXRAM_END 0x1502 271 272 /* Descriptor Control registers */ 273 #define ATL2_DESC_BASE_ADDR_HI 0x1540 274 #define ATL2_TXD_BASE_ADDR_LO 0x1544 275 #define ATL2_TXD_BUFFER_SIZE 0x1548 276 #define ATL2_TXS_BASE_ADDR_LO 0x154c 277 #define ATL2_TXS_NUM_ENTRIES 0x1550 278 #define ATL2_RXD_BASE_ADDR_LO 0x1554 279 #define ATL2_RXD_NUM_ENTRIES 0x1558 280 281 /* DMAR Control register */ 282 #define ATL2_DMAR 0x1580 283 #define DMAR_EN 0x01 284 285 /* TX Cur-Through Control register */ 286 #define ATL2_TX_CUT_THRESH 0x1590 287 288 /* DMAW Control register */ 289 #define ATL2_DMAW 0x15a0 290 #define DMAW_EN 0x01 291 292 /* Flow Control registers */ 293 #define ATL2_PAUSE_ON_TH 0x15a8 294 #define ATL2_PAUSE_OFF_TH 0x15aa 295 296 /* Mailbox registers */ 297 #define ATL2_MB_TXD_WR_IDX 0x15f0 298 #define ATL2_MB_RXD_RD_IDX 0x15f4 299 300 /* Interrupt Status register */ 301 #define ATL2_ISR 0x1600 302 #define ISR_TIMER 0x00000001 303 #define ISR_MANUAL 0x00000002 304 #define ISR_RXF_OV 0x00000004 305 #define ISR_TXF_UR 0x00000008 306 #define ISR_TXS_OV 0x00000010 307 #define ISR_RXS_OV 0x00000020 308 #define ISR_LINK_CHG 0x00000040 309 #define ISR_HOST_TXD_UR 0x00000080 310 #define ISR_HOST_RXD_OV 0x00000100 311 #define ISR_DMAR_TO_RST 0x00000200 312 #define ISR_DMAW_TO_RST 0x00000400 313 #define ISR_PHY 0x00000800 314 #define ISR_TS_UPDATE 0x00010000 315 #define ISR_RS_UPDATE 0x00020000 316 #define ISR_TX_EARLY 0x00040000 317 #define ISR_UR_DETECTED 0x01000000 318 #define ISR_FERR_DETECTED 0x02000000 319 #define ISR_NFERR_DETECTED 0x04000000 320 #define ISR_CERR_DETECTED 0x08000000 321 #define ISR_PHY_LINKDOWN 0x10000000 322 #define ISR_DIS_INT 0x80000000 323 324 #define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \ 325 ISR_HOST_TXD_UR | ISR_TS_UPDATE | \ 326 ISR_TX_EARLY) 327 #define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \ 328 ISR_HOST_RXD_OV | ISR_RS_UPDATE) 329 330 /* Interrupt Mask register */ 331 #define ATL2_IMR 0x1604 332 #define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \ 333 ISR_PHY | ISR_PHY_LINKDOWN | \ 334 ISR_TS_UPDATE | ISR_RS_UPDATE | \ 335 ISR_MANUAL) 336 337 /* MAC RX Statistics registers */ 338 #define ATL2_STS_RX_PAUSE 0x1700 339 #define ATL2_STS_RXD_OV 0x1704 340 #define ATL2_STS_RXS_OV 0x1708 341 #define ATL2_STS_RX_FILTER 0x170c 342 343 struct tx_pkt_header { 344 uint16_t txph_size; 345 #define ATL2_TXH_ADD_VLAN_TAG 0x8000 346 uint16_t txph_vlan; 347 } __packed; 348 349 struct tx_pkt_status { 350 uint16_t txps_size; 351 uint16_t txps_flags :15; 352 #define ATL2_TXF_SUCCESS 0x0001 353 #define ATL2_TXF_BCAST 0x0002 354 #define ATL2_TXF_MCAST 0x0004 355 #define ATL2_TXF_PAUSE 0x0008 356 #define ATL2_TXF_CTRL 0x0010 357 #define ATL2_TXF_DEFER 0x0020 358 #define ATL2_TXF_EXC_DEFER 0x0040 359 #define ATL2_TXF_SINGLE_COL 0x0080 360 #define ATL2_TXF_MULTI_COL 0x0100 361 #define ATL2_TXF_LATE_COL 0x0200 362 #define ATL2_TXF_ABORT_COL 0x0400 363 #define ATL2_TXF_UNDERRUN 0x0800 364 uint16_t txps_update:1; 365 } __packed; 366 367 struct rx_pkt { 368 uint16_t rxp_size; 369 uint16_t rxp_flags :15; 370 #define ATL2_RXF_SUCCESS 0x0001 371 #define ATL2_RXF_BCAST 0x0002 372 #define ATL2_RXF_MCAST 0x0004 373 #define ATL2_RXF_PAUSE 0x0008 374 #define ATL2_RXF_CTRL 0x0010 375 #define ATL2_RXF_CRC 0x0020 376 #define ATL2_RXF_CODE 0x0040 377 #define ATL2_RXF_RUNT 0x0080 378 #define ATL2_RXF_FRAG 0x0100 379 #define ATL2_RXF_TRUNC 0x0200 380 #define ATL2_RXF_ALIGN 0x0400 381 #define ATL2_RXF_VLAN 0x0800 382 uint16_t rxp_update:1; 383 uint16_t rxp_vlan; 384 uint16_t __pad; 385 uint8_t rxp_data[1528]; 386 } __packed; 387
Indexes created Sat Sep 27 14:09:57 GMT 2025