if_msk.c revision 1.1
1 /* $NetBSD: if_msk.c,v 1.1 2006/09/09 16:17:50 riz Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.11 2006/08/17 22:07:40 brad Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include "bpfilter.h" 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/kernel.h> 63 #include <sys/socket.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/callout.h> 67 #include <sys/sysctl.h> 68 #include <sys/endian.h> 69 #ifdef __NetBSD__ 70 #define letoh16 htole16 71 #define letoh32 htole32 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_types.h> 77 78 #include <net/if_media.h> 79 80 #if NBPFILTER > 0 81 #include <net/bpf.h> 82 #endif 83 #if NRND > 0 84 #include <sys/rnd.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/brgphyreg.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 95 #include <dev/pci/if_skreg.h> 96 #include <dev/pci/if_mskvar.h> 97 98 int mskc_probe(struct device *, struct cfdata *, void *); 99 void mskc_attach(struct device *, struct device *self, void *aux); 100 void mskc_shutdown(void *); 101 int msk_probe(struct device *, struct cfdata *, void *); 102 void msk_attach(struct device *, struct device *self, void *aux); 103 int mskcprint(void *, const char *); 104 int msk_intr(void *); 105 void msk_intr_yukon(struct sk_if_softc *); 106 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 107 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 108 void msk_txeof(struct sk_if_softc *); 109 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 110 void msk_start(struct ifnet *); 111 int msk_ioctl(struct ifnet *, u_long, caddr_t); 112 int msk_init(struct ifnet *); 113 void msk_init_yukon(struct sk_if_softc *); 114 void msk_stop(struct ifnet *, int); 115 void msk_watchdog(struct ifnet *); 116 int msk_ifmedia_upd(struct ifnet *); 117 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 void msk_reset(struct sk_softc *); 119 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 120 int msk_alloc_jumbo_mem(struct sk_if_softc *); 121 void *msk_jalloc(struct sk_if_softc *); 122 void msk_jfree(struct mbuf *, caddr_t, size_t, void *); 123 int msk_init_rx_ring(struct sk_if_softc *); 124 int msk_init_tx_ring(struct sk_if_softc *); 125 126 void msk_update_int_mod(struct sk_softc *); 127 128 int msk_marv_miibus_readreg(struct device *, int, int); 129 void msk_marv_miibus_writereg(struct device *, int, int, int); 130 void msk_marv_miibus_statchg(struct device *); 131 132 u_int32_t msk_yukon_hash(caddr_t); 133 void msk_setfilt(struct sk_if_softc *, caddr_t, int); 134 void msk_setmulti(struct sk_if_softc *); 135 void msk_setpromisc(struct sk_if_softc *); 136 void msk_yukon_tick(void *); 137 138 /* #define MSK_DEBUG 1 */ 139 #ifdef MSK_DEBUG 140 #define DPRINTF(x) if (mskdebug) printf x 141 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 142 int mskdebug = MSK_DEBUG; 143 144 void msk_dump_txdesc(struct msk_tx_desc *, int); 145 void msk_dump_mbuf(struct mbuf *); 146 void msk_dump_bytes(const char *, int); 147 #else 148 #define DPRINTF(x) 149 #define DPRINTFN(n,x) 150 #endif 151 152 static int msk_sysctl_handler(SYSCTLFN_PROTO); 153 static int msk_root_num; 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_3 }, 175 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 176 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 177 }; 178 179 static inline u_int32_t 180 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 181 { 182 return CSR_READ_4(sc, reg); 183 } 184 185 static inline u_int16_t 186 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 187 { 188 return CSR_READ_2(sc, reg); 189 } 190 191 static inline u_int8_t 192 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 193 { 194 return CSR_READ_1(sc, reg); 195 } 196 197 static inline void 198 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 199 { 200 CSR_WRITE_4(sc, reg, x); 201 } 202 203 static inline void 204 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 205 { 206 CSR_WRITE_2(sc, reg, x); 207 } 208 209 static inline void 210 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 211 { 212 CSR_WRITE_1(sc, reg, x); 213 } 214 215 int 216 msk_marv_miibus_readreg(struct device *dev, int phy, int reg) 217 { 218 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 219 u_int16_t val; 220 int i; 221 222 if (phy != 0 || 223 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 224 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 225 DPRINTFN(9, ("msk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 226 phy, reg)); 227 return (0); 228 } 229 230 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 231 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 232 233 for (i = 0; i < SK_TIMEOUT; i++) { 234 DELAY(1); 235 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 236 if (val & YU_SMICR_READ_VALID) 237 break; 238 } 239 240 if (i == SK_TIMEOUT) { 241 aprint_error("%s: phy failed to come ready\n", 242 sc_if->sk_dev.dv_xname); 243 return (0); 244 } 245 246 DPRINTFN(9, ("msk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 247 SK_TIMEOUT)); 248 249 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 250 251 DPRINTFN(9, ("msk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 252 phy, reg, val)); 253 254 return (val); 255 } 256 257 void 258 msk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 259 { 260 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 261 int i; 262 263 DPRINTFN(9, ("msk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 264 phy, reg, val)); 265 266 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 267 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 268 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 269 270 for (i = 0; i < SK_TIMEOUT; i++) { 271 DELAY(1); 272 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 273 break; 274 } 275 276 if (i == SK_TIMEOUT) 277 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 278 } 279 280 void 281 msk_marv_miibus_statchg(struct device *dev) 282 { 283 DPRINTFN(9, ("msk_marv_miibus_statchg: gpcr=%x\n", 284 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 285 } 286 287 #define HASH_BITS 6 288 289 u_int32_t 290 msk_yukon_hash(caddr_t addr) 291 { 292 u_int32_t crc; 293 294 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 295 return (crc & ((1 << HASH_BITS) - 1)); 296 } 297 298 void 299 msk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 300 { 301 int base = XM_RXFILT_ENTRY(slot); 302 303 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 304 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 305 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 306 } 307 308 void 309 msk_setmulti(struct sk_if_softc *sc_if) 310 { 311 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 312 u_int32_t hashes[2] = { 0, 0 }; 313 int h; 314 struct ethercom *ec = &sc_if->sk_ethercom; 315 struct ether_multi *enm; 316 struct ether_multistep step; 317 318 /* First, zot all the existing filters. */ 319 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 320 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 321 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 322 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 323 324 325 /* Now program new ones. */ 326 allmulti: 327 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 328 hashes[0] = 0xFFFFFFFF; 329 hashes[1] = 0xFFFFFFFF; 330 } else { 331 /* First find the tail of the list. */ 332 ETHER_FIRST_MULTI(step, ec, enm); 333 while (enm != NULL) { 334 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 335 ETHER_ADDR_LEN)) { 336 ifp->if_flags |= IFF_ALLMULTI; 337 goto allmulti; 338 } 339 h = msk_yukon_hash(enm->enm_addrlo); 340 if (h < 32) 341 hashes[0] |= (1 << h); 342 else 343 hashes[1] |= (1 << (h - 32)); 344 345 ETHER_NEXT_MULTI(step, enm); 346 } 347 } 348 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 353 } 354 355 void 356 msk_setpromisc(struct sk_if_softc *sc_if) 357 { 358 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 359 360 if (ifp->if_flags & IFF_PROMISC) 361 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 362 YU_RCR_UFLEN | YU_RCR_MUFLEN); 363 else 364 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 365 YU_RCR_UFLEN | YU_RCR_MUFLEN); 366 } 367 368 int 369 msk_init_rx_ring(struct sk_if_softc *sc_if) 370 { 371 struct msk_chain_data *cd = &sc_if->sk_cdata; 372 struct msk_ring_data *rd = sc_if->sk_rdata; 373 int i, nexti; 374 375 bzero((char *)rd->sk_rx_ring, 376 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 377 378 for (i = 0; i < MSK_RX_RING_CNT; i++) { 379 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 380 if (i == (MSK_RX_RING_CNT - 1)) 381 nexti = 0; 382 else 383 nexti = i + 1; 384 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 385 } 386 387 for (i = 0; i < MSK_RX_RING_CNT; i++) { 388 if (msk_newbuf(sc_if, i, NULL, 389 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 390 aprint_error("%s: failed alloc of %dth mbuf\n", 391 sc_if->sk_dev.dv_xname, i); 392 return (ENOBUFS); 393 } 394 } 395 396 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 397 sc_if->sk_cdata.sk_rx_cons = 0; 398 399 return (0); 400 } 401 402 int 403 msk_init_tx_ring(struct sk_if_softc *sc_if) 404 { 405 struct sk_softc *sc = sc_if->sk_softc; 406 struct msk_chain_data *cd = &sc_if->sk_cdata; 407 struct msk_ring_data *rd = sc_if->sk_rdata; 408 bus_dmamap_t dmamap; 409 struct sk_txmap_entry *entry; 410 int i, nexti; 411 412 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 413 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 414 415 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 416 for (i = 0; i < MSK_TX_RING_CNT; i++) { 417 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 418 if (i == (MSK_TX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 423 424 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 425 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 426 return (ENOBUFS); 427 428 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 429 if (!entry) { 430 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 431 return (ENOBUFS); 432 } 433 entry->dmamap = dmamap; 434 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 435 } 436 437 sc_if->sk_cdata.sk_tx_prod = 0; 438 sc_if->sk_cdata.sk_tx_cons = 0; 439 sc_if->sk_cdata.sk_tx_cnt = 0; 440 441 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 442 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 443 444 return (0); 445 } 446 447 int 448 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 449 bus_dmamap_t dmamap) 450 { 451 struct mbuf *m_new = NULL; 452 struct sk_chain *c; 453 struct msk_rx_desc *r; 454 455 if (m == NULL) { 456 caddr_t buf = NULL; 457 458 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 459 if (m_new == NULL) 460 return (ENOBUFS); 461 462 /* Allocate the jumbo buffer */ 463 buf = msk_jalloc(sc_if); 464 if (buf == NULL) { 465 m_freem(m_new); 466 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 467 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 468 return (ENOBUFS); 469 } 470 471 /* Attach the buffer to the mbuf */ 472 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 473 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 474 } else { 475 /* 476 * We're re-using a previously allocated mbuf; 477 * be sure to re-init pointers and lengths to 478 * default values. 479 */ 480 m_new = m; 481 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 482 m_new->m_data = m_new->m_ext.ext_buf; 483 } 484 m_adj(m_new, ETHER_ALIGN); 485 486 c = &sc_if->sk_cdata.sk_rx_chain[i]; 487 r = c->sk_le; 488 c->sk_mbuf = m_new; 489 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 490 (((vaddr_t)m_new->m_data 491 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 492 r->sk_len = htole16(SK_JLEN); 493 r->sk_ctl = 0; 494 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 495 496 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 497 498 return (0); 499 } 500 501 /* 502 * Memory management for jumbo frames. 503 */ 504 505 int 506 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 507 { 508 struct sk_softc *sc = sc_if->sk_softc; 509 caddr_t ptr, kva; 510 bus_dma_segment_t seg; 511 int i, rseg, state, error; 512 struct sk_jpool_entry *entry; 513 514 state = error = 0; 515 516 /* Grab a big chunk o' storage. */ 517 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 518 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 519 aprint_error(": can't alloc rx buffers"); 520 return (ENOBUFS); 521 } 522 523 state = 1; 524 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, &kva, 525 BUS_DMA_NOWAIT)) { 526 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 527 error = ENOBUFS; 528 goto out; 529 } 530 531 state = 2; 532 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 533 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 534 aprint_error(": can't create dma map"); 535 error = ENOBUFS; 536 goto out; 537 } 538 539 state = 3; 540 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 541 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 542 aprint_error(": can't load dma map"); 543 error = ENOBUFS; 544 goto out; 545 } 546 547 state = 4; 548 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 549 DPRINTFN(1,("msk_jumbo_buf = %p\n", (caddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 550 551 LIST_INIT(&sc_if->sk_jfree_listhead); 552 LIST_INIT(&sc_if->sk_jinuse_listhead); 553 554 /* 555 * Now divide it up into 9K pieces and save the addresses 556 * in an array. 557 */ 558 ptr = sc_if->sk_cdata.sk_jumbo_buf; 559 for (i = 0; i < MSK_JSLOTS; i++) { 560 sc_if->sk_cdata.sk_jslots[i] = ptr; 561 ptr += SK_JLEN; 562 entry = malloc(sizeof(struct sk_jpool_entry), 563 M_DEVBUF, M_NOWAIT); 564 if (entry == NULL) { 565 aprint_error(": no memory for jumbo buffer queue!"); 566 error = ENOBUFS; 567 goto out; 568 } 569 entry->slot = i; 570 if (i) 571 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 572 entry, jpool_entries); 573 else 574 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 575 entry, jpool_entries); 576 } 577 out: 578 if (error != 0) { 579 switch (state) { 580 case 4: 581 bus_dmamap_unload(sc->sc_dmatag, 582 sc_if->sk_cdata.sk_rx_jumbo_map); 583 case 3: 584 bus_dmamap_destroy(sc->sc_dmatag, 585 sc_if->sk_cdata.sk_rx_jumbo_map); 586 case 2: 587 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 588 case 1: 589 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 590 break; 591 default: 592 break; 593 } 594 } 595 596 return (error); 597 } 598 599 /* 600 * Allocate a jumbo buffer. 601 */ 602 void * 603 msk_jalloc(struct sk_if_softc *sc_if) 604 { 605 struct sk_jpool_entry *entry; 606 607 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 608 609 if (entry == NULL) 610 return (NULL); 611 612 LIST_REMOVE(entry, jpool_entries); 613 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 614 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 615 } 616 617 /* 618 * Release a jumbo buffer. 619 */ 620 void 621 msk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 622 { 623 struct sk_jpool_entry *entry; 624 struct sk_if_softc *sc; 625 int i, s; 626 627 /* Extract the softc struct pointer. */ 628 sc = (struct sk_if_softc *)arg; 629 630 if (sc == NULL) 631 panic("msk_jfree: can't find softc pointer!"); 632 633 /* calculate the slot this buffer belongs to */ 634 635 i = ((vaddr_t)buf 636 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 637 638 if ((i < 0) || (i >= MSK_JSLOTS)) 639 panic("sk_jfree: asked to free buffer that we don't manage!"); 640 641 s = splvm(); 642 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 643 if (entry == NULL) 644 panic("msk_jfree: buffer not in use!"); 645 entry->slot = i; 646 LIST_REMOVE(entry, jpool_entries); 647 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 648 649 if (__predict_true(m != NULL)) 650 pool_cache_put(&mbpool_cache, m); 651 splx(s); 652 } 653 654 /* 655 * Set media options. 656 */ 657 int 658 msk_ifmedia_upd(struct ifnet *ifp) 659 { 660 struct sk_if_softc *sc_if = ifp->if_softc; 661 662 msk_init(ifp); 663 mii_mediachg(&sc_if->sk_mii); 664 return (0); 665 } 666 667 /* 668 * Report current media status. 669 */ 670 void 671 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 672 { 673 struct sk_if_softc *sc_if = ifp->if_softc; 674 675 mii_pollstat(&sc_if->sk_mii); 676 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 677 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 678 } 679 680 int 681 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 682 { 683 struct sk_if_softc *sc_if = ifp->if_softc; 684 struct ifreq *ifr = (struct ifreq *) data; 685 struct mii_data *mii; 686 int s, error = 0; 687 688 s = splnet(); 689 690 switch(command) { 691 case SIOCGIFMEDIA: 692 case SIOCSIFMEDIA: 693 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA\n")); 694 mii = &sc_if->sk_mii; 695 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 696 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA done\n")); 697 break; 698 default: 699 DPRINTFN(2, ("msk_ioctl ETHER\n")); 700 error = ether_ioctl(ifp, command, data); 701 702 if (error == ENETRESET) { 703 /* 704 * Multicast list has changed; set the hardware 705 * filter accordingly. 706 */ 707 if (ifp->if_flags & IFF_RUNNING) 708 msk_setmulti(sc_if); 709 error = 0; 710 } 711 break; 712 } 713 714 splx(s); 715 return (error); 716 } 717 718 void 719 msk_update_int_mod(struct sk_softc *sc) 720 { 721 u_int32_t sk_imtimer_ticks; 722 723 /* 724 * Configure interrupt moderation. The moderation timer 725 * defers interrupts specified in the interrupt moderation 726 * timer mask based on the timeout specified in the interrupt 727 * moderation timer init register. Each bit in the timer 728 * register represents one tick, so to specify a timeout in 729 * microseconds, we have to multiply by the correct number of 730 * ticks-per-microsecond. 731 */ 732 switch (sc->sk_type) { 733 case SK_YUKON_EC: 734 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 735 break; 736 default: 737 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 738 } 739 aprint_verbose("%s: interrupt moderation is %d us\n", 740 sc->sk_dev.dv_xname, sc->sk_int_mod); 741 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 742 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 743 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 744 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 745 sc->sk_int_mod_pending = 0; 746 } 747 748 static int 749 msk_lookup(const struct pci_attach_args *pa) 750 { 751 const struct msk_product *pmsk; 752 753 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 754 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 755 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 756 return 1; 757 } 758 return 0; 759 } 760 761 /* 762 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 763 * IDs against our list and return a device name if we find a match. 764 */ 765 int 766 mskc_probe(struct device *parent, struct cfdata *match, void *aux) 767 { 768 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 769 770 return msk_lookup(pa); 771 } 772 773 /* 774 * Force the GEnesis into reset, then bring it out of reset. 775 */ 776 void msk_reset(struct sk_softc *sc) 777 { 778 u_int32_t sk_imtimer_ticks; 779 int reg; 780 781 DPRINTFN(2, ("msk_reset\n")); 782 783 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 784 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 785 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 786 787 DELAY(1000); 788 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 789 DELAY(2); 790 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 791 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 792 793 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 794 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 795 CSR_READ_2(sc, SK_LINK_CTRL))); 796 797 /* Disable ASF */ 798 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 799 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 800 801 /* Clear I2C IRQ noise */ 802 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 803 804 /* Disable hardware timer */ 805 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 806 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 807 808 /* Disable descriptor polling */ 809 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 810 811 /* Disable time stamps */ 812 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 813 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 814 815 /* Enable RAM interface */ 816 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 817 for (reg = SK_TO0;reg <= SK_TO11; reg++) 818 sk_win_write_1(sc, reg, 36); 819 820 /* 821 * Configure interrupt moderation. The moderation timer 822 * defers interrupts specified in the interrupt moderation 823 * timer mask based on the timeout specified in the interrupt 824 * moderation timer init register. Each bit in the timer 825 * register represents one tick, so to specify a timeout in 826 * microseconds, we have to multiply by the correct number of 827 * ticks-per-microsecond. 828 */ 829 switch (sc->sk_type) { 830 case SK_YUKON_EC: 831 case SK_YUKON_XL: 832 case SK_YUKON_FE: 833 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 834 break; 835 default: 836 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 837 } 838 839 /* Reset status ring. */ 840 bzero((char *)sc->sk_status_ring, 841 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 842 sc->sk_status_idx = 0; 843 844 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 845 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 846 847 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 848 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 849 sc->sk_status_map->dm_segs[0].ds_addr); 850 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 851 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 852 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 853 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 854 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 855 856 #if 0 857 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 858 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 859 860 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 861 #else 862 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 863 #endif 864 865 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 866 867 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 868 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 869 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 870 871 msk_update_int_mod(sc); 872 } 873 874 int 875 msk_probe(struct device *parent, struct cfdata *match, void *aux) 876 { 877 struct skc_attach_args *sa = aux; 878 879 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 880 return (0); 881 882 switch (sa->skc_type) { 883 case SK_YUKON_XL: 884 case SK_YUKON_EC_U: 885 case SK_YUKON_EC: 886 case SK_YUKON_FE: 887 return (1); 888 } 889 890 return (0); 891 } 892 893 /* 894 * Each XMAC chip is attached as a separate logical IP interface. 895 * Single port cards will have only one logical interface of course. 896 */ 897 void 898 msk_attach(struct device *parent, struct device *self, void *aux) 899 { 900 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 901 struct sk_softc *sc = (struct sk_softc *)parent; 902 struct skc_attach_args *sa = aux; 903 struct ifnet *ifp; 904 caddr_t kva; 905 bus_dma_segment_t seg; 906 int i, rseg; 907 u_int32_t chunk, val; 908 909 sc_if->sk_port = sa->skc_port; 910 sc_if->sk_softc = sc; 911 sc->sk_if[sa->skc_port] = sc_if; 912 913 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 914 915 /* 916 * Get station address for this interface. Note that 917 * dual port cards actually come with three station 918 * addresses: one for each port, plus an extra. The 919 * extra one is used by the SysKonnect driver software 920 * as a 'virtual' station address for when both ports 921 * are operating in failover mode. Currently we don't 922 * use this extra address. 923 */ 924 for (i = 0; i < ETHER_ADDR_LEN; i++) 925 sc_if->sk_enaddr[i] = 926 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 927 928 aprint_normal(": Ethernet address %s\n", 929 ether_sprintf(sc_if->sk_enaddr)); 930 931 /* 932 * Set up RAM buffer addresses. The NIC will have a certain 933 * amount of SRAM on it, somewhere between 512K and 2MB. We 934 * need to divide this up a) between the transmitter and 935 * receiver and b) between the two XMACs, if this is a 936 * dual port NIC. Our algorithm is to divide up the memory 937 * evenly so that everyone gets a fair share. 938 * 939 * Just to be contrary, Yukon2 appears to have separate memory 940 * for each MAC. 941 */ 942 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 943 val = sc->sk_rboff / sizeof(u_int64_t); 944 sc_if->sk_rx_ramstart = val; 945 val += (chunk / sizeof(u_int64_t)); 946 sc_if->sk_rx_ramend = val - 1; 947 chunk = sc->sk_ramsize - chunk; 948 sc_if->sk_tx_ramstart = val; 949 val += (chunk / sizeof(u_int64_t)); 950 sc_if->sk_tx_ramend = val - 1; 951 952 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 953 " tx_ramstart=%#x tx_ramend=%#x\n", 954 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 955 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 956 957 /* Read and save PHY type */ 958 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 959 960 /* Set PHY address */ 961 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 962 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 963 /* not initialized, punt */ 964 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 965 966 sc->sk_coppertype = 1; 967 } 968 969 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 970 971 if (!(sc->sk_coppertype)) 972 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 973 974 /* Allocate the descriptor queues. */ 975 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 976 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 977 aprint_error(": can't alloc rx buffers\n"); 978 goto fail; 979 } 980 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 981 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 982 aprint_error(": can't map dma buffers (%zu bytes)\n", 983 sizeof(struct msk_ring_data)); 984 goto fail_1; 985 } 986 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 987 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 988 &sc_if->sk_ring_map)) { 989 aprint_error(": can't create dma map\n"); 990 goto fail_2; 991 } 992 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 993 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 994 aprint_error(": can't load dma map\n"); 995 goto fail_3; 996 } 997 sc_if->sk_rdata = (struct msk_ring_data *)kva; 998 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 999 1000 ifp = &sc_if->sk_ethercom.ec_if; 1001 /* Try to allocate memory for jumbo buffers. */ 1002 if (msk_alloc_jumbo_mem(sc_if)) { 1003 aprint_error(": jumbo buffer allocation failed\n"); 1004 goto fail_3; 1005 } 1006 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1007 | ETHERCAP_JUMBO_MTU; 1008 1009 ifp->if_softc = sc_if; 1010 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1011 ifp->if_ioctl = msk_ioctl; 1012 ifp->if_start = msk_start; 1013 ifp->if_stop = msk_stop; 1014 ifp->if_init = msk_init; 1015 ifp->if_watchdog = msk_watchdog; 1016 ifp->if_baudrate = 1000000000; 1017 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1018 IFQ_SET_READY(&ifp->if_snd); 1019 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1020 1021 /* 1022 * Do miibus setup. 1023 */ 1024 msk_init_yukon(sc_if); 1025 1026 DPRINTFN(2, ("msk_attach: 1\n")); 1027 1028 sc_if->sk_mii.mii_ifp = ifp; 1029 sc_if->sk_mii.mii_readreg = msk_marv_miibus_readreg; 1030 sc_if->sk_mii.mii_writereg = msk_marv_miibus_writereg; 1031 sc_if->sk_mii.mii_statchg = msk_marv_miibus_statchg; 1032 1033 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1034 msk_ifmedia_upd, msk_ifmedia_sts); 1035 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1036 MII_OFFSET_ANY, 0); 1037 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1038 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1039 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1040 0, NULL); 1041 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1042 } else 1043 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1044 1045 callout_init(&sc_if->sk_tick_ch); 1046 callout_setfunc(&sc_if->sk_tick_ch, msk_yukon_tick, sc_if); 1047 callout_schedule(&sc_if->sk_tick_ch, hz); 1048 1049 /* 1050 * Call MI attach routines. 1051 */ 1052 if_attach(ifp); 1053 ether_ifattach(ifp, sc_if->sk_enaddr); 1054 1055 shutdownhook_establish(mskc_shutdown, sc); 1056 1057 #if NRND > 0 1058 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1059 RND_TYPE_NET, 0); 1060 #endif 1061 1062 DPRINTFN(2, ("msk_attach: end\n")); 1063 return; 1064 1065 fail_3: 1066 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1067 fail_2: 1068 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1069 fail_1: 1070 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1071 fail: 1072 sc->sk_if[sa->skc_port] = NULL; 1073 } 1074 1075 int 1076 mskcprint(void *aux, const char *pnp) 1077 { 1078 struct skc_attach_args *sa = aux; 1079 1080 if (pnp) 1081 aprint_normal("sk port %c at %s", 1082 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1083 else 1084 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1085 return (UNCONF); 1086 } 1087 1088 /* 1089 * Attach the interface. Allocate softc structures, do ifmedia 1090 * setup and ethernet/BPF attach. 1091 */ 1092 void 1093 mskc_attach(struct device *parent, struct device *self, void *aux) 1094 { 1095 struct sk_softc *sc = (struct sk_softc *)self; 1096 struct pci_attach_args *pa = aux; 1097 struct skc_attach_args skca; 1098 pci_chipset_tag_t pc = pa->pa_pc; 1099 pcireg_t command, memtype; 1100 pci_intr_handle_t ih; 1101 const char *intrstr = NULL; 1102 bus_size_t size; 1103 int rc, sk_nodenum; 1104 u_int8_t hw, skrs; 1105 const char *revstr = NULL; 1106 const struct sysctlnode *node; 1107 caddr_t kva; 1108 bus_dma_segment_t seg; 1109 int rseg; 1110 1111 DPRINTFN(2, ("begin mskc_attach\n")); 1112 1113 /* 1114 * Handle power management nonsense. 1115 */ 1116 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1117 1118 if (command == 0x01) { 1119 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1120 if (command & SK_PSTATE_MASK) { 1121 u_int32_t iobase, membase, irq; 1122 1123 /* Save important PCI config data. */ 1124 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1125 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1126 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1127 1128 /* Reset the power state. */ 1129 aprint_normal("%s chip is in D%d power mode " 1130 "-- setting to D0\n", sc->sk_dev.dv_xname, 1131 command & SK_PSTATE_MASK); 1132 command &= 0xFFFFFFFC; 1133 pci_conf_write(pc, pa->pa_tag, 1134 SK_PCI_PWRMGMTCTRL, command); 1135 1136 /* Restore PCI config data. */ 1137 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1138 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1139 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1140 } 1141 } 1142 1143 /* 1144 * Map control/status registers. 1145 */ 1146 1147 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1148 switch (memtype) { 1149 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1150 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1151 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1152 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1153 NULL, &size) == 0) 1154 break; 1155 default: 1156 aprint_error(": can't map mem space\n"); 1157 return; 1158 } 1159 1160 sc->sc_dmatag = pa->pa_dmat; 1161 1162 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1163 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1164 1165 /* bail out here if chip is not recognized */ 1166 if (!(SK_IS_YUKON(sc))) { 1167 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1168 goto fail_1; 1169 } 1170 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1171 1172 /* Allocate interrupt */ 1173 if (pci_intr_map(pa, &ih)) { 1174 aprint_error(": couldn't map interrupt\n"); 1175 goto fail_1; 1176 } 1177 1178 intrstr = pci_intr_string(pc, ih); 1179 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1180 if (sc->sk_intrhand == NULL) { 1181 aprint_error(": couldn't establish interrupt"); 1182 if (intrstr != NULL) 1183 aprint_error(" at %s", intrstr); 1184 aprint_error("\n"); 1185 goto fail_1; 1186 } 1187 1188 if (bus_dmamem_alloc(sc->sc_dmatag, 1189 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1190 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1191 aprint_error(": can't alloc status buffers\n"); 1192 goto fail_2; 1193 } 1194 1195 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1196 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1197 &kva, BUS_DMA_NOWAIT)) { 1198 aprint_error(": can't map dma buffers (%zu bytes)\n", 1199 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1200 goto fail_3; 1201 } 1202 if (bus_dmamap_create(sc->sc_dmatag, 1203 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1204 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1205 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1206 aprint_error(": can't create dma map\n"); 1207 goto fail_4; 1208 } 1209 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1210 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1211 NULL, BUS_DMA_NOWAIT)) { 1212 aprint_error(": can't load dma map\n"); 1213 goto fail_5; 1214 } 1215 sc->sk_status_ring = (struct msk_status_desc *)kva; 1216 bzero(sc->sk_status_ring, 1217 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1218 1219 /* Reset the adapter. */ 1220 msk_reset(sc); 1221 1222 skrs = sk_win_read_1(sc, SK_EPROM0); 1223 if (skrs == 0x00) 1224 sc->sk_ramsize = 0x20000; 1225 else 1226 sc->sk_ramsize = skrs * (1<<12); 1227 sc->sk_rboff = SK_RBOFF_0; 1228 1229 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1230 sc->sk_ramsize, sc->sk_ramsize / 1024, 1231 sc->sk_rboff)); 1232 1233 /* Read and save physical media type */ 1234 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1235 1236 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1' || 1237 (SK_IS_YUKON2(sc) && !(sc->sk_pmd == 'L' || 1238 sc->sk_pmd == 'S'))) 1239 sc->sk_coppertype = 1; 1240 else 1241 sc->sk_coppertype = 0; 1242 1243 switch (sc->sk_type) { 1244 case SK_YUKON_XL: 1245 sc->sk_name = "Marvell Yukon-2 XL"; 1246 break; 1247 case SK_YUKON_EC_U: 1248 sc->sk_name = "Marvell Yukon-2 EC Ultra"; 1249 break; 1250 case SK_YUKON_EC: 1251 sc->sk_name = "Marvell Yukon-2 EC"; 1252 break; 1253 case SK_YUKON_FE: 1254 sc->sk_name = "Marvell Yukon-2 FE"; 1255 break; 1256 default: 1257 sc->sk_name = "Marvell Yukon (Unknown)"; 1258 } 1259 1260 if (sc->sk_type == SK_YUKON_XL) { 1261 switch (sc->sk_rev) { 1262 case SK_YUKON_XL_REV_A0: 1263 revstr = "A0"; 1264 break; 1265 case SK_YUKON_XL_REV_A1: 1266 revstr = "A1"; 1267 break; 1268 case SK_YUKON_XL_REV_A2: 1269 revstr = "A2"; 1270 break; 1271 case SK_YUKON_XL_REV_A3: 1272 revstr = "A3"; 1273 break; 1274 default: 1275 ; 1276 } 1277 } 1278 1279 if (sc->sk_type == SK_YUKON_EC) { 1280 switch (sc->sk_rev) { 1281 case SK_YUKON_EC_REV_A1: 1282 revstr = "A1"; 1283 break; 1284 case SK_YUKON_EC_REV_A2: 1285 revstr = "A2"; 1286 break; 1287 case SK_YUKON_EC_REV_A3: 1288 revstr = "A3"; 1289 break; 1290 default: 1291 ; 1292 } 1293 } 1294 1295 if (sc->sk_type == SK_YUKON_EC_U) { 1296 switch (sc->sk_rev) { 1297 case SK_YUKON_EC_U_REV_A0: 1298 revstr = "A0"; 1299 break; 1300 case SK_YUKON_EC_U_REV_A1: 1301 revstr = "A1"; 1302 break; 1303 default: 1304 ; 1305 } 1306 } 1307 1308 /* Announce the product name. */ 1309 aprint_normal(", %s", sc->sk_name); 1310 if (revstr != NULL) 1311 aprint_normal(" rev. %s", revstr); 1312 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1313 1314 1315 sc->sk_macs = 1; 1316 1317 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1318 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1319 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1320 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1321 sc->sk_macs++; 1322 } 1323 1324 skca.skc_port = SK_PORT_A; 1325 skca.skc_type = sc->sk_type; 1326 skca.skc_rev = sc->sk_rev; 1327 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1328 1329 if (sc->sk_macs > 1) { 1330 skca.skc_port = SK_PORT_B; 1331 skca.skc_type = sc->sk_type; 1332 skca.skc_rev = sc->sk_rev; 1333 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1334 } 1335 1336 /* Turn on the 'driver is loaded' LED. */ 1337 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1338 1339 /* skc sysctl setup */ 1340 1341 sc->sk_int_mod = SK_IM_DEFAULT; 1342 sc->sk_int_mod_pending = 0; 1343 1344 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1345 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1346 SYSCTL_DESCR("mskc per-controller controls"), 1347 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1348 CTL_EOL)) != 0) { 1349 aprint_normal("%s: couldn't create sysctl node\n", 1350 sc->sk_dev.dv_xname); 1351 goto fail_6; 1352 } 1353 1354 sk_nodenum = node->sysctl_num; 1355 1356 /* interrupt moderation time in usecs */ 1357 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1358 CTLFLAG_READWRITE, 1359 CTLTYPE_INT, "int_mod", 1360 SYSCTL_DESCR("msk interrupt moderation timer"), 1361 msk_sysctl_handler, 0, sc, 1362 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1363 CTL_EOL)) != 0) { 1364 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1365 sc->sk_dev.dv_xname); 1366 goto fail_6; 1367 } 1368 1369 return; 1370 1371 fail_6: 1372 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1373 fail_5: 1374 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1375 fail_4: 1376 bus_dmamem_unmap(sc->sc_dmatag, kva, 1377 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1378 fail_3: 1379 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1380 fail_2: 1381 pci_intr_disestablish(pc, sc->sk_intrhand); 1382 fail_1: 1383 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1384 } 1385 1386 int 1387 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1388 { 1389 struct sk_softc *sc = sc_if->sk_softc; 1390 struct msk_tx_desc *f = NULL; 1391 u_int32_t frag, cur, cnt = 0; 1392 int i; 1393 struct sk_txmap_entry *entry; 1394 bus_dmamap_t txmap; 1395 1396 DPRINTFN(2, ("msk_encap\n")); 1397 1398 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1399 if (entry == NULL) { 1400 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1401 return (ENOBUFS); 1402 } 1403 txmap = entry->dmamap; 1404 1405 cur = frag = *txidx; 1406 1407 #ifdef MSK_DEBUG 1408 if (mskdebug >= 2) 1409 msk_dump_mbuf(m_head); 1410 #endif 1411 1412 /* 1413 * Start packing the mbufs in this chain into 1414 * the fragment pointers. Stop when we run out 1415 * of fragments or hit the end of the mbuf chain. 1416 */ 1417 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1418 BUS_DMA_NOWAIT)) { 1419 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1420 return (ENOBUFS); 1421 } 1422 1423 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1424 1425 /* Sync the DMA map. */ 1426 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1427 BUS_DMASYNC_PREWRITE); 1428 1429 for (i = 0; i < txmap->dm_nsegs; i++) { 1430 if ((MSK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1431 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1432 return (ENOBUFS); 1433 } 1434 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1435 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1436 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1437 f->sk_ctl = 0; 1438 if (cnt == 0) 1439 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1440 else 1441 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1442 cur = frag; 1443 SK_INC(frag, MSK_TX_RING_CNT); 1444 cnt++; 1445 } 1446 1447 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1448 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1449 1450 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1451 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1452 1453 /* Sync descriptors before handing to chip */ 1454 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1455 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1456 1457 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1458 1459 /* Sync first descriptor to hand it off */ 1460 MSK_CDTXSYNC(sc_if, *txidx, 1, 1461 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1462 1463 sc_if->sk_cdata.sk_tx_cnt += cnt; 1464 1465 #ifdef MSK_DEBUG 1466 if (mskdebug >= 2) { 1467 struct msk_tx_desc *le; 1468 u_int32_t idx; 1469 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1470 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1471 msk_dump_txdesc(le, idx); 1472 } 1473 } 1474 #endif 1475 1476 *txidx = frag; 1477 1478 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1479 1480 return (0); 1481 } 1482 1483 void 1484 msk_start(struct ifnet *ifp) 1485 { 1486 struct sk_if_softc *sc_if = ifp->if_softc; 1487 struct mbuf *m_head = NULL; 1488 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1489 int pkts = 0; 1490 1491 DPRINTFN(2, ("msk_start\n")); 1492 1493 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1494 IFQ_POLL(&ifp->if_snd, m_head); 1495 if (m_head == NULL) 1496 break; 1497 1498 /* 1499 * Pack the data into the transmit ring. If we 1500 * don't have room, set the OACTIVE flag and wait 1501 * for the NIC to drain the ring. 1502 */ 1503 if (msk_encap(sc_if, m_head, &idx)) { 1504 ifp->if_flags |= IFF_OACTIVE; 1505 break; 1506 } 1507 1508 /* now we are committed to transmit the packet */ 1509 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1510 pkts++; 1511 1512 /* 1513 * If there's a BPF listener, bounce a copy of this frame 1514 * to him. 1515 */ 1516 #if NBPFILTER > 0 1517 if (ifp->if_bpf) 1518 bpf_mtap(ifp->if_bpf, m_head); 1519 #endif 1520 } 1521 if (pkts == 0) 1522 return; 1523 1524 /* Transmit */ 1525 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1526 sc_if->sk_cdata.sk_tx_prod = idx; 1527 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1528 1529 /* Set a timeout in case the chip goes out to lunch. */ 1530 ifp->if_timer = 5; 1531 } 1532 } 1533 1534 void 1535 msk_watchdog(struct ifnet *ifp) 1536 { 1537 struct sk_if_softc *sc_if = ifp->if_softc; 1538 1539 /* 1540 * Reclaim first as there is a possibility of losing Tx completion 1541 * interrupts. 1542 */ 1543 msk_txeof(sc_if); 1544 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1545 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1546 1547 ifp->if_oerrors++; 1548 1549 /* XXX Resets both ports; we shouldn't do that. */ 1550 msk_reset(sc_if->sk_softc); 1551 msk_init(ifp); 1552 } 1553 } 1554 1555 void 1556 mskc_shutdown(void *v) 1557 { 1558 struct sk_softc *sc = v; 1559 1560 DPRINTFN(2, ("msk_shutdown\n")); 1561 1562 /* Turn off the 'driver is loaded' LED. */ 1563 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1564 1565 msk_reset(sc); 1566 } 1567 1568 __inline int 1569 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1570 { 1571 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1572 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1573 YU_RXSTAT_JABBER)) != 0 || 1574 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1575 YU_RXSTAT_BYTES(stat) != len) 1576 return (0); 1577 1578 return (1); 1579 } 1580 1581 void 1582 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1583 { 1584 struct sk_softc *sc = sc_if->sk_softc; 1585 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1586 struct mbuf *m; 1587 struct sk_chain *cur_rx; 1588 int cur, total_len = len; 1589 bus_dmamap_t dmamap; 1590 1591 DPRINTFN(2, ("msk_rxeof\n")); 1592 1593 cur = sc_if->sk_cdata.sk_rx_cons; 1594 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1595 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1596 1597 /* Sync the descriptor */ 1598 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1599 1600 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1601 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1602 1603 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1604 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1605 1606 m = cur_rx->sk_mbuf; 1607 cur_rx->sk_mbuf = NULL; 1608 1609 if (total_len < SK_MIN_FRAMELEN || 1610 total_len > SK_JUMBO_FRAMELEN || 1611 msk_rxvalid(sc, rxstat, total_len) == 0) { 1612 ifp->if_ierrors++; 1613 msk_newbuf(sc_if, cur, m, dmamap); 1614 return; 1615 } 1616 1617 /* 1618 * Try to allocate a new jumbo buffer. If that fails, copy the 1619 * packet to mbufs and put the jumbo buffer back in the ring 1620 * so it can be re-used. If allocating mbufs fails, then we 1621 * have to drop the packet. 1622 */ 1623 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1624 struct mbuf *m0; 1625 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1626 total_len + ETHER_ALIGN, 0, ifp, NULL); 1627 msk_newbuf(sc_if, cur, m, dmamap); 1628 if (m0 == NULL) { 1629 ifp->if_ierrors++; 1630 return; 1631 } 1632 m_adj(m0, ETHER_ALIGN); 1633 m = m0; 1634 } else { 1635 m->m_pkthdr.rcvif = ifp; 1636 m->m_pkthdr.len = m->m_len = total_len; 1637 } 1638 1639 ifp->if_ipackets++; 1640 1641 #if NBPFILTER > 0 1642 if (ifp->if_bpf) 1643 bpf_mtap(ifp->if_bpf, m); 1644 #endif 1645 1646 /* pass it on. */ 1647 (*ifp->if_input)(ifp, m); 1648 } 1649 1650 void 1651 msk_txeof(struct sk_if_softc *sc_if) 1652 { 1653 struct sk_softc *sc = sc_if->sk_softc; 1654 struct msk_tx_desc *cur_tx; 1655 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1656 u_int32_t idx, sk_ctl; 1657 struct sk_txmap_entry *entry; 1658 1659 DPRINTFN(2, ("msk_txeof\n")); 1660 1661 /* 1662 * Go through our tx ring and free mbufs for those 1663 * frames that have been sent. 1664 */ 1665 idx = sc_if->sk_cdata.sk_tx_cons; 1666 while (idx != sk_win_read_2(sc, SK_STAT_BMU_TXA1_RIDX)) { 1667 MSK_CDTXSYNC(sc_if, idx, 1, 1668 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1669 1670 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1671 sk_ctl = letoh32(cur_tx->sk_ctl); 1672 #ifdef MSK_DEBUG 1673 if (mskdebug >= 2) 1674 msk_dump_txdesc(cur_tx, idx); 1675 #endif 1676 if (sk_ctl & SK_TXCTL_LASTFRAG) 1677 ifp->if_opackets++; 1678 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1679 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1680 1681 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1682 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1683 1684 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1685 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1686 1687 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1688 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1689 link); 1690 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1691 } 1692 sc_if->sk_cdata.sk_tx_cnt--; 1693 SK_INC(idx, MSK_TX_RING_CNT); 1694 } 1695 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1696 1697 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1698 ifp->if_flags &= ~IFF_OACTIVE; 1699 1700 sc_if->sk_cdata.sk_tx_cons = idx; 1701 } 1702 1703 void 1704 msk_yukon_tick(void *xsc_if) 1705 { 1706 struct sk_if_softc *sc_if = xsc_if; 1707 struct mii_data *mii = &sc_if->sk_mii; 1708 1709 mii_tick(mii); 1710 callout_schedule(&sc_if->sk_tick_ch, hz); 1711 } 1712 1713 void 1714 msk_intr_yukon(struct sk_if_softc *sc_if) 1715 { 1716 u_int8_t status; 1717 1718 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1719 /* RX overrun */ 1720 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1721 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1722 SK_RFCTL_RX_FIFO_OVER); 1723 } 1724 /* TX underrun */ 1725 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1726 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1727 SK_TFCTL_TX_FIFO_UNDER); 1728 } 1729 1730 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1731 } 1732 1733 int 1734 msk_intr(void *xsc) 1735 { 1736 struct sk_softc *sc = xsc; 1737 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1738 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1739 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1740 int claimed = 0; 1741 u_int32_t status; 1742 u_int16_t idx; 1743 struct msk_status_desc *cur_st; 1744 1745 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1746 if (status == 0) { 1747 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1748 return (0); 1749 } 1750 1751 status = CSR_READ_4(sc, SK_ISR); 1752 1753 if (sc_if0 != NULL) 1754 ifp0 = &sc_if0->sk_ethercom.ec_if; 1755 if (sc_if1 != NULL) 1756 ifp1 = &sc_if1->sk_ethercom.ec_if; 1757 1758 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1759 (ifp0->if_flags & IFF_RUNNING)) { 1760 msk_intr_yukon(sc_if0); 1761 } 1762 1763 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1764 (ifp1->if_flags & IFF_RUNNING)) { 1765 msk_intr_yukon(sc_if1); 1766 } 1767 1768 idx = CSR_READ_2(sc, SK_STAT_BMU_PUTIDX); 1769 while (sc->sk_status_idx != idx) { 1770 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1771 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1772 1773 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1774 switch (cur_st->sk_opcode & ~SK_Y2_STOPC_OWN) { 1775 case SK_Y2_STOPC_RXSTAT: 1776 msk_rxeof(sc->sk_if[cur_st->sk_link], 1777 letoh16(cur_st->sk_len), 1778 letoh32(cur_st->sk_status)); 1779 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1780 SK_RXQ1_Y2_PREF_PUTIDX, 1781 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1782 break; 1783 case SK_Y2_STOPC_TXSTAT: 1784 msk_txeof(sc->sk_if[cur_st->sk_link]); 1785 break; 1786 default: 1787 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 1788 break; 1789 } 1790 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1791 idx = CSR_READ_2(sc, SK_STAT_BMU_PUTIDX); 1792 } 1793 1794 if (status & SK_Y2_IMR_BMU) { 1795 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1796 claimed = 1; 1797 } 1798 1799 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1800 1801 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1802 msk_start(ifp0); 1803 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1804 msk_start(ifp1); 1805 1806 #if NRND > 0 1807 if (RND_ENABLED(&sc->rnd_source)) 1808 rnd_add_uint32(&sc->rnd_source, status); 1809 #endif 1810 1811 if (sc->sk_int_mod_pending) 1812 msk_update_int_mod(sc); 1813 1814 return claimed; 1815 } 1816 1817 void 1818 msk_init_yukon(struct sk_if_softc *sc_if) 1819 { 1820 u_int32_t phy, v; 1821 u_int16_t reg; 1822 struct sk_softc *sc; 1823 int i; 1824 1825 sc = sc_if->sk_softc; 1826 1827 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1828 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1829 1830 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1831 1832 /* GMAC and GPHY Reset */ 1833 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1834 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1835 DELAY(1000); 1836 1837 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1838 1839 #if 0 1840 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 1841 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 1842 #else 1843 phy = SK_GPHY_ENA_PAUSE; 1844 #endif 1845 1846 if (sc->sk_coppertype) 1847 phy |= SK_GPHY_COPPER; 1848 else 1849 phy |= SK_GPHY_FIBER; 1850 1851 DPRINTFN(3, ("msk_init_yukon: phy=%#x\n", phy)); 1852 1853 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 1854 DELAY(1000); 1855 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 1856 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1857 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1858 1859 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1860 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1861 1862 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1863 1864 /* unused read of the interrupt source register */ 1865 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1866 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1867 1868 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1869 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1870 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1871 1872 /* MIB Counter Clear Mode set */ 1873 reg |= YU_PAR_MIB_CLR; 1874 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1875 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1876 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1877 1878 /* MIB Counter Clear Mode clear */ 1879 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1880 reg &= ~YU_PAR_MIB_CLR; 1881 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1882 1883 /* receive control reg */ 1884 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1885 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1886 1887 /* transmit parameter register */ 1888 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1889 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1890 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1891 1892 /* serial mode register */ 1893 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1894 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 1895 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 1896 YU_SMR_IPG_DATA(0x1e)); 1897 1898 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1899 /* Setup Yukon's address */ 1900 for (i = 0; i < 3; i++) { 1901 /* Write Source Address 1 (unicast filter) */ 1902 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1903 sc_if->sk_enaddr[i * 2] | 1904 sc_if->sk_enaddr[i * 2 + 1] << 8); 1905 } 1906 1907 for (i = 0; i < 3; i++) { 1908 reg = sk_win_read_2(sc_if->sk_softc, 1909 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1910 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1911 } 1912 1913 /* Set promiscuous mode */ 1914 msk_setpromisc(sc_if); 1915 1916 /* Set multicast filter */ 1917 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1918 msk_setmulti(sc_if); 1919 1920 /* enable interrupt mask for counter overflows */ 1921 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1922 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1923 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1924 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1925 1926 /* Configure RX MAC FIFO Flush Mask */ 1927 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1928 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1929 YU_RXSTAT_JABBER; 1930 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1931 1932 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 1933 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 1934 v = SK_TFCTL_OPERATION_ON; 1935 else 1936 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 1937 /* Configure RX MAC FIFO */ 1938 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1939 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 1940 1941 /* Increase flush threshould to 64 bytes */ 1942 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1943 SK_RFCTL_FIFO_THRESHOLD + 1); 1944 1945 /* Configure TX MAC FIFO */ 1946 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1947 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1948 1949 #if 1 1950 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1951 #endif 1952 DPRINTFN(6, ("msk_init_yukon: end\n")); 1953 } 1954 1955 /* 1956 * Note that to properly initialize any part of the GEnesis chip, 1957 * you first have to take it out of reset mode. 1958 */ 1959 int 1960 msk_init(struct ifnet *ifp) 1961 { 1962 struct sk_if_softc *sc_if = ifp->if_softc; 1963 struct sk_softc *sc = sc_if->sk_softc; 1964 struct mii_data *mii = &sc_if->sk_mii; 1965 int s; 1966 uint32_t imr, sk_imtimer_ticks; 1967 1968 1969 DPRINTFN(2, ("msk_init\n")); 1970 1971 s = splnet(); 1972 1973 /* Cancel pending I/O and free all RX/TX buffers. */ 1974 msk_stop(ifp,0); 1975 1976 /* Configure I2C registers */ 1977 1978 /* Configure XMAC(s) */ 1979 msk_init_yukon(sc_if); 1980 mii_mediachg(mii); 1981 1982 /* Configure transmit arbiter(s) */ 1983 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1984 #if 0 1985 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1986 #endif 1987 1988 /* Configure RAMbuffers */ 1989 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1990 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1991 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1992 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1993 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1994 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1995 1996 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 1997 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 1998 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 1999 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2000 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2001 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2002 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2003 2004 /* Configure BMUs */ 2005 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2006 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2007 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2008 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2009 2010 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2011 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2012 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2013 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2014 2015 /* Make sure the sync transmit queue is disabled. */ 2016 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2017 2018 /* Init descriptors */ 2019 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2020 aprint_error("%s: initialization failed: no " 2021 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2022 msk_stop(ifp,0); 2023 splx(s); 2024 return ENOBUFS; 2025 } 2026 2027 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2028 aprint_error("%s: initialization failed: no " 2029 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2030 msk_stop(ifp,0); 2031 splx(s); 2032 return ENOBUFS; 2033 } 2034 2035 /* Set interrupt moderation if changed via sysctl. */ 2036 switch (sc->sk_type) { 2037 case SK_YUKON_EC: 2038 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2039 break; 2040 default: 2041 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2042 } 2043 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2044 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2045 sk_win_write_4(sc, SK_IMTIMERINIT, 2046 SK_IM_USECS(sc->sk_int_mod)); 2047 aprint_verbose("%s: interrupt moderation is %d us\n", 2048 sc->sk_dev.dv_xname, sc->sk_int_mod); 2049 } 2050 2051 /* Initialize prefetch engine. */ 2052 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2053 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2054 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2055 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2056 MSK_RX_RING_ADDR(sc_if, 0)); 2057 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2058 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2059 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2060 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2061 2062 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2063 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2064 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2065 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2066 MSK_TX_RING_ADDR(sc_if, 0)); 2067 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2068 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2069 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2070 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2071 2072 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2073 sc_if->sk_cdata.sk_rx_prod); 2074 2075 /* Configure interrupt handling */ 2076 if (sc_if->sk_port == SK_PORT_A) 2077 sc->sk_intrmask |= SK_Y2_INTRS1; 2078 else 2079 sc->sk_intrmask |= SK_Y2_INTRS2; 2080 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2081 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2082 2083 ifp->if_flags |= IFF_RUNNING; 2084 ifp->if_flags &= ~IFF_OACTIVE; 2085 2086 callout_schedule(&sc_if->sk_tick_ch, hz); 2087 2088 splx(s); 2089 return 0; 2090 } 2091 2092 void 2093 msk_stop(struct ifnet *ifp, int disable) 2094 { 2095 struct sk_if_softc *sc_if = ifp->if_softc; 2096 struct sk_softc *sc = sc_if->sk_softc; 2097 struct sk_txmap_entry *dma; 2098 int i; 2099 2100 DPRINTFN(2, ("msk_stop\n")); 2101 2102 callout_stop(&sc_if->sk_tick_ch); 2103 2104 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2105 2106 /* Stop transfer of Tx descriptors */ 2107 2108 /* Stop transfer of Rx descriptors */ 2109 2110 /* Turn off various components of this interface. */ 2111 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2112 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2113 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2114 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2115 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2116 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2117 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2118 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2119 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2120 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2121 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2122 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2123 2124 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2125 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2126 2127 /* Disable interrupts */ 2128 if (sc_if->sk_port == SK_PORT_A) 2129 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2130 else 2131 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2132 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2133 2134 SK_XM_READ_2(sc_if, XM_ISR); 2135 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2136 2137 /* Free RX and TX mbufs still in the queues. */ 2138 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2139 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2140 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2141 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2142 } 2143 } 2144 2145 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2146 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2147 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2148 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2149 #if 1 2150 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2151 sc_if->sk_cdata.sk_tx_map[i], link); 2152 sc_if->sk_cdata.sk_tx_map[i] = 0; 2153 #endif 2154 } 2155 } 2156 2157 #if 1 2158 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2159 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2160 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2161 free(dma, M_DEVBUF); 2162 } 2163 #endif 2164 } 2165 2166 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2167 NULL, NULL); 2168 2169 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2170 NULL, NULL); 2171 2172 #ifdef MSK_DEBUG 2173 void 2174 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2175 { 2176 #define DESC_PRINT(X) \ 2177 if (X) \ 2178 printf("txdesc[%d]." #X "=%#x\n", \ 2179 idx, X); 2180 2181 DESC_PRINT(letoh32(le->sk_addr)); 2182 DESC_PRINT(letoh16(le->sk_len)); 2183 DESC_PRINT(le->sk_ctl); 2184 DESC_PRINT(le->sk_opcode); 2185 #undef DESC_PRINT 2186 } 2187 2188 void 2189 msk_dump_bytes(const char *data, int len) 2190 { 2191 int c, i, j; 2192 2193 for (i = 0; i < len; i += 16) { 2194 printf("%08x ", i); 2195 c = len - i; 2196 if (c > 16) c = 16; 2197 2198 for (j = 0; j < c; j++) { 2199 printf("%02x ", data[i + j] & 0xff); 2200 if ((j & 0xf) == 7 && j > 0) 2201 printf(" "); 2202 } 2203 2204 for (; j < 16; j++) 2205 printf(" "); 2206 printf(" "); 2207 2208 for (j = 0; j < c; j++) { 2209 int ch = data[i + j] & 0xff; 2210 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2211 } 2212 2213 printf("\n"); 2214 2215 if (c < 16) 2216 break; 2217 } 2218 } 2219 2220 void 2221 msk_dump_mbuf(struct mbuf *m) 2222 { 2223 int count = m->m_pkthdr.len; 2224 2225 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2226 2227 while (count > 0 && m) { 2228 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2229 m, m->m_data, m->m_len); 2230 msk_dump_bytes(mtod(m, char *), m->m_len); 2231 2232 count -= m->m_len; 2233 m = m->m_next; 2234 } 2235 } 2236 #endif 2237 2238 static int 2239 msk_sysctl_handler(SYSCTLFN_ARGS) 2240 { 2241 int error, t; 2242 struct sysctlnode node; 2243 struct sk_softc *sc; 2244 2245 node = *rnode; 2246 sc = node.sysctl_data; 2247 t = sc->sk_int_mod; 2248 node.sysctl_data = &t; 2249 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2250 if (error || newp == NULL) 2251 return error; 2252 2253 if (t < SK_IM_MIN || t > SK_IM_MAX) 2254 return EINVAL; 2255 2256 /* update the softc with sysctl-changed value, and mark 2257 for hardware update */ 2258 sc->sk_int_mod = t; 2259 sc->sk_int_mod_pending = 1; 2260 return 0; 2261 } 2262 2263 /* 2264 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2265 * set up in skc_attach() 2266 */ 2267 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2268 { 2269 int rc; 2270 const struct sysctlnode *node; 2271 2272 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2273 0, CTLTYPE_NODE, "hw", NULL, 2274 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2275 goto err; 2276 } 2277 2278 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2279 0, CTLTYPE_NODE, "msk", 2280 SYSCTL_DESCR("msk interface controls"), 2281 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2282 goto err; 2283 } 2284 2285 msk_root_num = node->sysctl_num; 2286 return; 2287 2288 err: 2289 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2290 } 2291
Indexes created Thu Oct 02 10:09:58 GMT 2025