if_msk.c revision 1.10.6.3
1 /* $NetBSD: if_msk.c,v 1.10.6.3 2008/01/09 01:53:48 matt Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.10.6.3 2008/01/09 01:53:48 matt Exp $"); 56 57 #include "bpfilter.h" 58 #include "rnd.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/device.h> 68 #include <sys/queue.h> 69 #include <sys/callout.h> 70 #include <sys/sysctl.h> 71 #include <sys/endian.h> 72 #ifdef __NetBSD__ 73 #define letoh16 htole16 74 #define letoh32 htole32 75 #endif 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 81 #include <net/if_media.h> 82 83 #if NBPFILTER > 0 84 #include <net/bpf.h> 85 #endif 86 #if NRND > 0 87 #include <sys/rnd.h> 88 #endif 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 #include <dev/mii/brgphyreg.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/pci/if_skreg.h> 99 #include <dev/pci/if_mskvar.h> 100 101 int mskc_probe(struct device *, struct cfdata *, void *); 102 void mskc_attach(struct device *, struct device *self, void *aux); 103 void mskc_shutdown(void *); 104 int msk_probe(struct device *, struct cfdata *, void *); 105 void msk_attach(struct device *, struct device *self, void *aux); 106 int mskcprint(void *, const char *); 107 int msk_intr(void *); 108 void msk_intr_yukon(struct sk_if_softc *); 109 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 110 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 111 void msk_txeof(struct sk_if_softc *, int); 112 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 113 void msk_start(struct ifnet *); 114 int msk_ioctl(struct ifnet *, u_long, void *); 115 int msk_init(struct ifnet *); 116 void msk_init_yukon(struct sk_if_softc *); 117 void msk_stop(struct ifnet *, int); 118 void msk_watchdog(struct ifnet *); 119 int msk_ifmedia_upd(struct ifnet *); 120 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 void msk_reset(struct sk_softc *); 122 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 123 int msk_alloc_jumbo_mem(struct sk_if_softc *); 124 void *msk_jalloc(struct sk_if_softc *); 125 void msk_jfree(struct mbuf *, void *, size_t, void *); 126 int msk_init_rx_ring(struct sk_if_softc *); 127 int msk_init_tx_ring(struct sk_if_softc *); 128 129 void msk_update_int_mod(struct sk_softc *); 130 131 int msk_miibus_readreg(struct device *, int, int); 132 void msk_miibus_writereg(struct device *, int, int, int); 133 void msk_miibus_statchg(struct device *); 134 135 void msk_setfilt(struct sk_if_softc *, void *, int); 136 void msk_setmulti(struct sk_if_softc *); 137 void msk_setpromisc(struct sk_if_softc *); 138 void msk_tick(void *); 139 140 /* #define MSK_DEBUG 1 */ 141 #ifdef MSK_DEBUG 142 #define DPRINTF(x) if (mskdebug) printf x 143 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 144 int mskdebug = MSK_DEBUG; 145 146 void msk_dump_txdesc(struct msk_tx_desc *, int); 147 void msk_dump_mbuf(struct mbuf *); 148 void msk_dump_bytes(const char *, int); 149 #else 150 #define DPRINTF(x) 151 #define DPRINTFN(n,x) 152 #endif 153 154 static int msk_sysctl_handler(SYSCTLFN_PROTO); 155 static int msk_root_num; 156 157 /* supported device vendors */ 158 static const struct msk_product { 159 pci_vendor_id_t msk_vendor; 160 pci_product_id_t msk_product; 161 } msk_products[] = { 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 190 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 191 }; 192 193 static inline u_int32_t 194 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 195 { 196 return CSR_READ_4(sc, reg); 197 } 198 199 static inline u_int16_t 200 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 201 { 202 return CSR_READ_2(sc, reg); 203 } 204 205 static inline u_int8_t 206 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_1(sc, reg); 209 } 210 211 static inline void 212 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 213 { 214 CSR_WRITE_4(sc, reg, x); 215 } 216 217 static inline void 218 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 219 { 220 CSR_WRITE_2(sc, reg, x); 221 } 222 223 static inline void 224 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 225 { 226 CSR_WRITE_1(sc, reg, x); 227 } 228 229 int 230 msk_miibus_readreg(struct device *dev, int phy, int reg) 231 { 232 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 233 u_int16_t val; 234 int i; 235 236 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 237 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 238 239 for (i = 0; i < SK_TIMEOUT; i++) { 240 DELAY(1); 241 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 242 if (val & YU_SMICR_READ_VALID) 243 break; 244 } 245 246 if (i == SK_TIMEOUT) { 247 aprint_error("%s: phy failed to come ready\n", 248 sc_if->sk_dev.dv_xname); 249 return (0); 250 } 251 252 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 253 SK_TIMEOUT)); 254 255 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 256 257 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 258 phy, reg, val)); 259 260 return (val); 261 } 262 263 void 264 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 265 { 266 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 267 int i; 268 269 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 270 phy, reg, val)); 271 272 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 273 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 274 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 275 276 for (i = 0; i < SK_TIMEOUT; i++) { 277 DELAY(1); 278 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 279 break; 280 } 281 282 if (i == SK_TIMEOUT) 283 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 284 } 285 286 void 287 msk_miibus_statchg(struct device *dev) 288 { 289 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 290 struct mii_data *mii = &sc_if->sk_mii; 291 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 292 int gpcr; 293 294 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 295 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 296 297 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 298 /* Set speed. */ 299 gpcr |= YU_GPCR_SPEED_DIS; 300 switch (IFM_SUBTYPE(mii->mii_media_active)) { 301 case IFM_1000_SX: 302 case IFM_1000_LX: 303 case IFM_1000_CX: 304 case IFM_1000_T: 305 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 306 break; 307 case IFM_100_TX: 308 gpcr |= YU_GPCR_SPEED; 309 break; 310 } 311 312 /* Set duplex. */ 313 gpcr |= YU_GPCR_DPLX_DIS; 314 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 315 gpcr |= YU_GPCR_DUPLEX; 316 317 /* Disable flow control. */ 318 gpcr |= YU_GPCR_FCTL_DIS; 319 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 320 } 321 322 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 323 324 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 325 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 326 } 327 328 #define HASH_BITS 6 329 330 void 331 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 332 { 333 char *addr = addrv; 334 int base = XM_RXFILT_ENTRY(slot); 335 336 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 337 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 338 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 339 } 340 341 void 342 msk_setmulti(struct sk_if_softc *sc_if) 343 { 344 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 345 u_int32_t hashes[2] = { 0, 0 }; 346 int h; 347 struct ethercom *ec = &sc_if->sk_ethercom; 348 struct ether_multi *enm; 349 struct ether_multistep step; 350 u_int16_t reg; 351 352 /* First, zot all the existing filters. */ 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 357 358 359 /* Now program new ones. */ 360 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 361 reg |= YU_RCR_UFLEN; 362 allmulti: 363 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 364 if ((ifp->if_flags & IFF_PROMISC) != 0) 365 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 366 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 367 hashes[0] = 0xFFFFFFFF; 368 hashes[1] = 0xFFFFFFFF; 369 } 370 } else { 371 /* First find the tail of the list. */ 372 ETHER_FIRST_MULTI(step, ec, enm); 373 while (enm != NULL) { 374 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 375 ETHER_ADDR_LEN)) { 376 ifp->if_flags |= IFF_ALLMULTI; 377 goto allmulti; 378 } 379 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 380 ((1 << HASH_BITS) - 1); 381 if (h < 32) 382 hashes[0] |= (1 << h); 383 else 384 hashes[1] |= (1 << (h - 32)); 385 386 ETHER_NEXT_MULTI(step, enm); 387 } 388 reg |= YU_RCR_MUFLEN; 389 } 390 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 395 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 396 } 397 398 void 399 msk_setpromisc(struct sk_if_softc *sc_if) 400 { 401 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 402 403 if (ifp->if_flags & IFF_PROMISC) 404 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 405 YU_RCR_UFLEN | YU_RCR_MUFLEN); 406 else 407 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 408 YU_RCR_UFLEN | YU_RCR_MUFLEN); 409 } 410 411 int 412 msk_init_rx_ring(struct sk_if_softc *sc_if) 413 { 414 struct msk_chain_data *cd = &sc_if->sk_cdata; 415 struct msk_ring_data *rd = sc_if->sk_rdata; 416 int i, nexti; 417 418 bzero((char *)rd->sk_rx_ring, 419 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 420 421 for (i = 0; i < MSK_RX_RING_CNT; i++) { 422 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 423 if (i == (MSK_RX_RING_CNT - 1)) 424 nexti = 0; 425 else 426 nexti = i + 1; 427 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 428 } 429 430 for (i = 0; i < MSK_RX_RING_CNT; i++) { 431 if (msk_newbuf(sc_if, i, NULL, 432 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 433 aprint_error("%s: failed alloc of %dth mbuf\n", 434 sc_if->sk_dev.dv_xname, i); 435 return (ENOBUFS); 436 } 437 } 438 439 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 440 sc_if->sk_cdata.sk_rx_cons = 0; 441 442 return (0); 443 } 444 445 int 446 msk_init_tx_ring(struct sk_if_softc *sc_if) 447 { 448 struct sk_softc *sc = sc_if->sk_softc; 449 struct msk_chain_data *cd = &sc_if->sk_cdata; 450 struct msk_ring_data *rd = sc_if->sk_rdata; 451 bus_dmamap_t dmamap; 452 struct sk_txmap_entry *entry; 453 int i, nexti; 454 455 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 456 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 457 458 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 459 for (i = 0; i < MSK_TX_RING_CNT; i++) { 460 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 461 if (i == (MSK_TX_RING_CNT - 1)) 462 nexti = 0; 463 else 464 nexti = i + 1; 465 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 466 467 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 468 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 469 return (ENOBUFS); 470 471 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 472 if (!entry) { 473 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 474 return (ENOBUFS); 475 } 476 entry->dmamap = dmamap; 477 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 478 } 479 480 sc_if->sk_cdata.sk_tx_prod = 0; 481 sc_if->sk_cdata.sk_tx_cons = 0; 482 sc_if->sk_cdata.sk_tx_cnt = 0; 483 484 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 485 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 486 487 return (0); 488 } 489 490 int 491 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 492 bus_dmamap_t dmamap) 493 { 494 struct mbuf *m_new = NULL; 495 struct sk_chain *c; 496 struct msk_rx_desc *r; 497 498 if (m == NULL) { 499 void *buf = NULL; 500 501 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 502 if (m_new == NULL) 503 return (ENOBUFS); 504 505 /* Allocate the jumbo buffer */ 506 buf = msk_jalloc(sc_if); 507 if (buf == NULL) { 508 m_freem(m_new); 509 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 510 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 511 return (ENOBUFS); 512 } 513 514 /* Attach the buffer to the mbuf */ 515 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 516 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 517 } else { 518 /* 519 * We're re-using a previously allocated mbuf; 520 * be sure to re-init pointers and lengths to 521 * default values. 522 */ 523 m_new = m; 524 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 525 m_new->m_data = m_new->m_ext.ext_buf; 526 } 527 m_adj(m_new, ETHER_ALIGN); 528 529 c = &sc_if->sk_cdata.sk_rx_chain[i]; 530 r = c->sk_le; 531 c->sk_mbuf = m_new; 532 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 533 (((vaddr_t)m_new->m_data 534 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 535 r->sk_len = htole16(SK_JLEN); 536 r->sk_ctl = 0; 537 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 538 539 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 540 541 return (0); 542 } 543 544 /* 545 * Memory management for jumbo frames. 546 */ 547 548 int 549 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 550 { 551 struct sk_softc *sc = sc_if->sk_softc; 552 char *ptr, *kva; 553 bus_dma_segment_t seg; 554 int i, rseg, state, error; 555 struct sk_jpool_entry *entry; 556 557 state = error = 0; 558 559 /* Grab a big chunk o' storage. */ 560 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 561 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 562 aprint_error(": can't alloc rx buffers"); 563 return (ENOBUFS); 564 } 565 566 state = 1; 567 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 568 BUS_DMA_NOWAIT)) { 569 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 570 error = ENOBUFS; 571 goto out; 572 } 573 574 state = 2; 575 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 576 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 577 aprint_error(": can't create dma map"); 578 error = ENOBUFS; 579 goto out; 580 } 581 582 state = 3; 583 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 584 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 585 aprint_error(": can't load dma map"); 586 error = ENOBUFS; 587 goto out; 588 } 589 590 state = 4; 591 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 592 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 593 594 LIST_INIT(&sc_if->sk_jfree_listhead); 595 LIST_INIT(&sc_if->sk_jinuse_listhead); 596 597 /* 598 * Now divide it up into 9K pieces and save the addresses 599 * in an array. 600 */ 601 ptr = sc_if->sk_cdata.sk_jumbo_buf; 602 for (i = 0; i < MSK_JSLOTS; i++) { 603 sc_if->sk_cdata.sk_jslots[i] = ptr; 604 ptr += SK_JLEN; 605 entry = malloc(sizeof(struct sk_jpool_entry), 606 M_DEVBUF, M_NOWAIT); 607 if (entry == NULL) { 608 sc_if->sk_cdata.sk_jumbo_buf = NULL; 609 aprint_error(": no memory for jumbo buffer queue!"); 610 error = ENOBUFS; 611 goto out; 612 } 613 entry->slot = i; 614 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 615 entry, jpool_entries); 616 } 617 out: 618 if (error != 0) { 619 switch (state) { 620 case 4: 621 bus_dmamap_unload(sc->sc_dmatag, 622 sc_if->sk_cdata.sk_rx_jumbo_map); 623 case 3: 624 bus_dmamap_destroy(sc->sc_dmatag, 625 sc_if->sk_cdata.sk_rx_jumbo_map); 626 case 2: 627 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 628 case 1: 629 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 630 break; 631 default: 632 break; 633 } 634 } 635 636 return (error); 637 } 638 639 /* 640 * Allocate a jumbo buffer. 641 */ 642 void * 643 msk_jalloc(struct sk_if_softc *sc_if) 644 { 645 struct sk_jpool_entry *entry; 646 647 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 648 649 if (entry == NULL) 650 return (NULL); 651 652 LIST_REMOVE(entry, jpool_entries); 653 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 654 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 655 } 656 657 /* 658 * Release a jumbo buffer. 659 */ 660 void 661 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 662 { 663 struct sk_jpool_entry *entry; 664 struct sk_if_softc *sc; 665 int i, s; 666 667 /* Extract the softc struct pointer. */ 668 sc = (struct sk_if_softc *)arg; 669 670 if (sc == NULL) 671 panic("msk_jfree: can't find softc pointer!"); 672 673 /* calculate the slot this buffer belongs to */ 674 i = ((vaddr_t)buf 675 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 676 677 if ((i < 0) || (i >= MSK_JSLOTS)) 678 panic("msk_jfree: asked to free buffer that we don't manage!"); 679 680 s = splvm(); 681 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 682 if (entry == NULL) 683 panic("msk_jfree: buffer not in use!"); 684 entry->slot = i; 685 LIST_REMOVE(entry, jpool_entries); 686 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 687 688 if (__predict_true(m != NULL)) 689 pool_cache_put(mb_cache, m); 690 splx(s); 691 } 692 693 /* 694 * Set media options. 695 */ 696 int 697 msk_ifmedia_upd(struct ifnet *ifp) 698 { 699 struct sk_if_softc *sc_if = ifp->if_softc; 700 701 mii_mediachg(&sc_if->sk_mii); 702 return (0); 703 } 704 705 /* 706 * Report current media status. 707 */ 708 void 709 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 710 { 711 struct sk_if_softc *sc_if = ifp->if_softc; 712 713 mii_pollstat(&sc_if->sk_mii); 714 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 715 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 716 } 717 718 int 719 msk_ioctl(struct ifnet *ifp, u_long command, void *data) 720 { 721 struct sk_if_softc *sc_if = ifp->if_softc; 722 struct ifreq *ifr = (struct ifreq *) data; 723 struct mii_data *mii; 724 int s, error = 0; 725 726 s = splnet(); 727 728 switch(command) { 729 case SIOCSIFMTU: 730 if (ifr->ifr_mtu < ETHERMIN) 731 return EINVAL; 732 else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) { 733 if (ifr->ifr_mtu > SK_JUMBO_MTU) 734 error = EINVAL; 735 } else if (ifr->ifr_mtu > ETHERMTU) 736 error = EINVAL; 737 ifp->if_mtu = ifr->ifr_mtu; 738 break; 739 case SIOCGIFMEDIA: 740 case SIOCSIFMEDIA: 741 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA\n")); 742 mii = &sc_if->sk_mii; 743 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 744 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA done\n")); 745 break; 746 default: 747 DPRINTFN(2, ("msk_ioctl ETHER\n")); 748 error = ether_ioctl(ifp, command, data); 749 750 if (error == ENETRESET) { 751 /* 752 * Multicast list has changed; set the hardware 753 * filter accordingly. 754 */ 755 if (ifp->if_flags & IFF_RUNNING) 756 msk_setmulti(sc_if); 757 error = 0; 758 } 759 break; 760 } 761 762 splx(s); 763 return (error); 764 } 765 766 void 767 msk_update_int_mod(struct sk_softc *sc) 768 { 769 u_int32_t imtimer_ticks; 770 771 /* 772 * Configure interrupt moderation. The moderation timer 773 * defers interrupts specified in the interrupt moderation 774 * timer mask based on the timeout specified in the interrupt 775 * moderation timer init register. Each bit in the timer 776 * register represents one tick, so to specify a timeout in 777 * microseconds, we have to multiply by the correct number of 778 * ticks-per-microsecond. 779 */ 780 switch (sc->sk_type) { 781 case SK_YUKON_EC: 782 case SK_YUKON_EC_U: 783 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 784 break; 785 case SK_YUKON_FE: 786 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 787 break; 788 case SK_YUKON_XL: 789 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 790 break; 791 default: 792 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 793 } 794 aprint_verbose("%s: interrupt moderation is %d us\n", 795 sc->sk_dev.dv_xname, sc->sk_int_mod); 796 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 797 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 798 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 799 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 800 sc->sk_int_mod_pending = 0; 801 } 802 803 static int 804 msk_lookup(const struct pci_attach_args *pa) 805 { 806 const struct msk_product *pmsk; 807 808 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 809 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 810 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 811 return 1; 812 } 813 return 0; 814 } 815 816 /* 817 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 818 * IDs against our list and return a device name if we find a match. 819 */ 820 int 821 mskc_probe(struct device *parent, struct cfdata *match, 822 void *aux) 823 { 824 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 825 826 return msk_lookup(pa); 827 } 828 829 /* 830 * Force the GEnesis into reset, then bring it out of reset. 831 */ 832 void msk_reset(struct sk_softc *sc) 833 { 834 u_int32_t imtimer_ticks, reg1; 835 int reg; 836 837 DPRINTFN(2, ("msk_reset\n")); 838 839 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 840 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 841 842 DELAY(1000); 843 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 844 DELAY(2); 845 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 846 sk_win_write_1(sc, SK_TESTCTL1, 2); 847 848 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 849 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 850 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 851 else 852 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 853 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 854 855 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 856 sk_win_write_1(sc, SK_Y2_CLKGATE, 857 SK_Y2_CLKGATE_LINK1_GATE_DIS | 858 SK_Y2_CLKGATE_LINK2_GATE_DIS | 859 SK_Y2_CLKGATE_LINK1_CORE_DIS | 860 SK_Y2_CLKGATE_LINK2_CORE_DIS | 861 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 862 else 863 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 864 865 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 866 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 867 DELAY(1000); 868 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 869 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 870 871 sk_win_write_1(sc, SK_TESTCTL1, 1); 872 873 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 874 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 875 CSR_READ_2(sc, SK_LINK_CTRL))); 876 877 /* Disable ASF */ 878 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 879 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 880 881 /* Clear I2C IRQ noise */ 882 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 883 884 /* Disable hardware timer */ 885 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 886 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 887 888 /* Disable descriptor polling */ 889 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 890 891 /* Disable time stamps */ 892 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 893 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 894 895 /* Enable RAM interface */ 896 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 897 for (reg = SK_TO0;reg <= SK_TO11; reg++) 898 sk_win_write_1(sc, reg, 36); 899 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 900 for (reg = SK_TO0;reg <= SK_TO11; reg++) 901 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 902 903 /* 904 * Configure interrupt moderation. The moderation timer 905 * defers interrupts specified in the interrupt moderation 906 * timer mask based on the timeout specified in the interrupt 907 * moderation timer init register. Each bit in the timer 908 * register represents one tick, so to specify a timeout in 909 * microseconds, we have to multiply by the correct number of 910 * ticks-per-microsecond. 911 */ 912 switch (sc->sk_type) { 913 case SK_YUKON_EC: 914 case SK_YUKON_EC_U: 915 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 916 break; 917 case SK_YUKON_FE: 918 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 919 break; 920 case SK_YUKON_XL: 921 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 922 break; 923 default: 924 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 925 } 926 927 /* Reset status ring. */ 928 bzero((char *)sc->sk_status_ring, 929 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 930 sc->sk_status_idx = 0; 931 932 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 933 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 934 935 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 936 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 937 sc->sk_status_map->dm_segs[0].ds_addr); 938 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 939 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 940 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 941 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 942 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 943 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 944 } else { 945 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 946 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 947 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 948 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 949 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 950 } 951 952 #if 0 953 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 954 #endif 955 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 956 957 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 958 959 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 960 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 961 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 962 963 msk_update_int_mod(sc); 964 } 965 966 int 967 msk_probe(struct device *parent, struct cfdata *match, 968 void *aux) 969 { 970 struct skc_attach_args *sa = aux; 971 972 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 973 return (0); 974 975 switch (sa->skc_type) { 976 case SK_YUKON_XL: 977 case SK_YUKON_EC_U: 978 case SK_YUKON_EC: 979 case SK_YUKON_FE: 980 return (1); 981 } 982 983 return (0); 984 } 985 986 /* 987 * Each XMAC chip is attached as a separate logical IP interface. 988 * Single port cards will have only one logical interface of course. 989 */ 990 void 991 msk_attach(struct device *parent, struct device *self, void *aux) 992 { 993 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 994 struct sk_softc *sc = (struct sk_softc *)parent; 995 struct skc_attach_args *sa = aux; 996 struct ifnet *ifp; 997 void *kva; 998 bus_dma_segment_t seg; 999 int i, rseg; 1000 u_int32_t chunk, val; 1001 1002 sc_if->sk_port = sa->skc_port; 1003 sc_if->sk_softc = sc; 1004 sc->sk_if[sa->skc_port] = sc_if; 1005 1006 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1007 1008 /* 1009 * Get station address for this interface. Note that 1010 * dual port cards actually come with three station 1011 * addresses: one for each port, plus an extra. The 1012 * extra one is used by the SysKonnect driver software 1013 * as a 'virtual' station address for when both ports 1014 * are operating in failover mode. Currently we don't 1015 * use this extra address. 1016 */ 1017 for (i = 0; i < ETHER_ADDR_LEN; i++) 1018 sc_if->sk_enaddr[i] = 1019 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1020 1021 aprint_normal(": Ethernet address %s\n", 1022 ether_sprintf(sc_if->sk_enaddr)); 1023 1024 /* 1025 * Set up RAM buffer addresses. The NIC will have a certain 1026 * amount of SRAM on it, somewhere between 512K and 2MB. We 1027 * need to divide this up a) between the transmitter and 1028 * receiver and b) between the two XMACs, if this is a 1029 * dual port NIC. Our algorithm is to divide up the memory 1030 * evenly so that everyone gets a fair share. 1031 * 1032 * Just to be contrary, Yukon2 appears to have separate memory 1033 * for each MAC. 1034 */ 1035 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1036 val = sc->sk_rboff / sizeof(u_int64_t); 1037 sc_if->sk_rx_ramstart = val; 1038 val += (chunk / sizeof(u_int64_t)); 1039 sc_if->sk_rx_ramend = val - 1; 1040 chunk = sc->sk_ramsize - chunk; 1041 sc_if->sk_tx_ramstart = val; 1042 val += (chunk / sizeof(u_int64_t)); 1043 sc_if->sk_tx_ramend = val - 1; 1044 1045 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1046 " tx_ramstart=%#x tx_ramend=%#x\n", 1047 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1048 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1049 1050 /* Allocate the descriptor queues. */ 1051 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1052 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1053 aprint_error(": can't alloc rx buffers\n"); 1054 goto fail; 1055 } 1056 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1057 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1058 aprint_error(": can't map dma buffers (%zu bytes)\n", 1059 sizeof(struct msk_ring_data)); 1060 goto fail_1; 1061 } 1062 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1063 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1064 &sc_if->sk_ring_map)) { 1065 aprint_error(": can't create dma map\n"); 1066 goto fail_2; 1067 } 1068 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1069 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1070 aprint_error(": can't load dma map\n"); 1071 goto fail_3; 1072 } 1073 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1074 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1075 1076 ifp = &sc_if->sk_ethercom.ec_if; 1077 /* Try to allocate memory for jumbo buffers. */ 1078 if (msk_alloc_jumbo_mem(sc_if)) { 1079 aprint_error(": jumbo buffer allocation failed\n"); 1080 goto fail_3; 1081 } 1082 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1083 | ETHERCAP_JUMBO_MTU; 1084 1085 ifp->if_softc = sc_if; 1086 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1087 ifp->if_ioctl = msk_ioctl; 1088 ifp->if_start = msk_start; 1089 ifp->if_stop = msk_stop; 1090 ifp->if_init = msk_init; 1091 ifp->if_watchdog = msk_watchdog; 1092 ifp->if_baudrate = 1000000000; 1093 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1094 IFQ_SET_READY(&ifp->if_snd); 1095 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1096 1097 /* 1098 * Do miibus setup. 1099 */ 1100 msk_init_yukon(sc_if); 1101 1102 DPRINTFN(2, ("msk_attach: 1\n")); 1103 1104 sc_if->sk_mii.mii_ifp = ifp; 1105 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1106 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1107 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1108 1109 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1110 msk_ifmedia_upd, msk_ifmedia_sts); 1111 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1112 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1113 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1114 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1115 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1116 0, NULL); 1117 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1118 } else 1119 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1120 1121 callout_init(&sc_if->sk_tick_ch, 0); 1122 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1123 callout_schedule(&sc_if->sk_tick_ch, hz); 1124 1125 /* 1126 * Call MI attach routines. 1127 */ 1128 if_attach(ifp); 1129 ether_ifattach(ifp, sc_if->sk_enaddr); 1130 1131 shutdownhook_establish(mskc_shutdown, sc); 1132 1133 #if NRND > 0 1134 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1135 RND_TYPE_NET, 0); 1136 #endif 1137 1138 DPRINTFN(2, ("msk_attach: end\n")); 1139 return; 1140 1141 fail_3: 1142 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1143 fail_2: 1144 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1145 fail_1: 1146 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1147 fail: 1148 sc->sk_if[sa->skc_port] = NULL; 1149 } 1150 1151 int 1152 mskcprint(void *aux, const char *pnp) 1153 { 1154 struct skc_attach_args *sa = aux; 1155 1156 if (pnp) 1157 aprint_normal("sk port %c at %s", 1158 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1159 else 1160 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1161 return (UNCONF); 1162 } 1163 1164 /* 1165 * Attach the interface. Allocate softc structures, do ifmedia 1166 * setup and ethernet/BPF attach. 1167 */ 1168 void 1169 mskc_attach(struct device *parent, struct device *self, void *aux) 1170 { 1171 struct sk_softc *sc = (struct sk_softc *)self; 1172 struct pci_attach_args *pa = aux; 1173 struct skc_attach_args skca; 1174 pci_chipset_tag_t pc = pa->pa_pc; 1175 pcireg_t command, memtype; 1176 pci_intr_handle_t ih; 1177 const char *intrstr = NULL; 1178 bus_size_t size; 1179 int rc, sk_nodenum; 1180 u_int8_t hw, skrs; 1181 const char *revstr = NULL; 1182 const struct sysctlnode *node; 1183 void *kva; 1184 bus_dma_segment_t seg; 1185 int rseg; 1186 1187 DPRINTFN(2, ("begin mskc_attach\n")); 1188 1189 /* 1190 * Handle power management nonsense. 1191 */ 1192 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1193 1194 if (command == 0x01) { 1195 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1196 if (command & SK_PSTATE_MASK) { 1197 u_int32_t iobase, membase, irq; 1198 1199 /* Save important PCI config data. */ 1200 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1201 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1202 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1203 1204 /* Reset the power state. */ 1205 aprint_normal("%s chip is in D%d power mode " 1206 "-- setting to D0\n", sc->sk_dev.dv_xname, 1207 command & SK_PSTATE_MASK); 1208 command &= 0xFFFFFFFC; 1209 pci_conf_write(pc, pa->pa_tag, 1210 SK_PCI_PWRMGMTCTRL, command); 1211 1212 /* Restore PCI config data. */ 1213 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1214 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1215 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1216 } 1217 } 1218 1219 /* 1220 * Map control/status registers. 1221 */ 1222 1223 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1224 switch (memtype) { 1225 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1226 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1227 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1228 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1229 NULL, &size) == 0) 1230 break; 1231 default: 1232 aprint_error(": can't map mem space\n"); 1233 return; 1234 } 1235 1236 sc->sc_dmatag = pa->pa_dmat; 1237 1238 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1239 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1240 1241 /* bail out here if chip is not recognized */ 1242 if (!(SK_IS_YUKON2(sc))) { 1243 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1244 goto fail_1; 1245 } 1246 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1247 1248 /* Allocate interrupt */ 1249 if (pci_intr_map(pa, &ih)) { 1250 aprint_error(": couldn't map interrupt\n"); 1251 goto fail_1; 1252 } 1253 1254 intrstr = pci_intr_string(pc, ih); 1255 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1256 if (sc->sk_intrhand == NULL) { 1257 aprint_error(": couldn't establish interrupt"); 1258 if (intrstr != NULL) 1259 aprint_error(" at %s", intrstr); 1260 aprint_error("\n"); 1261 goto fail_1; 1262 } 1263 1264 if (bus_dmamem_alloc(sc->sc_dmatag, 1265 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1266 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1267 aprint_error(": can't alloc status buffers\n"); 1268 goto fail_2; 1269 } 1270 1271 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1272 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1273 &kva, BUS_DMA_NOWAIT)) { 1274 aprint_error(": can't map dma buffers (%zu bytes)\n", 1275 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1276 goto fail_3; 1277 } 1278 if (bus_dmamap_create(sc->sc_dmatag, 1279 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1280 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1281 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1282 aprint_error(": can't create dma map\n"); 1283 goto fail_4; 1284 } 1285 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1286 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1287 NULL, BUS_DMA_NOWAIT)) { 1288 aprint_error(": can't load dma map\n"); 1289 goto fail_5; 1290 } 1291 sc->sk_status_ring = (struct msk_status_desc *)kva; 1292 bzero(sc->sk_status_ring, 1293 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1294 1295 /* Reset the adapter. */ 1296 msk_reset(sc); 1297 1298 skrs = sk_win_read_1(sc, SK_EPROM0); 1299 if (skrs == 0x00) 1300 sc->sk_ramsize = 0x20000; 1301 else 1302 sc->sk_ramsize = skrs * (1<<12); 1303 sc->sk_rboff = SK_RBOFF_0; 1304 1305 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1306 sc->sk_ramsize, sc->sk_ramsize / 1024, 1307 sc->sk_rboff)); 1308 1309 switch (sc->sk_type) { 1310 case SK_YUKON_XL: 1311 sc->sk_name = "Yukon-2 XL"; 1312 break; 1313 case SK_YUKON_EC_U: 1314 sc->sk_name = "Yukon-2 EC Ultra"; 1315 break; 1316 case SK_YUKON_EC: 1317 sc->sk_name = "Yukon-2 EC"; 1318 break; 1319 case SK_YUKON_FE: 1320 sc->sk_name = "Yukon-2 FE"; 1321 break; 1322 default: 1323 sc->sk_name = "Yukon (Unknown)"; 1324 } 1325 1326 if (sc->sk_type == SK_YUKON_XL) { 1327 switch (sc->sk_rev) { 1328 case SK_YUKON_XL_REV_A0: 1329 sc->sk_workaround = 0; 1330 revstr = "A0"; 1331 break; 1332 case SK_YUKON_XL_REV_A1: 1333 sc->sk_workaround = SK_WA_4109; 1334 revstr = "A1"; 1335 break; 1336 case SK_YUKON_XL_REV_A2: 1337 sc->sk_workaround = SK_WA_4109; 1338 revstr = "A2"; 1339 break; 1340 case SK_YUKON_XL_REV_A3: 1341 sc->sk_workaround = SK_WA_4109; 1342 revstr = "A3"; 1343 break; 1344 default: 1345 sc->sk_workaround = 0; 1346 break; 1347 } 1348 } 1349 1350 if (sc->sk_type == SK_YUKON_EC) { 1351 switch (sc->sk_rev) { 1352 case SK_YUKON_EC_REV_A1: 1353 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1354 revstr = "A1"; 1355 break; 1356 case SK_YUKON_EC_REV_A2: 1357 sc->sk_workaround = SK_WA_4109; 1358 revstr = "A2"; 1359 break; 1360 case SK_YUKON_EC_REV_A3: 1361 sc->sk_workaround = SK_WA_4109; 1362 revstr = "A3"; 1363 break; 1364 default: 1365 sc->sk_workaround = 0; 1366 break; 1367 } 1368 } 1369 1370 if (sc->sk_type == SK_YUKON_FE) { 1371 sc->sk_workaround = SK_WA_4109; 1372 switch (sc->sk_rev) { 1373 case SK_YUKON_FE_REV_A1: 1374 revstr = "A1"; 1375 break; 1376 case SK_YUKON_FE_REV_A2: 1377 revstr = "A2"; 1378 break; 1379 default: 1380 sc->sk_workaround = 0; 1381 break; 1382 } 1383 } 1384 1385 if (sc->sk_type == SK_YUKON_EC_U) { 1386 sc->sk_workaround = SK_WA_4109; 1387 switch (sc->sk_rev) { 1388 case SK_YUKON_EC_U_REV_A0: 1389 revstr = "A0"; 1390 break; 1391 case SK_YUKON_EC_U_REV_A1: 1392 revstr = "A1"; 1393 break; 1394 case SK_YUKON_EC_U_REV_B0: 1395 revstr = "B0"; 1396 break; 1397 default: 1398 sc->sk_workaround = 0; 1399 break; 1400 } 1401 } 1402 1403 /* Announce the product name. */ 1404 aprint_normal(", %s", sc->sk_name); 1405 if (revstr != NULL) 1406 aprint_normal(" rev. %s", revstr); 1407 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1408 1409 sc->sk_macs = 1; 1410 1411 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1412 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1413 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1414 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1415 sc->sk_macs++; 1416 } 1417 1418 skca.skc_port = SK_PORT_A; 1419 skca.skc_type = sc->sk_type; 1420 skca.skc_rev = sc->sk_rev; 1421 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1422 1423 if (sc->sk_macs > 1) { 1424 skca.skc_port = SK_PORT_B; 1425 skca.skc_type = sc->sk_type; 1426 skca.skc_rev = sc->sk_rev; 1427 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1428 } 1429 1430 /* Turn on the 'driver is loaded' LED. */ 1431 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1432 1433 /* skc sysctl setup */ 1434 1435 sc->sk_int_mod = SK_IM_DEFAULT; 1436 sc->sk_int_mod_pending = 0; 1437 1438 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1439 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1440 SYSCTL_DESCR("mskc per-controller controls"), 1441 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1442 CTL_EOL)) != 0) { 1443 aprint_normal("%s: couldn't create sysctl node\n", 1444 sc->sk_dev.dv_xname); 1445 goto fail_6; 1446 } 1447 1448 sk_nodenum = node->sysctl_num; 1449 1450 /* interrupt moderation time in usecs */ 1451 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1452 CTLFLAG_READWRITE, 1453 CTLTYPE_INT, "int_mod", 1454 SYSCTL_DESCR("msk interrupt moderation timer"), 1455 msk_sysctl_handler, 0, sc, 1456 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1457 CTL_EOL)) != 0) { 1458 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1459 sc->sk_dev.dv_xname); 1460 goto fail_6; 1461 } 1462 1463 return; 1464 1465 fail_6: 1466 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1467 fail_5: 1468 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1469 fail_4: 1470 bus_dmamem_unmap(sc->sc_dmatag, kva, 1471 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1472 fail_3: 1473 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1474 fail_2: 1475 pci_intr_disestablish(pc, sc->sk_intrhand); 1476 fail_1: 1477 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1478 } 1479 1480 int 1481 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1482 { 1483 struct sk_softc *sc = sc_if->sk_softc; 1484 struct msk_tx_desc *f = NULL; 1485 u_int32_t frag, cur; 1486 int i; 1487 struct sk_txmap_entry *entry; 1488 bus_dmamap_t txmap; 1489 1490 DPRINTFN(2, ("msk_encap\n")); 1491 1492 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1493 if (entry == NULL) { 1494 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1495 return (ENOBUFS); 1496 } 1497 txmap = entry->dmamap; 1498 1499 cur = frag = *txidx; 1500 1501 #ifdef MSK_DEBUG 1502 if (mskdebug >= 2) 1503 msk_dump_mbuf(m_head); 1504 #endif 1505 1506 /* 1507 * Start packing the mbufs in this chain into 1508 * the fragment pointers. Stop when we run out 1509 * of fragments or hit the end of the mbuf chain. 1510 */ 1511 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1512 BUS_DMA_NOWAIT)) { 1513 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1514 return (ENOBUFS); 1515 } 1516 1517 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1518 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1519 bus_dmamap_unload(sc->sc_dmatag, txmap); 1520 return (ENOBUFS); 1521 } 1522 1523 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1524 1525 /* Sync the DMA map. */ 1526 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1527 BUS_DMASYNC_PREWRITE); 1528 1529 for (i = 0; i < txmap->dm_nsegs; i++) { 1530 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1531 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1532 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1533 f->sk_ctl = 0; 1534 if (i == 0) 1535 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1536 else 1537 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1538 cur = frag; 1539 SK_INC(frag, MSK_TX_RING_CNT); 1540 } 1541 1542 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1543 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1544 1545 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1546 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1547 1548 /* Sync descriptors before handing to chip */ 1549 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1550 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1551 1552 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1553 1554 /* Sync first descriptor to hand it off */ 1555 MSK_CDTXSYNC(sc_if, *txidx, 1, 1556 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1557 1558 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1559 1560 #ifdef MSK_DEBUG 1561 if (mskdebug >= 2) { 1562 struct msk_tx_desc *le; 1563 u_int32_t idx; 1564 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1565 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1566 msk_dump_txdesc(le, idx); 1567 } 1568 } 1569 #endif 1570 1571 *txidx = frag; 1572 1573 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1574 1575 return (0); 1576 } 1577 1578 void 1579 msk_start(struct ifnet *ifp) 1580 { 1581 struct sk_if_softc *sc_if = ifp->if_softc; 1582 struct mbuf *m_head = NULL; 1583 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1584 int pkts = 0; 1585 1586 DPRINTFN(2, ("msk_start\n")); 1587 1588 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1589 IFQ_POLL(&ifp->if_snd, m_head); 1590 if (m_head == NULL) 1591 break; 1592 1593 /* 1594 * Pack the data into the transmit ring. If we 1595 * don't have room, set the OACTIVE flag and wait 1596 * for the NIC to drain the ring. 1597 */ 1598 if (msk_encap(sc_if, m_head, &idx)) { 1599 ifp->if_flags |= IFF_OACTIVE; 1600 break; 1601 } 1602 1603 /* now we are committed to transmit the packet */ 1604 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1605 pkts++; 1606 1607 /* 1608 * If there's a BPF listener, bounce a copy of this frame 1609 * to him. 1610 */ 1611 #if NBPFILTER > 0 1612 if (ifp->if_bpf) 1613 bpf_mtap(ifp->if_bpf, m_head); 1614 #endif 1615 } 1616 if (pkts == 0) 1617 return; 1618 1619 /* Transmit */ 1620 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1621 sc_if->sk_cdata.sk_tx_prod = idx; 1622 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1623 1624 /* Set a timeout in case the chip goes out to lunch. */ 1625 ifp->if_timer = 5; 1626 } 1627 } 1628 1629 void 1630 msk_watchdog(struct ifnet *ifp) 1631 { 1632 struct sk_if_softc *sc_if = ifp->if_softc; 1633 u_int32_t reg; 1634 int idx; 1635 1636 /* 1637 * Reclaim first as there is a possibility of losing Tx completion 1638 * interrupts. 1639 */ 1640 if (sc_if->sk_port == SK_PORT_A) 1641 reg = SK_STAT_BMU_TXA1_RIDX; 1642 else 1643 reg = SK_STAT_BMU_TXA2_RIDX; 1644 1645 idx = sk_win_read_2(sc_if->sk_softc, reg); 1646 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1647 msk_txeof(sc_if, idx); 1648 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1649 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1650 1651 ifp->if_oerrors++; 1652 1653 /* XXX Resets both ports; we shouldn't do that. */ 1654 msk_reset(sc_if->sk_softc); 1655 msk_init(ifp); 1656 } 1657 } 1658 } 1659 1660 void 1661 mskc_shutdown(void *v) 1662 { 1663 struct sk_softc *sc = v; 1664 1665 DPRINTFN(2, ("msk_shutdown\n")); 1666 1667 /* Turn off the 'driver is loaded' LED. */ 1668 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1669 1670 msk_reset(sc); 1671 } 1672 1673 __inline int 1674 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1675 { 1676 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1677 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1678 YU_RXSTAT_JABBER)) != 0 || 1679 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1680 YU_RXSTAT_BYTES(stat) != len) 1681 return (0); 1682 1683 return (1); 1684 } 1685 1686 void 1687 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1688 { 1689 struct sk_softc *sc = sc_if->sk_softc; 1690 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1691 struct mbuf *m; 1692 struct sk_chain *cur_rx; 1693 int cur, total_len = len; 1694 bus_dmamap_t dmamap; 1695 1696 DPRINTFN(2, ("msk_rxeof\n")); 1697 1698 cur = sc_if->sk_cdata.sk_rx_cons; 1699 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1700 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1701 1702 /* Sync the descriptor */ 1703 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1704 1705 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1706 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1707 1708 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1709 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1710 1711 m = cur_rx->sk_mbuf; 1712 cur_rx->sk_mbuf = NULL; 1713 1714 if (total_len < SK_MIN_FRAMELEN || 1715 total_len > SK_JUMBO_FRAMELEN || 1716 msk_rxvalid(sc, rxstat, total_len) == 0) { 1717 ifp->if_ierrors++; 1718 msk_newbuf(sc_if, cur, m, dmamap); 1719 return; 1720 } 1721 1722 /* 1723 * Try to allocate a new jumbo buffer. If that fails, copy the 1724 * packet to mbufs and put the jumbo buffer back in the ring 1725 * so it can be re-used. If allocating mbufs fails, then we 1726 * have to drop the packet. 1727 */ 1728 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1729 struct mbuf *m0; 1730 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1731 total_len + ETHER_ALIGN, 0, ifp, NULL); 1732 msk_newbuf(sc_if, cur, m, dmamap); 1733 if (m0 == NULL) { 1734 ifp->if_ierrors++; 1735 return; 1736 } 1737 m_adj(m0, ETHER_ALIGN); 1738 m = m0; 1739 } else { 1740 m->m_pkthdr.rcvif = ifp; 1741 m->m_pkthdr.len = m->m_len = total_len; 1742 } 1743 1744 ifp->if_ipackets++; 1745 1746 #if NBPFILTER > 0 1747 if (ifp->if_bpf) 1748 bpf_mtap(ifp->if_bpf, m); 1749 #endif 1750 1751 /* pass it on. */ 1752 (*ifp->if_input)(ifp, m); 1753 } 1754 1755 void 1756 msk_txeof(struct sk_if_softc *sc_if, int idx) 1757 { 1758 struct sk_softc *sc = sc_if->sk_softc; 1759 struct msk_tx_desc *cur_tx; 1760 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1761 u_int32_t sk_ctl; 1762 struct sk_txmap_entry *entry; 1763 int cons, prog; 1764 1765 DPRINTFN(2, ("msk_txeof\n")); 1766 1767 /* 1768 * Go through our tx ring and free mbufs for those 1769 * frames that have been sent. 1770 */ 1771 cons = sc_if->sk_cdata.sk_tx_cons; 1772 prog = 0; 1773 while (cons != idx) { 1774 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1775 break; 1776 prog++; 1777 MSK_CDTXSYNC(sc_if, cons, 1, 1778 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1779 1780 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1781 sk_ctl = cur_tx->sk_ctl; 1782 #ifdef MSK_DEBUG 1783 if (mskdebug >= 2) 1784 msk_dump_txdesc(cur_tx, cons); 1785 #endif 1786 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1787 ifp->if_opackets++; 1788 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1789 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1790 1791 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1792 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1793 1794 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1795 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1796 link); 1797 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1798 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1799 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1800 } 1801 sc_if->sk_cdata.sk_tx_cnt--; 1802 SK_INC(cons, MSK_TX_RING_CNT); 1803 } 1804 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1805 1806 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1807 ifp->if_flags &= ~IFF_OACTIVE; 1808 1809 if (prog > 0) 1810 sc_if->sk_cdata.sk_tx_cons = cons; 1811 } 1812 1813 void 1814 msk_tick(void *xsc_if) 1815 { 1816 struct sk_if_softc *sc_if = xsc_if; 1817 struct mii_data *mii = &sc_if->sk_mii; 1818 1819 mii_tick(mii); 1820 callout_schedule(&sc_if->sk_tick_ch, hz); 1821 } 1822 1823 void 1824 msk_intr_yukon(struct sk_if_softc *sc_if) 1825 { 1826 u_int8_t status; 1827 1828 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1829 /* RX overrun */ 1830 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1831 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1832 SK_RFCTL_RX_FIFO_OVER); 1833 } 1834 /* TX underrun */ 1835 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1836 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1837 SK_TFCTL_TX_FIFO_UNDER); 1838 } 1839 1840 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1841 } 1842 1843 int 1844 msk_intr(void *xsc) 1845 { 1846 struct sk_softc *sc = xsc; 1847 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1848 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1849 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1850 int claimed = 0; 1851 u_int32_t status; 1852 struct msk_status_desc *cur_st; 1853 1854 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1855 if (status == 0) { 1856 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1857 return (0); 1858 } 1859 1860 status = CSR_READ_4(sc, SK_ISR); 1861 1862 if (sc_if0 != NULL) 1863 ifp0 = &sc_if0->sk_ethercom.ec_if; 1864 if (sc_if1 != NULL) 1865 ifp1 = &sc_if1->sk_ethercom.ec_if; 1866 1867 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1868 (ifp0->if_flags & IFF_RUNNING)) { 1869 msk_intr_yukon(sc_if0); 1870 } 1871 1872 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1873 (ifp1->if_flags & IFF_RUNNING)) { 1874 msk_intr_yukon(sc_if1); 1875 } 1876 1877 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1878 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1879 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1880 1881 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1882 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1883 switch (cur_st->sk_opcode) { 1884 case SK_Y2_STOPC_RXSTAT: 1885 msk_rxeof(sc->sk_if[cur_st->sk_link], 1886 letoh16(cur_st->sk_len), 1887 letoh32(cur_st->sk_status)); 1888 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1889 SK_RXQ1_Y2_PREF_PUTIDX, 1890 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1891 break; 1892 case SK_Y2_STOPC_TXSTAT: 1893 if (sc_if0) 1894 msk_txeof(sc_if0, 1895 letoh32(cur_st->sk_status) 1896 & SK_Y2_ST_TXA1_MSKL); 1897 if (sc_if1) 1898 msk_txeof(sc_if1, 1899 ((letoh32(cur_st->sk_status) 1900 & SK_Y2_ST_TXA2_MSKL) 1901 >> SK_Y2_ST_TXA2_SHIFTL) 1902 | ((letoh16(cur_st->sk_len) & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1903 break; 1904 default: 1905 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 1906 break; 1907 } 1908 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1909 1910 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1911 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1912 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1913 } 1914 1915 if (status & SK_Y2_IMR_BMU) { 1916 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1917 claimed = 1; 1918 } 1919 1920 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1921 1922 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1923 msk_start(ifp0); 1924 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1925 msk_start(ifp1); 1926 1927 #if NRND > 0 1928 if (RND_ENABLED(&sc->rnd_source)) 1929 rnd_add_uint32(&sc->rnd_source, status); 1930 #endif 1931 1932 if (sc->sk_int_mod_pending) 1933 msk_update_int_mod(sc); 1934 1935 return claimed; 1936 } 1937 1938 void 1939 msk_init_yukon(struct sk_if_softc *sc_if) 1940 { 1941 u_int32_t v; 1942 u_int16_t reg; 1943 struct sk_softc *sc; 1944 int i; 1945 1946 sc = sc_if->sk_softc; 1947 1948 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1949 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1950 1951 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1952 1953 /* GMAC and GPHY Reset */ 1954 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1955 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1956 DELAY(1000); 1957 1958 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1959 1960 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1961 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1962 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1963 1964 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1965 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1966 1967 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1968 1969 /* unused read of the interrupt source register */ 1970 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1971 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1972 1973 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1974 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1975 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1976 1977 /* MIB Counter Clear Mode set */ 1978 reg |= YU_PAR_MIB_CLR; 1979 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1980 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1981 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1982 1983 /* MIB Counter Clear Mode clear */ 1984 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1985 reg &= ~YU_PAR_MIB_CLR; 1986 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1987 1988 /* receive control reg */ 1989 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1990 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1991 1992 /* transmit control register */ 1993 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 1994 1995 /* transmit flow control register */ 1996 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 1997 1998 /* transmit parameter register */ 1999 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2000 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2001 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2002 2003 /* serial mode register */ 2004 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2005 reg = YU_SMR_DATA_BLIND(0x1c) | 2006 YU_SMR_MFL_VLAN | 2007 YU_SMR_IPG_DATA(0x1e); 2008 2009 if (sc->sk_type != SK_YUKON_FE) 2010 reg |= YU_SMR_MFL_JUMBO; 2011 2012 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2013 2014 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2015 /* Setup Yukon's address */ 2016 for (i = 0; i < 3; i++) { 2017 /* Write Source Address 1 (unicast filter) */ 2018 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2019 sc_if->sk_enaddr[i * 2] | 2020 sc_if->sk_enaddr[i * 2 + 1] << 8); 2021 } 2022 2023 for (i = 0; i < 3; i++) { 2024 reg = sk_win_read_2(sc_if->sk_softc, 2025 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2026 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2027 } 2028 2029 /* Set promiscuous mode */ 2030 msk_setpromisc(sc_if); 2031 2032 /* Set multicast filter */ 2033 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2034 msk_setmulti(sc_if); 2035 2036 /* enable interrupt mask for counter overflows */ 2037 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2038 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2039 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2040 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2041 2042 /* Configure RX MAC FIFO Flush Mask */ 2043 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2044 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2045 YU_RXSTAT_JABBER; 2046 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2047 2048 /* Configure RX MAC FIFO */ 2049 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2050 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2051 SK_RFCTL_FIFO_FLUSH_ON); 2052 2053 /* Increase flush threshould to 64 bytes */ 2054 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2055 SK_RFCTL_FIFO_THRESHOLD + 1); 2056 2057 /* Configure TX MAC FIFO */ 2058 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2059 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2060 2061 #if 1 2062 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2063 #endif 2064 DPRINTFN(6, ("msk_init_yukon: end\n")); 2065 } 2066 2067 /* 2068 * Note that to properly initialize any part of the GEnesis chip, 2069 * you first have to take it out of reset mode. 2070 */ 2071 int 2072 msk_init(struct ifnet *ifp) 2073 { 2074 struct sk_if_softc *sc_if = ifp->if_softc; 2075 struct sk_softc *sc = sc_if->sk_softc; 2076 struct mii_data *mii = &sc_if->sk_mii; 2077 int s; 2078 uint32_t imr, imtimer_ticks; 2079 2080 2081 DPRINTFN(2, ("msk_init\n")); 2082 2083 s = splnet(); 2084 2085 /* Cancel pending I/O and free all RX/TX buffers. */ 2086 msk_stop(ifp,0); 2087 2088 /* Configure I2C registers */ 2089 2090 /* Configure XMAC(s) */ 2091 msk_init_yukon(sc_if); 2092 mii_mediachg(mii); 2093 2094 /* Configure transmit arbiter(s) */ 2095 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2096 #if 0 2097 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2098 #endif 2099 2100 /* Configure RAMbuffers */ 2101 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2102 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2103 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2104 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2105 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2106 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2107 2108 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2109 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2110 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2111 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2112 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2113 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2114 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2115 2116 /* Configure BMUs */ 2117 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2118 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2119 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2120 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2121 2122 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2123 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2124 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2125 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2126 2127 /* Make sure the sync transmit queue is disabled. */ 2128 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2129 2130 /* Init descriptors */ 2131 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2132 aprint_error("%s: initialization failed: no " 2133 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2134 msk_stop(ifp,0); 2135 splx(s); 2136 return ENOBUFS; 2137 } 2138 2139 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2140 aprint_error("%s: initialization failed: no " 2141 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2142 msk_stop(ifp,0); 2143 splx(s); 2144 return ENOBUFS; 2145 } 2146 2147 /* Set interrupt moderation if changed via sysctl. */ 2148 switch (sc->sk_type) { 2149 case SK_YUKON_EC: 2150 case SK_YUKON_EC_U: 2151 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2152 break; 2153 case SK_YUKON_FE: 2154 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2155 break; 2156 case SK_YUKON_XL: 2157 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2158 break; 2159 default: 2160 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2161 } 2162 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2163 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2164 sk_win_write_4(sc, SK_IMTIMERINIT, 2165 SK_IM_USECS(sc->sk_int_mod)); 2166 aprint_verbose("%s: interrupt moderation is %d us\n", 2167 sc->sk_dev.dv_xname, sc->sk_int_mod); 2168 } 2169 2170 /* Initialize prefetch engine. */ 2171 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2172 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2173 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2174 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2175 MSK_RX_RING_ADDR(sc_if, 0)); 2176 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2177 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2178 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2179 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2180 2181 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2182 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2183 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2184 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2185 MSK_TX_RING_ADDR(sc_if, 0)); 2186 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2187 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2188 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2189 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2190 2191 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2192 sc_if->sk_cdata.sk_rx_prod); 2193 2194 /* Configure interrupt handling */ 2195 if (sc_if->sk_port == SK_PORT_A) 2196 sc->sk_intrmask |= SK_Y2_INTRS1; 2197 else 2198 sc->sk_intrmask |= SK_Y2_INTRS2; 2199 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2200 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2201 2202 ifp->if_flags |= IFF_RUNNING; 2203 ifp->if_flags &= ~IFF_OACTIVE; 2204 2205 callout_schedule(&sc_if->sk_tick_ch, hz); 2206 2207 splx(s); 2208 return 0; 2209 } 2210 2211 void 2212 msk_stop(struct ifnet *ifp, int disable) 2213 { 2214 struct sk_if_softc *sc_if = ifp->if_softc; 2215 struct sk_softc *sc = sc_if->sk_softc; 2216 struct sk_txmap_entry *dma; 2217 int i; 2218 2219 DPRINTFN(2, ("msk_stop\n")); 2220 2221 callout_stop(&sc_if->sk_tick_ch); 2222 2223 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2224 2225 /* Stop transfer of Tx descriptors */ 2226 2227 /* Stop transfer of Rx descriptors */ 2228 2229 /* Turn off various components of this interface. */ 2230 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2231 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2232 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2233 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2234 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2235 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2236 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2237 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2238 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2239 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2240 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2241 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2242 2243 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2244 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2245 2246 /* Disable interrupts */ 2247 if (sc_if->sk_port == SK_PORT_A) 2248 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2249 else 2250 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2251 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2252 2253 SK_XM_READ_2(sc_if, XM_ISR); 2254 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2255 2256 /* Free RX and TX mbufs still in the queues. */ 2257 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2258 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2259 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2260 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2261 } 2262 } 2263 2264 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2265 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2266 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2267 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2268 #if 1 2269 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2270 sc_if->sk_cdata.sk_tx_map[i], link); 2271 sc_if->sk_cdata.sk_tx_map[i] = 0; 2272 #endif 2273 } 2274 } 2275 2276 #if 1 2277 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2278 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2279 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2280 free(dma, M_DEVBUF); 2281 } 2282 #endif 2283 } 2284 2285 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2286 NULL, NULL); 2287 2288 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2289 NULL, NULL); 2290 2291 #ifdef MSK_DEBUG 2292 void 2293 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2294 { 2295 #define DESC_PRINT(X) \ 2296 if (X) \ 2297 printf("txdesc[%d]." #X "=%#x\n", \ 2298 idx, X); 2299 2300 DESC_PRINT(letoh32(le->sk_addr)); 2301 DESC_PRINT(letoh16(le->sk_len)); 2302 DESC_PRINT(le->sk_ctl); 2303 DESC_PRINT(le->sk_opcode); 2304 #undef DESC_PRINT 2305 } 2306 2307 void 2308 msk_dump_bytes(const char *data, int len) 2309 { 2310 int c, i, j; 2311 2312 for (i = 0; i < len; i += 16) { 2313 printf("%08x ", i); 2314 c = len - i; 2315 if (c > 16) c = 16; 2316 2317 for (j = 0; j < c; j++) { 2318 printf("%02x ", data[i + j] & 0xff); 2319 if ((j & 0xf) == 7 && j > 0) 2320 printf(" "); 2321 } 2322 2323 for (; j < 16; j++) 2324 printf(" "); 2325 printf(" "); 2326 2327 for (j = 0; j < c; j++) { 2328 int ch = data[i + j] & 0xff; 2329 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2330 } 2331 2332 printf("\n"); 2333 2334 if (c < 16) 2335 break; 2336 } 2337 } 2338 2339 void 2340 msk_dump_mbuf(struct mbuf *m) 2341 { 2342 int count = m->m_pkthdr.len; 2343 2344 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2345 2346 while (count > 0 && m) { 2347 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2348 m, m->m_data, m->m_len); 2349 msk_dump_bytes(mtod(m, char *), m->m_len); 2350 2351 count -= m->m_len; 2352 m = m->m_next; 2353 } 2354 } 2355 #endif 2356 2357 static int 2358 msk_sysctl_handler(SYSCTLFN_ARGS) 2359 { 2360 int error, t; 2361 struct sysctlnode node; 2362 struct sk_softc *sc; 2363 2364 node = *rnode; 2365 sc = node.sysctl_data; 2366 t = sc->sk_int_mod; 2367 node.sysctl_data = &t; 2368 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2369 if (error || newp == NULL) 2370 return error; 2371 2372 if (t < SK_IM_MIN || t > SK_IM_MAX) 2373 return EINVAL; 2374 2375 /* update the softc with sysctl-changed value, and mark 2376 for hardware update */ 2377 sc->sk_int_mod = t; 2378 sc->sk_int_mod_pending = 1; 2379 return 0; 2380 } 2381 2382 /* 2383 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2384 * set up in skc_attach() 2385 */ 2386 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2387 { 2388 int rc; 2389 const struct sysctlnode *node; 2390 2391 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2392 0, CTLTYPE_NODE, "hw", NULL, 2393 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2394 goto err; 2395 } 2396 2397 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2398 0, CTLTYPE_NODE, "msk", 2399 SYSCTL_DESCR("msk interface controls"), 2400 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2401 goto err; 2402 } 2403 2404 msk_root_num = node->sysctl_num; 2405 return; 2406 2407 err: 2408 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2409 } 2410
Indexes created Thu Oct 02 07:10:07 GMT 2025