if_msk.c revision 1.103
1 /* $NetBSD: if_msk.c,v 1.103 2020/04/28 17:26:01 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.103 2020/04/28 17:26:01 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 le16toh 72 #define letoh32 le32toh 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/pci/if_skreg.h> 92 #include <dev/pci/if_mskvar.h> 93 94 static int mskc_probe(device_t, cfdata_t, void *); 95 static void mskc_attach(device_t, device_t, void *); 96 static int mskc_detach(device_t, int); 97 static void mskc_reset(struct sk_softc *); 98 static bool mskc_suspend(device_t, const pmf_qual_t *); 99 static bool mskc_resume(device_t, const pmf_qual_t *); 100 static int msk_probe(device_t, cfdata_t, void *); 101 static void msk_attach(device_t, device_t, void *); 102 static int msk_detach(device_t, int); 103 static void msk_reset(struct sk_if_softc *); 104 static int mskcprint(void *, const char *); 105 static int msk_intr(void *); 106 static void msk_intr_yukon(struct sk_if_softc *); 107 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 108 static void msk_txeof(struct sk_if_softc *); 109 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 110 static void msk_start(struct ifnet *); 111 static int msk_ioctl(struct ifnet *, u_long, void *); 112 static int msk_init(struct ifnet *); 113 static void msk_init_yukon(struct sk_if_softc *); 114 static void msk_stop(struct ifnet *, int); 115 static void msk_watchdog(struct ifnet *); 116 static int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 117 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 118 static void *msk_jalloc(struct sk_if_softc *); 119 static void msk_jfree(struct mbuf *, void *, size_t, void *); 120 static int msk_init_rx_ring(struct sk_if_softc *); 121 static int msk_init_tx_ring(struct sk_if_softc *); 122 static void msk_fill_rx_ring(struct sk_if_softc *); 123 124 static void msk_update_int_mod(struct sk_softc *, int); 125 126 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 127 static int msk_miibus_writereg(device_t, int, int, uint16_t); 128 static void msk_miibus_statchg(struct ifnet *); 129 130 static void msk_setmulti(struct sk_if_softc *); 131 static void msk_setpromisc(struct sk_if_softc *); 132 static void msk_tick(void *); 133 static void msk_fill_rx_tick(void *); 134 135 /* #define MSK_DEBUG 1 */ 136 #ifdef MSK_DEBUG 137 #define DPRINTF(x) if (mskdebug) printf x 138 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 139 int mskdebug = MSK_DEBUG; 140 141 static void msk_dump_txdesc(struct msk_tx_desc *, int); 142 static void msk_dump_mbuf(struct mbuf *); 143 static void msk_dump_bytes(const char *, int); 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 static int msk_sysctl_handler(SYSCTLFN_PROTO); 150 static int msk_root_num; 151 152 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 153 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 199 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 201 { 0, 0 } 202 }; 203 204 static inline uint32_t 205 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 206 { 207 return CSR_READ_4(sc, reg); 208 } 209 210 static inline uint16_t 211 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 212 { 213 return CSR_READ_2(sc, reg); 214 } 215 216 static inline uint8_t 217 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 218 { 219 return CSR_READ_1(sc, reg); 220 } 221 222 static inline void 223 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 224 { 225 CSR_WRITE_4(sc, reg, x); 226 } 227 228 static inline void 229 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 230 { 231 CSR_WRITE_2(sc, reg, x); 232 } 233 234 static inline void 235 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 236 { 237 CSR_WRITE_1(sc, reg, x); 238 } 239 240 static int 241 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 242 { 243 struct sk_if_softc *sc_if = device_private(dev); 244 uint16_t data; 245 int i; 246 247 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 248 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 249 250 for (i = 0; i < SK_TIMEOUT; i++) { 251 DELAY(1); 252 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 253 if (data & YU_SMICR_READ_VALID) 254 break; 255 } 256 257 if (i == SK_TIMEOUT) { 258 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 259 return ETIMEDOUT; 260 } 261 262 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 263 264 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 265 266 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 267 phy, reg, *val)); 268 269 return 0; 270 } 271 272 static int 273 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 274 { 275 struct sk_if_softc *sc_if = device_private(dev); 276 int i; 277 278 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 279 phy, reg, val)); 280 281 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 282 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 283 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 284 285 for (i = 0; i < SK_TIMEOUT; i++) { 286 DELAY(1); 287 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 288 break; 289 } 290 291 if (i == SK_TIMEOUT) { 292 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 293 return ETIMEDOUT; 294 } 295 296 return 0; 297 } 298 299 static void 300 msk_miibus_statchg(struct ifnet *ifp) 301 { 302 struct sk_if_softc *sc_if = ifp->if_softc; 303 struct mii_data *mii = &sc_if->sk_mii; 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 int gpcr; 306 307 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 308 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 309 310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 311 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 312 /* Set speed. */ 313 gpcr |= YU_GPCR_SPEED_DIS; 314 switch (IFM_SUBTYPE(mii->mii_media_active)) { 315 case IFM_1000_SX: 316 case IFM_1000_LX: 317 case IFM_1000_CX: 318 case IFM_1000_T: 319 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 320 break; 321 case IFM_100_TX: 322 gpcr |= YU_GPCR_SPEED; 323 break; 324 } 325 326 /* Set duplex. */ 327 gpcr |= YU_GPCR_DPLX_DIS; 328 if ((mii->mii_media_active & IFM_FDX) != 0) 329 gpcr |= YU_GPCR_DUPLEX; 330 331 /* Disable flow control. */ 332 gpcr |= YU_GPCR_FCTL_DIS; 333 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 334 } 335 336 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 337 338 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 339 SK_YU_READ_2(sc_if, YUKON_GPCR))); 340 } 341 342 static void 343 msk_setmulti(struct sk_if_softc *sc_if) 344 { 345 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 346 uint32_t hashes[2] = { 0, 0 }; 347 int h; 348 struct ethercom *ec = &sc_if->sk_ethercom; 349 struct ether_multi *enm; 350 struct ether_multistep step; 351 uint16_t reg; 352 353 /* First, zot all the existing filters. */ 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 358 359 360 /* Now program new ones. */ 361 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 362 reg |= YU_RCR_UFLEN; 363 allmulti: 364 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 365 if ((ifp->if_flags & IFF_PROMISC) != 0) 366 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 367 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 368 hashes[0] = 0xFFFFFFFF; 369 hashes[1] = 0xFFFFFFFF; 370 } 371 } else { 372 /* First find the tail of the list. */ 373 ETHER_LOCK(ec); 374 ETHER_FIRST_MULTI(step, ec, enm); 375 while (enm != NULL) { 376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 377 ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 ETHER_UNLOCK(ec); 380 goto allmulti; 381 } 382 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 383 ((1 << SK_HASH_BITS) - 1); 384 if (h < 32) 385 hashes[0] |= (1 << h); 386 else 387 hashes[1] |= (1 << (h - 32)); 388 389 ETHER_NEXT_MULTI(step, enm); 390 } 391 ETHER_UNLOCK(ec); 392 reg |= YU_RCR_MUFLEN; 393 } 394 395 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 400 } 401 402 static void 403 msk_setpromisc(struct sk_if_softc *sc_if) 404 { 405 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 406 407 if (ifp->if_flags & IFF_PROMISC) 408 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 409 YU_RCR_UFLEN | YU_RCR_MUFLEN); 410 else 411 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 412 YU_RCR_UFLEN | YU_RCR_MUFLEN); 413 } 414 415 static int 416 msk_init_rx_ring(struct sk_if_softc *sc_if) 417 { 418 struct msk_chain_data *cd = &sc_if->sk_cdata; 419 struct msk_ring_data *rd = sc_if->sk_rdata; 420 struct msk_rx_desc *r; 421 int i; 422 423 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 424 425 for (i = 0; i < MSK_RX_RING_CNT; i++) { 426 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 427 } 428 429 sc_if->sk_cdata.sk_rx_prod = 0; 430 sc_if->sk_cdata.sk_rx_cons = 0; 431 sc_if->sk_cdata.sk_rx_cnt = 0; 432 sc_if->sk_cdata.sk_rx_hiaddr = 0; 433 434 /* Mark the first ring element to initialize the high address. */ 435 sc_if->sk_cdata.sk_rx_hiaddr = 0; 436 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 437 r->sk_addr = htole32(cd->sk_rx_hiaddr); 438 r->sk_len = 0; 439 r->sk_ctl = 0; 440 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 441 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 442 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 443 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 444 sc_if->sk_cdata.sk_rx_cnt++; 445 446 msk_fill_rx_ring(sc_if); 447 return 0; 448 } 449 450 static int 451 msk_init_tx_ring(struct sk_if_softc *sc_if) 452 { 453 struct msk_chain_data *cd = &sc_if->sk_cdata; 454 struct msk_ring_data *rd = sc_if->sk_rdata; 455 struct msk_tx_desc *t; 456 int i; 457 458 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 459 460 for (i = 0; i < MSK_TX_RING_CNT; i++) { 461 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 462 } 463 464 sc_if->sk_cdata.sk_tx_prod = 0; 465 sc_if->sk_cdata.sk_tx_cons = 0; 466 sc_if->sk_cdata.sk_tx_cnt = 0; 467 sc_if->sk_cdata.sk_tx_hiaddr = 0; 468 469 /* Mark the first ring element to initialize the high address. */ 470 sc_if->sk_cdata.sk_tx_hiaddr = 0; 471 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 472 t->sk_addr = htole32(cd->sk_tx_hiaddr); 473 t->sk_len = 0; 474 t->sk_ctl = 0; 475 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 476 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 477 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 478 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 479 sc_if->sk_cdata.sk_tx_cnt++; 480 481 return 0; 482 } 483 484 static int 485 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 486 { 487 struct mbuf *m_new = NULL; 488 struct sk_chain *c; 489 struct msk_rx_desc *r; 490 void *buf = NULL; 491 bus_addr_t addr; 492 493 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 494 if (m_new == NULL) 495 return ENOBUFS; 496 497 /* Allocate the jumbo buffer */ 498 buf = msk_jalloc(sc_if); 499 if (buf == NULL) { 500 m_freem(m_new); 501 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 502 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 503 return ENOBUFS; 504 } 505 506 /* Attach the buffer to the mbuf */ 507 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 508 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 509 510 m_adj(m_new, ETHER_ALIGN); 511 512 addr = dmamap->dm_segs[0].ds_addr + 513 ((vaddr_t)m_new->m_data - 514 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 515 516 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 517 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 518 r = c->sk_le; 519 c->sk_mbuf = NULL; 520 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 521 r->sk_len = 0; 522 r->sk_ctl = 0; 523 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 524 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 525 526 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 528 529 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 530 sc_if->sk_cdata.sk_rx_cnt++; 531 532 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 533 sc_if->sk_ethercom.ec_if.if_xname, 534 (unsigned)MSK_ADDR_HI(addr))); 535 } 536 537 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 538 r = c->sk_le; 539 c->sk_mbuf = m_new; 540 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 541 r->sk_len = htole16(SK_JLEN); 542 r->sk_ctl = 0; 543 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 544 545 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 546 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 547 548 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 549 sc_if->sk_cdata.sk_rx_cnt++; 550 551 return 0; 552 } 553 554 /* 555 * Memory management for jumbo frames. 556 */ 557 558 static int 559 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 560 { 561 struct sk_softc *sc = sc_if->sk_softc; 562 char *ptr, *kva; 563 int i, state, error; 564 struct sk_jpool_entry *entry; 565 566 state = error = 0; 567 568 /* Grab a big chunk o' storage. */ 569 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 570 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 571 BUS_DMA_NOWAIT)) { 572 aprint_error(": can't alloc rx buffers"); 573 return ENOBUFS; 574 } 575 576 state = 1; 577 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 578 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 579 BUS_DMA_NOWAIT)) { 580 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 581 error = ENOBUFS; 582 goto out; 583 } 584 585 state = 2; 586 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 587 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 588 aprint_error(": can't create dma map"); 589 error = ENOBUFS; 590 goto out; 591 } 592 593 state = 3; 594 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 595 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 596 aprint_error(": can't load dma map"); 597 error = ENOBUFS; 598 goto out; 599 } 600 601 state = 4; 602 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 603 DPRINTFN(1,("msk_jumbo_buf = %p\n", 604 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 605 606 LIST_INIT(&sc_if->sk_jfree_listhead); 607 LIST_INIT(&sc_if->sk_jinuse_listhead); 608 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 609 610 /* 611 * Now divide it up into 9K pieces and save the addresses 612 * in an array. 613 */ 614 ptr = sc_if->sk_cdata.sk_jumbo_buf; 615 for (i = 0; i < MSK_JSLOTS; i++) { 616 sc_if->sk_cdata.sk_jslots[i] = ptr; 617 ptr += SK_JLEN; 618 entry = malloc(sizeof(struct sk_jpool_entry), 619 M_DEVBUF, M_WAITOK); 620 entry->slot = i; 621 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 622 entry, jpool_entries); 623 } 624 out: 625 if (error != 0) { 626 switch (state) { 627 case 4: 628 bus_dmamap_unload(sc->sc_dmatag, 629 sc_if->sk_cdata.sk_rx_jumbo_map); 630 /* FALLTHROUGH */ 631 case 3: 632 bus_dmamap_destroy(sc->sc_dmatag, 633 sc_if->sk_cdata.sk_rx_jumbo_map); 634 /* FALLTHROUGH */ 635 case 2: 636 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 637 /* FALLTHROUGH */ 638 case 1: 639 bus_dmamem_free(sc->sc_dmatag, 640 &sc_if->sk_cdata.sk_jumbo_seg, 641 sc_if->sk_cdata.sk_jumbo_nseg); 642 break; 643 default: 644 break; 645 } 646 } 647 648 return error; 649 } 650 651 static void 652 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 653 { 654 struct sk_softc *sc = sc_if->sk_softc; 655 656 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 657 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 658 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 659 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 660 sc_if->sk_cdata.sk_jumbo_nseg); 661 } 662 663 /* 664 * Allocate a jumbo buffer. 665 */ 666 static void * 667 msk_jalloc(struct sk_if_softc *sc_if) 668 { 669 struct sk_jpool_entry *entry; 670 671 mutex_enter(&sc_if->sk_jpool_mtx); 672 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 673 674 if (entry == NULL) { 675 mutex_exit(&sc_if->sk_jpool_mtx); 676 return NULL; 677 } 678 679 LIST_REMOVE(entry, jpool_entries); 680 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 681 mutex_exit(&sc_if->sk_jpool_mtx); 682 return sc_if->sk_cdata.sk_jslots[entry->slot]; 683 } 684 685 /* 686 * Release a jumbo buffer. 687 */ 688 static void 689 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 690 { 691 struct sk_jpool_entry *entry; 692 struct sk_if_softc *sc; 693 int i; 694 695 /* Extract the softc struct pointer. */ 696 sc = (struct sk_if_softc *)arg; 697 698 if (sc == NULL) 699 panic("msk_jfree: can't find softc pointer!"); 700 701 /* calculate the slot this buffer belongs to */ 702 i = ((vaddr_t)buf 703 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 704 705 if ((i < 0) || (i >= MSK_JSLOTS)) 706 panic("msk_jfree: asked to free buffer that we don't manage!"); 707 708 mutex_enter(&sc->sk_jpool_mtx); 709 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 710 if (entry == NULL) 711 panic("msk_jfree: buffer not in use!"); 712 entry->slot = i; 713 LIST_REMOVE(entry, jpool_entries); 714 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 715 mutex_exit(&sc->sk_jpool_mtx); 716 717 if (__predict_true(m != NULL)) 718 pool_cache_put(mb_cache, m); 719 720 /* Now that we know we have a free RX buffer, refill if running out */ 721 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 722 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 723 callout_schedule(&sc->sk_tick_rx, 0); 724 } 725 726 static int 727 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 728 { 729 struct sk_if_softc *sc = ifp->if_softc; 730 int s, error; 731 732 s = splnet(); 733 734 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 735 switch (cmd) { 736 case SIOCSIFFLAGS: 737 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 738 break; 739 740 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 741 case IFF_RUNNING: 742 msk_stop(ifp, 1); 743 break; 744 case IFF_UP: 745 msk_init(ifp); 746 break; 747 case IFF_UP | IFF_RUNNING: 748 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 749 msk_setpromisc(sc); 750 msk_setmulti(sc); 751 } else 752 msk_init(ifp); 753 break; 754 } 755 sc->sk_if_flags = ifp->if_flags; 756 break; 757 default: 758 error = ether_ioctl(ifp, cmd, data); 759 if (error == ENETRESET) { 760 error = 0; 761 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 762 ; 763 else if (ifp->if_flags & IFF_RUNNING) { 764 /* 765 * Multicast list has changed; set the hardware 766 * filter accordingly. 767 */ 768 msk_setmulti(sc); 769 } 770 } 771 break; 772 } 773 774 splx(s); 775 return error; 776 } 777 778 static void 779 msk_update_int_mod(struct sk_softc *sc, int verbose) 780 { 781 uint32_t imtimer_ticks; 782 783 /* 784 * Configure interrupt moderation. The moderation timer 785 * defers interrupts specified in the interrupt moderation 786 * timer mask based on the timeout specified in the interrupt 787 * moderation timer init register. Each bit in the timer 788 * register represents one tick, so to specify a timeout in 789 * microseconds, we have to multiply by the correct number of 790 * ticks-per-microsecond. 791 */ 792 switch (sc->sk_type) { 793 case SK_YUKON_EC: 794 case SK_YUKON_EC_U: 795 case SK_YUKON_EX: 796 case SK_YUKON_SUPR: 797 case SK_YUKON_ULTRA2: 798 case SK_YUKON_OPTIMA: 799 case SK_YUKON_PRM: 800 case SK_YUKON_OPTIMA2: 801 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 802 break; 803 case SK_YUKON_FE: 804 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 805 break; 806 case SK_YUKON_FE_P: 807 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 808 break; 809 case SK_YUKON_XL: 810 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 811 break; 812 default: 813 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 814 } 815 if (verbose) 816 aprint_verbose_dev(sc->sk_dev, 817 "interrupt moderation is %d us\n", sc->sk_int_mod); 818 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 819 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 820 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 821 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 822 sc->sk_int_mod_pending = 0; 823 } 824 825 static int 826 msk_lookup(const struct pci_attach_args *pa) 827 { 828 const struct msk_product *pmsk; 829 830 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 831 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 832 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 833 return 1; 834 } 835 return 0; 836 } 837 838 /* 839 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 840 * IDs against our list and return a device name if we find a match. 841 */ 842 static int 843 mskc_probe(device_t parent, cfdata_t match, void *aux) 844 { 845 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 846 847 return msk_lookup(pa); 848 } 849 850 /* 851 * Force the GEnesis into reset, then bring it out of reset. 852 */ 853 static void 854 mskc_reset(struct sk_softc *sc) 855 { 856 uint32_t imtimer_ticks, reg1; 857 uint16_t status; 858 int reg; 859 860 DPRINTFN(2, ("mskc_reset\n")); 861 862 /* Disable ASF */ 863 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 864 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 865 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 866 /* Clear AHB bridge & microcontroller reset. */ 867 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 868 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 869 /* Clear ASF microcontroller state. */ 870 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 871 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 872 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 873 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 874 } else 875 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 876 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 877 878 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 879 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 880 881 DELAY(1000); 882 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 883 DELAY(2); 884 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 885 sk_win_write_1(sc, SK_TESTCTL1, 2); 886 887 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 888 sc->sk_type >= SK_YUKON_FE_P) { 889 uint32_t our; 890 891 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 892 893 /* enable all clocks. */ 894 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 895 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 896 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 897 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 898 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 899 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 900 /* Set all bits to 0 except bits 15..12 */ 901 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 902 /* Set to default value */ 903 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 904 905 /* 906 * Disable status race, workaround for Yukon EC Ultra & 907 * Yukon EX. 908 */ 909 reg1 = sk_win_read_4(sc, SK_GPIO); 910 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 911 sk_win_write_4(sc, SK_GPIO, reg1); 912 sk_win_read_4(sc, SK_GPIO); 913 } 914 915 /* release PHY from PowerDown/Coma mode. */ 916 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 917 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 918 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 919 else 920 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 921 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 922 923 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 924 sk_win_write_1(sc, SK_Y2_CLKGATE, 925 SK_Y2_CLKGATE_LINK1_GATE_DIS | 926 SK_Y2_CLKGATE_LINK2_GATE_DIS | 927 SK_Y2_CLKGATE_LINK1_CORE_DIS | 928 SK_Y2_CLKGATE_LINK2_CORE_DIS | 929 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 930 else 931 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 932 933 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 934 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 935 DELAY(1000); 936 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 937 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 938 939 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 940 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 941 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 942 } 943 944 sk_win_write_1(sc, SK_TESTCTL1, 1); 945 946 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 947 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 948 CSR_READ_2(sc, SK_LINK_CTRL))); 949 950 /* Clear I2C IRQ noise */ 951 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 952 953 /* Disable hardware timer */ 954 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 955 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 956 957 /* Disable descriptor polling */ 958 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 959 960 /* Disable time stamps */ 961 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 962 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 963 964 /* Enable RAM interface */ 965 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 966 for (reg = SK_TO0;reg <= SK_TO11; reg++) 967 sk_win_write_1(sc, reg, 36); 968 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 969 for (reg = SK_TO0;reg <= SK_TO11; reg++) 970 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 971 972 /* 973 * Configure interrupt moderation. The moderation timer 974 * defers interrupts specified in the interrupt moderation 975 * timer mask based on the timeout specified in the interrupt 976 * moderation timer init register. Each bit in the timer 977 * register represents one tick, so to specify a timeout in 978 * microseconds, we have to multiply by the correct number of 979 * ticks-per-microsecond. 980 */ 981 switch (sc->sk_type) { 982 case SK_YUKON_EC: 983 case SK_YUKON_EC_U: 984 case SK_YUKON_EX: 985 case SK_YUKON_SUPR: 986 case SK_YUKON_ULTRA2: 987 case SK_YUKON_OPTIMA: 988 case SK_YUKON_PRM: 989 case SK_YUKON_OPTIMA2: 990 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 991 break; 992 case SK_YUKON_FE: 993 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 994 break; 995 case SK_YUKON_FE_P: 996 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 997 break; 998 case SK_YUKON_XL: 999 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1000 break; 1001 default: 1002 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1003 break; 1004 } 1005 1006 /* Reset status ring. */ 1007 memset(sc->sk_status_ring, 0, 1008 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1009 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1010 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1011 sc->sk_status_idx = 0; 1012 1013 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1014 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1015 1016 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1017 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1018 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1019 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1020 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1021 if (sc->sk_type == SK_YUKON_EC && 1022 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1023 /* WA for dev. #4.3 */ 1024 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1025 SK_STAT_BMU_TXTHIDX_MSK); 1026 /* WA for dev. #4.18 */ 1027 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1028 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1029 } else { 1030 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1031 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1032 if (sc->sk_type == SK_YUKON_XL) 1033 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1034 else 1035 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1036 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1037 } 1038 1039 #if 0 1040 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1041 #endif 1042 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1043 1044 /* Enable status unit. */ 1045 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1046 1047 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1048 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1049 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1050 1051 msk_update_int_mod(sc, 0); 1052 } 1053 1054 static int 1055 msk_probe(device_t parent, cfdata_t match, void *aux) 1056 { 1057 struct skc_attach_args *sa = aux; 1058 1059 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1060 return 0; 1061 1062 switch (sa->skc_type) { 1063 case SK_YUKON_XL: 1064 case SK_YUKON_EC_U: 1065 case SK_YUKON_EX: 1066 case SK_YUKON_EC: 1067 case SK_YUKON_FE: 1068 case SK_YUKON_FE_P: 1069 case SK_YUKON_SUPR: 1070 case SK_YUKON_ULTRA2: 1071 case SK_YUKON_OPTIMA: 1072 case SK_YUKON_PRM: 1073 case SK_YUKON_OPTIMA2: 1074 return 1; 1075 } 1076 1077 return 0; 1078 } 1079 1080 static void 1081 msk_reset(struct sk_if_softc *sc_if) 1082 { 1083 /* GMAC and GPHY Reset */ 1084 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1085 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1086 DELAY(1000); 1087 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1088 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1089 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1090 } 1091 1092 static bool 1093 msk_resume(device_t dv, const pmf_qual_t *qual) 1094 { 1095 struct sk_if_softc *sc_if = device_private(dv); 1096 1097 msk_init_yukon(sc_if); 1098 return true; 1099 } 1100 1101 /* 1102 * Each XMAC chip is attached as a separate logical IP interface. 1103 * Single port cards will have only one logical interface of course. 1104 */ 1105 static void 1106 msk_attach(device_t parent, device_t self, void *aux) 1107 { 1108 struct sk_if_softc *sc_if = device_private(self); 1109 struct sk_softc *sc = device_private(parent); 1110 struct skc_attach_args *sa = aux; 1111 bus_dmamap_t dmamap; 1112 struct sk_txmap_entry *entry; 1113 struct ifnet *ifp; 1114 struct mii_data * const mii = &sc_if->sk_mii; 1115 void *kva; 1116 int i; 1117 uint32_t chunk; 1118 int mii_flags; 1119 1120 sc_if->sk_dev = self; 1121 sc_if->sk_port = sa->skc_port; 1122 sc_if->sk_softc = sc; 1123 sc->sk_if[sa->skc_port] = sc_if; 1124 1125 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1126 1127 /* 1128 * Get station address for this interface. Note that 1129 * dual port cards actually come with three station 1130 * addresses: one for each port, plus an extra. The 1131 * extra one is used by the SysKonnect driver software 1132 * as a 'virtual' station address for when both ports 1133 * are operating in failover mode. Currently we don't 1134 * use this extra address. 1135 */ 1136 for (i = 0; i < ETHER_ADDR_LEN; i++) 1137 sc_if->sk_enaddr[i] = 1138 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1139 1140 aprint_normal(": Ethernet address %s\n", 1141 ether_sprintf(sc_if->sk_enaddr)); 1142 1143 /* 1144 * Set up RAM buffer addresses. The Yukon2 has a small amount 1145 * of SRAM on it, somewhere between 4K and 48K. We need to 1146 * divide this up between the transmitter and receiver. We 1147 * give the receiver 2/3 of the memory (rounded down), and the 1148 * transmitter whatever remains. 1149 */ 1150 if (sc->sk_ramsize) { 1151 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1152 sc_if->sk_rx_ramstart = 0; 1153 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1154 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1155 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1156 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1157 1158 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1159 " tx_ramstart=%#x tx_ramend=%#x\n", 1160 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1161 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1162 } 1163 1164 /* Allocate the descriptor queues. */ 1165 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1166 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1167 BUS_DMA_NOWAIT)) { 1168 aprint_error(": can't alloc rx buffers\n"); 1169 goto fail; 1170 } 1171 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1172 sc_if->sk_ring_nseg, 1173 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1174 aprint_error(": can't map dma buffers (%zu bytes)\n", 1175 sizeof(struct msk_ring_data)); 1176 goto fail_1; 1177 } 1178 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1179 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1180 &sc_if->sk_ring_map)) { 1181 aprint_error(": can't create dma map\n"); 1182 goto fail_2; 1183 } 1184 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1185 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1186 aprint_error(": can't load dma map\n"); 1187 goto fail_3; 1188 } 1189 1190 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1191 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1192 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1193 1194 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1195 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1196 aprint_error_dev(sc_if->sk_dev, 1197 "Can't create TX dmamap\n"); 1198 goto fail_3; 1199 } 1200 1201 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK); 1202 entry->dmamap = dmamap; 1203 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1204 } 1205 1206 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1207 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1208 1209 if (sc->sk_type != SK_YUKON_FE && 1210 sc->sk_type != SK_YUKON_FE_P) 1211 sc_if->sk_pktlen = SK_JLEN; 1212 else 1213 sc_if->sk_pktlen = MCLBYTES; 1214 1215 /* Try to allocate memory for jumbo buffers. */ 1216 if (msk_alloc_jumbo_mem(sc_if)) { 1217 aprint_error(": jumbo buffer allocation failed\n"); 1218 goto fail_3; 1219 } 1220 1221 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1222 if (sc->sk_type != SK_YUKON_FE && 1223 sc->sk_type != SK_YUKON_FE_P) 1224 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1225 1226 ifp = &sc_if->sk_ethercom.ec_if; 1227 ifp->if_softc = sc_if; 1228 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1229 ifp->if_ioctl = msk_ioctl; 1230 ifp->if_start = msk_start; 1231 ifp->if_stop = msk_stop; 1232 ifp->if_init = msk_init; 1233 ifp->if_watchdog = msk_watchdog; 1234 ifp->if_baudrate = 1000000000; 1235 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1236 IFQ_SET_READY(&ifp->if_snd); 1237 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1238 1239 msk_reset(sc_if); 1240 1241 /* 1242 * Do miibus setup. 1243 */ 1244 DPRINTFN(2, ("msk_attach: 1\n")); 1245 1246 mii->mii_ifp = ifp; 1247 mii->mii_readreg = msk_miibus_readreg; 1248 mii->mii_writereg = msk_miibus_writereg; 1249 mii->mii_statchg = msk_miibus_statchg; 1250 1251 sc_if->sk_ethercom.ec_mii = mii; 1252 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1253 mii_flags = MIIF_DOPAUSE; 1254 if (sc->sk_fibertype) 1255 mii_flags |= MIIF_HAVEFIBER; 1256 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1257 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1258 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1259 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1260 0, NULL); 1261 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1262 } else 1263 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1264 1265 callout_init(&sc_if->sk_tick_ch, 0); 1266 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1267 callout_schedule(&sc_if->sk_tick_ch, hz); 1268 1269 callout_init(&sc_if->sk_tick_rx, 0); 1270 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1271 1272 /* 1273 * Call MI attach routines. 1274 */ 1275 if_attach(ifp); 1276 if_deferred_start_init(ifp, NULL); 1277 ether_ifattach(ifp, sc_if->sk_enaddr); 1278 1279 if (pmf_device_register(self, NULL, msk_resume)) 1280 pmf_class_network_register(self, ifp); 1281 else 1282 aprint_error_dev(self, "couldn't establish power handler\n"); 1283 1284 if (sc->rnd_attached++ == 0) { 1285 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1286 RND_TYPE_NET, RND_FLAG_DEFAULT); 1287 } 1288 1289 DPRINTFN(2, ("msk_attach: end\n")); 1290 return; 1291 1292 fail_3: 1293 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1294 fail_2: 1295 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1296 fail_1: 1297 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1298 fail: 1299 sc->sk_if[sa->skc_port] = NULL; 1300 } 1301 1302 static int 1303 msk_detach(device_t self, int flags) 1304 { 1305 struct sk_if_softc *sc_if = device_private(self); 1306 struct sk_softc *sc = sc_if->sk_softc; 1307 struct sk_txmap_entry *entry; 1308 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1309 1310 if (sc->sk_if[sc_if->sk_port] == NULL) 1311 return 0; 1312 1313 msk_stop(ifp, 1); 1314 1315 while ((entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 1316 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1317 bus_dmamap_destroy(sc->sc_dmatag, entry->dmamap); 1318 free(entry, M_DEVBUF); 1319 } 1320 1321 if (--sc->rnd_attached == 0) 1322 rnd_detach_source(&sc->rnd_source); 1323 1324 callout_halt(&sc_if->sk_tick_ch, NULL); 1325 callout_destroy(&sc_if->sk_tick_ch); 1326 1327 callout_halt(&sc_if->sk_tick_rx, NULL); 1328 callout_destroy(&sc_if->sk_tick_rx); 1329 1330 /* Detach any PHYs we might have. */ 1331 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1332 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1333 1334 pmf_device_deregister(self); 1335 1336 ether_ifdetach(ifp); 1337 if_detach(ifp); 1338 1339 /* Delete any remaining media. */ 1340 ifmedia_fini(&sc_if->sk_mii.mii_media); 1341 1342 msk_free_jumbo_mem(sc_if); 1343 1344 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1345 sizeof(struct msk_ring_data)); 1346 bus_dmamem_free(sc->sc_dmatag, 1347 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1348 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1349 sc->sk_if[sc_if->sk_port] = NULL; 1350 1351 return 0; 1352 } 1353 1354 static int 1355 mskcprint(void *aux, const char *pnp) 1356 { 1357 struct skc_attach_args *sa = aux; 1358 1359 if (pnp) 1360 aprint_normal("msk port %c at %s", 1361 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1362 else 1363 aprint_normal(" port %c", 1364 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1365 return UNCONF; 1366 } 1367 1368 /* 1369 * Attach the interface. Allocate softc structures, do ifmedia 1370 * setup and ethernet/BPF attach. 1371 */ 1372 static void 1373 mskc_attach(device_t parent, device_t self, void *aux) 1374 { 1375 struct sk_softc *sc = device_private(self); 1376 struct pci_attach_args *pa = aux; 1377 struct skc_attach_args skca; 1378 pci_chipset_tag_t pc = pa->pa_pc; 1379 pcireg_t command, memtype; 1380 const char *intrstr = NULL; 1381 int rc, sk_nodenum; 1382 uint8_t hw, pmd; 1383 const char *revstr = NULL; 1384 const struct sysctlnode *node; 1385 void *kva; 1386 char intrbuf[PCI_INTRSTR_LEN]; 1387 1388 DPRINTFN(2, ("begin mskc_attach\n")); 1389 1390 sc->sk_dev = self; 1391 /* 1392 * Handle power management nonsense. 1393 */ 1394 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1395 1396 if (command == 0x01) { 1397 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1398 if (command & SK_PSTATE_MASK) { 1399 uint32_t iobase, membase, irq; 1400 1401 /* Save important PCI config data. */ 1402 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1403 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1404 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1405 1406 /* Reset the power state. */ 1407 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1408 "mode -- setting to D0\n", 1409 command & SK_PSTATE_MASK); 1410 command &= 0xFFFFFFFC; 1411 pci_conf_write(pc, pa->pa_tag, 1412 SK_PCI_PWRMGMTCTRL, command); 1413 1414 /* Restore PCI config data. */ 1415 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1416 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1417 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1418 } 1419 } 1420 1421 /* 1422 * Map control/status registers. 1423 */ 1424 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1425 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1426 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1427 aprint_error(": can't map mem space\n"); 1428 return; 1429 } 1430 1431 if (pci_dma64_available(pa)) 1432 sc->sc_dmatag = pa->pa_dmat64; 1433 else 1434 sc->sc_dmatag = pa->pa_dmat; 1435 1436 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1437 command |= PCI_COMMAND_MASTER_ENABLE; 1438 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1439 1440 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1441 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1442 1443 /* bail out here if chip is not recognized */ 1444 if (!(SK_IS_YUKON2(sc))) { 1445 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1446 goto fail_1; 1447 } 1448 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1449 1450 /* Allocate interrupt */ 1451 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1452 aprint_error(": couldn't map interrupt\n"); 1453 goto fail_1; 1454 } 1455 1456 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1457 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1458 msk_intr, sc, device_xname(sc->sk_dev)); 1459 if (sc->sk_intrhand == NULL) { 1460 aprint_error(": couldn't establish interrupt"); 1461 if (intrstr != NULL) 1462 aprint_error(" at %s", intrstr); 1463 aprint_error("\n"); 1464 goto fail_1; 1465 } 1466 sc->sk_pc = pc; 1467 1468 if (bus_dmamem_alloc(sc->sc_dmatag, 1469 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1470 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1471 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1472 aprint_error(": can't alloc status buffers\n"); 1473 goto fail_2; 1474 } 1475 1476 if (bus_dmamem_map(sc->sc_dmatag, 1477 &sc->sk_status_seg, sc->sk_status_nseg, 1478 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1479 &kva, BUS_DMA_NOWAIT)) { 1480 aprint_error(": can't map dma buffers (%zu bytes)\n", 1481 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1482 goto fail_3; 1483 } 1484 if (bus_dmamap_create(sc->sc_dmatag, 1485 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1486 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1487 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1488 aprint_error(": can't create dma map\n"); 1489 goto fail_4; 1490 } 1491 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1492 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1493 NULL, BUS_DMA_NOWAIT)) { 1494 aprint_error(": can't load dma map\n"); 1495 goto fail_5; 1496 } 1497 sc->sk_status_ring = (struct msk_status_desc *)kva; 1498 1499 sc->sk_int_mod = SK_IM_DEFAULT; 1500 sc->sk_int_mod_pending = 0; 1501 1502 /* Reset the adapter. */ 1503 mskc_reset(sc); 1504 1505 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1506 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1507 1508 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1509 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1510 sc->sk_fibertype = 1; 1511 1512 switch (sc->sk_type) { 1513 case SK_YUKON_XL: 1514 sc->sk_name = "Yukon-2 XL"; 1515 break; 1516 case SK_YUKON_EC_U: 1517 sc->sk_name = "Yukon-2 EC Ultra"; 1518 break; 1519 case SK_YUKON_EX: 1520 sc->sk_name = "Yukon-2 Extreme"; 1521 break; 1522 case SK_YUKON_EC: 1523 sc->sk_name = "Yukon-2 EC"; 1524 break; 1525 case SK_YUKON_FE: 1526 sc->sk_name = "Yukon-2 FE"; 1527 break; 1528 case SK_YUKON_FE_P: 1529 sc->sk_name = "Yukon-2 FE+"; 1530 break; 1531 case SK_YUKON_SUPR: 1532 sc->sk_name = "Yukon-2 Supreme"; 1533 break; 1534 case SK_YUKON_ULTRA2: 1535 sc->sk_name = "Yukon-2 Ultra 2"; 1536 break; 1537 case SK_YUKON_OPTIMA: 1538 sc->sk_name = "Yukon-2 Optima"; 1539 break; 1540 case SK_YUKON_PRM: 1541 sc->sk_name = "Yukon-2 Optima Prime"; 1542 break; 1543 case SK_YUKON_OPTIMA2: 1544 sc->sk_name = "Yukon-2 Optima 2"; 1545 break; 1546 default: 1547 sc->sk_name = "Yukon (Unknown)"; 1548 } 1549 1550 if (sc->sk_type == SK_YUKON_XL) { 1551 switch (sc->sk_rev) { 1552 case SK_YUKON_XL_REV_A0: 1553 revstr = "A0"; 1554 break; 1555 case SK_YUKON_XL_REV_A1: 1556 revstr = "A1"; 1557 break; 1558 case SK_YUKON_XL_REV_A2: 1559 revstr = "A2"; 1560 break; 1561 case SK_YUKON_XL_REV_A3: 1562 revstr = "A3"; 1563 break; 1564 default: 1565 break; 1566 } 1567 } 1568 1569 if (sc->sk_type == SK_YUKON_EC) { 1570 switch (sc->sk_rev) { 1571 case SK_YUKON_EC_REV_A1: 1572 revstr = "A1"; 1573 break; 1574 case SK_YUKON_EC_REV_A2: 1575 revstr = "A2"; 1576 break; 1577 case SK_YUKON_EC_REV_A3: 1578 revstr = "A3"; 1579 break; 1580 default: 1581 break; 1582 } 1583 } 1584 1585 if (sc->sk_type == SK_YUKON_FE) { 1586 switch (sc->sk_rev) { 1587 case SK_YUKON_FE_REV_A1: 1588 revstr = "A1"; 1589 break; 1590 case SK_YUKON_FE_REV_A2: 1591 revstr = "A2"; 1592 break; 1593 default: 1594 break; 1595 } 1596 } 1597 1598 if (sc->sk_type == SK_YUKON_EC_U) { 1599 switch (sc->sk_rev) { 1600 case SK_YUKON_EC_U_REV_A0: 1601 revstr = "A0"; 1602 break; 1603 case SK_YUKON_EC_U_REV_A1: 1604 revstr = "A1"; 1605 break; 1606 case SK_YUKON_EC_U_REV_B0: 1607 revstr = "B0"; 1608 break; 1609 case SK_YUKON_EC_U_REV_B1: 1610 revstr = "B1"; 1611 break; 1612 default: 1613 break; 1614 } 1615 } 1616 1617 if (sc->sk_type == SK_YUKON_FE) { 1618 switch (sc->sk_rev) { 1619 case SK_YUKON_FE_REV_A1: 1620 revstr = "A1"; 1621 break; 1622 case SK_YUKON_FE_REV_A2: 1623 revstr = "A2"; 1624 break; 1625 default: 1626 ; 1627 } 1628 } 1629 1630 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1631 revstr = "A0"; 1632 1633 if (sc->sk_type == SK_YUKON_EX) { 1634 switch (sc->sk_rev) { 1635 case SK_YUKON_EX_REV_A0: 1636 revstr = "A0"; 1637 break; 1638 case SK_YUKON_EX_REV_B0: 1639 revstr = "B0"; 1640 break; 1641 default: 1642 ; 1643 } 1644 } 1645 1646 if (sc->sk_type == SK_YUKON_SUPR) { 1647 switch (sc->sk_rev) { 1648 case SK_YUKON_SUPR_REV_A0: 1649 revstr = "A0"; 1650 break; 1651 case SK_YUKON_SUPR_REV_B0: 1652 revstr = "B0"; 1653 break; 1654 case SK_YUKON_SUPR_REV_B1: 1655 revstr = "B1"; 1656 break; 1657 default: 1658 ; 1659 } 1660 } 1661 1662 if (sc->sk_type == SK_YUKON_PRM) { 1663 switch (sc->sk_rev) { 1664 case SK_YUKON_PRM_REV_Z1: 1665 revstr = "Z1"; 1666 break; 1667 case SK_YUKON_PRM_REV_A0: 1668 revstr = "A0"; 1669 break; 1670 default: 1671 ; 1672 } 1673 } 1674 1675 /* Announce the product name. */ 1676 aprint_normal(", %s", sc->sk_name); 1677 if (revstr != NULL) 1678 aprint_normal(" rev. %s", revstr); 1679 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1680 1681 aprint_normal_dev(sc->sk_dev, "interrupting at %s\n", intrstr); 1682 1683 sc->sk_macs = 1; 1684 1685 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1686 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1687 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1688 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1689 sc->sk_macs++; 1690 } 1691 1692 skca.skc_port = SK_PORT_A; 1693 skca.skc_type = sc->sk_type; 1694 skca.skc_rev = sc->sk_rev; 1695 (void)config_found(sc->sk_dev, &skca, mskcprint); 1696 1697 if (sc->sk_macs > 1) { 1698 skca.skc_port = SK_PORT_B; 1699 skca.skc_type = sc->sk_type; 1700 skca.skc_rev = sc->sk_rev; 1701 (void)config_found(sc->sk_dev, &skca, mskcprint); 1702 } 1703 1704 /* Turn on the 'driver is loaded' LED. */ 1705 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1706 1707 /* skc sysctl setup */ 1708 1709 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1710 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1711 SYSCTL_DESCR("mskc per-controller controls"), 1712 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1713 CTL_EOL)) != 0) { 1714 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1715 goto fail_6; 1716 } 1717 1718 sk_nodenum = node->sysctl_num; 1719 1720 /* interrupt moderation time in usecs */ 1721 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1722 CTLFLAG_READWRITE, 1723 CTLTYPE_INT, "int_mod", 1724 SYSCTL_DESCR("msk interrupt moderation timer"), 1725 msk_sysctl_handler, 0, (void *)sc, 1726 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1727 CTL_EOL)) != 0) { 1728 aprint_normal_dev(sc->sk_dev, 1729 "couldn't create int_mod sysctl node\n"); 1730 goto fail_6; 1731 } 1732 1733 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1734 aprint_error_dev(self, "couldn't establish power handler\n"); 1735 1736 return; 1737 1738 fail_6: 1739 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1740 fail_4: 1741 bus_dmamem_unmap(sc->sc_dmatag, kva, 1742 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1743 fail_3: 1744 bus_dmamem_free(sc->sc_dmatag, 1745 &sc->sk_status_seg, sc->sk_status_nseg); 1746 sc->sk_status_nseg = 0; 1747 fail_5: 1748 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1749 fail_2: 1750 pci_intr_disestablish(pc, sc->sk_intrhand); 1751 sc->sk_intrhand = NULL; 1752 fail_1: 1753 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1754 sc->sk_bsize = 0; 1755 } 1756 1757 static int 1758 mskc_detach(device_t self, int flags) 1759 { 1760 struct sk_softc *sc = device_private(self); 1761 int rv; 1762 1763 if (sc->sk_intrhand) { 1764 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1765 sc->sk_intrhand = NULL; 1766 } 1767 1768 if (sc->sk_pihp != NULL) { 1769 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1770 sc->sk_pihp = NULL; 1771 } 1772 1773 rv = config_detach_children(self, flags); 1774 if (rv != 0) 1775 return rv; 1776 1777 if (sc->sk_status_nseg > 0) { 1778 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1779 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1780 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1781 bus_dmamem_free(sc->sc_dmatag, 1782 &sc->sk_status_seg, sc->sk_status_nseg); 1783 } 1784 1785 if (sc->sk_bsize > 0) 1786 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1787 1788 return 0; 1789 } 1790 1791 static int 1792 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1793 { 1794 struct sk_softc *sc = sc_if->sk_softc; 1795 struct msk_tx_desc *f = NULL; 1796 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1797 uint32_t entries = 0; 1798 size_t i; 1799 struct sk_txmap_entry *entry; 1800 bus_dmamap_t txmap; 1801 bus_addr_t addr; 1802 1803 DPRINTFN(2, ("msk_encap\n")); 1804 1805 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1806 if (entry == NULL) { 1807 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1808 return ENOBUFS; 1809 } 1810 txmap = entry->dmamap; 1811 1812 cur = frag = *txidx; 1813 1814 #ifdef MSK_DEBUG 1815 if (mskdebug >= 2) 1816 msk_dump_mbuf(m_head); 1817 #endif 1818 1819 /* 1820 * Start packing the mbufs in this chain into 1821 * the fragment pointers. Stop when we run out 1822 * of fragments or hit the end of the mbuf chain. 1823 */ 1824 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1825 BUS_DMA_NOWAIT)) { 1826 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1827 return ENOBUFS; 1828 } 1829 1830 /* Count how many tx descriptors needed. */ 1831 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1832 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1833 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1834 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1835 total++; 1836 } 1837 total++; 1838 } 1839 1840 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1841 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1842 bus_dmamap_unload(sc->sc_dmatag, txmap); 1843 return ENOBUFS; 1844 } 1845 1846 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1847 txmap->dm_nsegs, total)); 1848 1849 /* Sync the DMA map. */ 1850 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1851 BUS_DMASYNC_PREWRITE); 1852 1853 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1854 for (i = 0; i < txmap->dm_nsegs; i++) { 1855 addr = txmap->dm_segs[i].ds_addr; 1856 DPRINTFN(2, ("msk_encap: addr %llx\n", 1857 (unsigned long long)addr)); 1858 hiaddr = MSK_ADDR_HI(addr); 1859 1860 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1861 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1862 f->sk_addr = htole32(hiaddr); 1863 f->sk_len = 0; 1864 f->sk_ctl = 0; 1865 if (i == 0) 1866 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1867 else 1868 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1869 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1870 SK_INC(frag, MSK_TX_RING_CNT); 1871 entries++; 1872 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1873 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1874 } 1875 1876 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1877 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1878 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1879 f->sk_ctl = 0; 1880 if (i == 0) { 1881 if (hiaddr != old_hiaddr) 1882 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1883 else 1884 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1885 } else 1886 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1887 cur = frag; 1888 SK_INC(frag, MSK_TX_RING_CNT); 1889 entries++; 1890 } 1891 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1892 1893 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1894 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1895 1896 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1897 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1898 1899 /* Sync descriptors before handing to chip */ 1900 MSK_CDTXSYNC(sc_if, *txidx, entries, 1901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1902 1903 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1904 1905 /* Sync first descriptor to hand it off */ 1906 MSK_CDTXSYNC(sc_if, *txidx, 1, 1907 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1908 1909 sc_if->sk_cdata.sk_tx_cnt += entries; 1910 1911 #ifdef MSK_DEBUG 1912 if (mskdebug >= 2) { 1913 struct msk_tx_desc *le; 1914 uint32_t idx; 1915 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1916 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1917 msk_dump_txdesc(le, idx); 1918 } 1919 } 1920 #endif 1921 1922 *txidx = frag; 1923 1924 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1925 1926 return 0; 1927 } 1928 1929 static void 1930 msk_start(struct ifnet *ifp) 1931 { 1932 struct sk_if_softc *sc_if = ifp->if_softc; 1933 struct mbuf *m_head = NULL; 1934 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1935 int pkts = 0; 1936 1937 DPRINTFN(2, ("msk_start\n")); 1938 1939 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1940 IFQ_POLL(&ifp->if_snd, m_head); 1941 if (m_head == NULL) 1942 break; 1943 1944 /* 1945 * Pack the data into the transmit ring. If we 1946 * don't have room, set the OACTIVE flag and wait 1947 * for the NIC to drain the ring. 1948 */ 1949 if (msk_encap(sc_if, m_head, &idx)) { 1950 ifp->if_flags |= IFF_OACTIVE; 1951 break; 1952 } 1953 1954 /* now we are committed to transmit the packet */ 1955 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1956 pkts++; 1957 1958 /* 1959 * If there's a BPF listener, bounce a copy of this frame 1960 * to him. 1961 */ 1962 bpf_mtap(ifp, m_head, BPF_D_OUT); 1963 } 1964 if (pkts == 0) 1965 return; 1966 1967 /* Transmit */ 1968 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1969 sc_if->sk_cdata.sk_tx_prod = idx; 1970 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1971 1972 /* Set a timeout in case the chip goes out to lunch. */ 1973 ifp->if_timer = 5; 1974 } 1975 } 1976 1977 static void 1978 msk_watchdog(struct ifnet *ifp) 1979 { 1980 struct sk_if_softc *sc_if = ifp->if_softc; 1981 1982 /* 1983 * Reclaim first as there is a possibility of losing Tx completion 1984 * interrupts. 1985 */ 1986 msk_txeof(sc_if); 1987 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1988 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1989 1990 if_statinc(ifp, if_oerrors); 1991 1992 /* XXX Resets both ports; we shouldn't do that. */ 1993 mskc_reset(sc_if->sk_softc); 1994 msk_reset(sc_if); 1995 msk_init(ifp); 1996 } 1997 } 1998 1999 static bool 2000 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2001 { 2002 struct sk_softc *sc = device_private(dv); 2003 2004 DPRINTFN(2, ("mskc_suspend\n")); 2005 2006 /* Turn off the 'driver is loaded' LED. */ 2007 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2008 2009 return true; 2010 } 2011 2012 static bool 2013 mskc_resume(device_t dv, const pmf_qual_t *qual) 2014 { 2015 struct sk_softc *sc = device_private(dv); 2016 2017 DPRINTFN(2, ("mskc_resume\n")); 2018 2019 mskc_reset(sc); 2020 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2021 2022 return true; 2023 } 2024 2025 static __inline int 2026 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2027 { 2028 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2029 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2030 YU_RXSTAT_JABBER)) != 0 || 2031 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2032 YU_RXSTAT_BYTES(stat) != len) 2033 return 0; 2034 2035 return 1; 2036 } 2037 2038 static void 2039 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2040 { 2041 struct sk_softc *sc = sc_if->sk_softc; 2042 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2043 struct mbuf *m; 2044 unsigned cur, prod, tail, total_len = len; 2045 bus_dmamap_t dmamap; 2046 2047 cur = sc_if->sk_cdata.sk_rx_cons; 2048 prod = sc_if->sk_cdata.sk_rx_prod; 2049 2050 /* Sync the descriptor */ 2051 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2052 2053 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2054 sc_if->sk_cdata.sk_rx_cnt)); 2055 2056 while (prod != cur) { 2057 tail = cur; 2058 SK_INC(cur, MSK_RX_RING_CNT); 2059 2060 sc_if->sk_cdata.sk_rx_cnt--; 2061 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2062 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2063 if (m != NULL) 2064 break; /* found it */ 2065 } 2066 sc_if->sk_cdata.sk_rx_cons = cur; 2067 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2068 sc_if->sk_cdata.sk_rx_cnt, m)); 2069 2070 if (m == NULL) 2071 return; 2072 2073 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2074 2075 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2076 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2077 2078 if (total_len < SK_MIN_FRAMELEN || 2079 total_len > ETHER_MAX_LEN_JUMBO || 2080 msk_rxvalid(sc, rxstat, total_len) == 0) { 2081 if_statinc(ifp, if_ierrors); 2082 m_freem(m); 2083 return; 2084 } 2085 2086 m_set_rcvif(m, ifp); 2087 m->m_pkthdr.len = m->m_len = total_len; 2088 2089 /* pass it on. */ 2090 if_percpuq_enqueue(ifp->if_percpuq, m); 2091 } 2092 2093 static void 2094 msk_txeof(struct sk_if_softc *sc_if) 2095 { 2096 struct sk_softc *sc = sc_if->sk_softc; 2097 struct msk_tx_desc *cur_tx; 2098 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2099 uint32_t idx, reg, sk_ctl; 2100 struct sk_txmap_entry *entry; 2101 2102 DPRINTFN(2, ("msk_txeof\n")); 2103 2104 if (sc_if->sk_port == SK_PORT_A) 2105 reg = SK_STAT_BMU_TXA1_RIDX; 2106 else 2107 reg = SK_STAT_BMU_TXA2_RIDX; 2108 2109 /* 2110 * Go through our tx ring and free mbufs for those 2111 * frames that have been sent. 2112 */ 2113 idx = sc_if->sk_cdata.sk_tx_cons; 2114 while (idx != sk_win_read_2(sc, reg)) { 2115 MSK_CDTXSYNC(sc_if, idx, 1, 2116 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2117 2118 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2119 sk_ctl = cur_tx->sk_ctl; 2120 #ifdef MSK_DEBUG 2121 if (mskdebug >= 2) 2122 msk_dump_txdesc(cur_tx, idx); 2123 #endif 2124 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2125 if_statinc(ifp, if_opackets); 2126 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2127 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2128 2129 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2130 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2131 2132 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2133 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2134 link); 2135 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2136 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2137 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2138 } 2139 sc_if->sk_cdata.sk_tx_cnt--; 2140 SK_INC(idx, MSK_TX_RING_CNT); 2141 } 2142 if (idx == sc_if->sk_cdata.sk_tx_cons) 2143 return; 2144 2145 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2146 2147 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2148 ifp->if_flags &= ~IFF_OACTIVE; 2149 2150 sc_if->sk_cdata.sk_tx_cons = idx; 2151 } 2152 2153 static void 2154 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2155 { 2156 /* Make sure to not completely wrap around */ 2157 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2158 if (msk_newbuf(sc_if, 2159 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2160 goto schedretry; 2161 } 2162 } 2163 2164 return; 2165 2166 schedretry: 2167 /* Try later */ 2168 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2169 } 2170 2171 static void 2172 msk_fill_rx_tick(void *xsc_if) 2173 { 2174 struct sk_if_softc *sc_if = xsc_if; 2175 int s, rx_prod; 2176 2177 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2178 2179 s = splnet(); 2180 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2181 msk_fill_rx_ring(sc_if); 2182 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2183 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2184 sc_if->sk_cdata.sk_rx_prod); 2185 } 2186 splx(s); 2187 } 2188 2189 static void 2190 msk_tick(void *xsc_if) 2191 { 2192 struct sk_if_softc *sc_if = xsc_if; 2193 struct mii_data *mii = &sc_if->sk_mii; 2194 int s; 2195 2196 s = splnet(); 2197 mii_tick(mii); 2198 splx(s); 2199 2200 callout_schedule(&sc_if->sk_tick_ch, hz); 2201 } 2202 2203 static void 2204 msk_intr_yukon(struct sk_if_softc *sc_if) 2205 { 2206 uint8_t status; 2207 2208 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2209 /* RX overrun */ 2210 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2211 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2212 SK_RFCTL_RX_FIFO_OVER); 2213 } 2214 /* TX underrun */ 2215 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2216 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2217 SK_TFCTL_TX_FIFO_UNDER); 2218 } 2219 2220 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2221 } 2222 2223 static int 2224 msk_intr(void *xsc) 2225 { 2226 struct sk_softc *sc = xsc; 2227 struct sk_if_softc *sc_if; 2228 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2229 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2230 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2231 int claimed = 0; 2232 uint32_t status; 2233 struct msk_status_desc *cur_st; 2234 2235 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2236 if (status == 0xffffffff) 2237 return 0; 2238 if (status == 0) { 2239 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2240 return 0; 2241 } 2242 2243 status = CSR_READ_4(sc, SK_ISR); 2244 2245 if (sc_if0 != NULL) 2246 ifp0 = &sc_if0->sk_ethercom.ec_if; 2247 if (sc_if1 != NULL) 2248 ifp1 = &sc_if1->sk_ethercom.ec_if; 2249 2250 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2251 (ifp0->if_flags & IFF_RUNNING)) { 2252 msk_intr_yukon(sc_if0); 2253 } 2254 2255 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2256 (ifp1->if_flags & IFF_RUNNING)) { 2257 msk_intr_yukon(sc_if1); 2258 } 2259 2260 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2261 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2262 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2263 2264 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2265 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2266 switch (cur_st->sk_opcode) { 2267 case SK_Y2_STOPC_RXSTAT: 2268 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2269 if (sc_if) { 2270 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2271 letoh32(cur_st->sk_status)); 2272 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2273 msk_fill_rx_tick(sc_if); 2274 } 2275 break; 2276 case SK_Y2_STOPC_TXSTAT: 2277 if (sc_if0) 2278 msk_txeof(sc_if0); 2279 if (sc_if1) 2280 msk_txeof(sc_if1); 2281 break; 2282 default: 2283 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2284 break; 2285 } 2286 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2287 2288 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2289 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2290 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2291 } 2292 2293 if (status & SK_Y2_IMR_BMU) { 2294 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2295 claimed = 1; 2296 } 2297 2298 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2299 2300 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2301 if_schedule_deferred_start(ifp0); 2302 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2303 if_schedule_deferred_start(ifp1); 2304 2305 KASSERT(sc->rnd_attached > 0); 2306 rnd_add_uint32(&sc->rnd_source, status); 2307 2308 if (sc->sk_int_mod_pending) 2309 msk_update_int_mod(sc, 1); 2310 2311 return claimed; 2312 } 2313 2314 static void 2315 msk_init_yukon(struct sk_if_softc *sc_if) 2316 { 2317 uint32_t v; 2318 uint16_t reg; 2319 struct sk_softc *sc; 2320 int i; 2321 2322 sc = sc_if->sk_softc; 2323 2324 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2325 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2326 2327 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2328 2329 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2330 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2331 2332 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2333 2334 /* unused read of the interrupt source register */ 2335 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2336 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2337 2338 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2339 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2340 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2341 2342 /* MIB Counter Clear Mode set */ 2343 reg |= YU_PAR_MIB_CLR; 2344 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2345 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2346 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2347 2348 /* MIB Counter Clear Mode clear */ 2349 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2350 reg &= ~YU_PAR_MIB_CLR; 2351 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2352 2353 /* receive control reg */ 2354 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2355 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2356 2357 /* transmit control register */ 2358 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2359 2360 /* transmit flow control register */ 2361 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2362 2363 /* transmit parameter register */ 2364 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2365 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2366 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2367 2368 /* serial mode register */ 2369 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2370 reg = YU_SMR_DATA_BLIND(0x1c) | 2371 YU_SMR_MFL_VLAN | 2372 YU_SMR_IPG_DATA(0x1e); 2373 2374 if (sc->sk_type != SK_YUKON_FE && 2375 sc->sk_type != SK_YUKON_FE_P) 2376 reg |= YU_SMR_MFL_JUMBO; 2377 2378 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2379 2380 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2381 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2382 /* msk_attach calls me before ether_ifattach so check null */ 2383 if (ifp != NULL && ifp->if_sadl != NULL) 2384 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2385 sizeof(sc_if->sk_enaddr)); 2386 /* Setup Yukon's address */ 2387 for (i = 0; i < 3; i++) { 2388 /* Write Source Address 1 (unicast filter) */ 2389 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2390 sc_if->sk_enaddr[i * 2] | 2391 sc_if->sk_enaddr[i * 2 + 1] << 8); 2392 } 2393 2394 for (i = 0; i < 3; i++) { 2395 reg = sk_win_read_2(sc_if->sk_softc, 2396 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2397 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2398 } 2399 2400 /* Set promiscuous mode */ 2401 msk_setpromisc(sc_if); 2402 2403 /* Set multicast filter */ 2404 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2405 msk_setmulti(sc_if); 2406 2407 /* enable interrupt mask for counter overflows */ 2408 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2409 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2410 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2411 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2412 2413 /* Configure RX MAC FIFO Flush Mask */ 2414 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2415 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2416 YU_RXSTAT_JABBER; 2417 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2418 2419 /* Configure RX MAC FIFO */ 2420 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2421 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2422 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2423 v |= SK_RFCTL_RX_OVER_ON; 2424 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2425 2426 if ((sc->sk_type == SK_YUKON_FE_P) && 2427 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2428 v = 0x178; /* Magic value */ 2429 else { 2430 /* Increase flush threshold to 64 bytes */ 2431 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2432 } 2433 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2434 2435 /* Configure TX MAC FIFO */ 2436 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2437 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2438 2439 if ((sc->sk_type == SK_YUKON_FE_P) && 2440 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2441 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2442 v &= ~SK_TXEND_WM_ON; 2443 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2444 } 2445 2446 #if 1 2447 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2448 #endif 2449 DPRINTFN(6, ("msk_init_yukon: end\n")); 2450 } 2451 2452 /* 2453 * Note that to properly initialize any part of the GEnesis chip, 2454 * you first have to take it out of reset mode. 2455 */ 2456 static int 2457 msk_init(struct ifnet *ifp) 2458 { 2459 struct sk_if_softc *sc_if = ifp->if_softc; 2460 struct sk_softc *sc = sc_if->sk_softc; 2461 int rc = 0, s; 2462 uint32_t imr, imtimer_ticks; 2463 2464 2465 DPRINTFN(2, ("msk_init\n")); 2466 2467 s = splnet(); 2468 2469 /* Cancel pending I/O and free all RX/TX buffers. */ 2470 msk_stop(ifp, 1); 2471 2472 /* Configure I2C registers */ 2473 2474 /* Configure XMAC(s) */ 2475 msk_init_yukon(sc_if); 2476 if ((rc = ether_mediachange(ifp)) != 0) 2477 goto out; 2478 2479 /* Configure transmit arbiter(s) */ 2480 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2481 #if 0 2482 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2483 #endif 2484 2485 if (sc->sk_ramsize) { 2486 /* Configure RAMbuffers */ 2487 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2488 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2489 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2490 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2491 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2492 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2493 2494 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2495 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2496 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2497 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2498 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2499 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2500 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2501 } 2502 2503 /* Configure BMUs */ 2504 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2505 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2506 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2507 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2508 2509 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2510 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2511 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2512 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2513 2514 /* Make sure the sync transmit queue is disabled. */ 2515 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2516 2517 /* Init descriptors */ 2518 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2519 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2520 "memory for rx buffers\n"); 2521 msk_stop(ifp, 1); 2522 splx(s); 2523 return ENOBUFS; 2524 } 2525 2526 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2527 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2528 "memory for tx buffers\n"); 2529 msk_stop(ifp, 1); 2530 splx(s); 2531 return ENOBUFS; 2532 } 2533 2534 /* Set interrupt moderation if changed via sysctl. */ 2535 switch (sc->sk_type) { 2536 case SK_YUKON_EC: 2537 case SK_YUKON_EC_U: 2538 case SK_YUKON_EX: 2539 case SK_YUKON_SUPR: 2540 case SK_YUKON_ULTRA2: 2541 case SK_YUKON_OPTIMA: 2542 case SK_YUKON_PRM: 2543 case SK_YUKON_OPTIMA2: 2544 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2545 break; 2546 case SK_YUKON_FE: 2547 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2548 break; 2549 case SK_YUKON_FE_P: 2550 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2551 break; 2552 case SK_YUKON_XL: 2553 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2554 break; 2555 default: 2556 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2557 } 2558 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2559 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2560 sk_win_write_4(sc, SK_IMTIMERINIT, 2561 SK_IM_USECS(sc->sk_int_mod)); 2562 aprint_verbose_dev(sc->sk_dev, 2563 "interrupt moderation is %d us\n", sc->sk_int_mod); 2564 } 2565 2566 /* Initialize prefetch engine. */ 2567 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2568 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2569 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2570 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2571 MSK_RX_RING_ADDR(sc_if, 0)); 2572 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2573 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2574 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2575 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2576 2577 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2578 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2579 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2580 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2581 MSK_TX_RING_ADDR(sc_if, 0)); 2582 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2583 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2584 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2585 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2586 2587 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2588 sc_if->sk_cdata.sk_rx_prod); 2589 2590 2591 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2592 /* Disable flushing of non-ASF packets. */ 2593 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2594 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2595 } 2596 2597 /* Configure interrupt handling */ 2598 if (sc_if->sk_port == SK_PORT_A) 2599 sc->sk_intrmask |= SK_Y2_INTRS1; 2600 else 2601 sc->sk_intrmask |= SK_Y2_INTRS2; 2602 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2603 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2604 2605 ifp->if_flags |= IFF_RUNNING; 2606 ifp->if_flags &= ~IFF_OACTIVE; 2607 2608 callout_schedule(&sc_if->sk_tick_ch, hz); 2609 2610 out: 2611 splx(s); 2612 return rc; 2613 } 2614 2615 /* 2616 * Note: the logic of second parameter is inverted compared to OpenBSD 2617 * code, since this code uses the function as if_stop hook too. 2618 */ 2619 static void 2620 msk_stop(struct ifnet *ifp, int disable) 2621 { 2622 struct sk_if_softc *sc_if = ifp->if_softc; 2623 struct sk_softc *sc = sc_if->sk_softc; 2624 struct sk_txmap_entry *dma; 2625 int i; 2626 2627 DPRINTFN(2, ("msk_stop\n")); 2628 2629 callout_stop(&sc_if->sk_tick_ch); 2630 callout_stop(&sc_if->sk_tick_rx); 2631 2632 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2633 2634 /* Stop transfer of Tx descriptors */ 2635 2636 /* Stop transfer of Rx descriptors */ 2637 2638 if (disable) { 2639 /* Turn off various components of this interface. */ 2640 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2641 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2642 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2643 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2644 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2645 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2646 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2647 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2648 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2649 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2650 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2651 2652 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2653 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2654 2655 /* Disable interrupts */ 2656 if (sc_if->sk_port == SK_PORT_A) 2657 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2658 else 2659 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2660 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2661 } 2662 2663 /* Free RX and TX mbufs still in the queues. */ 2664 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2665 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2666 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2667 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2668 } 2669 } 2670 2671 sc_if->sk_cdata.sk_rx_prod = 0; 2672 sc_if->sk_cdata.sk_rx_cons = 0; 2673 sc_if->sk_cdata.sk_rx_cnt = 0; 2674 2675 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2676 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2677 dma = sc_if->sk_cdata.sk_tx_map[i]; 2678 2679 bus_dmamap_sync(sc->sc_dmatag, dma->dmamap, 0, 2680 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2681 2682 bus_dmamap_unload(sc->sc_dmatag, dma->dmamap); 2683 2684 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2685 sc_if->sk_cdata.sk_tx_map[i], link); 2686 sc_if->sk_cdata.sk_tx_map[i] = 0; 2687 2688 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2689 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2690 } 2691 } 2692 } 2693 2694 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2695 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2696 2697 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2698 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2699 2700 #ifdef MSK_DEBUG 2701 static void 2702 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2703 { 2704 #define DESC_PRINT(X) \ 2705 if (X) \ 2706 printf("txdesc[%d]." #X "=%#x\n", \ 2707 idx, X); 2708 2709 DESC_PRINT(letoh32(le->sk_addr)); 2710 DESC_PRINT(letoh16(le->sk_len)); 2711 DESC_PRINT(le->sk_ctl); 2712 DESC_PRINT(le->sk_opcode); 2713 #undef DESC_PRINT 2714 } 2715 2716 static void 2717 msk_dump_bytes(const char *data, int len) 2718 { 2719 int c, i, j; 2720 2721 for (i = 0; i < len; i += 16) { 2722 printf("%08x ", i); 2723 c = len - i; 2724 if (c > 16) c = 16; 2725 2726 for (j = 0; j < c; j++) { 2727 printf("%02x ", data[i + j] & 0xff); 2728 if ((j & 0xf) == 7 && j > 0) 2729 printf(" "); 2730 } 2731 2732 for (; j < 16; j++) 2733 printf(" "); 2734 printf(" "); 2735 2736 for (j = 0; j < c; j++) { 2737 int ch = data[i + j] & 0xff; 2738 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2739 } 2740 2741 printf("\n"); 2742 2743 if (c < 16) 2744 break; 2745 } 2746 } 2747 2748 static void 2749 msk_dump_mbuf(struct mbuf *m) 2750 { 2751 int count = m->m_pkthdr.len; 2752 2753 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2754 2755 while (count > 0 && m) { 2756 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2757 m, m->m_data, m->m_len); 2758 if (mskdebug >= 4) 2759 msk_dump_bytes(mtod(m, char *), m->m_len); 2760 2761 count -= m->m_len; 2762 m = m->m_next; 2763 } 2764 } 2765 #endif 2766 2767 static int 2768 msk_sysctl_handler(SYSCTLFN_ARGS) 2769 { 2770 int error, t; 2771 struct sysctlnode node; 2772 struct sk_softc *sc; 2773 2774 node = *rnode; 2775 sc = node.sysctl_data; 2776 t = sc->sk_int_mod; 2777 node.sysctl_data = &t; 2778 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2779 if (error || newp == NULL) 2780 return error; 2781 2782 if (t < SK_IM_MIN || t > SK_IM_MAX) 2783 return EINVAL; 2784 2785 /* update the softc with sysctl-changed value, and mark 2786 for hardware update */ 2787 sc->sk_int_mod = t; 2788 sc->sk_int_mod_pending = 1; 2789 return 0; 2790 } 2791 2792 /* 2793 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2794 * set up in mskc_attach() 2795 */ 2796 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2797 { 2798 int rc; 2799 const struct sysctlnode *node; 2800 2801 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2802 0, CTLTYPE_NODE, "msk", 2803 SYSCTL_DESCR("msk interface controls"), 2804 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2805 goto err; 2806 } 2807 2808 msk_root_num = node->sysctl_num; 2809 return; 2810 2811 err: 2812 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2813 } 2814
Indexes created Sun Sep 21 20:09:37 GMT 2025