if_msk.c revision 1.104
1 /* $NetBSD: if_msk.c,v 1.104 2020/04/29 18:52:03 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.104 2020/04/29 18:52:03 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 le16toh 72 #define letoh32 le32toh 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/pci/if_skreg.h> 92 #include <dev/pci/if_mskvar.h> 93 94 static int mskc_probe(device_t, cfdata_t, void *); 95 static void mskc_attach(device_t, device_t, void *); 96 static int mskc_detach(device_t, int); 97 static void mskc_reset(struct sk_softc *); 98 static bool mskc_suspend(device_t, const pmf_qual_t *); 99 static bool mskc_resume(device_t, const pmf_qual_t *); 100 static int msk_probe(device_t, cfdata_t, void *); 101 static void msk_attach(device_t, device_t, void *); 102 static int msk_detach(device_t, int); 103 static void msk_reset(struct sk_if_softc *); 104 static int mskcprint(void *, const char *); 105 static int msk_intr(void *); 106 static void msk_intr_yukon(struct sk_if_softc *); 107 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 108 static void msk_txeof(struct sk_if_softc *); 109 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 110 static void msk_start(struct ifnet *); 111 static int msk_ioctl(struct ifnet *, u_long, void *); 112 static int msk_init(struct ifnet *); 113 static void msk_init_yukon(struct sk_if_softc *); 114 static void msk_stop(struct ifnet *, int); 115 static void msk_watchdog(struct ifnet *); 116 static int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 117 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 118 static void *msk_jalloc(struct sk_if_softc *); 119 static void msk_jfree(struct mbuf *, void *, size_t, void *); 120 static int msk_init_rx_ring(struct sk_if_softc *); 121 static int msk_init_tx_ring(struct sk_if_softc *); 122 static void msk_fill_rx_ring(struct sk_if_softc *); 123 124 static void msk_update_int_mod(struct sk_softc *, int); 125 126 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 127 static int msk_miibus_writereg(device_t, int, int, uint16_t); 128 static void msk_miibus_statchg(struct ifnet *); 129 130 static void msk_setmulti(struct sk_if_softc *); 131 static void msk_setpromisc(struct sk_if_softc *); 132 static void msk_tick(void *); 133 static void msk_fill_rx_tick(void *); 134 135 /* #define MSK_DEBUG 1 */ 136 #ifdef MSK_DEBUG 137 #define DPRINTF(x) if (mskdebug) printf x 138 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 139 int mskdebug = MSK_DEBUG; 140 141 static void msk_dump_txdesc(struct msk_tx_desc *, int); 142 static void msk_dump_mbuf(struct mbuf *); 143 static void msk_dump_bytes(const char *, int); 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 static int msk_sysctl_handler(SYSCTLFN_PROTO); 150 static int msk_root_num; 151 152 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 153 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 199 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 201 { 0, 0 } 202 }; 203 204 static inline uint32_t 205 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 206 { 207 return CSR_READ_4(sc, reg); 208 } 209 210 static inline uint16_t 211 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 212 { 213 return CSR_READ_2(sc, reg); 214 } 215 216 static inline uint8_t 217 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 218 { 219 return CSR_READ_1(sc, reg); 220 } 221 222 static inline void 223 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 224 { 225 CSR_WRITE_4(sc, reg, x); 226 } 227 228 static inline void 229 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 230 { 231 CSR_WRITE_2(sc, reg, x); 232 } 233 234 static inline void 235 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 236 { 237 CSR_WRITE_1(sc, reg, x); 238 } 239 240 static int 241 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 242 { 243 struct sk_if_softc *sc_if = device_private(dev); 244 uint16_t data; 245 int i; 246 247 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 248 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 249 250 for (i = 0; i < SK_TIMEOUT; i++) { 251 DELAY(1); 252 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 253 if (data & YU_SMICR_READ_VALID) 254 break; 255 } 256 257 if (i == SK_TIMEOUT) { 258 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 259 return ETIMEDOUT; 260 } 261 262 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 263 264 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 265 266 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 267 phy, reg, *val)); 268 269 return 0; 270 } 271 272 static int 273 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 274 { 275 struct sk_if_softc *sc_if = device_private(dev); 276 int i; 277 278 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 279 phy, reg, val)); 280 281 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 282 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 283 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 284 285 for (i = 0; i < SK_TIMEOUT; i++) { 286 DELAY(1); 287 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 288 break; 289 } 290 291 if (i == SK_TIMEOUT) { 292 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 293 return ETIMEDOUT; 294 } 295 296 return 0; 297 } 298 299 static void 300 msk_miibus_statchg(struct ifnet *ifp) 301 { 302 struct sk_if_softc *sc_if = ifp->if_softc; 303 struct mii_data *mii = &sc_if->sk_mii; 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 int gpcr; 306 307 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 308 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 309 310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 311 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 312 /* Set speed. */ 313 gpcr |= YU_GPCR_SPEED_DIS; 314 switch (IFM_SUBTYPE(mii->mii_media_active)) { 315 case IFM_1000_SX: 316 case IFM_1000_LX: 317 case IFM_1000_CX: 318 case IFM_1000_T: 319 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 320 break; 321 case IFM_100_TX: 322 gpcr |= YU_GPCR_SPEED; 323 break; 324 } 325 326 /* Set duplex. */ 327 gpcr |= YU_GPCR_DPLX_DIS; 328 if ((mii->mii_media_active & IFM_FDX) != 0) 329 gpcr |= YU_GPCR_DUPLEX; 330 331 /* Disable flow control. */ 332 gpcr |= YU_GPCR_FCTL_DIS; 333 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 334 } 335 336 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 337 338 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 339 SK_YU_READ_2(sc_if, YUKON_GPCR))); 340 } 341 342 static void 343 msk_setmulti(struct sk_if_softc *sc_if) 344 { 345 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 346 uint32_t hashes[2] = { 0, 0 }; 347 int h; 348 struct ethercom *ec = &sc_if->sk_ethercom; 349 struct ether_multi *enm; 350 struct ether_multistep step; 351 uint16_t reg; 352 353 /* First, zot all the existing filters. */ 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 358 359 360 /* Now program new ones. */ 361 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 362 reg |= YU_RCR_UFLEN; 363 allmulti: 364 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 365 if ((ifp->if_flags & IFF_PROMISC) != 0) 366 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 367 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 368 hashes[0] = 0xFFFFFFFF; 369 hashes[1] = 0xFFFFFFFF; 370 } 371 } else { 372 /* First find the tail of the list. */ 373 ETHER_LOCK(ec); 374 ETHER_FIRST_MULTI(step, ec, enm); 375 while (enm != NULL) { 376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 377 ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 ETHER_UNLOCK(ec); 380 goto allmulti; 381 } 382 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 383 ((1 << SK_HASH_BITS) - 1); 384 if (h < 32) 385 hashes[0] |= (1 << h); 386 else 387 hashes[1] |= (1 << (h - 32)); 388 389 ETHER_NEXT_MULTI(step, enm); 390 } 391 ETHER_UNLOCK(ec); 392 reg |= YU_RCR_MUFLEN; 393 } 394 395 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 400 } 401 402 static void 403 msk_setpromisc(struct sk_if_softc *sc_if) 404 { 405 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 406 407 if (ifp->if_flags & IFF_PROMISC) 408 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 409 YU_RCR_UFLEN | YU_RCR_MUFLEN); 410 else 411 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 412 YU_RCR_UFLEN | YU_RCR_MUFLEN); 413 } 414 415 static int 416 msk_init_rx_ring(struct sk_if_softc *sc_if) 417 { 418 struct msk_chain_data *cd = &sc_if->sk_cdata; 419 struct msk_ring_data *rd = sc_if->sk_rdata; 420 struct msk_rx_desc *r; 421 422 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 423 424 sc_if->sk_cdata.sk_rx_prod = 0; 425 sc_if->sk_cdata.sk_rx_cons = 0; 426 sc_if->sk_cdata.sk_rx_cnt = 0; 427 sc_if->sk_cdata.sk_rx_hiaddr = 0; 428 429 /* Mark the first ring element to initialize the high address. */ 430 sc_if->sk_cdata.sk_rx_hiaddr = 0; 431 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 432 r->sk_addr = htole32(cd->sk_rx_hiaddr); 433 r->sk_len = 0; 434 r->sk_ctl = 0; 435 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 436 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 438 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 439 sc_if->sk_cdata.sk_rx_cnt++; 440 441 msk_fill_rx_ring(sc_if); 442 return 0; 443 } 444 445 static int 446 msk_init_tx_ring(struct sk_if_softc *sc_if) 447 { 448 struct msk_chain_data *cd = &sc_if->sk_cdata; 449 struct msk_ring_data *rd = sc_if->sk_rdata; 450 struct msk_tx_desc *t; 451 452 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 453 454 sc_if->sk_cdata.sk_tx_prod = 0; 455 sc_if->sk_cdata.sk_tx_cons = 0; 456 sc_if->sk_cdata.sk_tx_cnt = 0; 457 sc_if->sk_cdata.sk_tx_hiaddr = 0; 458 459 /* Mark the first ring element to initialize the high address. */ 460 sc_if->sk_cdata.sk_tx_hiaddr = 0; 461 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 462 t->sk_addr = htole32(cd->sk_tx_hiaddr); 463 t->sk_len = 0; 464 t->sk_ctl = 0; 465 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 466 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 468 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 469 sc_if->sk_cdata.sk_tx_cnt++; 470 471 return 0; 472 } 473 474 static int 475 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 476 { 477 struct mbuf *m_new = NULL; 478 struct sk_chain *c; 479 struct msk_rx_desc *r; 480 void *buf = NULL; 481 bus_addr_t addr; 482 483 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 484 if (m_new == NULL) 485 return ENOBUFS; 486 487 /* Allocate the jumbo buffer */ 488 buf = msk_jalloc(sc_if); 489 if (buf == NULL) { 490 m_freem(m_new); 491 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 492 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 493 return ENOBUFS; 494 } 495 496 /* Attach the buffer to the mbuf */ 497 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 498 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 499 500 m_adj(m_new, ETHER_ALIGN); 501 502 addr = dmamap->dm_segs[0].ds_addr + 503 ((vaddr_t)m_new->m_data - 504 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 505 506 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 507 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 508 r = &sc_if->sk_rdata->sk_rx_ring[sc_if->sk_cdata.sk_rx_prod]; 509 c->sk_mbuf = NULL; 510 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 511 r->sk_len = 0; 512 r->sk_ctl = 0; 513 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 514 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 515 516 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 518 519 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 520 sc_if->sk_cdata.sk_rx_cnt++; 521 522 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 523 sc_if->sk_ethercom.ec_if.if_xname, 524 (unsigned)MSK_ADDR_HI(addr))); 525 } 526 527 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 528 r = &sc_if->sk_rdata->sk_rx_ring[sc_if->sk_cdata.sk_rx_prod]; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 531 r->sk_len = htole16(SK_JLEN); 532 r->sk_ctl = 0; 533 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 534 535 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 536 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 537 538 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 539 sc_if->sk_cdata.sk_rx_cnt++; 540 541 return 0; 542 } 543 544 /* 545 * Memory management for jumbo frames. 546 */ 547 548 static int 549 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 550 { 551 struct sk_softc *sc = sc_if->sk_softc; 552 char *ptr, *kva; 553 int i, state, error; 554 struct sk_jpool_entry *entry; 555 556 state = error = 0; 557 558 /* Grab a big chunk o' storage. */ 559 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 560 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 561 BUS_DMA_NOWAIT)) { 562 aprint_error(": can't alloc rx buffers"); 563 return ENOBUFS; 564 } 565 566 state = 1; 567 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 568 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 569 BUS_DMA_NOWAIT)) { 570 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 571 error = ENOBUFS; 572 goto out; 573 } 574 575 state = 2; 576 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 577 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 578 aprint_error(": can't create dma map"); 579 error = ENOBUFS; 580 goto out; 581 } 582 583 state = 3; 584 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 585 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 586 aprint_error(": can't load dma map"); 587 error = ENOBUFS; 588 goto out; 589 } 590 591 state = 4; 592 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 593 DPRINTFN(1,("msk_jumbo_buf = %p\n", 594 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 595 596 LIST_INIT(&sc_if->sk_jfree_listhead); 597 LIST_INIT(&sc_if->sk_jinuse_listhead); 598 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 599 600 /* 601 * Now divide it up into 9K pieces and save the addresses 602 * in an array. 603 */ 604 ptr = sc_if->sk_cdata.sk_jumbo_buf; 605 for (i = 0; i < MSK_JSLOTS; i++) { 606 sc_if->sk_cdata.sk_jslots[i] = ptr; 607 ptr += SK_JLEN; 608 entry = malloc(sizeof(struct sk_jpool_entry), 609 M_DEVBUF, M_WAITOK); 610 entry->slot = i; 611 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 612 entry, jpool_entries); 613 } 614 out: 615 if (error != 0) { 616 switch (state) { 617 case 4: 618 bus_dmamap_unload(sc->sc_dmatag, 619 sc_if->sk_cdata.sk_rx_jumbo_map); 620 /* FALLTHROUGH */ 621 case 3: 622 bus_dmamap_destroy(sc->sc_dmatag, 623 sc_if->sk_cdata.sk_rx_jumbo_map); 624 /* FALLTHROUGH */ 625 case 2: 626 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 627 /* FALLTHROUGH */ 628 case 1: 629 bus_dmamem_free(sc->sc_dmatag, 630 &sc_if->sk_cdata.sk_jumbo_seg, 631 sc_if->sk_cdata.sk_jumbo_nseg); 632 break; 633 default: 634 break; 635 } 636 } 637 638 return error; 639 } 640 641 static void 642 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 643 { 644 struct sk_softc *sc = sc_if->sk_softc; 645 646 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 647 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 648 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 649 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 650 sc_if->sk_cdata.sk_jumbo_nseg); 651 } 652 653 /* 654 * Allocate a jumbo buffer. 655 */ 656 static void * 657 msk_jalloc(struct sk_if_softc *sc_if) 658 { 659 struct sk_jpool_entry *entry; 660 661 mutex_enter(&sc_if->sk_jpool_mtx); 662 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 663 664 if (entry == NULL) { 665 mutex_exit(&sc_if->sk_jpool_mtx); 666 return NULL; 667 } 668 669 LIST_REMOVE(entry, jpool_entries); 670 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 671 mutex_exit(&sc_if->sk_jpool_mtx); 672 return sc_if->sk_cdata.sk_jslots[entry->slot]; 673 } 674 675 /* 676 * Release a jumbo buffer. 677 */ 678 static void 679 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 680 { 681 struct sk_jpool_entry *entry; 682 struct sk_if_softc *sc; 683 int i; 684 685 /* Extract the softc struct pointer. */ 686 sc = (struct sk_if_softc *)arg; 687 688 if (sc == NULL) 689 panic("msk_jfree: can't find softc pointer!"); 690 691 /* calculate the slot this buffer belongs to */ 692 i = ((vaddr_t)buf 693 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 694 695 if ((i < 0) || (i >= MSK_JSLOTS)) 696 panic("msk_jfree: asked to free buffer that we don't manage!"); 697 698 mutex_enter(&sc->sk_jpool_mtx); 699 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 700 if (entry == NULL) 701 panic("msk_jfree: buffer not in use!"); 702 entry->slot = i; 703 LIST_REMOVE(entry, jpool_entries); 704 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 705 mutex_exit(&sc->sk_jpool_mtx); 706 707 if (__predict_true(m != NULL)) 708 pool_cache_put(mb_cache, m); 709 710 /* Now that we know we have a free RX buffer, refill if running out */ 711 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 712 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 713 callout_schedule(&sc->sk_tick_rx, 0); 714 } 715 716 static int 717 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 718 { 719 struct sk_if_softc *sc = ifp->if_softc; 720 int s, error; 721 722 s = splnet(); 723 724 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 725 switch (cmd) { 726 case SIOCSIFFLAGS: 727 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 728 break; 729 730 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 731 case IFF_RUNNING: 732 msk_stop(ifp, 1); 733 break; 734 case IFF_UP: 735 msk_init(ifp); 736 break; 737 case IFF_UP | IFF_RUNNING: 738 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 739 msk_setpromisc(sc); 740 msk_setmulti(sc); 741 } else 742 msk_init(ifp); 743 break; 744 } 745 sc->sk_if_flags = ifp->if_flags; 746 break; 747 default: 748 error = ether_ioctl(ifp, cmd, data); 749 if (error == ENETRESET) { 750 error = 0; 751 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 752 ; 753 else if (ifp->if_flags & IFF_RUNNING) { 754 /* 755 * Multicast list has changed; set the hardware 756 * filter accordingly. 757 */ 758 msk_setmulti(sc); 759 } 760 } 761 break; 762 } 763 764 splx(s); 765 return error; 766 } 767 768 static void 769 msk_update_int_mod(struct sk_softc *sc, int verbose) 770 { 771 uint32_t imtimer_ticks; 772 773 /* 774 * Configure interrupt moderation. The moderation timer 775 * defers interrupts specified in the interrupt moderation 776 * timer mask based on the timeout specified in the interrupt 777 * moderation timer init register. Each bit in the timer 778 * register represents one tick, so to specify a timeout in 779 * microseconds, we have to multiply by the correct number of 780 * ticks-per-microsecond. 781 */ 782 switch (sc->sk_type) { 783 case SK_YUKON_EC: 784 case SK_YUKON_EC_U: 785 case SK_YUKON_EX: 786 case SK_YUKON_SUPR: 787 case SK_YUKON_ULTRA2: 788 case SK_YUKON_OPTIMA: 789 case SK_YUKON_PRM: 790 case SK_YUKON_OPTIMA2: 791 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 792 break; 793 case SK_YUKON_FE: 794 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 795 break; 796 case SK_YUKON_FE_P: 797 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 798 break; 799 case SK_YUKON_XL: 800 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 801 break; 802 default: 803 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 804 } 805 if (verbose) 806 aprint_verbose_dev(sc->sk_dev, 807 "interrupt moderation is %d us\n", sc->sk_int_mod); 808 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 809 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 810 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 811 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 812 sc->sk_int_mod_pending = 0; 813 } 814 815 static int 816 msk_lookup(const struct pci_attach_args *pa) 817 { 818 const struct msk_product *pmsk; 819 820 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 821 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 822 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 823 return 1; 824 } 825 return 0; 826 } 827 828 /* 829 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 830 * IDs against our list and return a device name if we find a match. 831 */ 832 static int 833 mskc_probe(device_t parent, cfdata_t match, void *aux) 834 { 835 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 836 837 return msk_lookup(pa); 838 } 839 840 /* 841 * Force the GEnesis into reset, then bring it out of reset. 842 */ 843 static void 844 mskc_reset(struct sk_softc *sc) 845 { 846 uint32_t imtimer_ticks, reg1; 847 uint16_t status; 848 int reg; 849 850 DPRINTFN(2, ("mskc_reset\n")); 851 852 /* Disable ASF */ 853 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 854 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 855 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 856 /* Clear AHB bridge & microcontroller reset. */ 857 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 858 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 859 /* Clear ASF microcontroller state. */ 860 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 861 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 862 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 863 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 864 } else 865 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 866 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 867 868 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 869 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 870 871 DELAY(1000); 872 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 873 DELAY(2); 874 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 875 sk_win_write_1(sc, SK_TESTCTL1, 2); 876 877 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 878 sc->sk_type >= SK_YUKON_FE_P) { 879 uint32_t our; 880 881 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 882 883 /* enable all clocks. */ 884 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 885 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 886 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 887 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 888 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 889 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 890 /* Set all bits to 0 except bits 15..12 */ 891 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 892 /* Set to default value */ 893 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 894 895 /* 896 * Disable status race, workaround for Yukon EC Ultra & 897 * Yukon EX. 898 */ 899 reg1 = sk_win_read_4(sc, SK_GPIO); 900 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 901 sk_win_write_4(sc, SK_GPIO, reg1); 902 sk_win_read_4(sc, SK_GPIO); 903 } 904 905 /* release PHY from PowerDown/Coma mode. */ 906 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 907 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 908 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 909 else 910 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 911 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 912 913 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 914 sk_win_write_1(sc, SK_Y2_CLKGATE, 915 SK_Y2_CLKGATE_LINK1_GATE_DIS | 916 SK_Y2_CLKGATE_LINK2_GATE_DIS | 917 SK_Y2_CLKGATE_LINK1_CORE_DIS | 918 SK_Y2_CLKGATE_LINK2_CORE_DIS | 919 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 920 else 921 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 922 923 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 924 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 925 DELAY(1000); 926 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 927 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 928 929 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 930 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 931 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 932 } 933 934 sk_win_write_1(sc, SK_TESTCTL1, 1); 935 936 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 937 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 938 CSR_READ_2(sc, SK_LINK_CTRL))); 939 940 /* Clear I2C IRQ noise */ 941 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 942 943 /* Disable hardware timer */ 944 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 945 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 946 947 /* Disable descriptor polling */ 948 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 949 950 /* Disable time stamps */ 951 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 952 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 953 954 /* Enable RAM interface */ 955 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 956 for (reg = SK_TO0;reg <= SK_TO11; reg++) 957 sk_win_write_1(sc, reg, 36); 958 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 959 for (reg = SK_TO0;reg <= SK_TO11; reg++) 960 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 961 962 /* 963 * Configure interrupt moderation. The moderation timer 964 * defers interrupts specified in the interrupt moderation 965 * timer mask based on the timeout specified in the interrupt 966 * moderation timer init register. Each bit in the timer 967 * register represents one tick, so to specify a timeout in 968 * microseconds, we have to multiply by the correct number of 969 * ticks-per-microsecond. 970 */ 971 switch (sc->sk_type) { 972 case SK_YUKON_EC: 973 case SK_YUKON_EC_U: 974 case SK_YUKON_EX: 975 case SK_YUKON_SUPR: 976 case SK_YUKON_ULTRA2: 977 case SK_YUKON_OPTIMA: 978 case SK_YUKON_PRM: 979 case SK_YUKON_OPTIMA2: 980 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 981 break; 982 case SK_YUKON_FE: 983 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 984 break; 985 case SK_YUKON_FE_P: 986 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 987 break; 988 case SK_YUKON_XL: 989 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 990 break; 991 default: 992 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 993 break; 994 } 995 996 /* Reset status ring. */ 997 memset(sc->sk_status_ring, 0, 998 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 999 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1000 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1001 sc->sk_status_idx = 0; 1002 1003 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1004 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1005 1006 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1007 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1008 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1009 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1010 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1011 if (sc->sk_type == SK_YUKON_EC && 1012 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1013 /* WA for dev. #4.3 */ 1014 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1015 SK_STAT_BMU_TXTHIDX_MSK); 1016 /* WA for dev. #4.18 */ 1017 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1018 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1019 } else { 1020 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1021 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1022 if (sc->sk_type == SK_YUKON_XL) 1023 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1024 else 1025 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1026 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1027 } 1028 1029 #if 0 1030 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1031 #endif 1032 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1033 1034 /* Enable status unit. */ 1035 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1036 1037 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1038 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1039 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1040 1041 msk_update_int_mod(sc, 0); 1042 } 1043 1044 static int 1045 msk_probe(device_t parent, cfdata_t match, void *aux) 1046 { 1047 struct skc_attach_args *sa = aux; 1048 1049 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1050 return 0; 1051 1052 switch (sa->skc_type) { 1053 case SK_YUKON_XL: 1054 case SK_YUKON_EC_U: 1055 case SK_YUKON_EX: 1056 case SK_YUKON_EC: 1057 case SK_YUKON_FE: 1058 case SK_YUKON_FE_P: 1059 case SK_YUKON_SUPR: 1060 case SK_YUKON_ULTRA2: 1061 case SK_YUKON_OPTIMA: 1062 case SK_YUKON_PRM: 1063 case SK_YUKON_OPTIMA2: 1064 return 1; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static void 1071 msk_reset(struct sk_if_softc *sc_if) 1072 { 1073 /* GMAC and GPHY Reset */ 1074 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1075 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1076 DELAY(1000); 1077 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1078 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1079 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1080 } 1081 1082 static bool 1083 msk_resume(device_t dv, const pmf_qual_t *qual) 1084 { 1085 struct sk_if_softc *sc_if = device_private(dv); 1086 1087 msk_init_yukon(sc_if); 1088 return true; 1089 } 1090 1091 /* 1092 * Each XMAC chip is attached as a separate logical IP interface. 1093 * Single port cards will have only one logical interface of course. 1094 */ 1095 static void 1096 msk_attach(device_t parent, device_t self, void *aux) 1097 { 1098 struct sk_if_softc *sc_if = device_private(self); 1099 struct sk_softc *sc = device_private(parent); 1100 struct skc_attach_args *sa = aux; 1101 bus_dmamap_t dmamap; 1102 struct sk_txmap_entry *entry; 1103 struct ifnet *ifp; 1104 struct mii_data * const mii = &sc_if->sk_mii; 1105 void *kva; 1106 int i; 1107 uint32_t chunk; 1108 int mii_flags; 1109 1110 sc_if->sk_dev = self; 1111 sc_if->sk_port = sa->skc_port; 1112 sc_if->sk_softc = sc; 1113 sc->sk_if[sa->skc_port] = sc_if; 1114 1115 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1116 1117 /* 1118 * Get station address for this interface. Note that 1119 * dual port cards actually come with three station 1120 * addresses: one for each port, plus an extra. The 1121 * extra one is used by the SysKonnect driver software 1122 * as a 'virtual' station address for when both ports 1123 * are operating in failover mode. Currently we don't 1124 * use this extra address. 1125 */ 1126 for (i = 0; i < ETHER_ADDR_LEN; i++) 1127 sc_if->sk_enaddr[i] = 1128 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1129 1130 aprint_normal(": Ethernet address %s\n", 1131 ether_sprintf(sc_if->sk_enaddr)); 1132 1133 /* 1134 * Set up RAM buffer addresses. The Yukon2 has a small amount 1135 * of SRAM on it, somewhere between 4K and 48K. We need to 1136 * divide this up between the transmitter and receiver. We 1137 * give the receiver 2/3 of the memory (rounded down), and the 1138 * transmitter whatever remains. 1139 */ 1140 if (sc->sk_ramsize) { 1141 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1142 sc_if->sk_rx_ramstart = 0; 1143 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1144 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1145 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1146 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1147 1148 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1149 " tx_ramstart=%#x tx_ramend=%#x\n", 1150 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1151 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1152 } 1153 1154 /* Allocate the descriptor queues. */ 1155 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1156 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1157 BUS_DMA_NOWAIT)) { 1158 aprint_error(": can't alloc rx buffers\n"); 1159 goto fail; 1160 } 1161 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1162 sc_if->sk_ring_nseg, 1163 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1164 aprint_error(": can't map dma buffers (%zu bytes)\n", 1165 sizeof(struct msk_ring_data)); 1166 goto fail_1; 1167 } 1168 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1169 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1170 &sc_if->sk_ring_map)) { 1171 aprint_error(": can't create dma map\n"); 1172 goto fail_2; 1173 } 1174 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1175 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1176 aprint_error(": can't load dma map\n"); 1177 goto fail_3; 1178 } 1179 1180 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1181 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1182 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1183 1184 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1185 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1186 aprint_error_dev(sc_if->sk_dev, 1187 "Can't create TX dmamap\n"); 1188 goto fail_3; 1189 } 1190 1191 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK); 1192 entry->dmamap = dmamap; 1193 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1194 } 1195 1196 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1197 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1198 1199 if (sc->sk_type != SK_YUKON_FE && 1200 sc->sk_type != SK_YUKON_FE_P) 1201 sc_if->sk_pktlen = SK_JLEN; 1202 else 1203 sc_if->sk_pktlen = MCLBYTES; 1204 1205 /* Try to allocate memory for jumbo buffers. */ 1206 if (msk_alloc_jumbo_mem(sc_if)) { 1207 aprint_error(": jumbo buffer allocation failed\n"); 1208 goto fail_3; 1209 } 1210 1211 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1212 if (sc->sk_type != SK_YUKON_FE && 1213 sc->sk_type != SK_YUKON_FE_P) 1214 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1215 1216 ifp = &sc_if->sk_ethercom.ec_if; 1217 ifp->if_softc = sc_if; 1218 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1219 ifp->if_ioctl = msk_ioctl; 1220 ifp->if_start = msk_start; 1221 ifp->if_stop = msk_stop; 1222 ifp->if_init = msk_init; 1223 ifp->if_watchdog = msk_watchdog; 1224 ifp->if_baudrate = 1000000000; 1225 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1226 IFQ_SET_READY(&ifp->if_snd); 1227 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1228 1229 msk_reset(sc_if); 1230 1231 /* 1232 * Do miibus setup. 1233 */ 1234 DPRINTFN(2, ("msk_attach: 1\n")); 1235 1236 mii->mii_ifp = ifp; 1237 mii->mii_readreg = msk_miibus_readreg; 1238 mii->mii_writereg = msk_miibus_writereg; 1239 mii->mii_statchg = msk_miibus_statchg; 1240 1241 sc_if->sk_ethercom.ec_mii = mii; 1242 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1243 mii_flags = MIIF_DOPAUSE; 1244 if (sc->sk_fibertype) 1245 mii_flags |= MIIF_HAVEFIBER; 1246 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1247 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1248 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1249 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1250 0, NULL); 1251 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1252 } else 1253 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1254 1255 callout_init(&sc_if->sk_tick_ch, 0); 1256 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1257 callout_schedule(&sc_if->sk_tick_ch, hz); 1258 1259 callout_init(&sc_if->sk_tick_rx, 0); 1260 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1261 1262 /* 1263 * Call MI attach routines. 1264 */ 1265 if_attach(ifp); 1266 if_deferred_start_init(ifp, NULL); 1267 ether_ifattach(ifp, sc_if->sk_enaddr); 1268 1269 if (pmf_device_register(self, NULL, msk_resume)) 1270 pmf_class_network_register(self, ifp); 1271 else 1272 aprint_error_dev(self, "couldn't establish power handler\n"); 1273 1274 if (sc->rnd_attached++ == 0) { 1275 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1276 RND_TYPE_NET, RND_FLAG_DEFAULT); 1277 } 1278 1279 DPRINTFN(2, ("msk_attach: end\n")); 1280 return; 1281 1282 fail_3: 1283 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1284 fail_2: 1285 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1286 fail_1: 1287 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1288 fail: 1289 sc->sk_if[sa->skc_port] = NULL; 1290 } 1291 1292 static int 1293 msk_detach(device_t self, int flags) 1294 { 1295 struct sk_if_softc *sc_if = device_private(self); 1296 struct sk_softc *sc = sc_if->sk_softc; 1297 struct sk_txmap_entry *entry; 1298 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1299 1300 if (sc->sk_if[sc_if->sk_port] == NULL) 1301 return 0; 1302 1303 msk_stop(ifp, 1); 1304 1305 while ((entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 1306 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1307 bus_dmamap_destroy(sc->sc_dmatag, entry->dmamap); 1308 free(entry, M_DEVBUF); 1309 } 1310 1311 if (--sc->rnd_attached == 0) 1312 rnd_detach_source(&sc->rnd_source); 1313 1314 callout_halt(&sc_if->sk_tick_ch, NULL); 1315 callout_destroy(&sc_if->sk_tick_ch); 1316 1317 callout_halt(&sc_if->sk_tick_rx, NULL); 1318 callout_destroy(&sc_if->sk_tick_rx); 1319 1320 /* Detach any PHYs we might have. */ 1321 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1322 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1323 1324 pmf_device_deregister(self); 1325 1326 ether_ifdetach(ifp); 1327 if_detach(ifp); 1328 1329 /* Delete any remaining media. */ 1330 ifmedia_fini(&sc_if->sk_mii.mii_media); 1331 1332 msk_free_jumbo_mem(sc_if); 1333 1334 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1335 sizeof(struct msk_ring_data)); 1336 bus_dmamem_free(sc->sc_dmatag, 1337 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1338 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1339 sc->sk_if[sc_if->sk_port] = NULL; 1340 1341 return 0; 1342 } 1343 1344 static int 1345 mskcprint(void *aux, const char *pnp) 1346 { 1347 struct skc_attach_args *sa = aux; 1348 1349 if (pnp) 1350 aprint_normal("msk port %c at %s", 1351 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1352 else 1353 aprint_normal(" port %c", 1354 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1355 return UNCONF; 1356 } 1357 1358 /* 1359 * Attach the interface. Allocate softc structures, do ifmedia 1360 * setup and ethernet/BPF attach. 1361 */ 1362 static void 1363 mskc_attach(device_t parent, device_t self, void *aux) 1364 { 1365 struct sk_softc *sc = device_private(self); 1366 struct pci_attach_args *pa = aux; 1367 struct skc_attach_args skca; 1368 pci_chipset_tag_t pc = pa->pa_pc; 1369 pcireg_t command, memtype; 1370 const char *intrstr = NULL; 1371 int rc, sk_nodenum; 1372 uint8_t hw, pmd; 1373 const char *revstr = NULL; 1374 const struct sysctlnode *node; 1375 void *kva; 1376 char intrbuf[PCI_INTRSTR_LEN]; 1377 1378 DPRINTFN(2, ("begin mskc_attach\n")); 1379 1380 sc->sk_dev = self; 1381 /* 1382 * Handle power management nonsense. 1383 */ 1384 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1385 1386 if (command == 0x01) { 1387 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1388 if (command & SK_PSTATE_MASK) { 1389 uint32_t iobase, membase, irq; 1390 1391 /* Save important PCI config data. */ 1392 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1393 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1394 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1395 1396 /* Reset the power state. */ 1397 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1398 "mode -- setting to D0\n", 1399 command & SK_PSTATE_MASK); 1400 command &= 0xFFFFFFFC; 1401 pci_conf_write(pc, pa->pa_tag, 1402 SK_PCI_PWRMGMTCTRL, command); 1403 1404 /* Restore PCI config data. */ 1405 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1406 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1407 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1408 } 1409 } 1410 1411 /* 1412 * Map control/status registers. 1413 */ 1414 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1415 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1416 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1417 aprint_error(": can't map mem space\n"); 1418 return; 1419 } 1420 1421 if (pci_dma64_available(pa)) 1422 sc->sc_dmatag = pa->pa_dmat64; 1423 else 1424 sc->sc_dmatag = pa->pa_dmat; 1425 1426 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1427 command |= PCI_COMMAND_MASTER_ENABLE; 1428 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1429 1430 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1431 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1432 1433 /* bail out here if chip is not recognized */ 1434 if (!(SK_IS_YUKON2(sc))) { 1435 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1436 goto fail_1; 1437 } 1438 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1439 1440 /* Allocate interrupt */ 1441 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1442 aprint_error(": couldn't map interrupt\n"); 1443 goto fail_1; 1444 } 1445 1446 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1447 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1448 msk_intr, sc, device_xname(sc->sk_dev)); 1449 if (sc->sk_intrhand == NULL) { 1450 aprint_error(": couldn't establish interrupt"); 1451 if (intrstr != NULL) 1452 aprint_error(" at %s", intrstr); 1453 aprint_error("\n"); 1454 goto fail_1; 1455 } 1456 sc->sk_pc = pc; 1457 1458 if (bus_dmamem_alloc(sc->sc_dmatag, 1459 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1460 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1461 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1462 aprint_error(": can't alloc status buffers\n"); 1463 goto fail_2; 1464 } 1465 1466 if (bus_dmamem_map(sc->sc_dmatag, 1467 &sc->sk_status_seg, sc->sk_status_nseg, 1468 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1469 &kva, BUS_DMA_NOWAIT)) { 1470 aprint_error(": can't map dma buffers (%zu bytes)\n", 1471 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1472 goto fail_3; 1473 } 1474 if (bus_dmamap_create(sc->sc_dmatag, 1475 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1476 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1477 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1478 aprint_error(": can't create dma map\n"); 1479 goto fail_4; 1480 } 1481 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1482 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1483 NULL, BUS_DMA_NOWAIT)) { 1484 aprint_error(": can't load dma map\n"); 1485 goto fail_5; 1486 } 1487 sc->sk_status_ring = (struct msk_status_desc *)kva; 1488 1489 sc->sk_int_mod = SK_IM_DEFAULT; 1490 sc->sk_int_mod_pending = 0; 1491 1492 /* Reset the adapter. */ 1493 mskc_reset(sc); 1494 1495 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1496 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1497 1498 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1499 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1500 sc->sk_fibertype = 1; 1501 1502 switch (sc->sk_type) { 1503 case SK_YUKON_XL: 1504 sc->sk_name = "Yukon-2 XL"; 1505 break; 1506 case SK_YUKON_EC_U: 1507 sc->sk_name = "Yukon-2 EC Ultra"; 1508 break; 1509 case SK_YUKON_EX: 1510 sc->sk_name = "Yukon-2 Extreme"; 1511 break; 1512 case SK_YUKON_EC: 1513 sc->sk_name = "Yukon-2 EC"; 1514 break; 1515 case SK_YUKON_FE: 1516 sc->sk_name = "Yukon-2 FE"; 1517 break; 1518 case SK_YUKON_FE_P: 1519 sc->sk_name = "Yukon-2 FE+"; 1520 break; 1521 case SK_YUKON_SUPR: 1522 sc->sk_name = "Yukon-2 Supreme"; 1523 break; 1524 case SK_YUKON_ULTRA2: 1525 sc->sk_name = "Yukon-2 Ultra 2"; 1526 break; 1527 case SK_YUKON_OPTIMA: 1528 sc->sk_name = "Yukon-2 Optima"; 1529 break; 1530 case SK_YUKON_PRM: 1531 sc->sk_name = "Yukon-2 Optima Prime"; 1532 break; 1533 case SK_YUKON_OPTIMA2: 1534 sc->sk_name = "Yukon-2 Optima 2"; 1535 break; 1536 default: 1537 sc->sk_name = "Yukon (Unknown)"; 1538 } 1539 1540 if (sc->sk_type == SK_YUKON_XL) { 1541 switch (sc->sk_rev) { 1542 case SK_YUKON_XL_REV_A0: 1543 revstr = "A0"; 1544 break; 1545 case SK_YUKON_XL_REV_A1: 1546 revstr = "A1"; 1547 break; 1548 case SK_YUKON_XL_REV_A2: 1549 revstr = "A2"; 1550 break; 1551 case SK_YUKON_XL_REV_A3: 1552 revstr = "A3"; 1553 break; 1554 default: 1555 break; 1556 } 1557 } 1558 1559 if (sc->sk_type == SK_YUKON_EC) { 1560 switch (sc->sk_rev) { 1561 case SK_YUKON_EC_REV_A1: 1562 revstr = "A1"; 1563 break; 1564 case SK_YUKON_EC_REV_A2: 1565 revstr = "A2"; 1566 break; 1567 case SK_YUKON_EC_REV_A3: 1568 revstr = "A3"; 1569 break; 1570 default: 1571 break; 1572 } 1573 } 1574 1575 if (sc->sk_type == SK_YUKON_FE) { 1576 switch (sc->sk_rev) { 1577 case SK_YUKON_FE_REV_A1: 1578 revstr = "A1"; 1579 break; 1580 case SK_YUKON_FE_REV_A2: 1581 revstr = "A2"; 1582 break; 1583 default: 1584 break; 1585 } 1586 } 1587 1588 if (sc->sk_type == SK_YUKON_EC_U) { 1589 switch (sc->sk_rev) { 1590 case SK_YUKON_EC_U_REV_A0: 1591 revstr = "A0"; 1592 break; 1593 case SK_YUKON_EC_U_REV_A1: 1594 revstr = "A1"; 1595 break; 1596 case SK_YUKON_EC_U_REV_B0: 1597 revstr = "B0"; 1598 break; 1599 case SK_YUKON_EC_U_REV_B1: 1600 revstr = "B1"; 1601 break; 1602 default: 1603 break; 1604 } 1605 } 1606 1607 if (sc->sk_type == SK_YUKON_FE) { 1608 switch (sc->sk_rev) { 1609 case SK_YUKON_FE_REV_A1: 1610 revstr = "A1"; 1611 break; 1612 case SK_YUKON_FE_REV_A2: 1613 revstr = "A2"; 1614 break; 1615 default: 1616 ; 1617 } 1618 } 1619 1620 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1621 revstr = "A0"; 1622 1623 if (sc->sk_type == SK_YUKON_EX) { 1624 switch (sc->sk_rev) { 1625 case SK_YUKON_EX_REV_A0: 1626 revstr = "A0"; 1627 break; 1628 case SK_YUKON_EX_REV_B0: 1629 revstr = "B0"; 1630 break; 1631 default: 1632 ; 1633 } 1634 } 1635 1636 if (sc->sk_type == SK_YUKON_SUPR) { 1637 switch (sc->sk_rev) { 1638 case SK_YUKON_SUPR_REV_A0: 1639 revstr = "A0"; 1640 break; 1641 case SK_YUKON_SUPR_REV_B0: 1642 revstr = "B0"; 1643 break; 1644 case SK_YUKON_SUPR_REV_B1: 1645 revstr = "B1"; 1646 break; 1647 default: 1648 ; 1649 } 1650 } 1651 1652 if (sc->sk_type == SK_YUKON_PRM) { 1653 switch (sc->sk_rev) { 1654 case SK_YUKON_PRM_REV_Z1: 1655 revstr = "Z1"; 1656 break; 1657 case SK_YUKON_PRM_REV_A0: 1658 revstr = "A0"; 1659 break; 1660 default: 1661 ; 1662 } 1663 } 1664 1665 /* Announce the product name. */ 1666 aprint_normal(", %s", sc->sk_name); 1667 if (revstr != NULL) 1668 aprint_normal(" rev. %s", revstr); 1669 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1670 1671 aprint_normal_dev(sc->sk_dev, "interrupting at %s\n", intrstr); 1672 1673 sc->sk_macs = 1; 1674 1675 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1676 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1677 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1678 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1679 sc->sk_macs++; 1680 } 1681 1682 skca.skc_port = SK_PORT_A; 1683 skca.skc_type = sc->sk_type; 1684 skca.skc_rev = sc->sk_rev; 1685 (void)config_found(sc->sk_dev, &skca, mskcprint); 1686 1687 if (sc->sk_macs > 1) { 1688 skca.skc_port = SK_PORT_B; 1689 skca.skc_type = sc->sk_type; 1690 skca.skc_rev = sc->sk_rev; 1691 (void)config_found(sc->sk_dev, &skca, mskcprint); 1692 } 1693 1694 /* Turn on the 'driver is loaded' LED. */ 1695 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1696 1697 /* skc sysctl setup */ 1698 1699 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1700 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1701 SYSCTL_DESCR("mskc per-controller controls"), 1702 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1703 CTL_EOL)) != 0) { 1704 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1705 goto fail_6; 1706 } 1707 1708 sk_nodenum = node->sysctl_num; 1709 1710 /* interrupt moderation time in usecs */ 1711 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1712 CTLFLAG_READWRITE, 1713 CTLTYPE_INT, "int_mod", 1714 SYSCTL_DESCR("msk interrupt moderation timer"), 1715 msk_sysctl_handler, 0, (void *)sc, 1716 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1717 CTL_EOL)) != 0) { 1718 aprint_normal_dev(sc->sk_dev, 1719 "couldn't create int_mod sysctl node\n"); 1720 goto fail_6; 1721 } 1722 1723 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1724 aprint_error_dev(self, "couldn't establish power handler\n"); 1725 1726 return; 1727 1728 fail_6: 1729 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1730 fail_4: 1731 bus_dmamem_unmap(sc->sc_dmatag, kva, 1732 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1733 fail_3: 1734 bus_dmamem_free(sc->sc_dmatag, 1735 &sc->sk_status_seg, sc->sk_status_nseg); 1736 sc->sk_status_nseg = 0; 1737 fail_5: 1738 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1739 fail_2: 1740 pci_intr_disestablish(pc, sc->sk_intrhand); 1741 sc->sk_intrhand = NULL; 1742 fail_1: 1743 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1744 sc->sk_bsize = 0; 1745 } 1746 1747 static int 1748 mskc_detach(device_t self, int flags) 1749 { 1750 struct sk_softc *sc = device_private(self); 1751 int rv; 1752 1753 if (sc->sk_intrhand) { 1754 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1755 sc->sk_intrhand = NULL; 1756 } 1757 1758 if (sc->sk_pihp != NULL) { 1759 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1760 sc->sk_pihp = NULL; 1761 } 1762 1763 rv = config_detach_children(self, flags); 1764 if (rv != 0) 1765 return rv; 1766 1767 if (sc->sk_status_nseg > 0) { 1768 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1769 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1770 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1771 bus_dmamem_free(sc->sc_dmatag, 1772 &sc->sk_status_seg, sc->sk_status_nseg); 1773 } 1774 1775 if (sc->sk_bsize > 0) 1776 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1777 1778 return 0; 1779 } 1780 1781 static int 1782 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1783 { 1784 struct sk_softc *sc = sc_if->sk_softc; 1785 struct msk_tx_desc *f = NULL; 1786 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1787 uint32_t entries = 0; 1788 size_t i; 1789 struct sk_txmap_entry *entry; 1790 bus_dmamap_t txmap; 1791 bus_addr_t addr; 1792 1793 DPRINTFN(2, ("msk_encap\n")); 1794 1795 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1796 if (entry == NULL) { 1797 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1798 return ENOBUFS; 1799 } 1800 txmap = entry->dmamap; 1801 1802 cur = frag = *txidx; 1803 1804 #ifdef MSK_DEBUG 1805 if (mskdebug >= 2) 1806 msk_dump_mbuf(m_head); 1807 #endif 1808 1809 /* 1810 * Start packing the mbufs in this chain into 1811 * the fragment pointers. Stop when we run out 1812 * of fragments or hit the end of the mbuf chain. 1813 */ 1814 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1815 BUS_DMA_NOWAIT)) { 1816 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1817 return ENOBUFS; 1818 } 1819 1820 /* Count how many tx descriptors needed. */ 1821 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1822 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1823 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1824 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1825 total++; 1826 } 1827 total++; 1828 } 1829 1830 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1831 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1832 bus_dmamap_unload(sc->sc_dmatag, txmap); 1833 return ENOBUFS; 1834 } 1835 1836 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1837 txmap->dm_nsegs, total)); 1838 1839 /* Sync the DMA map. */ 1840 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1841 BUS_DMASYNC_PREWRITE); 1842 1843 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1844 for (i = 0; i < txmap->dm_nsegs; i++) { 1845 addr = txmap->dm_segs[i].ds_addr; 1846 DPRINTFN(2, ("msk_encap: addr %llx\n", 1847 (unsigned long long)addr)); 1848 hiaddr = MSK_ADDR_HI(addr); 1849 1850 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1851 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1852 f->sk_addr = htole32(hiaddr); 1853 f->sk_len = 0; 1854 f->sk_ctl = 0; 1855 if (i == 0) 1856 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1857 else 1858 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1859 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1860 SK_INC(frag, MSK_TX_RING_CNT); 1861 entries++; 1862 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1863 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1864 } 1865 1866 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1867 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1868 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1869 f->sk_ctl = 0; 1870 if (i == 0) { 1871 if (hiaddr != old_hiaddr) 1872 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1873 else 1874 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1875 } else 1876 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1877 cur = frag; 1878 SK_INC(frag, MSK_TX_RING_CNT); 1879 entries++; 1880 } 1881 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1882 1883 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1884 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1885 1886 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1887 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1888 1889 /* Sync descriptors before handing to chip */ 1890 MSK_CDTXSYNC(sc_if, *txidx, entries, 1891 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1892 1893 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1894 1895 /* Sync first descriptor to hand it off */ 1896 MSK_CDTXSYNC(sc_if, *txidx, 1, 1897 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1898 1899 sc_if->sk_cdata.sk_tx_cnt += entries; 1900 1901 #ifdef MSK_DEBUG 1902 if (mskdebug >= 2) { 1903 struct msk_tx_desc *le; 1904 uint32_t idx; 1905 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1906 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1907 msk_dump_txdesc(le, idx); 1908 } 1909 } 1910 #endif 1911 1912 *txidx = frag; 1913 1914 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1915 1916 return 0; 1917 } 1918 1919 static void 1920 msk_start(struct ifnet *ifp) 1921 { 1922 struct sk_if_softc *sc_if = ifp->if_softc; 1923 struct mbuf *m_head = NULL; 1924 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1925 int pkts = 0; 1926 1927 DPRINTFN(2, ("msk_start\n")); 1928 1929 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1930 IFQ_POLL(&ifp->if_snd, m_head); 1931 if (m_head == NULL) 1932 break; 1933 1934 /* 1935 * Pack the data into the transmit ring. If we 1936 * don't have room, set the OACTIVE flag and wait 1937 * for the NIC to drain the ring. 1938 */ 1939 if (msk_encap(sc_if, m_head, &idx)) { 1940 ifp->if_flags |= IFF_OACTIVE; 1941 break; 1942 } 1943 1944 /* now we are committed to transmit the packet */ 1945 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1946 pkts++; 1947 1948 /* 1949 * If there's a BPF listener, bounce a copy of this frame 1950 * to him. 1951 */ 1952 bpf_mtap(ifp, m_head, BPF_D_OUT); 1953 } 1954 if (pkts == 0) 1955 return; 1956 1957 /* Transmit */ 1958 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1959 sc_if->sk_cdata.sk_tx_prod = idx; 1960 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1961 1962 /* Set a timeout in case the chip goes out to lunch. */ 1963 ifp->if_timer = 5; 1964 } 1965 } 1966 1967 static void 1968 msk_watchdog(struct ifnet *ifp) 1969 { 1970 struct sk_if_softc *sc_if = ifp->if_softc; 1971 1972 /* 1973 * Reclaim first as there is a possibility of losing Tx completion 1974 * interrupts. 1975 */ 1976 msk_txeof(sc_if); 1977 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1978 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1979 1980 if_statinc(ifp, if_oerrors); 1981 1982 /* XXX Resets both ports; we shouldn't do that. */ 1983 mskc_reset(sc_if->sk_softc); 1984 msk_reset(sc_if); 1985 msk_init(ifp); 1986 } 1987 } 1988 1989 static bool 1990 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1991 { 1992 struct sk_softc *sc = device_private(dv); 1993 1994 DPRINTFN(2, ("mskc_suspend\n")); 1995 1996 /* Turn off the 'driver is loaded' LED. */ 1997 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1998 1999 return true; 2000 } 2001 2002 static bool 2003 mskc_resume(device_t dv, const pmf_qual_t *qual) 2004 { 2005 struct sk_softc *sc = device_private(dv); 2006 2007 DPRINTFN(2, ("mskc_resume\n")); 2008 2009 mskc_reset(sc); 2010 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2011 2012 return true; 2013 } 2014 2015 static __inline int 2016 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2017 { 2018 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2019 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2020 YU_RXSTAT_JABBER)) != 0 || 2021 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2022 YU_RXSTAT_BYTES(stat) != len) 2023 return 0; 2024 2025 return 1; 2026 } 2027 2028 static void 2029 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2030 { 2031 struct sk_softc *sc = sc_if->sk_softc; 2032 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2033 struct mbuf *m; 2034 unsigned cur, prod, tail, total_len = len; 2035 bus_dmamap_t dmamap; 2036 2037 cur = sc_if->sk_cdata.sk_rx_cons; 2038 prod = sc_if->sk_cdata.sk_rx_prod; 2039 2040 /* Sync the descriptor */ 2041 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2042 2043 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2044 sc_if->sk_cdata.sk_rx_cnt)); 2045 2046 while (prod != cur) { 2047 tail = cur; 2048 SK_INC(cur, MSK_RX_RING_CNT); 2049 2050 sc_if->sk_cdata.sk_rx_cnt--; 2051 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2052 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2053 if (m != NULL) 2054 break; /* found it */ 2055 } 2056 sc_if->sk_cdata.sk_rx_cons = cur; 2057 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2058 sc_if->sk_cdata.sk_rx_cnt, m)); 2059 2060 if (m == NULL) 2061 return; 2062 2063 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2064 2065 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2066 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2067 2068 if (total_len < SK_MIN_FRAMELEN || 2069 total_len > ETHER_MAX_LEN_JUMBO || 2070 msk_rxvalid(sc, rxstat, total_len) == 0) { 2071 if_statinc(ifp, if_ierrors); 2072 m_freem(m); 2073 return; 2074 } 2075 2076 m_set_rcvif(m, ifp); 2077 m->m_pkthdr.len = m->m_len = total_len; 2078 2079 /* pass it on. */ 2080 if_percpuq_enqueue(ifp->if_percpuq, m); 2081 } 2082 2083 static void 2084 msk_txeof(struct sk_if_softc *sc_if) 2085 { 2086 struct sk_softc *sc = sc_if->sk_softc; 2087 struct msk_tx_desc *cur_tx; 2088 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2089 uint32_t idx, reg, sk_ctl; 2090 struct sk_txmap_entry *entry; 2091 2092 DPRINTFN(2, ("msk_txeof\n")); 2093 2094 if (sc_if->sk_port == SK_PORT_A) 2095 reg = SK_STAT_BMU_TXA1_RIDX; 2096 else 2097 reg = SK_STAT_BMU_TXA2_RIDX; 2098 2099 /* 2100 * Go through our tx ring and free mbufs for those 2101 * frames that have been sent. 2102 */ 2103 idx = sc_if->sk_cdata.sk_tx_cons; 2104 while (idx != sk_win_read_2(sc, reg)) { 2105 MSK_CDTXSYNC(sc_if, idx, 1, 2106 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2107 2108 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2109 sk_ctl = cur_tx->sk_ctl; 2110 #ifdef MSK_DEBUG 2111 if (mskdebug >= 2) 2112 msk_dump_txdesc(cur_tx, idx); 2113 #endif 2114 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2115 if_statinc(ifp, if_opackets); 2116 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2117 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2118 2119 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2120 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2121 2122 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2123 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2124 link); 2125 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2126 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2127 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2128 } 2129 sc_if->sk_cdata.sk_tx_cnt--; 2130 SK_INC(idx, MSK_TX_RING_CNT); 2131 } 2132 if (idx == sc_if->sk_cdata.sk_tx_cons) 2133 return; 2134 2135 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2136 2137 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2138 ifp->if_flags &= ~IFF_OACTIVE; 2139 2140 sc_if->sk_cdata.sk_tx_cons = idx; 2141 } 2142 2143 static void 2144 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2145 { 2146 /* Make sure to not completely wrap around */ 2147 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2148 if (msk_newbuf(sc_if, 2149 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2150 goto schedretry; 2151 } 2152 } 2153 2154 return; 2155 2156 schedretry: 2157 /* Try later */ 2158 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2159 } 2160 2161 static void 2162 msk_fill_rx_tick(void *xsc_if) 2163 { 2164 struct sk_if_softc *sc_if = xsc_if; 2165 int s, rx_prod; 2166 2167 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2168 2169 s = splnet(); 2170 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2171 msk_fill_rx_ring(sc_if); 2172 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2173 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2174 sc_if->sk_cdata.sk_rx_prod); 2175 } 2176 splx(s); 2177 } 2178 2179 static void 2180 msk_tick(void *xsc_if) 2181 { 2182 struct sk_if_softc *sc_if = xsc_if; 2183 struct mii_data *mii = &sc_if->sk_mii; 2184 int s; 2185 2186 s = splnet(); 2187 mii_tick(mii); 2188 splx(s); 2189 2190 callout_schedule(&sc_if->sk_tick_ch, hz); 2191 } 2192 2193 static void 2194 msk_intr_yukon(struct sk_if_softc *sc_if) 2195 { 2196 uint8_t status; 2197 2198 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2199 /* RX overrun */ 2200 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2201 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2202 SK_RFCTL_RX_FIFO_OVER); 2203 } 2204 /* TX underrun */ 2205 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2206 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2207 SK_TFCTL_TX_FIFO_UNDER); 2208 } 2209 2210 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2211 } 2212 2213 static int 2214 msk_intr(void *xsc) 2215 { 2216 struct sk_softc *sc = xsc; 2217 struct sk_if_softc *sc_if; 2218 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2219 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2220 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2221 int claimed = 0; 2222 uint32_t status; 2223 struct msk_status_desc *cur_st; 2224 2225 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2226 if (status == 0xffffffff) 2227 return 0; 2228 if (status == 0) { 2229 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2230 return 0; 2231 } 2232 2233 status = CSR_READ_4(sc, SK_ISR); 2234 2235 if (sc_if0 != NULL) 2236 ifp0 = &sc_if0->sk_ethercom.ec_if; 2237 if (sc_if1 != NULL) 2238 ifp1 = &sc_if1->sk_ethercom.ec_if; 2239 2240 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2241 (ifp0->if_flags & IFF_RUNNING)) { 2242 msk_intr_yukon(sc_if0); 2243 } 2244 2245 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2246 (ifp1->if_flags & IFF_RUNNING)) { 2247 msk_intr_yukon(sc_if1); 2248 } 2249 2250 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2251 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2252 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2253 2254 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2255 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2256 switch (cur_st->sk_opcode) { 2257 case SK_Y2_STOPC_RXSTAT: 2258 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2259 if (sc_if) { 2260 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2261 letoh32(cur_st->sk_status)); 2262 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2263 msk_fill_rx_tick(sc_if); 2264 } 2265 break; 2266 case SK_Y2_STOPC_TXSTAT: 2267 if (sc_if0) 2268 msk_txeof(sc_if0); 2269 if (sc_if1) 2270 msk_txeof(sc_if1); 2271 break; 2272 default: 2273 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2274 break; 2275 } 2276 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2277 2278 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2279 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2280 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2281 } 2282 2283 if (status & SK_Y2_IMR_BMU) { 2284 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2285 claimed = 1; 2286 } 2287 2288 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2289 2290 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2291 if_schedule_deferred_start(ifp0); 2292 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2293 if_schedule_deferred_start(ifp1); 2294 2295 KASSERT(sc->rnd_attached > 0); 2296 rnd_add_uint32(&sc->rnd_source, status); 2297 2298 if (sc->sk_int_mod_pending) 2299 msk_update_int_mod(sc, 1); 2300 2301 return claimed; 2302 } 2303 2304 static void 2305 msk_init_yukon(struct sk_if_softc *sc_if) 2306 { 2307 uint32_t v; 2308 uint16_t reg; 2309 struct sk_softc *sc; 2310 int i; 2311 2312 sc = sc_if->sk_softc; 2313 2314 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2315 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2316 2317 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2318 2319 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2320 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2321 2322 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2323 2324 /* unused read of the interrupt source register */ 2325 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2326 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2327 2328 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2329 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2330 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2331 2332 /* MIB Counter Clear Mode set */ 2333 reg |= YU_PAR_MIB_CLR; 2334 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2335 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2336 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2337 2338 /* MIB Counter Clear Mode clear */ 2339 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2340 reg &= ~YU_PAR_MIB_CLR; 2341 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2342 2343 /* receive control reg */ 2344 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2345 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2346 2347 /* transmit control register */ 2348 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2349 2350 /* transmit flow control register */ 2351 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2352 2353 /* transmit parameter register */ 2354 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2355 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2356 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2357 2358 /* serial mode register */ 2359 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2360 reg = YU_SMR_DATA_BLIND(0x1c) | 2361 YU_SMR_MFL_VLAN | 2362 YU_SMR_IPG_DATA(0x1e); 2363 2364 if (sc->sk_type != SK_YUKON_FE && 2365 sc->sk_type != SK_YUKON_FE_P) 2366 reg |= YU_SMR_MFL_JUMBO; 2367 2368 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2369 2370 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2371 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2372 /* msk_attach calls me before ether_ifattach so check null */ 2373 if (ifp != NULL && ifp->if_sadl != NULL) 2374 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2375 sizeof(sc_if->sk_enaddr)); 2376 /* Setup Yukon's address */ 2377 for (i = 0; i < 3; i++) { 2378 /* Write Source Address 1 (unicast filter) */ 2379 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2380 sc_if->sk_enaddr[i * 2] | 2381 sc_if->sk_enaddr[i * 2 + 1] << 8); 2382 } 2383 2384 for (i = 0; i < 3; i++) { 2385 reg = sk_win_read_2(sc_if->sk_softc, 2386 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2387 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2388 } 2389 2390 /* Set promiscuous mode */ 2391 msk_setpromisc(sc_if); 2392 2393 /* Set multicast filter */ 2394 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2395 msk_setmulti(sc_if); 2396 2397 /* enable interrupt mask for counter overflows */ 2398 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2399 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2400 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2401 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2402 2403 /* Configure RX MAC FIFO Flush Mask */ 2404 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2405 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2406 YU_RXSTAT_JABBER; 2407 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2408 2409 /* Configure RX MAC FIFO */ 2410 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2411 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2412 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2413 v |= SK_RFCTL_RX_OVER_ON; 2414 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2415 2416 if ((sc->sk_type == SK_YUKON_FE_P) && 2417 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2418 v = 0x178; /* Magic value */ 2419 else { 2420 /* Increase flush threshold to 64 bytes */ 2421 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2422 } 2423 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2424 2425 /* Configure TX MAC FIFO */ 2426 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2427 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2428 2429 if ((sc->sk_type == SK_YUKON_FE_P) && 2430 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2431 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2432 v &= ~SK_TXEND_WM_ON; 2433 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2434 } 2435 2436 #if 1 2437 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2438 #endif 2439 DPRINTFN(6, ("msk_init_yukon: end\n")); 2440 } 2441 2442 /* 2443 * Note that to properly initialize any part of the GEnesis chip, 2444 * you first have to take it out of reset mode. 2445 */ 2446 static int 2447 msk_init(struct ifnet *ifp) 2448 { 2449 struct sk_if_softc *sc_if = ifp->if_softc; 2450 struct sk_softc *sc = sc_if->sk_softc; 2451 int rc = 0, s; 2452 uint32_t imr, imtimer_ticks; 2453 2454 2455 DPRINTFN(2, ("msk_init\n")); 2456 2457 s = splnet(); 2458 2459 /* Cancel pending I/O and free all RX/TX buffers. */ 2460 msk_stop(ifp, 1); 2461 2462 /* Configure I2C registers */ 2463 2464 /* Configure XMAC(s) */ 2465 msk_init_yukon(sc_if); 2466 if ((rc = ether_mediachange(ifp)) != 0) 2467 goto out; 2468 2469 /* Configure transmit arbiter(s) */ 2470 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2471 #if 0 2472 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2473 #endif 2474 2475 if (sc->sk_ramsize) { 2476 /* Configure RAMbuffers */ 2477 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2478 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2479 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2480 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2481 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2482 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2483 2484 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2485 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2486 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2487 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2488 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2489 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2490 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2491 } 2492 2493 /* Configure BMUs */ 2494 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2495 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2496 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2497 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2498 2499 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2500 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2501 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2502 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2503 2504 /* Make sure the sync transmit queue is disabled. */ 2505 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2506 2507 /* Init descriptors */ 2508 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2509 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2510 "memory for rx buffers\n"); 2511 msk_stop(ifp, 1); 2512 splx(s); 2513 return ENOBUFS; 2514 } 2515 2516 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2517 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2518 "memory for tx buffers\n"); 2519 msk_stop(ifp, 1); 2520 splx(s); 2521 return ENOBUFS; 2522 } 2523 2524 /* Set interrupt moderation if changed via sysctl. */ 2525 switch (sc->sk_type) { 2526 case SK_YUKON_EC: 2527 case SK_YUKON_EC_U: 2528 case SK_YUKON_EX: 2529 case SK_YUKON_SUPR: 2530 case SK_YUKON_ULTRA2: 2531 case SK_YUKON_OPTIMA: 2532 case SK_YUKON_PRM: 2533 case SK_YUKON_OPTIMA2: 2534 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2535 break; 2536 case SK_YUKON_FE: 2537 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2538 break; 2539 case SK_YUKON_FE_P: 2540 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2541 break; 2542 case SK_YUKON_XL: 2543 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2544 break; 2545 default: 2546 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2547 } 2548 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2549 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2550 sk_win_write_4(sc, SK_IMTIMERINIT, 2551 SK_IM_USECS(sc->sk_int_mod)); 2552 aprint_verbose_dev(sc->sk_dev, 2553 "interrupt moderation is %d us\n", sc->sk_int_mod); 2554 } 2555 2556 /* Initialize prefetch engine. */ 2557 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2558 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2559 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2560 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2561 MSK_RX_RING_ADDR(sc_if, 0)); 2562 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2563 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2564 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2565 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2566 2567 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2568 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2569 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2570 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2571 MSK_TX_RING_ADDR(sc_if, 0)); 2572 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2573 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2574 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2575 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2576 2577 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2578 sc_if->sk_cdata.sk_rx_prod); 2579 2580 2581 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2582 /* Disable flushing of non-ASF packets. */ 2583 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2584 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2585 } 2586 2587 /* Configure interrupt handling */ 2588 if (sc_if->sk_port == SK_PORT_A) 2589 sc->sk_intrmask |= SK_Y2_INTRS1; 2590 else 2591 sc->sk_intrmask |= SK_Y2_INTRS2; 2592 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2593 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2594 2595 ifp->if_flags |= IFF_RUNNING; 2596 ifp->if_flags &= ~IFF_OACTIVE; 2597 2598 callout_schedule(&sc_if->sk_tick_ch, hz); 2599 2600 out: 2601 splx(s); 2602 return rc; 2603 } 2604 2605 /* 2606 * Note: the logic of second parameter is inverted compared to OpenBSD 2607 * code, since this code uses the function as if_stop hook too. 2608 */ 2609 static void 2610 msk_stop(struct ifnet *ifp, int disable) 2611 { 2612 struct sk_if_softc *sc_if = ifp->if_softc; 2613 struct sk_softc *sc = sc_if->sk_softc; 2614 struct sk_txmap_entry *dma; 2615 int i; 2616 2617 DPRINTFN(2, ("msk_stop\n")); 2618 2619 callout_stop(&sc_if->sk_tick_ch); 2620 callout_stop(&sc_if->sk_tick_rx); 2621 2622 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2623 2624 /* Stop transfer of Tx descriptors */ 2625 2626 /* Stop transfer of Rx descriptors */ 2627 2628 if (disable) { 2629 /* Turn off various components of this interface. */ 2630 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2631 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2632 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2633 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2634 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2635 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2636 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2637 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2638 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2639 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2640 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2641 2642 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2643 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2644 2645 /* Disable interrupts */ 2646 if (sc_if->sk_port == SK_PORT_A) 2647 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2648 else 2649 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2650 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2651 } 2652 2653 /* Free RX and TX mbufs still in the queues. */ 2654 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2655 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2656 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2657 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2658 } 2659 } 2660 2661 sc_if->sk_cdata.sk_rx_prod = 0; 2662 sc_if->sk_cdata.sk_rx_cons = 0; 2663 sc_if->sk_cdata.sk_rx_cnt = 0; 2664 2665 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2666 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2667 dma = sc_if->sk_cdata.sk_tx_map[i]; 2668 2669 bus_dmamap_sync(sc->sc_dmatag, dma->dmamap, 0, 2670 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2671 2672 bus_dmamap_unload(sc->sc_dmatag, dma->dmamap); 2673 2674 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2675 sc_if->sk_cdata.sk_tx_map[i], link); 2676 sc_if->sk_cdata.sk_tx_map[i] = 0; 2677 2678 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2679 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2680 } 2681 } 2682 } 2683 2684 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2685 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2686 2687 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2688 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2689 2690 #ifdef MSK_DEBUG 2691 static void 2692 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2693 { 2694 #define DESC_PRINT(X) \ 2695 if (X) \ 2696 printf("txdesc[%d]." #X "=%#x\n", \ 2697 idx, X); 2698 2699 DESC_PRINT(letoh32(le->sk_addr)); 2700 DESC_PRINT(letoh16(le->sk_len)); 2701 DESC_PRINT(le->sk_ctl); 2702 DESC_PRINT(le->sk_opcode); 2703 #undef DESC_PRINT 2704 } 2705 2706 static void 2707 msk_dump_bytes(const char *data, int len) 2708 { 2709 int c, i, j; 2710 2711 for (i = 0; i < len; i += 16) { 2712 printf("%08x ", i); 2713 c = len - i; 2714 if (c > 16) c = 16; 2715 2716 for (j = 0; j < c; j++) { 2717 printf("%02x ", data[i + j] & 0xff); 2718 if ((j & 0xf) == 7 && j > 0) 2719 printf(" "); 2720 } 2721 2722 for (; j < 16; j++) 2723 printf(" "); 2724 printf(" "); 2725 2726 for (j = 0; j < c; j++) { 2727 int ch = data[i + j] & 0xff; 2728 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2729 } 2730 2731 printf("\n"); 2732 2733 if (c < 16) 2734 break; 2735 } 2736 } 2737 2738 static void 2739 msk_dump_mbuf(struct mbuf *m) 2740 { 2741 int count = m->m_pkthdr.len; 2742 2743 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2744 2745 while (count > 0 && m) { 2746 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2747 m, m->m_data, m->m_len); 2748 if (mskdebug >= 4) 2749 msk_dump_bytes(mtod(m, char *), m->m_len); 2750 2751 count -= m->m_len; 2752 m = m->m_next; 2753 } 2754 } 2755 #endif 2756 2757 static int 2758 msk_sysctl_handler(SYSCTLFN_ARGS) 2759 { 2760 int error, t; 2761 struct sysctlnode node; 2762 struct sk_softc *sc; 2763 2764 node = *rnode; 2765 sc = node.sysctl_data; 2766 t = sc->sk_int_mod; 2767 node.sysctl_data = &t; 2768 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2769 if (error || newp == NULL) 2770 return error; 2771 2772 if (t < SK_IM_MIN || t > SK_IM_MAX) 2773 return EINVAL; 2774 2775 /* update the softc with sysctl-changed value, and mark 2776 for hardware update */ 2777 sc->sk_int_mod = t; 2778 sc->sk_int_mod_pending = 1; 2779 return 0; 2780 } 2781 2782 /* 2783 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2784 * set up in mskc_attach() 2785 */ 2786 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2787 { 2788 int rc; 2789 const struct sysctlnode *node; 2790 2791 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2792 0, CTLTYPE_NODE, "msk", 2793 SYSCTL_DESCR("msk interface controls"), 2794 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2795 goto err; 2796 } 2797 2798 msk_root_num = node->sysctl_num; 2799 return; 2800 2801 err: 2802 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2803 } 2804
Indexes created Wed Sep 24 15:09:51 GMT 2025