if_msk.c revision 1.106
1 /* $NetBSD: if_msk.c,v 1.106 2020/04/30 01:52:08 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.106 2020/04/30 01:52:08 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 le16toh 72 #define letoh32 le32toh 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/pci/if_skreg.h> 92 #include <dev/pci/if_mskvar.h> 93 94 static int mskc_probe(device_t, cfdata_t, void *); 95 static void mskc_attach(device_t, device_t, void *); 96 static int mskc_detach(device_t, int); 97 static void mskc_reset(struct sk_softc *); 98 static bool mskc_suspend(device_t, const pmf_qual_t *); 99 static bool mskc_resume(device_t, const pmf_qual_t *); 100 static int msk_probe(device_t, cfdata_t, void *); 101 static void msk_attach(device_t, device_t, void *); 102 static int msk_detach(device_t, int); 103 static void msk_reset(struct sk_if_softc *); 104 static int mskcprint(void *, const char *); 105 static int msk_intr(void *); 106 static void msk_intr_yukon(struct sk_if_softc *); 107 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 108 static void msk_txeof(struct sk_if_softc *); 109 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 110 static void msk_start(struct ifnet *); 111 static int msk_ioctl(struct ifnet *, u_long, void *); 112 static int msk_init(struct ifnet *); 113 static void msk_init_yukon(struct sk_if_softc *); 114 static void msk_stop(struct ifnet *, int); 115 static void msk_watchdog(struct ifnet *); 116 static int msk_newbuf(struct sk_if_softc *); 117 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 118 static void *msk_jalloc(struct sk_if_softc *); 119 static void msk_jfree(struct mbuf *, void *, size_t, void *); 120 static int msk_init_rx_ring(struct sk_if_softc *); 121 static int msk_init_tx_ring(struct sk_if_softc *); 122 static void msk_fill_rx_ring(struct sk_if_softc *); 123 124 static void msk_update_int_mod(struct sk_softc *, int); 125 126 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 127 static int msk_miibus_writereg(device_t, int, int, uint16_t); 128 static void msk_miibus_statchg(struct ifnet *); 129 130 static void msk_setmulti(struct sk_if_softc *); 131 static void msk_setpromisc(struct sk_if_softc *); 132 static void msk_tick(void *); 133 static void msk_fill_rx_tick(void *); 134 135 /* #define MSK_DEBUG 1 */ 136 #ifdef MSK_DEBUG 137 #define DPRINTF(x) if (mskdebug) printf x 138 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 139 int mskdebug = MSK_DEBUG; 140 141 static void msk_dump_txdesc(struct msk_tx_desc *, int); 142 static void msk_dump_mbuf(struct mbuf *); 143 static void msk_dump_bytes(const char *, int); 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 static int msk_sysctl_handler(SYSCTLFN_PROTO); 150 static int msk_root_num; 151 152 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 153 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 199 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 201 { 0, 0 } 202 }; 203 204 static inline uint32_t 205 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 206 { 207 return CSR_READ_4(sc, reg); 208 } 209 210 static inline uint16_t 211 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 212 { 213 return CSR_READ_2(sc, reg); 214 } 215 216 static inline uint8_t 217 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 218 { 219 return CSR_READ_1(sc, reg); 220 } 221 222 static inline void 223 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 224 { 225 CSR_WRITE_4(sc, reg, x); 226 } 227 228 static inline void 229 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 230 { 231 CSR_WRITE_2(sc, reg, x); 232 } 233 234 static inline void 235 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 236 { 237 CSR_WRITE_1(sc, reg, x); 238 } 239 240 static int 241 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 242 { 243 struct sk_if_softc *sc_if = device_private(dev); 244 uint16_t data; 245 int i; 246 247 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 248 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 249 250 for (i = 0; i < SK_TIMEOUT; i++) { 251 DELAY(1); 252 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 253 if (data & YU_SMICR_READ_VALID) 254 break; 255 } 256 257 if (i == SK_TIMEOUT) { 258 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 259 return ETIMEDOUT; 260 } 261 262 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 263 264 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 265 266 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 267 phy, reg, *val)); 268 269 return 0; 270 } 271 272 static int 273 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 274 { 275 struct sk_if_softc *sc_if = device_private(dev); 276 int i; 277 278 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 279 phy, reg, val)); 280 281 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 282 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 283 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 284 285 for (i = 0; i < SK_TIMEOUT; i++) { 286 DELAY(1); 287 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 288 break; 289 } 290 291 if (i == SK_TIMEOUT) { 292 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 293 return ETIMEDOUT; 294 } 295 296 return 0; 297 } 298 299 static void 300 msk_miibus_statchg(struct ifnet *ifp) 301 { 302 struct sk_if_softc *sc_if = ifp->if_softc; 303 struct mii_data *mii = &sc_if->sk_mii; 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 int gpcr; 306 307 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 308 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 309 310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 311 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 312 /* Set speed. */ 313 gpcr |= YU_GPCR_SPEED_DIS; 314 switch (IFM_SUBTYPE(mii->mii_media_active)) { 315 case IFM_1000_SX: 316 case IFM_1000_LX: 317 case IFM_1000_CX: 318 case IFM_1000_T: 319 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 320 break; 321 case IFM_100_TX: 322 gpcr |= YU_GPCR_SPEED; 323 break; 324 } 325 326 /* Set duplex. */ 327 gpcr |= YU_GPCR_DPLX_DIS; 328 if ((mii->mii_media_active & IFM_FDX) != 0) 329 gpcr |= YU_GPCR_DUPLEX; 330 331 /* Disable flow control. */ 332 gpcr |= YU_GPCR_FCTL_DIS; 333 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 334 } 335 336 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 337 338 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 339 SK_YU_READ_2(sc_if, YUKON_GPCR))); 340 } 341 342 static void 343 msk_setmulti(struct sk_if_softc *sc_if) 344 { 345 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 346 uint32_t hashes[2] = { 0, 0 }; 347 int h; 348 struct ethercom *ec = &sc_if->sk_ethercom; 349 struct ether_multi *enm; 350 struct ether_multistep step; 351 uint16_t reg; 352 353 /* First, zot all the existing filters. */ 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 358 359 360 /* Now program new ones. */ 361 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 362 reg |= YU_RCR_UFLEN; 363 allmulti: 364 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 365 if ((ifp->if_flags & IFF_PROMISC) != 0) 366 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 367 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 368 hashes[0] = 0xFFFFFFFF; 369 hashes[1] = 0xFFFFFFFF; 370 } 371 } else { 372 /* First find the tail of the list. */ 373 ETHER_LOCK(ec); 374 ETHER_FIRST_MULTI(step, ec, enm); 375 while (enm != NULL) { 376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 377 ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 ETHER_UNLOCK(ec); 380 goto allmulti; 381 } 382 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 383 ((1 << SK_HASH_BITS) - 1); 384 if (h < 32) 385 hashes[0] |= (1 << h); 386 else 387 hashes[1] |= (1 << (h - 32)); 388 389 ETHER_NEXT_MULTI(step, enm); 390 } 391 ETHER_UNLOCK(ec); 392 reg |= YU_RCR_MUFLEN; 393 } 394 395 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 400 } 401 402 static void 403 msk_setpromisc(struct sk_if_softc *sc_if) 404 { 405 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 406 407 if (ifp->if_flags & IFF_PROMISC) 408 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 409 YU_RCR_UFLEN | YU_RCR_MUFLEN); 410 else 411 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 412 YU_RCR_UFLEN | YU_RCR_MUFLEN); 413 } 414 415 static int 416 msk_init_rx_ring(struct sk_if_softc *sc_if) 417 { 418 struct msk_chain_data *cd = &sc_if->sk_cdata; 419 struct msk_ring_data *rd = sc_if->sk_rdata; 420 struct msk_rx_desc *r; 421 422 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 423 424 sc_if->sk_cdata.sk_rx_prod = 0; 425 sc_if->sk_cdata.sk_rx_cons = 0; 426 sc_if->sk_cdata.sk_rx_cnt = 0; 427 sc_if->sk_cdata.sk_rx_hiaddr = 0; 428 429 /* Mark the first ring element to initialize the high address. */ 430 sc_if->sk_cdata.sk_rx_hiaddr = 0; 431 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 432 r->sk_addr = htole32(cd->sk_rx_hiaddr); 433 r->sk_len = 0; 434 r->sk_ctl = 0; 435 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 436 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 438 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 439 sc_if->sk_cdata.sk_rx_cnt++; 440 441 msk_fill_rx_ring(sc_if); 442 return 0; 443 } 444 445 static int 446 msk_init_tx_ring(struct sk_if_softc *sc_if) 447 { 448 struct msk_chain_data *cd = &sc_if->sk_cdata; 449 struct msk_ring_data *rd = sc_if->sk_rdata; 450 struct msk_tx_desc *t; 451 452 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 453 454 sc_if->sk_cdata.sk_tx_prod = 0; 455 sc_if->sk_cdata.sk_tx_cons = 0; 456 sc_if->sk_cdata.sk_tx_cnt = 0; 457 sc_if->sk_cdata.sk_tx_hiaddr = 0; 458 459 /* Mark the first ring element to initialize the high address. */ 460 sc_if->sk_cdata.sk_tx_hiaddr = 0; 461 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 462 t->sk_addr = htole32(cd->sk_tx_hiaddr); 463 t->sk_len = 0; 464 t->sk_ctl = 0; 465 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 466 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 468 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 469 sc_if->sk_cdata.sk_tx_cnt++; 470 471 return 0; 472 } 473 474 static int 475 msk_newbuf(struct sk_if_softc *sc_if) 476 { 477 struct sk_softc *sc = sc_if->sk_softc; 478 struct mbuf *m_new = NULL; 479 struct sk_chain *c; 480 struct msk_rx_desc *r; 481 void *buf = NULL; 482 bus_addr_t addr; 483 bus_dmamap_t rxmap; 484 size_t i; 485 uint32_t rxidx, frag, cur, hiaddr, old_hiaddr, total; 486 uint32_t entries = 0; 487 488 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 489 if (m_new == NULL) 490 return ENOBUFS; 491 492 /* Allocate the jumbo buffer */ 493 buf = msk_jalloc(sc_if); 494 if (buf == NULL) { 495 m_freem(m_new); 496 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 497 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 498 return ENOBUFS; 499 } 500 501 /* Attach the buffer to the mbuf */ 502 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 503 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 504 505 m_adj(m_new, ETHER_ALIGN); 506 507 rxidx = frag = cur = sc_if->sk_cdata.sk_rx_prod; 508 rxmap = sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap; 509 510 if (bus_dmamap_load_mbuf(sc->sc_dmatag, rxmap, m_new, BUS_DMA_NOWAIT)) { 511 DPRINTFN(2, ("msk_newbuf: dmamap_load failed\n")); 512 m_freem(m_new); 513 return ENOBUFS; 514 } 515 516 /* Count how many rx descriptors needed. */ 517 hiaddr = sc_if->sk_cdata.sk_rx_hiaddr; 518 for (total = i = 0; i < rxmap->dm_nsegs; i++) { 519 if (hiaddr != MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr)) { 520 hiaddr = MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr); 521 total++; 522 } 523 total++; 524 } 525 526 if (total > MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt - 1) { 527 DPRINTFN(2, ("msk_newbuf: too few descriptors free\n")); 528 bus_dmamap_unload(sc->sc_dmatag, rxmap); 529 m_freem(m_new); 530 return ENOBUFS; 531 } 532 533 DPRINTFN(2, ("msk_newbuf: dm_nsegs=%d total desc=%u\n", 534 rxmap->dm_nsegs, total)); 535 536 /* Sync the DMA map. */ 537 bus_dmamap_sync(sc->sc_dmatag, rxmap, 0, rxmap->dm_mapsize, 538 BUS_DMASYNC_PREREAD); 539 540 old_hiaddr = sc_if->sk_cdata.sk_rx_hiaddr; 541 for (i = 0; i < rxmap->dm_nsegs; i++) { 542 addr = rxmap->dm_segs[i].ds_addr; 543 DPRINTFN(2, ("msk_newbuf: addr %llx\n", 544 (unsigned long long)addr)); 545 hiaddr = MSK_ADDR_HI(addr); 546 547 if (sc_if->sk_cdata.sk_rx_hiaddr != hiaddr) { 548 c = &sc_if->sk_cdata.sk_rx_chain[frag]; 549 c->sk_mbuf = NULL; 550 r = &sc_if->sk_rdata->sk_rx_ring[frag]; 551 r->sk_addr = htole32(hiaddr); 552 r->sk_len = 0; 553 r->sk_ctl = 0; 554 if (i == 0) 555 r->sk_opcode = SK_Y2_BMUOPC_ADDR64; 556 else 557 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | 558 SK_Y2_RXOPC_OWN; 559 sc_if->sk_cdata.sk_rx_hiaddr = hiaddr; 560 MSK_CDRXSYNC(sc_if, frag, 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 SK_INC(frag, MSK_RX_RING_CNT); 563 entries++; 564 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 565 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 566 } 567 568 c = &sc_if->sk_cdata.sk_rx_chain[frag]; 569 r = &sc_if->sk_rdata->sk_rx_ring[frag]; 570 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 571 r->sk_len = htole16(rxmap->dm_segs[i].ds_len); 572 r->sk_ctl = 0; 573 if (i == 0) { 574 if (hiaddr != old_hiaddr) 575 r->sk_opcode = SK_Y2_RXOPC_PACKET | 576 SK_Y2_RXOPC_OWN; 577 else 578 r->sk_opcode = SK_Y2_RXOPC_PACKET; 579 } else 580 r->sk_opcode = SK_Y2_RXOPC_BUFFER | SK_Y2_RXOPC_OWN; 581 MSK_CDRXSYNC(sc_if, frag, 582 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 583 cur = frag; 584 SK_INC(frag, MSK_RX_RING_CNT); 585 entries++; 586 } 587 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 588 589 sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap = 590 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap; 591 sc_if->sk_cdata.sk_rx_chain[cur].sk_mbuf = m_new; 592 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap = rxmap; 593 594 sc_if->sk_rdata->sk_rx_ring[rxidx].sk_opcode |= SK_Y2_RXOPC_OWN; 595 MSK_CDRXSYNC(sc_if, rxidx, 596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 597 598 sc_if->sk_cdata.sk_rx_cnt += entries; 599 sc_if->sk_cdata.sk_rx_prod = frag; 600 601 return 0; 602 } 603 604 /* 605 * Memory management for jumbo frames. 606 */ 607 608 static int 609 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 610 { 611 struct sk_softc *sc = sc_if->sk_softc; 612 char *ptr, *kva; 613 int i, state, error; 614 struct sk_jpool_entry *entry; 615 616 state = error = 0; 617 618 /* Grab a big chunk o' storage. */ 619 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 620 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 621 BUS_DMA_NOWAIT)) { 622 aprint_error(": can't alloc rx buffers"); 623 return ENOBUFS; 624 } 625 626 state = 1; 627 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 628 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 629 BUS_DMA_NOWAIT)) { 630 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 631 error = ENOBUFS; 632 goto out; 633 } 634 635 state = 2; 636 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 637 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 638 aprint_error(": can't create dma map"); 639 error = ENOBUFS; 640 goto out; 641 } 642 643 state = 3; 644 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 645 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 646 aprint_error(": can't load dma map"); 647 error = ENOBUFS; 648 goto out; 649 } 650 651 state = 4; 652 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 653 DPRINTFN(1,("msk_jumbo_buf = %p\n", 654 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 655 656 LIST_INIT(&sc_if->sk_jfree_listhead); 657 LIST_INIT(&sc_if->sk_jinuse_listhead); 658 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 659 660 /* 661 * Now divide it up into 9K pieces and save the addresses 662 * in an array. 663 */ 664 ptr = sc_if->sk_cdata.sk_jumbo_buf; 665 for (i = 0; i < MSK_JSLOTS; i++) { 666 sc_if->sk_cdata.sk_jslots[i] = ptr; 667 ptr += SK_JLEN; 668 entry = malloc(sizeof(struct sk_jpool_entry), 669 M_DEVBUF, M_WAITOK); 670 entry->slot = i; 671 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 672 entry, jpool_entries); 673 } 674 out: 675 if (error != 0) { 676 switch (state) { 677 case 4: 678 bus_dmamap_unload(sc->sc_dmatag, 679 sc_if->sk_cdata.sk_rx_jumbo_map); 680 /* FALLTHROUGH */ 681 case 3: 682 bus_dmamap_destroy(sc->sc_dmatag, 683 sc_if->sk_cdata.sk_rx_jumbo_map); 684 /* FALLTHROUGH */ 685 case 2: 686 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 687 /* FALLTHROUGH */ 688 case 1: 689 bus_dmamem_free(sc->sc_dmatag, 690 &sc_if->sk_cdata.sk_jumbo_seg, 691 sc_if->sk_cdata.sk_jumbo_nseg); 692 break; 693 default: 694 break; 695 } 696 } 697 698 return error; 699 } 700 701 static void 702 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 703 { 704 struct sk_softc *sc = sc_if->sk_softc; 705 706 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 707 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 708 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 709 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 710 sc_if->sk_cdata.sk_jumbo_nseg); 711 } 712 713 /* 714 * Allocate a jumbo buffer. 715 */ 716 static void * 717 msk_jalloc(struct sk_if_softc *sc_if) 718 { 719 struct sk_jpool_entry *entry; 720 721 mutex_enter(&sc_if->sk_jpool_mtx); 722 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 723 724 if (entry == NULL) { 725 mutex_exit(&sc_if->sk_jpool_mtx); 726 return NULL; 727 } 728 729 LIST_REMOVE(entry, jpool_entries); 730 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 731 mutex_exit(&sc_if->sk_jpool_mtx); 732 return sc_if->sk_cdata.sk_jslots[entry->slot]; 733 } 734 735 /* 736 * Release a jumbo buffer. 737 */ 738 static void 739 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 740 { 741 struct sk_jpool_entry *entry; 742 struct sk_if_softc *sc; 743 int i; 744 745 /* Extract the softc struct pointer. */ 746 sc = (struct sk_if_softc *)arg; 747 748 if (sc == NULL) 749 panic("msk_jfree: can't find softc pointer!"); 750 751 /* calculate the slot this buffer belongs to */ 752 i = ((vaddr_t)buf 753 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 754 755 if ((i < 0) || (i >= MSK_JSLOTS)) 756 panic("msk_jfree: asked to free buffer that we don't manage!"); 757 758 mutex_enter(&sc->sk_jpool_mtx); 759 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 760 if (entry == NULL) 761 panic("msk_jfree: buffer not in use!"); 762 entry->slot = i; 763 LIST_REMOVE(entry, jpool_entries); 764 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 765 mutex_exit(&sc->sk_jpool_mtx); 766 767 if (__predict_true(m != NULL)) 768 pool_cache_put(mb_cache, m); 769 770 /* Now that we know we have a free RX buffer, refill if running out */ 771 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 772 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 773 callout_schedule(&sc->sk_tick_rx, 0); 774 } 775 776 static int 777 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 778 { 779 struct sk_if_softc *sc = ifp->if_softc; 780 int s, error; 781 782 s = splnet(); 783 784 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 785 switch (cmd) { 786 case SIOCSIFFLAGS: 787 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 788 break; 789 790 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 791 case IFF_RUNNING: 792 msk_stop(ifp, 1); 793 break; 794 case IFF_UP: 795 msk_init(ifp); 796 break; 797 case IFF_UP | IFF_RUNNING: 798 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 799 msk_setpromisc(sc); 800 msk_setmulti(sc); 801 } else 802 msk_init(ifp); 803 break; 804 } 805 sc->sk_if_flags = ifp->if_flags; 806 break; 807 default: 808 error = ether_ioctl(ifp, cmd, data); 809 if (error == ENETRESET) { 810 error = 0; 811 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 812 ; 813 else if (ifp->if_flags & IFF_RUNNING) { 814 /* 815 * Multicast list has changed; set the hardware 816 * filter accordingly. 817 */ 818 msk_setmulti(sc); 819 } 820 } 821 break; 822 } 823 824 splx(s); 825 return error; 826 } 827 828 static void 829 msk_update_int_mod(struct sk_softc *sc, int verbose) 830 { 831 uint32_t imtimer_ticks; 832 833 /* 834 * Configure interrupt moderation. The moderation timer 835 * defers interrupts specified in the interrupt moderation 836 * timer mask based on the timeout specified in the interrupt 837 * moderation timer init register. Each bit in the timer 838 * register represents one tick, so to specify a timeout in 839 * microseconds, we have to multiply by the correct number of 840 * ticks-per-microsecond. 841 */ 842 switch (sc->sk_type) { 843 case SK_YUKON_EC: 844 case SK_YUKON_EC_U: 845 case SK_YUKON_EX: 846 case SK_YUKON_SUPR: 847 case SK_YUKON_ULTRA2: 848 case SK_YUKON_OPTIMA: 849 case SK_YUKON_PRM: 850 case SK_YUKON_OPTIMA2: 851 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 852 break; 853 case SK_YUKON_FE: 854 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 855 break; 856 case SK_YUKON_FE_P: 857 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 858 break; 859 case SK_YUKON_XL: 860 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 861 break; 862 default: 863 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 864 } 865 if (verbose) 866 aprint_verbose_dev(sc->sk_dev, 867 "interrupt moderation is %d us\n", sc->sk_int_mod); 868 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 869 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 870 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 871 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 872 sc->sk_int_mod_pending = 0; 873 } 874 875 static int 876 msk_lookup(const struct pci_attach_args *pa) 877 { 878 const struct msk_product *pmsk; 879 880 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 881 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 882 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 883 return 1; 884 } 885 return 0; 886 } 887 888 /* 889 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 890 * IDs against our list and return a device name if we find a match. 891 */ 892 static int 893 mskc_probe(device_t parent, cfdata_t match, void *aux) 894 { 895 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 896 897 return msk_lookup(pa); 898 } 899 900 /* 901 * Force the GEnesis into reset, then bring it out of reset. 902 */ 903 static void 904 mskc_reset(struct sk_softc *sc) 905 { 906 uint32_t imtimer_ticks, reg1; 907 uint16_t status; 908 int reg; 909 910 DPRINTFN(2, ("mskc_reset\n")); 911 912 /* Disable ASF */ 913 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 914 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 915 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 916 /* Clear AHB bridge & microcontroller reset. */ 917 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 918 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 919 /* Clear ASF microcontroller state. */ 920 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 921 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 922 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 923 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 924 } else 925 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 926 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 927 928 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 929 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 930 931 DELAY(1000); 932 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 933 DELAY(2); 934 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 935 sk_win_write_1(sc, SK_TESTCTL1, 2); 936 937 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 938 sc->sk_type >= SK_YUKON_FE_P) { 939 uint32_t our; 940 941 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 942 943 /* enable all clocks. */ 944 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 945 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 946 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 947 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 948 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 949 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 950 /* Set all bits to 0 except bits 15..12 */ 951 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 952 /* Set to default value */ 953 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 954 955 /* 956 * Disable status race, workaround for Yukon EC Ultra & 957 * Yukon EX. 958 */ 959 reg1 = sk_win_read_4(sc, SK_GPIO); 960 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 961 sk_win_write_4(sc, SK_GPIO, reg1); 962 sk_win_read_4(sc, SK_GPIO); 963 } 964 965 /* release PHY from PowerDown/Coma mode. */ 966 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 967 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 968 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 969 else 970 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 971 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 972 973 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 974 sk_win_write_1(sc, SK_Y2_CLKGATE, 975 SK_Y2_CLKGATE_LINK1_GATE_DIS | 976 SK_Y2_CLKGATE_LINK2_GATE_DIS | 977 SK_Y2_CLKGATE_LINK1_CORE_DIS | 978 SK_Y2_CLKGATE_LINK2_CORE_DIS | 979 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 980 else 981 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 982 983 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 984 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 985 DELAY(1000); 986 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 987 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 988 989 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 990 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 991 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 992 } 993 994 sk_win_write_1(sc, SK_TESTCTL1, 1); 995 996 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 997 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 998 CSR_READ_2(sc, SK_LINK_CTRL))); 999 1000 /* Clear I2C IRQ noise */ 1001 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 1002 1003 /* Disable hardware timer */ 1004 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 1005 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 1006 1007 /* Disable descriptor polling */ 1008 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 1009 1010 /* Disable time stamps */ 1011 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 1012 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 1013 1014 /* Enable RAM interface */ 1015 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1016 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1017 sk_win_write_1(sc, reg, 36); 1018 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 1019 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1020 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 1021 1022 /* 1023 * Configure interrupt moderation. The moderation timer 1024 * defers interrupts specified in the interrupt moderation 1025 * timer mask based on the timeout specified in the interrupt 1026 * moderation timer init register. Each bit in the timer 1027 * register represents one tick, so to specify a timeout in 1028 * microseconds, we have to multiply by the correct number of 1029 * ticks-per-microsecond. 1030 */ 1031 switch (sc->sk_type) { 1032 case SK_YUKON_EC: 1033 case SK_YUKON_EC_U: 1034 case SK_YUKON_EX: 1035 case SK_YUKON_SUPR: 1036 case SK_YUKON_ULTRA2: 1037 case SK_YUKON_OPTIMA: 1038 case SK_YUKON_PRM: 1039 case SK_YUKON_OPTIMA2: 1040 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1041 break; 1042 case SK_YUKON_FE: 1043 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1044 break; 1045 case SK_YUKON_FE_P: 1046 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1047 break; 1048 case SK_YUKON_XL: 1049 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1050 break; 1051 default: 1052 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1053 break; 1054 } 1055 1056 /* Reset status ring. */ 1057 memset(sc->sk_status_ring, 0, 1058 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1059 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1060 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1061 sc->sk_status_idx = 0; 1062 1063 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1064 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1065 1066 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1067 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1068 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1069 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1070 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1071 if (sc->sk_type == SK_YUKON_EC && 1072 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1073 /* WA for dev. #4.3 */ 1074 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1075 SK_STAT_BMU_TXTHIDX_MSK); 1076 /* WA for dev. #4.18 */ 1077 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1078 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1079 } else { 1080 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1081 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1082 if (sc->sk_type == SK_YUKON_XL) 1083 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1084 else 1085 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1086 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1087 } 1088 1089 #if 0 1090 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1091 #endif 1092 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1093 1094 /* Enable status unit. */ 1095 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1096 1097 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1098 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1099 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1100 1101 msk_update_int_mod(sc, 0); 1102 } 1103 1104 static int 1105 msk_probe(device_t parent, cfdata_t match, void *aux) 1106 { 1107 struct skc_attach_args *sa = aux; 1108 1109 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1110 return 0; 1111 1112 switch (sa->skc_type) { 1113 case SK_YUKON_XL: 1114 case SK_YUKON_EC_U: 1115 case SK_YUKON_EX: 1116 case SK_YUKON_EC: 1117 case SK_YUKON_FE: 1118 case SK_YUKON_FE_P: 1119 case SK_YUKON_SUPR: 1120 case SK_YUKON_ULTRA2: 1121 case SK_YUKON_OPTIMA: 1122 case SK_YUKON_PRM: 1123 case SK_YUKON_OPTIMA2: 1124 return 1; 1125 } 1126 1127 return 0; 1128 } 1129 1130 static void 1131 msk_reset(struct sk_if_softc *sc_if) 1132 { 1133 /* GMAC and GPHY Reset */ 1134 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1135 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1136 DELAY(1000); 1137 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1138 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1139 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1140 } 1141 1142 static bool 1143 msk_resume(device_t dv, const pmf_qual_t *qual) 1144 { 1145 struct sk_if_softc *sc_if = device_private(dv); 1146 1147 msk_init_yukon(sc_if); 1148 return true; 1149 } 1150 1151 /* 1152 * Each XMAC chip is attached as a separate logical IP interface. 1153 * Single port cards will have only one logical interface of course. 1154 */ 1155 static void 1156 msk_attach(device_t parent, device_t self, void *aux) 1157 { 1158 struct sk_if_softc *sc_if = device_private(self); 1159 struct sk_softc *sc = device_private(parent); 1160 struct skc_attach_args *sa = aux; 1161 bus_dmamap_t dmamap; 1162 struct ifnet *ifp; 1163 struct mii_data * const mii = &sc_if->sk_mii; 1164 void *kva; 1165 int i; 1166 uint32_t chunk; 1167 int mii_flags; 1168 1169 sc_if->sk_dev = self; 1170 sc_if->sk_port = sa->skc_port; 1171 sc_if->sk_softc = sc; 1172 sc->sk_if[sa->skc_port] = sc_if; 1173 1174 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1175 1176 /* 1177 * Get station address for this interface. Note that 1178 * dual port cards actually come with three station 1179 * addresses: one for each port, plus an extra. The 1180 * extra one is used by the SysKonnect driver software 1181 * as a 'virtual' station address for when both ports 1182 * are operating in failover mode. Currently we don't 1183 * use this extra address. 1184 */ 1185 for (i = 0; i < ETHER_ADDR_LEN; i++) 1186 sc_if->sk_enaddr[i] = 1187 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1188 1189 aprint_normal(": Ethernet address %s\n", 1190 ether_sprintf(sc_if->sk_enaddr)); 1191 1192 /* 1193 * Set up RAM buffer addresses. The Yukon2 has a small amount 1194 * of SRAM on it, somewhere between 4K and 48K. We need to 1195 * divide this up between the transmitter and receiver. We 1196 * give the receiver 2/3 of the memory (rounded down), and the 1197 * transmitter whatever remains. 1198 */ 1199 if (sc->sk_ramsize) { 1200 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1201 sc_if->sk_rx_ramstart = 0; 1202 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1203 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1204 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1205 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1206 1207 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1208 " tx_ramstart=%#x tx_ramend=%#x\n", 1209 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1210 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1211 } 1212 1213 /* Allocate the descriptor queues. */ 1214 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1215 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1216 BUS_DMA_NOWAIT)) { 1217 aprint_error(": can't alloc rx buffers\n"); 1218 goto fail; 1219 } 1220 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1221 sc_if->sk_ring_nseg, 1222 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1223 aprint_error(": can't map dma buffers (%zu bytes)\n", 1224 sizeof(struct msk_ring_data)); 1225 goto fail_1; 1226 } 1227 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1228 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1229 &sc_if->sk_ring_map)) { 1230 aprint_error(": can't create dma map\n"); 1231 goto fail_2; 1232 } 1233 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1234 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1235 aprint_error(": can't load dma map\n"); 1236 goto fail_3; 1237 } 1238 1239 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1240 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1241 1242 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1243 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1244 aprint_error_dev(sc_if->sk_dev, 1245 "Can't create TX dmamap\n"); 1246 goto fail_3; 1247 } 1248 1249 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap = dmamap; 1250 } 1251 1252 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1253 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1254 1255 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, 1256 howmany(SK_JLEN + 1, NBPG), 1257 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1258 aprint_error_dev(sc_if->sk_dev, 1259 "Can't create RX dmamap\n"); 1260 goto fail_3; 1261 } 1262 1263 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap = dmamap; 1264 } 1265 1266 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1267 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1268 1269 if (sc->sk_type != SK_YUKON_FE && 1270 sc->sk_type != SK_YUKON_FE_P) 1271 sc_if->sk_pktlen = SK_JLEN; 1272 else 1273 sc_if->sk_pktlen = MCLBYTES; 1274 1275 /* Try to allocate memory for jumbo buffers. */ 1276 if (msk_alloc_jumbo_mem(sc_if)) { 1277 aprint_error(": jumbo buffer allocation failed\n"); 1278 goto fail_3; 1279 } 1280 1281 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1282 if (sc->sk_type != SK_YUKON_FE && 1283 sc->sk_type != SK_YUKON_FE_P) 1284 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1285 1286 ifp = &sc_if->sk_ethercom.ec_if; 1287 ifp->if_softc = sc_if; 1288 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1289 ifp->if_ioctl = msk_ioctl; 1290 ifp->if_start = msk_start; 1291 ifp->if_stop = msk_stop; 1292 ifp->if_init = msk_init; 1293 ifp->if_watchdog = msk_watchdog; 1294 ifp->if_baudrate = 1000000000; 1295 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1296 IFQ_SET_READY(&ifp->if_snd); 1297 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1298 1299 msk_reset(sc_if); 1300 1301 /* 1302 * Do miibus setup. 1303 */ 1304 DPRINTFN(2, ("msk_attach: 1\n")); 1305 1306 mii->mii_ifp = ifp; 1307 mii->mii_readreg = msk_miibus_readreg; 1308 mii->mii_writereg = msk_miibus_writereg; 1309 mii->mii_statchg = msk_miibus_statchg; 1310 1311 sc_if->sk_ethercom.ec_mii = mii; 1312 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1313 mii_flags = MIIF_DOPAUSE; 1314 if (sc->sk_fibertype) 1315 mii_flags |= MIIF_HAVEFIBER; 1316 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1317 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1318 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1319 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1320 0, NULL); 1321 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1322 } else 1323 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1324 1325 callout_init(&sc_if->sk_tick_ch, 0); 1326 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1327 callout_schedule(&sc_if->sk_tick_ch, hz); 1328 1329 callout_init(&sc_if->sk_tick_rx, 0); 1330 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1331 1332 /* 1333 * Call MI attach routines. 1334 */ 1335 if_attach(ifp); 1336 if_deferred_start_init(ifp, NULL); 1337 ether_ifattach(ifp, sc_if->sk_enaddr); 1338 1339 if (pmf_device_register(self, NULL, msk_resume)) 1340 pmf_class_network_register(self, ifp); 1341 else 1342 aprint_error_dev(self, "couldn't establish power handler\n"); 1343 1344 if (sc->rnd_attached++ == 0) { 1345 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1346 RND_TYPE_NET, RND_FLAG_DEFAULT); 1347 } 1348 1349 DPRINTFN(2, ("msk_attach: end\n")); 1350 return; 1351 1352 fail_3: 1353 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1354 fail_2: 1355 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1356 fail_1: 1357 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1358 fail: 1359 sc->sk_if[sa->skc_port] = NULL; 1360 } 1361 1362 static int 1363 msk_detach(device_t self, int flags) 1364 { 1365 struct sk_if_softc *sc_if = device_private(self); 1366 struct sk_softc *sc = sc_if->sk_softc; 1367 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1368 int i; 1369 1370 if (sc->sk_if[sc_if->sk_port] == NULL) 1371 return 0; 1372 1373 msk_stop(ifp, 1); 1374 1375 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1376 bus_dmamap_destroy(sc->sc_dmatag, 1377 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap); 1378 } 1379 1380 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1381 bus_dmamap_destroy(sc->sc_dmatag, 1382 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap); 1383 } 1384 1385 if (--sc->rnd_attached == 0) 1386 rnd_detach_source(&sc->rnd_source); 1387 1388 callout_halt(&sc_if->sk_tick_ch, NULL); 1389 callout_destroy(&sc_if->sk_tick_ch); 1390 1391 callout_halt(&sc_if->sk_tick_rx, NULL); 1392 callout_destroy(&sc_if->sk_tick_rx); 1393 1394 /* Detach any PHYs we might have. */ 1395 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1396 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1397 1398 pmf_device_deregister(self); 1399 1400 ether_ifdetach(ifp); 1401 if_detach(ifp); 1402 1403 /* Delete any remaining media. */ 1404 ifmedia_fini(&sc_if->sk_mii.mii_media); 1405 1406 msk_free_jumbo_mem(sc_if); 1407 1408 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1409 sizeof(struct msk_ring_data)); 1410 bus_dmamem_free(sc->sc_dmatag, 1411 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1412 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1413 sc->sk_if[sc_if->sk_port] = NULL; 1414 1415 return 0; 1416 } 1417 1418 static int 1419 mskcprint(void *aux, const char *pnp) 1420 { 1421 struct skc_attach_args *sa = aux; 1422 1423 if (pnp) 1424 aprint_normal("msk port %c at %s", 1425 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1426 else 1427 aprint_normal(" port %c", 1428 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1429 return UNCONF; 1430 } 1431 1432 /* 1433 * Attach the interface. Allocate softc structures, do ifmedia 1434 * setup and ethernet/BPF attach. 1435 */ 1436 static void 1437 mskc_attach(device_t parent, device_t self, void *aux) 1438 { 1439 struct sk_softc *sc = device_private(self); 1440 struct pci_attach_args *pa = aux; 1441 struct skc_attach_args skca; 1442 pci_chipset_tag_t pc = pa->pa_pc; 1443 pcireg_t command, memtype; 1444 const char *intrstr = NULL; 1445 int rc, sk_nodenum; 1446 uint8_t hw, pmd; 1447 const char *revstr = NULL; 1448 const struct sysctlnode *node; 1449 void *kva; 1450 char intrbuf[PCI_INTRSTR_LEN]; 1451 1452 DPRINTFN(2, ("begin mskc_attach\n")); 1453 1454 sc->sk_dev = self; 1455 /* 1456 * Handle power management nonsense. 1457 */ 1458 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1459 1460 if (command == 0x01) { 1461 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1462 if (command & SK_PSTATE_MASK) { 1463 uint32_t iobase, membase, irq; 1464 1465 /* Save important PCI config data. */ 1466 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1467 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1468 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1469 1470 /* Reset the power state. */ 1471 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1472 "mode -- setting to D0\n", 1473 command & SK_PSTATE_MASK); 1474 command &= 0xFFFFFFFC; 1475 pci_conf_write(pc, pa->pa_tag, 1476 SK_PCI_PWRMGMTCTRL, command); 1477 1478 /* Restore PCI config data. */ 1479 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1480 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1481 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1482 } 1483 } 1484 1485 /* 1486 * Map control/status registers. 1487 */ 1488 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1489 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1490 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1491 aprint_error(": can't map mem space\n"); 1492 return; 1493 } 1494 1495 if (pci_dma64_available(pa)) 1496 sc->sc_dmatag = pa->pa_dmat64; 1497 else 1498 sc->sc_dmatag = pa->pa_dmat; 1499 1500 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1501 command |= PCI_COMMAND_MASTER_ENABLE; 1502 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1503 1504 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1505 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1506 1507 /* bail out here if chip is not recognized */ 1508 if (!(SK_IS_YUKON2(sc))) { 1509 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1510 goto fail_1; 1511 } 1512 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1513 1514 /* Allocate interrupt */ 1515 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1516 aprint_error(": couldn't map interrupt\n"); 1517 goto fail_1; 1518 } 1519 1520 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1521 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1522 msk_intr, sc, device_xname(sc->sk_dev)); 1523 if (sc->sk_intrhand == NULL) { 1524 aprint_error(": couldn't establish interrupt"); 1525 if (intrstr != NULL) 1526 aprint_error(" at %s", intrstr); 1527 aprint_error("\n"); 1528 goto fail_1; 1529 } 1530 sc->sk_pc = pc; 1531 1532 if (bus_dmamem_alloc(sc->sc_dmatag, 1533 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1534 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1535 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1536 aprint_error(": can't alloc status buffers\n"); 1537 goto fail_2; 1538 } 1539 1540 if (bus_dmamem_map(sc->sc_dmatag, 1541 &sc->sk_status_seg, sc->sk_status_nseg, 1542 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1543 &kva, BUS_DMA_NOWAIT)) { 1544 aprint_error(": can't map dma buffers (%zu bytes)\n", 1545 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1546 goto fail_3; 1547 } 1548 if (bus_dmamap_create(sc->sc_dmatag, 1549 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1550 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1551 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1552 aprint_error(": can't create dma map\n"); 1553 goto fail_4; 1554 } 1555 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1556 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1557 NULL, BUS_DMA_NOWAIT)) { 1558 aprint_error(": can't load dma map\n"); 1559 goto fail_5; 1560 } 1561 sc->sk_status_ring = (struct msk_status_desc *)kva; 1562 1563 sc->sk_int_mod = SK_IM_DEFAULT; 1564 sc->sk_int_mod_pending = 0; 1565 1566 /* Reset the adapter. */ 1567 mskc_reset(sc); 1568 1569 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1570 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1571 1572 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1573 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1574 sc->sk_fibertype = 1; 1575 1576 switch (sc->sk_type) { 1577 case SK_YUKON_XL: 1578 sc->sk_name = "Yukon-2 XL"; 1579 break; 1580 case SK_YUKON_EC_U: 1581 sc->sk_name = "Yukon-2 EC Ultra"; 1582 break; 1583 case SK_YUKON_EX: 1584 sc->sk_name = "Yukon-2 Extreme"; 1585 break; 1586 case SK_YUKON_EC: 1587 sc->sk_name = "Yukon-2 EC"; 1588 break; 1589 case SK_YUKON_FE: 1590 sc->sk_name = "Yukon-2 FE"; 1591 break; 1592 case SK_YUKON_FE_P: 1593 sc->sk_name = "Yukon-2 FE+"; 1594 break; 1595 case SK_YUKON_SUPR: 1596 sc->sk_name = "Yukon-2 Supreme"; 1597 break; 1598 case SK_YUKON_ULTRA2: 1599 sc->sk_name = "Yukon-2 Ultra 2"; 1600 break; 1601 case SK_YUKON_OPTIMA: 1602 sc->sk_name = "Yukon-2 Optima"; 1603 break; 1604 case SK_YUKON_PRM: 1605 sc->sk_name = "Yukon-2 Optima Prime"; 1606 break; 1607 case SK_YUKON_OPTIMA2: 1608 sc->sk_name = "Yukon-2 Optima 2"; 1609 break; 1610 default: 1611 sc->sk_name = "Yukon (Unknown)"; 1612 } 1613 1614 if (sc->sk_type == SK_YUKON_XL) { 1615 switch (sc->sk_rev) { 1616 case SK_YUKON_XL_REV_A0: 1617 revstr = "A0"; 1618 break; 1619 case SK_YUKON_XL_REV_A1: 1620 revstr = "A1"; 1621 break; 1622 case SK_YUKON_XL_REV_A2: 1623 revstr = "A2"; 1624 break; 1625 case SK_YUKON_XL_REV_A3: 1626 revstr = "A3"; 1627 break; 1628 default: 1629 break; 1630 } 1631 } 1632 1633 if (sc->sk_type == SK_YUKON_EC) { 1634 switch (sc->sk_rev) { 1635 case SK_YUKON_EC_REV_A1: 1636 revstr = "A1"; 1637 break; 1638 case SK_YUKON_EC_REV_A2: 1639 revstr = "A2"; 1640 break; 1641 case SK_YUKON_EC_REV_A3: 1642 revstr = "A3"; 1643 break; 1644 default: 1645 break; 1646 } 1647 } 1648 1649 if (sc->sk_type == SK_YUKON_FE) { 1650 switch (sc->sk_rev) { 1651 case SK_YUKON_FE_REV_A1: 1652 revstr = "A1"; 1653 break; 1654 case SK_YUKON_FE_REV_A2: 1655 revstr = "A2"; 1656 break; 1657 default: 1658 break; 1659 } 1660 } 1661 1662 if (sc->sk_type == SK_YUKON_EC_U) { 1663 switch (sc->sk_rev) { 1664 case SK_YUKON_EC_U_REV_A0: 1665 revstr = "A0"; 1666 break; 1667 case SK_YUKON_EC_U_REV_A1: 1668 revstr = "A1"; 1669 break; 1670 case SK_YUKON_EC_U_REV_B0: 1671 revstr = "B0"; 1672 break; 1673 case SK_YUKON_EC_U_REV_B1: 1674 revstr = "B1"; 1675 break; 1676 default: 1677 break; 1678 } 1679 } 1680 1681 if (sc->sk_type == SK_YUKON_FE) { 1682 switch (sc->sk_rev) { 1683 case SK_YUKON_FE_REV_A1: 1684 revstr = "A1"; 1685 break; 1686 case SK_YUKON_FE_REV_A2: 1687 revstr = "A2"; 1688 break; 1689 default: 1690 ; 1691 } 1692 } 1693 1694 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1695 revstr = "A0"; 1696 1697 if (sc->sk_type == SK_YUKON_EX) { 1698 switch (sc->sk_rev) { 1699 case SK_YUKON_EX_REV_A0: 1700 revstr = "A0"; 1701 break; 1702 case SK_YUKON_EX_REV_B0: 1703 revstr = "B0"; 1704 break; 1705 default: 1706 ; 1707 } 1708 } 1709 1710 if (sc->sk_type == SK_YUKON_SUPR) { 1711 switch (sc->sk_rev) { 1712 case SK_YUKON_SUPR_REV_A0: 1713 revstr = "A0"; 1714 break; 1715 case SK_YUKON_SUPR_REV_B0: 1716 revstr = "B0"; 1717 break; 1718 case SK_YUKON_SUPR_REV_B1: 1719 revstr = "B1"; 1720 break; 1721 default: 1722 ; 1723 } 1724 } 1725 1726 if (sc->sk_type == SK_YUKON_PRM) { 1727 switch (sc->sk_rev) { 1728 case SK_YUKON_PRM_REV_Z1: 1729 revstr = "Z1"; 1730 break; 1731 case SK_YUKON_PRM_REV_A0: 1732 revstr = "A0"; 1733 break; 1734 default: 1735 ; 1736 } 1737 } 1738 1739 /* Announce the product name. */ 1740 aprint_normal(", %s", sc->sk_name); 1741 if (revstr != NULL) 1742 aprint_normal(" rev. %s", revstr); 1743 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1744 1745 aprint_normal_dev(sc->sk_dev, "interrupting at %s\n", intrstr); 1746 1747 sc->sk_macs = 1; 1748 1749 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1750 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1751 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1752 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1753 sc->sk_macs++; 1754 } 1755 1756 skca.skc_port = SK_PORT_A; 1757 skca.skc_type = sc->sk_type; 1758 skca.skc_rev = sc->sk_rev; 1759 (void)config_found(sc->sk_dev, &skca, mskcprint); 1760 1761 if (sc->sk_macs > 1) { 1762 skca.skc_port = SK_PORT_B; 1763 skca.skc_type = sc->sk_type; 1764 skca.skc_rev = sc->sk_rev; 1765 (void)config_found(sc->sk_dev, &skca, mskcprint); 1766 } 1767 1768 /* Turn on the 'driver is loaded' LED. */ 1769 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1770 1771 /* skc sysctl setup */ 1772 1773 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1774 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1775 SYSCTL_DESCR("mskc per-controller controls"), 1776 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1777 CTL_EOL)) != 0) { 1778 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1779 goto fail_6; 1780 } 1781 1782 sk_nodenum = node->sysctl_num; 1783 1784 /* interrupt moderation time in usecs */ 1785 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1786 CTLFLAG_READWRITE, 1787 CTLTYPE_INT, "int_mod", 1788 SYSCTL_DESCR("msk interrupt moderation timer"), 1789 msk_sysctl_handler, 0, (void *)sc, 1790 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1791 CTL_EOL)) != 0) { 1792 aprint_normal_dev(sc->sk_dev, 1793 "couldn't create int_mod sysctl node\n"); 1794 goto fail_6; 1795 } 1796 1797 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1798 aprint_error_dev(self, "couldn't establish power handler\n"); 1799 1800 return; 1801 1802 fail_6: 1803 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1804 fail_4: 1805 bus_dmamem_unmap(sc->sc_dmatag, kva, 1806 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1807 fail_3: 1808 bus_dmamem_free(sc->sc_dmatag, 1809 &sc->sk_status_seg, sc->sk_status_nseg); 1810 sc->sk_status_nseg = 0; 1811 fail_5: 1812 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1813 fail_2: 1814 pci_intr_disestablish(pc, sc->sk_intrhand); 1815 sc->sk_intrhand = NULL; 1816 fail_1: 1817 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1818 sc->sk_bsize = 0; 1819 } 1820 1821 static int 1822 mskc_detach(device_t self, int flags) 1823 { 1824 struct sk_softc *sc = device_private(self); 1825 int rv; 1826 1827 if (sc->sk_intrhand) { 1828 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1829 sc->sk_intrhand = NULL; 1830 } 1831 1832 if (sc->sk_pihp != NULL) { 1833 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1834 sc->sk_pihp = NULL; 1835 } 1836 1837 rv = config_detach_children(self, flags); 1838 if (rv != 0) 1839 return rv; 1840 1841 if (sc->sk_status_nseg > 0) { 1842 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1843 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1844 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1845 bus_dmamem_free(sc->sc_dmatag, 1846 &sc->sk_status_seg, sc->sk_status_nseg); 1847 } 1848 1849 if (sc->sk_bsize > 0) 1850 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1851 1852 return 0; 1853 } 1854 1855 static int 1856 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1857 { 1858 struct sk_softc *sc = sc_if->sk_softc; 1859 struct msk_tx_desc *f = NULL; 1860 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1861 uint32_t entries = 0; 1862 size_t i; 1863 bus_dmamap_t txmap; 1864 bus_addr_t addr; 1865 1866 DPRINTFN(2, ("msk_encap\n")); 1867 1868 txmap = sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap; 1869 1870 cur = frag = *txidx; 1871 1872 #ifdef MSK_DEBUG 1873 if (mskdebug >= 2) 1874 msk_dump_mbuf(m_head); 1875 #endif 1876 1877 /* 1878 * Start packing the mbufs in this chain into 1879 * the fragment pointers. Stop when we run out 1880 * of fragments or hit the end of the mbuf chain. 1881 */ 1882 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1883 BUS_DMA_NOWAIT)) { 1884 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1885 return ENOBUFS; 1886 } 1887 1888 /* Count how many tx descriptors needed. */ 1889 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1890 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1891 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1892 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1893 total++; 1894 } 1895 total++; 1896 } 1897 1898 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1899 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1900 bus_dmamap_unload(sc->sc_dmatag, txmap); 1901 return ENOBUFS; 1902 } 1903 1904 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1905 txmap->dm_nsegs, total)); 1906 1907 /* Sync the DMA map. */ 1908 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1909 BUS_DMASYNC_PREWRITE); 1910 1911 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1912 for (i = 0; i < txmap->dm_nsegs; i++) { 1913 addr = txmap->dm_segs[i].ds_addr; 1914 DPRINTFN(2, ("msk_encap: addr %llx\n", 1915 (unsigned long long)addr)); 1916 hiaddr = MSK_ADDR_HI(addr); 1917 1918 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1919 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1920 f->sk_addr = htole32(hiaddr); 1921 f->sk_len = 0; 1922 f->sk_ctl = 0; 1923 if (i == 0) 1924 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1925 else 1926 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1927 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1928 SK_INC(frag, MSK_TX_RING_CNT); 1929 entries++; 1930 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1931 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1932 } 1933 1934 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1935 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1936 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1937 f->sk_ctl = 0; 1938 if (i == 0) { 1939 if (hiaddr != old_hiaddr) 1940 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1941 else 1942 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1943 } else 1944 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1945 cur = frag; 1946 SK_INC(frag, MSK_TX_RING_CNT); 1947 entries++; 1948 } 1949 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1950 1951 sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap = 1952 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap; 1953 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1954 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap = txmap; 1955 1956 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1957 1958 /* Sync descriptors before handing to chip */ 1959 MSK_CDTXSYNC(sc_if, *txidx, entries, 1960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1961 1962 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1963 1964 /* Sync first descriptor to hand it off */ 1965 MSK_CDTXSYNC(sc_if, *txidx, 1, 1966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1967 1968 sc_if->sk_cdata.sk_tx_cnt += entries; 1969 1970 #ifdef MSK_DEBUG 1971 if (mskdebug >= 2) { 1972 struct msk_tx_desc *le; 1973 uint32_t idx; 1974 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1975 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1976 msk_dump_txdesc(le, idx); 1977 } 1978 } 1979 #endif 1980 1981 *txidx = frag; 1982 1983 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1984 1985 return 0; 1986 } 1987 1988 static void 1989 msk_start(struct ifnet *ifp) 1990 { 1991 struct sk_if_softc *sc_if = ifp->if_softc; 1992 struct mbuf *m_head = NULL; 1993 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1994 int pkts = 0; 1995 1996 DPRINTFN(2, ("msk_start\n")); 1997 1998 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1999 IFQ_POLL(&ifp->if_snd, m_head); 2000 if (m_head == NULL) 2001 break; 2002 2003 /* 2004 * Pack the data into the transmit ring. If we 2005 * don't have room, set the OACTIVE flag and wait 2006 * for the NIC to drain the ring. 2007 */ 2008 if (msk_encap(sc_if, m_head, &idx)) { 2009 ifp->if_flags |= IFF_OACTIVE; 2010 break; 2011 } 2012 2013 /* now we are committed to transmit the packet */ 2014 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2015 pkts++; 2016 2017 /* 2018 * If there's a BPF listener, bounce a copy of this frame 2019 * to him. 2020 */ 2021 bpf_mtap(ifp, m_head, BPF_D_OUT); 2022 } 2023 if (pkts == 0) 2024 return; 2025 2026 /* Transmit */ 2027 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2028 sc_if->sk_cdata.sk_tx_prod = idx; 2029 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 2030 2031 /* Set a timeout in case the chip goes out to lunch. */ 2032 ifp->if_timer = 5; 2033 } 2034 } 2035 2036 static void 2037 msk_watchdog(struct ifnet *ifp) 2038 { 2039 struct sk_if_softc *sc_if = ifp->if_softc; 2040 2041 /* 2042 * Reclaim first as there is a possibility of losing Tx completion 2043 * interrupts. 2044 */ 2045 msk_txeof(sc_if); 2046 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2047 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2048 2049 if_statinc(ifp, if_oerrors); 2050 2051 /* XXX Resets both ports; we shouldn't do that. */ 2052 mskc_reset(sc_if->sk_softc); 2053 msk_reset(sc_if); 2054 msk_init(ifp); 2055 } 2056 } 2057 2058 static bool 2059 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2060 { 2061 struct sk_softc *sc = device_private(dv); 2062 2063 DPRINTFN(2, ("mskc_suspend\n")); 2064 2065 /* Turn off the 'driver is loaded' LED. */ 2066 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2067 2068 return true; 2069 } 2070 2071 static bool 2072 mskc_resume(device_t dv, const pmf_qual_t *qual) 2073 { 2074 struct sk_softc *sc = device_private(dv); 2075 2076 DPRINTFN(2, ("mskc_resume\n")); 2077 2078 mskc_reset(sc); 2079 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2080 2081 return true; 2082 } 2083 2084 static __inline int 2085 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2086 { 2087 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2088 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2089 YU_RXSTAT_JABBER)) != 0 || 2090 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2091 YU_RXSTAT_BYTES(stat) != len) 2092 return 0; 2093 2094 return 1; 2095 } 2096 2097 static void 2098 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2099 { 2100 struct sk_softc *sc = sc_if->sk_softc; 2101 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2102 struct mbuf *m; 2103 unsigned cur, prod, tail, total_len = len; 2104 bus_dmamap_t dmamap; 2105 2106 cur = sc_if->sk_cdata.sk_rx_cons; 2107 prod = sc_if->sk_cdata.sk_rx_prod; 2108 2109 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2110 sc_if->sk_cdata.sk_rx_cnt)); 2111 2112 while (prod != cur) { 2113 MSK_CDRXSYNC(sc_if, cur, 2114 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2115 2116 tail = cur; 2117 SK_INC(cur, MSK_RX_RING_CNT); 2118 2119 sc_if->sk_cdata.sk_rx_cnt--; 2120 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2121 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2122 if (m != NULL) 2123 break; /* found it */ 2124 } 2125 sc_if->sk_cdata.sk_rx_cons = cur; 2126 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2127 sc_if->sk_cdata.sk_rx_cnt, m)); 2128 2129 if (m == NULL) 2130 return; 2131 2132 dmamap = sc_if->sk_cdata.sk_rx_chain[tail].sk_dmamap; 2133 2134 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2135 uimin(dmamap->dm_mapsize, total_len), BUS_DMASYNC_POSTREAD); 2136 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2137 2138 if (total_len < SK_MIN_FRAMELEN || 2139 total_len > ETHER_MAX_LEN_JUMBO || 2140 msk_rxvalid(sc, rxstat, total_len) == 0) { 2141 if_statinc(ifp, if_ierrors); 2142 m_freem(m); 2143 return; 2144 } 2145 2146 m_set_rcvif(m, ifp); 2147 m->m_pkthdr.len = m->m_len = total_len; 2148 2149 /* pass it on. */ 2150 if_percpuq_enqueue(ifp->if_percpuq, m); 2151 } 2152 2153 static void 2154 msk_txeof(struct sk_if_softc *sc_if) 2155 { 2156 struct sk_softc *sc = sc_if->sk_softc; 2157 struct msk_tx_desc *cur_tx; 2158 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2159 uint32_t idx, reg, sk_ctl; 2160 bus_dmamap_t dmamap; 2161 2162 DPRINTFN(2, ("msk_txeof\n")); 2163 2164 if (sc_if->sk_port == SK_PORT_A) 2165 reg = SK_STAT_BMU_TXA1_RIDX; 2166 else 2167 reg = SK_STAT_BMU_TXA2_RIDX; 2168 2169 /* 2170 * Go through our tx ring and free mbufs for those 2171 * frames that have been sent. 2172 */ 2173 idx = sc_if->sk_cdata.sk_tx_cons; 2174 while (idx != sk_win_read_2(sc, reg)) { 2175 MSK_CDTXSYNC(sc_if, idx, 1, 2176 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2177 2178 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2179 sk_ctl = cur_tx->sk_ctl; 2180 #ifdef MSK_DEBUG 2181 if (mskdebug >= 2) 2182 msk_dump_txdesc(cur_tx, idx); 2183 #endif 2184 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2185 if_statinc(ifp, if_opackets); 2186 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2187 dmamap = sc_if->sk_cdata.sk_tx_chain[idx].sk_dmamap; 2188 2189 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2190 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2191 2192 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2193 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2194 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2195 } 2196 sc_if->sk_cdata.sk_tx_cnt--; 2197 SK_INC(idx, MSK_TX_RING_CNT); 2198 } 2199 if (idx == sc_if->sk_cdata.sk_tx_cons) 2200 return; 2201 2202 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2203 2204 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2205 ifp->if_flags &= ~IFF_OACTIVE; 2206 2207 sc_if->sk_cdata.sk_tx_cons = idx; 2208 } 2209 2210 static void 2211 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2212 { 2213 /* Make sure to not completely wrap around */ 2214 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2215 if (msk_newbuf(sc_if) == ENOBUFS) { 2216 goto schedretry; 2217 } 2218 } 2219 2220 return; 2221 2222 schedretry: 2223 /* Try later */ 2224 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2225 } 2226 2227 static void 2228 msk_fill_rx_tick(void *xsc_if) 2229 { 2230 struct sk_if_softc *sc_if = xsc_if; 2231 int s, rx_prod; 2232 2233 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2234 2235 s = splnet(); 2236 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2237 msk_fill_rx_ring(sc_if); 2238 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2239 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2240 sc_if->sk_cdata.sk_rx_prod); 2241 } 2242 splx(s); 2243 } 2244 2245 static void 2246 msk_tick(void *xsc_if) 2247 { 2248 struct sk_if_softc *sc_if = xsc_if; 2249 struct mii_data *mii = &sc_if->sk_mii; 2250 int s; 2251 2252 s = splnet(); 2253 mii_tick(mii); 2254 splx(s); 2255 2256 callout_schedule(&sc_if->sk_tick_ch, hz); 2257 } 2258 2259 static void 2260 msk_intr_yukon(struct sk_if_softc *sc_if) 2261 { 2262 uint8_t status; 2263 2264 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2265 /* RX overrun */ 2266 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2267 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2268 SK_RFCTL_RX_FIFO_OVER); 2269 } 2270 /* TX underrun */ 2271 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2272 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2273 SK_TFCTL_TX_FIFO_UNDER); 2274 } 2275 2276 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2277 } 2278 2279 static int 2280 msk_intr(void *xsc) 2281 { 2282 struct sk_softc *sc = xsc; 2283 struct sk_if_softc *sc_if; 2284 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2285 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2286 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2287 int claimed = 0; 2288 uint32_t status; 2289 struct msk_status_desc *cur_st; 2290 2291 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2292 if (status == 0xffffffff) 2293 return 0; 2294 if (status == 0) { 2295 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2296 return 0; 2297 } 2298 2299 status = CSR_READ_4(sc, SK_ISR); 2300 2301 if (sc_if0 != NULL) 2302 ifp0 = &sc_if0->sk_ethercom.ec_if; 2303 if (sc_if1 != NULL) 2304 ifp1 = &sc_if1->sk_ethercom.ec_if; 2305 2306 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2307 (ifp0->if_flags & IFF_RUNNING)) { 2308 msk_intr_yukon(sc_if0); 2309 } 2310 2311 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2312 (ifp1->if_flags & IFF_RUNNING)) { 2313 msk_intr_yukon(sc_if1); 2314 } 2315 2316 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2317 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2318 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2319 2320 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2321 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2322 switch (cur_st->sk_opcode) { 2323 case SK_Y2_STOPC_RXSTAT: 2324 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2325 if (sc_if) { 2326 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2327 letoh32(cur_st->sk_status)); 2328 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2329 msk_fill_rx_tick(sc_if); 2330 } 2331 break; 2332 case SK_Y2_STOPC_TXSTAT: 2333 if (sc_if0) 2334 msk_txeof(sc_if0); 2335 if (sc_if1) 2336 msk_txeof(sc_if1); 2337 break; 2338 default: 2339 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2340 break; 2341 } 2342 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2343 2344 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2345 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2346 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2347 } 2348 2349 if (status & SK_Y2_IMR_BMU) { 2350 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2351 claimed = 1; 2352 } 2353 2354 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2355 2356 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2357 if_schedule_deferred_start(ifp0); 2358 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2359 if_schedule_deferred_start(ifp1); 2360 2361 KASSERT(sc->rnd_attached > 0); 2362 rnd_add_uint32(&sc->rnd_source, status); 2363 2364 if (sc->sk_int_mod_pending) 2365 msk_update_int_mod(sc, 1); 2366 2367 return claimed; 2368 } 2369 2370 static void 2371 msk_init_yukon(struct sk_if_softc *sc_if) 2372 { 2373 uint32_t v; 2374 uint16_t reg; 2375 struct sk_softc *sc; 2376 int i; 2377 2378 sc = sc_if->sk_softc; 2379 2380 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2381 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2382 2383 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2384 2385 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2386 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2387 2388 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2389 2390 /* unused read of the interrupt source register */ 2391 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2392 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2393 2394 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2395 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2396 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2397 2398 /* MIB Counter Clear Mode set */ 2399 reg |= YU_PAR_MIB_CLR; 2400 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2401 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2402 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2403 2404 /* MIB Counter Clear Mode clear */ 2405 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2406 reg &= ~YU_PAR_MIB_CLR; 2407 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2408 2409 /* receive control reg */ 2410 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2411 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2412 2413 /* transmit control register */ 2414 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2415 2416 /* transmit flow control register */ 2417 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2418 2419 /* transmit parameter register */ 2420 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2421 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2422 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2423 2424 /* serial mode register */ 2425 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2426 reg = YU_SMR_DATA_BLIND(0x1c) | 2427 YU_SMR_MFL_VLAN | 2428 YU_SMR_IPG_DATA(0x1e); 2429 2430 if (sc->sk_type != SK_YUKON_FE && 2431 sc->sk_type != SK_YUKON_FE_P) 2432 reg |= YU_SMR_MFL_JUMBO; 2433 2434 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2435 2436 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2437 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2438 /* msk_attach calls me before ether_ifattach so check null */ 2439 if (ifp != NULL && ifp->if_sadl != NULL) 2440 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2441 sizeof(sc_if->sk_enaddr)); 2442 /* Setup Yukon's address */ 2443 for (i = 0; i < 3; i++) { 2444 /* Write Source Address 1 (unicast filter) */ 2445 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2446 sc_if->sk_enaddr[i * 2] | 2447 sc_if->sk_enaddr[i * 2 + 1] << 8); 2448 } 2449 2450 for (i = 0; i < 3; i++) { 2451 reg = sk_win_read_2(sc_if->sk_softc, 2452 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2453 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2454 } 2455 2456 /* Set promiscuous mode */ 2457 msk_setpromisc(sc_if); 2458 2459 /* Set multicast filter */ 2460 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2461 msk_setmulti(sc_if); 2462 2463 /* enable interrupt mask for counter overflows */ 2464 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2465 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2466 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2467 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2468 2469 /* Configure RX MAC FIFO Flush Mask */ 2470 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2471 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2472 YU_RXSTAT_JABBER; 2473 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2474 2475 /* Configure RX MAC FIFO */ 2476 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2477 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2478 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2479 v |= SK_RFCTL_RX_OVER_ON; 2480 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2481 2482 if ((sc->sk_type == SK_YUKON_FE_P) && 2483 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2484 v = 0x178; /* Magic value */ 2485 else { 2486 /* Increase flush threshold to 64 bytes */ 2487 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2488 } 2489 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2490 2491 /* Configure TX MAC FIFO */ 2492 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2493 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2494 2495 if ((sc->sk_type == SK_YUKON_FE_P) && 2496 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2497 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2498 v &= ~SK_TXEND_WM_ON; 2499 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2500 } 2501 2502 #if 1 2503 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2504 #endif 2505 DPRINTFN(6, ("msk_init_yukon: end\n")); 2506 } 2507 2508 /* 2509 * Note that to properly initialize any part of the GEnesis chip, 2510 * you first have to take it out of reset mode. 2511 */ 2512 static int 2513 msk_init(struct ifnet *ifp) 2514 { 2515 struct sk_if_softc *sc_if = ifp->if_softc; 2516 struct sk_softc *sc = sc_if->sk_softc; 2517 int rc = 0, s; 2518 uint32_t imr, imtimer_ticks; 2519 2520 2521 DPRINTFN(2, ("msk_init\n")); 2522 2523 s = splnet(); 2524 2525 /* Cancel pending I/O and free all RX/TX buffers. */ 2526 msk_stop(ifp, 1); 2527 2528 /* Configure I2C registers */ 2529 2530 /* Configure XMAC(s) */ 2531 msk_init_yukon(sc_if); 2532 if ((rc = ether_mediachange(ifp)) != 0) 2533 goto out; 2534 2535 /* Configure transmit arbiter(s) */ 2536 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2537 #if 0 2538 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2539 #endif 2540 2541 if (sc->sk_ramsize) { 2542 /* Configure RAMbuffers */ 2543 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2544 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2545 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2546 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2547 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2548 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2549 2550 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2551 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2552 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2553 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2554 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2555 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2556 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2557 } 2558 2559 /* Configure BMUs */ 2560 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2561 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2562 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2563 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2564 2565 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2566 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2567 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2568 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2569 2570 /* Make sure the sync transmit queue is disabled. */ 2571 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2572 2573 /* Init descriptors */ 2574 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2575 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2576 "memory for rx buffers\n"); 2577 msk_stop(ifp, 1); 2578 splx(s); 2579 return ENOBUFS; 2580 } 2581 2582 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2583 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2584 "memory for tx buffers\n"); 2585 msk_stop(ifp, 1); 2586 splx(s); 2587 return ENOBUFS; 2588 } 2589 2590 /* Set interrupt moderation if changed via sysctl. */ 2591 switch (sc->sk_type) { 2592 case SK_YUKON_EC: 2593 case SK_YUKON_EC_U: 2594 case SK_YUKON_EX: 2595 case SK_YUKON_SUPR: 2596 case SK_YUKON_ULTRA2: 2597 case SK_YUKON_OPTIMA: 2598 case SK_YUKON_PRM: 2599 case SK_YUKON_OPTIMA2: 2600 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2601 break; 2602 case SK_YUKON_FE: 2603 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2604 break; 2605 case SK_YUKON_FE_P: 2606 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2607 break; 2608 case SK_YUKON_XL: 2609 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2610 break; 2611 default: 2612 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2613 } 2614 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2615 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2616 sk_win_write_4(sc, SK_IMTIMERINIT, 2617 SK_IM_USECS(sc->sk_int_mod)); 2618 aprint_verbose_dev(sc->sk_dev, 2619 "interrupt moderation is %d us\n", sc->sk_int_mod); 2620 } 2621 2622 /* Initialize prefetch engine. */ 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2624 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2625 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2626 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2627 MSK_RX_RING_ADDR(sc_if, 0)); 2628 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2629 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2630 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2631 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2632 2633 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2634 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2635 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2636 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2637 MSK_TX_RING_ADDR(sc_if, 0)); 2638 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2639 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2640 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2641 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2642 2643 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2644 sc_if->sk_cdata.sk_rx_prod); 2645 2646 2647 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2648 /* Disable flushing of non-ASF packets. */ 2649 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2650 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2651 } 2652 2653 /* Configure interrupt handling */ 2654 if (sc_if->sk_port == SK_PORT_A) 2655 sc->sk_intrmask |= SK_Y2_INTRS1; 2656 else 2657 sc->sk_intrmask |= SK_Y2_INTRS2; 2658 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2659 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2660 2661 ifp->if_flags |= IFF_RUNNING; 2662 ifp->if_flags &= ~IFF_OACTIVE; 2663 2664 callout_schedule(&sc_if->sk_tick_ch, hz); 2665 2666 out: 2667 splx(s); 2668 return rc; 2669 } 2670 2671 /* 2672 * Note: the logic of second parameter is inverted compared to OpenBSD 2673 * code, since this code uses the function as if_stop hook too. 2674 */ 2675 static void 2676 msk_stop(struct ifnet *ifp, int disable) 2677 { 2678 struct sk_if_softc *sc_if = ifp->if_softc; 2679 struct sk_softc *sc = sc_if->sk_softc; 2680 bus_dmamap_t dmamap; 2681 int i; 2682 2683 DPRINTFN(2, ("msk_stop\n")); 2684 2685 callout_stop(&sc_if->sk_tick_ch); 2686 callout_stop(&sc_if->sk_tick_rx); 2687 2688 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2689 2690 /* Stop transfer of Tx descriptors */ 2691 2692 /* Stop transfer of Rx descriptors */ 2693 2694 if (disable) { 2695 /* Turn off various components of this interface. */ 2696 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2697 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2698 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2699 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2700 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2701 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2702 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2703 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2704 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2705 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2706 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2707 2708 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2709 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2710 2711 /* Disable interrupts */ 2712 if (sc_if->sk_port == SK_PORT_A) 2713 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2714 else 2715 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2716 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2717 } 2718 2719 /* Free RX and TX mbufs still in the queues. */ 2720 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2721 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2722 dmamap = sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap; 2723 2724 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2725 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2726 2727 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2728 2729 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2730 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2731 } 2732 } 2733 2734 sc_if->sk_cdata.sk_rx_prod = 0; 2735 sc_if->sk_cdata.sk_rx_cons = 0; 2736 sc_if->sk_cdata.sk_rx_cnt = 0; 2737 2738 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2739 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2740 dmamap = sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap; 2741 2742 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2743 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2744 2745 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2746 2747 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2748 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2749 } 2750 } 2751 } 2752 2753 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2754 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2755 2756 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2757 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2758 2759 #ifdef MSK_DEBUG 2760 static void 2761 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2762 { 2763 #define DESC_PRINT(X) \ 2764 if (X) \ 2765 printf("txdesc[%d]." #X "=%#x\n", \ 2766 idx, X); 2767 2768 DESC_PRINT(letoh32(le->sk_addr)); 2769 DESC_PRINT(letoh16(le->sk_len)); 2770 DESC_PRINT(le->sk_ctl); 2771 DESC_PRINT(le->sk_opcode); 2772 #undef DESC_PRINT 2773 } 2774 2775 static void 2776 msk_dump_bytes(const char *data, int len) 2777 { 2778 int c, i, j; 2779 2780 for (i = 0; i < len; i += 16) { 2781 printf("%08x ", i); 2782 c = len - i; 2783 if (c > 16) c = 16; 2784 2785 for (j = 0; j < c; j++) { 2786 printf("%02x ", data[i + j] & 0xff); 2787 if ((j & 0xf) == 7 && j > 0) 2788 printf(" "); 2789 } 2790 2791 for (; j < 16; j++) 2792 printf(" "); 2793 printf(" "); 2794 2795 for (j = 0; j < c; j++) { 2796 int ch = data[i + j] & 0xff; 2797 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2798 } 2799 2800 printf("\n"); 2801 2802 if (c < 16) 2803 break; 2804 } 2805 } 2806 2807 static void 2808 msk_dump_mbuf(struct mbuf *m) 2809 { 2810 int count = m->m_pkthdr.len; 2811 2812 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2813 2814 while (count > 0 && m) { 2815 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2816 m, m->m_data, m->m_len); 2817 if (mskdebug >= 4) 2818 msk_dump_bytes(mtod(m, char *), m->m_len); 2819 2820 count -= m->m_len; 2821 m = m->m_next; 2822 } 2823 } 2824 #endif 2825 2826 static int 2827 msk_sysctl_handler(SYSCTLFN_ARGS) 2828 { 2829 int error, t; 2830 struct sysctlnode node; 2831 struct sk_softc *sc; 2832 2833 node = *rnode; 2834 sc = node.sysctl_data; 2835 t = sc->sk_int_mod; 2836 node.sysctl_data = &t; 2837 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2838 if (error || newp == NULL) 2839 return error; 2840 2841 if (t < SK_IM_MIN || t > SK_IM_MAX) 2842 return EINVAL; 2843 2844 /* update the softc with sysctl-changed value, and mark 2845 for hardware update */ 2846 sc->sk_int_mod = t; 2847 sc->sk_int_mod_pending = 1; 2848 return 0; 2849 } 2850 2851 /* 2852 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2853 * set up in mskc_attach() 2854 */ 2855 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2856 { 2857 int rc; 2858 const struct sysctlnode *node; 2859 2860 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2861 0, CTLTYPE_NODE, "msk", 2862 SYSCTL_DESCR("msk interface controls"), 2863 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2864 goto err; 2865 } 2866 2867 msk_root_num = node->sysctl_num; 2868 return; 2869 2870 err: 2871 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2872 } 2873
Indexes created Sun Sep 21 20:09:37 GMT 2025