if_msk.c revision 1.108
1 /* $NetBSD: if_msk.c,v 1.108 2020/04/30 14:04:54 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.108 2020/04/30 14:04:54 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 le16toh 72 #define letoh32 le32toh 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/pci/if_skreg.h> 92 #include <dev/pci/if_mskvar.h> 93 94 static int mskc_probe(device_t, cfdata_t, void *); 95 static void mskc_attach(device_t, device_t, void *); 96 static int mskc_detach(device_t, int); 97 static void mskc_reset(struct sk_softc *); 98 static bool mskc_suspend(device_t, const pmf_qual_t *); 99 static bool mskc_resume(device_t, const pmf_qual_t *); 100 static int msk_probe(device_t, cfdata_t, void *); 101 static void msk_attach(device_t, device_t, void *); 102 static int msk_detach(device_t, int); 103 static void msk_reset(struct sk_if_softc *); 104 static int mskcprint(void *, const char *); 105 static int msk_intr(void *); 106 static void msk_intr_yukon(struct sk_if_softc *); 107 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 108 static void msk_txeof(struct sk_if_softc *); 109 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 110 static void msk_start(struct ifnet *); 111 static int msk_ioctl(struct ifnet *, u_long, void *); 112 static int msk_init(struct ifnet *); 113 static void msk_init_yukon(struct sk_if_softc *); 114 static void msk_stop(struct ifnet *, int); 115 static void msk_watchdog(struct ifnet *); 116 static int msk_newbuf(struct sk_if_softc *); 117 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 118 static void *msk_jalloc(struct sk_if_softc *); 119 static void msk_jfree(struct mbuf *, void *, size_t, void *); 120 static int msk_init_rx_ring(struct sk_if_softc *); 121 static int msk_init_tx_ring(struct sk_if_softc *); 122 static void msk_fill_rx_ring(struct sk_if_softc *); 123 124 static void msk_update_int_mod(struct sk_softc *, int); 125 126 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 127 static int msk_miibus_writereg(device_t, int, int, uint16_t); 128 static void msk_miibus_statchg(struct ifnet *); 129 130 static void msk_setmulti(struct sk_if_softc *); 131 static void msk_setpromisc(struct sk_if_softc *); 132 static void msk_tick(void *); 133 static void msk_fill_rx_tick(void *); 134 135 /* #define MSK_DEBUG 1 */ 136 #ifdef MSK_DEBUG 137 #define DPRINTF(x) if (mskdebug) printf x 138 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 139 int mskdebug = MSK_DEBUG; 140 141 static void msk_dump_txdesc(struct msk_tx_desc *, int); 142 static void msk_dump_mbuf(struct mbuf *); 143 static void msk_dump_bytes(const char *, int); 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 static int msk_sysctl_handler(SYSCTLFN_PROTO); 150 static int msk_root_num; 151 152 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 153 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 199 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 201 { 0, 0 } 202 }; 203 204 static inline uint32_t 205 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 206 { 207 return CSR_READ_4(sc, reg); 208 } 209 210 static inline uint16_t 211 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 212 { 213 return CSR_READ_2(sc, reg); 214 } 215 216 static inline uint8_t 217 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 218 { 219 return CSR_READ_1(sc, reg); 220 } 221 222 static inline void 223 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 224 { 225 CSR_WRITE_4(sc, reg, x); 226 } 227 228 static inline void 229 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 230 { 231 CSR_WRITE_2(sc, reg, x); 232 } 233 234 static inline void 235 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 236 { 237 CSR_WRITE_1(sc, reg, x); 238 } 239 240 static int 241 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 242 { 243 struct sk_if_softc *sc_if = device_private(dev); 244 uint16_t data; 245 int i; 246 247 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 248 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 249 250 for (i = 0; i < SK_TIMEOUT; i++) { 251 DELAY(1); 252 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 253 if (data & YU_SMICR_READ_VALID) 254 break; 255 } 256 257 if (i == SK_TIMEOUT) { 258 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 259 return ETIMEDOUT; 260 } 261 262 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 263 264 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 265 266 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 267 phy, reg, *val)); 268 269 return 0; 270 } 271 272 static int 273 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 274 { 275 struct sk_if_softc *sc_if = device_private(dev); 276 int i; 277 278 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 279 phy, reg, val)); 280 281 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 282 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 283 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 284 285 for (i = 0; i < SK_TIMEOUT; i++) { 286 DELAY(1); 287 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 288 break; 289 } 290 291 if (i == SK_TIMEOUT) { 292 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 293 return ETIMEDOUT; 294 } 295 296 return 0; 297 } 298 299 static void 300 msk_miibus_statchg(struct ifnet *ifp) 301 { 302 struct sk_if_softc *sc_if = ifp->if_softc; 303 struct mii_data *mii = &sc_if->sk_mii; 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 int gpcr; 306 307 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 308 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 309 310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 311 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 312 /* Set speed. */ 313 gpcr |= YU_GPCR_SPEED_DIS; 314 switch (IFM_SUBTYPE(mii->mii_media_active)) { 315 case IFM_1000_SX: 316 case IFM_1000_LX: 317 case IFM_1000_CX: 318 case IFM_1000_T: 319 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 320 break; 321 case IFM_100_TX: 322 gpcr |= YU_GPCR_SPEED; 323 break; 324 } 325 326 /* Set duplex. */ 327 gpcr |= YU_GPCR_DPLX_DIS; 328 if ((mii->mii_media_active & IFM_FDX) != 0) 329 gpcr |= YU_GPCR_DUPLEX; 330 331 /* Disable flow control. */ 332 gpcr |= YU_GPCR_FCTL_DIS; 333 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 334 } 335 336 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 337 338 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 339 SK_YU_READ_2(sc_if, YUKON_GPCR))); 340 } 341 342 static void 343 msk_setmulti(struct sk_if_softc *sc_if) 344 { 345 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 346 uint32_t hashes[2] = { 0, 0 }; 347 int h; 348 struct ethercom *ec = &sc_if->sk_ethercom; 349 struct ether_multi *enm; 350 struct ether_multistep step; 351 uint16_t reg; 352 353 /* First, zot all the existing filters. */ 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 358 359 360 /* Now program new ones. */ 361 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 362 reg |= YU_RCR_UFLEN; 363 allmulti: 364 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 365 if ((ifp->if_flags & IFF_PROMISC) != 0) 366 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 367 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 368 hashes[0] = 0xFFFFFFFF; 369 hashes[1] = 0xFFFFFFFF; 370 } 371 } else { 372 /* First find the tail of the list. */ 373 ETHER_LOCK(ec); 374 ETHER_FIRST_MULTI(step, ec, enm); 375 while (enm != NULL) { 376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 377 ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 ETHER_UNLOCK(ec); 380 goto allmulti; 381 } 382 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 383 ((1 << SK_HASH_BITS) - 1); 384 if (h < 32) 385 hashes[0] |= (1 << h); 386 else 387 hashes[1] |= (1 << (h - 32)); 388 389 ETHER_NEXT_MULTI(step, enm); 390 } 391 ETHER_UNLOCK(ec); 392 reg |= YU_RCR_MUFLEN; 393 } 394 395 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 400 } 401 402 static void 403 msk_setpromisc(struct sk_if_softc *sc_if) 404 { 405 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 406 407 if (ifp->if_flags & IFF_PROMISC) 408 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 409 YU_RCR_UFLEN | YU_RCR_MUFLEN); 410 else 411 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 412 YU_RCR_UFLEN | YU_RCR_MUFLEN); 413 } 414 415 static int 416 msk_init_rx_ring(struct sk_if_softc *sc_if) 417 { 418 struct msk_chain_data *cd = &sc_if->sk_cdata; 419 struct msk_ring_data *rd = sc_if->sk_rdata; 420 struct msk_rx_desc *r; 421 422 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 423 424 sc_if->sk_cdata.sk_rx_prod = 0; 425 sc_if->sk_cdata.sk_rx_cons = 0; 426 sc_if->sk_cdata.sk_rx_cnt = 0; 427 sc_if->sk_cdata.sk_rx_hiaddr = 0; 428 429 /* Mark the first ring element to initialize the high address. */ 430 sc_if->sk_cdata.sk_rx_hiaddr = 0; 431 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 432 r->sk_addr = htole32(cd->sk_rx_hiaddr); 433 r->sk_len = 0; 434 r->sk_ctl = 0; 435 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 436 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 438 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 439 sc_if->sk_cdata.sk_rx_cnt++; 440 441 msk_fill_rx_ring(sc_if); 442 return 0; 443 } 444 445 static int 446 msk_init_tx_ring(struct sk_if_softc *sc_if) 447 { 448 struct msk_chain_data *cd = &sc_if->sk_cdata; 449 struct msk_ring_data *rd = sc_if->sk_rdata; 450 struct msk_tx_desc *t; 451 452 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 453 454 sc_if->sk_cdata.sk_tx_prod = 0; 455 sc_if->sk_cdata.sk_tx_cons = 0; 456 sc_if->sk_cdata.sk_tx_cnt = 0; 457 sc_if->sk_cdata.sk_tx_hiaddr = 0; 458 459 /* Mark the first ring element to initialize the high address. */ 460 sc_if->sk_cdata.sk_tx_hiaddr = 0; 461 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 462 t->sk_addr = htole32(cd->sk_tx_hiaddr); 463 t->sk_len = 0; 464 t->sk_ctl = 0; 465 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 466 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 468 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 469 sc_if->sk_cdata.sk_tx_cnt++; 470 471 return 0; 472 } 473 474 static int 475 msk_newbuf(struct sk_if_softc *sc_if) 476 { 477 struct sk_softc *sc = sc_if->sk_softc; 478 struct mbuf *m_new = NULL; 479 struct sk_chain *c; 480 struct msk_rx_desc *r; 481 void *buf = NULL; 482 bus_addr_t addr; 483 bus_dmamap_t rxmap; 484 size_t i; 485 uint32_t rxidx, frag, cur, hiaddr, old_hiaddr, total; 486 uint32_t entries = 0; 487 488 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 489 if (m_new == NULL) 490 return ENOBUFS; 491 492 /* Allocate the jumbo buffer */ 493 buf = msk_jalloc(sc_if); 494 if (buf == NULL) { 495 m_freem(m_new); 496 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 497 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 498 return ENOBUFS; 499 } 500 501 /* Attach the buffer to the mbuf */ 502 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 503 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 504 505 m_adj(m_new, ETHER_ALIGN); 506 507 rxidx = frag = cur = sc_if->sk_cdata.sk_rx_prod; 508 rxmap = sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap; 509 510 if (bus_dmamap_load_mbuf(sc->sc_dmatag, rxmap, m_new, BUS_DMA_NOWAIT)) { 511 DPRINTFN(2, ("msk_newbuf: dmamap_load failed\n")); 512 m_freem(m_new); 513 return ENOBUFS; 514 } 515 516 /* Count how many rx descriptors needed. */ 517 hiaddr = sc_if->sk_cdata.sk_rx_hiaddr; 518 for (total = i = 0; i < rxmap->dm_nsegs; i++) { 519 if (hiaddr != MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr)) { 520 hiaddr = MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr); 521 total++; 522 } 523 total++; 524 } 525 526 if (total > MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt - 1) { 527 DPRINTFN(2, ("msk_newbuf: too few descriptors free\n")); 528 bus_dmamap_unload(sc->sc_dmatag, rxmap); 529 m_freem(m_new); 530 return ENOBUFS; 531 } 532 533 DPRINTFN(2, ("msk_newbuf: dm_nsegs=%d total desc=%u\n", 534 rxmap->dm_nsegs, total)); 535 536 /* Sync the DMA map. */ 537 bus_dmamap_sync(sc->sc_dmatag, rxmap, 0, rxmap->dm_mapsize, 538 BUS_DMASYNC_PREREAD); 539 540 old_hiaddr = sc_if->sk_cdata.sk_rx_hiaddr; 541 for (i = 0; i < rxmap->dm_nsegs; i++) { 542 addr = rxmap->dm_segs[i].ds_addr; 543 DPRINTFN(2, ("msk_newbuf: addr %llx\n", 544 (unsigned long long)addr)); 545 hiaddr = MSK_ADDR_HI(addr); 546 547 if (sc_if->sk_cdata.sk_rx_hiaddr != hiaddr) { 548 c = &sc_if->sk_cdata.sk_rx_chain[frag]; 549 c->sk_mbuf = NULL; 550 r = &sc_if->sk_rdata->sk_rx_ring[frag]; 551 r->sk_addr = htole32(hiaddr); 552 r->sk_len = 0; 553 r->sk_ctl = 0; 554 if (i == 0) 555 r->sk_opcode = SK_Y2_BMUOPC_ADDR64; 556 else 557 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | 558 SK_Y2_RXOPC_OWN; 559 sc_if->sk_cdata.sk_rx_hiaddr = hiaddr; 560 MSK_CDRXSYNC(sc_if, frag, 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 SK_INC(frag, MSK_RX_RING_CNT); 563 entries++; 564 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 565 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 566 } 567 568 c = &sc_if->sk_cdata.sk_rx_chain[frag]; 569 r = &sc_if->sk_rdata->sk_rx_ring[frag]; 570 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 571 r->sk_len = htole16(rxmap->dm_segs[i].ds_len); 572 r->sk_ctl = 0; 573 if (i == 0) { 574 if (hiaddr != old_hiaddr) 575 r->sk_opcode = SK_Y2_RXOPC_PACKET | 576 SK_Y2_RXOPC_OWN; 577 else 578 r->sk_opcode = SK_Y2_RXOPC_PACKET; 579 } else 580 r->sk_opcode = SK_Y2_RXOPC_BUFFER | SK_Y2_RXOPC_OWN; 581 MSK_CDRXSYNC(sc_if, frag, 582 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 583 cur = frag; 584 SK_INC(frag, MSK_RX_RING_CNT); 585 entries++; 586 } 587 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 588 589 sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap = 590 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap; 591 sc_if->sk_cdata.sk_rx_chain[cur].sk_mbuf = m_new; 592 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap = rxmap; 593 594 sc_if->sk_rdata->sk_rx_ring[rxidx].sk_opcode |= SK_Y2_RXOPC_OWN; 595 MSK_CDRXSYNC(sc_if, rxidx, 596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 597 598 sc_if->sk_cdata.sk_rx_cnt += entries; 599 sc_if->sk_cdata.sk_rx_prod = frag; 600 601 return 0; 602 } 603 604 /* 605 * Memory management for jumbo frames. 606 */ 607 608 static int 609 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 610 { 611 struct sk_softc *sc = sc_if->sk_softc; 612 char *ptr, *kva; 613 int i, state, error; 614 struct sk_jpool_entry *entry; 615 616 state = error = 0; 617 618 /* Grab a big chunk o' storage. */ 619 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 620 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 621 BUS_DMA_NOWAIT)) { 622 aprint_error(": can't alloc rx buffers"); 623 return ENOBUFS; 624 } 625 626 state = 1; 627 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 628 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 629 BUS_DMA_NOWAIT)) { 630 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 631 error = ENOBUFS; 632 goto out; 633 } 634 635 state = 2; 636 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 637 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 638 aprint_error(": can't create dma map"); 639 error = ENOBUFS; 640 goto out; 641 } 642 643 state = 3; 644 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 645 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 646 aprint_error(": can't load dma map"); 647 error = ENOBUFS; 648 goto out; 649 } 650 651 state = 4; 652 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 653 DPRINTFN(1,("msk_jumbo_buf = %p\n", 654 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 655 656 LIST_INIT(&sc_if->sk_jfree_listhead); 657 LIST_INIT(&sc_if->sk_jinuse_listhead); 658 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 659 660 /* 661 * Now divide it up into 9K pieces and save the addresses 662 * in an array. 663 */ 664 ptr = sc_if->sk_cdata.sk_jumbo_buf; 665 for (i = 0; i < MSK_JSLOTS; i++) { 666 sc_if->sk_cdata.sk_jslots[i] = ptr; 667 ptr += SK_JLEN; 668 entry = malloc(sizeof(struct sk_jpool_entry), 669 M_DEVBUF, M_WAITOK); 670 entry->slot = i; 671 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 672 entry, jpool_entries); 673 } 674 out: 675 if (error != 0) { 676 switch (state) { 677 case 4: 678 bus_dmamap_unload(sc->sc_dmatag, 679 sc_if->sk_cdata.sk_rx_jumbo_map); 680 /* FALLTHROUGH */ 681 case 3: 682 bus_dmamap_destroy(sc->sc_dmatag, 683 sc_if->sk_cdata.sk_rx_jumbo_map); 684 /* FALLTHROUGH */ 685 case 2: 686 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 687 /* FALLTHROUGH */ 688 case 1: 689 bus_dmamem_free(sc->sc_dmatag, 690 &sc_if->sk_cdata.sk_jumbo_seg, 691 sc_if->sk_cdata.sk_jumbo_nseg); 692 break; 693 default: 694 break; 695 } 696 } 697 698 return error; 699 } 700 701 static void 702 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 703 { 704 struct sk_softc *sc = sc_if->sk_softc; 705 706 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 707 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 708 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 709 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 710 sc_if->sk_cdata.sk_jumbo_nseg); 711 } 712 713 /* 714 * Allocate a jumbo buffer. 715 */ 716 static void * 717 msk_jalloc(struct sk_if_softc *sc_if) 718 { 719 struct sk_jpool_entry *entry; 720 721 mutex_enter(&sc_if->sk_jpool_mtx); 722 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 723 724 if (entry == NULL) { 725 mutex_exit(&sc_if->sk_jpool_mtx); 726 return NULL; 727 } 728 729 LIST_REMOVE(entry, jpool_entries); 730 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 731 mutex_exit(&sc_if->sk_jpool_mtx); 732 return sc_if->sk_cdata.sk_jslots[entry->slot]; 733 } 734 735 /* 736 * Release a jumbo buffer. 737 */ 738 static void 739 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 740 { 741 struct sk_jpool_entry *entry; 742 struct sk_if_softc *sc; 743 int i; 744 745 /* Extract the softc struct pointer. */ 746 sc = (struct sk_if_softc *)arg; 747 748 if (sc == NULL) 749 panic("msk_jfree: can't find softc pointer!"); 750 751 /* calculate the slot this buffer belongs to */ 752 i = ((vaddr_t)buf 753 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 754 755 if ((i < 0) || (i >= MSK_JSLOTS)) 756 panic("msk_jfree: asked to free buffer that we don't manage!"); 757 758 mutex_enter(&sc->sk_jpool_mtx); 759 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 760 if (entry == NULL) 761 panic("msk_jfree: buffer not in use!"); 762 entry->slot = i; 763 LIST_REMOVE(entry, jpool_entries); 764 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 765 mutex_exit(&sc->sk_jpool_mtx); 766 767 if (__predict_true(m != NULL)) 768 pool_cache_put(mb_cache, m); 769 770 /* Now that we know we have a free RX buffer, refill if running out */ 771 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 772 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 773 callout_schedule(&sc->sk_tick_rx, 0); 774 } 775 776 static int 777 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 778 { 779 struct sk_if_softc *sc = ifp->if_softc; 780 int s, error; 781 782 s = splnet(); 783 784 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 785 switch (cmd) { 786 case SIOCSIFFLAGS: 787 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 788 break; 789 790 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 791 case IFF_RUNNING: 792 msk_stop(ifp, 1); 793 break; 794 case IFF_UP: 795 msk_init(ifp); 796 break; 797 case IFF_UP | IFF_RUNNING: 798 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 799 msk_setpromisc(sc); 800 msk_setmulti(sc); 801 } else 802 msk_init(ifp); 803 break; 804 } 805 sc->sk_if_flags = ifp->if_flags; 806 break; 807 default: 808 error = ether_ioctl(ifp, cmd, data); 809 if (error == ENETRESET) { 810 error = 0; 811 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 812 ; 813 else if (ifp->if_flags & IFF_RUNNING) { 814 /* 815 * Multicast list has changed; set the hardware 816 * filter accordingly. 817 */ 818 msk_setmulti(sc); 819 } 820 } 821 break; 822 } 823 824 splx(s); 825 return error; 826 } 827 828 static void 829 msk_update_int_mod(struct sk_softc *sc, int verbose) 830 { 831 uint32_t imtimer_ticks; 832 833 /* 834 * Configure interrupt moderation. The moderation timer 835 * defers interrupts specified in the interrupt moderation 836 * timer mask based on the timeout specified in the interrupt 837 * moderation timer init register. Each bit in the timer 838 * register represents one tick, so to specify a timeout in 839 * microseconds, we have to multiply by the correct number of 840 * ticks-per-microsecond. 841 */ 842 switch (sc->sk_type) { 843 case SK_YUKON_EC: 844 case SK_YUKON_EC_U: 845 case SK_YUKON_EX: 846 case SK_YUKON_SUPR: 847 case SK_YUKON_ULTRA2: 848 case SK_YUKON_OPTIMA: 849 case SK_YUKON_PRM: 850 case SK_YUKON_OPTIMA2: 851 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 852 break; 853 case SK_YUKON_FE: 854 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 855 break; 856 case SK_YUKON_FE_P: 857 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 858 break; 859 case SK_YUKON_XL: 860 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 861 break; 862 default: 863 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 864 } 865 if (verbose) 866 aprint_verbose_dev(sc->sk_dev, 867 "interrupt moderation is %d us\n", sc->sk_int_mod); 868 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 869 sk_win_write_4(sc, SK_IMMR, SK_Y2_IMR_BMU); 870 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 871 sc->sk_int_mod_pending = 0; 872 } 873 874 static int 875 msk_lookup(const struct pci_attach_args *pa) 876 { 877 const struct msk_product *pmsk; 878 879 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 880 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 881 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 882 return 1; 883 } 884 return 0; 885 } 886 887 /* 888 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 889 * IDs against our list and return a device name if we find a match. 890 */ 891 static int 892 mskc_probe(device_t parent, cfdata_t match, void *aux) 893 { 894 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 895 896 return msk_lookup(pa); 897 } 898 899 /* 900 * Force the GEnesis into reset, then bring it out of reset. 901 */ 902 static void 903 mskc_reset(struct sk_softc *sc) 904 { 905 uint32_t imtimer_ticks, reg1; 906 uint16_t status; 907 int reg; 908 909 DPRINTFN(2, ("mskc_reset\n")); 910 911 /* Disable ASF */ 912 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 913 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 914 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 915 /* Clear AHB bridge & microcontroller reset. */ 916 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 917 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 918 /* Clear ASF microcontroller state. */ 919 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 920 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 921 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 922 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 923 } else 924 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 925 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 926 927 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 928 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 929 930 DELAY(1000); 931 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 932 DELAY(2); 933 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 934 sk_win_write_1(sc, SK_TESTCTL1, 2); 935 936 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 937 sc->sk_type >= SK_YUKON_FE_P) { 938 uint32_t our; 939 940 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 941 942 /* enable all clocks. */ 943 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 944 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 945 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 946 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 947 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 948 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 949 /* Set all bits to 0 except bits 15..12 */ 950 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 951 /* Set to default value */ 952 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 953 954 /* 955 * Disable status race, workaround for Yukon EC Ultra & 956 * Yukon EX. 957 */ 958 reg1 = sk_win_read_4(sc, SK_GPIO); 959 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 960 sk_win_write_4(sc, SK_GPIO, reg1); 961 sk_win_read_4(sc, SK_GPIO); 962 } 963 964 /* release PHY from PowerDown/Coma mode. */ 965 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 966 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 967 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 968 else 969 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 970 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 971 972 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 973 sk_win_write_1(sc, SK_Y2_CLKGATE, 974 SK_Y2_CLKGATE_LINK1_GATE_DIS | 975 SK_Y2_CLKGATE_LINK2_GATE_DIS | 976 SK_Y2_CLKGATE_LINK1_CORE_DIS | 977 SK_Y2_CLKGATE_LINK2_CORE_DIS | 978 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 979 else 980 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 981 982 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 983 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 984 DELAY(1000); 985 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 986 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 987 988 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 989 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 990 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 991 } 992 993 sk_win_write_1(sc, SK_TESTCTL1, 1); 994 995 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 996 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 997 CSR_READ_2(sc, SK_LINK_CTRL))); 998 999 /* Clear I2C IRQ noise */ 1000 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 1001 1002 /* Disable hardware timer */ 1003 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 1004 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 1005 1006 /* Disable descriptor polling */ 1007 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 1008 1009 /* Disable time stamps */ 1010 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 1011 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 1012 1013 /* Enable RAM interface */ 1014 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1015 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1016 sk_win_write_1(sc, reg, 36); 1017 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 1018 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1019 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 1020 1021 /* 1022 * Configure interrupt moderation. The moderation timer 1023 * defers interrupts specified in the interrupt moderation 1024 * timer mask based on the timeout specified in the interrupt 1025 * moderation timer init register. Each bit in the timer 1026 * register represents one tick, so to specify a timeout in 1027 * microseconds, we have to multiply by the correct number of 1028 * ticks-per-microsecond. 1029 */ 1030 switch (sc->sk_type) { 1031 case SK_YUKON_EC: 1032 case SK_YUKON_EC_U: 1033 case SK_YUKON_EX: 1034 case SK_YUKON_SUPR: 1035 case SK_YUKON_ULTRA2: 1036 case SK_YUKON_OPTIMA: 1037 case SK_YUKON_PRM: 1038 case SK_YUKON_OPTIMA2: 1039 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1040 break; 1041 case SK_YUKON_FE: 1042 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1043 break; 1044 case SK_YUKON_FE_P: 1045 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1046 break; 1047 case SK_YUKON_XL: 1048 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1049 break; 1050 default: 1051 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1052 break; 1053 } 1054 1055 /* Reset status ring. */ 1056 memset(sc->sk_status_ring, 0, 1057 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1058 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1059 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1060 sc->sk_status_idx = 0; 1061 1062 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1063 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1064 1065 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1066 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1067 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1068 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1069 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1070 if (sc->sk_type == SK_YUKON_EC && 1071 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1072 /* WA for dev. #4.3 */ 1073 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1074 SK_STAT_BMU_TXTHIDX_MSK); 1075 /* WA for dev. #4.18 */ 1076 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1077 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1078 } else { 1079 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1080 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1081 if (sc->sk_type == SK_YUKON_XL) 1082 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1083 else 1084 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1085 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1086 } 1087 1088 #if 0 1089 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1090 #endif 1091 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1092 1093 /* Enable status unit. */ 1094 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1095 1096 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1097 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1098 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1099 1100 msk_update_int_mod(sc, 0); 1101 } 1102 1103 static int 1104 msk_probe(device_t parent, cfdata_t match, void *aux) 1105 { 1106 struct skc_attach_args *sa = aux; 1107 1108 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1109 return 0; 1110 1111 switch (sa->skc_type) { 1112 case SK_YUKON_XL: 1113 case SK_YUKON_EC_U: 1114 case SK_YUKON_EX: 1115 case SK_YUKON_EC: 1116 case SK_YUKON_FE: 1117 case SK_YUKON_FE_P: 1118 case SK_YUKON_SUPR: 1119 case SK_YUKON_ULTRA2: 1120 case SK_YUKON_OPTIMA: 1121 case SK_YUKON_PRM: 1122 case SK_YUKON_OPTIMA2: 1123 return 1; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static void 1130 msk_reset(struct sk_if_softc *sc_if) 1131 { 1132 /* GMAC and GPHY Reset */ 1133 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1134 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1135 DELAY(1000); 1136 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1137 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1138 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1139 } 1140 1141 static bool 1142 msk_resume(device_t dv, const pmf_qual_t *qual) 1143 { 1144 struct sk_if_softc *sc_if = device_private(dv); 1145 1146 msk_init_yukon(sc_if); 1147 return true; 1148 } 1149 1150 /* 1151 * Each XMAC chip is attached as a separate logical IP interface. 1152 * Single port cards will have only one logical interface of course. 1153 */ 1154 static void 1155 msk_attach(device_t parent, device_t self, void *aux) 1156 { 1157 struct sk_if_softc *sc_if = device_private(self); 1158 struct sk_softc *sc = device_private(parent); 1159 struct skc_attach_args *sa = aux; 1160 bus_dmamap_t dmamap; 1161 struct ifnet *ifp; 1162 struct mii_data * const mii = &sc_if->sk_mii; 1163 void *kva; 1164 int i; 1165 uint32_t chunk; 1166 int mii_flags; 1167 1168 sc_if->sk_dev = self; 1169 sc_if->sk_port = sa->skc_port; 1170 sc_if->sk_softc = sc; 1171 sc->sk_if[sa->skc_port] = sc_if; 1172 1173 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1174 1175 /* 1176 * Get station address for this interface. Note that 1177 * dual port cards actually come with three station 1178 * addresses: one for each port, plus an extra. The 1179 * extra one is used by the SysKonnect driver software 1180 * as a 'virtual' station address for when both ports 1181 * are operating in failover mode. Currently we don't 1182 * use this extra address. 1183 */ 1184 for (i = 0; i < ETHER_ADDR_LEN; i++) 1185 sc_if->sk_enaddr[i] = 1186 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1187 1188 aprint_normal(": Ethernet address %s\n", 1189 ether_sprintf(sc_if->sk_enaddr)); 1190 1191 /* 1192 * Set up RAM buffer addresses. The Yukon2 has a small amount 1193 * of SRAM on it, somewhere between 4K and 48K. We need to 1194 * divide this up between the transmitter and receiver. We 1195 * give the receiver 2/3 of the memory (rounded down), and the 1196 * transmitter whatever remains. 1197 */ 1198 if (sc->sk_ramsize) { 1199 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1200 sc_if->sk_rx_ramstart = 0; 1201 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1202 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1203 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1204 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1205 1206 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1207 " tx_ramstart=%#x tx_ramend=%#x\n", 1208 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1209 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1210 } 1211 1212 /* Allocate the descriptor queues. */ 1213 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1214 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1215 BUS_DMA_NOWAIT)) { 1216 aprint_error(": can't alloc rx buffers\n"); 1217 goto fail; 1218 } 1219 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1220 sc_if->sk_ring_nseg, 1221 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1222 aprint_error(": can't map dma buffers (%zu bytes)\n", 1223 sizeof(struct msk_ring_data)); 1224 goto fail_1; 1225 } 1226 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1227 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1228 &sc_if->sk_ring_map)) { 1229 aprint_error(": can't create dma map\n"); 1230 goto fail_2; 1231 } 1232 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1233 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1234 aprint_error(": can't load dma map\n"); 1235 goto fail_3; 1236 } 1237 1238 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1239 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1240 1241 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1242 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1243 aprint_error_dev(sc_if->sk_dev, 1244 "Can't create TX dmamap\n"); 1245 goto fail_3; 1246 } 1247 1248 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap = dmamap; 1249 } 1250 1251 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1252 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1253 1254 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, 1255 howmany(SK_JLEN + 1, NBPG), 1256 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1257 aprint_error_dev(sc_if->sk_dev, 1258 "Can't create RX dmamap\n"); 1259 goto fail_3; 1260 } 1261 1262 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap = dmamap; 1263 } 1264 1265 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1266 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1267 1268 if (sc->sk_type != SK_YUKON_FE && 1269 sc->sk_type != SK_YUKON_FE_P) 1270 sc_if->sk_pktlen = SK_JLEN; 1271 else 1272 sc_if->sk_pktlen = MCLBYTES; 1273 1274 /* Try to allocate memory for jumbo buffers. */ 1275 if (msk_alloc_jumbo_mem(sc_if)) { 1276 aprint_error(": jumbo buffer allocation failed\n"); 1277 goto fail_3; 1278 } 1279 1280 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1281 if (sc->sk_type != SK_YUKON_FE && 1282 sc->sk_type != SK_YUKON_FE_P) 1283 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1284 1285 ifp = &sc_if->sk_ethercom.ec_if; 1286 ifp->if_softc = sc_if; 1287 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1288 ifp->if_ioctl = msk_ioctl; 1289 ifp->if_start = msk_start; 1290 ifp->if_stop = msk_stop; 1291 ifp->if_init = msk_init; 1292 ifp->if_watchdog = msk_watchdog; 1293 ifp->if_baudrate = 1000000000; 1294 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1295 IFQ_SET_READY(&ifp->if_snd); 1296 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1297 1298 msk_reset(sc_if); 1299 1300 /* 1301 * Do miibus setup. 1302 */ 1303 DPRINTFN(2, ("msk_attach: 1\n")); 1304 1305 mii->mii_ifp = ifp; 1306 mii->mii_readreg = msk_miibus_readreg; 1307 mii->mii_writereg = msk_miibus_writereg; 1308 mii->mii_statchg = msk_miibus_statchg; 1309 1310 sc_if->sk_ethercom.ec_mii = mii; 1311 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1312 mii_flags = MIIF_DOPAUSE; 1313 if (sc->sk_fibertype) 1314 mii_flags |= MIIF_HAVEFIBER; 1315 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1316 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1317 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1318 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1319 0, NULL); 1320 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1321 } else 1322 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1323 1324 callout_init(&sc_if->sk_tick_ch, 0); 1325 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1326 callout_schedule(&sc_if->sk_tick_ch, hz); 1327 1328 callout_init(&sc_if->sk_tick_rx, 0); 1329 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1330 1331 /* 1332 * Call MI attach routines. 1333 */ 1334 if_attach(ifp); 1335 if_deferred_start_init(ifp, NULL); 1336 ether_ifattach(ifp, sc_if->sk_enaddr); 1337 1338 if (pmf_device_register(self, NULL, msk_resume)) 1339 pmf_class_network_register(self, ifp); 1340 else 1341 aprint_error_dev(self, "couldn't establish power handler\n"); 1342 1343 if (sc->rnd_attached++ == 0) { 1344 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1345 RND_TYPE_NET, RND_FLAG_DEFAULT); 1346 } 1347 1348 DPRINTFN(2, ("msk_attach: end\n")); 1349 return; 1350 1351 fail_3: 1352 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1353 fail_2: 1354 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1355 fail_1: 1356 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1357 fail: 1358 sc->sk_if[sa->skc_port] = NULL; 1359 } 1360 1361 static int 1362 msk_detach(device_t self, int flags) 1363 { 1364 struct sk_if_softc *sc_if = device_private(self); 1365 struct sk_softc *sc = sc_if->sk_softc; 1366 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1367 int i; 1368 1369 if (sc->sk_if[sc_if->sk_port] == NULL) 1370 return 0; 1371 1372 msk_stop(ifp, 1); 1373 1374 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1375 bus_dmamap_destroy(sc->sc_dmatag, 1376 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap); 1377 } 1378 1379 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1380 bus_dmamap_destroy(sc->sc_dmatag, 1381 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap); 1382 } 1383 1384 if (--sc->rnd_attached == 0) 1385 rnd_detach_source(&sc->rnd_source); 1386 1387 callout_halt(&sc_if->sk_tick_ch, NULL); 1388 callout_destroy(&sc_if->sk_tick_ch); 1389 1390 callout_halt(&sc_if->sk_tick_rx, NULL); 1391 callout_destroy(&sc_if->sk_tick_rx); 1392 1393 /* Detach any PHYs we might have. */ 1394 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1395 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1396 1397 pmf_device_deregister(self); 1398 1399 ether_ifdetach(ifp); 1400 if_detach(ifp); 1401 1402 /* Delete any remaining media. */ 1403 ifmedia_fini(&sc_if->sk_mii.mii_media); 1404 1405 msk_free_jumbo_mem(sc_if); 1406 1407 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1408 sizeof(struct msk_ring_data)); 1409 bus_dmamem_free(sc->sc_dmatag, 1410 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1411 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1412 sc->sk_if[sc_if->sk_port] = NULL; 1413 1414 return 0; 1415 } 1416 1417 static int 1418 mskcprint(void *aux, const char *pnp) 1419 { 1420 struct skc_attach_args *sa = aux; 1421 1422 if (pnp) 1423 aprint_normal("msk port %c at %s", 1424 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1425 else 1426 aprint_normal(" port %c", 1427 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1428 return UNCONF; 1429 } 1430 1431 /* 1432 * Attach the interface. Allocate softc structures, do ifmedia 1433 * setup and ethernet/BPF attach. 1434 */ 1435 static void 1436 mskc_attach(device_t parent, device_t self, void *aux) 1437 { 1438 struct sk_softc *sc = device_private(self); 1439 struct pci_attach_args *pa = aux; 1440 struct skc_attach_args skca; 1441 pci_chipset_tag_t pc = pa->pa_pc; 1442 pcireg_t command, memtype; 1443 const char *intrstr = NULL; 1444 int rc, sk_nodenum; 1445 uint8_t hw, pmd; 1446 const char *revstr = NULL; 1447 const struct sysctlnode *node; 1448 void *kva; 1449 char intrbuf[PCI_INTRSTR_LEN]; 1450 1451 DPRINTFN(2, ("begin mskc_attach\n")); 1452 1453 sc->sk_dev = self; 1454 /* 1455 * Handle power management nonsense. 1456 */ 1457 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1458 1459 if (command == 0x01) { 1460 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1461 if (command & SK_PSTATE_MASK) { 1462 uint32_t iobase, membase, irq; 1463 1464 /* Save important PCI config data. */ 1465 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1466 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1467 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1468 1469 /* Reset the power state. */ 1470 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1471 "mode -- setting to D0\n", 1472 command & SK_PSTATE_MASK); 1473 command &= 0xFFFFFFFC; 1474 pci_conf_write(pc, pa->pa_tag, 1475 SK_PCI_PWRMGMTCTRL, command); 1476 1477 /* Restore PCI config data. */ 1478 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1479 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1480 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1481 } 1482 } 1483 1484 /* 1485 * Map control/status registers. 1486 */ 1487 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1488 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1489 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1490 aprint_error(": can't map mem space\n"); 1491 return; 1492 } 1493 1494 if (pci_dma64_available(pa)) 1495 sc->sc_dmatag = pa->pa_dmat64; 1496 else 1497 sc->sc_dmatag = pa->pa_dmat; 1498 1499 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1500 command |= PCI_COMMAND_MASTER_ENABLE; 1501 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1502 1503 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1504 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1505 1506 /* bail out here if chip is not recognized */ 1507 if (!(SK_IS_YUKON2(sc))) { 1508 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1509 goto fail_1; 1510 } 1511 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1512 1513 /* Allocate interrupt */ 1514 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1515 aprint_error(": couldn't map interrupt\n"); 1516 goto fail_1; 1517 } 1518 1519 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1520 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1521 msk_intr, sc, device_xname(sc->sk_dev)); 1522 if (sc->sk_intrhand == NULL) { 1523 aprint_error(": couldn't establish interrupt"); 1524 if (intrstr != NULL) 1525 aprint_error(" at %s", intrstr); 1526 aprint_error("\n"); 1527 goto fail_1; 1528 } 1529 sc->sk_pc = pc; 1530 1531 if (bus_dmamem_alloc(sc->sc_dmatag, 1532 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1533 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1534 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1535 aprint_error(": can't alloc status buffers\n"); 1536 goto fail_2; 1537 } 1538 1539 if (bus_dmamem_map(sc->sc_dmatag, 1540 &sc->sk_status_seg, sc->sk_status_nseg, 1541 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1542 &kva, BUS_DMA_NOWAIT)) { 1543 aprint_error(": can't map dma buffers (%zu bytes)\n", 1544 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1545 goto fail_3; 1546 } 1547 if (bus_dmamap_create(sc->sc_dmatag, 1548 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1549 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1550 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1551 aprint_error(": can't create dma map\n"); 1552 goto fail_4; 1553 } 1554 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1555 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1556 NULL, BUS_DMA_NOWAIT)) { 1557 aprint_error(": can't load dma map\n"); 1558 goto fail_5; 1559 } 1560 sc->sk_status_ring = (struct msk_status_desc *)kva; 1561 1562 sc->sk_int_mod = SK_IM_DEFAULT; 1563 sc->sk_int_mod_pending = 0; 1564 1565 /* Reset the adapter. */ 1566 mskc_reset(sc); 1567 1568 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1569 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1570 1571 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1572 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1573 sc->sk_fibertype = 1; 1574 1575 switch (sc->sk_type) { 1576 case SK_YUKON_XL: 1577 sc->sk_name = "Yukon-2 XL"; 1578 break; 1579 case SK_YUKON_EC_U: 1580 sc->sk_name = "Yukon-2 EC Ultra"; 1581 break; 1582 case SK_YUKON_EX: 1583 sc->sk_name = "Yukon-2 Extreme"; 1584 break; 1585 case SK_YUKON_EC: 1586 sc->sk_name = "Yukon-2 EC"; 1587 break; 1588 case SK_YUKON_FE: 1589 sc->sk_name = "Yukon-2 FE"; 1590 break; 1591 case SK_YUKON_FE_P: 1592 sc->sk_name = "Yukon-2 FE+"; 1593 break; 1594 case SK_YUKON_SUPR: 1595 sc->sk_name = "Yukon-2 Supreme"; 1596 break; 1597 case SK_YUKON_ULTRA2: 1598 sc->sk_name = "Yukon-2 Ultra 2"; 1599 break; 1600 case SK_YUKON_OPTIMA: 1601 sc->sk_name = "Yukon-2 Optima"; 1602 break; 1603 case SK_YUKON_PRM: 1604 sc->sk_name = "Yukon-2 Optima Prime"; 1605 break; 1606 case SK_YUKON_OPTIMA2: 1607 sc->sk_name = "Yukon-2 Optima 2"; 1608 break; 1609 default: 1610 sc->sk_name = "Yukon (Unknown)"; 1611 } 1612 1613 if (sc->sk_type == SK_YUKON_XL) { 1614 switch (sc->sk_rev) { 1615 case SK_YUKON_XL_REV_A0: 1616 revstr = "A0"; 1617 break; 1618 case SK_YUKON_XL_REV_A1: 1619 revstr = "A1"; 1620 break; 1621 case SK_YUKON_XL_REV_A2: 1622 revstr = "A2"; 1623 break; 1624 case SK_YUKON_XL_REV_A3: 1625 revstr = "A3"; 1626 break; 1627 default: 1628 break; 1629 } 1630 } 1631 1632 if (sc->sk_type == SK_YUKON_EC) { 1633 switch (sc->sk_rev) { 1634 case SK_YUKON_EC_REV_A1: 1635 revstr = "A1"; 1636 break; 1637 case SK_YUKON_EC_REV_A2: 1638 revstr = "A2"; 1639 break; 1640 case SK_YUKON_EC_REV_A3: 1641 revstr = "A3"; 1642 break; 1643 default: 1644 break; 1645 } 1646 } 1647 1648 if (sc->sk_type == SK_YUKON_FE) { 1649 switch (sc->sk_rev) { 1650 case SK_YUKON_FE_REV_A1: 1651 revstr = "A1"; 1652 break; 1653 case SK_YUKON_FE_REV_A2: 1654 revstr = "A2"; 1655 break; 1656 default: 1657 break; 1658 } 1659 } 1660 1661 if (sc->sk_type == SK_YUKON_EC_U) { 1662 switch (sc->sk_rev) { 1663 case SK_YUKON_EC_U_REV_A0: 1664 revstr = "A0"; 1665 break; 1666 case SK_YUKON_EC_U_REV_A1: 1667 revstr = "A1"; 1668 break; 1669 case SK_YUKON_EC_U_REV_B0: 1670 revstr = "B0"; 1671 break; 1672 case SK_YUKON_EC_U_REV_B1: 1673 revstr = "B1"; 1674 break; 1675 default: 1676 break; 1677 } 1678 } 1679 1680 if (sc->sk_type == SK_YUKON_FE) { 1681 switch (sc->sk_rev) { 1682 case SK_YUKON_FE_REV_A1: 1683 revstr = "A1"; 1684 break; 1685 case SK_YUKON_FE_REV_A2: 1686 revstr = "A2"; 1687 break; 1688 default: 1689 ; 1690 } 1691 } 1692 1693 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1694 revstr = "A0"; 1695 1696 if (sc->sk_type == SK_YUKON_EX) { 1697 switch (sc->sk_rev) { 1698 case SK_YUKON_EX_REV_A0: 1699 revstr = "A0"; 1700 break; 1701 case SK_YUKON_EX_REV_B0: 1702 revstr = "B0"; 1703 break; 1704 default: 1705 ; 1706 } 1707 } 1708 1709 if (sc->sk_type == SK_YUKON_SUPR) { 1710 switch (sc->sk_rev) { 1711 case SK_YUKON_SUPR_REV_A0: 1712 revstr = "A0"; 1713 break; 1714 case SK_YUKON_SUPR_REV_B0: 1715 revstr = "B0"; 1716 break; 1717 case SK_YUKON_SUPR_REV_B1: 1718 revstr = "B1"; 1719 break; 1720 default: 1721 ; 1722 } 1723 } 1724 1725 if (sc->sk_type == SK_YUKON_PRM) { 1726 switch (sc->sk_rev) { 1727 case SK_YUKON_PRM_REV_Z1: 1728 revstr = "Z1"; 1729 break; 1730 case SK_YUKON_PRM_REV_A0: 1731 revstr = "A0"; 1732 break; 1733 default: 1734 ; 1735 } 1736 } 1737 1738 /* Announce the product name. */ 1739 aprint_normal(", %s", sc->sk_name); 1740 if (revstr != NULL) 1741 aprint_normal(" rev. %s", revstr); 1742 aprint_normal(" (0x%x)\n", sc->sk_rev); 1743 1744 aprint_normal_dev(sc->sk_dev, "interrupting at %s\n", intrstr); 1745 1746 sc->sk_macs = 1; 1747 1748 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1749 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1750 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1751 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1752 sc->sk_macs++; 1753 } 1754 1755 skca.skc_port = SK_PORT_A; 1756 skca.skc_type = sc->sk_type; 1757 skca.skc_rev = sc->sk_rev; 1758 (void)config_found(sc->sk_dev, &skca, mskcprint); 1759 1760 if (sc->sk_macs > 1) { 1761 skca.skc_port = SK_PORT_B; 1762 skca.skc_type = sc->sk_type; 1763 skca.skc_rev = sc->sk_rev; 1764 (void)config_found(sc->sk_dev, &skca, mskcprint); 1765 } 1766 1767 /* Turn on the 'driver is loaded' LED. */ 1768 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1769 1770 /* skc sysctl setup */ 1771 1772 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1773 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1774 SYSCTL_DESCR("mskc per-controller controls"), 1775 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1776 CTL_EOL)) != 0) { 1777 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1778 goto fail_6; 1779 } 1780 1781 sk_nodenum = node->sysctl_num; 1782 1783 /* interrupt moderation time in usecs */ 1784 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1785 CTLFLAG_READWRITE, 1786 CTLTYPE_INT, "int_mod", 1787 SYSCTL_DESCR("msk interrupt moderation timer"), 1788 msk_sysctl_handler, 0, (void *)sc, 1789 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1790 CTL_EOL)) != 0) { 1791 aprint_normal_dev(sc->sk_dev, 1792 "couldn't create int_mod sysctl node\n"); 1793 goto fail_6; 1794 } 1795 1796 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1797 aprint_error_dev(self, "couldn't establish power handler\n"); 1798 1799 return; 1800 1801 fail_6: 1802 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1803 fail_4: 1804 bus_dmamem_unmap(sc->sc_dmatag, kva, 1805 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1806 fail_3: 1807 bus_dmamem_free(sc->sc_dmatag, 1808 &sc->sk_status_seg, sc->sk_status_nseg); 1809 sc->sk_status_nseg = 0; 1810 fail_5: 1811 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1812 fail_2: 1813 pci_intr_disestablish(pc, sc->sk_intrhand); 1814 sc->sk_intrhand = NULL; 1815 fail_1: 1816 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1817 sc->sk_bsize = 0; 1818 } 1819 1820 static int 1821 mskc_detach(device_t self, int flags) 1822 { 1823 struct sk_softc *sc = device_private(self); 1824 int rv; 1825 1826 if (sc->sk_intrhand) { 1827 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1828 sc->sk_intrhand = NULL; 1829 } 1830 1831 if (sc->sk_pihp != NULL) { 1832 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1833 sc->sk_pihp = NULL; 1834 } 1835 1836 rv = config_detach_children(self, flags); 1837 if (rv != 0) 1838 return rv; 1839 1840 if (sc->sk_status_nseg > 0) { 1841 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1842 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1843 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1844 bus_dmamem_free(sc->sc_dmatag, 1845 &sc->sk_status_seg, sc->sk_status_nseg); 1846 } 1847 1848 if (sc->sk_bsize > 0) 1849 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1850 1851 return 0; 1852 } 1853 1854 static int 1855 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1856 { 1857 struct sk_softc *sc = sc_if->sk_softc; 1858 struct msk_tx_desc *f = NULL; 1859 uint32_t frag, cur, hiaddr, old_hiaddr, total; 1860 uint32_t entries = 0; 1861 size_t i; 1862 bus_dmamap_t txmap; 1863 bus_addr_t addr; 1864 1865 DPRINTFN(2, ("msk_encap\n")); 1866 1867 txmap = sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap; 1868 1869 cur = frag = *txidx; 1870 1871 #ifdef MSK_DEBUG 1872 if (mskdebug >= 2) 1873 msk_dump_mbuf(m_head); 1874 #endif 1875 1876 /* 1877 * Start packing the mbufs in this chain into 1878 * the fragment pointers. Stop when we run out 1879 * of fragments or hit the end of the mbuf chain. 1880 */ 1881 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1882 BUS_DMA_NOWAIT)) { 1883 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1884 return ENOBUFS; 1885 } 1886 1887 /* Count how many tx descriptors needed. */ 1888 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1889 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1890 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1891 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1892 total++; 1893 } 1894 total++; 1895 } 1896 1897 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1898 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1899 bus_dmamap_unload(sc->sc_dmatag, txmap); 1900 return ENOBUFS; 1901 } 1902 1903 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1904 txmap->dm_nsegs, total)); 1905 1906 /* Sync the DMA map. */ 1907 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1908 BUS_DMASYNC_PREWRITE); 1909 1910 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1911 for (i = 0; i < txmap->dm_nsegs; i++) { 1912 addr = txmap->dm_segs[i].ds_addr; 1913 DPRINTFN(2, ("msk_encap: addr %llx\n", 1914 (unsigned long long)addr)); 1915 hiaddr = MSK_ADDR_HI(addr); 1916 1917 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1918 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1919 f->sk_addr = htole32(hiaddr); 1920 f->sk_len = 0; 1921 f->sk_ctl = 0; 1922 if (i == 0) 1923 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1924 else 1925 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1926 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1927 SK_INC(frag, MSK_TX_RING_CNT); 1928 entries++; 1929 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1930 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1931 } 1932 1933 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1934 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1935 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1936 f->sk_ctl = 0; 1937 if (i == 0) { 1938 if (hiaddr != old_hiaddr) 1939 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1940 else 1941 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1942 } else 1943 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1944 cur = frag; 1945 SK_INC(frag, MSK_TX_RING_CNT); 1946 entries++; 1947 } 1948 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1949 1950 sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap = 1951 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap; 1952 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1953 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap = txmap; 1954 1955 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1956 1957 /* Sync descriptors before handing to chip */ 1958 MSK_CDTXSYNC(sc_if, *txidx, entries, 1959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1960 1961 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1962 1963 /* Sync first descriptor to hand it off */ 1964 MSK_CDTXSYNC(sc_if, *txidx, 1, 1965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1966 1967 sc_if->sk_cdata.sk_tx_cnt += entries; 1968 1969 #ifdef MSK_DEBUG 1970 if (mskdebug >= 2) { 1971 struct msk_tx_desc *le; 1972 uint32_t idx; 1973 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1974 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1975 msk_dump_txdesc(le, idx); 1976 } 1977 } 1978 #endif 1979 1980 *txidx = frag; 1981 1982 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1983 1984 return 0; 1985 } 1986 1987 static void 1988 msk_start(struct ifnet *ifp) 1989 { 1990 struct sk_if_softc *sc_if = ifp->if_softc; 1991 struct mbuf *m_head = NULL; 1992 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1993 int pkts = 0; 1994 1995 DPRINTFN(2, ("msk_start\n")); 1996 1997 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1998 IFQ_POLL(&ifp->if_snd, m_head); 1999 if (m_head == NULL) 2000 break; 2001 2002 /* 2003 * Pack the data into the transmit ring. If we 2004 * don't have room, set the OACTIVE flag and wait 2005 * for the NIC to drain the ring. 2006 */ 2007 if (msk_encap(sc_if, m_head, &idx)) { 2008 ifp->if_flags |= IFF_OACTIVE; 2009 break; 2010 } 2011 2012 /* now we are committed to transmit the packet */ 2013 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2014 pkts++; 2015 2016 /* 2017 * If there's a BPF listener, bounce a copy of this frame 2018 * to him. 2019 */ 2020 bpf_mtap(ifp, m_head, BPF_D_OUT); 2021 } 2022 if (pkts == 0) 2023 return; 2024 2025 /* Transmit */ 2026 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2027 sc_if->sk_cdata.sk_tx_prod = idx; 2028 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 2029 2030 /* Set a timeout in case the chip goes out to lunch. */ 2031 ifp->if_timer = 5; 2032 } 2033 } 2034 2035 static void 2036 msk_watchdog(struct ifnet *ifp) 2037 { 2038 struct sk_if_softc *sc_if = ifp->if_softc; 2039 2040 /* 2041 * Reclaim first as there is a possibility of losing Tx completion 2042 * interrupts. 2043 */ 2044 msk_txeof(sc_if); 2045 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2046 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2047 2048 if_statinc(ifp, if_oerrors); 2049 2050 /* XXX Resets both ports; we shouldn't do that. */ 2051 mskc_reset(sc_if->sk_softc); 2052 msk_reset(sc_if); 2053 msk_init(ifp); 2054 } 2055 } 2056 2057 static bool 2058 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2059 { 2060 struct sk_softc *sc = device_private(dv); 2061 2062 DPRINTFN(2, ("mskc_suspend\n")); 2063 2064 /* Turn off the 'driver is loaded' LED. */ 2065 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2066 2067 return true; 2068 } 2069 2070 static bool 2071 mskc_resume(device_t dv, const pmf_qual_t *qual) 2072 { 2073 struct sk_softc *sc = device_private(dv); 2074 2075 DPRINTFN(2, ("mskc_resume\n")); 2076 2077 mskc_reset(sc); 2078 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2079 2080 return true; 2081 } 2082 2083 static __inline int 2084 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2085 { 2086 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2087 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2088 YU_RXSTAT_JABBER)) != 0 || 2089 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2090 YU_RXSTAT_BYTES(stat) != len) 2091 return 0; 2092 2093 return 1; 2094 } 2095 2096 static void 2097 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2098 { 2099 struct sk_softc *sc = sc_if->sk_softc; 2100 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2101 struct mbuf *m; 2102 unsigned cur, prod, tail, total_len = len; 2103 bus_dmamap_t dmamap; 2104 2105 cur = sc_if->sk_cdata.sk_rx_cons; 2106 prod = sc_if->sk_cdata.sk_rx_prod; 2107 2108 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2109 sc_if->sk_cdata.sk_rx_cnt)); 2110 2111 while (prod != cur) { 2112 MSK_CDRXSYNC(sc_if, cur, 2113 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2114 2115 tail = cur; 2116 SK_INC(cur, MSK_RX_RING_CNT); 2117 2118 sc_if->sk_cdata.sk_rx_cnt--; 2119 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2120 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2121 if (m != NULL) 2122 break; /* found it */ 2123 } 2124 sc_if->sk_cdata.sk_rx_cons = cur; 2125 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2126 sc_if->sk_cdata.sk_rx_cnt, m)); 2127 2128 if (m == NULL) 2129 return; 2130 2131 dmamap = sc_if->sk_cdata.sk_rx_chain[tail].sk_dmamap; 2132 2133 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2134 uimin(dmamap->dm_mapsize, total_len), BUS_DMASYNC_POSTREAD); 2135 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2136 2137 if (total_len < SK_MIN_FRAMELEN || 2138 total_len > ETHER_MAX_LEN_JUMBO || 2139 msk_rxvalid(sc, rxstat, total_len) == 0) { 2140 if_statinc(ifp, if_ierrors); 2141 m_freem(m); 2142 return; 2143 } 2144 2145 m_set_rcvif(m, ifp); 2146 m->m_pkthdr.len = m->m_len = total_len; 2147 2148 /* pass it on. */ 2149 if_percpuq_enqueue(ifp->if_percpuq, m); 2150 } 2151 2152 static void 2153 msk_txeof(struct sk_if_softc *sc_if) 2154 { 2155 struct sk_softc *sc = sc_if->sk_softc; 2156 struct msk_tx_desc *cur_tx; 2157 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2158 uint32_t idx, reg, sk_ctl; 2159 bus_dmamap_t dmamap; 2160 2161 DPRINTFN(2, ("msk_txeof\n")); 2162 2163 if (sc_if->sk_port == SK_PORT_A) 2164 reg = SK_STAT_BMU_TXA1_RIDX; 2165 else 2166 reg = SK_STAT_BMU_TXA2_RIDX; 2167 2168 /* 2169 * Go through our tx ring and free mbufs for those 2170 * frames that have been sent. 2171 */ 2172 idx = sc_if->sk_cdata.sk_tx_cons; 2173 while (idx != sk_win_read_2(sc, reg)) { 2174 MSK_CDTXSYNC(sc_if, idx, 1, 2175 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2176 2177 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2178 sk_ctl = cur_tx->sk_ctl; 2179 #ifdef MSK_DEBUG 2180 if (mskdebug >= 2) 2181 msk_dump_txdesc(cur_tx, idx); 2182 #endif 2183 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2184 if_statinc(ifp, if_opackets); 2185 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2186 dmamap = sc_if->sk_cdata.sk_tx_chain[idx].sk_dmamap; 2187 2188 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2189 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2190 2191 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2192 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2193 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2194 } 2195 sc_if->sk_cdata.sk_tx_cnt--; 2196 SK_INC(idx, MSK_TX_RING_CNT); 2197 } 2198 if (idx == sc_if->sk_cdata.sk_tx_cons) 2199 return; 2200 2201 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2202 2203 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2204 ifp->if_flags &= ~IFF_OACTIVE; 2205 2206 sc_if->sk_cdata.sk_tx_cons = idx; 2207 } 2208 2209 static void 2210 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2211 { 2212 /* Make sure to not completely wrap around */ 2213 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2214 if (msk_newbuf(sc_if) == ENOBUFS) { 2215 goto schedretry; 2216 } 2217 } 2218 2219 return; 2220 2221 schedretry: 2222 /* Try later */ 2223 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2224 } 2225 2226 static void 2227 msk_fill_rx_tick(void *xsc_if) 2228 { 2229 struct sk_if_softc *sc_if = xsc_if; 2230 int s, rx_prod; 2231 2232 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2233 2234 s = splnet(); 2235 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2236 msk_fill_rx_ring(sc_if); 2237 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2238 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2239 sc_if->sk_cdata.sk_rx_prod); 2240 } 2241 splx(s); 2242 } 2243 2244 static void 2245 msk_tick(void *xsc_if) 2246 { 2247 struct sk_if_softc *sc_if = xsc_if; 2248 struct mii_data *mii = &sc_if->sk_mii; 2249 int s; 2250 2251 s = splnet(); 2252 mii_tick(mii); 2253 splx(s); 2254 2255 callout_schedule(&sc_if->sk_tick_ch, hz); 2256 } 2257 2258 static void 2259 msk_intr_yukon(struct sk_if_softc *sc_if) 2260 { 2261 uint8_t status; 2262 2263 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2264 /* RX overrun */ 2265 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2266 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2267 SK_RFCTL_RX_FIFO_OVER); 2268 } 2269 /* TX underrun */ 2270 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2271 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2272 SK_TFCTL_TX_FIFO_UNDER); 2273 } 2274 2275 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2276 } 2277 2278 static int 2279 msk_intr(void *xsc) 2280 { 2281 struct sk_softc *sc = xsc; 2282 struct sk_if_softc *sc_if; 2283 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2284 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2285 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2286 int claimed = 0; 2287 uint32_t status; 2288 struct msk_status_desc *cur_st; 2289 2290 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2291 if (status == 0xffffffff) 2292 return 0; 2293 if (status == 0) { 2294 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2295 return 0; 2296 } 2297 2298 status = CSR_READ_4(sc, SK_ISR); 2299 2300 if (sc_if0 != NULL) 2301 ifp0 = &sc_if0->sk_ethercom.ec_if; 2302 if (sc_if1 != NULL) 2303 ifp1 = &sc_if1->sk_ethercom.ec_if; 2304 2305 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2306 (ifp0->if_flags & IFF_RUNNING)) { 2307 msk_intr_yukon(sc_if0); 2308 } 2309 2310 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2311 (ifp1->if_flags & IFF_RUNNING)) { 2312 msk_intr_yukon(sc_if1); 2313 } 2314 2315 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2316 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2317 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2318 2319 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2320 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2321 switch (cur_st->sk_opcode) { 2322 case SK_Y2_STOPC_RXSTAT: 2323 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2324 if (sc_if) { 2325 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2326 letoh32(cur_st->sk_status)); 2327 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2328 msk_fill_rx_tick(sc_if); 2329 } 2330 break; 2331 case SK_Y2_STOPC_TXSTAT: 2332 if (sc_if0) 2333 msk_txeof(sc_if0); 2334 if (sc_if1) 2335 msk_txeof(sc_if1); 2336 break; 2337 default: 2338 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2339 break; 2340 } 2341 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2342 2343 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2344 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2345 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2346 } 2347 2348 if (status & SK_Y2_IMR_BMU) { 2349 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2350 claimed = 1; 2351 } 2352 2353 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2354 2355 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2356 if_schedule_deferred_start(ifp0); 2357 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2358 if_schedule_deferred_start(ifp1); 2359 2360 KASSERT(sc->rnd_attached > 0); 2361 rnd_add_uint32(&sc->rnd_source, status); 2362 2363 if (sc->sk_int_mod_pending) 2364 msk_update_int_mod(sc, 1); 2365 2366 return claimed; 2367 } 2368 2369 static void 2370 msk_init_yukon(struct sk_if_softc *sc_if) 2371 { 2372 uint32_t v; 2373 uint16_t reg; 2374 struct sk_softc *sc; 2375 int i; 2376 2377 sc = sc_if->sk_softc; 2378 2379 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2380 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2381 2382 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2383 2384 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2385 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2386 2387 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2388 2389 /* unused read of the interrupt source register */ 2390 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2391 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2392 2393 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2394 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2395 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2396 2397 /* MIB Counter Clear Mode set */ 2398 reg |= YU_PAR_MIB_CLR; 2399 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2400 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2401 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2402 2403 /* MIB Counter Clear Mode clear */ 2404 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2405 reg &= ~YU_PAR_MIB_CLR; 2406 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2407 2408 /* receive control reg */ 2409 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2410 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2411 2412 /* transmit control register */ 2413 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2414 2415 /* transmit flow control register */ 2416 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2417 2418 /* transmit parameter register */ 2419 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2420 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2421 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2422 2423 /* serial mode register */ 2424 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2425 reg = YU_SMR_DATA_BLIND(0x1c) | 2426 YU_SMR_MFL_VLAN | 2427 YU_SMR_IPG_DATA(0x1e); 2428 2429 if (sc->sk_type != SK_YUKON_FE && 2430 sc->sk_type != SK_YUKON_FE_P) 2431 reg |= YU_SMR_MFL_JUMBO; 2432 2433 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2434 2435 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2436 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2437 /* msk_attach calls me before ether_ifattach so check null */ 2438 if (ifp != NULL && ifp->if_sadl != NULL) 2439 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2440 sizeof(sc_if->sk_enaddr)); 2441 /* Setup Yukon's address */ 2442 for (i = 0; i < 3; i++) { 2443 /* Write Source Address 1 (unicast filter) */ 2444 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2445 sc_if->sk_enaddr[i * 2] | 2446 sc_if->sk_enaddr[i * 2 + 1] << 8); 2447 } 2448 2449 for (i = 0; i < 3; i++) { 2450 reg = sk_win_read_2(sc_if->sk_softc, 2451 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2452 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2453 } 2454 2455 /* Set promiscuous mode */ 2456 msk_setpromisc(sc_if); 2457 2458 /* Set multicast filter */ 2459 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2460 msk_setmulti(sc_if); 2461 2462 /* enable interrupt mask for counter overflows */ 2463 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2464 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2465 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2466 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2467 2468 /* Configure RX MAC FIFO Flush Mask */ 2469 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2470 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2471 YU_RXSTAT_JABBER; 2472 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2473 2474 /* Configure RX MAC FIFO */ 2475 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2476 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2477 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2478 v |= SK_RFCTL_RX_OVER_ON; 2479 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2480 2481 if ((sc->sk_type == SK_YUKON_FE_P) && 2482 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2483 v = 0x178; /* Magic value */ 2484 else { 2485 /* Increase flush threshold to 64 bytes */ 2486 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2487 } 2488 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2489 2490 /* Configure TX MAC FIFO */ 2491 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2492 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2493 2494 if ((sc->sk_type == SK_YUKON_FE_P) && 2495 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2496 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2497 v &= ~SK_TXEND_WM_ON; 2498 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2499 } 2500 2501 #if 1 2502 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2503 #endif 2504 DPRINTFN(6, ("msk_init_yukon: end\n")); 2505 } 2506 2507 /* 2508 * Note that to properly initialize any part of the GEnesis chip, 2509 * you first have to take it out of reset mode. 2510 */ 2511 static int 2512 msk_init(struct ifnet *ifp) 2513 { 2514 struct sk_if_softc *sc_if = ifp->if_softc; 2515 struct sk_softc *sc = sc_if->sk_softc; 2516 int rc = 0, s; 2517 uint32_t imr, imtimer_ticks; 2518 2519 2520 DPRINTFN(2, ("msk_init\n")); 2521 2522 s = splnet(); 2523 2524 /* Cancel pending I/O and free all RX/TX buffers. */ 2525 msk_stop(ifp, 1); 2526 2527 /* Configure I2C registers */ 2528 2529 /* Configure XMAC(s) */ 2530 msk_init_yukon(sc_if); 2531 if ((rc = ether_mediachange(ifp)) != 0) 2532 goto out; 2533 2534 /* Configure transmit arbiter(s) */ 2535 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2536 #if 0 2537 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2538 #endif 2539 2540 if (sc->sk_ramsize) { 2541 /* Configure RAMbuffers */ 2542 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2543 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2544 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2545 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2546 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2547 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2548 2549 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2550 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2551 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2552 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2553 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2554 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2555 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2556 } 2557 2558 /* Configure BMUs */ 2559 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2560 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2561 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2562 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2563 2564 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2565 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2566 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2567 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2568 2569 /* Make sure the sync transmit queue is disabled. */ 2570 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2571 2572 /* Init descriptors */ 2573 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2574 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2575 "memory for rx buffers\n"); 2576 msk_stop(ifp, 1); 2577 splx(s); 2578 return ENOBUFS; 2579 } 2580 2581 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2582 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2583 "memory for tx buffers\n"); 2584 msk_stop(ifp, 1); 2585 splx(s); 2586 return ENOBUFS; 2587 } 2588 2589 /* Set interrupt moderation if changed via sysctl. */ 2590 switch (sc->sk_type) { 2591 case SK_YUKON_EC: 2592 case SK_YUKON_EC_U: 2593 case SK_YUKON_EX: 2594 case SK_YUKON_SUPR: 2595 case SK_YUKON_ULTRA2: 2596 case SK_YUKON_OPTIMA: 2597 case SK_YUKON_PRM: 2598 case SK_YUKON_OPTIMA2: 2599 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2600 break; 2601 case SK_YUKON_FE: 2602 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2603 break; 2604 case SK_YUKON_FE_P: 2605 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2606 break; 2607 case SK_YUKON_XL: 2608 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2609 break; 2610 default: 2611 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2612 } 2613 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2614 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2615 sk_win_write_4(sc, SK_IMTIMERINIT, 2616 SK_IM_USECS(sc->sk_int_mod)); 2617 aprint_verbose_dev(sc->sk_dev, 2618 "interrupt moderation is %d us\n", sc->sk_int_mod); 2619 } 2620 2621 /* Initialize prefetch engine. */ 2622 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2624 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2625 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2626 MSK_RX_RING_ADDR(sc_if, 0)); 2627 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2628 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2629 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2630 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2631 2632 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2633 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2634 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2635 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2636 MSK_TX_RING_ADDR(sc_if, 0)); 2637 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2638 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2639 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2640 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2641 2642 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2643 sc_if->sk_cdata.sk_rx_prod); 2644 2645 2646 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2647 /* Disable flushing of non-ASF packets. */ 2648 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2649 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2650 } 2651 2652 /* Configure interrupt handling */ 2653 if (sc_if->sk_port == SK_PORT_A) 2654 sc->sk_intrmask |= SK_Y2_INTRS1; 2655 else 2656 sc->sk_intrmask |= SK_Y2_INTRS2; 2657 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2658 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2659 2660 ifp->if_flags |= IFF_RUNNING; 2661 ifp->if_flags &= ~IFF_OACTIVE; 2662 2663 callout_schedule(&sc_if->sk_tick_ch, hz); 2664 2665 out: 2666 splx(s); 2667 return rc; 2668 } 2669 2670 /* 2671 * Note: the logic of second parameter is inverted compared to OpenBSD 2672 * code, since this code uses the function as if_stop hook too. 2673 */ 2674 static void 2675 msk_stop(struct ifnet *ifp, int disable) 2676 { 2677 struct sk_if_softc *sc_if = ifp->if_softc; 2678 struct sk_softc *sc = sc_if->sk_softc; 2679 bus_dmamap_t dmamap; 2680 int i; 2681 2682 DPRINTFN(2, ("msk_stop\n")); 2683 2684 callout_stop(&sc_if->sk_tick_ch); 2685 callout_stop(&sc_if->sk_tick_rx); 2686 2687 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2688 2689 /* Stop transfer of Tx descriptors */ 2690 2691 /* Stop transfer of Rx descriptors */ 2692 2693 if (disable) { 2694 /* Turn off various components of this interface. */ 2695 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2696 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2697 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2698 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2699 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2700 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2701 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2702 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2703 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2704 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2705 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2706 2707 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2708 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2709 2710 /* Disable interrupts */ 2711 if (sc_if->sk_port == SK_PORT_A) 2712 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2713 else 2714 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2715 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2716 } 2717 2718 /* Free RX and TX mbufs still in the queues. */ 2719 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2720 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2721 dmamap = sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap; 2722 2723 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2724 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2725 2726 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2727 2728 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2729 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2730 } 2731 } 2732 2733 sc_if->sk_cdata.sk_rx_prod = 0; 2734 sc_if->sk_cdata.sk_rx_cons = 0; 2735 sc_if->sk_cdata.sk_rx_cnt = 0; 2736 2737 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2738 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2739 dmamap = sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap; 2740 2741 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2742 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2743 2744 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2745 2746 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2747 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2748 } 2749 } 2750 } 2751 2752 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2753 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2754 2755 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2756 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2757 2758 #ifdef MSK_DEBUG 2759 static void 2760 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2761 { 2762 #define DESC_PRINT(X) \ 2763 if (X) \ 2764 printf("txdesc[%d]." #X "=%#x\n", \ 2765 idx, X); 2766 2767 DESC_PRINT(letoh32(le->sk_addr)); 2768 DESC_PRINT(letoh16(le->sk_len)); 2769 DESC_PRINT(le->sk_ctl); 2770 DESC_PRINT(le->sk_opcode); 2771 #undef DESC_PRINT 2772 } 2773 2774 static void 2775 msk_dump_bytes(const char *data, int len) 2776 { 2777 int c, i, j; 2778 2779 for (i = 0; i < len; i += 16) { 2780 printf("%08x ", i); 2781 c = len - i; 2782 if (c > 16) c = 16; 2783 2784 for (j = 0; j < c; j++) { 2785 printf("%02x ", data[i + j] & 0xff); 2786 if ((j & 0xf) == 7 && j > 0) 2787 printf(" "); 2788 } 2789 2790 for (; j < 16; j++) 2791 printf(" "); 2792 printf(" "); 2793 2794 for (j = 0; j < c; j++) { 2795 int ch = data[i + j] & 0xff; 2796 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2797 } 2798 2799 printf("\n"); 2800 2801 if (c < 16) 2802 break; 2803 } 2804 } 2805 2806 static void 2807 msk_dump_mbuf(struct mbuf *m) 2808 { 2809 int count = m->m_pkthdr.len; 2810 2811 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2812 2813 while (count > 0 && m) { 2814 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2815 m, m->m_data, m->m_len); 2816 if (mskdebug >= 4) 2817 msk_dump_bytes(mtod(m, char *), m->m_len); 2818 2819 count -= m->m_len; 2820 m = m->m_next; 2821 } 2822 } 2823 #endif 2824 2825 static int 2826 msk_sysctl_handler(SYSCTLFN_ARGS) 2827 { 2828 int error, t; 2829 struct sysctlnode node; 2830 struct sk_softc *sc; 2831 2832 node = *rnode; 2833 sc = node.sysctl_data; 2834 t = sc->sk_int_mod; 2835 node.sysctl_data = &t; 2836 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2837 if (error || newp == NULL) 2838 return error; 2839 2840 if (t < SK_IM_MIN || t > SK_IM_MAX) 2841 return EINVAL; 2842 2843 /* update the softc with sysctl-changed value, and mark 2844 for hardware update */ 2845 sc->sk_int_mod = t; 2846 sc->sk_int_mod_pending = 1; 2847 return 0; 2848 } 2849 2850 /* 2851 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2852 * set up in mskc_attach() 2853 */ 2854 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2855 { 2856 int rc; 2857 const struct sysctlnode *node; 2858 2859 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2860 0, CTLTYPE_NODE, "msk", 2861 SYSCTL_DESCR("msk interface controls"), 2862 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2863 goto err; 2864 } 2865 2866 msk_root_num = node->sysctl_num; 2867 return; 2868 2869 err: 2870 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2871 } 2872
Indexes created Wed Sep 24 15:09:51 GMT 2025