if_msk.c revision 1.109
1 /* $NetBSD: if_msk.c,v 1.109 2020/05/08 14:35:19 jakllsch Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.109 2020/05/08 14:35:19 jakllsch Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 le16toh 72 #define letoh32 le32toh 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/pci/if_skreg.h> 92 #include <dev/pci/if_mskvar.h> 93 94 static int mskc_probe(device_t, cfdata_t, void *); 95 static void mskc_attach(device_t, device_t, void *); 96 static int mskc_detach(device_t, int); 97 static void mskc_reset(struct sk_softc *); 98 static bool mskc_suspend(device_t, const pmf_qual_t *); 99 static bool mskc_resume(device_t, const pmf_qual_t *); 100 static int msk_probe(device_t, cfdata_t, void *); 101 static void msk_attach(device_t, device_t, void *); 102 static int msk_detach(device_t, int); 103 static void msk_reset(struct sk_if_softc *); 104 static int mskcprint(void *, const char *); 105 static int msk_intr(void *); 106 static void msk_intr_yukon(struct sk_if_softc *); 107 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t); 108 static void msk_txeof(struct sk_if_softc *); 109 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 110 static void msk_start(struct ifnet *); 111 static int msk_ioctl(struct ifnet *, u_long, void *); 112 static int msk_init(struct ifnet *); 113 static void msk_init_yukon(struct sk_if_softc *); 114 static void msk_stop(struct ifnet *, int); 115 static void msk_watchdog(struct ifnet *); 116 static int msk_newbuf(struct sk_if_softc *); 117 static int msk_alloc_jumbo_mem(struct sk_if_softc *); 118 static void *msk_jalloc(struct sk_if_softc *); 119 static void msk_jfree(struct mbuf *, void *, size_t, void *); 120 static int msk_init_rx_ring(struct sk_if_softc *); 121 static int msk_init_tx_ring(struct sk_if_softc *); 122 static void msk_fill_rx_ring(struct sk_if_softc *); 123 124 static void msk_update_int_mod(struct sk_softc *, int); 125 126 static int msk_miibus_readreg(device_t, int, int, uint16_t *); 127 static int msk_miibus_writereg(device_t, int, int, uint16_t); 128 static void msk_miibus_statchg(struct ifnet *); 129 130 static void msk_setmulti(struct sk_if_softc *); 131 static void msk_setpromisc(struct sk_if_softc *); 132 static void msk_tick(void *); 133 static void msk_fill_rx_tick(void *); 134 135 /* #define MSK_DEBUG 1 */ 136 #ifdef MSK_DEBUG 137 #define DPRINTF(x) if (mskdebug) printf x 138 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x 139 int mskdebug = MSK_DEBUG; 140 141 static void msk_dump_txdesc(struct msk_tx_desc *, int); 142 static void msk_dump_mbuf(struct mbuf *); 143 static void msk_dump_bytes(const char *, int); 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n, x) 147 #endif 148 149 static int msk_sysctl_handler(SYSCTLFN_PROTO); 150 static int msk_root_num; 151 152 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 153 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 199 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 201 { 0, 0 } 202 }; 203 204 static inline uint32_t 205 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 206 { 207 return CSR_READ_4(sc, reg); 208 } 209 210 static inline uint16_t 211 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 212 { 213 return CSR_READ_2(sc, reg); 214 } 215 216 static inline uint8_t 217 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 218 { 219 return CSR_READ_1(sc, reg); 220 } 221 222 static inline void 223 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 224 { 225 CSR_WRITE_4(sc, reg, x); 226 } 227 228 static inline void 229 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 230 { 231 CSR_WRITE_2(sc, reg, x); 232 } 233 234 static inline void 235 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 236 { 237 CSR_WRITE_1(sc, reg, x); 238 } 239 240 static int 241 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 242 { 243 struct sk_if_softc *sc_if = device_private(dev); 244 uint16_t data; 245 int i; 246 247 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 248 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 249 250 for (i = 0; i < SK_TIMEOUT; i++) { 251 DELAY(1); 252 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 253 if (data & YU_SMICR_READ_VALID) 254 break; 255 } 256 257 if (i == SK_TIMEOUT) { 258 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 259 return ETIMEDOUT; 260 } 261 262 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); 263 264 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 265 266 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 267 phy, reg, *val)); 268 269 return 0; 270 } 271 272 static int 273 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 274 { 275 struct sk_if_softc *sc_if = device_private(dev); 276 int i; 277 278 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n", 279 phy, reg, val)); 280 281 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 282 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 283 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 284 285 for (i = 0; i < SK_TIMEOUT; i++) { 286 DELAY(1); 287 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 288 break; 289 } 290 291 if (i == SK_TIMEOUT) { 292 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 293 return ETIMEDOUT; 294 } 295 296 return 0; 297 } 298 299 static void 300 msk_miibus_statchg(struct ifnet *ifp) 301 { 302 struct sk_if_softc *sc_if = ifp->if_softc; 303 struct mii_data *mii = &sc_if->sk_mii; 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 int gpcr; 306 307 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 308 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 309 310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 311 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 312 /* Set speed. */ 313 gpcr |= YU_GPCR_SPEED_DIS; 314 switch (IFM_SUBTYPE(mii->mii_media_active)) { 315 case IFM_1000_SX: 316 case IFM_1000_LX: 317 case IFM_1000_CX: 318 case IFM_1000_T: 319 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 320 break; 321 case IFM_100_TX: 322 gpcr |= YU_GPCR_SPEED; 323 break; 324 } 325 326 /* Set duplex. */ 327 gpcr |= YU_GPCR_DPLX_DIS; 328 if ((mii->mii_media_active & IFM_FDX) != 0) 329 gpcr |= YU_GPCR_DUPLEX; 330 331 /* Disable flow control. */ 332 gpcr |= YU_GPCR_FCTL_DIS; 333 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 334 } 335 336 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 337 338 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 339 SK_YU_READ_2(sc_if, YUKON_GPCR))); 340 } 341 342 static void 343 msk_setmulti(struct sk_if_softc *sc_if) 344 { 345 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 346 uint32_t hashes[2] = { 0, 0 }; 347 int h; 348 struct ethercom *ec = &sc_if->sk_ethercom; 349 struct ether_multi *enm; 350 struct ether_multistep step; 351 uint16_t reg; 352 353 /* First, zot all the existing filters. */ 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 357 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 358 359 360 /* Now program new ones. */ 361 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 362 reg |= YU_RCR_UFLEN; 363 allmulti: 364 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 365 if ((ifp->if_flags & IFF_PROMISC) != 0) 366 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 367 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 368 hashes[0] = 0xFFFFFFFF; 369 hashes[1] = 0xFFFFFFFF; 370 } 371 } else { 372 /* First find the tail of the list. */ 373 ETHER_LOCK(ec); 374 ETHER_FIRST_MULTI(step, ec, enm); 375 while (enm != NULL) { 376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 377 ETHER_ADDR_LEN)) { 378 ifp->if_flags |= IFF_ALLMULTI; 379 ETHER_UNLOCK(ec); 380 goto allmulti; 381 } 382 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 383 ((1 << SK_HASH_BITS) - 1); 384 if (h < 32) 385 hashes[0] |= (1 << h); 386 else 387 hashes[1] |= (1 << (h - 32)); 388 389 ETHER_NEXT_MULTI(step, enm); 390 } 391 ETHER_UNLOCK(ec); 392 reg |= YU_RCR_MUFLEN; 393 } 394 395 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 396 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 397 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 398 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 399 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 400 } 401 402 static void 403 msk_setpromisc(struct sk_if_softc *sc_if) 404 { 405 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 406 407 if (ifp->if_flags & IFF_PROMISC) 408 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 409 YU_RCR_UFLEN | YU_RCR_MUFLEN); 410 else 411 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 412 YU_RCR_UFLEN | YU_RCR_MUFLEN); 413 } 414 415 static int 416 msk_init_rx_ring(struct sk_if_softc *sc_if) 417 { 418 struct msk_chain_data *cd = &sc_if->sk_cdata; 419 struct msk_ring_data *rd = sc_if->sk_rdata; 420 struct msk_rx_desc *r; 421 422 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 423 424 sc_if->sk_cdata.sk_rx_prod = 0; 425 sc_if->sk_cdata.sk_rx_cons = 0; 426 sc_if->sk_cdata.sk_rx_cnt = 0; 427 sc_if->sk_cdata.sk_rx_hiaddr = 0; 428 429 /* Mark the first ring element to initialize the high address. */ 430 sc_if->sk_cdata.sk_rx_hiaddr = 0; 431 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 432 r->sk_addr = htole32(cd->sk_rx_hiaddr); 433 r->sk_len = 0; 434 r->sk_ctl = 0; 435 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 436 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 438 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 439 sc_if->sk_cdata.sk_rx_cnt++; 440 441 msk_fill_rx_ring(sc_if); 442 return 0; 443 } 444 445 static int 446 msk_init_tx_ring(struct sk_if_softc *sc_if) 447 { 448 struct msk_chain_data *cd = &sc_if->sk_cdata; 449 struct msk_ring_data *rd = sc_if->sk_rdata; 450 struct msk_tx_desc *t; 451 452 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 453 454 sc_if->sk_cdata.sk_tx_prod = 0; 455 sc_if->sk_cdata.sk_tx_cons = 0; 456 sc_if->sk_cdata.sk_tx_cnt = 0; 457 sc_if->sk_cdata.sk_tx_hiaddr = 0; 458 459 /* Mark the first ring element to initialize the high address. */ 460 sc_if->sk_cdata.sk_tx_hiaddr = 0; 461 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 462 t->sk_addr = htole32(cd->sk_tx_hiaddr); 463 t->sk_len = 0; 464 t->sk_ctl = 0; 465 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 466 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 468 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 469 sc_if->sk_cdata.sk_tx_cnt++; 470 471 return 0; 472 } 473 474 static int 475 msk_newbuf(struct sk_if_softc *sc_if) 476 { 477 struct sk_softc *sc = sc_if->sk_softc; 478 struct mbuf *m_new = NULL; 479 struct sk_chain *c; 480 struct msk_rx_desc *r; 481 void *buf = NULL; 482 bus_addr_t addr; 483 bus_dmamap_t rxmap; 484 size_t i; 485 uint32_t rxidx, frag, cur, hiaddr, total; 486 uint32_t entries = 0; 487 uint8_t own = 0; 488 489 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 490 if (m_new == NULL) 491 return ENOBUFS; 492 493 /* Allocate the jumbo buffer */ 494 buf = msk_jalloc(sc_if); 495 if (buf == NULL) { 496 m_freem(m_new); 497 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 498 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 499 return ENOBUFS; 500 } 501 502 /* Attach the buffer to the mbuf */ 503 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 504 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 505 506 m_adj(m_new, ETHER_ALIGN); 507 508 rxidx = frag = cur = sc_if->sk_cdata.sk_rx_prod; 509 rxmap = sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap; 510 511 if (bus_dmamap_load_mbuf(sc->sc_dmatag, rxmap, m_new, BUS_DMA_NOWAIT)) { 512 DPRINTFN(2, ("msk_newbuf: dmamap_load failed\n")); 513 m_freem(m_new); 514 return ENOBUFS; 515 } 516 517 /* Count how many rx descriptors needed. */ 518 hiaddr = sc_if->sk_cdata.sk_rx_hiaddr; 519 for (total = i = 0; i < rxmap->dm_nsegs; i++) { 520 if (hiaddr != MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr)) { 521 hiaddr = MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr); 522 total++; 523 } 524 total++; 525 } 526 527 if (total > MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt - 1) { 528 DPRINTFN(2, ("msk_newbuf: too few descriptors free\n")); 529 bus_dmamap_unload(sc->sc_dmatag, rxmap); 530 m_freem(m_new); 531 return ENOBUFS; 532 } 533 534 DPRINTFN(2, ("msk_newbuf: dm_nsegs=%d total desc=%u\n", 535 rxmap->dm_nsegs, total)); 536 537 /* Sync the DMA map. */ 538 bus_dmamap_sync(sc->sc_dmatag, rxmap, 0, rxmap->dm_mapsize, 539 BUS_DMASYNC_PREREAD); 540 541 for (i = 0; i < rxmap->dm_nsegs; i++) { 542 addr = rxmap->dm_segs[i].ds_addr; 543 DPRINTFN(2, ("msk_newbuf: addr %llx\n", 544 (unsigned long long)addr)); 545 hiaddr = MSK_ADDR_HI(addr); 546 547 if (sc_if->sk_cdata.sk_rx_hiaddr != hiaddr) { 548 c = &sc_if->sk_cdata.sk_rx_chain[frag]; 549 c->sk_mbuf = NULL; 550 r = &sc_if->sk_rdata->sk_rx_ring[frag]; 551 r->sk_addr = htole32(hiaddr); 552 r->sk_len = 0; 553 r->sk_ctl = 0; 554 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | own; 555 own = SK_Y2_RXOPC_OWN; 556 sc_if->sk_cdata.sk_rx_hiaddr = hiaddr; 557 MSK_CDRXSYNC(sc_if, frag, 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 SK_INC(frag, MSK_RX_RING_CNT); 560 entries++; 561 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 562 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 563 } 564 565 c = &sc_if->sk_cdata.sk_rx_chain[frag]; 566 r = &sc_if->sk_rdata->sk_rx_ring[frag]; 567 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 568 r->sk_len = htole16(rxmap->dm_segs[i].ds_len); 569 r->sk_ctl = 0; 570 if (i == 0) { 571 r->sk_opcode = SK_Y2_RXOPC_PACKET | own; 572 } else 573 r->sk_opcode = SK_Y2_RXOPC_BUFFER | own; 574 own = SK_Y2_RXOPC_OWN; 575 MSK_CDRXSYNC(sc_if, frag, 576 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 577 cur = frag; 578 SK_INC(frag, MSK_RX_RING_CNT); 579 entries++; 580 } 581 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 582 583 sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap = 584 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap; 585 sc_if->sk_cdata.sk_rx_chain[cur].sk_mbuf = m_new; 586 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap = rxmap; 587 588 sc_if->sk_rdata->sk_rx_ring[rxidx].sk_opcode |= SK_Y2_RXOPC_OWN; 589 MSK_CDRXSYNC(sc_if, rxidx, 590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 591 592 sc_if->sk_cdata.sk_rx_cnt += entries; 593 sc_if->sk_cdata.sk_rx_prod = frag; 594 595 return 0; 596 } 597 598 /* 599 * Memory management for jumbo frames. 600 */ 601 602 static int 603 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 604 { 605 struct sk_softc *sc = sc_if->sk_softc; 606 char *ptr, *kva; 607 int i, state, error; 608 struct sk_jpool_entry *entry; 609 610 state = error = 0; 611 612 /* Grab a big chunk o' storage. */ 613 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 614 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 615 BUS_DMA_NOWAIT)) { 616 aprint_error(": can't alloc rx buffers"); 617 return ENOBUFS; 618 } 619 620 state = 1; 621 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 622 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 623 BUS_DMA_NOWAIT)) { 624 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 625 error = ENOBUFS; 626 goto out; 627 } 628 629 state = 2; 630 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 631 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 632 aprint_error(": can't create dma map"); 633 error = ENOBUFS; 634 goto out; 635 } 636 637 state = 3; 638 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 639 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 640 aprint_error(": can't load dma map"); 641 error = ENOBUFS; 642 goto out; 643 } 644 645 state = 4; 646 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 647 DPRINTFN(1,("msk_jumbo_buf = %p\n", 648 (void *)sc_if->sk_cdata.sk_jumbo_buf)); 649 650 LIST_INIT(&sc_if->sk_jfree_listhead); 651 LIST_INIT(&sc_if->sk_jinuse_listhead); 652 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 653 654 /* 655 * Now divide it up into 9K pieces and save the addresses 656 * in an array. 657 */ 658 ptr = sc_if->sk_cdata.sk_jumbo_buf; 659 for (i = 0; i < MSK_JSLOTS; i++) { 660 sc_if->sk_cdata.sk_jslots[i] = ptr; 661 ptr += SK_JLEN; 662 entry = malloc(sizeof(struct sk_jpool_entry), 663 M_DEVBUF, M_WAITOK); 664 entry->slot = i; 665 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 666 entry, jpool_entries); 667 } 668 out: 669 if (error != 0) { 670 switch (state) { 671 case 4: 672 bus_dmamap_unload(sc->sc_dmatag, 673 sc_if->sk_cdata.sk_rx_jumbo_map); 674 /* FALLTHROUGH */ 675 case 3: 676 bus_dmamap_destroy(sc->sc_dmatag, 677 sc_if->sk_cdata.sk_rx_jumbo_map); 678 /* FALLTHROUGH */ 679 case 2: 680 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 681 /* FALLTHROUGH */ 682 case 1: 683 bus_dmamem_free(sc->sc_dmatag, 684 &sc_if->sk_cdata.sk_jumbo_seg, 685 sc_if->sk_cdata.sk_jumbo_nseg); 686 break; 687 default: 688 break; 689 } 690 } 691 692 return error; 693 } 694 695 static void 696 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 697 { 698 struct sk_softc *sc = sc_if->sk_softc; 699 700 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 701 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 702 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 703 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 704 sc_if->sk_cdata.sk_jumbo_nseg); 705 } 706 707 /* 708 * Allocate a jumbo buffer. 709 */ 710 static void * 711 msk_jalloc(struct sk_if_softc *sc_if) 712 { 713 struct sk_jpool_entry *entry; 714 715 mutex_enter(&sc_if->sk_jpool_mtx); 716 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 717 718 if (entry == NULL) { 719 mutex_exit(&sc_if->sk_jpool_mtx); 720 return NULL; 721 } 722 723 LIST_REMOVE(entry, jpool_entries); 724 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 725 mutex_exit(&sc_if->sk_jpool_mtx); 726 return sc_if->sk_cdata.sk_jslots[entry->slot]; 727 } 728 729 /* 730 * Release a jumbo buffer. 731 */ 732 static void 733 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 734 { 735 struct sk_jpool_entry *entry; 736 struct sk_if_softc *sc; 737 int i; 738 739 /* Extract the softc struct pointer. */ 740 sc = (struct sk_if_softc *)arg; 741 742 if (sc == NULL) 743 panic("msk_jfree: can't find softc pointer!"); 744 745 /* calculate the slot this buffer belongs to */ 746 i = ((vaddr_t)buf 747 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 748 749 if ((i < 0) || (i >= MSK_JSLOTS)) 750 panic("msk_jfree: asked to free buffer that we don't manage!"); 751 752 mutex_enter(&sc->sk_jpool_mtx); 753 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 754 if (entry == NULL) 755 panic("msk_jfree: buffer not in use!"); 756 entry->slot = i; 757 LIST_REMOVE(entry, jpool_entries); 758 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 759 mutex_exit(&sc->sk_jpool_mtx); 760 761 if (__predict_true(m != NULL)) 762 pool_cache_put(mb_cache, m); 763 764 /* Now that we know we have a free RX buffer, refill if running out */ 765 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 766 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 767 callout_schedule(&sc->sk_tick_rx, 0); 768 } 769 770 static int 771 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 772 { 773 struct sk_if_softc *sc = ifp->if_softc; 774 int s, error; 775 776 s = splnet(); 777 778 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 779 switch (cmd) { 780 case SIOCSIFFLAGS: 781 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 782 break; 783 784 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 785 case IFF_RUNNING: 786 msk_stop(ifp, 1); 787 break; 788 case IFF_UP: 789 msk_init(ifp); 790 break; 791 case IFF_UP | IFF_RUNNING: 792 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 793 msk_setpromisc(sc); 794 msk_setmulti(sc); 795 } else 796 msk_init(ifp); 797 break; 798 } 799 sc->sk_if_flags = ifp->if_flags; 800 break; 801 default: 802 error = ether_ioctl(ifp, cmd, data); 803 if (error == ENETRESET) { 804 error = 0; 805 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 806 ; 807 else if (ifp->if_flags & IFF_RUNNING) { 808 /* 809 * Multicast list has changed; set the hardware 810 * filter accordingly. 811 */ 812 msk_setmulti(sc); 813 } 814 } 815 break; 816 } 817 818 splx(s); 819 return error; 820 } 821 822 static void 823 msk_update_int_mod(struct sk_softc *sc, int verbose) 824 { 825 uint32_t imtimer_ticks; 826 827 /* 828 * Configure interrupt moderation. The moderation timer 829 * defers interrupts specified in the interrupt moderation 830 * timer mask based on the timeout specified in the interrupt 831 * moderation timer init register. Each bit in the timer 832 * register represents one tick, so to specify a timeout in 833 * microseconds, we have to multiply by the correct number of 834 * ticks-per-microsecond. 835 */ 836 switch (sc->sk_type) { 837 case SK_YUKON_EC: 838 case SK_YUKON_EC_U: 839 case SK_YUKON_EX: 840 case SK_YUKON_SUPR: 841 case SK_YUKON_ULTRA2: 842 case SK_YUKON_OPTIMA: 843 case SK_YUKON_PRM: 844 case SK_YUKON_OPTIMA2: 845 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 846 break; 847 case SK_YUKON_FE: 848 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 849 break; 850 case SK_YUKON_FE_P: 851 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 852 break; 853 case SK_YUKON_XL: 854 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 855 break; 856 default: 857 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 858 } 859 if (verbose) 860 aprint_verbose_dev(sc->sk_dev, 861 "interrupt moderation is %d us\n", sc->sk_int_mod); 862 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 863 sk_win_write_4(sc, SK_IMMR, SK_Y2_IMR_BMU); 864 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 865 sc->sk_int_mod_pending = 0; 866 } 867 868 static int 869 msk_lookup(const struct pci_attach_args *pa) 870 { 871 const struct msk_product *pmsk; 872 873 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 874 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 875 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 876 return 1; 877 } 878 return 0; 879 } 880 881 /* 882 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 883 * IDs against our list and return a device name if we find a match. 884 */ 885 static int 886 mskc_probe(device_t parent, cfdata_t match, void *aux) 887 { 888 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 889 890 return msk_lookup(pa); 891 } 892 893 /* 894 * Force the GEnesis into reset, then bring it out of reset. 895 */ 896 static void 897 mskc_reset(struct sk_softc *sc) 898 { 899 uint32_t imtimer_ticks, reg1; 900 uint16_t status; 901 int reg; 902 903 DPRINTFN(2, ("mskc_reset\n")); 904 905 /* Disable ASF */ 906 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 907 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 908 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR); 909 /* Clear AHB bridge & microcontroller reset. */ 910 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST | 911 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE); 912 /* Clear ASF microcontroller state. */ 913 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK; 914 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK; 915 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status); 916 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0); 917 } else 918 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 919 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 920 921 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 922 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 923 924 DELAY(1000); 925 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 926 DELAY(2); 927 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 928 sk_win_write_1(sc, SK_TESTCTL1, 2); 929 930 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 931 sc->sk_type >= SK_YUKON_FE_P) { 932 uint32_t our; 933 934 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 935 936 /* enable all clocks. */ 937 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 938 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 939 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST | 940 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN | 941 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY | 942 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 943 /* Set all bits to 0 except bits 15..12 */ 944 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 945 /* Set to default value */ 946 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 947 948 /* 949 * Disable status race, workaround for Yukon EC Ultra & 950 * Yukon EX. 951 */ 952 reg1 = sk_win_read_4(sc, SK_GPIO); 953 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 954 sk_win_write_4(sc, SK_GPIO, reg1); 955 sk_win_read_4(sc, SK_GPIO); 956 } 957 958 /* release PHY from PowerDown/Coma mode. */ 959 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 960 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 961 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 962 else 963 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 964 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 965 966 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 967 sk_win_write_1(sc, SK_Y2_CLKGATE, 968 SK_Y2_CLKGATE_LINK1_GATE_DIS | 969 SK_Y2_CLKGATE_LINK2_GATE_DIS | 970 SK_Y2_CLKGATE_LINK1_CORE_DIS | 971 SK_Y2_CLKGATE_LINK2_CORE_DIS | 972 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 973 else 974 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 975 976 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 977 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 978 DELAY(1000); 979 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 980 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 981 982 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 983 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 984 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 985 } 986 987 sk_win_write_1(sc, SK_TESTCTL1, 1); 988 989 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 990 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 991 CSR_READ_2(sc, SK_LINK_CTRL))); 992 993 /* Clear I2C IRQ noise */ 994 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 995 996 /* Disable hardware timer */ 997 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 998 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 999 1000 /* Disable descriptor polling */ 1001 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 1002 1003 /* Disable time stamps */ 1004 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 1005 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 1006 1007 /* Enable RAM interface */ 1008 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1009 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1010 sk_win_write_1(sc, reg, 36); 1011 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 1012 for (reg = SK_TO0;reg <= SK_TO11; reg++) 1013 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 1014 1015 /* 1016 * Configure interrupt moderation. The moderation timer 1017 * defers interrupts specified in the interrupt moderation 1018 * timer mask based on the timeout specified in the interrupt 1019 * moderation timer init register. Each bit in the timer 1020 * register represents one tick, so to specify a timeout in 1021 * microseconds, we have to multiply by the correct number of 1022 * ticks-per-microsecond. 1023 */ 1024 switch (sc->sk_type) { 1025 case SK_YUKON_EC: 1026 case SK_YUKON_EC_U: 1027 case SK_YUKON_EX: 1028 case SK_YUKON_SUPR: 1029 case SK_YUKON_ULTRA2: 1030 case SK_YUKON_OPTIMA: 1031 case SK_YUKON_PRM: 1032 case SK_YUKON_OPTIMA2: 1033 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1034 break; 1035 case SK_YUKON_FE: 1036 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1037 break; 1038 case SK_YUKON_FE_P: 1039 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1040 break; 1041 case SK_YUKON_XL: 1042 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1043 break; 1044 default: 1045 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1046 break; 1047 } 1048 1049 /* Reset status ring. */ 1050 memset(sc->sk_status_ring, 0, 1051 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1052 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1053 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1054 sc->sk_status_idx = 0; 1055 1056 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1057 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1058 1059 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1060 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1061 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr)); 1062 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1063 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr)); 1064 if (sc->sk_type == SK_YUKON_EC && 1065 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1066 /* WA for dev. #4.3 */ 1067 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 1068 SK_STAT_BMU_TXTHIDX_MSK); 1069 /* WA for dev. #4.18 */ 1070 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1071 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1072 } else { 1073 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1074 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1075 if (sc->sk_type == SK_YUKON_XL) 1076 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1077 else 1078 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1079 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1080 } 1081 1082 #if 0 1083 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1084 #endif 1085 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1086 1087 /* Enable status unit. */ 1088 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1089 1090 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1091 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1092 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1093 1094 msk_update_int_mod(sc, 0); 1095 } 1096 1097 static int 1098 msk_probe(device_t parent, cfdata_t match, void *aux) 1099 { 1100 struct skc_attach_args *sa = aux; 1101 1102 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1103 return 0; 1104 1105 switch (sa->skc_type) { 1106 case SK_YUKON_XL: 1107 case SK_YUKON_EC_U: 1108 case SK_YUKON_EX: 1109 case SK_YUKON_EC: 1110 case SK_YUKON_FE: 1111 case SK_YUKON_FE_P: 1112 case SK_YUKON_SUPR: 1113 case SK_YUKON_ULTRA2: 1114 case SK_YUKON_OPTIMA: 1115 case SK_YUKON_PRM: 1116 case SK_YUKON_OPTIMA2: 1117 return 1; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static void 1124 msk_reset(struct sk_if_softc *sc_if) 1125 { 1126 /* GMAC and GPHY Reset */ 1127 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1128 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1129 DELAY(1000); 1130 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1131 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1132 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1133 } 1134 1135 static bool 1136 msk_resume(device_t dv, const pmf_qual_t *qual) 1137 { 1138 struct sk_if_softc *sc_if = device_private(dv); 1139 1140 msk_init_yukon(sc_if); 1141 return true; 1142 } 1143 1144 /* 1145 * Each XMAC chip is attached as a separate logical IP interface. 1146 * Single port cards will have only one logical interface of course. 1147 */ 1148 static void 1149 msk_attach(device_t parent, device_t self, void *aux) 1150 { 1151 struct sk_if_softc *sc_if = device_private(self); 1152 struct sk_softc *sc = device_private(parent); 1153 struct skc_attach_args *sa = aux; 1154 bus_dmamap_t dmamap; 1155 struct ifnet *ifp; 1156 struct mii_data * const mii = &sc_if->sk_mii; 1157 void *kva; 1158 int i; 1159 uint32_t chunk; 1160 int mii_flags; 1161 1162 sc_if->sk_dev = self; 1163 sc_if->sk_port = sa->skc_port; 1164 sc_if->sk_softc = sc; 1165 sc->sk_if[sa->skc_port] = sc_if; 1166 1167 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1168 1169 /* 1170 * Get station address for this interface. Note that 1171 * dual port cards actually come with three station 1172 * addresses: one for each port, plus an extra. The 1173 * extra one is used by the SysKonnect driver software 1174 * as a 'virtual' station address for when both ports 1175 * are operating in failover mode. Currently we don't 1176 * use this extra address. 1177 */ 1178 for (i = 0; i < ETHER_ADDR_LEN; i++) 1179 sc_if->sk_enaddr[i] = 1180 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1181 1182 aprint_normal(": Ethernet address %s\n", 1183 ether_sprintf(sc_if->sk_enaddr)); 1184 1185 /* 1186 * Set up RAM buffer addresses. The Yukon2 has a small amount 1187 * of SRAM on it, somewhere between 4K and 48K. We need to 1188 * divide this up between the transmitter and receiver. We 1189 * give the receiver 2/3 of the memory (rounded down), and the 1190 * transmitter whatever remains. 1191 */ 1192 if (sc->sk_ramsize) { 1193 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff; 1194 sc_if->sk_rx_ramstart = 0; 1195 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1196 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk; 1197 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1198 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1199 1200 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1201 " tx_ramstart=%#x tx_ramend=%#x\n", 1202 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1203 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1204 } 1205 1206 /* Allocate the descriptor queues. */ 1207 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1208 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1209 BUS_DMA_NOWAIT)) { 1210 aprint_error(": can't alloc rx buffers\n"); 1211 goto fail; 1212 } 1213 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1214 sc_if->sk_ring_nseg, 1215 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1216 aprint_error(": can't map dma buffers (%zu bytes)\n", 1217 sizeof(struct msk_ring_data)); 1218 goto fail_1; 1219 } 1220 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1221 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1222 &sc_if->sk_ring_map)) { 1223 aprint_error(": can't create dma map\n"); 1224 goto fail_2; 1225 } 1226 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1227 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1228 aprint_error(": can't load dma map\n"); 1229 goto fail_3; 1230 } 1231 1232 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1233 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1234 1235 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1236 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1237 aprint_error_dev(sc_if->sk_dev, 1238 "Can't create TX dmamap\n"); 1239 goto fail_3; 1240 } 1241 1242 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap = dmamap; 1243 } 1244 1245 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1246 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1247 1248 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, 1249 howmany(SK_JLEN + 1, NBPG), 1250 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1251 aprint_error_dev(sc_if->sk_dev, 1252 "Can't create RX dmamap\n"); 1253 goto fail_3; 1254 } 1255 1256 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap = dmamap; 1257 } 1258 1259 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1260 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1261 1262 if (sc->sk_type != SK_YUKON_FE && 1263 sc->sk_type != SK_YUKON_FE_P) 1264 sc_if->sk_pktlen = SK_JLEN; 1265 else 1266 sc_if->sk_pktlen = MCLBYTES; 1267 1268 /* Try to allocate memory for jumbo buffers. */ 1269 if (msk_alloc_jumbo_mem(sc_if)) { 1270 aprint_error(": jumbo buffer allocation failed\n"); 1271 goto fail_3; 1272 } 1273 1274 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1275 if (sc->sk_type != SK_YUKON_FE && 1276 sc->sk_type != SK_YUKON_FE_P) 1277 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1278 1279 ifp = &sc_if->sk_ethercom.ec_if; 1280 ifp->if_softc = sc_if; 1281 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1282 ifp->if_ioctl = msk_ioctl; 1283 ifp->if_start = msk_start; 1284 ifp->if_stop = msk_stop; 1285 ifp->if_init = msk_init; 1286 ifp->if_watchdog = msk_watchdog; 1287 ifp->if_baudrate = 1000000000; 1288 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1289 IFQ_SET_READY(&ifp->if_snd); 1290 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1291 1292 msk_reset(sc_if); 1293 1294 /* 1295 * Do miibus setup. 1296 */ 1297 DPRINTFN(2, ("msk_attach: 1\n")); 1298 1299 mii->mii_ifp = ifp; 1300 mii->mii_readreg = msk_miibus_readreg; 1301 mii->mii_writereg = msk_miibus_writereg; 1302 mii->mii_statchg = msk_miibus_statchg; 1303 1304 sc_if->sk_ethercom.ec_mii = mii; 1305 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1306 mii_flags = MIIF_DOPAUSE; 1307 if (sc->sk_fibertype) 1308 mii_flags |= MIIF_HAVEFIBER; 1309 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags); 1310 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1311 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1312 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 1313 0, NULL); 1314 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1315 } else 1316 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1317 1318 callout_init(&sc_if->sk_tick_ch, 0); 1319 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1320 callout_schedule(&sc_if->sk_tick_ch, hz); 1321 1322 callout_init(&sc_if->sk_tick_rx, 0); 1323 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1324 1325 /* 1326 * Call MI attach routines. 1327 */ 1328 if_attach(ifp); 1329 if_deferred_start_init(ifp, NULL); 1330 ether_ifattach(ifp, sc_if->sk_enaddr); 1331 1332 if (pmf_device_register(self, NULL, msk_resume)) 1333 pmf_class_network_register(self, ifp); 1334 else 1335 aprint_error_dev(self, "couldn't establish power handler\n"); 1336 1337 if (sc->rnd_attached++ == 0) { 1338 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1339 RND_TYPE_NET, RND_FLAG_DEFAULT); 1340 } 1341 1342 DPRINTFN(2, ("msk_attach: end\n")); 1343 return; 1344 1345 fail_3: 1346 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1347 fail_2: 1348 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1349 fail_1: 1350 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1351 fail: 1352 sc->sk_if[sa->skc_port] = NULL; 1353 } 1354 1355 static int 1356 msk_detach(device_t self, int flags) 1357 { 1358 struct sk_if_softc *sc_if = device_private(self); 1359 struct sk_softc *sc = sc_if->sk_softc; 1360 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1361 int i; 1362 1363 if (sc->sk_if[sc_if->sk_port] == NULL) 1364 return 0; 1365 1366 msk_stop(ifp, 1); 1367 1368 for (i = 0; i < MSK_TX_RING_CNT; i++) { 1369 bus_dmamap_destroy(sc->sc_dmatag, 1370 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap); 1371 } 1372 1373 for (i = 0; i < MSK_RX_RING_CNT; i++) { 1374 bus_dmamap_destroy(sc->sc_dmatag, 1375 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap); 1376 } 1377 1378 if (--sc->rnd_attached == 0) 1379 rnd_detach_source(&sc->rnd_source); 1380 1381 callout_halt(&sc_if->sk_tick_ch, NULL); 1382 callout_destroy(&sc_if->sk_tick_ch); 1383 1384 callout_halt(&sc_if->sk_tick_rx, NULL); 1385 callout_destroy(&sc_if->sk_tick_rx); 1386 1387 /* Detach any PHYs we might have. */ 1388 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1389 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1390 1391 pmf_device_deregister(self); 1392 1393 ether_ifdetach(ifp); 1394 if_detach(ifp); 1395 1396 /* Delete any remaining media. */ 1397 ifmedia_fini(&sc_if->sk_mii.mii_media); 1398 1399 msk_free_jumbo_mem(sc_if); 1400 1401 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1402 sizeof(struct msk_ring_data)); 1403 bus_dmamem_free(sc->sc_dmatag, 1404 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1405 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1406 sc->sk_if[sc_if->sk_port] = NULL; 1407 1408 return 0; 1409 } 1410 1411 static int 1412 mskcprint(void *aux, const char *pnp) 1413 { 1414 struct skc_attach_args *sa = aux; 1415 1416 if (pnp) 1417 aprint_normal("msk port %c at %s", 1418 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1419 else 1420 aprint_normal(" port %c", 1421 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1422 return UNCONF; 1423 } 1424 1425 /* 1426 * Attach the interface. Allocate softc structures, do ifmedia 1427 * setup and ethernet/BPF attach. 1428 */ 1429 static void 1430 mskc_attach(device_t parent, device_t self, void *aux) 1431 { 1432 struct sk_softc *sc = device_private(self); 1433 struct pci_attach_args *pa = aux; 1434 struct skc_attach_args skca; 1435 pci_chipset_tag_t pc = pa->pa_pc; 1436 pcireg_t command, memtype; 1437 const char *intrstr = NULL; 1438 int rc, sk_nodenum; 1439 uint8_t hw, pmd; 1440 const char *revstr = NULL; 1441 const struct sysctlnode *node; 1442 void *kva; 1443 char intrbuf[PCI_INTRSTR_LEN]; 1444 1445 DPRINTFN(2, ("begin mskc_attach\n")); 1446 1447 sc->sk_dev = self; 1448 /* 1449 * Handle power management nonsense. 1450 */ 1451 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1452 1453 if (command == 0x01) { 1454 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1455 if (command & SK_PSTATE_MASK) { 1456 uint32_t iobase, membase, irq; 1457 1458 /* Save important PCI config data. */ 1459 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1460 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1461 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1462 1463 /* Reset the power state. */ 1464 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1465 "mode -- setting to D0\n", 1466 command & SK_PSTATE_MASK); 1467 command &= 0xFFFFFFFC; 1468 pci_conf_write(pc, pa->pa_tag, 1469 SK_PCI_PWRMGMTCTRL, command); 1470 1471 /* Restore PCI config data. */ 1472 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1473 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1474 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1475 } 1476 } 1477 1478 /* 1479 * Map control/status registers. 1480 */ 1481 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1482 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1483 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1484 aprint_error(": can't map mem space\n"); 1485 return; 1486 } 1487 1488 if (pci_dma64_available(pa)) 1489 sc->sc_dmatag = pa->pa_dmat64; 1490 else 1491 sc->sc_dmatag = pa->pa_dmat; 1492 1493 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1494 command |= PCI_COMMAND_MASTER_ENABLE; 1495 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1496 1497 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1498 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1499 1500 /* bail out here if chip is not recognized */ 1501 if (!(SK_IS_YUKON2(sc))) { 1502 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1503 goto fail_1; 1504 } 1505 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1506 1507 /* Allocate interrupt */ 1508 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) { 1509 aprint_error(": couldn't map interrupt\n"); 1510 goto fail_1; 1511 } 1512 1513 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf)); 1514 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET, 1515 msk_intr, sc, device_xname(sc->sk_dev)); 1516 if (sc->sk_intrhand == NULL) { 1517 aprint_error(": couldn't establish interrupt"); 1518 if (intrstr != NULL) 1519 aprint_error(" at %s", intrstr); 1520 aprint_error("\n"); 1521 goto fail_1; 1522 } 1523 sc->sk_pc = pc; 1524 1525 if (bus_dmamem_alloc(sc->sc_dmatag, 1526 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1527 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1528 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1529 aprint_error(": can't alloc status buffers\n"); 1530 goto fail_2; 1531 } 1532 1533 if (bus_dmamem_map(sc->sc_dmatag, 1534 &sc->sk_status_seg, sc->sk_status_nseg, 1535 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1536 &kva, BUS_DMA_NOWAIT)) { 1537 aprint_error(": can't map dma buffers (%zu bytes)\n", 1538 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1539 goto fail_3; 1540 } 1541 if (bus_dmamap_create(sc->sc_dmatag, 1542 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1543 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1544 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1545 aprint_error(": can't create dma map\n"); 1546 goto fail_4; 1547 } 1548 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1549 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1550 NULL, BUS_DMA_NOWAIT)) { 1551 aprint_error(": can't load dma map\n"); 1552 goto fail_5; 1553 } 1554 sc->sk_status_ring = (struct msk_status_desc *)kva; 1555 1556 sc->sk_int_mod = SK_IM_DEFAULT; 1557 sc->sk_int_mod_pending = 0; 1558 1559 /* Reset the adapter. */ 1560 mskc_reset(sc); 1561 1562 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1563 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1564 1565 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1566 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1567 sc->sk_fibertype = 1; 1568 1569 switch (sc->sk_type) { 1570 case SK_YUKON_XL: 1571 sc->sk_name = "Yukon-2 XL"; 1572 break; 1573 case SK_YUKON_EC_U: 1574 sc->sk_name = "Yukon-2 EC Ultra"; 1575 break; 1576 case SK_YUKON_EX: 1577 sc->sk_name = "Yukon-2 Extreme"; 1578 break; 1579 case SK_YUKON_EC: 1580 sc->sk_name = "Yukon-2 EC"; 1581 break; 1582 case SK_YUKON_FE: 1583 sc->sk_name = "Yukon-2 FE"; 1584 break; 1585 case SK_YUKON_FE_P: 1586 sc->sk_name = "Yukon-2 FE+"; 1587 break; 1588 case SK_YUKON_SUPR: 1589 sc->sk_name = "Yukon-2 Supreme"; 1590 break; 1591 case SK_YUKON_ULTRA2: 1592 sc->sk_name = "Yukon-2 Ultra 2"; 1593 break; 1594 case SK_YUKON_OPTIMA: 1595 sc->sk_name = "Yukon-2 Optima"; 1596 break; 1597 case SK_YUKON_PRM: 1598 sc->sk_name = "Yukon-2 Optima Prime"; 1599 break; 1600 case SK_YUKON_OPTIMA2: 1601 sc->sk_name = "Yukon-2 Optima 2"; 1602 break; 1603 default: 1604 sc->sk_name = "Yukon (Unknown)"; 1605 } 1606 1607 if (sc->sk_type == SK_YUKON_XL) { 1608 switch (sc->sk_rev) { 1609 case SK_YUKON_XL_REV_A0: 1610 revstr = "A0"; 1611 break; 1612 case SK_YUKON_XL_REV_A1: 1613 revstr = "A1"; 1614 break; 1615 case SK_YUKON_XL_REV_A2: 1616 revstr = "A2"; 1617 break; 1618 case SK_YUKON_XL_REV_A3: 1619 revstr = "A3"; 1620 break; 1621 default: 1622 break; 1623 } 1624 } 1625 1626 if (sc->sk_type == SK_YUKON_EC) { 1627 switch (sc->sk_rev) { 1628 case SK_YUKON_EC_REV_A1: 1629 revstr = "A1"; 1630 break; 1631 case SK_YUKON_EC_REV_A2: 1632 revstr = "A2"; 1633 break; 1634 case SK_YUKON_EC_REV_A3: 1635 revstr = "A3"; 1636 break; 1637 default: 1638 break; 1639 } 1640 } 1641 1642 if (sc->sk_type == SK_YUKON_FE) { 1643 switch (sc->sk_rev) { 1644 case SK_YUKON_FE_REV_A1: 1645 revstr = "A1"; 1646 break; 1647 case SK_YUKON_FE_REV_A2: 1648 revstr = "A2"; 1649 break; 1650 default: 1651 break; 1652 } 1653 } 1654 1655 if (sc->sk_type == SK_YUKON_EC_U) { 1656 switch (sc->sk_rev) { 1657 case SK_YUKON_EC_U_REV_A0: 1658 revstr = "A0"; 1659 break; 1660 case SK_YUKON_EC_U_REV_A1: 1661 revstr = "A1"; 1662 break; 1663 case SK_YUKON_EC_U_REV_B0: 1664 revstr = "B0"; 1665 break; 1666 case SK_YUKON_EC_U_REV_B1: 1667 revstr = "B1"; 1668 break; 1669 default: 1670 break; 1671 } 1672 } 1673 1674 if (sc->sk_type == SK_YUKON_FE) { 1675 switch (sc->sk_rev) { 1676 case SK_YUKON_FE_REV_A1: 1677 revstr = "A1"; 1678 break; 1679 case SK_YUKON_FE_REV_A2: 1680 revstr = "A2"; 1681 break; 1682 default: 1683 ; 1684 } 1685 } 1686 1687 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1688 revstr = "A0"; 1689 1690 if (sc->sk_type == SK_YUKON_EX) { 1691 switch (sc->sk_rev) { 1692 case SK_YUKON_EX_REV_A0: 1693 revstr = "A0"; 1694 break; 1695 case SK_YUKON_EX_REV_B0: 1696 revstr = "B0"; 1697 break; 1698 default: 1699 ; 1700 } 1701 } 1702 1703 if (sc->sk_type == SK_YUKON_SUPR) { 1704 switch (sc->sk_rev) { 1705 case SK_YUKON_SUPR_REV_A0: 1706 revstr = "A0"; 1707 break; 1708 case SK_YUKON_SUPR_REV_B0: 1709 revstr = "B0"; 1710 break; 1711 case SK_YUKON_SUPR_REV_B1: 1712 revstr = "B1"; 1713 break; 1714 default: 1715 ; 1716 } 1717 } 1718 1719 if (sc->sk_type == SK_YUKON_PRM) { 1720 switch (sc->sk_rev) { 1721 case SK_YUKON_PRM_REV_Z1: 1722 revstr = "Z1"; 1723 break; 1724 case SK_YUKON_PRM_REV_A0: 1725 revstr = "A0"; 1726 break; 1727 default: 1728 ; 1729 } 1730 } 1731 1732 /* Announce the product name. */ 1733 aprint_normal(", %s", sc->sk_name); 1734 if (revstr != NULL) 1735 aprint_normal(" rev. %s", revstr); 1736 aprint_normal(" (0x%x)\n", sc->sk_rev); 1737 1738 aprint_normal_dev(sc->sk_dev, "interrupting at %s\n", intrstr); 1739 1740 sc->sk_macs = 1; 1741 1742 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1743 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1744 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1745 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1746 sc->sk_macs++; 1747 } 1748 1749 skca.skc_port = SK_PORT_A; 1750 skca.skc_type = sc->sk_type; 1751 skca.skc_rev = sc->sk_rev; 1752 (void)config_found(sc->sk_dev, &skca, mskcprint); 1753 1754 if (sc->sk_macs > 1) { 1755 skca.skc_port = SK_PORT_B; 1756 skca.skc_type = sc->sk_type; 1757 skca.skc_rev = sc->sk_rev; 1758 (void)config_found(sc->sk_dev, &skca, mskcprint); 1759 } 1760 1761 /* Turn on the 'driver is loaded' LED. */ 1762 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1763 1764 /* skc sysctl setup */ 1765 1766 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1767 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1768 SYSCTL_DESCR("mskc per-controller controls"), 1769 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1770 CTL_EOL)) != 0) { 1771 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1772 goto fail_6; 1773 } 1774 1775 sk_nodenum = node->sysctl_num; 1776 1777 /* interrupt moderation time in usecs */ 1778 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1779 CTLFLAG_READWRITE, 1780 CTLTYPE_INT, "int_mod", 1781 SYSCTL_DESCR("msk interrupt moderation timer"), 1782 msk_sysctl_handler, 0, (void *)sc, 1783 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1784 CTL_EOL)) != 0) { 1785 aprint_normal_dev(sc->sk_dev, 1786 "couldn't create int_mod sysctl node\n"); 1787 goto fail_6; 1788 } 1789 1790 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1791 aprint_error_dev(self, "couldn't establish power handler\n"); 1792 1793 return; 1794 1795 fail_6: 1796 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1797 fail_4: 1798 bus_dmamem_unmap(sc->sc_dmatag, kva, 1799 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1800 fail_3: 1801 bus_dmamem_free(sc->sc_dmatag, 1802 &sc->sk_status_seg, sc->sk_status_nseg); 1803 sc->sk_status_nseg = 0; 1804 fail_5: 1805 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1806 fail_2: 1807 pci_intr_disestablish(pc, sc->sk_intrhand); 1808 sc->sk_intrhand = NULL; 1809 fail_1: 1810 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1811 sc->sk_bsize = 0; 1812 } 1813 1814 static int 1815 mskc_detach(device_t self, int flags) 1816 { 1817 struct sk_softc *sc = device_private(self); 1818 int rv; 1819 1820 if (sc->sk_intrhand) { 1821 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1822 sc->sk_intrhand = NULL; 1823 } 1824 1825 if (sc->sk_pihp != NULL) { 1826 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1); 1827 sc->sk_pihp = NULL; 1828 } 1829 1830 rv = config_detach_children(self, flags); 1831 if (rv != 0) 1832 return rv; 1833 1834 if (sc->sk_status_nseg > 0) { 1835 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1836 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1837 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1838 bus_dmamem_free(sc->sc_dmatag, 1839 &sc->sk_status_seg, sc->sk_status_nseg); 1840 } 1841 1842 if (sc->sk_bsize > 0) 1843 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1844 1845 return 0; 1846 } 1847 1848 static int 1849 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1850 { 1851 struct sk_softc *sc = sc_if->sk_softc; 1852 struct msk_tx_desc *f = NULL; 1853 uint32_t frag, cur, hiaddr, total; 1854 uint32_t entries = 0; 1855 uint8_t own = 0; 1856 size_t i; 1857 bus_dmamap_t txmap; 1858 bus_addr_t addr; 1859 1860 DPRINTFN(2, ("msk_encap\n")); 1861 1862 txmap = sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap; 1863 1864 cur = frag = *txidx; 1865 1866 #ifdef MSK_DEBUG 1867 if (mskdebug >= 2) 1868 msk_dump_mbuf(m_head); 1869 #endif 1870 1871 /* 1872 * Start packing the mbufs in this chain into 1873 * the fragment pointers. Stop when we run out 1874 * of fragments or hit the end of the mbuf chain. 1875 */ 1876 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1877 BUS_DMA_NOWAIT)) { 1878 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1879 return ENOBUFS; 1880 } 1881 1882 /* Count how many tx descriptors needed. */ 1883 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1884 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1885 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1886 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1887 total++; 1888 } 1889 total++; 1890 } 1891 1892 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1893 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1894 bus_dmamap_unload(sc->sc_dmatag, txmap); 1895 return ENOBUFS; 1896 } 1897 1898 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1899 txmap->dm_nsegs, total)); 1900 1901 /* Sync the DMA map. */ 1902 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1903 BUS_DMASYNC_PREWRITE); 1904 1905 for (i = 0; i < txmap->dm_nsegs; i++) { 1906 addr = txmap->dm_segs[i].ds_addr; 1907 DPRINTFN(2, ("msk_encap: addr %llx\n", 1908 (unsigned long long)addr)); 1909 hiaddr = MSK_ADDR_HI(addr); 1910 1911 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1912 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1913 f->sk_addr = htole32(hiaddr); 1914 f->sk_len = 0; 1915 f->sk_ctl = 0; 1916 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | own; 1917 own = SK_Y2_TXOPC_OWN; 1918 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1919 SK_INC(frag, MSK_TX_RING_CNT); 1920 entries++; 1921 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1922 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1923 } 1924 1925 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1926 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1927 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1928 f->sk_ctl = 0; 1929 if (i == 0) { 1930 f->sk_opcode = SK_Y2_TXOPC_PACKET | own; 1931 } else 1932 f->sk_opcode = SK_Y2_TXOPC_BUFFER | own; 1933 own = SK_Y2_TXOPC_OWN; 1934 cur = frag; 1935 SK_INC(frag, MSK_TX_RING_CNT); 1936 entries++; 1937 } 1938 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1939 1940 sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap = 1941 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap; 1942 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1943 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap = txmap; 1944 1945 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1946 1947 /* Sync descriptors before handing to chip */ 1948 MSK_CDTXSYNC(sc_if, *txidx, entries, 1949 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1950 1951 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1952 1953 /* Sync first descriptor to hand it off */ 1954 MSK_CDTXSYNC(sc_if, *txidx, 1, 1955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1956 1957 sc_if->sk_cdata.sk_tx_cnt += entries; 1958 1959 #ifdef MSK_DEBUG 1960 if (mskdebug >= 2) { 1961 struct msk_tx_desc *le; 1962 uint32_t idx; 1963 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1964 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1965 msk_dump_txdesc(le, idx); 1966 } 1967 } 1968 #endif 1969 1970 *txidx = frag; 1971 1972 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries)); 1973 1974 return 0; 1975 } 1976 1977 static void 1978 msk_start(struct ifnet *ifp) 1979 { 1980 struct sk_if_softc *sc_if = ifp->if_softc; 1981 struct mbuf *m_head = NULL; 1982 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1983 int pkts = 0; 1984 1985 DPRINTFN(2, ("msk_start\n")); 1986 1987 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1988 IFQ_POLL(&ifp->if_snd, m_head); 1989 if (m_head == NULL) 1990 break; 1991 1992 /* 1993 * Pack the data into the transmit ring. If we 1994 * don't have room, set the OACTIVE flag and wait 1995 * for the NIC to drain the ring. 1996 */ 1997 if (msk_encap(sc_if, m_head, &idx)) { 1998 ifp->if_flags |= IFF_OACTIVE; 1999 break; 2000 } 2001 2002 /* now we are committed to transmit the packet */ 2003 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2004 pkts++; 2005 2006 /* 2007 * If there's a BPF listener, bounce a copy of this frame 2008 * to him. 2009 */ 2010 bpf_mtap(ifp, m_head, BPF_D_OUT); 2011 } 2012 if (pkts == 0) 2013 return; 2014 2015 /* Transmit */ 2016 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2017 sc_if->sk_cdata.sk_tx_prod = idx; 2018 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 2019 2020 /* Set a timeout in case the chip goes out to lunch. */ 2021 ifp->if_timer = 5; 2022 } 2023 } 2024 2025 static void 2026 msk_watchdog(struct ifnet *ifp) 2027 { 2028 struct sk_if_softc *sc_if = ifp->if_softc; 2029 2030 /* 2031 * Reclaim first as there is a possibility of losing Tx completion 2032 * interrupts. 2033 */ 2034 msk_txeof(sc_if); 2035 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2036 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2037 2038 if_statinc(ifp, if_oerrors); 2039 2040 /* XXX Resets both ports; we shouldn't do that. */ 2041 mskc_reset(sc_if->sk_softc); 2042 msk_reset(sc_if); 2043 msk_init(ifp); 2044 } 2045 } 2046 2047 static bool 2048 mskc_suspend(device_t dv, const pmf_qual_t *qual) 2049 { 2050 struct sk_softc *sc = device_private(dv); 2051 2052 DPRINTFN(2, ("mskc_suspend\n")); 2053 2054 /* Turn off the 'driver is loaded' LED. */ 2055 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2056 2057 return true; 2058 } 2059 2060 static bool 2061 mskc_resume(device_t dv, const pmf_qual_t *qual) 2062 { 2063 struct sk_softc *sc = device_private(dv); 2064 2065 DPRINTFN(2, ("mskc_resume\n")); 2066 2067 mskc_reset(sc); 2068 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2069 2070 return true; 2071 } 2072 2073 static __inline int 2074 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 2075 { 2076 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2077 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2078 YU_RXSTAT_JABBER)) != 0 || 2079 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2080 YU_RXSTAT_BYTES(stat) != len) 2081 return 0; 2082 2083 return 1; 2084 } 2085 2086 static void 2087 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat) 2088 { 2089 struct sk_softc *sc = sc_if->sk_softc; 2090 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2091 struct mbuf *m; 2092 unsigned cur, prod, tail, total_len = len; 2093 bus_dmamap_t dmamap; 2094 2095 cur = sc_if->sk_cdata.sk_rx_cons; 2096 prod = sc_if->sk_cdata.sk_rx_prod; 2097 2098 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, 2099 sc_if->sk_cdata.sk_rx_cnt)); 2100 2101 while (prod != cur) { 2102 MSK_CDRXSYNC(sc_if, cur, 2103 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2104 2105 tail = cur; 2106 SK_INC(cur, MSK_RX_RING_CNT); 2107 2108 sc_if->sk_cdata.sk_rx_cnt--; 2109 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2110 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2111 if (m != NULL) 2112 break; /* found it */ 2113 } 2114 sc_if->sk_cdata.sk_rx_cons = cur; 2115 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, 2116 sc_if->sk_cdata.sk_rx_cnt, m)); 2117 2118 if (m == NULL) 2119 return; 2120 2121 dmamap = sc_if->sk_cdata.sk_rx_chain[tail].sk_dmamap; 2122 2123 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2124 uimin(dmamap->dm_mapsize, total_len), BUS_DMASYNC_POSTREAD); 2125 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2126 2127 if (total_len < SK_MIN_FRAMELEN || 2128 total_len > ETHER_MAX_LEN_JUMBO || 2129 msk_rxvalid(sc, rxstat, total_len) == 0) { 2130 if_statinc(ifp, if_ierrors); 2131 m_freem(m); 2132 return; 2133 } 2134 2135 m_set_rcvif(m, ifp); 2136 m->m_pkthdr.len = m->m_len = total_len; 2137 2138 /* pass it on. */ 2139 if_percpuq_enqueue(ifp->if_percpuq, m); 2140 } 2141 2142 static void 2143 msk_txeof(struct sk_if_softc *sc_if) 2144 { 2145 struct sk_softc *sc = sc_if->sk_softc; 2146 struct msk_tx_desc *cur_tx; 2147 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2148 uint32_t idx, reg, sk_ctl; 2149 bus_dmamap_t dmamap; 2150 2151 DPRINTFN(2, ("msk_txeof\n")); 2152 2153 if (sc_if->sk_port == SK_PORT_A) 2154 reg = SK_STAT_BMU_TXA1_RIDX; 2155 else 2156 reg = SK_STAT_BMU_TXA2_RIDX; 2157 2158 /* 2159 * Go through our tx ring and free mbufs for those 2160 * frames that have been sent. 2161 */ 2162 idx = sc_if->sk_cdata.sk_tx_cons; 2163 while (idx != sk_win_read_2(sc, reg)) { 2164 MSK_CDTXSYNC(sc_if, idx, 1, 2165 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2166 2167 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2168 sk_ctl = cur_tx->sk_ctl; 2169 #ifdef MSK_DEBUG 2170 if (mskdebug >= 2) 2171 msk_dump_txdesc(cur_tx, idx); 2172 #endif 2173 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2174 if_statinc(ifp, if_opackets); 2175 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2176 dmamap = sc_if->sk_cdata.sk_tx_chain[idx].sk_dmamap; 2177 2178 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2179 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2180 2181 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2182 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2183 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2184 } 2185 sc_if->sk_cdata.sk_tx_cnt--; 2186 SK_INC(idx, MSK_TX_RING_CNT); 2187 } 2188 if (idx == sc_if->sk_cdata.sk_tx_cons) 2189 return; 2190 2191 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2192 2193 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2194 ifp->if_flags &= ~IFF_OACTIVE; 2195 2196 sc_if->sk_cdata.sk_tx_cons = idx; 2197 } 2198 2199 static void 2200 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2201 { 2202 /* Make sure to not completely wrap around */ 2203 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2204 if (msk_newbuf(sc_if) == ENOBUFS) { 2205 goto schedretry; 2206 } 2207 } 2208 2209 return; 2210 2211 schedretry: 2212 /* Try later */ 2213 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2214 } 2215 2216 static void 2217 msk_fill_rx_tick(void *xsc_if) 2218 { 2219 struct sk_if_softc *sc_if = xsc_if; 2220 int s, rx_prod; 2221 2222 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2223 2224 s = splnet(); 2225 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2226 msk_fill_rx_ring(sc_if); 2227 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2228 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2229 sc_if->sk_cdata.sk_rx_prod); 2230 } 2231 splx(s); 2232 } 2233 2234 static void 2235 msk_tick(void *xsc_if) 2236 { 2237 struct sk_if_softc *sc_if = xsc_if; 2238 struct mii_data *mii = &sc_if->sk_mii; 2239 int s; 2240 2241 s = splnet(); 2242 mii_tick(mii); 2243 splx(s); 2244 2245 callout_schedule(&sc_if->sk_tick_ch, hz); 2246 } 2247 2248 static void 2249 msk_intr_yukon(struct sk_if_softc *sc_if) 2250 { 2251 uint8_t status; 2252 2253 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2254 /* RX overrun */ 2255 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2256 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2257 SK_RFCTL_RX_FIFO_OVER); 2258 } 2259 /* TX underrun */ 2260 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2261 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2262 SK_TFCTL_TX_FIFO_UNDER); 2263 } 2264 2265 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2266 } 2267 2268 static int 2269 msk_intr(void *xsc) 2270 { 2271 struct sk_softc *sc = xsc; 2272 struct sk_if_softc *sc_if; 2273 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2274 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2275 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2276 int claimed = 0; 2277 uint32_t status; 2278 struct msk_status_desc *cur_st; 2279 2280 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2281 if (status == 0xffffffff) 2282 return 0; 2283 if (status == 0) { 2284 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2285 return 0; 2286 } 2287 2288 status = CSR_READ_4(sc, SK_ISR); 2289 2290 if (sc_if0 != NULL) 2291 ifp0 = &sc_if0->sk_ethercom.ec_if; 2292 if (sc_if1 != NULL) 2293 ifp1 = &sc_if1->sk_ethercom.ec_if; 2294 2295 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2296 (ifp0->if_flags & IFF_RUNNING)) { 2297 msk_intr_yukon(sc_if0); 2298 } 2299 2300 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2301 (ifp1->if_flags & IFF_RUNNING)) { 2302 msk_intr_yukon(sc_if1); 2303 } 2304 2305 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2306 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2307 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2308 2309 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2310 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2311 switch (cur_st->sk_opcode) { 2312 case SK_Y2_STOPC_RXSTAT: 2313 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2314 if (sc_if) { 2315 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2316 letoh32(cur_st->sk_status)); 2317 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2318 msk_fill_rx_tick(sc_if); 2319 } 2320 break; 2321 case SK_Y2_STOPC_TXSTAT: 2322 if (sc_if0) 2323 msk_txeof(sc_if0); 2324 if (sc_if1) 2325 msk_txeof(sc_if1); 2326 break; 2327 default: 2328 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2329 break; 2330 } 2331 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2332 2333 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2334 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2335 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2336 } 2337 2338 if (status & SK_Y2_IMR_BMU) { 2339 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2340 claimed = 1; 2341 } 2342 2343 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2344 2345 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2346 if_schedule_deferred_start(ifp0); 2347 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2348 if_schedule_deferred_start(ifp1); 2349 2350 KASSERT(sc->rnd_attached > 0); 2351 rnd_add_uint32(&sc->rnd_source, status); 2352 2353 if (sc->sk_int_mod_pending) 2354 msk_update_int_mod(sc, 1); 2355 2356 return claimed; 2357 } 2358 2359 static void 2360 msk_init_yukon(struct sk_if_softc *sc_if) 2361 { 2362 uint32_t v; 2363 uint16_t reg; 2364 struct sk_softc *sc; 2365 int i; 2366 2367 sc = sc_if->sk_softc; 2368 2369 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2370 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2371 2372 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2373 2374 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2375 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2376 2377 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2378 2379 /* unused read of the interrupt source register */ 2380 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2381 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2382 2383 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2384 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2385 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2386 2387 /* MIB Counter Clear Mode set */ 2388 reg |= YU_PAR_MIB_CLR; 2389 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2390 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2391 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2392 2393 /* MIB Counter Clear Mode clear */ 2394 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2395 reg &= ~YU_PAR_MIB_CLR; 2396 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2397 2398 /* receive control reg */ 2399 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2400 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2401 2402 /* transmit control register */ 2403 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2404 2405 /* transmit flow control register */ 2406 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2407 2408 /* transmit parameter register */ 2409 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2410 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2411 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2412 2413 /* serial mode register */ 2414 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2415 reg = YU_SMR_DATA_BLIND(0x1c) | 2416 YU_SMR_MFL_VLAN | 2417 YU_SMR_IPG_DATA(0x1e); 2418 2419 if (sc->sk_type != SK_YUKON_FE && 2420 sc->sk_type != SK_YUKON_FE_P) 2421 reg |= YU_SMR_MFL_JUMBO; 2422 2423 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2424 2425 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2426 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2427 /* msk_attach calls me before ether_ifattach so check null */ 2428 if (ifp != NULL && ifp->if_sadl != NULL) 2429 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2430 sizeof(sc_if->sk_enaddr)); 2431 /* Setup Yukon's address */ 2432 for (i = 0; i < 3; i++) { 2433 /* Write Source Address 1 (unicast filter) */ 2434 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2435 sc_if->sk_enaddr[i * 2] | 2436 sc_if->sk_enaddr[i * 2 + 1] << 8); 2437 } 2438 2439 for (i = 0; i < 3; i++) { 2440 reg = sk_win_read_2(sc_if->sk_softc, 2441 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2442 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2443 } 2444 2445 /* Set promiscuous mode */ 2446 msk_setpromisc(sc_if); 2447 2448 /* Set multicast filter */ 2449 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2450 msk_setmulti(sc_if); 2451 2452 /* enable interrupt mask for counter overflows */ 2453 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2454 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2455 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2456 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2457 2458 /* Configure RX MAC FIFO Flush Mask */ 2459 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2460 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2461 YU_RXSTAT_JABBER; 2462 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2463 2464 /* Configure RX MAC FIFO */ 2465 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2466 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2467 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P)) 2468 v |= SK_RFCTL_RX_OVER_ON; 2469 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2470 2471 if ((sc->sk_type == SK_YUKON_FE_P) && 2472 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) 2473 v = 0x178; /* Magic value */ 2474 else { 2475 /* Increase flush threshold to 64 bytes */ 2476 v = SK_RFCTL_FIFO_THRESHOLD + 1; 2477 } 2478 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v); 2479 2480 /* Configure TX MAC FIFO */ 2481 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2482 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2483 2484 if ((sc->sk_type == SK_YUKON_FE_P) && 2485 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) { 2486 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END); 2487 v &= ~SK_TXEND_WM_ON; 2488 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v); 2489 } 2490 2491 #if 1 2492 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2493 #endif 2494 DPRINTFN(6, ("msk_init_yukon: end\n")); 2495 } 2496 2497 /* 2498 * Note that to properly initialize any part of the GEnesis chip, 2499 * you first have to take it out of reset mode. 2500 */ 2501 static int 2502 msk_init(struct ifnet *ifp) 2503 { 2504 struct sk_if_softc *sc_if = ifp->if_softc; 2505 struct sk_softc *sc = sc_if->sk_softc; 2506 int rc = 0, s; 2507 uint32_t imr, imtimer_ticks; 2508 2509 2510 DPRINTFN(2, ("msk_init\n")); 2511 2512 s = splnet(); 2513 2514 /* Cancel pending I/O and free all RX/TX buffers. */ 2515 msk_stop(ifp, 1); 2516 2517 /* Configure I2C registers */ 2518 2519 /* Configure XMAC(s) */ 2520 msk_init_yukon(sc_if); 2521 if ((rc = ether_mediachange(ifp)) != 0) 2522 goto out; 2523 2524 /* Configure transmit arbiter(s) */ 2525 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2526 #if 0 2527 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */ 2528 #endif 2529 2530 if (sc->sk_ramsize) { 2531 /* Configure RAMbuffers */ 2532 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2533 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2534 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2535 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2536 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2537 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2538 2539 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2540 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2541 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2542 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2543 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2544 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2545 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2546 } 2547 2548 /* Configure BMUs */ 2549 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2550 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2551 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2552 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2553 2554 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2555 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2556 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2557 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2558 2559 /* Make sure the sync transmit queue is disabled. */ 2560 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2561 2562 /* Init descriptors */ 2563 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2564 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2565 "memory for rx buffers\n"); 2566 msk_stop(ifp, 1); 2567 splx(s); 2568 return ENOBUFS; 2569 } 2570 2571 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2572 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2573 "memory for tx buffers\n"); 2574 msk_stop(ifp, 1); 2575 splx(s); 2576 return ENOBUFS; 2577 } 2578 2579 /* Set interrupt moderation if changed via sysctl. */ 2580 switch (sc->sk_type) { 2581 case SK_YUKON_EC: 2582 case SK_YUKON_EC_U: 2583 case SK_YUKON_EX: 2584 case SK_YUKON_SUPR: 2585 case SK_YUKON_ULTRA2: 2586 case SK_YUKON_OPTIMA: 2587 case SK_YUKON_PRM: 2588 case SK_YUKON_OPTIMA2: 2589 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2590 break; 2591 case SK_YUKON_FE: 2592 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2593 break; 2594 case SK_YUKON_FE_P: 2595 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2596 break; 2597 case SK_YUKON_XL: 2598 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2599 break; 2600 default: 2601 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2602 } 2603 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2604 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2605 sk_win_write_4(sc, SK_IMTIMERINIT, 2606 SK_IM_USECS(sc->sk_int_mod)); 2607 aprint_verbose_dev(sc->sk_dev, 2608 "interrupt moderation is %d us\n", sc->sk_int_mod); 2609 } 2610 2611 /* Initialize prefetch engine. */ 2612 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2613 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2614 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2615 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2616 MSK_RX_RING_ADDR(sc_if, 0)); 2617 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2618 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2619 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2620 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2621 2622 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2623 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2624 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2625 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2626 MSK_TX_RING_ADDR(sc_if, 0)); 2627 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2628 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2629 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2630 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2631 2632 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2633 sc_if->sk_cdata.sk_rx_prod); 2634 2635 2636 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) { 2637 /* Disable flushing of non-ASF packets. */ 2638 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, 2639 SK_RFCTL_RX_MACSEC_FLUSH_OFF); 2640 } 2641 2642 /* Configure interrupt handling */ 2643 if (sc_if->sk_port == SK_PORT_A) 2644 sc->sk_intrmask |= SK_Y2_INTRS1; 2645 else 2646 sc->sk_intrmask |= SK_Y2_INTRS2; 2647 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2648 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2649 2650 ifp->if_flags |= IFF_RUNNING; 2651 ifp->if_flags &= ~IFF_OACTIVE; 2652 2653 callout_schedule(&sc_if->sk_tick_ch, hz); 2654 2655 out: 2656 splx(s); 2657 return rc; 2658 } 2659 2660 /* 2661 * Note: the logic of second parameter is inverted compared to OpenBSD 2662 * code, since this code uses the function as if_stop hook too. 2663 */ 2664 static void 2665 msk_stop(struct ifnet *ifp, int disable) 2666 { 2667 struct sk_if_softc *sc_if = ifp->if_softc; 2668 struct sk_softc *sc = sc_if->sk_softc; 2669 bus_dmamap_t dmamap; 2670 int i; 2671 2672 DPRINTFN(2, ("msk_stop\n")); 2673 2674 callout_stop(&sc_if->sk_tick_ch); 2675 callout_stop(&sc_if->sk_tick_rx); 2676 2677 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2678 2679 /* Stop transfer of Tx descriptors */ 2680 2681 /* Stop transfer of Rx descriptors */ 2682 2683 if (disable) { 2684 /* Turn off various components of this interface. */ 2685 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2686 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2687 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2688 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2689 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2690 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2691 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2692 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2693 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2694 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2695 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2696 2697 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2698 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2699 2700 /* Disable interrupts */ 2701 if (sc_if->sk_port == SK_PORT_A) 2702 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2703 else 2704 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2705 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2706 } 2707 2708 /* Free RX and TX mbufs still in the queues. */ 2709 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2710 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2711 dmamap = sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap; 2712 2713 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2714 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2715 2716 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2717 2718 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2719 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2720 } 2721 } 2722 2723 sc_if->sk_cdata.sk_rx_prod = 0; 2724 sc_if->sk_cdata.sk_rx_cons = 0; 2725 sc_if->sk_cdata.sk_rx_cnt = 0; 2726 2727 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2728 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2729 dmamap = sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap; 2730 2731 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, 2732 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2733 2734 bus_dmamap_unload(sc->sc_dmatag, dmamap); 2735 2736 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2737 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2738 } 2739 } 2740 } 2741 2742 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2743 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2744 2745 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2746 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2747 2748 #ifdef MSK_DEBUG 2749 static void 2750 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2751 { 2752 #define DESC_PRINT(X) \ 2753 if (X) \ 2754 printf("txdesc[%d]." #X "=%#x\n", \ 2755 idx, X); 2756 2757 DESC_PRINT(letoh32(le->sk_addr)); 2758 DESC_PRINT(letoh16(le->sk_len)); 2759 DESC_PRINT(le->sk_ctl); 2760 DESC_PRINT(le->sk_opcode); 2761 #undef DESC_PRINT 2762 } 2763 2764 static void 2765 msk_dump_bytes(const char *data, int len) 2766 { 2767 int c, i, j; 2768 2769 for (i = 0; i < len; i += 16) { 2770 printf("%08x ", i); 2771 c = len - i; 2772 if (c > 16) c = 16; 2773 2774 for (j = 0; j < c; j++) { 2775 printf("%02x ", data[i + j] & 0xff); 2776 if ((j & 0xf) == 7 && j > 0) 2777 printf(" "); 2778 } 2779 2780 for (; j < 16; j++) 2781 printf(" "); 2782 printf(" "); 2783 2784 for (j = 0; j < c; j++) { 2785 int ch = data[i + j] & 0xff; 2786 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2787 } 2788 2789 printf("\n"); 2790 2791 if (c < 16) 2792 break; 2793 } 2794 } 2795 2796 static void 2797 msk_dump_mbuf(struct mbuf *m) 2798 { 2799 int count = m->m_pkthdr.len; 2800 2801 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2802 2803 while (count > 0 && m) { 2804 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2805 m, m->m_data, m->m_len); 2806 if (mskdebug >= 4) 2807 msk_dump_bytes(mtod(m, char *), m->m_len); 2808 2809 count -= m->m_len; 2810 m = m->m_next; 2811 } 2812 } 2813 #endif 2814 2815 static int 2816 msk_sysctl_handler(SYSCTLFN_ARGS) 2817 { 2818 int error, t; 2819 struct sysctlnode node; 2820 struct sk_softc *sc; 2821 2822 node = *rnode; 2823 sc = node.sysctl_data; 2824 t = sc->sk_int_mod; 2825 node.sysctl_data = &t; 2826 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2827 if (error || newp == NULL) 2828 return error; 2829 2830 if (t < SK_IM_MIN || t > SK_IM_MAX) 2831 return EINVAL; 2832 2833 /* update the softc with sysctl-changed value, and mark 2834 for hardware update */ 2835 sc->sk_int_mod = t; 2836 sc->sk_int_mod_pending = 1; 2837 return 0; 2838 } 2839 2840 /* 2841 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2842 * set up in mskc_attach() 2843 */ 2844 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2845 { 2846 int rc; 2847 const struct sysctlnode *node; 2848 2849 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2850 0, CTLTYPE_NODE, "msk", 2851 SYSCTL_DESCR("msk interface controls"), 2852 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2853 goto err; 2854 } 2855 2856 msk_root_num = node->sysctl_num; 2857 return; 2858 2859 err: 2860 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2861 } 2862
Indexes created Thu Sep 25 16:09:42 GMT 2025