if_msk.c revision 1.15 1 /* $NetBSD: if_msk.c,v 1.15 2008/01/19 22:10:18 dyoung Exp $ */
2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */
3
4 /*
5 * Copyright (c) 1997, 1998, 1999, 2000
6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
36 */
37
38 /*
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu>
40 *
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
44 *
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.15 2008/01/19 22:10:18 dyoung Exp $");
56
57 #include "bpfilter.h"
58 #include "rnd.h"
59
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/sockio.h>
63 #include <sys/mbuf.h>
64 #include <sys/malloc.h>
65 #include <sys/kernel.h>
66 #include <sys/socket.h>
67 #include <sys/device.h>
68 #include <sys/queue.h>
69 #include <sys/callout.h>
70 #include <sys/sysctl.h>
71 #include <sys/endian.h>
72 #ifdef __NetBSD__
73 #define letoh16 htole16
74 #define letoh32 htole32
75 #endif
76
77 #include <net/if.h>
78 #include <net/if_dl.h>
79 #include <net/if_types.h>
80
81 #include <net/if_media.h>
82
83 #if NBPFILTER > 0
84 #include <net/bpf.h>
85 #endif
86 #if NRND > 0
87 #include <sys/rnd.h>
88 #endif
89
90 #include <dev/mii/mii.h>
91 #include <dev/mii/miivar.h>
92 #include <dev/mii/brgphyreg.h>
93
94 #include <dev/pci/pcireg.h>
95 #include <dev/pci/pcivar.h>
96 #include <dev/pci/pcidevs.h>
97
98 #include <dev/pci/if_skreg.h>
99 #include <dev/pci/if_mskvar.h>
100
101 int mskc_probe(struct device *, struct cfdata *, void *);
102 void mskc_attach(struct device *, struct device *self, void *aux);
103 void mskc_shutdown(void *);
104 int msk_probe(struct device *, struct cfdata *, void *);
105 void msk_attach(struct device *, struct device *self, void *aux);
106 int mskcprint(void *, const char *);
107 int msk_intr(void *);
108 void msk_intr_yukon(struct sk_if_softc *);
109 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
110 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t);
111 void msk_txeof(struct sk_if_softc *, int);
112 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *);
113 void msk_start(struct ifnet *);
114 int msk_ioctl(struct ifnet *, u_long, void *);
115 int msk_init(struct ifnet *);
116 void msk_init_yukon(struct sk_if_softc *);
117 void msk_stop(struct ifnet *, int);
118 void msk_watchdog(struct ifnet *);
119 void msk_reset(struct sk_softc *);
120 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t);
121 int msk_alloc_jumbo_mem(struct sk_if_softc *);
122 void *msk_jalloc(struct sk_if_softc *);
123 void msk_jfree(struct mbuf *, void *, size_t, void *);
124 int msk_init_rx_ring(struct sk_if_softc *);
125 int msk_init_tx_ring(struct sk_if_softc *);
126
127 void msk_update_int_mod(struct sk_softc *);
128
129 int msk_miibus_readreg(struct device *, int, int);
130 void msk_miibus_writereg(struct device *, int, int, int);
131 void msk_miibus_statchg(struct device *);
132
133 void msk_setfilt(struct sk_if_softc *, void *, int);
134 void msk_setmulti(struct sk_if_softc *);
135 void msk_setpromisc(struct sk_if_softc *);
136 void msk_tick(void *);
137
138 /* #define MSK_DEBUG 1 */
139 #ifdef MSK_DEBUG
140 #define DPRINTF(x) if (mskdebug) printf x
141 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x
142 int mskdebug = MSK_DEBUG;
143
144 void msk_dump_txdesc(struct msk_tx_desc *, int);
145 void msk_dump_mbuf(struct mbuf *);
146 void msk_dump_bytes(const char *, int);
147 #else
148 #define DPRINTF(x)
149 #define DPRINTFN(n,x)
150 #endif
151
152 static int msk_sysctl_handler(SYSCTLFN_PROTO);
153 static int msk_root_num;
154
155 /* supported device vendors */
156 static const struct msk_product {
157 pci_vendor_id_t msk_vendor;
158 pci_product_id_t msk_product;
159 } msk_products[] = {
160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX },
161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX },
162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T },
163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 },
164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 },
165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 },
166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 },
167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 },
168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 },
169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 },
170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 },
171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 },
172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 },
173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 },
174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 },
175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 },
176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 },
177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 },
178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 },
179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU },
180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X },
181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU },
182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X },
183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU },
184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X },
185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU },
186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X },
187 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX },
188 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }
189 };
190
191 static inline u_int32_t
192 sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
193 {
194 return CSR_READ_4(sc, reg);
195 }
196
197 static inline u_int16_t
198 sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
199 {
200 return CSR_READ_2(sc, reg);
201 }
202
203 static inline u_int8_t
204 sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
205 {
206 return CSR_READ_1(sc, reg);
207 }
208
209 static inline void
210 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
211 {
212 CSR_WRITE_4(sc, reg, x);
213 }
214
215 static inline void
216 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
217 {
218 CSR_WRITE_2(sc, reg, x);
219 }
220
221 static inline void
222 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
223 {
224 CSR_WRITE_1(sc, reg, x);
225 }
226
227 int
228 msk_miibus_readreg(struct device *dev, int phy, int reg)
229 {
230 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
231 u_int16_t val;
232 int i;
233
234 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
235 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
236
237 for (i = 0; i < SK_TIMEOUT; i++) {
238 DELAY(1);
239 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
240 if (val & YU_SMICR_READ_VALID)
241 break;
242 }
243
244 if (i == SK_TIMEOUT) {
245 aprint_error("%s: phy failed to come ready\n",
246 sc_if->sk_dev.dv_xname);
247 return (0);
248 }
249
250 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i,
251 SK_TIMEOUT));
252
253 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
254
255 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
256 phy, reg, val));
257
258 return (val);
259 }
260
261 void
262 msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
263 {
264 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
265 int i;
266
267 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n",
268 phy, reg, val));
269
270 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
271 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
272 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
273
274 for (i = 0; i < SK_TIMEOUT; i++) {
275 DELAY(1);
276 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
277 break;
278 }
279
280 if (i == SK_TIMEOUT)
281 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname);
282 }
283
284 void
285 msk_miibus_statchg(struct device *dev)
286 {
287 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
288 struct mii_data *mii = &sc_if->sk_mii;
289 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
290 int gpcr;
291
292 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR);
293 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN);
294
295 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
296 /* Set speed. */
297 gpcr |= YU_GPCR_SPEED_DIS;
298 switch (IFM_SUBTYPE(mii->mii_media_active)) {
299 case IFM_1000_SX:
300 case IFM_1000_LX:
301 case IFM_1000_CX:
302 case IFM_1000_T:
303 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED);
304 break;
305 case IFM_100_TX:
306 gpcr |= YU_GPCR_SPEED;
307 break;
308 }
309
310 /* Set duplex. */
311 gpcr |= YU_GPCR_DPLX_DIS;
312 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
313 gpcr |= YU_GPCR_DUPLEX;
314
315 /* Disable flow control. */
316 gpcr |= YU_GPCR_FCTL_DIS;
317 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS);
318 }
319
320 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr);
321
322 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n",
323 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR)));
324 }
325
326 #define HASH_BITS 6
327
328 void
329 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot)
330 {
331 char *addr = addrv;
332 int base = XM_RXFILT_ENTRY(slot);
333
334 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
335 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
336 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
337 }
338
339 void
340 msk_setmulti(struct sk_if_softc *sc_if)
341 {
342 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if;
343 u_int32_t hashes[2] = { 0, 0 };
344 int h;
345 struct ethercom *ec = &sc_if->sk_ethercom;
346 struct ether_multi *enm;
347 struct ether_multistep step;
348 u_int16_t reg;
349
350 /* First, zot all the existing filters. */
351 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
352 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
353 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
354 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
355
356
357 /* Now program new ones. */
358 reg = SK_YU_READ_2(sc_if, YUKON_RCR);
359 reg |= YU_RCR_UFLEN;
360 allmulti:
361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
362 if ((ifp->if_flags & IFF_PROMISC) != 0)
363 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
364 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
365 hashes[0] = 0xFFFFFFFF;
366 hashes[1] = 0xFFFFFFFF;
367 }
368 } else {
369 /* First find the tail of the list. */
370 ETHER_FIRST_MULTI(step, ec, enm);
371 while (enm != NULL) {
372 if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
373 ETHER_ADDR_LEN)) {
374 ifp->if_flags |= IFF_ALLMULTI;
375 goto allmulti;
376 }
377 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
378 ((1 << HASH_BITS) - 1);
379 if (h < 32)
380 hashes[0] |= (1 << h);
381 else
382 hashes[1] |= (1 << (h - 32));
383
384 ETHER_NEXT_MULTI(step, enm);
385 }
386 reg |= YU_RCR_MUFLEN;
387 }
388
389 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
390 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
391 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
392 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
393 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg);
394 }
395
396 void
397 msk_setpromisc(struct sk_if_softc *sc_if)
398 {
399 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
400
401 if (ifp->if_flags & IFF_PROMISC)
402 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
403 YU_RCR_UFLEN | YU_RCR_MUFLEN);
404 else
405 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
406 YU_RCR_UFLEN | YU_RCR_MUFLEN);
407 }
408
409 int
410 msk_init_rx_ring(struct sk_if_softc *sc_if)
411 {
412 struct msk_chain_data *cd = &sc_if->sk_cdata;
413 struct msk_ring_data *rd = sc_if->sk_rdata;
414 int i, nexti;
415
416 bzero((char *)rd->sk_rx_ring,
417 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
418
419 for (i = 0; i < MSK_RX_RING_CNT; i++) {
420 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i];
421 if (i == (MSK_RX_RING_CNT - 1))
422 nexti = 0;
423 else
424 nexti = i + 1;
425 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti];
426 }
427
428 for (i = 0; i < MSK_RX_RING_CNT; i++) {
429 if (msk_newbuf(sc_if, i, NULL,
430 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) {
431 aprint_error("%s: failed alloc of %dth mbuf\n",
432 sc_if->sk_dev.dv_xname, i);
433 return (ENOBUFS);
434 }
435 }
436
437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1;
438 sc_if->sk_cdata.sk_rx_cons = 0;
439
440 return (0);
441 }
442
443 int
444 msk_init_tx_ring(struct sk_if_softc *sc_if)
445 {
446 struct sk_softc *sc = sc_if->sk_softc;
447 struct msk_chain_data *cd = &sc_if->sk_cdata;
448 struct msk_ring_data *rd = sc_if->sk_rdata;
449 bus_dmamap_t dmamap;
450 struct sk_txmap_entry *entry;
451 int i, nexti;
452
453 bzero((char *)sc_if->sk_rdata->sk_tx_ring,
454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
455
456 SIMPLEQ_INIT(&sc_if->sk_txmap_head);
457 for (i = 0; i < MSK_TX_RING_CNT; i++) {
458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i];
459 if (i == (MSK_TX_RING_CNT - 1))
460 nexti = 0;
461 else
462 nexti = i + 1;
463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
464
465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap))
467 return (ENOBUFS);
468
469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT);
470 if (!entry) {
471 bus_dmamap_destroy(sc->sc_dmatag, dmamap);
472 return (ENOBUFS);
473 }
474 entry->dmamap = dmamap;
475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
476 }
477
478 sc_if->sk_cdata.sk_tx_prod = 0;
479 sc_if->sk_cdata.sk_tx_cons = 0;
480 sc_if->sk_cdata.sk_tx_cnt = 0;
481
482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT,
483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
484
485 return (0);
486 }
487
488 int
489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m,
490 bus_dmamap_t dmamap)
491 {
492 struct mbuf *m_new = NULL;
493 struct sk_chain *c;
494 struct msk_rx_desc *r;
495
496 if (m == NULL) {
497 void *buf = NULL;
498
499 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
500 if (m_new == NULL)
501 return (ENOBUFS);
502
503 /* Allocate the jumbo buffer */
504 buf = msk_jalloc(sc_if);
505 if (buf == NULL) {
506 m_freem(m_new);
507 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname));
509 return (ENOBUFS);
510 }
511
512 /* Attach the buffer to the mbuf */
513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if);
515 } else {
516 /*
517 * We're re-using a previously allocated mbuf;
518 * be sure to re-init pointers and lengths to
519 * default values.
520 */
521 m_new = m;
522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
523 m_new->m_data = m_new->m_ext.ext_buf;
524 }
525 m_adj(m_new, ETHER_ALIGN);
526
527 c = &sc_if->sk_cdata.sk_rx_chain[i];
528 r = c->sk_le;
529 c->sk_mbuf = m_new;
530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr +
531 (((vaddr_t)m_new->m_data
532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)));
533 r->sk_len = htole16(SK_JLEN);
534 r->sk_ctl = 0;
535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN;
536
537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
538
539 return (0);
540 }
541
542 /*
543 * Memory management for jumbo frames.
544 */
545
546 int
547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
548 {
549 struct sk_softc *sc = sc_if->sk_softc;
550 char *ptr, *kva;
551 bus_dma_segment_t seg;
552 int i, rseg, state, error;
553 struct sk_jpool_entry *entry;
554
555 state = error = 0;
556
557 /* Grab a big chunk o' storage. */
558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0,
559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
560 aprint_error(": can't alloc rx buffers");
561 return (ENOBUFS);
562 }
563
564 state = 1;
565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva,
566 BUS_DMA_NOWAIT)) {
567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM);
568 error = ENOBUFS;
569 goto out;
570 }
571
572 state = 2;
573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0,
574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
575 aprint_error(": can't create dma map");
576 error = ENOBUFS;
577 goto out;
578 }
579
580 state = 3;
581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) {
583 aprint_error(": can't load dma map");
584 error = ENOBUFS;
585 goto out;
586 }
587
588 state = 4;
589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva;
590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf));
591
592 LIST_INIT(&sc_if->sk_jfree_listhead);
593 LIST_INIT(&sc_if->sk_jinuse_listhead);
594
595 /*
596 * Now divide it up into 9K pieces and save the addresses
597 * in an array.
598 */
599 ptr = sc_if->sk_cdata.sk_jumbo_buf;
600 for (i = 0; i < MSK_JSLOTS; i++) {
601 sc_if->sk_cdata.sk_jslots[i] = ptr;
602 ptr += SK_JLEN;
603 entry = malloc(sizeof(struct sk_jpool_entry),
604 M_DEVBUF, M_NOWAIT);
605 if (entry == NULL) {
606 sc_if->sk_cdata.sk_jumbo_buf = NULL;
607 aprint_error(": no memory for jumbo buffer queue!");
608 error = ENOBUFS;
609 goto out;
610 }
611 entry->slot = i;
612 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
613 entry, jpool_entries);
614 }
615 out:
616 if (error != 0) {
617 switch (state) {
618 case 4:
619 bus_dmamap_unload(sc->sc_dmatag,
620 sc_if->sk_cdata.sk_rx_jumbo_map);
621 case 3:
622 bus_dmamap_destroy(sc->sc_dmatag,
623 sc_if->sk_cdata.sk_rx_jumbo_map);
624 case 2:
625 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM);
626 case 1:
627 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
628 break;
629 default:
630 break;
631 }
632 }
633
634 return (error);
635 }
636
637 /*
638 * Allocate a jumbo buffer.
639 */
640 void *
641 msk_jalloc(struct sk_if_softc *sc_if)
642 {
643 struct sk_jpool_entry *entry;
644
645 entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
646
647 if (entry == NULL)
648 return (NULL);
649
650 LIST_REMOVE(entry, jpool_entries);
651 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
652 return (sc_if->sk_cdata.sk_jslots[entry->slot]);
653 }
654
655 /*
656 * Release a jumbo buffer.
657 */
658 void
659 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
660 {
661 struct sk_jpool_entry *entry;
662 struct sk_if_softc *sc;
663 int i, s;
664
665 /* Extract the softc struct pointer. */
666 sc = (struct sk_if_softc *)arg;
667
668 if (sc == NULL)
669 panic("msk_jfree: can't find softc pointer!");
670
671 /* calculate the slot this buffer belongs to */
672 i = ((vaddr_t)buf
673 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
674
675 if ((i < 0) || (i >= MSK_JSLOTS))
676 panic("msk_jfree: asked to free buffer that we don't manage!");
677
678 s = splvm();
679 entry = LIST_FIRST(&sc->sk_jinuse_listhead);
680 if (entry == NULL)
681 panic("msk_jfree: buffer not in use!");
682 entry->slot = i;
683 LIST_REMOVE(entry, jpool_entries);
684 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries);
685
686 if (__predict_true(m != NULL))
687 pool_cache_put(mb_cache, m);
688 splx(s);
689 }
690
691 int
692 msk_ioctl(struct ifnet *ifp, u_long command, void *data)
693 {
694 struct sk_if_softc *sc_if = ifp->if_softc;
695 struct ifreq *ifr = (struct ifreq *) data;
696 int s, error = 0;
697
698 s = splnet();
699
700 switch(command) {
701 case SIOCSIFMTU:
702 if (ifr->ifr_mtu < ETHERMIN)
703 return EINVAL;
704 else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) {
705 if (ifr->ifr_mtu > SK_JUMBO_MTU)
706 error = EINVAL;
707 } else if (ifr->ifr_mtu > ETHERMTU)
708 error = EINVAL;
709 ifp->if_mtu = ifr->ifr_mtu;
710 break;
711 default:
712 DPRINTFN(2, ("msk_ioctl ETHER\n"));
713 error = ether_ioctl(ifp, command, data);
714
715 if (error == ENETRESET) {
716 /*
717 * Multicast list has changed; set the hardware
718 * filter accordingly.
719 */
720 if (ifp->if_flags & IFF_RUNNING)
721 msk_setmulti(sc_if);
722 error = 0;
723 }
724 break;
725 }
726
727 splx(s);
728 return (error);
729 }
730
731 void
732 msk_update_int_mod(struct sk_softc *sc)
733 {
734 u_int32_t imtimer_ticks;
735
736 /*
737 * Configure interrupt moderation. The moderation timer
738 * defers interrupts specified in the interrupt moderation
739 * timer mask based on the timeout specified in the interrupt
740 * moderation timer init register. Each bit in the timer
741 * register represents one tick, so to specify a timeout in
742 * microseconds, we have to multiply by the correct number of
743 * ticks-per-microsecond.
744 */
745 switch (sc->sk_type) {
746 case SK_YUKON_EC:
747 case SK_YUKON_EC_U:
748 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
749 break;
750 case SK_YUKON_FE:
751 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
752 break;
753 case SK_YUKON_XL:
754 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
755 break;
756 default:
757 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
758 }
759 aprint_verbose("%s: interrupt moderation is %d us\n",
760 sc->sk_dev.dv_xname, sc->sk_int_mod);
761 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod));
762 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
763 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
764 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
765 sc->sk_int_mod_pending = 0;
766 }
767
768 static int
769 msk_lookup(const struct pci_attach_args *pa)
770 {
771 const struct msk_product *pmsk;
772
773 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) {
774 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor &&
775 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product)
776 return 1;
777 }
778 return 0;
779 }
780
781 /*
782 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
783 * IDs against our list and return a device name if we find a match.
784 */
785 int
786 mskc_probe(struct device *parent, struct cfdata *match,
787 void *aux)
788 {
789 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
790
791 return msk_lookup(pa);
792 }
793
794 /*
795 * Force the GEnesis into reset, then bring it out of reset.
796 */
797 void msk_reset(struct sk_softc *sc)
798 {
799 u_int32_t imtimer_ticks, reg1;
800 int reg;
801
802 DPRINTFN(2, ("msk_reset\n"));
803
804 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
805 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
806
807 DELAY(1000);
808 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
809 DELAY(2);
810 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
811 sk_win_write_1(sc, SK_TESTCTL1, 2);
812
813 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
814 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
815 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
816 else
817 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
818 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
819
820 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
821 sk_win_write_1(sc, SK_Y2_CLKGATE,
822 SK_Y2_CLKGATE_LINK1_GATE_DIS |
823 SK_Y2_CLKGATE_LINK2_GATE_DIS |
824 SK_Y2_CLKGATE_LINK1_CORE_DIS |
825 SK_Y2_CLKGATE_LINK2_CORE_DIS |
826 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS);
827 else
828 sk_win_write_1(sc, SK_Y2_CLKGATE, 0);
829
830 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
831 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);
832 DELAY(1000);
833 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
834 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);
835
836 sk_win_write_1(sc, SK_TESTCTL1, 1);
837
838 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
839 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n",
840 CSR_READ_2(sc, SK_LINK_CTRL)));
841
842 /* Disable ASF */
843 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
844 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
845
846 /* Clear I2C IRQ noise */
847 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1);
848
849 /* Disable hardware timer */
850 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);
851 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);
852
853 /* Disable descriptor polling */
854 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
855
856 /* Disable time stamps */
857 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);
858 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR);
859
860 /* Enable RAM interface */
861 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
862 for (reg = SK_TO0;reg <= SK_TO11; reg++)
863 sk_win_write_1(sc, reg, 36);
864 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET);
865 for (reg = SK_TO0;reg <= SK_TO11; reg++)
866 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
867
868 /*
869 * Configure interrupt moderation. The moderation timer
870 * defers interrupts specified in the interrupt moderation
871 * timer mask based on the timeout specified in the interrupt
872 * moderation timer init register. Each bit in the timer
873 * register represents one tick, so to specify a timeout in
874 * microseconds, we have to multiply by the correct number of
875 * ticks-per-microsecond.
876 */
877 switch (sc->sk_type) {
878 case SK_YUKON_EC:
879 case SK_YUKON_EC_U:
880 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
881 break;
882 case SK_YUKON_FE:
883 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
884 break;
885 case SK_YUKON_XL:
886 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
887 break;
888 default:
889 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
890 }
891
892 /* Reset status ring. */
893 bzero((char *)sc->sk_status_ring,
894 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
895 sc->sk_status_idx = 0;
896
897 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET);
898 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET);
899
900 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1);
901 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO,
902 sc->sk_status_map->dm_segs[0].ds_addr);
903 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI,
904 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32);
905 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) {
906 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK);
907 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21);
908 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07);
909 } else {
910 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a);
911 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10);
912 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM,
913 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04);
914 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */
915 }
916
917 #if 0
918 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100));
919 #endif
920 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000));
921
922 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON);
923
924 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START);
925 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START);
926 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START);
927
928 msk_update_int_mod(sc);
929 }
930
931 int
932 msk_probe(struct device *parent, struct cfdata *match,
933 void *aux)
934 {
935 struct skc_attach_args *sa = aux;
936
937 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
938 return (0);
939
940 switch (sa->skc_type) {
941 case SK_YUKON_XL:
942 case SK_YUKON_EC_U:
943 case SK_YUKON_EC:
944 case SK_YUKON_FE:
945 return (1);
946 }
947
948 return (0);
949 }
950
951 /*
952 * Each XMAC chip is attached as a separate logical IP interface.
953 * Single port cards will have only one logical interface of course.
954 */
955 void
956 msk_attach(struct device *parent, struct device *self, void *aux)
957 {
958 struct sk_if_softc *sc_if = (struct sk_if_softc *) self;
959 struct sk_softc *sc = (struct sk_softc *)parent;
960 struct skc_attach_args *sa = aux;
961 struct ifnet *ifp;
962 void *kva;
963 bus_dma_segment_t seg;
964 int i, rseg;
965 u_int32_t chunk, val;
966
967 sc_if->sk_port = sa->skc_port;
968 sc_if->sk_softc = sc;
969 sc->sk_if[sa->skc_port] = sc_if;
970
971 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port));
972
973 /*
974 * Get station address for this interface. Note that
975 * dual port cards actually come with three station
976 * addresses: one for each port, plus an extra. The
977 * extra one is used by the SysKonnect driver software
978 * as a 'virtual' station address for when both ports
979 * are operating in failover mode. Currently we don't
980 * use this extra address.
981 */
982 for (i = 0; i < ETHER_ADDR_LEN; i++)
983 sc_if->sk_enaddr[i] =
984 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i);
985
986 aprint_normal(": Ethernet address %s\n",
987 ether_sprintf(sc_if->sk_enaddr));
988
989 /*
990 * Set up RAM buffer addresses. The NIC will have a certain
991 * amount of SRAM on it, somewhere between 512K and 2MB. We
992 * need to divide this up a) between the transmitter and
993 * receiver and b) between the two XMACs, if this is a
994 * dual port NIC. Our algorithm is to divide up the memory
995 * evenly so that everyone gets a fair share.
996 *
997 * Just to be contrary, Yukon2 appears to have separate memory
998 * for each MAC.
999 */
1000 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3;
1001 val = sc->sk_rboff / sizeof(u_int64_t);
1002 sc_if->sk_rx_ramstart = val;
1003 val += (chunk / sizeof(u_int64_t));
1004 sc_if->sk_rx_ramend = val - 1;
1005 chunk = sc->sk_ramsize - chunk;
1006 sc_if->sk_tx_ramstart = val;
1007 val += (chunk / sizeof(u_int64_t));
1008 sc_if->sk_tx_ramend = val - 1;
1009
1010 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1011 " tx_ramstart=%#x tx_ramend=%#x\n",
1012 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1013 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1014
1015 /* Allocate the descriptor queues. */
1016 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data),
1017 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1018 aprint_error(": can't alloc rx buffers\n");
1019 goto fail;
1020 }
1021 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
1022 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) {
1023 aprint_error(": can't map dma buffers (%zu bytes)\n",
1024 sizeof(struct msk_ring_data));
1025 goto fail_1;
1026 }
1027 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1,
1028 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT,
1029 &sc_if->sk_ring_map)) {
1030 aprint_error(": can't create dma map\n");
1031 goto fail_2;
1032 }
1033 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
1034 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) {
1035 aprint_error(": can't load dma map\n");
1036 goto fail_3;
1037 }
1038 sc_if->sk_rdata = (struct msk_ring_data *)kva;
1039 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data));
1040
1041 ifp = &sc_if->sk_ethercom.ec_if;
1042 /* Try to allocate memory for jumbo buffers. */
1043 if (msk_alloc_jumbo_mem(sc_if)) {
1044 aprint_error(": jumbo buffer allocation failed\n");
1045 goto fail_3;
1046 }
1047 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU
1048 | ETHERCAP_JUMBO_MTU;
1049
1050 ifp->if_softc = sc_if;
1051 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1052 ifp->if_ioctl = msk_ioctl;
1053 ifp->if_start = msk_start;
1054 ifp->if_stop = msk_stop;
1055 ifp->if_init = msk_init;
1056 ifp->if_watchdog = msk_watchdog;
1057 ifp->if_baudrate = 1000000000;
1058 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1059 IFQ_SET_READY(&ifp->if_snd);
1060 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname);
1061
1062 /*
1063 * Do miibus setup.
1064 */
1065 msk_init_yukon(sc_if);
1066
1067 DPRINTFN(2, ("msk_attach: 1\n"));
1068
1069 sc_if->sk_mii.mii_ifp = ifp;
1070 sc_if->sk_mii.mii_readreg = msk_miibus_readreg;
1071 sc_if->sk_mii.mii_writereg = msk_miibus_writereg;
1072 sc_if->sk_mii.mii_statchg = msk_miibus_statchg;
1073
1074 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii;
1075 ifmedia_init(&sc_if->sk_mii.mii_media, 0,
1076 ether_mediachange, ether_mediastatus);
1077 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
1078 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG);
1079 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) {
1080 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname);
1081 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL,
1082 0, NULL);
1083 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL);
1084 } else
1085 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO);
1086
1087 callout_init(&sc_if->sk_tick_ch, 0);
1088 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if);
1089 callout_schedule(&sc_if->sk_tick_ch, hz);
1090
1091 /*
1092 * Call MI attach routines.
1093 */
1094 if_attach(ifp);
1095 ether_ifattach(ifp, sc_if->sk_enaddr);
1096
1097 shutdownhook_establish(mskc_shutdown, sc);
1098
1099 #if NRND > 0
1100 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname,
1101 RND_TYPE_NET, 0);
1102 #endif
1103
1104 DPRINTFN(2, ("msk_attach: end\n"));
1105 return;
1106
1107 fail_3:
1108 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1109 fail_2:
1110 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data));
1111 fail_1:
1112 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1113 fail:
1114 sc->sk_if[sa->skc_port] = NULL;
1115 }
1116
1117 int
1118 mskcprint(void *aux, const char *pnp)
1119 {
1120 struct skc_attach_args *sa = aux;
1121
1122 if (pnp)
1123 aprint_normal("sk port %c at %s",
1124 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
1125 else
1126 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
1127 return (UNCONF);
1128 }
1129
1130 /*
1131 * Attach the interface. Allocate softc structures, do ifmedia
1132 * setup and ethernet/BPF attach.
1133 */
1134 void
1135 mskc_attach(struct device *parent, struct device *self, void *aux)
1136 {
1137 struct sk_softc *sc = (struct sk_softc *)self;
1138 struct pci_attach_args *pa = aux;
1139 struct skc_attach_args skca;
1140 pci_chipset_tag_t pc = pa->pa_pc;
1141 pcireg_t command, memtype;
1142 pci_intr_handle_t ih;
1143 const char *intrstr = NULL;
1144 bus_size_t size;
1145 int rc, sk_nodenum;
1146 u_int8_t hw, skrs;
1147 const char *revstr = NULL;
1148 const struct sysctlnode *node;
1149 void *kva;
1150 bus_dma_segment_t seg;
1151 int rseg;
1152
1153 DPRINTFN(2, ("begin mskc_attach\n"));
1154
1155 /*
1156 * Handle power management nonsense.
1157 */
1158 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF;
1159
1160 if (command == 0x01) {
1161 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL);
1162 if (command & SK_PSTATE_MASK) {
1163 u_int32_t iobase, membase, irq;
1164
1165 /* Save important PCI config data. */
1166 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO);
1167 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM);
1168 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE);
1169
1170 /* Reset the power state. */
1171 aprint_normal("%s chip is in D%d power mode "
1172 "-- setting to D0\n", sc->sk_dev.dv_xname,
1173 command & SK_PSTATE_MASK);
1174 command &= 0xFFFFFFFC;
1175 pci_conf_write(pc, pa->pa_tag,
1176 SK_PCI_PWRMGMTCTRL, command);
1177
1178 /* Restore PCI config data. */
1179 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase);
1180 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase);
1181 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq);
1182 }
1183 }
1184
1185 /*
1186 * Map control/status registers.
1187 */
1188
1189 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
1190 switch (memtype) {
1191 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1192 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1193 if (pci_mapreg_map(pa, SK_PCI_LOMEM,
1194 memtype, 0, &sc->sk_btag, &sc->sk_bhandle,
1195 NULL, &size) == 0)
1196 break;
1197 default:
1198 aprint_error(": can't map mem space\n");
1199 return;
1200 }
1201
1202 sc->sc_dmatag = pa->pa_dmat;
1203
1204 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1205 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1206
1207 /* bail out here if chip is not recognized */
1208 if (!(SK_IS_YUKON2(sc))) {
1209 aprint_error(": unknown chip type: %d\n", sc->sk_type);
1210 goto fail_1;
1211 }
1212 DPRINTFN(2, ("mskc_attach: allocate interrupt\n"));
1213
1214 /* Allocate interrupt */
1215 if (pci_intr_map(pa, &ih)) {
1216 aprint_error(": couldn't map interrupt\n");
1217 goto fail_1;
1218 }
1219
1220 intrstr = pci_intr_string(pc, ih);
1221 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc);
1222 if (sc->sk_intrhand == NULL) {
1223 aprint_error(": couldn't establish interrupt");
1224 if (intrstr != NULL)
1225 aprint_error(" at %s", intrstr);
1226 aprint_error("\n");
1227 goto fail_1;
1228 }
1229
1230 if (bus_dmamem_alloc(sc->sc_dmatag,
1231 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1232 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1233 aprint_error(": can't alloc status buffers\n");
1234 goto fail_2;
1235 }
1236
1237 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
1238 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1239 &kva, BUS_DMA_NOWAIT)) {
1240 aprint_error(": can't map dma buffers (%zu bytes)\n",
1241 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1242 goto fail_3;
1243 }
1244 if (bus_dmamap_create(sc->sc_dmatag,
1245 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1,
1246 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0,
1247 BUS_DMA_NOWAIT, &sc->sk_status_map)) {
1248 aprint_error(": can't create dma map\n");
1249 goto fail_4;
1250 }
1251 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva,
1252 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1253 NULL, BUS_DMA_NOWAIT)) {
1254 aprint_error(": can't load dma map\n");
1255 goto fail_5;
1256 }
1257 sc->sk_status_ring = (struct msk_status_desc *)kva;
1258 bzero(sc->sk_status_ring,
1259 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1260
1261 /* Reset the adapter. */
1262 msk_reset(sc);
1263
1264 skrs = sk_win_read_1(sc, SK_EPROM0);
1265 if (skrs == 0x00)
1266 sc->sk_ramsize = 0x20000;
1267 else
1268 sc->sk_ramsize = skrs * (1<<12);
1269 sc->sk_rboff = SK_RBOFF_0;
1270
1271 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n",
1272 sc->sk_ramsize, sc->sk_ramsize / 1024,
1273 sc->sk_rboff));
1274
1275 switch (sc->sk_type) {
1276 case SK_YUKON_XL:
1277 sc->sk_name = "Yukon-2 XL";
1278 break;
1279 case SK_YUKON_EC_U:
1280 sc->sk_name = "Yukon-2 EC Ultra";
1281 break;
1282 case SK_YUKON_EC:
1283 sc->sk_name = "Yukon-2 EC";
1284 break;
1285 case SK_YUKON_FE:
1286 sc->sk_name = "Yukon-2 FE";
1287 break;
1288 default:
1289 sc->sk_name = "Yukon (Unknown)";
1290 }
1291
1292 if (sc->sk_type == SK_YUKON_XL) {
1293 switch (sc->sk_rev) {
1294 case SK_YUKON_XL_REV_A0:
1295 sc->sk_workaround = 0;
1296 revstr = "A0";
1297 break;
1298 case SK_YUKON_XL_REV_A1:
1299 sc->sk_workaround = SK_WA_4109;
1300 revstr = "A1";
1301 break;
1302 case SK_YUKON_XL_REV_A2:
1303 sc->sk_workaround = SK_WA_4109;
1304 revstr = "A2";
1305 break;
1306 case SK_YUKON_XL_REV_A3:
1307 sc->sk_workaround = SK_WA_4109;
1308 revstr = "A3";
1309 break;
1310 default:
1311 sc->sk_workaround = 0;
1312 break;
1313 }
1314 }
1315
1316 if (sc->sk_type == SK_YUKON_EC) {
1317 switch (sc->sk_rev) {
1318 case SK_YUKON_EC_REV_A1:
1319 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109;
1320 revstr = "A1";
1321 break;
1322 case SK_YUKON_EC_REV_A2:
1323 sc->sk_workaround = SK_WA_4109;
1324 revstr = "A2";
1325 break;
1326 case SK_YUKON_EC_REV_A3:
1327 sc->sk_workaround = SK_WA_4109;
1328 revstr = "A3";
1329 break;
1330 default:
1331 sc->sk_workaround = 0;
1332 break;
1333 }
1334 }
1335
1336 if (sc->sk_type == SK_YUKON_FE) {
1337 sc->sk_workaround = SK_WA_4109;
1338 switch (sc->sk_rev) {
1339 case SK_YUKON_FE_REV_A1:
1340 revstr = "A1";
1341 break;
1342 case SK_YUKON_FE_REV_A2:
1343 revstr = "A2";
1344 break;
1345 default:
1346 sc->sk_workaround = 0;
1347 break;
1348 }
1349 }
1350
1351 if (sc->sk_type == SK_YUKON_EC_U) {
1352 sc->sk_workaround = SK_WA_4109;
1353 switch (sc->sk_rev) {
1354 case SK_YUKON_EC_U_REV_A0:
1355 revstr = "A0";
1356 break;
1357 case SK_YUKON_EC_U_REV_A1:
1358 revstr = "A1";
1359 break;
1360 case SK_YUKON_EC_U_REV_B0:
1361 revstr = "B0";
1362 break;
1363 default:
1364 sc->sk_workaround = 0;
1365 break;
1366 }
1367 }
1368
1369 /* Announce the product name. */
1370 aprint_normal(", %s", sc->sk_name);
1371 if (revstr != NULL)
1372 aprint_normal(" rev. %s", revstr);
1373 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr);
1374
1375 sc->sk_macs = 1;
1376
1377 hw = sk_win_read_1(sc, SK_Y2_HWRES);
1378 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) {
1379 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) &
1380 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0)
1381 sc->sk_macs++;
1382 }
1383
1384 skca.skc_port = SK_PORT_A;
1385 skca.skc_type = sc->sk_type;
1386 skca.skc_rev = sc->sk_rev;
1387 (void)config_found(&sc->sk_dev, &skca, mskcprint);
1388
1389 if (sc->sk_macs > 1) {
1390 skca.skc_port = SK_PORT_B;
1391 skca.skc_type = sc->sk_type;
1392 skca.skc_rev = sc->sk_rev;
1393 (void)config_found(&sc->sk_dev, &skca, mskcprint);
1394 }
1395
1396 /* Turn on the 'driver is loaded' LED. */
1397 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1398
1399 /* skc sysctl setup */
1400
1401 sc->sk_int_mod = SK_IM_DEFAULT;
1402 sc->sk_int_mod_pending = 0;
1403
1404 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1405 0, CTLTYPE_NODE, sc->sk_dev.dv_xname,
1406 SYSCTL_DESCR("mskc per-controller controls"),
1407 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE,
1408 CTL_EOL)) != 0) {
1409 aprint_normal("%s: couldn't create sysctl node\n",
1410 sc->sk_dev.dv_xname);
1411 goto fail_6;
1412 }
1413
1414 sk_nodenum = node->sysctl_num;
1415
1416 /* interrupt moderation time in usecs */
1417 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1418 CTLFLAG_READWRITE,
1419 CTLTYPE_INT, "int_mod",
1420 SYSCTL_DESCR("msk interrupt moderation timer"),
1421 msk_sysctl_handler, 0, sc,
1422 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE,
1423 CTL_EOL)) != 0) {
1424 aprint_normal("%s: couldn't create int_mod sysctl node\n",
1425 sc->sk_dev.dv_xname);
1426 goto fail_6;
1427 }
1428
1429 return;
1430
1431 fail_6:
1432 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map);
1433 fail_5:
1434 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map);
1435 fail_4:
1436 bus_dmamem_unmap(sc->sc_dmatag, kva,
1437 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1438 fail_3:
1439 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1440 fail_2:
1441 pci_intr_disestablish(pc, sc->sk_intrhand);
1442 fail_1:
1443 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size);
1444 }
1445
1446 int
1447 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
1448 {
1449 struct sk_softc *sc = sc_if->sk_softc;
1450 struct msk_tx_desc *f = NULL;
1451 u_int32_t frag, cur;
1452 int i;
1453 struct sk_txmap_entry *entry;
1454 bus_dmamap_t txmap;
1455
1456 DPRINTFN(2, ("msk_encap\n"));
1457
1458 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
1459 if (entry == NULL) {
1460 DPRINTFN(2, ("msk_encap: no txmap available\n"));
1461 return (ENOBUFS);
1462 }
1463 txmap = entry->dmamap;
1464
1465 cur = frag = *txidx;
1466
1467 #ifdef MSK_DEBUG
1468 if (mskdebug >= 2)
1469 msk_dump_mbuf(m_head);
1470 #endif
1471
1472 /*
1473 * Start packing the mbufs in this chain into
1474 * the fragment pointers. Stop when we run out
1475 * of fragments or hit the end of the mbuf chain.
1476 */
1477 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1478 BUS_DMA_NOWAIT)) {
1479 DPRINTFN(2, ("msk_encap: dmamap failed\n"));
1480 return (ENOBUFS);
1481 }
1482
1483 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) {
1484 DPRINTFN(2, ("msk_encap: too few descriptors free\n"));
1485 bus_dmamap_unload(sc->sc_dmatag, txmap);
1486 return (ENOBUFS);
1487 }
1488
1489 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
1490
1491 /* Sync the DMA map. */
1492 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1493 BUS_DMASYNC_PREWRITE);
1494
1495 for (i = 0; i < txmap->dm_nsegs; i++) {
1496 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1497 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr);
1498 f->sk_len = htole16(txmap->dm_segs[i].ds_len);
1499 f->sk_ctl = 0;
1500 if (i == 0)
1501 f->sk_opcode = SK_Y2_TXOPC_PACKET;
1502 else
1503 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN;
1504 cur = frag;
1505 SK_INC(frag, MSK_TX_RING_CNT);
1506 }
1507
1508 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1509 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
1510
1511 sc_if->sk_cdata.sk_tx_map[cur] = entry;
1512 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG;
1513
1514 /* Sync descriptors before handing to chip */
1515 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
1516 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1517
1518 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN;
1519
1520 /* Sync first descriptor to hand it off */
1521 MSK_CDTXSYNC(sc_if, *txidx, 1,
1522 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1523
1524 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs;
1525
1526 #ifdef MSK_DEBUG
1527 if (mskdebug >= 2) {
1528 struct msk_tx_desc *le;
1529 u_int32_t idx;
1530 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) {
1531 le = &sc_if->sk_rdata->sk_tx_ring[idx];
1532 msk_dump_txdesc(le, idx);
1533 }
1534 }
1535 #endif
1536
1537 *txidx = frag;
1538
1539 DPRINTFN(2, ("msk_encap: completed successfully\n"));
1540
1541 return (0);
1542 }
1543
1544 void
1545 msk_start(struct ifnet *ifp)
1546 {
1547 struct sk_if_softc *sc_if = ifp->if_softc;
1548 struct mbuf *m_head = NULL;
1549 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod;
1550 int pkts = 0;
1551
1552 DPRINTFN(2, ("msk_start\n"));
1553
1554 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1555 IFQ_POLL(&ifp->if_snd, m_head);
1556 if (m_head == NULL)
1557 break;
1558
1559 /*
1560 * Pack the data into the transmit ring. If we
1561 * don't have room, set the OACTIVE flag and wait
1562 * for the NIC to drain the ring.
1563 */
1564 if (msk_encap(sc_if, m_head, &idx)) {
1565 ifp->if_flags |= IFF_OACTIVE;
1566 break;
1567 }
1568
1569 /* now we are committed to transmit the packet */
1570 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1571 pkts++;
1572
1573 /*
1574 * If there's a BPF listener, bounce a copy of this frame
1575 * to him.
1576 */
1577 #if NBPFILTER > 0
1578 if (ifp->if_bpf)
1579 bpf_mtap(ifp->if_bpf, m_head);
1580 #endif
1581 }
1582 if (pkts == 0)
1583 return;
1584
1585 /* Transmit */
1586 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1587 sc_if->sk_cdata.sk_tx_prod = idx;
1588 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx);
1589
1590 /* Set a timeout in case the chip goes out to lunch. */
1591 ifp->if_timer = 5;
1592 }
1593 }
1594
1595 void
1596 msk_watchdog(struct ifnet *ifp)
1597 {
1598 struct sk_if_softc *sc_if = ifp->if_softc;
1599 u_int32_t reg;
1600 int idx;
1601
1602 /*
1603 * Reclaim first as there is a possibility of losing Tx completion
1604 * interrupts.
1605 */
1606 if (sc_if->sk_port == SK_PORT_A)
1607 reg = SK_STAT_BMU_TXA1_RIDX;
1608 else
1609 reg = SK_STAT_BMU_TXA2_RIDX;
1610
1611 idx = sk_win_read_2(sc_if->sk_softc, reg);
1612 if (sc_if->sk_cdata.sk_tx_cons != idx) {
1613 msk_txeof(sc_if, idx);
1614 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1615 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname);
1616
1617 ifp->if_oerrors++;
1618
1619 /* XXX Resets both ports; we shouldn't do that. */
1620 msk_reset(sc_if->sk_softc);
1621 msk_init(ifp);
1622 }
1623 }
1624 }
1625
1626 void
1627 mskc_shutdown(void *v)
1628 {
1629 struct sk_softc *sc = v;
1630
1631 DPRINTFN(2, ("msk_shutdown\n"));
1632
1633 /* Turn off the 'driver is loaded' LED. */
1634 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1635
1636 msk_reset(sc);
1637 }
1638
1639 __inline int
1640 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
1641 {
1642 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1643 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1644 YU_RXSTAT_JABBER)) != 0 ||
1645 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1646 YU_RXSTAT_BYTES(stat) != len)
1647 return (0);
1648
1649 return (1);
1650 }
1651
1652 void
1653 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat)
1654 {
1655 struct sk_softc *sc = sc_if->sk_softc;
1656 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
1657 struct mbuf *m;
1658 struct sk_chain *cur_rx;
1659 int cur, total_len = len;
1660 bus_dmamap_t dmamap;
1661
1662 DPRINTFN(2, ("msk_rxeof\n"));
1663
1664 cur = sc_if->sk_cdata.sk_rx_cons;
1665 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT);
1666 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT);
1667
1668 /* Sync the descriptor */
1669 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1670
1671 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
1672 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map;
1673
1674 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
1675 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1676
1677 m = cur_rx->sk_mbuf;
1678 cur_rx->sk_mbuf = NULL;
1679
1680 if (total_len < SK_MIN_FRAMELEN ||
1681 total_len > SK_JUMBO_FRAMELEN ||
1682 msk_rxvalid(sc, rxstat, total_len) == 0) {
1683 ifp->if_ierrors++;
1684 msk_newbuf(sc_if, cur, m, dmamap);
1685 return;
1686 }
1687
1688 /*
1689 * Try to allocate a new jumbo buffer. If that fails, copy the
1690 * packet to mbufs and put the jumbo buffer back in the ring
1691 * so it can be re-used. If allocating mbufs fails, then we
1692 * have to drop the packet.
1693 */
1694 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) {
1695 struct mbuf *m0;
1696 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1697 total_len + ETHER_ALIGN, 0, ifp, NULL);
1698 msk_newbuf(sc_if, cur, m, dmamap);
1699 if (m0 == NULL) {
1700 ifp->if_ierrors++;
1701 return;
1702 }
1703 m_adj(m0, ETHER_ALIGN);
1704 m = m0;
1705 } else {
1706 m->m_pkthdr.rcvif = ifp;
1707 m->m_pkthdr.len = m->m_len = total_len;
1708 }
1709
1710 ifp->if_ipackets++;
1711
1712 #if NBPFILTER > 0
1713 if (ifp->if_bpf)
1714 bpf_mtap(ifp->if_bpf, m);
1715 #endif
1716
1717 /* pass it on. */
1718 (*ifp->if_input)(ifp, m);
1719 }
1720
1721 void
1722 msk_txeof(struct sk_if_softc *sc_if, int idx)
1723 {
1724 struct sk_softc *sc = sc_if->sk_softc;
1725 struct msk_tx_desc *cur_tx;
1726 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
1727 u_int32_t sk_ctl;
1728 struct sk_txmap_entry *entry;
1729 int cons, prog;
1730
1731 DPRINTFN(2, ("msk_txeof\n"));
1732
1733 /*
1734 * Go through our tx ring and free mbufs for those
1735 * frames that have been sent.
1736 */
1737 cons = sc_if->sk_cdata.sk_tx_cons;
1738 prog = 0;
1739 while (cons != idx) {
1740 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
1741 break;
1742 prog++;
1743 MSK_CDTXSYNC(sc_if, cons, 1,
1744 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1745
1746 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons];
1747 sk_ctl = cur_tx->sk_ctl;
1748 #ifdef MSK_DEBUG
1749 if (mskdebug >= 2)
1750 msk_dump_txdesc(cur_tx, cons);
1751 #endif
1752 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG)
1753 ifp->if_opackets++;
1754 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) {
1755 entry = sc_if->sk_cdata.sk_tx_map[cons];
1756
1757 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
1758 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1759
1760 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
1761 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
1762 link);
1763 sc_if->sk_cdata.sk_tx_map[cons] = NULL;
1764 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf);
1765 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL;
1766 }
1767 sc_if->sk_cdata.sk_tx_cnt--;
1768 SK_INC(cons, MSK_TX_RING_CNT);
1769 }
1770 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
1771
1772 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2)
1773 ifp->if_flags &= ~IFF_OACTIVE;
1774
1775 if (prog > 0)
1776 sc_if->sk_cdata.sk_tx_cons = cons;
1777 }
1778
1779 void
1780 msk_tick(void *xsc_if)
1781 {
1782 struct sk_if_softc *sc_if = xsc_if;
1783 struct mii_data *mii = &sc_if->sk_mii;
1784
1785 mii_tick(mii);
1786 callout_schedule(&sc_if->sk_tick_ch, hz);
1787 }
1788
1789 void
1790 msk_intr_yukon(struct sk_if_softc *sc_if)
1791 {
1792 u_int8_t status;
1793
1794 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
1795 /* RX overrun */
1796 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
1797 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
1798 SK_RFCTL_RX_FIFO_OVER);
1799 }
1800 /* TX underrun */
1801 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
1802 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST,
1803 SK_TFCTL_TX_FIFO_UNDER);
1804 }
1805
1806 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status));
1807 }
1808
1809 int
1810 msk_intr(void *xsc)
1811 {
1812 struct sk_softc *sc = xsc;
1813 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
1814 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
1815 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1816 int claimed = 0;
1817 u_int32_t status;
1818 struct msk_status_desc *cur_st;
1819
1820 status = CSR_READ_4(sc, SK_Y2_ISSR2);
1821 if (status == 0) {
1822 CSR_WRITE_4(sc, SK_Y2_ICR, 2);
1823 return (0);
1824 }
1825
1826 status = CSR_READ_4(sc, SK_ISR);
1827
1828 if (sc_if0 != NULL)
1829 ifp0 = &sc_if0->sk_ethercom.ec_if;
1830 if (sc_if1 != NULL)
1831 ifp1 = &sc_if1->sk_ethercom.ec_if;
1832
1833 if (sc_if0 && (status & SK_Y2_IMR_MAC1) &&
1834 (ifp0->if_flags & IFF_RUNNING)) {
1835 msk_intr_yukon(sc_if0);
1836 }
1837
1838 if (sc_if1 && (status & SK_Y2_IMR_MAC2) &&
1839 (ifp1->if_flags & IFF_RUNNING)) {
1840 msk_intr_yukon(sc_if1);
1841 }
1842
1843 MSK_CDSTSYNC(sc, sc->sk_status_idx,
1844 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1845 cur_st = &sc->sk_status_ring[sc->sk_status_idx];
1846
1847 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) {
1848 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN;
1849 switch (cur_st->sk_opcode) {
1850 case SK_Y2_STOPC_RXSTAT:
1851 msk_rxeof(sc->sk_if[cur_st->sk_link],
1852 letoh16(cur_st->sk_len),
1853 letoh32(cur_st->sk_status));
1854 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0,
1855 SK_RXQ1_Y2_PREF_PUTIDX,
1856 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod);
1857 break;
1858 case SK_Y2_STOPC_TXSTAT:
1859 if (sc_if0)
1860 msk_txeof(sc_if0,
1861 letoh32(cur_st->sk_status)
1862 & SK_Y2_ST_TXA1_MSKL);
1863 if (sc_if1)
1864 msk_txeof(sc_if1,
1865 ((letoh32(cur_st->sk_status)
1866 & SK_Y2_ST_TXA2_MSKL)
1867 >> SK_Y2_ST_TXA2_SHIFTL)
1868 | ((letoh16(cur_st->sk_len) & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH));
1869 break;
1870 default:
1871 aprint_error("opcode=0x%x\n", cur_st->sk_opcode);
1872 break;
1873 }
1874 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT);
1875
1876 MSK_CDSTSYNC(sc, sc->sk_status_idx,
1877 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1878 cur_st = &sc->sk_status_ring[sc->sk_status_idx];
1879 }
1880
1881 if (status & SK_Y2_IMR_BMU) {
1882 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR);
1883 claimed = 1;
1884 }
1885
1886 CSR_WRITE_4(sc, SK_Y2_ICR, 2);
1887
1888 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd))
1889 msk_start(ifp0);
1890 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd))
1891 msk_start(ifp1);
1892
1893 #if NRND > 0
1894 if (RND_ENABLED(&sc->rnd_source))
1895 rnd_add_uint32(&sc->rnd_source, status);
1896 #endif
1897
1898 if (sc->sk_int_mod_pending)
1899 msk_update_int_mod(sc);
1900
1901 return claimed;
1902 }
1903
1904 void
1905 msk_init_yukon(struct sk_if_softc *sc_if)
1906 {
1907 u_int32_t v;
1908 u_int16_t reg;
1909 struct sk_softc *sc;
1910 int i;
1911
1912 sc = sc_if->sk_softc;
1913
1914 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n",
1915 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
1916
1917 DPRINTFN(6, ("msk_init_yukon: 1\n"));
1918
1919 /* GMAC and GPHY Reset */
1920 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
1921 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
1922 DELAY(1000);
1923
1924 DPRINTFN(6, ("msk_init_yukon: 2\n"));
1925
1926 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
1927 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
1928 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
1929
1930 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n",
1931 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
1932
1933 DPRINTFN(6, ("msk_init_yukon: 3\n"));
1934
1935 /* unused read of the interrupt source register */
1936 DPRINTFN(6, ("msk_init_yukon: 4\n"));
1937 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
1938
1939 DPRINTFN(6, ("msk_init_yukon: 4a\n"));
1940 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
1941 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
1942
1943 /* MIB Counter Clear Mode set */
1944 reg |= YU_PAR_MIB_CLR;
1945 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
1946 DPRINTFN(6, ("msk_init_yukon: 4b\n"));
1947 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
1948
1949 /* MIB Counter Clear Mode clear */
1950 DPRINTFN(6, ("msk_init_yukon: 5\n"));
1951 reg &= ~YU_PAR_MIB_CLR;
1952 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
1953
1954 /* receive control reg */
1955 DPRINTFN(6, ("msk_init_yukon: 7\n"));
1956 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
1957
1958 /* transmit control register */
1959 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10));
1960
1961 /* transmit flow control register */
1962 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff);
1963
1964 /* transmit parameter register */
1965 DPRINTFN(6, ("msk_init_yukon: 8\n"));
1966 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
1967 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04);
1968
1969 /* serial mode register */
1970 DPRINTFN(6, ("msk_init_yukon: 9\n"));
1971 reg = YU_SMR_DATA_BLIND(0x1c) |
1972 YU_SMR_MFL_VLAN |
1973 YU_SMR_IPG_DATA(0x1e);
1974
1975 if (sc->sk_type != SK_YUKON_FE)
1976 reg |= YU_SMR_MFL_JUMBO;
1977
1978 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
1979
1980 DPRINTFN(6, ("msk_init_yukon: 10\n"));
1981 /* Setup Yukon's address */
1982 for (i = 0; i < 3; i++) {
1983 /* Write Source Address 1 (unicast filter) */
1984 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
1985 sc_if->sk_enaddr[i * 2] |
1986 sc_if->sk_enaddr[i * 2 + 1] << 8);
1987 }
1988
1989 for (i = 0; i < 3; i++) {
1990 reg = sk_win_read_2(sc_if->sk_softc,
1991 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
1992 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
1993 }
1994
1995 /* Set promiscuous mode */
1996 msk_setpromisc(sc_if);
1997
1998 /* Set multicast filter */
1999 DPRINTFN(6, ("msk_init_yukon: 11\n"));
2000 msk_setmulti(sc_if);
2001
2002 /* enable interrupt mask for counter overflows */
2003 DPRINTFN(6, ("msk_init_yukon: 12\n"));
2004 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2005 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2006 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2007
2008 /* Configure RX MAC FIFO Flush Mask */
2009 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2010 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2011 YU_RXSTAT_JABBER;
2012 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2013
2014 /* Configure RX MAC FIFO */
2015 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2016 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON |
2017 SK_RFCTL_FIFO_FLUSH_ON);
2018
2019 /* Increase flush threshould to 64 bytes */
2020 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2021 SK_RFCTL_FIFO_THRESHOLD + 1);
2022
2023 /* Configure TX MAC FIFO */
2024 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2025 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2026
2027 #if 1
2028 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN);
2029 #endif
2030 DPRINTFN(6, ("msk_init_yukon: end\n"));
2031 }
2032
2033 /*
2034 * Note that to properly initialize any part of the GEnesis chip,
2035 * you first have to take it out of reset mode.
2036 */
2037 int
2038 msk_init(struct ifnet *ifp)
2039 {
2040 struct sk_if_softc *sc_if = ifp->if_softc;
2041 struct sk_softc *sc = sc_if->sk_softc;
2042 int rc = 0, s;
2043 uint32_t imr, imtimer_ticks;
2044
2045
2046 DPRINTFN(2, ("msk_init\n"));
2047
2048 s = splnet();
2049
2050 /* Cancel pending I/O and free all RX/TX buffers. */
2051 msk_stop(ifp,0);
2052
2053 /* Configure I2C registers */
2054
2055 /* Configure XMAC(s) */
2056 msk_init_yukon(sc_if);
2057 if ((rc = ether_mediachange(ifp)) != 0)
2058 goto out;
2059
2060 /* Configure transmit arbiter(s) */
2061 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON);
2062 #if 0
2063 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2064 #endif
2065
2066 /* Configure RAMbuffers */
2067 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2068 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2069 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2070 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2071 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2072 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2073
2074 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET);
2075 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON);
2076 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart);
2077 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart);
2078 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart);
2079 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend);
2080 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON);
2081
2082 /* Configure BMUs */
2083 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016);
2084 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28);
2085 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080);
2086 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */
2087
2088 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016);
2089 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28);
2090 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080);
2091 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */
2092
2093 /* Make sure the sync transmit queue is disabled. */
2094 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET);
2095
2096 /* Init descriptors */
2097 if (msk_init_rx_ring(sc_if) == ENOBUFS) {
2098 aprint_error("%s: initialization failed: no "
2099 "memory for rx buffers\n", sc_if->sk_dev.dv_xname);
2100 msk_stop(ifp,0);
2101 splx(s);
2102 return ENOBUFS;
2103 }
2104
2105 if (msk_init_tx_ring(sc_if) == ENOBUFS) {
2106 aprint_error("%s: initialization failed: no "
2107 "memory for tx buffers\n", sc_if->sk_dev.dv_xname);
2108 msk_stop(ifp,0);
2109 splx(s);
2110 return ENOBUFS;
2111 }
2112
2113 /* Set interrupt moderation if changed via sysctl. */
2114 switch (sc->sk_type) {
2115 case SK_YUKON_EC:
2116 case SK_YUKON_EC_U:
2117 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
2118 break;
2119 case SK_YUKON_FE:
2120 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
2121 break;
2122 case SK_YUKON_XL:
2123 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
2124 break;
2125 default:
2126 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
2127 }
2128 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2129 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
2130 sk_win_write_4(sc, SK_IMTIMERINIT,
2131 SK_IM_USECS(sc->sk_int_mod));
2132 aprint_verbose("%s: interrupt moderation is %d us\n",
2133 sc->sk_dev.dv_xname, sc->sk_int_mod);
2134 }
2135
2136 /* Initialize prefetch engine. */
2137 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
2138 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002);
2139 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1);
2140 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO,
2141 MSK_RX_RING_ADDR(sc_if, 0));
2142 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI,
2143 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32);
2144 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008);
2145 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR);
2146
2147 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
2148 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002);
2149 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1);
2150 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO,
2151 MSK_TX_RING_ADDR(sc_if, 0));
2152 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI,
2153 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32);
2154 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008);
2155 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR);
2156
2157 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
2158 sc_if->sk_cdata.sk_rx_prod);
2159
2160 /* Configure interrupt handling */
2161 if (sc_if->sk_port == SK_PORT_A)
2162 sc->sk_intrmask |= SK_Y2_INTRS1;
2163 else
2164 sc->sk_intrmask |= SK_Y2_INTRS2;
2165 sc->sk_intrmask |= SK_Y2_IMR_BMU;
2166 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2167
2168 ifp->if_flags |= IFF_RUNNING;
2169 ifp->if_flags &= ~IFF_OACTIVE;
2170
2171 callout_schedule(&sc_if->sk_tick_ch, hz);
2172
2173 out:
2174 splx(s);
2175 return rc;
2176 }
2177
2178 void
2179 msk_stop(struct ifnet *ifp, int disable)
2180 {
2181 struct sk_if_softc *sc_if = ifp->if_softc;
2182 struct sk_softc *sc = sc_if->sk_softc;
2183 struct sk_txmap_entry *dma;
2184 int i;
2185
2186 DPRINTFN(2, ("msk_stop\n"));
2187
2188 callout_stop(&sc_if->sk_tick_ch);
2189
2190 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2191
2192 /* Stop transfer of Tx descriptors */
2193
2194 /* Stop transfer of Rx descriptors */
2195
2196 /* Turn off various components of this interface. */
2197 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2198 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2199 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2200 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2201 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2202 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE);
2203 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2204 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2205 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2206 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP);
2207 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2208 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2209
2210 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
2211 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
2212
2213 /* Disable interrupts */
2214 if (sc_if->sk_port == SK_PORT_A)
2215 sc->sk_intrmask &= ~SK_Y2_INTRS1;
2216 else
2217 sc->sk_intrmask &= ~SK_Y2_INTRS2;
2218 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2219
2220 SK_XM_READ_2(sc_if, XM_ISR);
2221 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2222
2223 /* Free RX and TX mbufs still in the queues. */
2224 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2225 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2226 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2227 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2228 }
2229 }
2230
2231 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2232 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2233 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2234 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2235 #if 1
2236 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head,
2237 sc_if->sk_cdata.sk_tx_map[i], link);
2238 sc_if->sk_cdata.sk_tx_map[i] = 0;
2239 #endif
2240 }
2241 }
2242
2243 #if 1
2244 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) {
2245 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
2246 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap);
2247 free(dma, M_DEVBUF);
2248 }
2249 #endif
2250 }
2251
2252 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach,
2253 NULL, NULL);
2254
2255 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach,
2256 NULL, NULL);
2257
2258 #ifdef MSK_DEBUG
2259 void
2260 msk_dump_txdesc(struct msk_tx_desc *le, int idx)
2261 {
2262 #define DESC_PRINT(X) \
2263 if (X) \
2264 printf("txdesc[%d]." #X "=%#x\n", \
2265 idx, X);
2266
2267 DESC_PRINT(letoh32(le->sk_addr));
2268 DESC_PRINT(letoh16(le->sk_len));
2269 DESC_PRINT(le->sk_ctl);
2270 DESC_PRINT(le->sk_opcode);
2271 #undef DESC_PRINT
2272 }
2273
2274 void
2275 msk_dump_bytes(const char *data, int len)
2276 {
2277 int c, i, j;
2278
2279 for (i = 0; i < len; i += 16) {
2280 printf("%08x ", i);
2281 c = len - i;
2282 if (c > 16) c = 16;
2283
2284 for (j = 0; j < c; j++) {
2285 printf("%02x ", data[i + j] & 0xff);
2286 if ((j & 0xf) == 7 && j > 0)
2287 printf(" ");
2288 }
2289
2290 for (; j < 16; j++)
2291 printf(" ");
2292 printf(" ");
2293
2294 for (j = 0; j < c; j++) {
2295 int ch = data[i + j] & 0xff;
2296 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2297 }
2298
2299 printf("\n");
2300
2301 if (c < 16)
2302 break;
2303 }
2304 }
2305
2306 void
2307 msk_dump_mbuf(struct mbuf *m)
2308 {
2309 int count = m->m_pkthdr.len;
2310
2311 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2312
2313 while (count > 0 && m) {
2314 printf("m=%p, m->m_data=%p, m->m_len=%d\n",
2315 m, m->m_data, m->m_len);
2316 msk_dump_bytes(mtod(m, char *), m->m_len);
2317
2318 count -= m->m_len;
2319 m = m->m_next;
2320 }
2321 }
2322 #endif
2323
2324 static int
2325 msk_sysctl_handler(SYSCTLFN_ARGS)
2326 {
2327 int error, t;
2328 struct sysctlnode node;
2329 struct sk_softc *sc;
2330
2331 node = *rnode;
2332 sc = node.sysctl_data;
2333 t = sc->sk_int_mod;
2334 node.sysctl_data = &t;
2335 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2336 if (error || newp == NULL)
2337 return error;
2338
2339 if (t < SK_IM_MIN || t > SK_IM_MAX)
2340 return EINVAL;
2341
2342 /* update the softc with sysctl-changed value, and mark
2343 for hardware update */
2344 sc->sk_int_mod = t;
2345 sc->sk_int_mod_pending = 1;
2346 return 0;
2347 }
2348
2349 /*
2350 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be
2351 * set up in skc_attach()
2352 */
2353 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup")
2354 {
2355 int rc;
2356 const struct sysctlnode *node;
2357
2358 if ((rc = sysctl_createv(clog, 0, NULL, NULL,
2359 0, CTLTYPE_NODE, "hw", NULL,
2360 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
2361 goto err;
2362 }
2363
2364 if ((rc = sysctl_createv(clog, 0, NULL, &node,
2365 0, CTLTYPE_NODE, "msk",
2366 SYSCTL_DESCR("msk interface controls"),
2367 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
2368 goto err;
2369 }
2370
2371 msk_root_num = node->sysctl_num;
2372 return;
2373
2374 err:
2375 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
2376 }
2377