if_msk.c revision 1.20.2.1
1 /* $NetBSD: if_msk.c,v 1.20.2.1 2008/06/27 15:11:22 simonb Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.20.2.1 2008/06/27 15:11:22 simonb Exp $"); 56 57 #include "bpfilter.h" 58 #include "rnd.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/sockio.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/mutex.h> 66 #include <sys/kernel.h> 67 #include <sys/socket.h> 68 #include <sys/device.h> 69 #include <sys/queue.h> 70 #include <sys/callout.h> 71 #include <sys/sysctl.h> 72 #include <sys/endian.h> 73 #ifdef __NetBSD__ 74 #define letoh16 htole16 75 #define letoh32 htole32 76 #endif 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 82 #include <net/if_media.h> 83 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #endif 87 #if NRND > 0 88 #include <sys/rnd.h> 89 #endif 90 91 #include <dev/mii/mii.h> 92 #include <dev/mii/miivar.h> 93 #include <dev/mii/brgphyreg.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/pci/if_skreg.h> 100 #include <dev/pci/if_mskvar.h> 101 102 int mskc_probe(struct device *, struct cfdata *, void *); 103 void mskc_attach(struct device *, struct device *self, void *aux); 104 static bool mskc_suspend(device_t PMF_FN_PROTO); 105 static bool mskc_resume(device_t PMF_FN_PROTO); 106 int msk_probe(struct device *, struct cfdata *, void *); 107 void msk_attach(struct device *, struct device *self, void *aux); 108 int mskcprint(void *, const char *); 109 int msk_intr(void *); 110 void msk_intr_yukon(struct sk_if_softc *); 111 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 112 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 113 void msk_txeof(struct sk_if_softc *, int); 114 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 115 void msk_start(struct ifnet *); 116 int msk_ioctl(struct ifnet *, u_long, void *); 117 int msk_init(struct ifnet *); 118 void msk_init_yukon(struct sk_if_softc *); 119 void msk_stop(struct ifnet *, int); 120 void msk_watchdog(struct ifnet *); 121 void msk_reset(struct sk_softc *); 122 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 123 int msk_alloc_jumbo_mem(struct sk_if_softc *); 124 void *msk_jalloc(struct sk_if_softc *); 125 void msk_jfree(struct mbuf *, void *, size_t, void *); 126 int msk_init_rx_ring(struct sk_if_softc *); 127 int msk_init_tx_ring(struct sk_if_softc *); 128 129 void msk_update_int_mod(struct sk_softc *); 130 131 int msk_miibus_readreg(struct device *, int, int); 132 void msk_miibus_writereg(struct device *, int, int, int); 133 void msk_miibus_statchg(struct device *); 134 135 void msk_setfilt(struct sk_if_softc *, void *, int); 136 void msk_setmulti(struct sk_if_softc *); 137 void msk_setpromisc(struct sk_if_softc *); 138 void msk_tick(void *); 139 140 /* #define MSK_DEBUG 1 */ 141 #ifdef MSK_DEBUG 142 #define DPRINTF(x) if (mskdebug) printf x 143 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 144 int mskdebug = MSK_DEBUG; 145 146 void msk_dump_txdesc(struct msk_tx_desc *, int); 147 void msk_dump_mbuf(struct mbuf *); 148 void msk_dump_bytes(const char *, int); 149 #else 150 #define DPRINTF(x) 151 #define DPRINTFN(n,x) 152 #endif 153 154 static int msk_sysctl_handler(SYSCTLFN_PROTO); 155 static int msk_root_num; 156 157 /* supported device vendors */ 158 static const struct msk_product { 159 pci_vendor_id_t msk_vendor; 160 pci_product_id_t msk_product; 161 } msk_products[] = { 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 189 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 190 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 191 }; 192 193 static inline u_int32_t 194 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 195 { 196 return CSR_READ_4(sc, reg); 197 } 198 199 static inline u_int16_t 200 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 201 { 202 return CSR_READ_2(sc, reg); 203 } 204 205 static inline u_int8_t 206 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_1(sc, reg); 209 } 210 211 static inline void 212 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 213 { 214 CSR_WRITE_4(sc, reg, x); 215 } 216 217 static inline void 218 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 219 { 220 CSR_WRITE_2(sc, reg, x); 221 } 222 223 static inline void 224 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 225 { 226 CSR_WRITE_1(sc, reg, x); 227 } 228 229 int 230 msk_miibus_readreg(struct device *dev, int phy, int reg) 231 { 232 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 233 u_int16_t val; 234 int i; 235 236 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 237 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 238 239 for (i = 0; i < SK_TIMEOUT; i++) { 240 DELAY(1); 241 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 242 if (val & YU_SMICR_READ_VALID) 243 break; 244 } 245 246 if (i == SK_TIMEOUT) { 247 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 248 return (0); 249 } 250 251 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 252 SK_TIMEOUT)); 253 254 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 255 256 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 257 phy, reg, val)); 258 259 return (val); 260 } 261 262 void 263 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 264 { 265 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 266 int i; 267 268 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 269 phy, reg, val)); 270 271 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 272 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 273 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 274 275 for (i = 0; i < SK_TIMEOUT; i++) { 276 DELAY(1); 277 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 278 break; 279 } 280 281 if (i == SK_TIMEOUT) 282 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 283 } 284 285 void 286 msk_miibus_statchg(struct device *dev) 287 { 288 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 289 struct mii_data *mii = &sc_if->sk_mii; 290 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 291 int gpcr; 292 293 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 294 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 295 296 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 297 /* Set speed. */ 298 gpcr |= YU_GPCR_SPEED_DIS; 299 switch (IFM_SUBTYPE(mii->mii_media_active)) { 300 case IFM_1000_SX: 301 case IFM_1000_LX: 302 case IFM_1000_CX: 303 case IFM_1000_T: 304 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 305 break; 306 case IFM_100_TX: 307 gpcr |= YU_GPCR_SPEED; 308 break; 309 } 310 311 /* Set duplex. */ 312 gpcr |= YU_GPCR_DPLX_DIS; 313 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 314 gpcr |= YU_GPCR_DUPLEX; 315 316 /* Disable flow control. */ 317 gpcr |= YU_GPCR_FCTL_DIS; 318 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 319 } 320 321 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 322 323 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 324 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 325 } 326 327 #define HASH_BITS 6 328 329 void 330 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 331 { 332 char *addr = addrv; 333 int base = XM_RXFILT_ENTRY(slot); 334 335 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 336 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 337 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 338 } 339 340 void 341 msk_setmulti(struct sk_if_softc *sc_if) 342 { 343 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 344 u_int32_t hashes[2] = { 0, 0 }; 345 int h; 346 struct ethercom *ec = &sc_if->sk_ethercom; 347 struct ether_multi *enm; 348 struct ether_multistep step; 349 u_int16_t reg; 350 351 /* First, zot all the existing filters. */ 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 356 357 358 /* Now program new ones. */ 359 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 360 reg |= YU_RCR_UFLEN; 361 allmulti: 362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 363 if ((ifp->if_flags & IFF_PROMISC) != 0) 364 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 365 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 366 hashes[0] = 0xFFFFFFFF; 367 hashes[1] = 0xFFFFFFFF; 368 } 369 } else { 370 /* First find the tail of the list. */ 371 ETHER_FIRST_MULTI(step, ec, enm); 372 while (enm != NULL) { 373 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 374 ETHER_ADDR_LEN)) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 goto allmulti; 377 } 378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 379 ((1 << HASH_BITS) - 1); 380 if (h < 32) 381 hashes[0] |= (1 << h); 382 else 383 hashes[1] |= (1 << (h - 32)); 384 385 ETHER_NEXT_MULTI(step, enm); 386 } 387 reg |= YU_RCR_MUFLEN; 388 } 389 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 395 } 396 397 void 398 msk_setpromisc(struct sk_if_softc *sc_if) 399 { 400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 401 402 if (ifp->if_flags & IFF_PROMISC) 403 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 else 406 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 407 YU_RCR_UFLEN | YU_RCR_MUFLEN); 408 } 409 410 int 411 msk_init_rx_ring(struct sk_if_softc *sc_if) 412 { 413 struct msk_chain_data *cd = &sc_if->sk_cdata; 414 struct msk_ring_data *rd = sc_if->sk_rdata; 415 int i, nexti; 416 417 bzero((char *)rd->sk_rx_ring, 418 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 422 if (i == (MSK_RX_RING_CNT - 1)) 423 nexti = 0; 424 else 425 nexti = i + 1; 426 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 427 } 428 429 for (i = 0; i < MSK_RX_RING_CNT; i++) { 430 if (msk_newbuf(sc_if, i, NULL, 431 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 432 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 433 return (ENOBUFS); 434 } 435 } 436 437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 438 sc_if->sk_cdata.sk_rx_cons = 0; 439 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 490 bus_dmamap_t dmamap) 491 { 492 struct mbuf *m_new = NULL; 493 struct sk_chain *c; 494 struct msk_rx_desc *r; 495 496 if (m == NULL) { 497 void *buf = NULL; 498 499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 500 if (m_new == NULL) 501 return (ENOBUFS); 502 503 /* Allocate the jumbo buffer */ 504 buf = msk_jalloc(sc_if); 505 if (buf == NULL) { 506 m_freem(m_new); 507 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 509 return (ENOBUFS); 510 } 511 512 /* Attach the buffer to the mbuf */ 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 515 } else { 516 /* 517 * We're re-using a previously allocated mbuf; 518 * be sure to re-init pointers and lengths to 519 * default values. 520 */ 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 } 525 m_adj(m_new, ETHER_ALIGN); 526 527 c = &sc_if->sk_cdata.sk_rx_chain[i]; 528 r = c->sk_le; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 531 (((vaddr_t)m_new->m_data 532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 533 r->sk_len = htole16(SK_JLEN); 534 r->sk_ctl = 0; 535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 536 537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 538 539 return (0); 540 } 541 542 /* 543 * Memory management for jumbo frames. 544 */ 545 546 int 547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 548 { 549 struct sk_softc *sc = sc_if->sk_softc; 550 char *ptr, *kva; 551 bus_dma_segment_t seg; 552 int i, rseg, state, error; 553 struct sk_jpool_entry *entry; 554 555 state = error = 0; 556 557 /* Grab a big chunk o' storage. */ 558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 560 aprint_error(": can't alloc rx buffers"); 561 return (ENOBUFS); 562 } 563 564 state = 1; 565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 566 BUS_DMA_NOWAIT)) { 567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 2; 573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 575 aprint_error(": can't create dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 3; 581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 583 aprint_error(": can't load dma map"); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 4; 589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 591 592 LIST_INIT(&sc_if->sk_jfree_listhead); 593 LIST_INIT(&sc_if->sk_jinuse_listhead); 594 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 595 596 /* 597 * Now divide it up into 9K pieces and save the addresses 598 * in an array. 599 */ 600 ptr = sc_if->sk_cdata.sk_jumbo_buf; 601 for (i = 0; i < MSK_JSLOTS; i++) { 602 sc_if->sk_cdata.sk_jslots[i] = ptr; 603 ptr += SK_JLEN; 604 entry = malloc(sizeof(struct sk_jpool_entry), 605 M_DEVBUF, M_NOWAIT); 606 if (entry == NULL) { 607 sc_if->sk_cdata.sk_jumbo_buf = NULL; 608 aprint_error(": no memory for jumbo buffer queue!"); 609 error = ENOBUFS; 610 goto out; 611 } 612 entry->slot = i; 613 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 614 entry, jpool_entries); 615 } 616 out: 617 if (error != 0) { 618 switch (state) { 619 case 4: 620 bus_dmamap_unload(sc->sc_dmatag, 621 sc_if->sk_cdata.sk_rx_jumbo_map); 622 case 3: 623 bus_dmamap_destroy(sc->sc_dmatag, 624 sc_if->sk_cdata.sk_rx_jumbo_map); 625 case 2: 626 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 627 case 1: 628 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 629 break; 630 default: 631 break; 632 } 633 } 634 635 return (error); 636 } 637 638 /* 639 * Allocate a jumbo buffer. 640 */ 641 void * 642 msk_jalloc(struct sk_if_softc *sc_if) 643 { 644 struct sk_jpool_entry *entry; 645 646 mutex_enter(&sc_if->sk_jpool_mtx); 647 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 648 649 if (entry == NULL) { 650 mutex_exit(&sc_if->sk_jpool_mtx); 651 return NULL; 652 } 653 654 LIST_REMOVE(entry, jpool_entries); 655 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 656 mutex_exit(&sc_if->sk_jpool_mtx); 657 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 void 664 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 665 { 666 struct sk_jpool_entry *entry; 667 struct sk_if_softc *sc; 668 int i; 669 670 /* Extract the softc struct pointer. */ 671 sc = (struct sk_if_softc *)arg; 672 673 if (sc == NULL) 674 panic("msk_jfree: can't find softc pointer!"); 675 676 /* calculate the slot this buffer belongs to */ 677 i = ((vaddr_t)buf 678 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 679 680 if ((i < 0) || (i >= MSK_JSLOTS)) 681 panic("msk_jfree: asked to free buffer that we don't manage!"); 682 683 mutex_enter(&sc->sk_jpool_mtx); 684 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 685 if (entry == NULL) 686 panic("msk_jfree: buffer not in use!"); 687 entry->slot = i; 688 LIST_REMOVE(entry, jpool_entries); 689 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 690 mutex_exit(&sc->sk_jpool_mtx); 691 692 if (__predict_true(m != NULL)) 693 pool_cache_put(mb_cache, m); 694 } 695 696 int 697 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 698 { 699 struct sk_if_softc *sc_if = ifp->if_softc; 700 int s, error = 0; 701 702 s = splnet(); 703 704 DPRINTFN(2, ("msk_ioctl ETHER\n")); 705 error = ether_ioctl(ifp, cmd, data); 706 707 if (error == ENETRESET) { 708 error = 0; 709 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 710 ; 711 else if (ifp->if_flags & IFF_RUNNING) { 712 /* 713 * Multicast list has changed; set the hardware 714 * filter accordingly. 715 */ 716 msk_setmulti(sc_if); 717 } 718 } 719 720 splx(s); 721 return (error); 722 } 723 724 void 725 msk_update_int_mod(struct sk_softc *sc) 726 { 727 u_int32_t imtimer_ticks; 728 729 /* 730 * Configure interrupt moderation. The moderation timer 731 * defers interrupts specified in the interrupt moderation 732 * timer mask based on the timeout specified in the interrupt 733 * moderation timer init register. Each bit in the timer 734 * register represents one tick, so to specify a timeout in 735 * microseconds, we have to multiply by the correct number of 736 * ticks-per-microsecond. 737 */ 738 switch (sc->sk_type) { 739 case SK_YUKON_EC: 740 case SK_YUKON_EC_U: 741 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 742 break; 743 case SK_YUKON_FE: 744 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 745 break; 746 case SK_YUKON_XL: 747 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 748 break; 749 default: 750 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 751 } 752 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 753 sc->sk_int_mod); 754 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 755 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 756 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 757 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 758 sc->sk_int_mod_pending = 0; 759 } 760 761 static int 762 msk_lookup(const struct pci_attach_args *pa) 763 { 764 const struct msk_product *pmsk; 765 766 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 767 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 768 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 769 return 1; 770 } 771 return 0; 772 } 773 774 /* 775 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 776 * IDs against our list and return a device name if we find a match. 777 */ 778 int 779 mskc_probe(struct device *parent, struct cfdata *match, 780 void *aux) 781 { 782 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 783 784 return msk_lookup(pa); 785 } 786 787 /* 788 * Force the GEnesis into reset, then bring it out of reset. 789 */ 790 void msk_reset(struct sk_softc *sc) 791 { 792 u_int32_t imtimer_ticks, reg1; 793 int reg; 794 795 DPRINTFN(2, ("msk_reset\n")); 796 797 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 798 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 799 800 DELAY(1000); 801 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 802 DELAY(2); 803 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 804 sk_win_write_1(sc, SK_TESTCTL1, 2); 805 806 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 807 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 808 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 809 else 810 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 811 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 812 813 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 814 sk_win_write_1(sc, SK_Y2_CLKGATE, 815 SK_Y2_CLKGATE_LINK1_GATE_DIS | 816 SK_Y2_CLKGATE_LINK2_GATE_DIS | 817 SK_Y2_CLKGATE_LINK1_CORE_DIS | 818 SK_Y2_CLKGATE_LINK2_CORE_DIS | 819 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 820 else 821 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 822 823 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 824 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 825 DELAY(1000); 826 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 827 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 828 829 sk_win_write_1(sc, SK_TESTCTL1, 1); 830 831 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 832 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 833 CSR_READ_2(sc, SK_LINK_CTRL))); 834 835 /* Disable ASF */ 836 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 837 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 838 839 /* Clear I2C IRQ noise */ 840 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 841 842 /* Disable hardware timer */ 843 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 844 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 845 846 /* Disable descriptor polling */ 847 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 848 849 /* Disable time stamps */ 850 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 851 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 852 853 /* Enable RAM interface */ 854 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 855 for (reg = SK_TO0;reg <= SK_TO11; reg++) 856 sk_win_write_1(sc, reg, 36); 857 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 858 for (reg = SK_TO0;reg <= SK_TO11; reg++) 859 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 860 861 /* 862 * Configure interrupt moderation. The moderation timer 863 * defers interrupts specified in the interrupt moderation 864 * timer mask based on the timeout specified in the interrupt 865 * moderation timer init register. Each bit in the timer 866 * register represents one tick, so to specify a timeout in 867 * microseconds, we have to multiply by the correct number of 868 * ticks-per-microsecond. 869 */ 870 switch (sc->sk_type) { 871 case SK_YUKON_EC: 872 case SK_YUKON_EC_U: 873 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 874 break; 875 case SK_YUKON_FE: 876 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 877 break; 878 case SK_YUKON_XL: 879 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 880 break; 881 default: 882 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 883 } 884 885 /* Reset status ring. */ 886 bzero((char *)sc->sk_status_ring, 887 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 888 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 889 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 890 sc->sk_status_idx = 0; 891 sc->sk_status_own_idx = 0; 892 893 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 894 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 895 896 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 897 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 898 sc->sk_status_map->dm_segs[0].ds_addr); 899 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 900 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 901 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 902 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 903 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 904 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 905 } else { 906 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 907 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 908 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 909 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 910 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 911 } 912 913 #if 0 914 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 915 #endif 916 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 917 918 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 919 920 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 921 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 922 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 923 924 msk_update_int_mod(sc); 925 } 926 927 int 928 msk_probe(struct device *parent, struct cfdata *match, 929 void *aux) 930 { 931 struct skc_attach_args *sa = aux; 932 933 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 934 return (0); 935 936 switch (sa->skc_type) { 937 case SK_YUKON_XL: 938 case SK_YUKON_EC_U: 939 case SK_YUKON_EC: 940 case SK_YUKON_FE: 941 return (1); 942 } 943 944 return (0); 945 } 946 947 static bool 948 msk_resume(device_t dv PMF_FN_ARGS) 949 { 950 struct sk_if_softc *sc_if = device_private(dv); 951 952 msk_init_yukon(sc_if); 953 return true; 954 } 955 956 /* 957 * Each XMAC chip is attached as a separate logical IP interface. 958 * Single port cards will have only one logical interface of course. 959 */ 960 void 961 msk_attach(struct device *parent, struct device *self, void *aux) 962 { 963 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 964 struct sk_softc *sc = (struct sk_softc *)parent; 965 struct skc_attach_args *sa = aux; 966 struct ifnet *ifp; 967 void *kva; 968 bus_dma_segment_t seg; 969 int i, rseg; 970 u_int32_t chunk, val; 971 972 sc_if->sk_port = sa->skc_port; 973 sc_if->sk_softc = sc; 974 sc->sk_if[sa->skc_port] = sc_if; 975 976 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 977 978 /* 979 * Get station address for this interface. Note that 980 * dual port cards actually come with three station 981 * addresses: one for each port, plus an extra. The 982 * extra one is used by the SysKonnect driver software 983 * as a 'virtual' station address for when both ports 984 * are operating in failover mode. Currently we don't 985 * use this extra address. 986 */ 987 for (i = 0; i < ETHER_ADDR_LEN; i++) 988 sc_if->sk_enaddr[i] = 989 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 990 991 aprint_normal(": Ethernet address %s\n", 992 ether_sprintf(sc_if->sk_enaddr)); 993 994 /* 995 * Set up RAM buffer addresses. The NIC will have a certain 996 * amount of SRAM on it, somewhere between 512K and 2MB. We 997 * need to divide this up a) between the transmitter and 998 * receiver and b) between the two XMACs, if this is a 999 * dual port NIC. Our algorithm is to divide up the memory 1000 * evenly so that everyone gets a fair share. 1001 * 1002 * Just to be contrary, Yukon2 appears to have separate memory 1003 * for each MAC. 1004 */ 1005 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1006 val = sc->sk_rboff / sizeof(u_int64_t); 1007 sc_if->sk_rx_ramstart = val; 1008 val += (chunk / sizeof(u_int64_t)); 1009 sc_if->sk_rx_ramend = val - 1; 1010 chunk = sc->sk_ramsize - chunk; 1011 sc_if->sk_tx_ramstart = val; 1012 val += (chunk / sizeof(u_int64_t)); 1013 sc_if->sk_tx_ramend = val - 1; 1014 1015 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1016 " tx_ramstart=%#x tx_ramend=%#x\n", 1017 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1018 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1019 1020 /* Allocate the descriptor queues. */ 1021 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1022 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1023 aprint_error(": can't alloc rx buffers\n"); 1024 goto fail; 1025 } 1026 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1027 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1028 aprint_error(": can't map dma buffers (%zu bytes)\n", 1029 sizeof(struct msk_ring_data)); 1030 goto fail_1; 1031 } 1032 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1033 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1034 &sc_if->sk_ring_map)) { 1035 aprint_error(": can't create dma map\n"); 1036 goto fail_2; 1037 } 1038 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1039 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1040 aprint_error(": can't load dma map\n"); 1041 goto fail_3; 1042 } 1043 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1044 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1045 1046 ifp = &sc_if->sk_ethercom.ec_if; 1047 /* Try to allocate memory for jumbo buffers. */ 1048 if (msk_alloc_jumbo_mem(sc_if)) { 1049 aprint_error(": jumbo buffer allocation failed\n"); 1050 goto fail_3; 1051 } 1052 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1053 if (sc->sk_type != SK_YUKON_FE) 1054 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1055 1056 ifp->if_softc = sc_if; 1057 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1058 ifp->if_ioctl = msk_ioctl; 1059 ifp->if_start = msk_start; 1060 ifp->if_stop = msk_stop; 1061 ifp->if_init = msk_init; 1062 ifp->if_watchdog = msk_watchdog; 1063 ifp->if_baudrate = 1000000000; 1064 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1065 IFQ_SET_READY(&ifp->if_snd); 1066 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1067 1068 /* 1069 * Do miibus setup. 1070 */ 1071 msk_init_yukon(sc_if); 1072 1073 DPRINTFN(2, ("msk_attach: 1\n")); 1074 1075 sc_if->sk_mii.mii_ifp = ifp; 1076 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1077 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1078 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1079 1080 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1081 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1082 ether_mediachange, ether_mediastatus); 1083 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1084 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1085 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1086 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1087 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1088 0, NULL); 1089 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1090 } else 1091 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1092 1093 callout_init(&sc_if->sk_tick_ch, 0); 1094 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1095 callout_schedule(&sc_if->sk_tick_ch, hz); 1096 1097 /* 1098 * Call MI attach routines. 1099 */ 1100 if_attach(ifp); 1101 ether_ifattach(ifp, sc_if->sk_enaddr); 1102 1103 if (!pmf_device_register(self, NULL, msk_resume)) 1104 aprint_error_dev(self, "couldn't establish power handler\n"); 1105 else 1106 pmf_class_network_register(self, ifp); 1107 1108 #if NRND > 0 1109 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1110 RND_TYPE_NET, 0); 1111 #endif 1112 1113 DPRINTFN(2, ("msk_attach: end\n")); 1114 return; 1115 1116 fail_3: 1117 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1118 fail_2: 1119 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1120 fail_1: 1121 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1122 fail: 1123 sc->sk_if[sa->skc_port] = NULL; 1124 } 1125 1126 int 1127 mskcprint(void *aux, const char *pnp) 1128 { 1129 struct skc_attach_args *sa = aux; 1130 1131 if (pnp) 1132 aprint_normal("sk port %c at %s", 1133 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1134 else 1135 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1136 return (UNCONF); 1137 } 1138 1139 /* 1140 * Attach the interface. Allocate softc structures, do ifmedia 1141 * setup and ethernet/BPF attach. 1142 */ 1143 void 1144 mskc_attach(struct device *parent, struct device *self, void *aux) 1145 { 1146 struct sk_softc *sc = (struct sk_softc *)self; 1147 struct pci_attach_args *pa = aux; 1148 struct skc_attach_args skca; 1149 pci_chipset_tag_t pc = pa->pa_pc; 1150 pcireg_t command, memtype; 1151 pci_intr_handle_t ih; 1152 const char *intrstr = NULL; 1153 bus_size_t size; 1154 int rc, sk_nodenum; 1155 u_int8_t hw, skrs; 1156 const char *revstr = NULL; 1157 const struct sysctlnode *node; 1158 void *kva; 1159 bus_dma_segment_t seg; 1160 int rseg; 1161 1162 DPRINTFN(2, ("begin mskc_attach\n")); 1163 1164 /* 1165 * Handle power management nonsense. 1166 */ 1167 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1168 1169 if (command == 0x01) { 1170 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1171 if (command & SK_PSTATE_MASK) { 1172 u_int32_t iobase, membase, irq; 1173 1174 /* Save important PCI config data. */ 1175 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1176 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1177 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1178 1179 /* Reset the power state. */ 1180 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1181 "-- setting to D0\n", 1182 command & SK_PSTATE_MASK); 1183 command &= 0xFFFFFFFC; 1184 pci_conf_write(pc, pa->pa_tag, 1185 SK_PCI_PWRMGMTCTRL, command); 1186 1187 /* Restore PCI config data. */ 1188 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1189 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1190 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1191 } 1192 } 1193 1194 /* 1195 * Map control/status registers. 1196 */ 1197 1198 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1199 switch (memtype) { 1200 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1201 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1202 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1203 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1204 NULL, &size) == 0) 1205 break; 1206 default: 1207 aprint_error(": can't map mem space\n"); 1208 return; 1209 } 1210 1211 sc->sc_dmatag = pa->pa_dmat; 1212 1213 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1214 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1215 1216 /* bail out here if chip is not recognized */ 1217 if (!(SK_IS_YUKON2(sc))) { 1218 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1219 goto fail_1; 1220 } 1221 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1222 1223 /* Allocate interrupt */ 1224 if (pci_intr_map(pa, &ih)) { 1225 aprint_error(": couldn't map interrupt\n"); 1226 goto fail_1; 1227 } 1228 1229 intrstr = pci_intr_string(pc, ih); 1230 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1231 if (sc->sk_intrhand == NULL) { 1232 aprint_error(": couldn't establish interrupt"); 1233 if (intrstr != NULL) 1234 aprint_error(" at %s", intrstr); 1235 aprint_error("\n"); 1236 goto fail_1; 1237 } 1238 1239 if (bus_dmamem_alloc(sc->sc_dmatag, 1240 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1241 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1242 aprint_error(": can't alloc status buffers\n"); 1243 goto fail_2; 1244 } 1245 1246 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1247 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1248 &kva, BUS_DMA_NOWAIT)) { 1249 aprint_error(": can't map dma buffers (%zu bytes)\n", 1250 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1251 goto fail_3; 1252 } 1253 if (bus_dmamap_create(sc->sc_dmatag, 1254 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1255 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1256 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1257 aprint_error(": can't create dma map\n"); 1258 goto fail_4; 1259 } 1260 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1261 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1262 NULL, BUS_DMA_NOWAIT)) { 1263 aprint_error(": can't load dma map\n"); 1264 goto fail_5; 1265 } 1266 sc->sk_status_ring = (struct msk_status_desc *)kva; 1267 1268 /* Reset the adapter. */ 1269 msk_reset(sc); 1270 1271 skrs = sk_win_read_1(sc, SK_EPROM0); 1272 if (skrs == 0x00) 1273 sc->sk_ramsize = 0x20000; 1274 else 1275 sc->sk_ramsize = skrs * (1<<12); 1276 sc->sk_rboff = SK_RBOFF_0; 1277 1278 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1279 sc->sk_ramsize, sc->sk_ramsize / 1024, 1280 sc->sk_rboff)); 1281 1282 switch (sc->sk_type) { 1283 case SK_YUKON_XL: 1284 sc->sk_name = "Yukon-2 XL"; 1285 break; 1286 case SK_YUKON_EC_U: 1287 sc->sk_name = "Yukon-2 EC Ultra"; 1288 break; 1289 case SK_YUKON_EC: 1290 sc->sk_name = "Yukon-2 EC"; 1291 break; 1292 case SK_YUKON_FE: 1293 sc->sk_name = "Yukon-2 FE"; 1294 break; 1295 default: 1296 sc->sk_name = "Yukon (Unknown)"; 1297 } 1298 1299 if (sc->sk_type == SK_YUKON_XL) { 1300 switch (sc->sk_rev) { 1301 case SK_YUKON_XL_REV_A0: 1302 sc->sk_workaround = 0; 1303 revstr = "A0"; 1304 break; 1305 case SK_YUKON_XL_REV_A1: 1306 sc->sk_workaround = SK_WA_4109; 1307 revstr = "A1"; 1308 break; 1309 case SK_YUKON_XL_REV_A2: 1310 sc->sk_workaround = SK_WA_4109; 1311 revstr = "A2"; 1312 break; 1313 case SK_YUKON_XL_REV_A3: 1314 sc->sk_workaround = SK_WA_4109; 1315 revstr = "A3"; 1316 break; 1317 default: 1318 sc->sk_workaround = 0; 1319 break; 1320 } 1321 } 1322 1323 if (sc->sk_type == SK_YUKON_EC) { 1324 switch (sc->sk_rev) { 1325 case SK_YUKON_EC_REV_A1: 1326 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1327 revstr = "A1"; 1328 break; 1329 case SK_YUKON_EC_REV_A2: 1330 sc->sk_workaround = SK_WA_4109; 1331 revstr = "A2"; 1332 break; 1333 case SK_YUKON_EC_REV_A3: 1334 sc->sk_workaround = SK_WA_4109; 1335 revstr = "A3"; 1336 break; 1337 default: 1338 sc->sk_workaround = 0; 1339 break; 1340 } 1341 } 1342 1343 if (sc->sk_type == SK_YUKON_FE) { 1344 sc->sk_workaround = SK_WA_4109; 1345 switch (sc->sk_rev) { 1346 case SK_YUKON_FE_REV_A1: 1347 revstr = "A1"; 1348 break; 1349 case SK_YUKON_FE_REV_A2: 1350 revstr = "A2"; 1351 break; 1352 default: 1353 sc->sk_workaround = 0; 1354 break; 1355 } 1356 } 1357 1358 if (sc->sk_type == SK_YUKON_EC_U) { 1359 sc->sk_workaround = SK_WA_4109; 1360 switch (sc->sk_rev) { 1361 case SK_YUKON_EC_U_REV_A0: 1362 revstr = "A0"; 1363 break; 1364 case SK_YUKON_EC_U_REV_A1: 1365 revstr = "A1"; 1366 break; 1367 case SK_YUKON_EC_U_REV_B0: 1368 revstr = "B0"; 1369 break; 1370 default: 1371 sc->sk_workaround = 0; 1372 break; 1373 } 1374 } 1375 1376 /* Announce the product name. */ 1377 aprint_normal(", %s", sc->sk_name); 1378 if (revstr != NULL) 1379 aprint_normal(" rev. %s", revstr); 1380 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1381 1382 sc->sk_macs = 1; 1383 1384 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1385 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1386 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1387 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1388 sc->sk_macs++; 1389 } 1390 1391 skca.skc_port = SK_PORT_A; 1392 skca.skc_type = sc->sk_type; 1393 skca.skc_rev = sc->sk_rev; 1394 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1395 1396 if (sc->sk_macs > 1) { 1397 skca.skc_port = SK_PORT_B; 1398 skca.skc_type = sc->sk_type; 1399 skca.skc_rev = sc->sk_rev; 1400 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1401 } 1402 1403 /* Turn on the 'driver is loaded' LED. */ 1404 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1405 1406 /* skc sysctl setup */ 1407 1408 sc->sk_int_mod = SK_IM_DEFAULT; 1409 sc->sk_int_mod_pending = 0; 1410 1411 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1412 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1413 SYSCTL_DESCR("mskc per-controller controls"), 1414 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1415 CTL_EOL)) != 0) { 1416 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1417 goto fail_6; 1418 } 1419 1420 sk_nodenum = node->sysctl_num; 1421 1422 /* interrupt moderation time in usecs */ 1423 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1424 CTLFLAG_READWRITE, 1425 CTLTYPE_INT, "int_mod", 1426 SYSCTL_DESCR("msk interrupt moderation timer"), 1427 msk_sysctl_handler, 0, sc, 1428 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1429 CTL_EOL)) != 0) { 1430 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1431 goto fail_6; 1432 } 1433 1434 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1435 aprint_error_dev(self, "couldn't establish power handler\n"); 1436 1437 return; 1438 1439 fail_6: 1440 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1441 fail_5: 1442 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1443 fail_4: 1444 bus_dmamem_unmap(sc->sc_dmatag, kva, 1445 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1446 fail_3: 1447 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1448 fail_2: 1449 pci_intr_disestablish(pc, sc->sk_intrhand); 1450 fail_1: 1451 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1452 } 1453 1454 int 1455 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1456 { 1457 struct sk_softc *sc = sc_if->sk_softc; 1458 struct msk_tx_desc *f = NULL; 1459 u_int32_t frag, cur; 1460 int i; 1461 struct sk_txmap_entry *entry; 1462 bus_dmamap_t txmap; 1463 1464 DPRINTFN(2, ("msk_encap\n")); 1465 1466 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1467 if (entry == NULL) { 1468 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1469 return (ENOBUFS); 1470 } 1471 txmap = entry->dmamap; 1472 1473 cur = frag = *txidx; 1474 1475 #ifdef MSK_DEBUG 1476 if (mskdebug >= 2) 1477 msk_dump_mbuf(m_head); 1478 #endif 1479 1480 /* 1481 * Start packing the mbufs in this chain into 1482 * the fragment pointers. Stop when we run out 1483 * of fragments or hit the end of the mbuf chain. 1484 */ 1485 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1486 BUS_DMA_NOWAIT)) { 1487 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1488 return (ENOBUFS); 1489 } 1490 1491 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1492 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1493 bus_dmamap_unload(sc->sc_dmatag, txmap); 1494 return (ENOBUFS); 1495 } 1496 1497 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1498 1499 /* Sync the DMA map. */ 1500 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1501 BUS_DMASYNC_PREWRITE); 1502 1503 for (i = 0; i < txmap->dm_nsegs; i++) { 1504 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1505 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1506 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1507 f->sk_ctl = 0; 1508 if (i == 0) 1509 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1510 else 1511 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1512 cur = frag; 1513 SK_INC(frag, MSK_TX_RING_CNT); 1514 } 1515 1516 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1517 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1518 1519 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1520 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1521 1522 /* Sync descriptors before handing to chip */ 1523 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1524 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1525 1526 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1527 1528 /* Sync first descriptor to hand it off */ 1529 MSK_CDTXSYNC(sc_if, *txidx, 1, 1530 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1531 1532 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1533 1534 #ifdef MSK_DEBUG 1535 if (mskdebug >= 2) { 1536 struct msk_tx_desc *le; 1537 u_int32_t idx; 1538 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1539 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1540 msk_dump_txdesc(le, idx); 1541 } 1542 } 1543 #endif 1544 1545 *txidx = frag; 1546 1547 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1548 1549 return (0); 1550 } 1551 1552 void 1553 msk_start(struct ifnet *ifp) 1554 { 1555 struct sk_if_softc *sc_if = ifp->if_softc; 1556 struct mbuf *m_head = NULL; 1557 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1558 int pkts = 0; 1559 1560 DPRINTFN(2, ("msk_start\n")); 1561 1562 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1563 IFQ_POLL(&ifp->if_snd, m_head); 1564 if (m_head == NULL) 1565 break; 1566 1567 /* 1568 * Pack the data into the transmit ring. If we 1569 * don't have room, set the OACTIVE flag and wait 1570 * for the NIC to drain the ring. 1571 */ 1572 if (msk_encap(sc_if, m_head, &idx)) { 1573 ifp->if_flags |= IFF_OACTIVE; 1574 break; 1575 } 1576 1577 /* now we are committed to transmit the packet */ 1578 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1579 pkts++; 1580 1581 /* 1582 * If there's a BPF listener, bounce a copy of this frame 1583 * to him. 1584 */ 1585 #if NBPFILTER > 0 1586 if (ifp->if_bpf) 1587 bpf_mtap(ifp->if_bpf, m_head); 1588 #endif 1589 } 1590 if (pkts == 0) 1591 return; 1592 1593 /* Transmit */ 1594 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1595 sc_if->sk_cdata.sk_tx_prod = idx; 1596 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1597 1598 /* Set a timeout in case the chip goes out to lunch. */ 1599 ifp->if_timer = 5; 1600 } 1601 } 1602 1603 void 1604 msk_watchdog(struct ifnet *ifp) 1605 { 1606 struct sk_if_softc *sc_if = ifp->if_softc; 1607 u_int32_t reg; 1608 int idx; 1609 1610 /* 1611 * Reclaim first as there is a possibility of losing Tx completion 1612 * interrupts. 1613 */ 1614 if (sc_if->sk_port == SK_PORT_A) 1615 reg = SK_STAT_BMU_TXA1_RIDX; 1616 else 1617 reg = SK_STAT_BMU_TXA2_RIDX; 1618 1619 idx = sk_win_read_2(sc_if->sk_softc, reg); 1620 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1621 msk_txeof(sc_if, idx); 1622 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1623 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1624 1625 ifp->if_oerrors++; 1626 1627 /* XXX Resets both ports; we shouldn't do that. */ 1628 msk_reset(sc_if->sk_softc); 1629 msk_init(ifp); 1630 } 1631 } 1632 } 1633 1634 static bool 1635 mskc_suspend(device_t dv PMF_FN_ARGS) 1636 { 1637 struct sk_softc *sc = device_private(dv); 1638 1639 DPRINTFN(2, ("mskc_suspend\n")); 1640 1641 /* Turn off the 'driver is loaded' LED. */ 1642 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1643 1644 return true; 1645 } 1646 1647 static bool 1648 mskc_resume(device_t dv PMF_FN_ARGS) 1649 { 1650 struct sk_softc *sc = device_private(dv); 1651 1652 DPRINTFN(2, ("mskc_resume\n")); 1653 1654 msk_reset(sc); 1655 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1656 1657 return true; 1658 } 1659 1660 __inline int 1661 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1662 { 1663 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1664 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1665 YU_RXSTAT_JABBER)) != 0 || 1666 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1667 YU_RXSTAT_BYTES(stat) != len) 1668 return (0); 1669 1670 return (1); 1671 } 1672 1673 void 1674 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1675 { 1676 struct sk_softc *sc = sc_if->sk_softc; 1677 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1678 struct mbuf *m; 1679 struct sk_chain *cur_rx; 1680 int cur, total_len = len; 1681 bus_dmamap_t dmamap; 1682 1683 DPRINTFN(2, ("msk_rxeof\n")); 1684 1685 cur = sc_if->sk_cdata.sk_rx_cons; 1686 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1687 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1688 1689 /* Sync the descriptor */ 1690 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1691 1692 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1693 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1694 1695 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1696 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1697 1698 m = cur_rx->sk_mbuf; 1699 cur_rx->sk_mbuf = NULL; 1700 1701 if (total_len < SK_MIN_FRAMELEN || 1702 total_len > ETHER_MAX_LEN_JUMBO || 1703 msk_rxvalid(sc, rxstat, total_len) == 0) { 1704 ifp->if_ierrors++; 1705 msk_newbuf(sc_if, cur, m, dmamap); 1706 return; 1707 } 1708 1709 /* 1710 * Try to allocate a new jumbo buffer. If that fails, copy the 1711 * packet to mbufs and put the jumbo buffer back in the ring 1712 * so it can be re-used. If allocating mbufs fails, then we 1713 * have to drop the packet. 1714 */ 1715 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1716 struct mbuf *m0; 1717 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1718 total_len + ETHER_ALIGN, 0, ifp, NULL); 1719 msk_newbuf(sc_if, cur, m, dmamap); 1720 if (m0 == NULL) { 1721 ifp->if_ierrors++; 1722 return; 1723 } 1724 m_adj(m0, ETHER_ALIGN); 1725 m = m0; 1726 } else { 1727 m->m_pkthdr.rcvif = ifp; 1728 m->m_pkthdr.len = m->m_len = total_len; 1729 } 1730 1731 ifp->if_ipackets++; 1732 1733 #if NBPFILTER > 0 1734 if (ifp->if_bpf) 1735 bpf_mtap(ifp->if_bpf, m); 1736 #endif 1737 1738 /* pass it on. */ 1739 (*ifp->if_input)(ifp, m); 1740 } 1741 1742 void 1743 msk_txeof(struct sk_if_softc *sc_if, int idx) 1744 { 1745 struct sk_softc *sc = sc_if->sk_softc; 1746 struct msk_tx_desc *cur_tx; 1747 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1748 u_int32_t sk_ctl; 1749 struct sk_txmap_entry *entry; 1750 int cons, prog; 1751 1752 DPRINTFN(2, ("msk_txeof\n")); 1753 1754 /* 1755 * Go through our tx ring and free mbufs for those 1756 * frames that have been sent. 1757 */ 1758 cons = sc_if->sk_cdata.sk_tx_cons; 1759 prog = 0; 1760 while (cons != idx) { 1761 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1762 break; 1763 prog++; 1764 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1765 1766 MSK_CDTXSYNC(sc_if, cons, 1, 1767 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1768 sk_ctl = cur_tx->sk_ctl; 1769 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1770 #ifdef MSK_DEBUG 1771 if (mskdebug >= 2) 1772 msk_dump_txdesc(cur_tx, cons); 1773 #endif 1774 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1775 ifp->if_opackets++; 1776 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1777 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1778 1779 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1780 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1781 1782 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1783 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1784 link); 1785 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1786 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1787 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1788 } 1789 sc_if->sk_cdata.sk_tx_cnt--; 1790 SK_INC(cons, MSK_TX_RING_CNT); 1791 } 1792 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1793 1794 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1795 ifp->if_flags &= ~IFF_OACTIVE; 1796 1797 if (prog > 0) 1798 sc_if->sk_cdata.sk_tx_cons = cons; 1799 } 1800 1801 void 1802 msk_tick(void *xsc_if) 1803 { 1804 struct sk_if_softc *sc_if = xsc_if; 1805 struct mii_data *mii = &sc_if->sk_mii; 1806 1807 mii_tick(mii); 1808 callout_schedule(&sc_if->sk_tick_ch, hz); 1809 } 1810 1811 void 1812 msk_intr_yukon(struct sk_if_softc *sc_if) 1813 { 1814 u_int8_t status; 1815 1816 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1817 /* RX overrun */ 1818 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1819 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1820 SK_RFCTL_RX_FIFO_OVER); 1821 } 1822 /* TX underrun */ 1823 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1824 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1825 SK_TFCTL_TX_FIFO_UNDER); 1826 } 1827 1828 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1829 } 1830 1831 int 1832 msk_intr(void *xsc) 1833 { 1834 struct sk_softc *sc = xsc; 1835 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1836 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1837 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1838 int claimed = 0; 1839 u_int32_t status; 1840 uint32_t st_status; 1841 uint16_t st_len; 1842 uint8_t st_opcode, st_link; 1843 struct msk_status_desc *cur_st; 1844 1845 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1846 if (status == 0) { 1847 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1848 return (0); 1849 } 1850 1851 status = CSR_READ_4(sc, SK_ISR); 1852 1853 if (sc_if0 != NULL) 1854 ifp0 = &sc_if0->sk_ethercom.ec_if; 1855 if (sc_if1 != NULL) 1856 ifp1 = &sc_if1->sk_ethercom.ec_if; 1857 1858 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1859 (ifp0->if_flags & IFF_RUNNING)) { 1860 msk_intr_yukon(sc_if0); 1861 } 1862 1863 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1864 (ifp1->if_flags & IFF_RUNNING)) { 1865 msk_intr_yukon(sc_if1); 1866 } 1867 1868 for (;;) { 1869 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1870 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1871 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1872 st_opcode = cur_st->sk_opcode; 1873 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1874 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1875 BUS_DMASYNC_PREREAD); 1876 break; 1877 } 1878 st_status = le32toh(cur_st->sk_status); 1879 st_len = le16toh(cur_st->sk_len); 1880 st_link = cur_st->sk_link; 1881 st_opcode &= ~SK_Y2_STOPC_OWN; 1882 1883 switch (st_opcode) { 1884 case SK_Y2_STOPC_RXSTAT: 1885 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1886 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1887 SK_RXQ1_Y2_PREF_PUTIDX, 1888 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1889 break; 1890 case SK_Y2_STOPC_TXSTAT: 1891 if (sc_if0) 1892 msk_txeof(sc_if0, st_status 1893 & SK_Y2_ST_TXA1_MSKL); 1894 if (sc_if1) 1895 msk_txeof(sc_if1, 1896 ((st_status & SK_Y2_ST_TXA2_MSKL) 1897 >> SK_Y2_ST_TXA2_SHIFTL) 1898 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1899 break; 1900 default: 1901 aprint_error("opcode=0x%x\n", st_opcode); 1902 break; 1903 } 1904 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1905 } 1906 1907 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1908 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1909 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1910 1911 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1912 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1913 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1914 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1915 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1916 1917 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1918 } 1919 1920 if (status & SK_Y2_IMR_BMU) { 1921 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1922 claimed = 1; 1923 } 1924 1925 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1926 1927 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1928 msk_start(ifp0); 1929 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1930 msk_start(ifp1); 1931 1932 #if NRND > 0 1933 if (RND_ENABLED(&sc->rnd_source)) 1934 rnd_add_uint32(&sc->rnd_source, status); 1935 #endif 1936 1937 if (sc->sk_int_mod_pending) 1938 msk_update_int_mod(sc); 1939 1940 return claimed; 1941 } 1942 1943 void 1944 msk_init_yukon(struct sk_if_softc *sc_if) 1945 { 1946 u_int32_t v; 1947 u_int16_t reg; 1948 struct sk_softc *sc; 1949 int i; 1950 1951 sc = sc_if->sk_softc; 1952 1953 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1954 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1955 1956 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1957 1958 /* GMAC and GPHY Reset */ 1959 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1960 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1961 DELAY(1000); 1962 1963 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1964 1965 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1966 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1967 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1968 1969 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1970 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1971 1972 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1973 1974 /* unused read of the interrupt source register */ 1975 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1976 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1977 1978 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1979 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1980 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1981 1982 /* MIB Counter Clear Mode set */ 1983 reg |= YU_PAR_MIB_CLR; 1984 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1985 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1986 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1987 1988 /* MIB Counter Clear Mode clear */ 1989 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1990 reg &= ~YU_PAR_MIB_CLR; 1991 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1992 1993 /* receive control reg */ 1994 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1995 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1996 1997 /* transmit control register */ 1998 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 1999 2000 /* transmit flow control register */ 2001 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2002 2003 /* transmit parameter register */ 2004 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2005 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2006 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2007 2008 /* serial mode register */ 2009 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2010 reg = YU_SMR_DATA_BLIND(0x1c) | 2011 YU_SMR_MFL_VLAN | 2012 YU_SMR_IPG_DATA(0x1e); 2013 2014 if (sc->sk_type != SK_YUKON_FE) 2015 reg |= YU_SMR_MFL_JUMBO; 2016 2017 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2018 2019 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2020 /* Setup Yukon's address */ 2021 for (i = 0; i < 3; i++) { 2022 /* Write Source Address 1 (unicast filter) */ 2023 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2024 sc_if->sk_enaddr[i * 2] | 2025 sc_if->sk_enaddr[i * 2 + 1] << 8); 2026 } 2027 2028 for (i = 0; i < 3; i++) { 2029 reg = sk_win_read_2(sc_if->sk_softc, 2030 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2031 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2032 } 2033 2034 /* Set promiscuous mode */ 2035 msk_setpromisc(sc_if); 2036 2037 /* Set multicast filter */ 2038 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2039 msk_setmulti(sc_if); 2040 2041 /* enable interrupt mask for counter overflows */ 2042 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2043 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2044 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2045 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2046 2047 /* Configure RX MAC FIFO Flush Mask */ 2048 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2049 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2050 YU_RXSTAT_JABBER; 2051 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2052 2053 /* Configure RX MAC FIFO */ 2054 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2055 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2056 SK_RFCTL_FIFO_FLUSH_ON); 2057 2058 /* Increase flush threshould to 64 bytes */ 2059 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2060 SK_RFCTL_FIFO_THRESHOLD + 1); 2061 2062 /* Configure TX MAC FIFO */ 2063 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2064 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2065 2066 #if 1 2067 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2068 #endif 2069 DPRINTFN(6, ("msk_init_yukon: end\n")); 2070 } 2071 2072 /* 2073 * Note that to properly initialize any part of the GEnesis chip, 2074 * you first have to take it out of reset mode. 2075 */ 2076 int 2077 msk_init(struct ifnet *ifp) 2078 { 2079 struct sk_if_softc *sc_if = ifp->if_softc; 2080 struct sk_softc *sc = sc_if->sk_softc; 2081 int rc = 0, s; 2082 uint32_t imr, imtimer_ticks; 2083 2084 2085 DPRINTFN(2, ("msk_init\n")); 2086 2087 s = splnet(); 2088 2089 /* Cancel pending I/O and free all RX/TX buffers. */ 2090 msk_stop(ifp,0); 2091 2092 /* Configure I2C registers */ 2093 2094 /* Configure XMAC(s) */ 2095 msk_init_yukon(sc_if); 2096 if ((rc = ether_mediachange(ifp)) != 0) 2097 goto out; 2098 2099 /* Configure transmit arbiter(s) */ 2100 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2101 #if 0 2102 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2103 #endif 2104 2105 /* Configure RAMbuffers */ 2106 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2107 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2108 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2109 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2110 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2111 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2112 2113 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2114 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2115 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2116 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2117 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2118 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2119 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2120 2121 /* Configure BMUs */ 2122 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2123 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2124 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2125 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2126 2127 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2128 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2129 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2130 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2131 2132 /* Make sure the sync transmit queue is disabled. */ 2133 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2134 2135 /* Init descriptors */ 2136 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2137 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2138 "memory for rx buffers\n"); 2139 msk_stop(ifp,0); 2140 splx(s); 2141 return ENOBUFS; 2142 } 2143 2144 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2145 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2146 "memory for tx buffers\n"); 2147 msk_stop(ifp,0); 2148 splx(s); 2149 return ENOBUFS; 2150 } 2151 2152 /* Set interrupt moderation if changed via sysctl. */ 2153 switch (sc->sk_type) { 2154 case SK_YUKON_EC: 2155 case SK_YUKON_EC_U: 2156 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2157 break; 2158 case SK_YUKON_FE: 2159 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2160 break; 2161 case SK_YUKON_XL: 2162 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2163 break; 2164 default: 2165 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2166 } 2167 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2168 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2169 sk_win_write_4(sc, SK_IMTIMERINIT, 2170 SK_IM_USECS(sc->sk_int_mod)); 2171 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2172 sc->sk_int_mod); 2173 } 2174 2175 /* Initialize prefetch engine. */ 2176 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2177 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2178 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2179 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2180 MSK_RX_RING_ADDR(sc_if, 0)); 2181 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2182 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2183 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2184 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2185 2186 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2187 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2188 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2189 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2190 MSK_TX_RING_ADDR(sc_if, 0)); 2191 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2192 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2193 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2194 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2195 2196 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2197 sc_if->sk_cdata.sk_rx_prod); 2198 2199 /* Configure interrupt handling */ 2200 if (sc_if->sk_port == SK_PORT_A) 2201 sc->sk_intrmask |= SK_Y2_INTRS1; 2202 else 2203 sc->sk_intrmask |= SK_Y2_INTRS2; 2204 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2205 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2206 2207 ifp->if_flags |= IFF_RUNNING; 2208 ifp->if_flags &= ~IFF_OACTIVE; 2209 2210 callout_schedule(&sc_if->sk_tick_ch, hz); 2211 2212 out: 2213 splx(s); 2214 return rc; 2215 } 2216 2217 void 2218 msk_stop(struct ifnet *ifp, int disable) 2219 { 2220 struct sk_if_softc *sc_if = ifp->if_softc; 2221 struct sk_softc *sc = sc_if->sk_softc; 2222 struct sk_txmap_entry *dma; 2223 int i; 2224 2225 DPRINTFN(2, ("msk_stop\n")); 2226 2227 callout_stop(&sc_if->sk_tick_ch); 2228 2229 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2230 2231 /* Stop transfer of Tx descriptors */ 2232 2233 /* Stop transfer of Rx descriptors */ 2234 2235 /* Turn off various components of this interface. */ 2236 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2237 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2238 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2239 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2240 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2241 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2242 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2243 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2244 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2245 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2246 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2247 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2248 2249 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2250 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2251 2252 /* Disable interrupts */ 2253 if (sc_if->sk_port == SK_PORT_A) 2254 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2255 else 2256 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2257 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2258 2259 SK_XM_READ_2(sc_if, XM_ISR); 2260 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2261 2262 /* Free RX and TX mbufs still in the queues. */ 2263 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2264 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2265 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2266 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2267 } 2268 } 2269 2270 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2271 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2272 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2273 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2274 #if 1 2275 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2276 sc_if->sk_cdata.sk_tx_map[i], link); 2277 sc_if->sk_cdata.sk_tx_map[i] = 0; 2278 #endif 2279 } 2280 } 2281 2282 #if 1 2283 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2284 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2285 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2286 free(dma, M_DEVBUF); 2287 } 2288 #endif 2289 } 2290 2291 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2292 NULL, NULL); 2293 2294 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2295 NULL, NULL); 2296 2297 #ifdef MSK_DEBUG 2298 void 2299 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2300 { 2301 #define DESC_PRINT(X) \ 2302 if (X) \ 2303 printf("txdesc[%d]." #X "=%#x\n", \ 2304 idx, X); 2305 2306 DESC_PRINT(letoh32(le->sk_addr)); 2307 DESC_PRINT(letoh16(le->sk_len)); 2308 DESC_PRINT(le->sk_ctl); 2309 DESC_PRINT(le->sk_opcode); 2310 #undef DESC_PRINT 2311 } 2312 2313 void 2314 msk_dump_bytes(const char *data, int len) 2315 { 2316 int c, i, j; 2317 2318 for (i = 0; i < len; i += 16) { 2319 printf("%08x ", i); 2320 c = len - i; 2321 if (c > 16) c = 16; 2322 2323 for (j = 0; j < c; j++) { 2324 printf("%02x ", data[i + j] & 0xff); 2325 if ((j & 0xf) == 7 && j > 0) 2326 printf(" "); 2327 } 2328 2329 for (; j < 16; j++) 2330 printf(" "); 2331 printf(" "); 2332 2333 for (j = 0; j < c; j++) { 2334 int ch = data[i + j] & 0xff; 2335 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2336 } 2337 2338 printf("\n"); 2339 2340 if (c < 16) 2341 break; 2342 } 2343 } 2344 2345 void 2346 msk_dump_mbuf(struct mbuf *m) 2347 { 2348 int count = m->m_pkthdr.len; 2349 2350 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2351 2352 while (count > 0 && m) { 2353 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2354 m, m->m_data, m->m_len); 2355 msk_dump_bytes(mtod(m, char *), m->m_len); 2356 2357 count -= m->m_len; 2358 m = m->m_next; 2359 } 2360 } 2361 #endif 2362 2363 static int 2364 msk_sysctl_handler(SYSCTLFN_ARGS) 2365 { 2366 int error, t; 2367 struct sysctlnode node; 2368 struct sk_softc *sc; 2369 2370 node = *rnode; 2371 sc = node.sysctl_data; 2372 t = sc->sk_int_mod; 2373 node.sysctl_data = &t; 2374 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2375 if (error || newp == NULL) 2376 return error; 2377 2378 if (t < SK_IM_MIN || t > SK_IM_MAX) 2379 return EINVAL; 2380 2381 /* update the softc with sysctl-changed value, and mark 2382 for hardware update */ 2383 sc->sk_int_mod = t; 2384 sc->sk_int_mod_pending = 1; 2385 return 0; 2386 } 2387 2388 /* 2389 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2390 * set up in skc_attach() 2391 */ 2392 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2393 { 2394 int rc; 2395 const struct sysctlnode *node; 2396 2397 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2398 0, CTLTYPE_NODE, "hw", NULL, 2399 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2400 goto err; 2401 } 2402 2403 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2404 0, CTLTYPE_NODE, "msk", 2405 SYSCTL_DESCR("msk interface controls"), 2406 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2407 goto err; 2408 } 2409 2410 msk_root_num = node->sysctl_num; 2411 return; 2412 2413 err: 2414 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2415 } 2416
Indexes created Thu Oct 02 07:10:07 GMT 2025