if_msk.c revision 1.3.2.4
1 /* $NetBSD: if_msk.c,v 1.3.2.4 2007/02/01 08:48:22 ad Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include "bpfilter.h" 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/kernel.h> 63 #include <sys/socket.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/callout.h> 67 #include <sys/sysctl.h> 68 #include <sys/endian.h> 69 #ifdef __NetBSD__ 70 #define letoh16 htole16 71 #define letoh32 htole32 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_types.h> 77 78 #include <net/if_media.h> 79 80 #if NBPFILTER > 0 81 #include <net/bpf.h> 82 #endif 83 #if NRND > 0 84 #include <sys/rnd.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/brgphyreg.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 95 #include <dev/pci/if_skreg.h> 96 #include <dev/pci/if_mskvar.h> 97 98 int mskc_probe(struct device *, struct cfdata *, void *); 99 void mskc_attach(struct device *, struct device *self, void *aux); 100 void mskc_shutdown(void *); 101 int msk_probe(struct device *, struct cfdata *, void *); 102 void msk_attach(struct device *, struct device *self, void *aux); 103 int mskcprint(void *, const char *); 104 int msk_intr(void *); 105 void msk_intr_yukon(struct sk_if_softc *); 106 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 107 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 108 void msk_txeof(struct sk_if_softc *, int); 109 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 110 void msk_start(struct ifnet *); 111 int msk_ioctl(struct ifnet *, u_long, caddr_t); 112 int msk_init(struct ifnet *); 113 void msk_init_yukon(struct sk_if_softc *); 114 void msk_stop(struct ifnet *, int); 115 void msk_watchdog(struct ifnet *); 116 int msk_ifmedia_upd(struct ifnet *); 117 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 void msk_reset(struct sk_softc *); 119 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 120 int msk_alloc_jumbo_mem(struct sk_if_softc *); 121 void *msk_jalloc(struct sk_if_softc *); 122 void msk_jfree(struct mbuf *, caddr_t, size_t, void *); 123 int msk_init_rx_ring(struct sk_if_softc *); 124 int msk_init_tx_ring(struct sk_if_softc *); 125 126 void msk_update_int_mod(struct sk_softc *); 127 128 int msk_miibus_readreg(struct device *, int, int); 129 void msk_miibus_writereg(struct device *, int, int, int); 130 void msk_miibus_statchg(struct device *); 131 132 void msk_setfilt(struct sk_if_softc *, caddr_t, int); 133 void msk_setmulti(struct sk_if_softc *); 134 void msk_setpromisc(struct sk_if_softc *); 135 void msk_tick(void *); 136 137 /* #define MSK_DEBUG 1 */ 138 #ifdef MSK_DEBUG 139 #define DPRINTF(x) if (mskdebug) printf x 140 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 141 int mskdebug = MSK_DEBUG; 142 143 void msk_dump_txdesc(struct msk_tx_desc *, int); 144 void msk_dump_mbuf(struct mbuf *); 145 void msk_dump_bytes(const char *, int); 146 #else 147 #define DPRINTF(x) 148 #define DPRINTFN(n,x) 149 #endif 150 151 static int msk_sysctl_handler(SYSCTLFN_PROTO); 152 static int msk_root_num; 153 154 /* supported device vendors */ 155 static const struct msk_product { 156 pci_vendor_id_t msk_vendor; 157 pci_product_id_t msk_product; 158 } msk_products[] = { 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 185 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 186 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 187 }; 188 189 static inline u_int32_t 190 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 191 { 192 return CSR_READ_4(sc, reg); 193 } 194 195 static inline u_int16_t 196 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 197 { 198 return CSR_READ_2(sc, reg); 199 } 200 201 static inline u_int8_t 202 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 203 { 204 return CSR_READ_1(sc, reg); 205 } 206 207 static inline void 208 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 209 { 210 CSR_WRITE_4(sc, reg, x); 211 } 212 213 static inline void 214 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 215 { 216 CSR_WRITE_2(sc, reg, x); 217 } 218 219 static inline void 220 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 221 { 222 CSR_WRITE_1(sc, reg, x); 223 } 224 225 int 226 msk_miibus_readreg(struct device *dev, int phy, int reg) 227 { 228 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 229 u_int16_t val; 230 int i; 231 232 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 233 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 234 235 for (i = 0; i < SK_TIMEOUT; i++) { 236 DELAY(1); 237 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 238 if (val & YU_SMICR_READ_VALID) 239 break; 240 } 241 242 if (i == SK_TIMEOUT) { 243 aprint_error("%s: phy failed to come ready\n", 244 sc_if->sk_dev.dv_xname); 245 return (0); 246 } 247 248 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 249 SK_TIMEOUT)); 250 251 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 252 253 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 254 phy, reg, val)); 255 256 return (val); 257 } 258 259 void 260 msk_miibus_writereg(struct device *dev, int phy, int reg, int val) 261 { 262 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 263 int i; 264 265 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 266 phy, reg, val)); 267 268 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 269 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 270 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 271 272 for (i = 0; i < SK_TIMEOUT; i++) { 273 DELAY(1); 274 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 275 break; 276 } 277 278 if (i == SK_TIMEOUT) 279 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 280 } 281 282 void 283 msk_miibus_statchg(struct device *dev) 284 { 285 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 286 struct mii_data *mii = &sc_if->sk_mii; 287 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 288 int gpcr; 289 290 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 291 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 292 293 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 294 /* Set speed. */ 295 gpcr |= YU_GPCR_SPEED_DIS; 296 switch (IFM_SUBTYPE(mii->mii_media_active)) { 297 case IFM_1000_SX: 298 case IFM_1000_LX: 299 case IFM_1000_CX: 300 case IFM_1000_T: 301 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 302 break; 303 case IFM_100_TX: 304 gpcr |= YU_GPCR_SPEED; 305 break; 306 } 307 308 /* Set duplex. */ 309 gpcr |= YU_GPCR_DPLX_DIS; 310 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 311 gpcr |= YU_GPCR_DUPLEX; 312 313 /* Disable flow control. */ 314 gpcr |= YU_GPCR_FCTL_DIS; 315 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 316 } 317 318 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 319 320 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 321 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 322 } 323 324 #define HASH_BITS 6 325 326 void 327 msk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 328 { 329 int base = XM_RXFILT_ENTRY(slot); 330 331 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 332 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 333 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 334 } 335 336 void 337 msk_setmulti(struct sk_if_softc *sc_if) 338 { 339 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 340 u_int32_t hashes[2] = { 0, 0 }; 341 int h; 342 struct ethercom *ec = &sc_if->sk_ethercom; 343 struct ether_multi *enm; 344 struct ether_multistep step; 345 u_int16_t reg; 346 347 /* First, zot all the existing filters. */ 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 352 353 354 /* Now program new ones. */ 355 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 356 reg |= YU_RCR_UFLEN; 357 allmulti: 358 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 359 if ((ifp->if_flags & IFF_PROMISC) != 0) 360 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 361 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 362 hashes[0] = 0xFFFFFFFF; 363 hashes[1] = 0xFFFFFFFF; 364 } 365 } else { 366 /* First find the tail of the list. */ 367 ETHER_FIRST_MULTI(step, ec, enm); 368 while (enm != NULL) { 369 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 370 ETHER_ADDR_LEN)) { 371 ifp->if_flags |= IFF_ALLMULTI; 372 goto allmulti; 373 } 374 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 375 ((1 << HASH_BITS) - 1); 376 if (h < 32) 377 hashes[0] |= (1 << h); 378 else 379 hashes[1] |= (1 << (h - 32)); 380 381 ETHER_NEXT_MULTI(step, enm); 382 } 383 reg |= YU_RCR_MUFLEN; 384 } 385 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 391 } 392 393 void 394 msk_setpromisc(struct sk_if_softc *sc_if) 395 { 396 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 397 398 if (ifp->if_flags & IFF_PROMISC) 399 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 400 YU_RCR_UFLEN | YU_RCR_MUFLEN); 401 else 402 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 403 YU_RCR_UFLEN | YU_RCR_MUFLEN); 404 } 405 406 int 407 msk_init_rx_ring(struct sk_if_softc *sc_if) 408 { 409 struct msk_chain_data *cd = &sc_if->sk_cdata; 410 struct msk_ring_data *rd = sc_if->sk_rdata; 411 int i, nexti; 412 413 bzero((char *)rd->sk_rx_ring, 414 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 415 416 for (i = 0; i < MSK_RX_RING_CNT; i++) { 417 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 418 if (i == (MSK_RX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 423 } 424 425 for (i = 0; i < MSK_RX_RING_CNT; i++) { 426 if (msk_newbuf(sc_if, i, NULL, 427 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 428 aprint_error("%s: failed alloc of %dth mbuf\n", 429 sc_if->sk_dev.dv_xname, i); 430 return (ENOBUFS); 431 } 432 } 433 434 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 435 sc_if->sk_cdata.sk_rx_cons = 0; 436 437 return (0); 438 } 439 440 int 441 msk_init_tx_ring(struct sk_if_softc *sc_if) 442 { 443 struct sk_softc *sc = sc_if->sk_softc; 444 struct msk_chain_data *cd = &sc_if->sk_cdata; 445 struct msk_ring_data *rd = sc_if->sk_rdata; 446 bus_dmamap_t dmamap; 447 struct sk_txmap_entry *entry; 448 int i, nexti; 449 450 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 451 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 452 453 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 454 for (i = 0; i < MSK_TX_RING_CNT; i++) { 455 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 456 if (i == (MSK_TX_RING_CNT - 1)) 457 nexti = 0; 458 else 459 nexti = i + 1; 460 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 461 462 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 463 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 464 return (ENOBUFS); 465 466 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 467 if (!entry) { 468 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 469 return (ENOBUFS); 470 } 471 entry->dmamap = dmamap; 472 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 473 } 474 475 sc_if->sk_cdata.sk_tx_prod = 0; 476 sc_if->sk_cdata.sk_tx_cons = 0; 477 sc_if->sk_cdata.sk_tx_cnt = 0; 478 479 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 480 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 481 482 return (0); 483 } 484 485 int 486 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 487 bus_dmamap_t dmamap) 488 { 489 struct mbuf *m_new = NULL; 490 struct sk_chain *c; 491 struct msk_rx_desc *r; 492 493 if (m == NULL) { 494 caddr_t buf = NULL; 495 496 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 497 if (m_new == NULL) 498 return (ENOBUFS); 499 500 /* Allocate the jumbo buffer */ 501 buf = msk_jalloc(sc_if); 502 if (buf == NULL) { 503 m_freem(m_new); 504 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 505 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 506 return (ENOBUFS); 507 } 508 509 /* Attach the buffer to the mbuf */ 510 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 511 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 512 } else { 513 /* 514 * We're re-using a previously allocated mbuf; 515 * be sure to re-init pointers and lengths to 516 * default values. 517 */ 518 m_new = m; 519 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 520 m_new->m_data = m_new->m_ext.ext_buf; 521 } 522 m_adj(m_new, ETHER_ALIGN); 523 524 c = &sc_if->sk_cdata.sk_rx_chain[i]; 525 r = c->sk_le; 526 c->sk_mbuf = m_new; 527 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 528 (((vaddr_t)m_new->m_data 529 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 530 r->sk_len = htole16(SK_JLEN); 531 r->sk_ctl = 0; 532 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 533 534 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 535 536 return (0); 537 } 538 539 /* 540 * Memory management for jumbo frames. 541 */ 542 543 int 544 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 545 { 546 struct sk_softc *sc = sc_if->sk_softc; 547 caddr_t ptr, kva; 548 bus_dma_segment_t seg; 549 int i, rseg, state, error; 550 struct sk_jpool_entry *entry; 551 552 state = error = 0; 553 554 /* Grab a big chunk o' storage. */ 555 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 556 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 557 aprint_error(": can't alloc rx buffers"); 558 return (ENOBUFS); 559 } 560 561 state = 1; 562 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, &kva, 563 BUS_DMA_NOWAIT)) { 564 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 565 error = ENOBUFS; 566 goto out; 567 } 568 569 state = 2; 570 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 571 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 572 aprint_error(": can't create dma map"); 573 error = ENOBUFS; 574 goto out; 575 } 576 577 state = 3; 578 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 579 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 580 aprint_error(": can't load dma map"); 581 error = ENOBUFS; 582 goto out; 583 } 584 585 state = 4; 586 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 587 DPRINTFN(1,("msk_jumbo_buf = %p\n", (caddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 588 589 LIST_INIT(&sc_if->sk_jfree_listhead); 590 LIST_INIT(&sc_if->sk_jinuse_listhead); 591 592 /* 593 * Now divide it up into 9K pieces and save the addresses 594 * in an array. 595 */ 596 ptr = sc_if->sk_cdata.sk_jumbo_buf; 597 for (i = 0; i < MSK_JSLOTS; i++) { 598 sc_if->sk_cdata.sk_jslots[i] = ptr; 599 ptr += SK_JLEN; 600 entry = malloc(sizeof(struct sk_jpool_entry), 601 M_DEVBUF, M_NOWAIT); 602 if (entry == NULL) { 603 sc_if->sk_cdata.sk_jumbo_buf = NULL; 604 aprint_error(": no memory for jumbo buffer queue!"); 605 error = ENOBUFS; 606 goto out; 607 } 608 entry->slot = i; 609 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 610 entry, jpool_entries); 611 } 612 out: 613 if (error != 0) { 614 switch (state) { 615 case 4: 616 bus_dmamap_unload(sc->sc_dmatag, 617 sc_if->sk_cdata.sk_rx_jumbo_map); 618 case 3: 619 bus_dmamap_destroy(sc->sc_dmatag, 620 sc_if->sk_cdata.sk_rx_jumbo_map); 621 case 2: 622 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 623 case 1: 624 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 625 break; 626 default: 627 break; 628 } 629 } 630 631 return (error); 632 } 633 634 /* 635 * Allocate a jumbo buffer. 636 */ 637 void * 638 msk_jalloc(struct sk_if_softc *sc_if) 639 { 640 struct sk_jpool_entry *entry; 641 642 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 643 644 if (entry == NULL) 645 return (NULL); 646 647 LIST_REMOVE(entry, jpool_entries); 648 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 649 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 650 } 651 652 /* 653 * Release a jumbo buffer. 654 */ 655 void 656 msk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 657 { 658 struct sk_jpool_entry *entry; 659 struct sk_if_softc *sc; 660 int i, s; 661 662 /* Extract the softc struct pointer. */ 663 sc = (struct sk_if_softc *)arg; 664 665 if (sc == NULL) 666 panic("msk_jfree: can't find softc pointer!"); 667 668 /* calculate the slot this buffer belongs to */ 669 i = ((vaddr_t)buf 670 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 671 672 if ((i < 0) || (i >= MSK_JSLOTS)) 673 panic("msk_jfree: asked to free buffer that we don't manage!"); 674 675 s = splvm(); 676 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 677 if (entry == NULL) 678 panic("msk_jfree: buffer not in use!"); 679 entry->slot = i; 680 LIST_REMOVE(entry, jpool_entries); 681 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 682 683 if (__predict_true(m != NULL)) 684 pool_cache_put(&mbpool_cache, m); 685 splx(s); 686 } 687 688 /* 689 * Set media options. 690 */ 691 int 692 msk_ifmedia_upd(struct ifnet *ifp) 693 { 694 struct sk_if_softc *sc_if = ifp->if_softc; 695 696 mii_mediachg(&sc_if->sk_mii); 697 return (0); 698 } 699 700 /* 701 * Report current media status. 702 */ 703 void 704 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 705 { 706 struct sk_if_softc *sc_if = ifp->if_softc; 707 708 mii_pollstat(&sc_if->sk_mii); 709 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 710 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 711 } 712 713 int 714 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 715 { 716 struct sk_if_softc *sc_if = ifp->if_softc; 717 struct ifreq *ifr = (struct ifreq *) data; 718 struct mii_data *mii; 719 int s, error = 0; 720 721 s = splnet(); 722 723 switch(command) { 724 case SIOCSIFMTU: 725 if (ifr->ifr_mtu < ETHERMIN) 726 return EINVAL; 727 else if (sc_if->sk_softc->sk_type != SK_YUKON_FE) { 728 if (ifr->ifr_mtu > SK_JUMBO_MTU) 729 error = EINVAL; 730 } else if (ifr->ifr_mtu > ETHERMTU) 731 error = EINVAL; 732 ifp->if_mtu = ifr->ifr_mtu; 733 break; 734 case SIOCGIFMEDIA: 735 case SIOCSIFMEDIA: 736 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA\n")); 737 mii = &sc_if->sk_mii; 738 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 739 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA done\n")); 740 break; 741 default: 742 DPRINTFN(2, ("msk_ioctl ETHER\n")); 743 error = ether_ioctl(ifp, command, data); 744 745 if (error == ENETRESET) { 746 /* 747 * Multicast list has changed; set the hardware 748 * filter accordingly. 749 */ 750 if (ifp->if_flags & IFF_RUNNING) 751 msk_setmulti(sc_if); 752 error = 0; 753 } 754 break; 755 } 756 757 splx(s); 758 return (error); 759 } 760 761 void 762 msk_update_int_mod(struct sk_softc *sc) 763 { 764 u_int32_t imtimer_ticks; 765 766 /* 767 * Configure interrupt moderation. The moderation timer 768 * defers interrupts specified in the interrupt moderation 769 * timer mask based on the timeout specified in the interrupt 770 * moderation timer init register. Each bit in the timer 771 * register represents one tick, so to specify a timeout in 772 * microseconds, we have to multiply by the correct number of 773 * ticks-per-microsecond. 774 */ 775 switch (sc->sk_type) { 776 case SK_YUKON_EC: 777 case SK_YUKON_EC_U: 778 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 779 break; 780 case SK_YUKON_FE: 781 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 782 break; 783 case SK_YUKON_XL: 784 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 785 break; 786 default: 787 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 788 } 789 aprint_verbose("%s: interrupt moderation is %d us\n", 790 sc->sk_dev.dv_xname, sc->sk_int_mod); 791 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 792 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 793 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 794 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 795 sc->sk_int_mod_pending = 0; 796 } 797 798 static int 799 msk_lookup(const struct pci_attach_args *pa) 800 { 801 const struct msk_product *pmsk; 802 803 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 804 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 805 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 806 return 1; 807 } 808 return 0; 809 } 810 811 /* 812 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 813 * IDs against our list and return a device name if we find a match. 814 */ 815 int 816 mskc_probe(struct device *parent, struct cfdata *match, 817 void *aux) 818 { 819 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 820 821 return msk_lookup(pa); 822 } 823 824 /* 825 * Force the GEnesis into reset, then bring it out of reset. 826 */ 827 void msk_reset(struct sk_softc *sc) 828 { 829 u_int32_t imtimer_ticks, reg1; 830 int reg; 831 832 DPRINTFN(2, ("msk_reset\n")); 833 834 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 835 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 836 837 DELAY(1000); 838 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 839 DELAY(2); 840 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 841 sk_win_write_1(sc, SK_TESTCTL1, 2); 842 843 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 844 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 845 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 846 else 847 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 848 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 849 850 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 851 sk_win_write_1(sc, SK_Y2_CLKGATE, 852 SK_Y2_CLKGATE_LINK1_GATE_DIS | 853 SK_Y2_CLKGATE_LINK2_GATE_DIS | 854 SK_Y2_CLKGATE_LINK1_CORE_DIS | 855 SK_Y2_CLKGATE_LINK2_CORE_DIS | 856 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 857 else 858 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 859 860 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 861 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 862 DELAY(1000); 863 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 864 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 865 866 sk_win_write_1(sc, SK_TESTCTL1, 1); 867 868 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 869 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 870 CSR_READ_2(sc, SK_LINK_CTRL))); 871 872 /* Disable ASF */ 873 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 874 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 875 876 /* Clear I2C IRQ noise */ 877 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 878 879 /* Disable hardware timer */ 880 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 881 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 882 883 /* Disable descriptor polling */ 884 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 885 886 /* Disable time stamps */ 887 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 888 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 889 890 /* Enable RAM interface */ 891 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 892 for (reg = SK_TO0;reg <= SK_TO11; reg++) 893 sk_win_write_1(sc, reg, 36); 894 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 895 for (reg = SK_TO0;reg <= SK_TO11; reg++) 896 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 897 898 /* 899 * Configure interrupt moderation. The moderation timer 900 * defers interrupts specified in the interrupt moderation 901 * timer mask based on the timeout specified in the interrupt 902 * moderation timer init register. Each bit in the timer 903 * register represents one tick, so to specify a timeout in 904 * microseconds, we have to multiply by the correct number of 905 * ticks-per-microsecond. 906 */ 907 switch (sc->sk_type) { 908 case SK_YUKON_EC: 909 case SK_YUKON_EC_U: 910 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 911 break; 912 case SK_YUKON_FE: 913 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 914 break; 915 case SK_YUKON_XL: 916 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 917 break; 918 default: 919 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 920 } 921 922 /* Reset status ring. */ 923 bzero((char *)sc->sk_status_ring, 924 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 925 sc->sk_status_idx = 0; 926 927 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 928 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 929 930 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 931 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 932 sc->sk_status_map->dm_segs[0].ds_addr); 933 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 934 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 935 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 936 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 937 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 938 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 939 } else { 940 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 941 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 942 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 943 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 944 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 945 } 946 947 #if 0 948 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 949 #endif 950 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 951 952 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 953 954 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 955 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 956 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 957 958 msk_update_int_mod(sc); 959 } 960 961 int 962 msk_probe(struct device *parent, struct cfdata *match, 963 void *aux) 964 { 965 struct skc_attach_args *sa = aux; 966 967 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 968 return (0); 969 970 switch (sa->skc_type) { 971 case SK_YUKON_XL: 972 case SK_YUKON_EC_U: 973 case SK_YUKON_EC: 974 case SK_YUKON_FE: 975 return (1); 976 } 977 978 return (0); 979 } 980 981 /* 982 * Each XMAC chip is attached as a separate logical IP interface. 983 * Single port cards will have only one logical interface of course. 984 */ 985 void 986 msk_attach(struct device *parent, struct device *self, void *aux) 987 { 988 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 989 struct sk_softc *sc = (struct sk_softc *)parent; 990 struct skc_attach_args *sa = aux; 991 struct ifnet *ifp; 992 caddr_t kva; 993 bus_dma_segment_t seg; 994 int i, rseg; 995 u_int32_t chunk, val; 996 997 sc_if->sk_port = sa->skc_port; 998 sc_if->sk_softc = sc; 999 sc->sk_if[sa->skc_port] = sc_if; 1000 1001 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1002 1003 /* 1004 * Get station address for this interface. Note that 1005 * dual port cards actually come with three station 1006 * addresses: one for each port, plus an extra. The 1007 * extra one is used by the SysKonnect driver software 1008 * as a 'virtual' station address for when both ports 1009 * are operating in failover mode. Currently we don't 1010 * use this extra address. 1011 */ 1012 for (i = 0; i < ETHER_ADDR_LEN; i++) 1013 sc_if->sk_enaddr[i] = 1014 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1015 1016 aprint_normal(": Ethernet address %s\n", 1017 ether_sprintf(sc_if->sk_enaddr)); 1018 1019 /* 1020 * Set up RAM buffer addresses. The NIC will have a certain 1021 * amount of SRAM on it, somewhere between 512K and 2MB. We 1022 * need to divide this up a) between the transmitter and 1023 * receiver and b) between the two XMACs, if this is a 1024 * dual port NIC. Our algorithm is to divide up the memory 1025 * evenly so that everyone gets a fair share. 1026 * 1027 * Just to be contrary, Yukon2 appears to have separate memory 1028 * for each MAC. 1029 */ 1030 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1031 val = sc->sk_rboff / sizeof(u_int64_t); 1032 sc_if->sk_rx_ramstart = val; 1033 val += (chunk / sizeof(u_int64_t)); 1034 sc_if->sk_rx_ramend = val - 1; 1035 chunk = sc->sk_ramsize - chunk; 1036 sc_if->sk_tx_ramstart = val; 1037 val += (chunk / sizeof(u_int64_t)); 1038 sc_if->sk_tx_ramend = val - 1; 1039 1040 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1041 " tx_ramstart=%#x tx_ramend=%#x\n", 1042 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1043 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1044 1045 /* Allocate the descriptor queues. */ 1046 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1047 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1048 aprint_error(": can't alloc rx buffers\n"); 1049 goto fail; 1050 } 1051 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1052 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1053 aprint_error(": can't map dma buffers (%zu bytes)\n", 1054 sizeof(struct msk_ring_data)); 1055 goto fail_1; 1056 } 1057 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1058 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1059 &sc_if->sk_ring_map)) { 1060 aprint_error(": can't create dma map\n"); 1061 goto fail_2; 1062 } 1063 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1064 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1065 aprint_error(": can't load dma map\n"); 1066 goto fail_3; 1067 } 1068 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1069 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1070 1071 ifp = &sc_if->sk_ethercom.ec_if; 1072 /* Try to allocate memory for jumbo buffers. */ 1073 if (msk_alloc_jumbo_mem(sc_if)) { 1074 aprint_error(": jumbo buffer allocation failed\n"); 1075 goto fail_3; 1076 } 1077 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1078 | ETHERCAP_JUMBO_MTU; 1079 1080 ifp->if_softc = sc_if; 1081 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1082 ifp->if_ioctl = msk_ioctl; 1083 ifp->if_start = msk_start; 1084 ifp->if_stop = msk_stop; 1085 ifp->if_init = msk_init; 1086 ifp->if_watchdog = msk_watchdog; 1087 ifp->if_baudrate = 1000000000; 1088 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1089 IFQ_SET_READY(&ifp->if_snd); 1090 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1091 1092 /* 1093 * Do miibus setup. 1094 */ 1095 msk_init_yukon(sc_if); 1096 1097 DPRINTFN(2, ("msk_attach: 1\n")); 1098 1099 sc_if->sk_mii.mii_ifp = ifp; 1100 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1101 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1102 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1103 1104 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1105 msk_ifmedia_upd, msk_ifmedia_sts); 1106 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1107 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1108 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1109 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1110 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1111 0, NULL); 1112 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1113 } else 1114 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1115 1116 callout_init(&sc_if->sk_tick_ch); 1117 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1118 callout_schedule(&sc_if->sk_tick_ch, hz); 1119 1120 /* 1121 * Call MI attach routines. 1122 */ 1123 if_attach(ifp); 1124 ether_ifattach(ifp, sc_if->sk_enaddr); 1125 1126 shutdownhook_establish(mskc_shutdown, sc); 1127 1128 #if NRND > 0 1129 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1130 RND_TYPE_NET, 0); 1131 #endif 1132 1133 DPRINTFN(2, ("msk_attach: end\n")); 1134 return; 1135 1136 fail_3: 1137 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1138 fail_2: 1139 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1140 fail_1: 1141 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1142 fail: 1143 sc->sk_if[sa->skc_port] = NULL; 1144 } 1145 1146 int 1147 mskcprint(void *aux, const char *pnp) 1148 { 1149 struct skc_attach_args *sa = aux; 1150 1151 if (pnp) 1152 aprint_normal("sk port %c at %s", 1153 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1154 else 1155 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1156 return (UNCONF); 1157 } 1158 1159 /* 1160 * Attach the interface. Allocate softc structures, do ifmedia 1161 * setup and ethernet/BPF attach. 1162 */ 1163 void 1164 mskc_attach(struct device *parent, struct device *self, void *aux) 1165 { 1166 struct sk_softc *sc = (struct sk_softc *)self; 1167 struct pci_attach_args *pa = aux; 1168 struct skc_attach_args skca; 1169 pci_chipset_tag_t pc = pa->pa_pc; 1170 pcireg_t command, memtype; 1171 pci_intr_handle_t ih; 1172 const char *intrstr = NULL; 1173 bus_size_t size; 1174 int rc, sk_nodenum; 1175 u_int8_t hw, skrs; 1176 const char *revstr = NULL; 1177 const struct sysctlnode *node; 1178 caddr_t kva; 1179 bus_dma_segment_t seg; 1180 int rseg; 1181 1182 DPRINTFN(2, ("begin mskc_attach\n")); 1183 1184 /* 1185 * Handle power management nonsense. 1186 */ 1187 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1188 1189 if (command == 0x01) { 1190 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1191 if (command & SK_PSTATE_MASK) { 1192 u_int32_t iobase, membase, irq; 1193 1194 /* Save important PCI config data. */ 1195 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1196 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1197 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1198 1199 /* Reset the power state. */ 1200 aprint_normal("%s chip is in D%d power mode " 1201 "-- setting to D0\n", sc->sk_dev.dv_xname, 1202 command & SK_PSTATE_MASK); 1203 command &= 0xFFFFFFFC; 1204 pci_conf_write(pc, pa->pa_tag, 1205 SK_PCI_PWRMGMTCTRL, command); 1206 1207 /* Restore PCI config data. */ 1208 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1209 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1210 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1211 } 1212 } 1213 1214 /* 1215 * Map control/status registers. 1216 */ 1217 1218 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1219 switch (memtype) { 1220 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1221 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1222 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1223 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1224 NULL, &size) == 0) 1225 break; 1226 default: 1227 aprint_error(": can't map mem space\n"); 1228 return; 1229 } 1230 1231 sc->sc_dmatag = pa->pa_dmat; 1232 1233 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1234 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1235 1236 /* bail out here if chip is not recognized */ 1237 if (!(SK_IS_YUKON2(sc))) { 1238 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1239 goto fail_1; 1240 } 1241 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1242 1243 /* Allocate interrupt */ 1244 if (pci_intr_map(pa, &ih)) { 1245 aprint_error(": couldn't map interrupt\n"); 1246 goto fail_1; 1247 } 1248 1249 intrstr = pci_intr_string(pc, ih); 1250 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1251 if (sc->sk_intrhand == NULL) { 1252 aprint_error(": couldn't establish interrupt"); 1253 if (intrstr != NULL) 1254 aprint_error(" at %s", intrstr); 1255 aprint_error("\n"); 1256 goto fail_1; 1257 } 1258 1259 if (bus_dmamem_alloc(sc->sc_dmatag, 1260 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1261 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1262 aprint_error(": can't alloc status buffers\n"); 1263 goto fail_2; 1264 } 1265 1266 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1267 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1268 &kva, BUS_DMA_NOWAIT)) { 1269 aprint_error(": can't map dma buffers (%zu bytes)\n", 1270 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1271 goto fail_3; 1272 } 1273 if (bus_dmamap_create(sc->sc_dmatag, 1274 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1275 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1276 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1277 aprint_error(": can't create dma map\n"); 1278 goto fail_4; 1279 } 1280 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1281 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1282 NULL, BUS_DMA_NOWAIT)) { 1283 aprint_error(": can't load dma map\n"); 1284 goto fail_5; 1285 } 1286 sc->sk_status_ring = (struct msk_status_desc *)kva; 1287 bzero(sc->sk_status_ring, 1288 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1289 1290 /* Reset the adapter. */ 1291 msk_reset(sc); 1292 1293 skrs = sk_win_read_1(sc, SK_EPROM0); 1294 if (skrs == 0x00) 1295 sc->sk_ramsize = 0x20000; 1296 else 1297 sc->sk_ramsize = skrs * (1<<12); 1298 sc->sk_rboff = SK_RBOFF_0; 1299 1300 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1301 sc->sk_ramsize, sc->sk_ramsize / 1024, 1302 sc->sk_rboff)); 1303 1304 switch (sc->sk_type) { 1305 case SK_YUKON_XL: 1306 sc->sk_name = "Yukon-2 XL"; 1307 break; 1308 case SK_YUKON_EC_U: 1309 sc->sk_name = "Yukon-2 EC Ultra"; 1310 break; 1311 case SK_YUKON_EC: 1312 sc->sk_name = "Yukon-2 EC"; 1313 break; 1314 case SK_YUKON_FE: 1315 sc->sk_name = "Yukon-2 FE"; 1316 break; 1317 default: 1318 sc->sk_name = "Yukon (Unknown)"; 1319 } 1320 1321 if (sc->sk_type == SK_YUKON_XL) { 1322 switch (sc->sk_rev) { 1323 case SK_YUKON_XL_REV_A0: 1324 sc->sk_workaround = 0; 1325 revstr = "A0"; 1326 break; 1327 case SK_YUKON_XL_REV_A1: 1328 sc->sk_workaround = SK_WA_4109; 1329 revstr = "A1"; 1330 break; 1331 case SK_YUKON_XL_REV_A2: 1332 sc->sk_workaround = SK_WA_4109; 1333 revstr = "A2"; 1334 break; 1335 case SK_YUKON_XL_REV_A3: 1336 sc->sk_workaround = SK_WA_4109; 1337 revstr = "A3"; 1338 break; 1339 default: 1340 sc->sk_workaround = 0; 1341 break; 1342 } 1343 } 1344 1345 if (sc->sk_type == SK_YUKON_EC) { 1346 switch (sc->sk_rev) { 1347 case SK_YUKON_EC_REV_A1: 1348 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1349 revstr = "A1"; 1350 break; 1351 case SK_YUKON_EC_REV_A2: 1352 sc->sk_workaround = SK_WA_4109; 1353 revstr = "A2"; 1354 break; 1355 case SK_YUKON_EC_REV_A3: 1356 sc->sk_workaround = SK_WA_4109; 1357 revstr = "A3"; 1358 break; 1359 default: 1360 sc->sk_workaround = 0; 1361 break; 1362 } 1363 } 1364 1365 if (sc->sk_type == SK_YUKON_FE) { 1366 sc->sk_workaround = SK_WA_4109; 1367 switch (sc->sk_rev) { 1368 case SK_YUKON_FE_REV_A1: 1369 revstr = "A1"; 1370 break; 1371 case SK_YUKON_FE_REV_A2: 1372 revstr = "A2"; 1373 break; 1374 default: 1375 sc->sk_workaround = 0; 1376 break; 1377 } 1378 } 1379 1380 if (sc->sk_type == SK_YUKON_EC_U) { 1381 sc->sk_workaround = SK_WA_4109; 1382 switch (sc->sk_rev) { 1383 case SK_YUKON_EC_U_REV_A0: 1384 revstr = "A0"; 1385 break; 1386 case SK_YUKON_EC_U_REV_A1: 1387 revstr = "A1"; 1388 break; 1389 case SK_YUKON_EC_U_REV_B0: 1390 revstr = "B0"; 1391 break; 1392 default: 1393 sc->sk_workaround = 0; 1394 break; 1395 } 1396 } 1397 1398 /* Announce the product name. */ 1399 aprint_normal(", %s", sc->sk_name); 1400 if (revstr != NULL) 1401 aprint_normal(" rev. %s", revstr); 1402 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1403 1404 sc->sk_macs = 1; 1405 1406 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1407 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1408 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1409 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1410 sc->sk_macs++; 1411 } 1412 1413 skca.skc_port = SK_PORT_A; 1414 skca.skc_type = sc->sk_type; 1415 skca.skc_rev = sc->sk_rev; 1416 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1417 1418 if (sc->sk_macs > 1) { 1419 skca.skc_port = SK_PORT_B; 1420 skca.skc_type = sc->sk_type; 1421 skca.skc_rev = sc->sk_rev; 1422 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1423 } 1424 1425 /* Turn on the 'driver is loaded' LED. */ 1426 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1427 1428 /* skc sysctl setup */ 1429 1430 sc->sk_int_mod = SK_IM_DEFAULT; 1431 sc->sk_int_mod_pending = 0; 1432 1433 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1434 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1435 SYSCTL_DESCR("mskc per-controller controls"), 1436 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1437 CTL_EOL)) != 0) { 1438 aprint_normal("%s: couldn't create sysctl node\n", 1439 sc->sk_dev.dv_xname); 1440 goto fail_6; 1441 } 1442 1443 sk_nodenum = node->sysctl_num; 1444 1445 /* interrupt moderation time in usecs */ 1446 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1447 CTLFLAG_READWRITE, 1448 CTLTYPE_INT, "int_mod", 1449 SYSCTL_DESCR("msk interrupt moderation timer"), 1450 msk_sysctl_handler, 0, sc, 1451 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1452 CTL_EOL)) != 0) { 1453 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1454 sc->sk_dev.dv_xname); 1455 goto fail_6; 1456 } 1457 1458 return; 1459 1460 fail_6: 1461 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1462 fail_5: 1463 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1464 fail_4: 1465 bus_dmamem_unmap(sc->sc_dmatag, kva, 1466 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1467 fail_3: 1468 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1469 fail_2: 1470 pci_intr_disestablish(pc, sc->sk_intrhand); 1471 fail_1: 1472 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1473 } 1474 1475 int 1476 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1477 { 1478 struct sk_softc *sc = sc_if->sk_softc; 1479 struct msk_tx_desc *f = NULL; 1480 u_int32_t frag, cur; 1481 int i; 1482 struct sk_txmap_entry *entry; 1483 bus_dmamap_t txmap; 1484 1485 DPRINTFN(2, ("msk_encap\n")); 1486 1487 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1488 if (entry == NULL) { 1489 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1490 return (ENOBUFS); 1491 } 1492 txmap = entry->dmamap; 1493 1494 cur = frag = *txidx; 1495 1496 #ifdef MSK_DEBUG 1497 if (mskdebug >= 2) 1498 msk_dump_mbuf(m_head); 1499 #endif 1500 1501 /* 1502 * Start packing the mbufs in this chain into 1503 * the fragment pointers. Stop when we run out 1504 * of fragments or hit the end of the mbuf chain. 1505 */ 1506 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1507 BUS_DMA_NOWAIT)) { 1508 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1509 return (ENOBUFS); 1510 } 1511 1512 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1513 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1514 bus_dmamap_unload(sc->sc_dmatag, txmap); 1515 return (ENOBUFS); 1516 } 1517 1518 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1519 1520 /* Sync the DMA map. */ 1521 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1522 BUS_DMASYNC_PREWRITE); 1523 1524 for (i = 0; i < txmap->dm_nsegs; i++) { 1525 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1526 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1527 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1528 f->sk_ctl = 0; 1529 if (i == 0) 1530 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1531 else 1532 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1533 cur = frag; 1534 SK_INC(frag, MSK_TX_RING_CNT); 1535 } 1536 1537 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1538 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1539 1540 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1541 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1542 1543 /* Sync descriptors before handing to chip */ 1544 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1545 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1546 1547 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1548 1549 /* Sync first descriptor to hand it off */ 1550 MSK_CDTXSYNC(sc_if, *txidx, 1, 1551 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1552 1553 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1554 1555 #ifdef MSK_DEBUG 1556 if (mskdebug >= 2) { 1557 struct msk_tx_desc *le; 1558 u_int32_t idx; 1559 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1560 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1561 msk_dump_txdesc(le, idx); 1562 } 1563 } 1564 #endif 1565 1566 *txidx = frag; 1567 1568 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1569 1570 return (0); 1571 } 1572 1573 void 1574 msk_start(struct ifnet *ifp) 1575 { 1576 struct sk_if_softc *sc_if = ifp->if_softc; 1577 struct mbuf *m_head = NULL; 1578 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1579 int pkts = 0; 1580 1581 DPRINTFN(2, ("msk_start\n")); 1582 1583 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1584 IFQ_POLL(&ifp->if_snd, m_head); 1585 if (m_head == NULL) 1586 break; 1587 1588 /* 1589 * Pack the data into the transmit ring. If we 1590 * don't have room, set the OACTIVE flag and wait 1591 * for the NIC to drain the ring. 1592 */ 1593 if (msk_encap(sc_if, m_head, &idx)) { 1594 ifp->if_flags |= IFF_OACTIVE; 1595 break; 1596 } 1597 1598 /* now we are committed to transmit the packet */ 1599 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1600 pkts++; 1601 1602 /* 1603 * If there's a BPF listener, bounce a copy of this frame 1604 * to him. 1605 */ 1606 #if NBPFILTER > 0 1607 if (ifp->if_bpf) 1608 bpf_mtap(ifp->if_bpf, m_head); 1609 #endif 1610 } 1611 if (pkts == 0) 1612 return; 1613 1614 /* Transmit */ 1615 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1616 sc_if->sk_cdata.sk_tx_prod = idx; 1617 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1618 1619 /* Set a timeout in case the chip goes out to lunch. */ 1620 ifp->if_timer = 5; 1621 } 1622 } 1623 1624 void 1625 msk_watchdog(struct ifnet *ifp) 1626 { 1627 struct sk_if_softc *sc_if = ifp->if_softc; 1628 u_int32_t reg; 1629 int idx; 1630 1631 /* 1632 * Reclaim first as there is a possibility of losing Tx completion 1633 * interrupts. 1634 */ 1635 if (sc_if->sk_port == SK_PORT_A) 1636 reg = SK_STAT_BMU_TXA1_RIDX; 1637 else 1638 reg = SK_STAT_BMU_TXA2_RIDX; 1639 1640 idx = sk_win_read_2(sc_if->sk_softc, reg); 1641 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1642 msk_txeof(sc_if, idx); 1643 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1644 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1645 1646 ifp->if_oerrors++; 1647 1648 /* XXX Resets both ports; we shouldn't do that. */ 1649 msk_reset(sc_if->sk_softc); 1650 msk_init(ifp); 1651 } 1652 } 1653 } 1654 1655 void 1656 mskc_shutdown(void *v) 1657 { 1658 struct sk_softc *sc = v; 1659 1660 DPRINTFN(2, ("msk_shutdown\n")); 1661 1662 /* Turn off the 'driver is loaded' LED. */ 1663 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1664 1665 msk_reset(sc); 1666 } 1667 1668 __inline int 1669 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1670 { 1671 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1672 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1673 YU_RXSTAT_JABBER)) != 0 || 1674 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1675 YU_RXSTAT_BYTES(stat) != len) 1676 return (0); 1677 1678 return (1); 1679 } 1680 1681 void 1682 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1683 { 1684 struct sk_softc *sc = sc_if->sk_softc; 1685 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1686 struct mbuf *m; 1687 struct sk_chain *cur_rx; 1688 int cur, total_len = len; 1689 bus_dmamap_t dmamap; 1690 1691 DPRINTFN(2, ("msk_rxeof\n")); 1692 1693 cur = sc_if->sk_cdata.sk_rx_cons; 1694 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1695 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1696 1697 /* Sync the descriptor */ 1698 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1699 1700 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1701 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1702 1703 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1704 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1705 1706 m = cur_rx->sk_mbuf; 1707 cur_rx->sk_mbuf = NULL; 1708 1709 if (total_len < SK_MIN_FRAMELEN || 1710 total_len > SK_JUMBO_FRAMELEN || 1711 msk_rxvalid(sc, rxstat, total_len) == 0) { 1712 ifp->if_ierrors++; 1713 msk_newbuf(sc_if, cur, m, dmamap); 1714 return; 1715 } 1716 1717 /* 1718 * Try to allocate a new jumbo buffer. If that fails, copy the 1719 * packet to mbufs and put the jumbo buffer back in the ring 1720 * so it can be re-used. If allocating mbufs fails, then we 1721 * have to drop the packet. 1722 */ 1723 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1724 struct mbuf *m0; 1725 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1726 total_len + ETHER_ALIGN, 0, ifp, NULL); 1727 msk_newbuf(sc_if, cur, m, dmamap); 1728 if (m0 == NULL) { 1729 ifp->if_ierrors++; 1730 return; 1731 } 1732 m_adj(m0, ETHER_ALIGN); 1733 m = m0; 1734 } else { 1735 m->m_pkthdr.rcvif = ifp; 1736 m->m_pkthdr.len = m->m_len = total_len; 1737 } 1738 1739 ifp->if_ipackets++; 1740 1741 #if NBPFILTER > 0 1742 if (ifp->if_bpf) 1743 bpf_mtap(ifp->if_bpf, m); 1744 #endif 1745 1746 /* pass it on. */ 1747 (*ifp->if_input)(ifp, m); 1748 } 1749 1750 void 1751 msk_txeof(struct sk_if_softc *sc_if, int idx) 1752 { 1753 struct sk_softc *sc = sc_if->sk_softc; 1754 struct msk_tx_desc *cur_tx; 1755 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1756 u_int32_t sk_ctl; 1757 struct sk_txmap_entry *entry; 1758 int cons, prog; 1759 1760 DPRINTFN(2, ("msk_txeof\n")); 1761 1762 /* 1763 * Go through our tx ring and free mbufs for those 1764 * frames that have been sent. 1765 */ 1766 cons = sc_if->sk_cdata.sk_tx_cons; 1767 prog = 0; 1768 while (cons != idx) { 1769 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1770 break; 1771 prog++; 1772 MSK_CDTXSYNC(sc_if, cons, 1, 1773 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1774 1775 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1776 sk_ctl = cur_tx->sk_ctl; 1777 #ifdef MSK_DEBUG 1778 if (mskdebug >= 2) 1779 msk_dump_txdesc(cur_tx, cons); 1780 #endif 1781 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1782 ifp->if_opackets++; 1783 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1784 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1785 1786 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1787 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1788 1789 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1790 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1791 link); 1792 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1793 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1794 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1795 } 1796 sc_if->sk_cdata.sk_tx_cnt--; 1797 SK_INC(cons, MSK_TX_RING_CNT); 1798 } 1799 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1800 1801 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1802 ifp->if_flags &= ~IFF_OACTIVE; 1803 1804 if (prog > 0) 1805 sc_if->sk_cdata.sk_tx_cons = cons; 1806 } 1807 1808 void 1809 msk_tick(void *xsc_if) 1810 { 1811 struct sk_if_softc *sc_if = xsc_if; 1812 struct mii_data *mii = &sc_if->sk_mii; 1813 1814 mii_tick(mii); 1815 callout_schedule(&sc_if->sk_tick_ch, hz); 1816 } 1817 1818 void 1819 msk_intr_yukon(struct sk_if_softc *sc_if) 1820 { 1821 u_int8_t status; 1822 1823 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1824 /* RX overrun */ 1825 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1826 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1827 SK_RFCTL_RX_FIFO_OVER); 1828 } 1829 /* TX underrun */ 1830 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1831 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1832 SK_TFCTL_TX_FIFO_UNDER); 1833 } 1834 1835 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1836 } 1837 1838 int 1839 msk_intr(void *xsc) 1840 { 1841 struct sk_softc *sc = xsc; 1842 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1843 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1844 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1845 int claimed = 0; 1846 u_int32_t status; 1847 struct msk_status_desc *cur_st; 1848 1849 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1850 if (status == 0) { 1851 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1852 return (0); 1853 } 1854 1855 status = CSR_READ_4(sc, SK_ISR); 1856 1857 if (sc_if0 != NULL) 1858 ifp0 = &sc_if0->sk_ethercom.ec_if; 1859 if (sc_if1 != NULL) 1860 ifp1 = &sc_if1->sk_ethercom.ec_if; 1861 1862 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1863 (ifp0->if_flags & IFF_RUNNING)) { 1864 msk_intr_yukon(sc_if0); 1865 } 1866 1867 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1868 (ifp1->if_flags & IFF_RUNNING)) { 1869 msk_intr_yukon(sc_if1); 1870 } 1871 1872 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1873 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1874 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1875 1876 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 1877 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1878 switch (cur_st->sk_opcode) { 1879 case SK_Y2_STOPC_RXSTAT: 1880 msk_rxeof(sc->sk_if[cur_st->sk_link], 1881 letoh16(cur_st->sk_len), 1882 letoh32(cur_st->sk_status)); 1883 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1884 SK_RXQ1_Y2_PREF_PUTIDX, 1885 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1886 break; 1887 case SK_Y2_STOPC_TXSTAT: 1888 if (sc_if0) 1889 msk_txeof(sc_if0, 1890 letoh32(cur_st->sk_status) 1891 & SK_Y2_ST_TXA1_MSKL); 1892 if (sc_if1) 1893 msk_txeof(sc_if1, 1894 ((letoh32(cur_st->sk_status) 1895 & SK_Y2_ST_TXA2_MSKL) 1896 >> SK_Y2_ST_TXA2_SHIFTL) 1897 | ((letoh16(cur_st->sk_len) & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1898 break; 1899 default: 1900 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 1901 break; 1902 } 1903 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1904 1905 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1906 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1907 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1908 } 1909 1910 if (status & SK_Y2_IMR_BMU) { 1911 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1912 claimed = 1; 1913 } 1914 1915 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1916 1917 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1918 msk_start(ifp0); 1919 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1920 msk_start(ifp1); 1921 1922 #if NRND > 0 1923 if (RND_ENABLED(&sc->rnd_source)) 1924 rnd_add_uint32(&sc->rnd_source, status); 1925 #endif 1926 1927 if (sc->sk_int_mod_pending) 1928 msk_update_int_mod(sc); 1929 1930 return claimed; 1931 } 1932 1933 void 1934 msk_init_yukon(struct sk_if_softc *sc_if) 1935 { 1936 u_int32_t v; 1937 u_int16_t reg; 1938 struct sk_softc *sc; 1939 int i; 1940 1941 sc = sc_if->sk_softc; 1942 1943 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1944 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1945 1946 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1947 1948 /* GMAC and GPHY Reset */ 1949 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1950 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1951 DELAY(1000); 1952 1953 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1954 1955 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1956 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1957 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1958 1959 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1960 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1961 1962 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1963 1964 /* unused read of the interrupt source register */ 1965 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1966 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1967 1968 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1969 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1970 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1971 1972 /* MIB Counter Clear Mode set */ 1973 reg |= YU_PAR_MIB_CLR; 1974 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1975 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1976 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1977 1978 /* MIB Counter Clear Mode clear */ 1979 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1980 reg &= ~YU_PAR_MIB_CLR; 1981 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1982 1983 /* receive control reg */ 1984 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1985 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1986 1987 /* transmit control register */ 1988 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 1989 1990 /* transmit flow control register */ 1991 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 1992 1993 /* transmit parameter register */ 1994 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1995 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1996 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 1997 1998 /* serial mode register */ 1999 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2000 reg = YU_SMR_DATA_BLIND(0x1c) | 2001 YU_SMR_MFL_VLAN | 2002 YU_SMR_IPG_DATA(0x1e); 2003 2004 if (sc->sk_type != SK_YUKON_FE) 2005 reg |= YU_SMR_MFL_JUMBO; 2006 2007 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2008 2009 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2010 /* Setup Yukon's address */ 2011 for (i = 0; i < 3; i++) { 2012 /* Write Source Address 1 (unicast filter) */ 2013 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2014 sc_if->sk_enaddr[i * 2] | 2015 sc_if->sk_enaddr[i * 2 + 1] << 8); 2016 } 2017 2018 for (i = 0; i < 3; i++) { 2019 reg = sk_win_read_2(sc_if->sk_softc, 2020 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2021 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2022 } 2023 2024 /* Set promiscuous mode */ 2025 msk_setpromisc(sc_if); 2026 2027 /* Set multicast filter */ 2028 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2029 msk_setmulti(sc_if); 2030 2031 /* enable interrupt mask for counter overflows */ 2032 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2033 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2034 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2035 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2036 2037 /* Configure RX MAC FIFO Flush Mask */ 2038 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2039 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2040 YU_RXSTAT_JABBER; 2041 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2042 2043 /* Configure RX MAC FIFO */ 2044 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2045 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2046 SK_RFCTL_FIFO_FLUSH_ON); 2047 2048 /* Increase flush threshould to 64 bytes */ 2049 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2050 SK_RFCTL_FIFO_THRESHOLD + 1); 2051 2052 /* Configure TX MAC FIFO */ 2053 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2054 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2055 2056 #if 1 2057 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2058 #endif 2059 DPRINTFN(6, ("msk_init_yukon: end\n")); 2060 } 2061 2062 /* 2063 * Note that to properly initialize any part of the GEnesis chip, 2064 * you first have to take it out of reset mode. 2065 */ 2066 int 2067 msk_init(struct ifnet *ifp) 2068 { 2069 struct sk_if_softc *sc_if = ifp->if_softc; 2070 struct sk_softc *sc = sc_if->sk_softc; 2071 struct mii_data *mii = &sc_if->sk_mii; 2072 int s; 2073 uint32_t imr, imtimer_ticks; 2074 2075 2076 DPRINTFN(2, ("msk_init\n")); 2077 2078 s = splnet(); 2079 2080 /* Cancel pending I/O and free all RX/TX buffers. */ 2081 msk_stop(ifp,0); 2082 2083 /* Configure I2C registers */ 2084 2085 /* Configure XMAC(s) */ 2086 msk_init_yukon(sc_if); 2087 mii_mediachg(mii); 2088 2089 /* Configure transmit arbiter(s) */ 2090 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2091 #if 0 2092 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2093 #endif 2094 2095 /* Configure RAMbuffers */ 2096 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2097 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2098 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2099 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2100 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2101 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2102 2103 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2104 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2105 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2106 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2107 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2108 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2109 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2110 2111 /* Configure BMUs */ 2112 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2113 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2114 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2115 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2116 2117 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2118 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2119 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2120 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2121 2122 /* Make sure the sync transmit queue is disabled. */ 2123 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2124 2125 /* Init descriptors */ 2126 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2127 aprint_error("%s: initialization failed: no " 2128 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2129 msk_stop(ifp,0); 2130 splx(s); 2131 return ENOBUFS; 2132 } 2133 2134 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2135 aprint_error("%s: initialization failed: no " 2136 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2137 msk_stop(ifp,0); 2138 splx(s); 2139 return ENOBUFS; 2140 } 2141 2142 /* Set interrupt moderation if changed via sysctl. */ 2143 switch (sc->sk_type) { 2144 case SK_YUKON_EC: 2145 case SK_YUKON_EC_U: 2146 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2147 break; 2148 case SK_YUKON_FE: 2149 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2150 break; 2151 case SK_YUKON_XL: 2152 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2153 break; 2154 default: 2155 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2156 } 2157 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2158 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2159 sk_win_write_4(sc, SK_IMTIMERINIT, 2160 SK_IM_USECS(sc->sk_int_mod)); 2161 aprint_verbose("%s: interrupt moderation is %d us\n", 2162 sc->sk_dev.dv_xname, sc->sk_int_mod); 2163 } 2164 2165 /* Initialize prefetch engine. */ 2166 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2167 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2168 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2169 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2170 MSK_RX_RING_ADDR(sc_if, 0)); 2171 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2172 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2173 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2174 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2175 2176 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2177 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2178 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2179 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2180 MSK_TX_RING_ADDR(sc_if, 0)); 2181 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2182 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2183 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2184 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2185 2186 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2187 sc_if->sk_cdata.sk_rx_prod); 2188 2189 /* Configure interrupt handling */ 2190 if (sc_if->sk_port == SK_PORT_A) 2191 sc->sk_intrmask |= SK_Y2_INTRS1; 2192 else 2193 sc->sk_intrmask |= SK_Y2_INTRS2; 2194 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2195 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2196 2197 ifp->if_flags |= IFF_RUNNING; 2198 ifp->if_flags &= ~IFF_OACTIVE; 2199 2200 callout_schedule(&sc_if->sk_tick_ch, hz); 2201 2202 splx(s); 2203 return 0; 2204 } 2205 2206 void 2207 msk_stop(struct ifnet *ifp, int disable) 2208 { 2209 struct sk_if_softc *sc_if = ifp->if_softc; 2210 struct sk_softc *sc = sc_if->sk_softc; 2211 struct sk_txmap_entry *dma; 2212 int i; 2213 2214 DPRINTFN(2, ("msk_stop\n")); 2215 2216 callout_stop(&sc_if->sk_tick_ch); 2217 2218 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2219 2220 /* Stop transfer of Tx descriptors */ 2221 2222 /* Stop transfer of Rx descriptors */ 2223 2224 /* Turn off various components of this interface. */ 2225 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2226 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2227 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2228 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2229 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2230 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2231 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2232 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2233 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2234 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2235 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2236 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2237 2238 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2239 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2240 2241 /* Disable interrupts */ 2242 if (sc_if->sk_port == SK_PORT_A) 2243 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2244 else 2245 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2246 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2247 2248 SK_XM_READ_2(sc_if, XM_ISR); 2249 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2250 2251 /* Free RX and TX mbufs still in the queues. */ 2252 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2253 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2254 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2255 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2256 } 2257 } 2258 2259 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2260 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2261 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2262 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2263 #if 1 2264 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2265 sc_if->sk_cdata.sk_tx_map[i], link); 2266 sc_if->sk_cdata.sk_tx_map[i] = 0; 2267 #endif 2268 } 2269 } 2270 2271 #if 1 2272 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2273 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2274 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2275 free(dma, M_DEVBUF); 2276 } 2277 #endif 2278 } 2279 2280 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2281 NULL, NULL); 2282 2283 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2284 NULL, NULL); 2285 2286 #ifdef MSK_DEBUG 2287 void 2288 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2289 { 2290 #define DESC_PRINT(X) \ 2291 if (X) \ 2292 printf("txdesc[%d]." #X "=%#x\n", \ 2293 idx, X); 2294 2295 DESC_PRINT(letoh32(le->sk_addr)); 2296 DESC_PRINT(letoh16(le->sk_len)); 2297 DESC_PRINT(le->sk_ctl); 2298 DESC_PRINT(le->sk_opcode); 2299 #undef DESC_PRINT 2300 } 2301 2302 void 2303 msk_dump_bytes(const char *data, int len) 2304 { 2305 int c, i, j; 2306 2307 for (i = 0; i < len; i += 16) { 2308 printf("%08x ", i); 2309 c = len - i; 2310 if (c > 16) c = 16; 2311 2312 for (j = 0; j < c; j++) { 2313 printf("%02x ", data[i + j] & 0xff); 2314 if ((j & 0xf) == 7 && j > 0) 2315 printf(" "); 2316 } 2317 2318 for (; j < 16; j++) 2319 printf(" "); 2320 printf(" "); 2321 2322 for (j = 0; j < c; j++) { 2323 int ch = data[i + j] & 0xff; 2324 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2325 } 2326 2327 printf("\n"); 2328 2329 if (c < 16) 2330 break; 2331 } 2332 } 2333 2334 void 2335 msk_dump_mbuf(struct mbuf *m) 2336 { 2337 int count = m->m_pkthdr.len; 2338 2339 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2340 2341 while (count > 0 && m) { 2342 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2343 m, m->m_data, m->m_len); 2344 msk_dump_bytes(mtod(m, char *), m->m_len); 2345 2346 count -= m->m_len; 2347 m = m->m_next; 2348 } 2349 } 2350 #endif 2351 2352 static int 2353 msk_sysctl_handler(SYSCTLFN_ARGS) 2354 { 2355 int error, t; 2356 struct sysctlnode node; 2357 struct sk_softc *sc; 2358 2359 node = *rnode; 2360 sc = node.sysctl_data; 2361 t = sc->sk_int_mod; 2362 node.sysctl_data = &t; 2363 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2364 if (error || newp == NULL) 2365 return error; 2366 2367 if (t < SK_IM_MIN || t > SK_IM_MAX) 2368 return EINVAL; 2369 2370 /* update the softc with sysctl-changed value, and mark 2371 for hardware update */ 2372 sc->sk_int_mod = t; 2373 sc->sk_int_mod_pending = 1; 2374 return 0; 2375 } 2376 2377 /* 2378 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2379 * set up in skc_attach() 2380 */ 2381 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2382 { 2383 int rc; 2384 const struct sysctlnode *node; 2385 2386 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2387 0, CTLTYPE_NODE, "hw", NULL, 2388 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2389 goto err; 2390 } 2391 2392 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2393 0, CTLTYPE_NODE, "msk", 2394 SYSCTL_DESCR("msk interface controls"), 2395 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2396 goto err; 2397 } 2398 2399 msk_root_num = node->sysctl_num; 2400 return; 2401 2402 err: 2403 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2404 } 2405
Indexes created Thu Oct 02 07:10:07 GMT 2025