if_msk.c revision 1.3.6.2
1 /* $NetBSD: if_msk.c,v 1.3.6.2 2006/12/30 20:48:45 yamt Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.11 2006/08/17 22:07:40 brad Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include "bpfilter.h" 55 #include "rnd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/kernel.h> 63 #include <sys/socket.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/callout.h> 67 #include <sys/sysctl.h> 68 #include <sys/endian.h> 69 #ifdef __NetBSD__ 70 #define letoh16 htole16 71 #define letoh32 htole32 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_types.h> 77 78 #include <net/if_media.h> 79 80 #if NBPFILTER > 0 81 #include <net/bpf.h> 82 #endif 83 #if NRND > 0 84 #include <sys/rnd.h> 85 #endif 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/brgphyreg.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcidevs.h> 94 95 #include <dev/pci/if_skreg.h> 96 #include <dev/pci/if_mskvar.h> 97 98 int mskc_probe(struct device *, struct cfdata *, void *); 99 void mskc_attach(struct device *, struct device *self, void *aux); 100 void mskc_shutdown(void *); 101 int msk_probe(struct device *, struct cfdata *, void *); 102 void msk_attach(struct device *, struct device *self, void *aux); 103 int mskcprint(void *, const char *); 104 int msk_intr(void *); 105 void msk_intr_yukon(struct sk_if_softc *); 106 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 107 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 108 void msk_txeof(struct sk_if_softc *); 109 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 110 void msk_start(struct ifnet *); 111 int msk_ioctl(struct ifnet *, u_long, caddr_t); 112 int msk_init(struct ifnet *); 113 void msk_init_yukon(struct sk_if_softc *); 114 void msk_stop(struct ifnet *, int); 115 void msk_watchdog(struct ifnet *); 116 int msk_ifmedia_upd(struct ifnet *); 117 void msk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 void msk_reset(struct sk_softc *); 119 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 120 int msk_alloc_jumbo_mem(struct sk_if_softc *); 121 void *msk_jalloc(struct sk_if_softc *); 122 void msk_jfree(struct mbuf *, caddr_t, size_t, void *); 123 int msk_init_rx_ring(struct sk_if_softc *); 124 int msk_init_tx_ring(struct sk_if_softc *); 125 126 void msk_update_int_mod(struct sk_softc *); 127 128 int msk_marv_miibus_readreg(struct device *, int, int); 129 void msk_marv_miibus_writereg(struct device *, int, int, int); 130 void msk_marv_miibus_statchg(struct device *); 131 132 u_int32_t msk_yukon_hash(caddr_t); 133 void msk_setfilt(struct sk_if_softc *, caddr_t, int); 134 void msk_setmulti(struct sk_if_softc *); 135 void msk_setpromisc(struct sk_if_softc *); 136 void msk_yukon_tick(void *); 137 138 /* #define MSK_DEBUG 1 */ 139 #ifdef MSK_DEBUG 140 #define DPRINTF(x) if (mskdebug) printf x 141 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 142 int mskdebug = MSK_DEBUG; 143 144 void msk_dump_txdesc(struct msk_tx_desc *, int); 145 void msk_dump_mbuf(struct mbuf *); 146 void msk_dump_bytes(const char *, int); 147 #else 148 #define DPRINTF(x) 149 #define DPRINTFN(n,x) 150 #endif 151 152 static int msk_sysctl_handler(SYSCTLFN_PROTO); 153 static int msk_root_num; 154 155 /* supported device vendors */ 156 static const struct msk_product { 157 pci_vendor_id_t msk_vendor; 158 pci_product_id_t msk_product; 159 } msk_products[] = { 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_3 }, 175 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 176 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 177 }; 178 179 static inline u_int32_t 180 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 181 { 182 return CSR_READ_4(sc, reg); 183 } 184 185 static inline u_int16_t 186 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 187 { 188 return CSR_READ_2(sc, reg); 189 } 190 191 static inline u_int8_t 192 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 193 { 194 return CSR_READ_1(sc, reg); 195 } 196 197 static inline void 198 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 199 { 200 CSR_WRITE_4(sc, reg, x); 201 } 202 203 static inline void 204 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 205 { 206 CSR_WRITE_2(sc, reg, x); 207 } 208 209 static inline void 210 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 211 { 212 CSR_WRITE_1(sc, reg, x); 213 } 214 215 int 216 msk_marv_miibus_readreg(struct device *dev, int phy, int reg) 217 { 218 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 219 u_int16_t val; 220 int i; 221 222 if (phy != 0 || 223 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 224 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 225 DPRINTFN(9, ("msk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 226 phy, reg)); 227 return (0); 228 } 229 230 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 231 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 232 233 for (i = 0; i < SK_TIMEOUT; i++) { 234 DELAY(1); 235 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 236 if (val & YU_SMICR_READ_VALID) 237 break; 238 } 239 240 if (i == SK_TIMEOUT) { 241 aprint_error("%s: phy failed to come ready\n", 242 sc_if->sk_dev.dv_xname); 243 return (0); 244 } 245 246 DPRINTFN(9, ("msk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 247 SK_TIMEOUT)); 248 249 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 250 251 DPRINTFN(9, ("msk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 252 phy, reg, val)); 253 254 return (val); 255 } 256 257 void 258 msk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 259 { 260 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 261 int i; 262 263 DPRINTFN(9, ("msk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 264 phy, reg, val)); 265 266 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 267 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 268 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 269 270 for (i = 0; i < SK_TIMEOUT; i++) { 271 DELAY(1); 272 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 273 break; 274 } 275 276 if (i == SK_TIMEOUT) 277 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 278 } 279 280 void 281 msk_marv_miibus_statchg(struct device *dev) 282 { 283 DPRINTFN(9, ("msk_marv_miibus_statchg: gpcr=%x\n", 284 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 285 } 286 287 #define HASH_BITS 6 288 289 u_int32_t 290 msk_yukon_hash(caddr_t addr) 291 { 292 u_int32_t crc; 293 294 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 295 return (crc & ((1 << HASH_BITS) - 1)); 296 } 297 298 void 299 msk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 300 { 301 int base = XM_RXFILT_ENTRY(slot); 302 303 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 304 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 305 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 306 } 307 308 void 309 msk_setmulti(struct sk_if_softc *sc_if) 310 { 311 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 312 u_int32_t hashes[2] = { 0, 0 }; 313 int h; 314 struct ethercom *ec = &sc_if->sk_ethercom; 315 struct ether_multi *enm; 316 struct ether_multistep step; 317 318 /* First, zot all the existing filters. */ 319 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 320 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 321 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 322 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 323 324 325 /* Now program new ones. */ 326 allmulti: 327 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 328 hashes[0] = 0xFFFFFFFF; 329 hashes[1] = 0xFFFFFFFF; 330 } else { 331 /* First find the tail of the list. */ 332 ETHER_FIRST_MULTI(step, ec, enm); 333 while (enm != NULL) { 334 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 335 ETHER_ADDR_LEN)) { 336 ifp->if_flags |= IFF_ALLMULTI; 337 goto allmulti; 338 } 339 h = msk_yukon_hash(enm->enm_addrlo); 340 if (h < 32) 341 hashes[0] |= (1 << h); 342 else 343 hashes[1] |= (1 << (h - 32)); 344 345 ETHER_NEXT_MULTI(step, enm); 346 } 347 } 348 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 353 } 354 355 void 356 msk_setpromisc(struct sk_if_softc *sc_if) 357 { 358 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 359 360 if (ifp->if_flags & IFF_PROMISC) 361 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 362 YU_RCR_UFLEN | YU_RCR_MUFLEN); 363 else 364 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 365 YU_RCR_UFLEN | YU_RCR_MUFLEN); 366 } 367 368 int 369 msk_init_rx_ring(struct sk_if_softc *sc_if) 370 { 371 struct msk_chain_data *cd = &sc_if->sk_cdata; 372 struct msk_ring_data *rd = sc_if->sk_rdata; 373 int i, nexti; 374 375 bzero((char *)rd->sk_rx_ring, 376 sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 377 378 for (i = 0; i < MSK_RX_RING_CNT; i++) { 379 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 380 if (i == (MSK_RX_RING_CNT - 1)) 381 nexti = 0; 382 else 383 nexti = i + 1; 384 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 385 } 386 387 for (i = 0; i < MSK_RX_RING_CNT; i++) { 388 if (msk_newbuf(sc_if, i, NULL, 389 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 390 aprint_error("%s: failed alloc of %dth mbuf\n", 391 sc_if->sk_dev.dv_xname, i); 392 return (ENOBUFS); 393 } 394 } 395 396 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 397 sc_if->sk_cdata.sk_rx_cons = 0; 398 399 return (0); 400 } 401 402 int 403 msk_init_tx_ring(struct sk_if_softc *sc_if) 404 { 405 struct sk_softc *sc = sc_if->sk_softc; 406 struct msk_chain_data *cd = &sc_if->sk_cdata; 407 struct msk_ring_data *rd = sc_if->sk_rdata; 408 bus_dmamap_t dmamap; 409 struct sk_txmap_entry *entry; 410 int i, nexti; 411 412 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 413 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 414 415 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 416 for (i = 0; i < MSK_TX_RING_CNT; i++) { 417 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 418 if (i == (MSK_TX_RING_CNT - 1)) 419 nexti = 0; 420 else 421 nexti = i + 1; 422 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 423 424 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 425 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 426 return (ENOBUFS); 427 428 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 429 if (!entry) { 430 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 431 return (ENOBUFS); 432 } 433 entry->dmamap = dmamap; 434 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 435 } 436 437 sc_if->sk_cdata.sk_tx_prod = 0; 438 sc_if->sk_cdata.sk_tx_cons = 0; 439 sc_if->sk_cdata.sk_tx_cnt = 0; 440 441 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 442 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 443 444 return (0); 445 } 446 447 int 448 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 449 bus_dmamap_t dmamap) 450 { 451 struct mbuf *m_new = NULL; 452 struct sk_chain *c; 453 struct msk_rx_desc *r; 454 455 if (m == NULL) { 456 caddr_t buf = NULL; 457 458 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 459 if (m_new == NULL) 460 return (ENOBUFS); 461 462 /* Allocate the jumbo buffer */ 463 buf = msk_jalloc(sc_if); 464 if (buf == NULL) { 465 m_freem(m_new); 466 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 467 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 468 return (ENOBUFS); 469 } 470 471 /* Attach the buffer to the mbuf */ 472 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 473 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 474 } else { 475 /* 476 * We're re-using a previously allocated mbuf; 477 * be sure to re-init pointers and lengths to 478 * default values. 479 */ 480 m_new = m; 481 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 482 m_new->m_data = m_new->m_ext.ext_buf; 483 } 484 m_adj(m_new, ETHER_ALIGN); 485 486 c = &sc_if->sk_cdata.sk_rx_chain[i]; 487 r = c->sk_le; 488 c->sk_mbuf = m_new; 489 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 490 (((vaddr_t)m_new->m_data 491 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 492 r->sk_len = htole16(SK_JLEN); 493 r->sk_ctl = 0; 494 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 495 496 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 497 498 return (0); 499 } 500 501 /* 502 * Memory management for jumbo frames. 503 */ 504 505 int 506 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 507 { 508 struct sk_softc *sc = sc_if->sk_softc; 509 caddr_t ptr, kva; 510 bus_dma_segment_t seg; 511 int i, rseg, state, error; 512 struct sk_jpool_entry *entry; 513 514 state = error = 0; 515 516 /* Grab a big chunk o' storage. */ 517 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 518 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 519 aprint_error(": can't alloc rx buffers"); 520 return (ENOBUFS); 521 } 522 523 state = 1; 524 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, &kva, 525 BUS_DMA_NOWAIT)) { 526 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 527 error = ENOBUFS; 528 goto out; 529 } 530 531 state = 2; 532 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 533 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 534 aprint_error(": can't create dma map"); 535 error = ENOBUFS; 536 goto out; 537 } 538 539 state = 3; 540 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 541 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 542 aprint_error(": can't load dma map"); 543 error = ENOBUFS; 544 goto out; 545 } 546 547 state = 4; 548 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 549 DPRINTFN(1,("msk_jumbo_buf = %p\n", (caddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 550 551 LIST_INIT(&sc_if->sk_jfree_listhead); 552 LIST_INIT(&sc_if->sk_jinuse_listhead); 553 554 /* 555 * Now divide it up into 9K pieces and save the addresses 556 * in an array. 557 */ 558 ptr = sc_if->sk_cdata.sk_jumbo_buf; 559 for (i = 0; i < MSK_JSLOTS; i++) { 560 sc_if->sk_cdata.sk_jslots[i] = ptr; 561 ptr += SK_JLEN; 562 entry = malloc(sizeof(struct sk_jpool_entry), 563 M_DEVBUF, M_NOWAIT); 564 if (entry == NULL) { 565 aprint_error(": no memory for jumbo buffer queue!"); 566 error = ENOBUFS; 567 goto out; 568 } 569 entry->slot = i; 570 if (i) 571 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 572 entry, jpool_entries); 573 else 574 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 575 entry, jpool_entries); 576 } 577 out: 578 if (error != 0) { 579 switch (state) { 580 case 4: 581 bus_dmamap_unload(sc->sc_dmatag, 582 sc_if->sk_cdata.sk_rx_jumbo_map); 583 case 3: 584 bus_dmamap_destroy(sc->sc_dmatag, 585 sc_if->sk_cdata.sk_rx_jumbo_map); 586 case 2: 587 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 588 case 1: 589 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 590 break; 591 default: 592 break; 593 } 594 } 595 596 return (error); 597 } 598 599 /* 600 * Allocate a jumbo buffer. 601 */ 602 void * 603 msk_jalloc(struct sk_if_softc *sc_if) 604 { 605 struct sk_jpool_entry *entry; 606 607 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 608 609 if (entry == NULL) 610 return (NULL); 611 612 LIST_REMOVE(entry, jpool_entries); 613 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 614 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 615 } 616 617 /* 618 * Release a jumbo buffer. 619 */ 620 void 621 msk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 622 { 623 struct sk_jpool_entry *entry; 624 struct sk_if_softc *sc; 625 int i, s; 626 627 /* Extract the softc struct pointer. */ 628 sc = (struct sk_if_softc *)arg; 629 630 if (sc == NULL) 631 panic("msk_jfree: can't find softc pointer!"); 632 633 /* calculate the slot this buffer belongs to */ 634 635 i = ((vaddr_t)buf 636 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 637 638 if ((i < 0) || (i >= MSK_JSLOTS)) 639 panic("sk_jfree: asked to free buffer that we don't manage!"); 640 641 s = splvm(); 642 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 643 if (entry == NULL) 644 panic("msk_jfree: buffer not in use!"); 645 entry->slot = i; 646 LIST_REMOVE(entry, jpool_entries); 647 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 648 649 if (__predict_true(m != NULL)) 650 pool_cache_put(&mbpool_cache, m); 651 splx(s); 652 } 653 654 /* 655 * Set media options. 656 */ 657 int 658 msk_ifmedia_upd(struct ifnet *ifp) 659 { 660 struct sk_if_softc *sc_if = ifp->if_softc; 661 662 msk_init(ifp); 663 mii_mediachg(&sc_if->sk_mii); 664 return (0); 665 } 666 667 /* 668 * Report current media status. 669 */ 670 void 671 msk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 672 { 673 struct sk_if_softc *sc_if = ifp->if_softc; 674 675 mii_pollstat(&sc_if->sk_mii); 676 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 677 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 678 } 679 680 int 681 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 682 { 683 struct sk_if_softc *sc_if = ifp->if_softc; 684 struct ifreq *ifr = (struct ifreq *) data; 685 struct mii_data *mii; 686 int s, error = 0; 687 688 s = splnet(); 689 690 switch(command) { 691 case SIOCGIFMEDIA: 692 case SIOCSIFMEDIA: 693 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA\n")); 694 mii = &sc_if->sk_mii; 695 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 696 DPRINTFN(2,("msk_ioctl: SIOC[GS]IFMEDIA done\n")); 697 break; 698 default: 699 DPRINTFN(2, ("msk_ioctl ETHER\n")); 700 error = ether_ioctl(ifp, command, data); 701 702 if (error == ENETRESET) { 703 /* 704 * Multicast list has changed; set the hardware 705 * filter accordingly. 706 */ 707 if (ifp->if_flags & IFF_RUNNING) 708 msk_setmulti(sc_if); 709 error = 0; 710 } 711 break; 712 } 713 714 splx(s); 715 return (error); 716 } 717 718 void 719 msk_update_int_mod(struct sk_softc *sc) 720 { 721 u_int32_t sk_imtimer_ticks; 722 723 /* 724 * Configure interrupt moderation. The moderation timer 725 * defers interrupts specified in the interrupt moderation 726 * timer mask based on the timeout specified in the interrupt 727 * moderation timer init register. Each bit in the timer 728 * register represents one tick, so to specify a timeout in 729 * microseconds, we have to multiply by the correct number of 730 * ticks-per-microsecond. 731 */ 732 switch (sc->sk_type) { 733 case SK_YUKON_EC: 734 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 735 break; 736 default: 737 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 738 } 739 aprint_verbose("%s: interrupt moderation is %d us\n", 740 sc->sk_dev.dv_xname, sc->sk_int_mod); 741 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 742 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 743 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 744 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 745 sc->sk_int_mod_pending = 0; 746 } 747 748 static int 749 msk_lookup(const struct pci_attach_args *pa) 750 { 751 const struct msk_product *pmsk; 752 753 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 754 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 755 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 756 return 1; 757 } 758 return 0; 759 } 760 761 /* 762 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 763 * IDs against our list and return a device name if we find a match. 764 */ 765 int 766 mskc_probe(struct device *parent, struct cfdata *match, 767 void *aux) 768 { 769 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 770 771 return msk_lookup(pa); 772 } 773 774 /* 775 * Force the GEnesis into reset, then bring it out of reset. 776 */ 777 void msk_reset(struct sk_softc *sc) 778 { 779 u_int32_t sk_imtimer_ticks; 780 int reg; 781 782 DPRINTFN(2, ("msk_reset\n")); 783 784 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 785 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 786 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 787 788 DELAY(1000); 789 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 790 DELAY(2); 791 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 792 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 793 794 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 795 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 796 CSR_READ_2(sc, SK_LINK_CTRL))); 797 798 /* Disable ASF */ 799 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 800 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 801 802 /* Clear I2C IRQ noise */ 803 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 804 805 /* Disable hardware timer */ 806 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 807 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 808 809 /* Disable descriptor polling */ 810 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 811 812 /* Disable time stamps */ 813 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 814 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 815 816 /* Enable RAM interface */ 817 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 818 for (reg = SK_TO0;reg <= SK_TO11; reg++) 819 sk_win_write_1(sc, reg, 36); 820 821 /* 822 * Configure interrupt moderation. The moderation timer 823 * defers interrupts specified in the interrupt moderation 824 * timer mask based on the timeout specified in the interrupt 825 * moderation timer init register. Each bit in the timer 826 * register represents one tick, so to specify a timeout in 827 * microseconds, we have to multiply by the correct number of 828 * ticks-per-microsecond. 829 */ 830 switch (sc->sk_type) { 831 case SK_YUKON_EC: 832 case SK_YUKON_XL: 833 case SK_YUKON_FE: 834 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 835 break; 836 default: 837 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 838 } 839 840 /* Reset status ring. */ 841 bzero((char *)sc->sk_status_ring, 842 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 843 sc->sk_status_idx = 0; 844 845 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 846 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 847 848 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 849 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 850 sc->sk_status_map->dm_segs[0].ds_addr); 851 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 852 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 853 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 10); 854 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 16); 855 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 16); 856 857 #if 0 858 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 859 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 860 861 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(20)); 862 #else 863 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, SK_IM_USECS(4)); 864 #endif 865 866 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 867 868 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 869 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 870 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 871 872 msk_update_int_mod(sc); 873 } 874 875 int 876 msk_probe(struct device *parent, struct cfdata *match, 877 void *aux) 878 { 879 struct skc_attach_args *sa = aux; 880 881 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 882 return (0); 883 884 switch (sa->skc_type) { 885 case SK_YUKON_XL: 886 case SK_YUKON_EC_U: 887 case SK_YUKON_EC: 888 case SK_YUKON_FE: 889 return (1); 890 } 891 892 return (0); 893 } 894 895 /* 896 * Each XMAC chip is attached as a separate logical IP interface. 897 * Single port cards will have only one logical interface of course. 898 */ 899 void 900 msk_attach(struct device *parent, struct device *self, void *aux) 901 { 902 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 903 struct sk_softc *sc = (struct sk_softc *)parent; 904 struct skc_attach_args *sa = aux; 905 struct ifnet *ifp; 906 caddr_t kva; 907 bus_dma_segment_t seg; 908 int i, rseg; 909 u_int32_t chunk, val; 910 911 sc_if->sk_port = sa->skc_port; 912 sc_if->sk_softc = sc; 913 sc->sk_if[sa->skc_port] = sc_if; 914 915 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 916 917 /* 918 * Get station address for this interface. Note that 919 * dual port cards actually come with three station 920 * addresses: one for each port, plus an extra. The 921 * extra one is used by the SysKonnect driver software 922 * as a 'virtual' station address for when both ports 923 * are operating in failover mode. Currently we don't 924 * use this extra address. 925 */ 926 for (i = 0; i < ETHER_ADDR_LEN; i++) 927 sc_if->sk_enaddr[i] = 928 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 929 930 aprint_normal(": Ethernet address %s\n", 931 ether_sprintf(sc_if->sk_enaddr)); 932 933 /* 934 * Set up RAM buffer addresses. The NIC will have a certain 935 * amount of SRAM on it, somewhere between 512K and 2MB. We 936 * need to divide this up a) between the transmitter and 937 * receiver and b) between the two XMACs, if this is a 938 * dual port NIC. Our algorithm is to divide up the memory 939 * evenly so that everyone gets a fair share. 940 * 941 * Just to be contrary, Yukon2 appears to have separate memory 942 * for each MAC. 943 */ 944 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 945 val = sc->sk_rboff / sizeof(u_int64_t); 946 sc_if->sk_rx_ramstart = val; 947 val += (chunk / sizeof(u_int64_t)); 948 sc_if->sk_rx_ramend = val - 1; 949 chunk = sc->sk_ramsize - chunk; 950 sc_if->sk_tx_ramstart = val; 951 val += (chunk / sizeof(u_int64_t)); 952 sc_if->sk_tx_ramend = val - 1; 953 954 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 955 " tx_ramstart=%#x tx_ramend=%#x\n", 956 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 957 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 958 959 /* Read and save PHY type */ 960 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 961 962 /* Set PHY address */ 963 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 964 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 965 /* not initialized, punt */ 966 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 967 968 sc->sk_coppertype = 1; 969 } 970 971 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 972 973 if (!(sc->sk_coppertype)) 974 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 975 976 /* Allocate the descriptor queues. */ 977 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 978 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 979 aprint_error(": can't alloc rx buffers\n"); 980 goto fail; 981 } 982 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 983 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 984 aprint_error(": can't map dma buffers (%zu bytes)\n", 985 sizeof(struct msk_ring_data)); 986 goto fail_1; 987 } 988 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 989 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 990 &sc_if->sk_ring_map)) { 991 aprint_error(": can't create dma map\n"); 992 goto fail_2; 993 } 994 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 995 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 996 aprint_error(": can't load dma map\n"); 997 goto fail_3; 998 } 999 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1000 bzero(sc_if->sk_rdata, sizeof(struct msk_ring_data)); 1001 1002 ifp = &sc_if->sk_ethercom.ec_if; 1003 /* Try to allocate memory for jumbo buffers. */ 1004 if (msk_alloc_jumbo_mem(sc_if)) { 1005 aprint_error(": jumbo buffer allocation failed\n"); 1006 goto fail_3; 1007 } 1008 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1009 | ETHERCAP_JUMBO_MTU; 1010 1011 ifp->if_softc = sc_if; 1012 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1013 ifp->if_ioctl = msk_ioctl; 1014 ifp->if_start = msk_start; 1015 ifp->if_stop = msk_stop; 1016 ifp->if_init = msk_init; 1017 ifp->if_watchdog = msk_watchdog; 1018 ifp->if_baudrate = 1000000000; 1019 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1020 IFQ_SET_READY(&ifp->if_snd); 1021 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1022 1023 /* 1024 * Do miibus setup. 1025 */ 1026 msk_init_yukon(sc_if); 1027 1028 DPRINTFN(2, ("msk_attach: 1\n")); 1029 1030 sc_if->sk_mii.mii_ifp = ifp; 1031 sc_if->sk_mii.mii_readreg = msk_marv_miibus_readreg; 1032 sc_if->sk_mii.mii_writereg = msk_marv_miibus_writereg; 1033 sc_if->sk_mii.mii_statchg = msk_marv_miibus_statchg; 1034 1035 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1036 msk_ifmedia_upd, msk_ifmedia_sts); 1037 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1038 MII_OFFSET_ANY, 0); 1039 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1040 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1041 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1042 0, NULL); 1043 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1044 } else 1045 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1046 1047 callout_init(&sc_if->sk_tick_ch); 1048 callout_setfunc(&sc_if->sk_tick_ch, msk_yukon_tick, sc_if); 1049 callout_schedule(&sc_if->sk_tick_ch, hz); 1050 1051 /* 1052 * Call MI attach routines. 1053 */ 1054 if_attach(ifp); 1055 ether_ifattach(ifp, sc_if->sk_enaddr); 1056 1057 shutdownhook_establish(mskc_shutdown, sc); 1058 1059 #if NRND > 0 1060 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1061 RND_TYPE_NET, 0); 1062 #endif 1063 1064 DPRINTFN(2, ("msk_attach: end\n")); 1065 return; 1066 1067 fail_3: 1068 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1069 fail_2: 1070 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1071 fail_1: 1072 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1073 fail: 1074 sc->sk_if[sa->skc_port] = NULL; 1075 } 1076 1077 int 1078 mskcprint(void *aux, const char *pnp) 1079 { 1080 struct skc_attach_args *sa = aux; 1081 1082 if (pnp) 1083 aprint_normal("sk port %c at %s", 1084 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1085 else 1086 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1087 return (UNCONF); 1088 } 1089 1090 /* 1091 * Attach the interface. Allocate softc structures, do ifmedia 1092 * setup and ethernet/BPF attach. 1093 */ 1094 void 1095 mskc_attach(struct device *parent, struct device *self, void *aux) 1096 { 1097 struct sk_softc *sc = (struct sk_softc *)self; 1098 struct pci_attach_args *pa = aux; 1099 struct skc_attach_args skca; 1100 pci_chipset_tag_t pc = pa->pa_pc; 1101 pcireg_t command, memtype; 1102 pci_intr_handle_t ih; 1103 const char *intrstr = NULL; 1104 bus_size_t size; 1105 int rc, sk_nodenum; 1106 u_int8_t hw, skrs; 1107 const char *revstr = NULL; 1108 const struct sysctlnode *node; 1109 caddr_t kva; 1110 bus_dma_segment_t seg; 1111 int rseg; 1112 1113 DPRINTFN(2, ("begin mskc_attach\n")); 1114 1115 /* 1116 * Handle power management nonsense. 1117 */ 1118 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1119 1120 if (command == 0x01) { 1121 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1122 if (command & SK_PSTATE_MASK) { 1123 u_int32_t iobase, membase, irq; 1124 1125 /* Save important PCI config data. */ 1126 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1127 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1128 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1129 1130 /* Reset the power state. */ 1131 aprint_normal("%s chip is in D%d power mode " 1132 "-- setting to D0\n", sc->sk_dev.dv_xname, 1133 command & SK_PSTATE_MASK); 1134 command &= 0xFFFFFFFC; 1135 pci_conf_write(pc, pa->pa_tag, 1136 SK_PCI_PWRMGMTCTRL, command); 1137 1138 /* Restore PCI config data. */ 1139 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1140 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1141 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1142 } 1143 } 1144 1145 /* 1146 * Map control/status registers. 1147 */ 1148 1149 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1150 switch (memtype) { 1151 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1152 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1153 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1154 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1155 NULL, &size) == 0) 1156 break; 1157 default: 1158 aprint_error(": can't map mem space\n"); 1159 return; 1160 } 1161 1162 sc->sc_dmatag = pa->pa_dmat; 1163 1164 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1165 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1166 1167 /* bail out here if chip is not recognized */ 1168 if (!(SK_IS_YUKON(sc))) { 1169 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1170 goto fail_1; 1171 } 1172 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1173 1174 /* Allocate interrupt */ 1175 if (pci_intr_map(pa, &ih)) { 1176 aprint_error(": couldn't map interrupt\n"); 1177 goto fail_1; 1178 } 1179 1180 intrstr = pci_intr_string(pc, ih); 1181 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1182 if (sc->sk_intrhand == NULL) { 1183 aprint_error(": couldn't establish interrupt"); 1184 if (intrstr != NULL) 1185 aprint_error(" at %s", intrstr); 1186 aprint_error("\n"); 1187 goto fail_1; 1188 } 1189 1190 if (bus_dmamem_alloc(sc->sc_dmatag, 1191 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1192 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1193 aprint_error(": can't alloc status buffers\n"); 1194 goto fail_2; 1195 } 1196 1197 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1198 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1199 &kva, BUS_DMA_NOWAIT)) { 1200 aprint_error(": can't map dma buffers (%zu bytes)\n", 1201 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1202 goto fail_3; 1203 } 1204 if (bus_dmamap_create(sc->sc_dmatag, 1205 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1206 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1207 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1208 aprint_error(": can't create dma map\n"); 1209 goto fail_4; 1210 } 1211 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1212 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1213 NULL, BUS_DMA_NOWAIT)) { 1214 aprint_error(": can't load dma map\n"); 1215 goto fail_5; 1216 } 1217 sc->sk_status_ring = (struct msk_status_desc *)kva; 1218 bzero(sc->sk_status_ring, 1219 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1220 1221 /* Reset the adapter. */ 1222 msk_reset(sc); 1223 1224 skrs = sk_win_read_1(sc, SK_EPROM0); 1225 if (skrs == 0x00) 1226 sc->sk_ramsize = 0x20000; 1227 else 1228 sc->sk_ramsize = skrs * (1<<12); 1229 sc->sk_rboff = SK_RBOFF_0; 1230 1231 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1232 sc->sk_ramsize, sc->sk_ramsize / 1024, 1233 sc->sk_rboff)); 1234 1235 /* Read and save physical media type */ 1236 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1237 1238 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1' || 1239 (SK_IS_YUKON2(sc) && !(sc->sk_pmd == 'L' || 1240 sc->sk_pmd == 'S'))) 1241 sc->sk_coppertype = 1; 1242 else 1243 sc->sk_coppertype = 0; 1244 1245 switch (sc->sk_type) { 1246 case SK_YUKON_XL: 1247 sc->sk_name = "Marvell Yukon-2 XL"; 1248 break; 1249 case SK_YUKON_EC_U: 1250 sc->sk_name = "Marvell Yukon-2 EC Ultra"; 1251 break; 1252 case SK_YUKON_EC: 1253 sc->sk_name = "Marvell Yukon-2 EC"; 1254 break; 1255 case SK_YUKON_FE: 1256 sc->sk_name = "Marvell Yukon-2 FE"; 1257 break; 1258 default: 1259 sc->sk_name = "Marvell Yukon (Unknown)"; 1260 } 1261 1262 if (sc->sk_type == SK_YUKON_XL) { 1263 switch (sc->sk_rev) { 1264 case SK_YUKON_XL_REV_A0: 1265 revstr = "A0"; 1266 break; 1267 case SK_YUKON_XL_REV_A1: 1268 revstr = "A1"; 1269 break; 1270 case SK_YUKON_XL_REV_A2: 1271 revstr = "A2"; 1272 break; 1273 case SK_YUKON_XL_REV_A3: 1274 revstr = "A3"; 1275 break; 1276 default: 1277 ; 1278 } 1279 } 1280 1281 if (sc->sk_type == SK_YUKON_EC) { 1282 switch (sc->sk_rev) { 1283 case SK_YUKON_EC_REV_A1: 1284 revstr = "A1"; 1285 break; 1286 case SK_YUKON_EC_REV_A2: 1287 revstr = "A2"; 1288 break; 1289 case SK_YUKON_EC_REV_A3: 1290 revstr = "A3"; 1291 break; 1292 default: 1293 ; 1294 } 1295 } 1296 1297 if (sc->sk_type == SK_YUKON_EC_U) { 1298 switch (sc->sk_rev) { 1299 case SK_YUKON_EC_U_REV_A0: 1300 revstr = "A0"; 1301 break; 1302 case SK_YUKON_EC_U_REV_A1: 1303 revstr = "A1"; 1304 break; 1305 default: 1306 ; 1307 } 1308 } 1309 1310 /* Announce the product name. */ 1311 aprint_normal(", %s", sc->sk_name); 1312 if (revstr != NULL) 1313 aprint_normal(" rev. %s", revstr); 1314 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1315 1316 1317 sc->sk_macs = 1; 1318 1319 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1320 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1321 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1322 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1323 sc->sk_macs++; 1324 } 1325 1326 skca.skc_port = SK_PORT_A; 1327 skca.skc_type = sc->sk_type; 1328 skca.skc_rev = sc->sk_rev; 1329 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1330 1331 if (sc->sk_macs > 1) { 1332 skca.skc_port = SK_PORT_B; 1333 skca.skc_type = sc->sk_type; 1334 skca.skc_rev = sc->sk_rev; 1335 (void)config_found(&sc->sk_dev, &skca, mskcprint); 1336 } 1337 1338 /* Turn on the 'driver is loaded' LED. */ 1339 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1340 1341 /* skc sysctl setup */ 1342 1343 sc->sk_int_mod = SK_IM_DEFAULT; 1344 sc->sk_int_mod_pending = 0; 1345 1346 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1347 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1348 SYSCTL_DESCR("mskc per-controller controls"), 1349 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1350 CTL_EOL)) != 0) { 1351 aprint_normal("%s: couldn't create sysctl node\n", 1352 sc->sk_dev.dv_xname); 1353 goto fail_6; 1354 } 1355 1356 sk_nodenum = node->sysctl_num; 1357 1358 /* interrupt moderation time in usecs */ 1359 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1360 CTLFLAG_READWRITE, 1361 CTLTYPE_INT, "int_mod", 1362 SYSCTL_DESCR("msk interrupt moderation timer"), 1363 msk_sysctl_handler, 0, sc, 1364 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1365 CTL_EOL)) != 0) { 1366 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1367 sc->sk_dev.dv_xname); 1368 goto fail_6; 1369 } 1370 1371 return; 1372 1373 fail_6: 1374 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1375 fail_5: 1376 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1377 fail_4: 1378 bus_dmamem_unmap(sc->sc_dmatag, kva, 1379 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1380 fail_3: 1381 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1382 fail_2: 1383 pci_intr_disestablish(pc, sc->sk_intrhand); 1384 fail_1: 1385 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1386 } 1387 1388 int 1389 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1390 { 1391 struct sk_softc *sc = sc_if->sk_softc; 1392 struct msk_tx_desc *f = NULL; 1393 u_int32_t frag, cur, cnt = 0; 1394 int i; 1395 struct sk_txmap_entry *entry; 1396 bus_dmamap_t txmap; 1397 1398 DPRINTFN(2, ("msk_encap\n")); 1399 1400 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1401 if (entry == NULL) { 1402 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1403 return (ENOBUFS); 1404 } 1405 txmap = entry->dmamap; 1406 1407 cur = frag = *txidx; 1408 1409 #ifdef MSK_DEBUG 1410 if (mskdebug >= 2) 1411 msk_dump_mbuf(m_head); 1412 #endif 1413 1414 /* 1415 * Start packing the mbufs in this chain into 1416 * the fragment pointers. Stop when we run out 1417 * of fragments or hit the end of the mbuf chain. 1418 */ 1419 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1420 BUS_DMA_NOWAIT)) { 1421 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1422 return (ENOBUFS); 1423 } 1424 1425 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1426 1427 /* Sync the DMA map. */ 1428 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1429 BUS_DMASYNC_PREWRITE); 1430 1431 for (i = 0; i < txmap->dm_nsegs; i++) { 1432 if ((MSK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1433 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1434 return (ENOBUFS); 1435 } 1436 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1437 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1438 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1439 f->sk_ctl = 0; 1440 if (cnt == 0) 1441 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1442 else 1443 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1444 cur = frag; 1445 SK_INC(frag, MSK_TX_RING_CNT); 1446 cnt++; 1447 } 1448 1449 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1450 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1451 1452 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1453 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1454 1455 /* Sync descriptors before handing to chip */ 1456 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1457 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1458 1459 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1460 1461 /* Sync first descriptor to hand it off */ 1462 MSK_CDTXSYNC(sc_if, *txidx, 1, 1463 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1464 1465 sc_if->sk_cdata.sk_tx_cnt += cnt; 1466 1467 #ifdef MSK_DEBUG 1468 if (mskdebug >= 2) { 1469 struct msk_tx_desc *le; 1470 u_int32_t idx; 1471 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1472 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1473 msk_dump_txdesc(le, idx); 1474 } 1475 } 1476 #endif 1477 1478 *txidx = frag; 1479 1480 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1481 1482 return (0); 1483 } 1484 1485 void 1486 msk_start(struct ifnet *ifp) 1487 { 1488 struct sk_if_softc *sc_if = ifp->if_softc; 1489 struct mbuf *m_head = NULL; 1490 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1491 int pkts = 0; 1492 1493 DPRINTFN(2, ("msk_start\n")); 1494 1495 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1496 IFQ_POLL(&ifp->if_snd, m_head); 1497 if (m_head == NULL) 1498 break; 1499 1500 /* 1501 * Pack the data into the transmit ring. If we 1502 * don't have room, set the OACTIVE flag and wait 1503 * for the NIC to drain the ring. 1504 */ 1505 if (msk_encap(sc_if, m_head, &idx)) { 1506 ifp->if_flags |= IFF_OACTIVE; 1507 break; 1508 } 1509 1510 /* now we are committed to transmit the packet */ 1511 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1512 pkts++; 1513 1514 /* 1515 * If there's a BPF listener, bounce a copy of this frame 1516 * to him. 1517 */ 1518 #if NBPFILTER > 0 1519 if (ifp->if_bpf) 1520 bpf_mtap(ifp->if_bpf, m_head); 1521 #endif 1522 } 1523 if (pkts == 0) 1524 return; 1525 1526 /* Transmit */ 1527 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1528 sc_if->sk_cdata.sk_tx_prod = idx; 1529 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1530 1531 /* Set a timeout in case the chip goes out to lunch. */ 1532 ifp->if_timer = 5; 1533 } 1534 } 1535 1536 void 1537 msk_watchdog(struct ifnet *ifp) 1538 { 1539 struct sk_if_softc *sc_if = ifp->if_softc; 1540 1541 /* 1542 * Reclaim first as there is a possibility of losing Tx completion 1543 * interrupts. 1544 */ 1545 msk_txeof(sc_if); 1546 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1547 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1548 1549 ifp->if_oerrors++; 1550 1551 /* XXX Resets both ports; we shouldn't do that. */ 1552 msk_reset(sc_if->sk_softc); 1553 msk_init(ifp); 1554 } 1555 } 1556 1557 void 1558 mskc_shutdown(void *v) 1559 { 1560 struct sk_softc *sc = v; 1561 1562 DPRINTFN(2, ("msk_shutdown\n")); 1563 1564 /* Turn off the 'driver is loaded' LED. */ 1565 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1566 1567 msk_reset(sc); 1568 } 1569 1570 __inline int 1571 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1572 { 1573 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1574 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1575 YU_RXSTAT_JABBER)) != 0 || 1576 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1577 YU_RXSTAT_BYTES(stat) != len) 1578 return (0); 1579 1580 return (1); 1581 } 1582 1583 void 1584 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1585 { 1586 struct sk_softc *sc = sc_if->sk_softc; 1587 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1588 struct mbuf *m; 1589 struct sk_chain *cur_rx; 1590 int cur, total_len = len; 1591 bus_dmamap_t dmamap; 1592 1593 DPRINTFN(2, ("msk_rxeof\n")); 1594 1595 cur = sc_if->sk_cdata.sk_rx_cons; 1596 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1597 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1598 1599 /* Sync the descriptor */ 1600 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1601 1602 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1603 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1604 1605 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1606 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1607 1608 m = cur_rx->sk_mbuf; 1609 cur_rx->sk_mbuf = NULL; 1610 1611 if (total_len < SK_MIN_FRAMELEN || 1612 total_len > SK_JUMBO_FRAMELEN || 1613 msk_rxvalid(sc, rxstat, total_len) == 0) { 1614 ifp->if_ierrors++; 1615 msk_newbuf(sc_if, cur, m, dmamap); 1616 return; 1617 } 1618 1619 /* 1620 * Try to allocate a new jumbo buffer. If that fails, copy the 1621 * packet to mbufs and put the jumbo buffer back in the ring 1622 * so it can be re-used. If allocating mbufs fails, then we 1623 * have to drop the packet. 1624 */ 1625 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1626 struct mbuf *m0; 1627 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1628 total_len + ETHER_ALIGN, 0, ifp, NULL); 1629 msk_newbuf(sc_if, cur, m, dmamap); 1630 if (m0 == NULL) { 1631 ifp->if_ierrors++; 1632 return; 1633 } 1634 m_adj(m0, ETHER_ALIGN); 1635 m = m0; 1636 } else { 1637 m->m_pkthdr.rcvif = ifp; 1638 m->m_pkthdr.len = m->m_len = total_len; 1639 } 1640 1641 ifp->if_ipackets++; 1642 1643 #if NBPFILTER > 0 1644 if (ifp->if_bpf) 1645 bpf_mtap(ifp->if_bpf, m); 1646 #endif 1647 1648 /* pass it on. */ 1649 (*ifp->if_input)(ifp, m); 1650 } 1651 1652 void 1653 msk_txeof(struct sk_if_softc *sc_if) 1654 { 1655 struct sk_softc *sc = sc_if->sk_softc; 1656 struct msk_tx_desc *cur_tx; 1657 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1658 u_int32_t idx, sk_ctl; 1659 struct sk_txmap_entry *entry; 1660 1661 DPRINTFN(2, ("msk_txeof\n")); 1662 1663 /* 1664 * Go through our tx ring and free mbufs for those 1665 * frames that have been sent. 1666 */ 1667 idx = sc_if->sk_cdata.sk_tx_cons; 1668 while (idx != sk_win_read_2(sc, SK_STAT_BMU_TXA1_RIDX)) { 1669 MSK_CDTXSYNC(sc_if, idx, 1, 1670 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1671 1672 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1673 sk_ctl = letoh32(cur_tx->sk_ctl); 1674 #ifdef MSK_DEBUG 1675 if (mskdebug >= 2) 1676 msk_dump_txdesc(cur_tx, idx); 1677 #endif 1678 if (sk_ctl & SK_TXCTL_LASTFRAG) 1679 ifp->if_opackets++; 1680 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1681 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1682 1683 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1684 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1685 1686 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1687 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1688 1689 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1690 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1691 link); 1692 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1693 } 1694 sc_if->sk_cdata.sk_tx_cnt--; 1695 SK_INC(idx, MSK_TX_RING_CNT); 1696 } 1697 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1698 1699 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1700 ifp->if_flags &= ~IFF_OACTIVE; 1701 1702 sc_if->sk_cdata.sk_tx_cons = idx; 1703 } 1704 1705 void 1706 msk_yukon_tick(void *xsc_if) 1707 { 1708 struct sk_if_softc *sc_if = xsc_if; 1709 struct mii_data *mii = &sc_if->sk_mii; 1710 1711 mii_tick(mii); 1712 callout_schedule(&sc_if->sk_tick_ch, hz); 1713 } 1714 1715 void 1716 msk_intr_yukon(struct sk_if_softc *sc_if) 1717 { 1718 u_int8_t status; 1719 1720 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1721 /* RX overrun */ 1722 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1723 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1724 SK_RFCTL_RX_FIFO_OVER); 1725 } 1726 /* TX underrun */ 1727 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1728 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1729 SK_TFCTL_TX_FIFO_UNDER); 1730 } 1731 1732 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1733 } 1734 1735 int 1736 msk_intr(void *xsc) 1737 { 1738 struct sk_softc *sc = xsc; 1739 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1740 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1741 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1742 int claimed = 0; 1743 u_int32_t status; 1744 u_int16_t idx; 1745 struct msk_status_desc *cur_st; 1746 1747 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1748 if (status == 0) { 1749 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1750 return (0); 1751 } 1752 1753 status = CSR_READ_4(sc, SK_ISR); 1754 1755 if (sc_if0 != NULL) 1756 ifp0 = &sc_if0->sk_ethercom.ec_if; 1757 if (sc_if1 != NULL) 1758 ifp1 = &sc_if1->sk_ethercom.ec_if; 1759 1760 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1761 (ifp0->if_flags & IFF_RUNNING)) { 1762 msk_intr_yukon(sc_if0); 1763 } 1764 1765 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1766 (ifp1->if_flags & IFF_RUNNING)) { 1767 msk_intr_yukon(sc_if1); 1768 } 1769 1770 idx = CSR_READ_2(sc, SK_STAT_BMU_PUTIDX); 1771 while (sc->sk_status_idx != idx) { 1772 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1773 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1774 1775 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1776 switch (cur_st->sk_opcode & ~SK_Y2_STOPC_OWN) { 1777 case SK_Y2_STOPC_RXSTAT: 1778 msk_rxeof(sc->sk_if[cur_st->sk_link], 1779 letoh16(cur_st->sk_len), 1780 letoh32(cur_st->sk_status)); 1781 SK_IF_WRITE_2(sc->sk_if[cur_st->sk_link], 0, 1782 SK_RXQ1_Y2_PREF_PUTIDX, 1783 sc->sk_if[cur_st->sk_link]->sk_cdata.sk_rx_prod); 1784 break; 1785 case SK_Y2_STOPC_TXSTAT: 1786 msk_txeof(sc->sk_if[cur_st->sk_link]); 1787 break; 1788 default: 1789 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 1790 break; 1791 } 1792 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1793 idx = CSR_READ_2(sc, SK_STAT_BMU_PUTIDX); 1794 } 1795 1796 if (status & SK_Y2_IMR_BMU) { 1797 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1798 claimed = 1; 1799 } 1800 1801 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1802 1803 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1804 msk_start(ifp0); 1805 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1806 msk_start(ifp1); 1807 1808 #if NRND > 0 1809 if (RND_ENABLED(&sc->rnd_source)) 1810 rnd_add_uint32(&sc->rnd_source, status); 1811 #endif 1812 1813 if (sc->sk_int_mod_pending) 1814 msk_update_int_mod(sc); 1815 1816 return claimed; 1817 } 1818 1819 void 1820 msk_init_yukon(struct sk_if_softc *sc_if) 1821 { 1822 u_int32_t phy, v; 1823 u_int16_t reg; 1824 struct sk_softc *sc; 1825 int i; 1826 1827 sc = sc_if->sk_softc; 1828 1829 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1830 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1831 1832 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1833 1834 /* GMAC and GPHY Reset */ 1835 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1836 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1837 DELAY(1000); 1838 1839 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1840 1841 #if 0 1842 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 1843 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 1844 #else 1845 phy = SK_GPHY_ENA_PAUSE; 1846 #endif 1847 1848 if (sc->sk_coppertype) 1849 phy |= SK_GPHY_COPPER; 1850 else 1851 phy |= SK_GPHY_FIBER; 1852 1853 DPRINTFN(3, ("msk_init_yukon: phy=%#x\n", phy)); 1854 1855 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 1856 DELAY(1000); 1857 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 1858 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1859 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1860 1861 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1862 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1863 1864 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1865 1866 /* unused read of the interrupt source register */ 1867 DPRINTFN(6, ("msk_init_yukon: 4\n")); 1868 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1869 1870 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 1871 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 1872 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1873 1874 /* MIB Counter Clear Mode set */ 1875 reg |= YU_PAR_MIB_CLR; 1876 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 1877 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 1878 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1879 1880 /* MIB Counter Clear Mode clear */ 1881 DPRINTFN(6, ("msk_init_yukon: 5\n")); 1882 reg &= ~YU_PAR_MIB_CLR; 1883 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 1884 1885 /* receive control reg */ 1886 DPRINTFN(6, ("msk_init_yukon: 7\n")); 1887 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 1888 1889 /* transmit parameter register */ 1890 DPRINTFN(6, ("msk_init_yukon: 8\n")); 1891 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 1892 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 1893 1894 /* serial mode register */ 1895 DPRINTFN(6, ("msk_init_yukon: 9\n")); 1896 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 1897 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 1898 YU_SMR_IPG_DATA(0x1e)); 1899 1900 DPRINTFN(6, ("msk_init_yukon: 10\n")); 1901 /* Setup Yukon's address */ 1902 for (i = 0; i < 3; i++) { 1903 /* Write Source Address 1 (unicast filter) */ 1904 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 1905 sc_if->sk_enaddr[i * 2] | 1906 sc_if->sk_enaddr[i * 2 + 1] << 8); 1907 } 1908 1909 for (i = 0; i < 3; i++) { 1910 reg = sk_win_read_2(sc_if->sk_softc, 1911 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 1912 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 1913 } 1914 1915 /* Set promiscuous mode */ 1916 msk_setpromisc(sc_if); 1917 1918 /* Set multicast filter */ 1919 DPRINTFN(6, ("msk_init_yukon: 11\n")); 1920 msk_setmulti(sc_if); 1921 1922 /* enable interrupt mask for counter overflows */ 1923 DPRINTFN(6, ("msk_init_yukon: 12\n")); 1924 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 1925 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 1926 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 1927 1928 /* Configure RX MAC FIFO Flush Mask */ 1929 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 1930 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 1931 YU_RXSTAT_JABBER; 1932 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 1933 1934 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 1935 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 1936 v = SK_TFCTL_OPERATION_ON; 1937 else 1938 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 1939 /* Configure RX MAC FIFO */ 1940 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 1941 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 1942 1943 /* Increase flush threshould to 64 bytes */ 1944 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 1945 SK_RFCTL_FIFO_THRESHOLD + 1); 1946 1947 /* Configure TX MAC FIFO */ 1948 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 1949 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 1950 1951 #if 1 1952 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 1953 #endif 1954 DPRINTFN(6, ("msk_init_yukon: end\n")); 1955 } 1956 1957 /* 1958 * Note that to properly initialize any part of the GEnesis chip, 1959 * you first have to take it out of reset mode. 1960 */ 1961 int 1962 msk_init(struct ifnet *ifp) 1963 { 1964 struct sk_if_softc *sc_if = ifp->if_softc; 1965 struct sk_softc *sc = sc_if->sk_softc; 1966 struct mii_data *mii = &sc_if->sk_mii; 1967 int s; 1968 uint32_t imr, sk_imtimer_ticks; 1969 1970 1971 DPRINTFN(2, ("msk_init\n")); 1972 1973 s = splnet(); 1974 1975 /* Cancel pending I/O and free all RX/TX buffers. */ 1976 msk_stop(ifp,0); 1977 1978 /* Configure I2C registers */ 1979 1980 /* Configure XMAC(s) */ 1981 msk_init_yukon(sc_if); 1982 mii_mediachg(mii); 1983 1984 /* Configure transmit arbiter(s) */ 1985 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 1986 #if 0 1987 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1988 #endif 1989 1990 /* Configure RAMbuffers */ 1991 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1992 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1993 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1994 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1995 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1996 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1997 1998 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 1999 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2000 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2001 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2002 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2003 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2004 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2005 2006 /* Configure BMUs */ 2007 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2008 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2009 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2010 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_WATERMARK, 0x00000600); 2011 2012 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2013 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2014 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2015 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_WATERMARK, 0x00000600); 2016 2017 /* Make sure the sync transmit queue is disabled. */ 2018 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2019 2020 /* Init descriptors */ 2021 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2022 aprint_error("%s: initialization failed: no " 2023 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2024 msk_stop(ifp,0); 2025 splx(s); 2026 return ENOBUFS; 2027 } 2028 2029 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2030 aprint_error("%s: initialization failed: no " 2031 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2032 msk_stop(ifp,0); 2033 splx(s); 2034 return ENOBUFS; 2035 } 2036 2037 /* Set interrupt moderation if changed via sysctl. */ 2038 switch (sc->sk_type) { 2039 case SK_YUKON_EC: 2040 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2041 break; 2042 default: 2043 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2044 } 2045 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2046 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2047 sk_win_write_4(sc, SK_IMTIMERINIT, 2048 SK_IM_USECS(sc->sk_int_mod)); 2049 aprint_verbose("%s: interrupt moderation is %d us\n", 2050 sc->sk_dev.dv_xname, sc->sk_int_mod); 2051 } 2052 2053 /* Initialize prefetch engine. */ 2054 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2055 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2056 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2057 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2058 MSK_RX_RING_ADDR(sc_if, 0)); 2059 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2060 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2061 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2062 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2063 2064 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2065 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2066 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2067 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2068 MSK_TX_RING_ADDR(sc_if, 0)); 2069 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2070 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2071 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2072 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2073 2074 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2075 sc_if->sk_cdata.sk_rx_prod); 2076 2077 /* Configure interrupt handling */ 2078 if (sc_if->sk_port == SK_PORT_A) 2079 sc->sk_intrmask |= SK_Y2_INTRS1; 2080 else 2081 sc->sk_intrmask |= SK_Y2_INTRS2; 2082 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2083 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2084 2085 ifp->if_flags |= IFF_RUNNING; 2086 ifp->if_flags &= ~IFF_OACTIVE; 2087 2088 callout_schedule(&sc_if->sk_tick_ch, hz); 2089 2090 splx(s); 2091 return 0; 2092 } 2093 2094 void 2095 msk_stop(struct ifnet *ifp, int disable) 2096 { 2097 struct sk_if_softc *sc_if = ifp->if_softc; 2098 struct sk_softc *sc = sc_if->sk_softc; 2099 struct sk_txmap_entry *dma; 2100 int i; 2101 2102 DPRINTFN(2, ("msk_stop\n")); 2103 2104 callout_stop(&sc_if->sk_tick_ch); 2105 2106 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2107 2108 /* Stop transfer of Tx descriptors */ 2109 2110 /* Stop transfer of Rx descriptors */ 2111 2112 /* Turn off various components of this interface. */ 2113 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2114 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2115 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2116 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2117 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2118 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2119 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2120 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2121 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2122 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2123 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2124 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2125 2126 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2127 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2128 2129 /* Disable interrupts */ 2130 if (sc_if->sk_port == SK_PORT_A) 2131 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2132 else 2133 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2134 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2135 2136 SK_XM_READ_2(sc_if, XM_ISR); 2137 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2138 2139 /* Free RX and TX mbufs still in the queues. */ 2140 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2141 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2142 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2143 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2144 } 2145 } 2146 2147 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2148 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2149 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2150 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2151 #if 1 2152 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2153 sc_if->sk_cdata.sk_tx_map[i], link); 2154 sc_if->sk_cdata.sk_tx_map[i] = 0; 2155 #endif 2156 } 2157 } 2158 2159 #if 1 2160 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2161 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2162 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2163 free(dma, M_DEVBUF); 2164 } 2165 #endif 2166 } 2167 2168 CFATTACH_DECL(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2169 NULL, NULL); 2170 2171 CFATTACH_DECL(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2172 NULL, NULL); 2173 2174 #ifdef MSK_DEBUG 2175 void 2176 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2177 { 2178 #define DESC_PRINT(X) \ 2179 if (X) \ 2180 printf("txdesc[%d]." #X "=%#x\n", \ 2181 idx, X); 2182 2183 DESC_PRINT(letoh32(le->sk_addr)); 2184 DESC_PRINT(letoh16(le->sk_len)); 2185 DESC_PRINT(le->sk_ctl); 2186 DESC_PRINT(le->sk_opcode); 2187 #undef DESC_PRINT 2188 } 2189 2190 void 2191 msk_dump_bytes(const char *data, int len) 2192 { 2193 int c, i, j; 2194 2195 for (i = 0; i < len; i += 16) { 2196 printf("%08x ", i); 2197 c = len - i; 2198 if (c > 16) c = 16; 2199 2200 for (j = 0; j < c; j++) { 2201 printf("%02x ", data[i + j] & 0xff); 2202 if ((j & 0xf) == 7 && j > 0) 2203 printf(" "); 2204 } 2205 2206 for (; j < 16; j++) 2207 printf(" "); 2208 printf(" "); 2209 2210 for (j = 0; j < c; j++) { 2211 int ch = data[i + j] & 0xff; 2212 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2213 } 2214 2215 printf("\n"); 2216 2217 if (c < 16) 2218 break; 2219 } 2220 } 2221 2222 void 2223 msk_dump_mbuf(struct mbuf *m) 2224 { 2225 int count = m->m_pkthdr.len; 2226 2227 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2228 2229 while (count > 0 && m) { 2230 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2231 m, m->m_data, m->m_len); 2232 msk_dump_bytes(mtod(m, char *), m->m_len); 2233 2234 count -= m->m_len; 2235 m = m->m_next; 2236 } 2237 } 2238 #endif 2239 2240 static int 2241 msk_sysctl_handler(SYSCTLFN_ARGS) 2242 { 2243 int error, t; 2244 struct sysctlnode node; 2245 struct sk_softc *sc; 2246 2247 node = *rnode; 2248 sc = node.sysctl_data; 2249 t = sc->sk_int_mod; 2250 node.sysctl_data = &t; 2251 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2252 if (error || newp == NULL) 2253 return error; 2254 2255 if (t < SK_IM_MIN || t > SK_IM_MAX) 2256 return EINVAL; 2257 2258 /* update the softc with sysctl-changed value, and mark 2259 for hardware update */ 2260 sc->sk_int_mod = t; 2261 sc->sk_int_mod_pending = 1; 2262 return 0; 2263 } 2264 2265 /* 2266 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2267 * set up in skc_attach() 2268 */ 2269 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2270 { 2271 int rc; 2272 const struct sysctlnode *node; 2273 2274 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2275 0, CTLTYPE_NODE, "hw", NULL, 2276 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2277 goto err; 2278 } 2279 2280 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2281 0, CTLTYPE_NODE, "msk", 2282 SYSCTL_DESCR("msk interface controls"), 2283 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2284 goto err; 2285 } 2286 2287 msk_root_num = node->sysctl_num; 2288 return; 2289 2290 err: 2291 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2292 } 2293
Indexes created Thu Oct 02 10:09:58 GMT 2025