if_msk.c revision 1.35.2.1
1 /* $NetBSD: if_msk.c,v 1.35.2.1 2011/06/06 09:08:14 jruoho Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.35.2.1 2011/06/06 09:08:14 jruoho Exp $"); 56 57 #include "rnd.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/sockio.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/mutex.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/device.h> 68 #include <sys/queue.h> 69 #include <sys/callout.h> 70 #include <sys/sysctl.h> 71 #include <sys/endian.h> 72 #ifdef __NetBSD__ 73 #define letoh16 htole16 74 #define letoh32 htole32 75 #endif 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 81 #include <net/if_media.h> 82 83 #include <net/bpf.h> 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/brgphyreg.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 96 #include <dev/pci/if_skreg.h> 97 #include <dev/pci/if_mskvar.h> 98 99 int mskc_probe(device_t, cfdata_t, void *); 100 void mskc_attach(device_t, device_t, void *); 101 static bool mskc_suspend(device_t, const pmf_qual_t *); 102 static bool mskc_resume(device_t, const pmf_qual_t *); 103 int msk_probe(device_t, cfdata_t, void *); 104 void msk_attach(device_t, device_t, void *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *, int); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 void msk_reset(struct sk_softc *); 118 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 119 int msk_alloc_jumbo_mem(struct sk_if_softc *); 120 void *msk_jalloc(struct sk_if_softc *); 121 void msk_jfree(struct mbuf *, void *, size_t, void *); 122 int msk_init_rx_ring(struct sk_if_softc *); 123 int msk_init_tx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(device_t); 130 131 void msk_setfilt(struct sk_if_softc *, void *, int); 132 void msk_setmulti(struct sk_if_softc *); 133 void msk_setpromisc(struct sk_if_softc *); 134 void msk_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n,x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 /* supported device vendors */ 154 static const struct msk_product { 155 pci_vendor_id_t msk_vendor; 156 pci_product_id_t msk_product; 157 } msk_products[] = { 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 185 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 186 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 187 }; 188 189 static inline u_int32_t 190 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 191 { 192 return CSR_READ_4(sc, reg); 193 } 194 195 static inline u_int16_t 196 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 197 { 198 return CSR_READ_2(sc, reg); 199 } 200 201 static inline u_int8_t 202 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 203 { 204 return CSR_READ_1(sc, reg); 205 } 206 207 static inline void 208 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 209 { 210 CSR_WRITE_4(sc, reg, x); 211 } 212 213 static inline void 214 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 215 { 216 CSR_WRITE_2(sc, reg, x); 217 } 218 219 static inline void 220 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 221 { 222 CSR_WRITE_1(sc, reg, x); 223 } 224 225 int 226 msk_miibus_readreg(device_t dev, int phy, int reg) 227 { 228 struct sk_if_softc *sc_if = device_private(dev); 229 u_int16_t val; 230 int i; 231 232 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 233 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 234 235 for (i = 0; i < SK_TIMEOUT; i++) { 236 DELAY(1); 237 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 238 if (val & YU_SMICR_READ_VALID) 239 break; 240 } 241 242 if (i == SK_TIMEOUT) { 243 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 244 return (0); 245 } 246 247 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 248 SK_TIMEOUT)); 249 250 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 251 252 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 253 phy, reg, val)); 254 255 return (val); 256 } 257 258 void 259 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 260 { 261 struct sk_if_softc *sc_if = device_private(dev); 262 int i; 263 264 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 265 phy, reg, val)); 266 267 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 268 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 269 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 270 271 for (i = 0; i < SK_TIMEOUT; i++) { 272 DELAY(1); 273 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 274 break; 275 } 276 277 if (i == SK_TIMEOUT) 278 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 279 } 280 281 void 282 msk_miibus_statchg(device_t dev) 283 { 284 struct sk_if_softc *sc_if = device_private(dev); 285 struct mii_data *mii = &sc_if->sk_mii; 286 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 287 int gpcr; 288 289 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 290 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 291 292 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 293 /* Set speed. */ 294 gpcr |= YU_GPCR_SPEED_DIS; 295 switch (IFM_SUBTYPE(mii->mii_media_active)) { 296 case IFM_1000_SX: 297 case IFM_1000_LX: 298 case IFM_1000_CX: 299 case IFM_1000_T: 300 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 301 break; 302 case IFM_100_TX: 303 gpcr |= YU_GPCR_SPEED; 304 break; 305 } 306 307 /* Set duplex. */ 308 gpcr |= YU_GPCR_DPLX_DIS; 309 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 310 gpcr |= YU_GPCR_DUPLEX; 311 312 /* Disable flow control. */ 313 gpcr |= YU_GPCR_FCTL_DIS; 314 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 315 } 316 317 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 318 319 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 320 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 321 } 322 323 #define HASH_BITS 6 324 325 void 326 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 327 { 328 char *addr = addrv; 329 int base = XM_RXFILT_ENTRY(slot); 330 331 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 332 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 333 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 334 } 335 336 void 337 msk_setmulti(struct sk_if_softc *sc_if) 338 { 339 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 340 u_int32_t hashes[2] = { 0, 0 }; 341 int h; 342 struct ethercom *ec = &sc_if->sk_ethercom; 343 struct ether_multi *enm; 344 struct ether_multistep step; 345 u_int16_t reg; 346 347 /* First, zot all the existing filters. */ 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 351 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 352 353 354 /* Now program new ones. */ 355 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 356 reg |= YU_RCR_UFLEN; 357 allmulti: 358 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 359 if ((ifp->if_flags & IFF_PROMISC) != 0) 360 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 361 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 362 hashes[0] = 0xFFFFFFFF; 363 hashes[1] = 0xFFFFFFFF; 364 } 365 } else { 366 /* First find the tail of the list. */ 367 ETHER_FIRST_MULTI(step, ec, enm); 368 while (enm != NULL) { 369 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 370 ETHER_ADDR_LEN)) { 371 ifp->if_flags |= IFF_ALLMULTI; 372 goto allmulti; 373 } 374 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 375 ((1 << HASH_BITS) - 1); 376 if (h < 32) 377 hashes[0] |= (1 << h); 378 else 379 hashes[1] |= (1 << (h - 32)); 380 381 ETHER_NEXT_MULTI(step, enm); 382 } 383 reg |= YU_RCR_MUFLEN; 384 } 385 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 390 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 391 } 392 393 void 394 msk_setpromisc(struct sk_if_softc *sc_if) 395 { 396 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 397 398 if (ifp->if_flags & IFF_PROMISC) 399 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 400 YU_RCR_UFLEN | YU_RCR_MUFLEN); 401 else 402 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 403 YU_RCR_UFLEN | YU_RCR_MUFLEN); 404 } 405 406 int 407 msk_init_rx_ring(struct sk_if_softc *sc_if) 408 { 409 struct msk_chain_data *cd = &sc_if->sk_cdata; 410 struct msk_ring_data *rd = sc_if->sk_rdata; 411 int i, nexti; 412 413 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 414 415 for (i = 0; i < MSK_RX_RING_CNT; i++) { 416 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 417 if (i == (MSK_RX_RING_CNT - 1)) 418 nexti = 0; 419 else 420 nexti = i + 1; 421 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 422 } 423 424 for (i = 0; i < MSK_RX_RING_CNT; i++) { 425 if (msk_newbuf(sc_if, i, NULL, 426 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 427 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 428 return (ENOBUFS); 429 } 430 } 431 432 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 433 sc_if->sk_cdata.sk_rx_cons = 0; 434 435 return (0); 436 } 437 438 int 439 msk_init_tx_ring(struct sk_if_softc *sc_if) 440 { 441 struct sk_softc *sc = sc_if->sk_softc; 442 struct msk_chain_data *cd = &sc_if->sk_cdata; 443 struct msk_ring_data *rd = sc_if->sk_rdata; 444 bus_dmamap_t dmamap; 445 struct sk_txmap_entry *entry; 446 int i, nexti; 447 448 memset(sc_if->sk_rdata->sk_tx_ring, 0, 449 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 450 451 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 452 for (i = 0; i < MSK_TX_RING_CNT; i++) { 453 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 454 if (i == (MSK_TX_RING_CNT - 1)) 455 nexti = 0; 456 else 457 nexti = i + 1; 458 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 459 460 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 461 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 462 return (ENOBUFS); 463 464 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 465 if (!entry) { 466 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 467 return (ENOBUFS); 468 } 469 entry->dmamap = dmamap; 470 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 471 } 472 473 sc_if->sk_cdata.sk_tx_prod = 0; 474 sc_if->sk_cdata.sk_tx_cons = 0; 475 sc_if->sk_cdata.sk_tx_cnt = 0; 476 477 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 478 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 479 480 return (0); 481 } 482 483 int 484 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 485 bus_dmamap_t dmamap) 486 { 487 struct mbuf *m_new = NULL; 488 struct sk_chain *c; 489 struct msk_rx_desc *r; 490 491 if (m == NULL) { 492 void *buf = NULL; 493 494 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 495 if (m_new == NULL) 496 return (ENOBUFS); 497 498 /* Allocate the jumbo buffer */ 499 buf = msk_jalloc(sc_if); 500 if (buf == NULL) { 501 m_freem(m_new); 502 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 503 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 504 return (ENOBUFS); 505 } 506 507 /* Attach the buffer to the mbuf */ 508 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 509 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 510 } else { 511 /* 512 * We're re-using a previously allocated mbuf; 513 * be sure to re-init pointers and lengths to 514 * default values. 515 */ 516 m_new = m; 517 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 518 m_new->m_data = m_new->m_ext.ext_buf; 519 } 520 m_adj(m_new, ETHER_ALIGN); 521 522 c = &sc_if->sk_cdata.sk_rx_chain[i]; 523 r = c->sk_le; 524 c->sk_mbuf = m_new; 525 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 526 (((vaddr_t)m_new->m_data 527 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 528 r->sk_len = htole16(SK_JLEN); 529 r->sk_ctl = 0; 530 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 531 532 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 533 534 return (0); 535 } 536 537 /* 538 * Memory management for jumbo frames. 539 */ 540 541 int 542 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 543 { 544 struct sk_softc *sc = sc_if->sk_softc; 545 char *ptr, *kva; 546 bus_dma_segment_t seg; 547 int i, rseg, state, error; 548 struct sk_jpool_entry *entry; 549 550 state = error = 0; 551 552 /* Grab a big chunk o' storage. */ 553 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 554 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 555 aprint_error(": can't alloc rx buffers"); 556 return (ENOBUFS); 557 } 558 559 state = 1; 560 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 561 BUS_DMA_NOWAIT)) { 562 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 563 error = ENOBUFS; 564 goto out; 565 } 566 567 state = 2; 568 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 569 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 570 aprint_error(": can't create dma map"); 571 error = ENOBUFS; 572 goto out; 573 } 574 575 state = 3; 576 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 577 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 578 aprint_error(": can't load dma map"); 579 error = ENOBUFS; 580 goto out; 581 } 582 583 state = 4; 584 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 585 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 586 587 LIST_INIT(&sc_if->sk_jfree_listhead); 588 LIST_INIT(&sc_if->sk_jinuse_listhead); 589 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 590 591 /* 592 * Now divide it up into 9K pieces and save the addresses 593 * in an array. 594 */ 595 ptr = sc_if->sk_cdata.sk_jumbo_buf; 596 for (i = 0; i < MSK_JSLOTS; i++) { 597 sc_if->sk_cdata.sk_jslots[i] = ptr; 598 ptr += SK_JLEN; 599 entry = malloc(sizeof(struct sk_jpool_entry), 600 M_DEVBUF, M_NOWAIT); 601 if (entry == NULL) { 602 sc_if->sk_cdata.sk_jumbo_buf = NULL; 603 aprint_error(": no memory for jumbo buffer queue!"); 604 error = ENOBUFS; 605 goto out; 606 } 607 entry->slot = i; 608 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 609 entry, jpool_entries); 610 } 611 out: 612 if (error != 0) { 613 switch (state) { 614 case 4: 615 bus_dmamap_unload(sc->sc_dmatag, 616 sc_if->sk_cdata.sk_rx_jumbo_map); 617 case 3: 618 bus_dmamap_destroy(sc->sc_dmatag, 619 sc_if->sk_cdata.sk_rx_jumbo_map); 620 case 2: 621 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 622 case 1: 623 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 624 break; 625 default: 626 break; 627 } 628 } 629 630 return (error); 631 } 632 633 /* 634 * Allocate a jumbo buffer. 635 */ 636 void * 637 msk_jalloc(struct sk_if_softc *sc_if) 638 { 639 struct sk_jpool_entry *entry; 640 641 mutex_enter(&sc_if->sk_jpool_mtx); 642 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 643 644 if (entry == NULL) { 645 mutex_exit(&sc_if->sk_jpool_mtx); 646 return NULL; 647 } 648 649 LIST_REMOVE(entry, jpool_entries); 650 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 651 mutex_exit(&sc_if->sk_jpool_mtx); 652 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 void 659 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 660 { 661 struct sk_jpool_entry *entry; 662 struct sk_if_softc *sc; 663 int i; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct sk_if_softc *)arg; 667 668 if (sc == NULL) 669 panic("msk_jfree: can't find softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 i = ((vaddr_t)buf 673 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 674 675 if ((i < 0) || (i >= MSK_JSLOTS)) 676 panic("msk_jfree: asked to free buffer that we don't manage!"); 677 678 mutex_enter(&sc->sk_jpool_mtx); 679 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 680 if (entry == NULL) 681 panic("msk_jfree: buffer not in use!"); 682 entry->slot = i; 683 LIST_REMOVE(entry, jpool_entries); 684 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 685 mutex_exit(&sc->sk_jpool_mtx); 686 687 if (__predict_true(m != NULL)) 688 pool_cache_put(mb_cache, m); 689 } 690 691 int 692 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 693 { 694 struct sk_if_softc *sc_if = ifp->if_softc; 695 int s, error = 0; 696 697 s = splnet(); 698 699 DPRINTFN(2, ("msk_ioctl ETHER\n")); 700 error = ether_ioctl(ifp, cmd, data); 701 702 if (error == ENETRESET) { 703 error = 0; 704 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 705 ; 706 else if (ifp->if_flags & IFF_RUNNING) { 707 /* 708 * Multicast list has changed; set the hardware 709 * filter accordingly. 710 */ 711 msk_setmulti(sc_if); 712 } 713 } 714 715 splx(s); 716 return (error); 717 } 718 719 void 720 msk_update_int_mod(struct sk_softc *sc, int verbose) 721 { 722 u_int32_t imtimer_ticks; 723 724 /* 725 * Configure interrupt moderation. The moderation timer 726 * defers interrupts specified in the interrupt moderation 727 * timer mask based on the timeout specified in the interrupt 728 * moderation timer init register. Each bit in the timer 729 * register represents one tick, so to specify a timeout in 730 * microseconds, we have to multiply by the correct number of 731 * ticks-per-microsecond. 732 */ 733 switch (sc->sk_type) { 734 case SK_YUKON_EC: 735 case SK_YUKON_EC_U: 736 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 737 break; 738 case SK_YUKON_FE: 739 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 740 break; 741 case SK_YUKON_XL: 742 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 743 break; 744 default: 745 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 746 } 747 if (verbose) 748 aprint_verbose_dev(sc->sk_dev, 749 "interrupt moderation is %d us\n", sc->sk_int_mod); 750 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 751 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 752 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 753 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 754 sc->sk_int_mod_pending = 0; 755 } 756 757 static int 758 msk_lookup(const struct pci_attach_args *pa) 759 { 760 const struct msk_product *pmsk; 761 762 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 763 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 764 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 765 return 1; 766 } 767 return 0; 768 } 769 770 /* 771 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 772 * IDs against our list and return a device name if we find a match. 773 */ 774 int 775 mskc_probe(device_t parent, cfdata_t match, void *aux) 776 { 777 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 778 779 return msk_lookup(pa); 780 } 781 782 /* 783 * Force the GEnesis into reset, then bring it out of reset. 784 */ 785 void msk_reset(struct sk_softc *sc) 786 { 787 u_int32_t imtimer_ticks, reg1; 788 int reg; 789 790 DPRINTFN(2, ("msk_reset\n")); 791 792 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 793 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 794 795 DELAY(1000); 796 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 797 DELAY(2); 798 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 799 sk_win_write_1(sc, SK_TESTCTL1, 2); 800 801 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 802 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 803 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 804 else 805 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 806 807 if (sc->sk_type == SK_YUKON_EC_U) { 808 uint32_t our; 809 810 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 811 812 /* enable all clocks. */ 813 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 814 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 815 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 816 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 817 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 818 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 819 /* Set all bits to 0 except bits 15..12 */ 820 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 821 /* Set to default value */ 822 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 823 } 824 825 /* release PHY from PowerDown/Coma mode. */ 826 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 827 828 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 829 sk_win_write_1(sc, SK_Y2_CLKGATE, 830 SK_Y2_CLKGATE_LINK1_GATE_DIS | 831 SK_Y2_CLKGATE_LINK2_GATE_DIS | 832 SK_Y2_CLKGATE_LINK1_CORE_DIS | 833 SK_Y2_CLKGATE_LINK2_CORE_DIS | 834 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 835 else 836 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 837 838 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 839 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 840 DELAY(1000); 841 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 842 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 843 844 sk_win_write_1(sc, SK_TESTCTL1, 1); 845 846 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 847 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 848 CSR_READ_2(sc, SK_LINK_CTRL))); 849 850 /* Disable ASF */ 851 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 852 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 853 854 /* Clear I2C IRQ noise */ 855 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 856 857 /* Disable hardware timer */ 858 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 859 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 860 861 /* Disable descriptor polling */ 862 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 863 864 /* Disable time stamps */ 865 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 866 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 867 868 /* Enable RAM interface */ 869 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 870 for (reg = SK_TO0;reg <= SK_TO11; reg++) 871 sk_win_write_1(sc, reg, 36); 872 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 873 for (reg = SK_TO0;reg <= SK_TO11; reg++) 874 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 875 876 /* 877 * Configure interrupt moderation. The moderation timer 878 * defers interrupts specified in the interrupt moderation 879 * timer mask based on the timeout specified in the interrupt 880 * moderation timer init register. Each bit in the timer 881 * register represents one tick, so to specify a timeout in 882 * microseconds, we have to multiply by the correct number of 883 * ticks-per-microsecond. 884 */ 885 switch (sc->sk_type) { 886 case SK_YUKON_EC: 887 case SK_YUKON_EC_U: 888 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 889 break; 890 case SK_YUKON_FE: 891 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 892 break; 893 case SK_YUKON_XL: 894 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 895 break; 896 default: 897 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 898 } 899 900 /* Reset status ring. */ 901 memset(sc->sk_status_ring, 0, 902 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 903 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 904 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 905 sc->sk_status_idx = 0; 906 sc->sk_status_own_idx = 0; 907 908 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 909 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 910 911 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 912 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 913 sc->sk_status_map->dm_segs[0].ds_addr); 914 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 915 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 916 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 917 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 918 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 919 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 920 } else { 921 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 922 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 923 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 924 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 925 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 926 } 927 928 #if 0 929 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 930 #endif 931 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 932 933 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 934 935 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 936 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 937 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 938 939 msk_update_int_mod(sc, 0); 940 } 941 942 int 943 msk_probe(device_t parent, cfdata_t match, void *aux) 944 { 945 struct skc_attach_args *sa = aux; 946 947 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 948 return (0); 949 950 switch (sa->skc_type) { 951 case SK_YUKON_XL: 952 case SK_YUKON_EC_U: 953 case SK_YUKON_EC: 954 case SK_YUKON_FE: 955 return (1); 956 } 957 958 return (0); 959 } 960 961 static bool 962 msk_resume(device_t dv, const pmf_qual_t *qual) 963 { 964 struct sk_if_softc *sc_if = device_private(dv); 965 966 msk_init_yukon(sc_if); 967 return true; 968 } 969 970 /* 971 * Each XMAC chip is attached as a separate logical IP interface. 972 * Single port cards will have only one logical interface of course. 973 */ 974 void 975 msk_attach(device_t parent, device_t self, void *aux) 976 { 977 struct sk_if_softc *sc_if = device_private(self); 978 struct sk_softc *sc = device_private(parent); 979 struct skc_attach_args *sa = aux; 980 struct ifnet *ifp; 981 void *kva; 982 bus_dma_segment_t seg; 983 int i, rseg; 984 u_int32_t chunk, val; 985 986 sc_if->sk_dev = self; 987 sc_if->sk_port = sa->skc_port; 988 sc_if->sk_softc = sc; 989 sc->sk_if[sa->skc_port] = sc_if; 990 991 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 992 993 /* 994 * Get station address for this interface. Note that 995 * dual port cards actually come with three station 996 * addresses: one for each port, plus an extra. The 997 * extra one is used by the SysKonnect driver software 998 * as a 'virtual' station address for when both ports 999 * are operating in failover mode. Currently we don't 1000 * use this extra address. 1001 */ 1002 for (i = 0; i < ETHER_ADDR_LEN; i++) 1003 sc_if->sk_enaddr[i] = 1004 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1005 1006 aprint_normal(": Ethernet address %s\n", 1007 ether_sprintf(sc_if->sk_enaddr)); 1008 1009 /* 1010 * Set up RAM buffer addresses. The NIC will have a certain 1011 * amount of SRAM on it, somewhere between 512K and 2MB. We 1012 * need to divide this up a) between the transmitter and 1013 * receiver and b) between the two XMACs, if this is a 1014 * dual port NIC. Our algorithm is to divide up the memory 1015 * evenly so that everyone gets a fair share. 1016 * 1017 * Just to be contrary, Yukon2 appears to have separate memory 1018 * for each MAC. 1019 */ 1020 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1021 val = sc->sk_rboff / sizeof(u_int64_t); 1022 sc_if->sk_rx_ramstart = val; 1023 val += (chunk / sizeof(u_int64_t)); 1024 sc_if->sk_rx_ramend = val - 1; 1025 chunk = sc->sk_ramsize - chunk; 1026 sc_if->sk_tx_ramstart = val; 1027 val += (chunk / sizeof(u_int64_t)); 1028 sc_if->sk_tx_ramend = val - 1; 1029 1030 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1031 " tx_ramstart=%#x tx_ramend=%#x\n", 1032 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1033 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1034 1035 /* Allocate the descriptor queues. */ 1036 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1037 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1038 aprint_error(": can't alloc rx buffers\n"); 1039 goto fail; 1040 } 1041 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1042 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1043 aprint_error(": can't map dma buffers (%zu bytes)\n", 1044 sizeof(struct msk_ring_data)); 1045 goto fail_1; 1046 } 1047 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1048 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1049 &sc_if->sk_ring_map)) { 1050 aprint_error(": can't create dma map\n"); 1051 goto fail_2; 1052 } 1053 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1054 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1055 aprint_error(": can't load dma map\n"); 1056 goto fail_3; 1057 } 1058 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1059 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1060 1061 ifp = &sc_if->sk_ethercom.ec_if; 1062 /* Try to allocate memory for jumbo buffers. */ 1063 if (msk_alloc_jumbo_mem(sc_if)) { 1064 aprint_error(": jumbo buffer allocation failed\n"); 1065 goto fail_3; 1066 } 1067 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1068 if (sc->sk_type != SK_YUKON_FE) 1069 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1070 1071 ifp->if_softc = sc_if; 1072 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1073 ifp->if_ioctl = msk_ioctl; 1074 ifp->if_start = msk_start; 1075 ifp->if_stop = msk_stop; 1076 ifp->if_init = msk_init; 1077 ifp->if_watchdog = msk_watchdog; 1078 ifp->if_baudrate = 1000000000; 1079 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1080 IFQ_SET_READY(&ifp->if_snd); 1081 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1082 1083 /* 1084 * Do miibus setup. 1085 */ 1086 msk_init_yukon(sc_if); 1087 1088 DPRINTFN(2, ("msk_attach: 1\n")); 1089 1090 sc_if->sk_mii.mii_ifp = ifp; 1091 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1092 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1093 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1094 1095 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1096 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1097 ether_mediachange, ether_mediastatus); 1098 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1099 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1100 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1101 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1102 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1103 0, NULL); 1104 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1105 } else 1106 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1107 1108 callout_init(&sc_if->sk_tick_ch, 0); 1109 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1110 callout_schedule(&sc_if->sk_tick_ch, hz); 1111 1112 /* 1113 * Call MI attach routines. 1114 */ 1115 if_attach(ifp); 1116 ether_ifattach(ifp, sc_if->sk_enaddr); 1117 1118 if (pmf_device_register(self, NULL, msk_resume)) 1119 pmf_class_network_register(self, ifp); 1120 else 1121 aprint_error_dev(self, "couldn't establish power handler\n"); 1122 1123 #if NRND > 0 1124 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1125 RND_TYPE_NET, 0); 1126 #endif 1127 1128 DPRINTFN(2, ("msk_attach: end\n")); 1129 return; 1130 1131 fail_3: 1132 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1133 fail_2: 1134 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1135 fail_1: 1136 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1137 fail: 1138 sc->sk_if[sa->skc_port] = NULL; 1139 } 1140 1141 int 1142 mskcprint(void *aux, const char *pnp) 1143 { 1144 struct skc_attach_args *sa = aux; 1145 1146 if (pnp) 1147 aprint_normal("sk port %c at %s", 1148 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1149 else 1150 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1151 return (UNCONF); 1152 } 1153 1154 /* 1155 * Attach the interface. Allocate softc structures, do ifmedia 1156 * setup and ethernet/BPF attach. 1157 */ 1158 void 1159 mskc_attach(device_t parent, device_t self, void *aux) 1160 { 1161 struct sk_softc *sc = device_private(self); 1162 struct pci_attach_args *pa = aux; 1163 struct skc_attach_args skca; 1164 pci_chipset_tag_t pc = pa->pa_pc; 1165 pcireg_t command, memtype; 1166 pci_intr_handle_t ih; 1167 const char *intrstr = NULL; 1168 bus_size_t size; 1169 int rc, sk_nodenum; 1170 u_int8_t hw, skrs; 1171 const char *revstr = NULL; 1172 const struct sysctlnode *node; 1173 void *kva; 1174 bus_dma_segment_t seg; 1175 int rseg; 1176 1177 DPRINTFN(2, ("begin mskc_attach\n")); 1178 1179 sc->sk_dev = self; 1180 /* 1181 * Handle power management nonsense. 1182 */ 1183 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1184 1185 if (command == 0x01) { 1186 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1187 if (command & SK_PSTATE_MASK) { 1188 u_int32_t iobase, membase, irq; 1189 1190 /* Save important PCI config data. */ 1191 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1192 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1193 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1194 1195 /* Reset the power state. */ 1196 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1197 "mode -- setting to D0\n", 1198 command & SK_PSTATE_MASK); 1199 command &= 0xFFFFFFFC; 1200 pci_conf_write(pc, pa->pa_tag, 1201 SK_PCI_PWRMGMTCTRL, command); 1202 1203 /* Restore PCI config data. */ 1204 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1205 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1206 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1207 } 1208 } 1209 1210 /* 1211 * Map control/status registers. 1212 */ 1213 1214 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1215 switch (memtype) { 1216 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1217 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1218 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1219 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1220 NULL, &size) == 0) { 1221 break; 1222 } 1223 default: 1224 aprint_error(": can't map mem space\n"); 1225 return; 1226 } 1227 1228 sc->sc_dmatag = pa->pa_dmat; 1229 1230 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1231 command |= PCI_COMMAND_MASTER_ENABLE; 1232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1233 1234 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1235 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1236 1237 /* bail out here if chip is not recognized */ 1238 if (!(SK_IS_YUKON2(sc))) { 1239 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1240 goto fail_1; 1241 } 1242 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1243 1244 /* Allocate interrupt */ 1245 if (pci_intr_map(pa, &ih)) { 1246 aprint_error(": couldn't map interrupt\n"); 1247 goto fail_1; 1248 } 1249 1250 intrstr = pci_intr_string(pc, ih); 1251 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1252 if (sc->sk_intrhand == NULL) { 1253 aprint_error(": couldn't establish interrupt"); 1254 if (intrstr != NULL) 1255 aprint_error(" at %s", intrstr); 1256 aprint_error("\n"); 1257 goto fail_1; 1258 } 1259 1260 if (bus_dmamem_alloc(sc->sc_dmatag, 1261 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1262 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1263 aprint_error(": can't alloc status buffers\n"); 1264 goto fail_2; 1265 } 1266 1267 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1268 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1269 &kva, BUS_DMA_NOWAIT)) { 1270 aprint_error(": can't map dma buffers (%zu bytes)\n", 1271 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1272 goto fail_3; 1273 } 1274 if (bus_dmamap_create(sc->sc_dmatag, 1275 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1276 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1277 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1278 aprint_error(": can't create dma map\n"); 1279 goto fail_4; 1280 } 1281 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1282 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1283 NULL, BUS_DMA_NOWAIT)) { 1284 aprint_error(": can't load dma map\n"); 1285 goto fail_5; 1286 } 1287 sc->sk_status_ring = (struct msk_status_desc *)kva; 1288 1289 1290 sc->sk_int_mod = SK_IM_DEFAULT; 1291 sc->sk_int_mod_pending = 0; 1292 1293 /* Reset the adapter. */ 1294 msk_reset(sc); 1295 1296 skrs = sk_win_read_1(sc, SK_EPROM0); 1297 if (skrs == 0x00) 1298 sc->sk_ramsize = 0x20000; 1299 else 1300 sc->sk_ramsize = skrs * (1<<12); 1301 sc->sk_rboff = SK_RBOFF_0; 1302 1303 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1304 sc->sk_ramsize, sc->sk_ramsize / 1024, 1305 sc->sk_rboff)); 1306 1307 switch (sc->sk_type) { 1308 case SK_YUKON_XL: 1309 sc->sk_name = "Yukon-2 XL"; 1310 break; 1311 case SK_YUKON_EC_U: 1312 sc->sk_name = "Yukon-2 EC Ultra"; 1313 break; 1314 case SK_YUKON_EC: 1315 sc->sk_name = "Yukon-2 EC"; 1316 break; 1317 case SK_YUKON_FE: 1318 sc->sk_name = "Yukon-2 FE"; 1319 break; 1320 default: 1321 sc->sk_name = "Yukon (Unknown)"; 1322 } 1323 1324 if (sc->sk_type == SK_YUKON_XL) { 1325 switch (sc->sk_rev) { 1326 case SK_YUKON_XL_REV_A0: 1327 sc->sk_workaround = 0; 1328 revstr = "A0"; 1329 break; 1330 case SK_YUKON_XL_REV_A1: 1331 sc->sk_workaround = SK_WA_4109; 1332 revstr = "A1"; 1333 break; 1334 case SK_YUKON_XL_REV_A2: 1335 sc->sk_workaround = SK_WA_4109; 1336 revstr = "A2"; 1337 break; 1338 case SK_YUKON_XL_REV_A3: 1339 sc->sk_workaround = SK_WA_4109; 1340 revstr = "A3"; 1341 break; 1342 default: 1343 sc->sk_workaround = 0; 1344 break; 1345 } 1346 } 1347 1348 if (sc->sk_type == SK_YUKON_EC) { 1349 switch (sc->sk_rev) { 1350 case SK_YUKON_EC_REV_A1: 1351 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1352 revstr = "A1"; 1353 break; 1354 case SK_YUKON_EC_REV_A2: 1355 sc->sk_workaround = SK_WA_4109; 1356 revstr = "A2"; 1357 break; 1358 case SK_YUKON_EC_REV_A3: 1359 sc->sk_workaround = SK_WA_4109; 1360 revstr = "A3"; 1361 break; 1362 default: 1363 sc->sk_workaround = 0; 1364 break; 1365 } 1366 } 1367 1368 if (sc->sk_type == SK_YUKON_FE) { 1369 sc->sk_workaround = SK_WA_4109; 1370 switch (sc->sk_rev) { 1371 case SK_YUKON_FE_REV_A1: 1372 revstr = "A1"; 1373 break; 1374 case SK_YUKON_FE_REV_A2: 1375 revstr = "A2"; 1376 break; 1377 default: 1378 sc->sk_workaround = 0; 1379 break; 1380 } 1381 } 1382 1383 if (sc->sk_type == SK_YUKON_EC_U) { 1384 sc->sk_workaround = SK_WA_4109; 1385 switch (sc->sk_rev) { 1386 case SK_YUKON_EC_U_REV_A0: 1387 revstr = "A0"; 1388 break; 1389 case SK_YUKON_EC_U_REV_A1: 1390 revstr = "A1"; 1391 break; 1392 case SK_YUKON_EC_U_REV_B0: 1393 revstr = "B0"; 1394 break; 1395 default: 1396 sc->sk_workaround = 0; 1397 break; 1398 } 1399 } 1400 1401 /* Announce the product name. */ 1402 aprint_normal(", %s", sc->sk_name); 1403 if (revstr != NULL) 1404 aprint_normal(" rev. %s", revstr); 1405 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1406 1407 sc->sk_macs = 1; 1408 1409 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1410 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1411 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1412 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1413 sc->sk_macs++; 1414 } 1415 1416 skca.skc_port = SK_PORT_A; 1417 skca.skc_type = sc->sk_type; 1418 skca.skc_rev = sc->sk_rev; 1419 (void)config_found(sc->sk_dev, &skca, mskcprint); 1420 1421 if (sc->sk_macs > 1) { 1422 skca.skc_port = SK_PORT_B; 1423 skca.skc_type = sc->sk_type; 1424 skca.skc_rev = sc->sk_rev; 1425 (void)config_found(sc->sk_dev, &skca, mskcprint); 1426 } 1427 1428 /* Turn on the 'driver is loaded' LED. */ 1429 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1430 1431 /* skc sysctl setup */ 1432 1433 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1434 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1435 SYSCTL_DESCR("mskc per-controller controls"), 1436 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1437 CTL_EOL)) != 0) { 1438 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1439 goto fail_6; 1440 } 1441 1442 sk_nodenum = node->sysctl_num; 1443 1444 /* interrupt moderation time in usecs */ 1445 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1446 CTLFLAG_READWRITE, 1447 CTLTYPE_INT, "int_mod", 1448 SYSCTL_DESCR("msk interrupt moderation timer"), 1449 msk_sysctl_handler, 0, sc, 1450 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1451 CTL_EOL)) != 0) { 1452 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1453 goto fail_6; 1454 } 1455 1456 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1457 aprint_error_dev(self, "couldn't establish power handler\n"); 1458 1459 return; 1460 1461 fail_6: 1462 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1463 fail_5: 1464 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1465 fail_4: 1466 bus_dmamem_unmap(sc->sc_dmatag, kva, 1467 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1468 fail_3: 1469 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1470 fail_2: 1471 pci_intr_disestablish(pc, sc->sk_intrhand); 1472 fail_1: 1473 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1474 } 1475 1476 int 1477 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1478 { 1479 struct sk_softc *sc = sc_if->sk_softc; 1480 struct msk_tx_desc *f = NULL; 1481 u_int32_t frag, cur; 1482 int i; 1483 struct sk_txmap_entry *entry; 1484 bus_dmamap_t txmap; 1485 1486 DPRINTFN(2, ("msk_encap\n")); 1487 1488 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1489 if (entry == NULL) { 1490 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1491 return (ENOBUFS); 1492 } 1493 txmap = entry->dmamap; 1494 1495 cur = frag = *txidx; 1496 1497 #ifdef MSK_DEBUG 1498 if (mskdebug >= 2) 1499 msk_dump_mbuf(m_head); 1500 #endif 1501 1502 /* 1503 * Start packing the mbufs in this chain into 1504 * the fragment pointers. Stop when we run out 1505 * of fragments or hit the end of the mbuf chain. 1506 */ 1507 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1508 BUS_DMA_NOWAIT)) { 1509 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1510 return (ENOBUFS); 1511 } 1512 1513 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1514 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1515 bus_dmamap_unload(sc->sc_dmatag, txmap); 1516 return (ENOBUFS); 1517 } 1518 1519 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1520 1521 /* Sync the DMA map. */ 1522 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1523 BUS_DMASYNC_PREWRITE); 1524 1525 for (i = 0; i < txmap->dm_nsegs; i++) { 1526 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1527 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1528 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1529 f->sk_ctl = 0; 1530 if (i == 0) 1531 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1532 else 1533 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1534 cur = frag; 1535 SK_INC(frag, MSK_TX_RING_CNT); 1536 } 1537 1538 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1539 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1540 1541 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1542 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1543 1544 /* Sync descriptors before handing to chip */ 1545 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1546 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1547 1548 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1549 1550 /* Sync first descriptor to hand it off */ 1551 MSK_CDTXSYNC(sc_if, *txidx, 1, 1552 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1553 1554 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1555 1556 #ifdef MSK_DEBUG 1557 if (mskdebug >= 2) { 1558 struct msk_tx_desc *le; 1559 u_int32_t idx; 1560 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1561 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1562 msk_dump_txdesc(le, idx); 1563 } 1564 } 1565 #endif 1566 1567 *txidx = frag; 1568 1569 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1570 1571 return (0); 1572 } 1573 1574 void 1575 msk_start(struct ifnet *ifp) 1576 { 1577 struct sk_if_softc *sc_if = ifp->if_softc; 1578 struct mbuf *m_head = NULL; 1579 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1580 int pkts = 0; 1581 1582 DPRINTFN(2, ("msk_start\n")); 1583 1584 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1585 IFQ_POLL(&ifp->if_snd, m_head); 1586 if (m_head == NULL) 1587 break; 1588 1589 /* 1590 * Pack the data into the transmit ring. If we 1591 * don't have room, set the OACTIVE flag and wait 1592 * for the NIC to drain the ring. 1593 */ 1594 if (msk_encap(sc_if, m_head, &idx)) { 1595 ifp->if_flags |= IFF_OACTIVE; 1596 break; 1597 } 1598 1599 /* now we are committed to transmit the packet */ 1600 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1601 pkts++; 1602 1603 /* 1604 * If there's a BPF listener, bounce a copy of this frame 1605 * to him. 1606 */ 1607 bpf_mtap(ifp, m_head); 1608 } 1609 if (pkts == 0) 1610 return; 1611 1612 /* Transmit */ 1613 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1614 sc_if->sk_cdata.sk_tx_prod = idx; 1615 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1616 1617 /* Set a timeout in case the chip goes out to lunch. */ 1618 ifp->if_timer = 5; 1619 } 1620 } 1621 1622 void 1623 msk_watchdog(struct ifnet *ifp) 1624 { 1625 struct sk_if_softc *sc_if = ifp->if_softc; 1626 u_int32_t reg; 1627 int idx; 1628 1629 /* 1630 * Reclaim first as there is a possibility of losing Tx completion 1631 * interrupts. 1632 */ 1633 if (sc_if->sk_port == SK_PORT_A) 1634 reg = SK_STAT_BMU_TXA1_RIDX; 1635 else 1636 reg = SK_STAT_BMU_TXA2_RIDX; 1637 1638 idx = sk_win_read_2(sc_if->sk_softc, reg); 1639 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1640 msk_txeof(sc_if, idx); 1641 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1642 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1643 1644 ifp->if_oerrors++; 1645 1646 /* XXX Resets both ports; we shouldn't do that. */ 1647 msk_reset(sc_if->sk_softc); 1648 msk_init(ifp); 1649 } 1650 } 1651 } 1652 1653 static bool 1654 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1655 { 1656 struct sk_softc *sc = device_private(dv); 1657 1658 DPRINTFN(2, ("mskc_suspend\n")); 1659 1660 /* Turn off the 'driver is loaded' LED. */ 1661 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1662 1663 return true; 1664 } 1665 1666 static bool 1667 mskc_resume(device_t dv, const pmf_qual_t *qual) 1668 { 1669 struct sk_softc *sc = device_private(dv); 1670 1671 DPRINTFN(2, ("mskc_resume\n")); 1672 1673 msk_reset(sc); 1674 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1675 1676 return true; 1677 } 1678 1679 static __inline int 1680 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1681 { 1682 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1683 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1684 YU_RXSTAT_JABBER)) != 0 || 1685 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1686 YU_RXSTAT_BYTES(stat) != len) 1687 return (0); 1688 1689 return (1); 1690 } 1691 1692 void 1693 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1694 { 1695 struct sk_softc *sc = sc_if->sk_softc; 1696 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1697 struct mbuf *m; 1698 struct sk_chain *cur_rx; 1699 int cur, total_len = len; 1700 bus_dmamap_t dmamap; 1701 1702 DPRINTFN(2, ("msk_rxeof\n")); 1703 1704 cur = sc_if->sk_cdata.sk_rx_cons; 1705 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1706 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1707 1708 /* Sync the descriptor */ 1709 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1710 1711 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1712 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1713 1714 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1715 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1716 1717 m = cur_rx->sk_mbuf; 1718 cur_rx->sk_mbuf = NULL; 1719 1720 if (total_len < SK_MIN_FRAMELEN || 1721 total_len > ETHER_MAX_LEN_JUMBO || 1722 msk_rxvalid(sc, rxstat, total_len) == 0) { 1723 ifp->if_ierrors++; 1724 msk_newbuf(sc_if, cur, m, dmamap); 1725 return; 1726 } 1727 1728 /* 1729 * Try to allocate a new jumbo buffer. If that fails, copy the 1730 * packet to mbufs and put the jumbo buffer back in the ring 1731 * so it can be re-used. If allocating mbufs fails, then we 1732 * have to drop the packet. 1733 */ 1734 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1735 struct mbuf *m0; 1736 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1737 total_len + ETHER_ALIGN, 0, ifp, NULL); 1738 msk_newbuf(sc_if, cur, m, dmamap); 1739 if (m0 == NULL) { 1740 ifp->if_ierrors++; 1741 return; 1742 } 1743 m_adj(m0, ETHER_ALIGN); 1744 m = m0; 1745 } else { 1746 m->m_pkthdr.rcvif = ifp; 1747 m->m_pkthdr.len = m->m_len = total_len; 1748 } 1749 1750 ifp->if_ipackets++; 1751 1752 bpf_mtap(ifp, m); 1753 1754 /* pass it on. */ 1755 (*ifp->if_input)(ifp, m); 1756 } 1757 1758 void 1759 msk_txeof(struct sk_if_softc *sc_if, int idx) 1760 { 1761 struct sk_softc *sc = sc_if->sk_softc; 1762 struct msk_tx_desc *cur_tx; 1763 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1764 u_int32_t sk_ctl; 1765 struct sk_txmap_entry *entry; 1766 int cons, prog; 1767 1768 DPRINTFN(2, ("msk_txeof\n")); 1769 1770 /* 1771 * Go through our tx ring and free mbufs for those 1772 * frames that have been sent. 1773 */ 1774 cons = sc_if->sk_cdata.sk_tx_cons; 1775 prog = 0; 1776 while (cons != idx) { 1777 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1778 break; 1779 prog++; 1780 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1781 1782 MSK_CDTXSYNC(sc_if, cons, 1, 1783 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1784 sk_ctl = cur_tx->sk_ctl; 1785 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1786 #ifdef MSK_DEBUG 1787 if (mskdebug >= 2) 1788 msk_dump_txdesc(cur_tx, cons); 1789 #endif 1790 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1791 ifp->if_opackets++; 1792 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1793 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1794 1795 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1796 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1797 1798 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1799 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1800 link); 1801 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1802 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1803 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1804 } 1805 sc_if->sk_cdata.sk_tx_cnt--; 1806 SK_INC(cons, MSK_TX_RING_CNT); 1807 } 1808 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1809 1810 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1811 ifp->if_flags &= ~IFF_OACTIVE; 1812 1813 if (prog > 0) 1814 sc_if->sk_cdata.sk_tx_cons = cons; 1815 } 1816 1817 void 1818 msk_tick(void *xsc_if) 1819 { 1820 struct sk_if_softc *sc_if = xsc_if; 1821 struct mii_data *mii = &sc_if->sk_mii; 1822 uint16_t gpsr; 1823 int s; 1824 1825 s = splnet(); 1826 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); 1827 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { 1828 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); 1829 mii_tick(mii); 1830 } 1831 splx(s); 1832 1833 callout_schedule(&sc_if->sk_tick_ch, hz); 1834 } 1835 1836 void 1837 msk_intr_yukon(struct sk_if_softc *sc_if) 1838 { 1839 u_int8_t status; 1840 1841 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1842 /* RX overrun */ 1843 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1844 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1845 SK_RFCTL_RX_FIFO_OVER); 1846 } 1847 /* TX underrun */ 1848 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1849 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1850 SK_TFCTL_TX_FIFO_UNDER); 1851 } 1852 1853 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1854 } 1855 1856 int 1857 msk_intr(void *xsc) 1858 { 1859 struct sk_softc *sc = xsc; 1860 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1861 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1862 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1863 int claimed = 0; 1864 u_int32_t status; 1865 uint32_t st_status; 1866 uint16_t st_len; 1867 uint8_t st_opcode, st_link; 1868 struct msk_status_desc *cur_st; 1869 1870 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1871 if (status == 0) { 1872 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1873 return (0); 1874 } 1875 1876 status = CSR_READ_4(sc, SK_ISR); 1877 1878 if (sc_if0 != NULL) 1879 ifp0 = &sc_if0->sk_ethercom.ec_if; 1880 if (sc_if1 != NULL) 1881 ifp1 = &sc_if1->sk_ethercom.ec_if; 1882 1883 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1884 (ifp0->if_flags & IFF_RUNNING)) { 1885 msk_intr_yukon(sc_if0); 1886 } 1887 1888 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1889 (ifp1->if_flags & IFF_RUNNING)) { 1890 msk_intr_yukon(sc_if1); 1891 } 1892 1893 for (;;) { 1894 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1895 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1896 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1897 st_opcode = cur_st->sk_opcode; 1898 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1899 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1900 BUS_DMASYNC_PREREAD); 1901 break; 1902 } 1903 st_status = le32toh(cur_st->sk_status); 1904 st_len = le16toh(cur_st->sk_len); 1905 st_link = cur_st->sk_link; 1906 st_opcode &= ~SK_Y2_STOPC_OWN; 1907 1908 switch (st_opcode) { 1909 case SK_Y2_STOPC_RXSTAT: 1910 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1911 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1912 SK_RXQ1_Y2_PREF_PUTIDX, 1913 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1914 break; 1915 case SK_Y2_STOPC_TXSTAT: 1916 if (sc_if0) 1917 msk_txeof(sc_if0, st_status 1918 & SK_Y2_ST_TXA1_MSKL); 1919 if (sc_if1) 1920 msk_txeof(sc_if1, 1921 ((st_status & SK_Y2_ST_TXA2_MSKL) 1922 >> SK_Y2_ST_TXA2_SHIFTL) 1923 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1924 break; 1925 default: 1926 aprint_error("opcode=0x%x\n", st_opcode); 1927 break; 1928 } 1929 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1930 } 1931 1932 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1933 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1934 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1935 1936 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1937 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1938 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1939 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1940 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1941 1942 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1943 } 1944 1945 if (status & SK_Y2_IMR_BMU) { 1946 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1947 claimed = 1; 1948 } 1949 1950 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1951 1952 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1953 msk_start(ifp0); 1954 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1955 msk_start(ifp1); 1956 1957 #if NRND > 0 1958 if (RND_ENABLED(&sc->rnd_source)) 1959 rnd_add_uint32(&sc->rnd_source, status); 1960 #endif 1961 1962 if (sc->sk_int_mod_pending) 1963 msk_update_int_mod(sc, 1); 1964 1965 return claimed; 1966 } 1967 1968 void 1969 msk_init_yukon(struct sk_if_softc *sc_if) 1970 { 1971 u_int32_t v; 1972 u_int16_t reg; 1973 struct sk_softc *sc; 1974 int i; 1975 1976 sc = sc_if->sk_softc; 1977 1978 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1979 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1980 1981 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1982 1983 /* GMAC and GPHY Reset */ 1984 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1985 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1986 DELAY(1000); 1987 1988 DPRINTFN(6, ("msk_init_yukon: 2\n")); 1989 1990 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1991 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1992 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1993 1994 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 1995 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 1996 1997 DPRINTFN(6, ("msk_init_yukon: 3\n")); 1998 1999 /* unused read of the interrupt source register */ 2000 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2001 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2002 2003 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2004 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2005 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2006 2007 /* MIB Counter Clear Mode set */ 2008 reg |= YU_PAR_MIB_CLR; 2009 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2010 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2011 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2012 2013 /* MIB Counter Clear Mode clear */ 2014 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2015 reg &= ~YU_PAR_MIB_CLR; 2016 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2017 2018 /* receive control reg */ 2019 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2020 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2021 2022 /* transmit control register */ 2023 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2024 2025 /* transmit flow control register */ 2026 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2027 2028 /* transmit parameter register */ 2029 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2030 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2031 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2032 2033 /* serial mode register */ 2034 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2035 reg = YU_SMR_DATA_BLIND(0x1c) | 2036 YU_SMR_MFL_VLAN | 2037 YU_SMR_IPG_DATA(0x1e); 2038 2039 if (sc->sk_type != SK_YUKON_FE) 2040 reg |= YU_SMR_MFL_JUMBO; 2041 2042 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2043 2044 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2045 /* Setup Yukon's address */ 2046 for (i = 0; i < 3; i++) { 2047 /* Write Source Address 1 (unicast filter) */ 2048 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2049 sc_if->sk_enaddr[i * 2] | 2050 sc_if->sk_enaddr[i * 2 + 1] << 8); 2051 } 2052 2053 for (i = 0; i < 3; i++) { 2054 reg = sk_win_read_2(sc_if->sk_softc, 2055 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2056 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2057 } 2058 2059 /* Set promiscuous mode */ 2060 msk_setpromisc(sc_if); 2061 2062 /* Set multicast filter */ 2063 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2064 msk_setmulti(sc_if); 2065 2066 /* enable interrupt mask for counter overflows */ 2067 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2068 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2069 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2070 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2071 2072 /* Configure RX MAC FIFO Flush Mask */ 2073 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2074 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2075 YU_RXSTAT_JABBER; 2076 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2077 2078 /* Configure RX MAC FIFO */ 2079 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2080 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2081 SK_RFCTL_FIFO_FLUSH_ON); 2082 2083 /* Increase flush threshould to 64 bytes */ 2084 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2085 SK_RFCTL_FIFO_THRESHOLD + 1); 2086 2087 /* Configure TX MAC FIFO */ 2088 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2089 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2090 2091 #if 1 2092 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2093 #endif 2094 DPRINTFN(6, ("msk_init_yukon: end\n")); 2095 } 2096 2097 /* 2098 * Note that to properly initialize any part of the GEnesis chip, 2099 * you first have to take it out of reset mode. 2100 */ 2101 int 2102 msk_init(struct ifnet *ifp) 2103 { 2104 struct sk_if_softc *sc_if = ifp->if_softc; 2105 struct sk_softc *sc = sc_if->sk_softc; 2106 int rc = 0, s; 2107 uint32_t imr, imtimer_ticks; 2108 2109 2110 DPRINTFN(2, ("msk_init\n")); 2111 2112 s = splnet(); 2113 2114 /* Cancel pending I/O and free all RX/TX buffers. */ 2115 msk_stop(ifp,0); 2116 2117 /* Configure I2C registers */ 2118 2119 /* Configure XMAC(s) */ 2120 msk_init_yukon(sc_if); 2121 if ((rc = ether_mediachange(ifp)) != 0) 2122 goto out; 2123 2124 /* Configure transmit arbiter(s) */ 2125 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2126 #if 0 2127 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2128 #endif 2129 2130 /* Configure RAMbuffers */ 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2132 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2133 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2134 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2135 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2136 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2137 2138 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2139 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2140 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2141 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2142 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2143 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2144 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2145 2146 /* Configure BMUs */ 2147 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2148 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2149 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2150 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2151 2152 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2153 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2154 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2155 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2156 2157 /* Make sure the sync transmit queue is disabled. */ 2158 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2159 2160 /* Init descriptors */ 2161 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2162 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2163 "memory for rx buffers\n"); 2164 msk_stop(ifp,0); 2165 splx(s); 2166 return ENOBUFS; 2167 } 2168 2169 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2170 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2171 "memory for tx buffers\n"); 2172 msk_stop(ifp,0); 2173 splx(s); 2174 return ENOBUFS; 2175 } 2176 2177 /* Set interrupt moderation if changed via sysctl. */ 2178 switch (sc->sk_type) { 2179 case SK_YUKON_EC: 2180 case SK_YUKON_EC_U: 2181 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2182 break; 2183 case SK_YUKON_FE: 2184 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2185 break; 2186 case SK_YUKON_XL: 2187 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2188 break; 2189 default: 2190 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2191 } 2192 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2193 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2194 sk_win_write_4(sc, SK_IMTIMERINIT, 2195 SK_IM_USECS(sc->sk_int_mod)); 2196 aprint_verbose_dev(sc->sk_dev, 2197 "interrupt moderation is %d us\n", sc->sk_int_mod); 2198 } 2199 2200 /* Initialize prefetch engine. */ 2201 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2202 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2203 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2204 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2205 MSK_RX_RING_ADDR(sc_if, 0)); 2206 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2207 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2208 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2209 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2210 2211 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2212 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2213 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2214 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2215 MSK_TX_RING_ADDR(sc_if, 0)); 2216 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2217 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2218 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2219 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2220 2221 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2222 sc_if->sk_cdata.sk_rx_prod); 2223 2224 /* Configure interrupt handling */ 2225 if (sc_if->sk_port == SK_PORT_A) 2226 sc->sk_intrmask |= SK_Y2_INTRS1; 2227 else 2228 sc->sk_intrmask |= SK_Y2_INTRS2; 2229 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2230 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2231 2232 ifp->if_flags |= IFF_RUNNING; 2233 ifp->if_flags &= ~IFF_OACTIVE; 2234 2235 callout_schedule(&sc_if->sk_tick_ch, hz); 2236 2237 out: 2238 splx(s); 2239 return rc; 2240 } 2241 2242 void 2243 msk_stop(struct ifnet *ifp, int disable) 2244 { 2245 struct sk_if_softc *sc_if = ifp->if_softc; 2246 struct sk_softc *sc = sc_if->sk_softc; 2247 struct sk_txmap_entry *dma; 2248 int i; 2249 2250 DPRINTFN(2, ("msk_stop\n")); 2251 2252 callout_stop(&sc_if->sk_tick_ch); 2253 2254 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2255 2256 /* Stop transfer of Tx descriptors */ 2257 2258 /* Stop transfer of Rx descriptors */ 2259 2260 /* Turn off various components of this interface. */ 2261 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2262 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2263 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2264 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2265 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2266 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2267 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2268 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2269 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2270 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2271 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2272 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2273 2274 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2275 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2276 2277 /* Disable interrupts */ 2278 if (sc_if->sk_port == SK_PORT_A) 2279 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2280 else 2281 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2282 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2283 2284 SK_XM_READ_2(sc_if, XM_ISR); 2285 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2286 2287 /* Free RX and TX mbufs still in the queues. */ 2288 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2289 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2290 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2291 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2292 } 2293 } 2294 2295 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2296 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2297 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2298 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2299 #if 1 2300 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2301 sc_if->sk_cdata.sk_tx_map[i], link); 2302 sc_if->sk_cdata.sk_tx_map[i] = 0; 2303 #endif 2304 } 2305 } 2306 2307 #if 1 2308 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2309 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2310 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2311 free(dma, M_DEVBUF); 2312 } 2313 #endif 2314 } 2315 2316 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2317 NULL, NULL); 2318 2319 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2320 NULL, NULL); 2321 2322 #ifdef MSK_DEBUG 2323 void 2324 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2325 { 2326 #define DESC_PRINT(X) \ 2327 if (X) \ 2328 printf("txdesc[%d]." #X "=%#x\n", \ 2329 idx, X); 2330 2331 DESC_PRINT(letoh32(le->sk_addr)); 2332 DESC_PRINT(letoh16(le->sk_len)); 2333 DESC_PRINT(le->sk_ctl); 2334 DESC_PRINT(le->sk_opcode); 2335 #undef DESC_PRINT 2336 } 2337 2338 void 2339 msk_dump_bytes(const char *data, int len) 2340 { 2341 int c, i, j; 2342 2343 for (i = 0; i < len; i += 16) { 2344 printf("%08x ", i); 2345 c = len - i; 2346 if (c > 16) c = 16; 2347 2348 for (j = 0; j < c; j++) { 2349 printf("%02x ", data[i + j] & 0xff); 2350 if ((j & 0xf) == 7 && j > 0) 2351 printf(" "); 2352 } 2353 2354 for (; j < 16; j++) 2355 printf(" "); 2356 printf(" "); 2357 2358 for (j = 0; j < c; j++) { 2359 int ch = data[i + j] & 0xff; 2360 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2361 } 2362 2363 printf("\n"); 2364 2365 if (c < 16) 2366 break; 2367 } 2368 } 2369 2370 void 2371 msk_dump_mbuf(struct mbuf *m) 2372 { 2373 int count = m->m_pkthdr.len; 2374 2375 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2376 2377 while (count > 0 && m) { 2378 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2379 m, m->m_data, m->m_len); 2380 msk_dump_bytes(mtod(m, char *), m->m_len); 2381 2382 count -= m->m_len; 2383 m = m->m_next; 2384 } 2385 } 2386 #endif 2387 2388 static int 2389 msk_sysctl_handler(SYSCTLFN_ARGS) 2390 { 2391 int error, t; 2392 struct sysctlnode node; 2393 struct sk_softc *sc; 2394 2395 node = *rnode; 2396 sc = node.sysctl_data; 2397 t = sc->sk_int_mod; 2398 node.sysctl_data = &t; 2399 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2400 if (error || newp == NULL) 2401 return error; 2402 2403 if (t < SK_IM_MIN || t > SK_IM_MAX) 2404 return EINVAL; 2405 2406 /* update the softc with sysctl-changed value, and mark 2407 for hardware update */ 2408 sc->sk_int_mod = t; 2409 sc->sk_int_mod_pending = 1; 2410 return 0; 2411 } 2412 2413 /* 2414 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2415 * set up in skc_attach() 2416 */ 2417 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2418 { 2419 int rc; 2420 const struct sysctlnode *node; 2421 2422 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2423 0, CTLTYPE_NODE, "hw", NULL, 2424 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2425 goto err; 2426 } 2427 2428 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2429 0, CTLTYPE_NODE, "msk", 2430 SYSCTL_DESCR("msk interface controls"), 2431 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2432 goto err; 2433 } 2434 2435 msk_root_num = node->sysctl_num; 2436 return; 2437 2438 err: 2439 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2440 } 2441
Indexes created Thu Oct 02 07:10:07 GMT 2025