if_msk.c revision 1.51.2.1
1 /* $NetBSD: if_msk.c,v 1.51.2.1 2017/01/07 08:56:33 pgoyette Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.51.2.1 2017/01/07 08:56:33 pgoyette Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 static bool mskc_suspend(device_t, const pmf_qual_t *); 98 static bool mskc_resume(device_t, const pmf_qual_t *); 99 int msk_probe(device_t, cfdata_t, void *); 100 void msk_attach(device_t, device_t, void *); 101 int mskcprint(void *, const char *); 102 int msk_intr(void *); 103 void msk_intr_yukon(struct sk_if_softc *); 104 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 105 void msk_txeof(struct sk_if_softc *, int); 106 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 107 void msk_start(struct ifnet *); 108 int msk_ioctl(struct ifnet *, u_long, void *); 109 int msk_init(struct ifnet *); 110 void msk_init_yukon(struct sk_if_softc *); 111 void msk_stop(struct ifnet *, int); 112 void msk_watchdog(struct ifnet *); 113 void msk_reset(struct sk_softc *); 114 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 115 int msk_alloc_jumbo_mem(struct sk_if_softc *); 116 void *msk_jalloc(struct sk_if_softc *); 117 void msk_jfree(struct mbuf *, void *, size_t, void *); 118 int msk_init_rx_ring(struct sk_if_softc *); 119 int msk_init_tx_ring(struct sk_if_softc *); 120 121 void msk_update_int_mod(struct sk_softc *, int); 122 123 int msk_miibus_readreg(device_t, int, int); 124 void msk_miibus_writereg(device_t, int, int, int); 125 void msk_miibus_statchg(struct ifnet *); 126 127 void msk_setfilt(struct sk_if_softc *, void *, int); 128 void msk_setmulti(struct sk_if_softc *); 129 void msk_setpromisc(struct sk_if_softc *); 130 void msk_tick(void *); 131 132 /* #define MSK_DEBUG 1 */ 133 #ifdef MSK_DEBUG 134 #define DPRINTF(x) if (mskdebug) printf x 135 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 136 int mskdebug = MSK_DEBUG; 137 138 void msk_dump_txdesc(struct msk_tx_desc *, int); 139 void msk_dump_mbuf(struct mbuf *); 140 void msk_dump_bytes(const char *, int); 141 #else 142 #define DPRINTF(x) 143 #define DPRINTFN(n,x) 144 #endif 145 146 static int msk_sysctl_handler(SYSCTLFN_PROTO); 147 static int msk_root_num; 148 149 /* supported device vendors */ 150 static const struct msk_product { 151 pci_vendor_id_t msk_vendor; 152 pci_product_id_t msk_product; 153 } msk_products[] = { 154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 157 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 }, 158 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 159 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 182 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 183 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 184 }; 185 186 static inline u_int32_t 187 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 188 { 189 return CSR_READ_4(sc, reg); 190 } 191 192 static inline u_int16_t 193 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 194 { 195 return CSR_READ_2(sc, reg); 196 } 197 198 static inline u_int8_t 199 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 200 { 201 return CSR_READ_1(sc, reg); 202 } 203 204 static inline void 205 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 206 { 207 CSR_WRITE_4(sc, reg, x); 208 } 209 210 static inline void 211 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 212 { 213 CSR_WRITE_2(sc, reg, x); 214 } 215 216 static inline void 217 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 218 { 219 CSR_WRITE_1(sc, reg, x); 220 } 221 222 int 223 msk_miibus_readreg(device_t dev, int phy, int reg) 224 { 225 struct sk_if_softc *sc_if = device_private(dev); 226 u_int16_t val; 227 int i; 228 229 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 230 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 231 232 for (i = 0; i < SK_TIMEOUT; i++) { 233 DELAY(1); 234 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 235 if (val & YU_SMICR_READ_VALID) 236 break; 237 } 238 239 if (i == SK_TIMEOUT) { 240 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 241 return (0); 242 } 243 244 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 245 SK_TIMEOUT)); 246 247 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 248 249 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 250 phy, reg, val)); 251 252 return (val); 253 } 254 255 void 256 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 257 { 258 struct sk_if_softc *sc_if = device_private(dev); 259 int i; 260 261 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 262 phy, reg, val)); 263 264 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 265 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 266 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 267 268 for (i = 0; i < SK_TIMEOUT; i++) { 269 DELAY(1); 270 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 271 break; 272 } 273 274 if (i == SK_TIMEOUT) 275 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 276 } 277 278 void 279 msk_miibus_statchg(struct ifnet *ifp) 280 { 281 struct sk_if_softc *sc_if = ifp->if_softc; 282 struct mii_data *mii = &sc_if->sk_mii; 283 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 284 int gpcr; 285 286 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 287 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 288 289 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 290 /* Set speed. */ 291 gpcr |= YU_GPCR_SPEED_DIS; 292 switch (IFM_SUBTYPE(mii->mii_media_active)) { 293 case IFM_1000_SX: 294 case IFM_1000_LX: 295 case IFM_1000_CX: 296 case IFM_1000_T: 297 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 298 break; 299 case IFM_100_TX: 300 gpcr |= YU_GPCR_SPEED; 301 break; 302 } 303 304 /* Set duplex. */ 305 gpcr |= YU_GPCR_DPLX_DIS; 306 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 307 gpcr |= YU_GPCR_DUPLEX; 308 309 /* Disable flow control. */ 310 gpcr |= YU_GPCR_FCTL_DIS; 311 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 312 } 313 314 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 315 316 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 317 SK_YU_READ_2(sc_if, YUKON_GPCR))); 318 } 319 320 #define HASH_BITS 6 321 322 void 323 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 324 { 325 char *addr = addrv; 326 int base = XM_RXFILT_ENTRY(slot); 327 328 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 329 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 330 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 331 } 332 333 void 334 msk_setmulti(struct sk_if_softc *sc_if) 335 { 336 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 337 u_int32_t hashes[2] = { 0, 0 }; 338 int h; 339 struct ethercom *ec = &sc_if->sk_ethercom; 340 struct ether_multi *enm; 341 struct ether_multistep step; 342 u_int16_t reg; 343 344 /* First, zot all the existing filters. */ 345 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 346 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 347 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 349 350 351 /* Now program new ones. */ 352 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 353 reg |= YU_RCR_UFLEN; 354 allmulti: 355 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 356 if ((ifp->if_flags & IFF_PROMISC) != 0) 357 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 358 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 359 hashes[0] = 0xFFFFFFFF; 360 hashes[1] = 0xFFFFFFFF; 361 } 362 } else { 363 /* First find the tail of the list. */ 364 ETHER_FIRST_MULTI(step, ec, enm); 365 while (enm != NULL) { 366 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 367 ETHER_ADDR_LEN)) { 368 ifp->if_flags |= IFF_ALLMULTI; 369 goto allmulti; 370 } 371 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 372 ((1 << HASH_BITS) - 1); 373 if (h < 32) 374 hashes[0] |= (1 << h); 375 else 376 hashes[1] |= (1 << (h - 32)); 377 378 ETHER_NEXT_MULTI(step, enm); 379 } 380 reg |= YU_RCR_MUFLEN; 381 } 382 383 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 384 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 385 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 388 } 389 390 void 391 msk_setpromisc(struct sk_if_softc *sc_if) 392 { 393 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 394 395 if (ifp->if_flags & IFF_PROMISC) 396 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 397 YU_RCR_UFLEN | YU_RCR_MUFLEN); 398 else 399 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 400 YU_RCR_UFLEN | YU_RCR_MUFLEN); 401 } 402 403 int 404 msk_init_rx_ring(struct sk_if_softc *sc_if) 405 { 406 struct msk_chain_data *cd = &sc_if->sk_cdata; 407 struct msk_ring_data *rd = sc_if->sk_rdata; 408 int i, nexti; 409 410 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 411 412 for (i = 0; i < MSK_RX_RING_CNT; i++) { 413 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 414 if (i == (MSK_RX_RING_CNT - 1)) 415 nexti = 0; 416 else 417 nexti = i + 1; 418 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 419 } 420 421 for (i = 0; i < MSK_RX_RING_CNT; i++) { 422 if (msk_newbuf(sc_if, i, NULL, 423 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 424 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 425 return (ENOBUFS); 426 } 427 } 428 429 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 430 sc_if->sk_cdata.sk_rx_cons = 0; 431 432 return (0); 433 } 434 435 int 436 msk_init_tx_ring(struct sk_if_softc *sc_if) 437 { 438 struct sk_softc *sc = sc_if->sk_softc; 439 struct msk_chain_data *cd = &sc_if->sk_cdata; 440 struct msk_ring_data *rd = sc_if->sk_rdata; 441 bus_dmamap_t dmamap; 442 struct sk_txmap_entry *entry; 443 int i, nexti; 444 445 memset(sc_if->sk_rdata->sk_tx_ring, 0, 446 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 447 448 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 449 for (i = 0; i < MSK_TX_RING_CNT; i++) { 450 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 451 if (i == (MSK_TX_RING_CNT - 1)) 452 nexti = 0; 453 else 454 nexti = i + 1; 455 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 456 457 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 458 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 459 return (ENOBUFS); 460 461 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 462 if (!entry) { 463 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 464 return (ENOBUFS); 465 } 466 entry->dmamap = dmamap; 467 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 468 } 469 470 sc_if->sk_cdata.sk_tx_prod = 0; 471 sc_if->sk_cdata.sk_tx_cons = 0; 472 sc_if->sk_cdata.sk_tx_cnt = 0; 473 474 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 475 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 476 477 return (0); 478 } 479 480 int 481 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 482 bus_dmamap_t dmamap) 483 { 484 struct mbuf *m_new = NULL; 485 struct sk_chain *c; 486 struct msk_rx_desc *r; 487 488 if (m == NULL) { 489 void *buf = NULL; 490 491 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 492 if (m_new == NULL) 493 return (ENOBUFS); 494 495 /* Allocate the jumbo buffer */ 496 buf = msk_jalloc(sc_if); 497 if (buf == NULL) { 498 m_freem(m_new); 499 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 500 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 501 return (ENOBUFS); 502 } 503 504 /* Attach the buffer to the mbuf */ 505 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 506 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 507 } else { 508 /* 509 * We're re-using a previously allocated mbuf; 510 * be sure to re-init pointers and lengths to 511 * default values. 512 */ 513 m_new = m; 514 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 515 m_new->m_data = m_new->m_ext.ext_buf; 516 } 517 m_adj(m_new, ETHER_ALIGN); 518 519 c = &sc_if->sk_cdata.sk_rx_chain[i]; 520 r = c->sk_le; 521 c->sk_mbuf = m_new; 522 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 523 (((vaddr_t)m_new->m_data 524 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 525 r->sk_len = htole16(SK_JLEN); 526 r->sk_ctl = 0; 527 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 528 529 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 530 531 return (0); 532 } 533 534 /* 535 * Memory management for jumbo frames. 536 */ 537 538 int 539 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 540 { 541 struct sk_softc *sc = sc_if->sk_softc; 542 char *ptr, *kva; 543 bus_dma_segment_t seg; 544 int i, rseg, state, error; 545 struct sk_jpool_entry *entry; 546 547 state = error = 0; 548 549 /* Grab a big chunk o' storage. */ 550 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 551 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 552 aprint_error(": can't alloc rx buffers"); 553 return (ENOBUFS); 554 } 555 556 state = 1; 557 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 558 BUS_DMA_NOWAIT)) { 559 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 560 error = ENOBUFS; 561 goto out; 562 } 563 564 state = 2; 565 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 566 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 567 aprint_error(": can't create dma map"); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 3; 573 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 574 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 575 aprint_error(": can't load dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 4; 581 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 582 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 583 584 LIST_INIT(&sc_if->sk_jfree_listhead); 585 LIST_INIT(&sc_if->sk_jinuse_listhead); 586 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 587 588 /* 589 * Now divide it up into 9K pieces and save the addresses 590 * in an array. 591 */ 592 ptr = sc_if->sk_cdata.sk_jumbo_buf; 593 for (i = 0; i < MSK_JSLOTS; i++) { 594 sc_if->sk_cdata.sk_jslots[i] = ptr; 595 ptr += SK_JLEN; 596 entry = malloc(sizeof(struct sk_jpool_entry), 597 M_DEVBUF, M_NOWAIT); 598 if (entry == NULL) { 599 sc_if->sk_cdata.sk_jumbo_buf = NULL; 600 aprint_error(": no memory for jumbo buffer queue!"); 601 error = ENOBUFS; 602 goto out; 603 } 604 entry->slot = i; 605 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 606 entry, jpool_entries); 607 } 608 out: 609 if (error != 0) { 610 switch (state) { 611 case 4: 612 bus_dmamap_unload(sc->sc_dmatag, 613 sc_if->sk_cdata.sk_rx_jumbo_map); 614 case 3: 615 bus_dmamap_destroy(sc->sc_dmatag, 616 sc_if->sk_cdata.sk_rx_jumbo_map); 617 case 2: 618 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 619 case 1: 620 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 621 break; 622 default: 623 break; 624 } 625 } 626 627 return error; 628 } 629 630 /* 631 * Allocate a jumbo buffer. 632 */ 633 void * 634 msk_jalloc(struct sk_if_softc *sc_if) 635 { 636 struct sk_jpool_entry *entry; 637 638 mutex_enter(&sc_if->sk_jpool_mtx); 639 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 640 641 if (entry == NULL) { 642 mutex_exit(&sc_if->sk_jpool_mtx); 643 return NULL; 644 } 645 646 LIST_REMOVE(entry, jpool_entries); 647 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 648 mutex_exit(&sc_if->sk_jpool_mtx); 649 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 650 } 651 652 /* 653 * Release a jumbo buffer. 654 */ 655 void 656 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 657 { 658 struct sk_jpool_entry *entry; 659 struct sk_if_softc *sc; 660 int i; 661 662 /* Extract the softc struct pointer. */ 663 sc = (struct sk_if_softc *)arg; 664 665 if (sc == NULL) 666 panic("msk_jfree: can't find softc pointer!"); 667 668 /* calculate the slot this buffer belongs to */ 669 i = ((vaddr_t)buf 670 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 671 672 if ((i < 0) || (i >= MSK_JSLOTS)) 673 panic("msk_jfree: asked to free buffer that we don't manage!"); 674 675 mutex_enter(&sc->sk_jpool_mtx); 676 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 677 if (entry == NULL) 678 panic("msk_jfree: buffer not in use!"); 679 entry->slot = i; 680 LIST_REMOVE(entry, jpool_entries); 681 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 682 mutex_exit(&sc->sk_jpool_mtx); 683 684 if (__predict_true(m != NULL)) 685 pool_cache_put(mb_cache, m); 686 } 687 688 int 689 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 690 { 691 struct sk_if_softc *sc = ifp->if_softc; 692 int s, error; 693 694 s = splnet(); 695 696 DPRINTFN(2, ("msk_ioctl ETHER\n")); 697 switch (cmd) { 698 case SIOCSIFFLAGS: 699 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 700 break; 701 702 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 703 case IFF_RUNNING: 704 msk_stop(ifp, 1); 705 break; 706 case IFF_UP: 707 msk_init(ifp); 708 break; 709 case IFF_UP | IFF_RUNNING: 710 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 711 msk_setpromisc(sc); 712 msk_setmulti(sc); 713 } else 714 msk_init(ifp); 715 break; 716 } 717 sc->sk_if_flags = ifp->if_flags; 718 break; 719 default: 720 error = ether_ioctl(ifp, cmd, data); 721 if (error == ENETRESET) { 722 error = 0; 723 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 724 ; 725 else if (ifp->if_flags & IFF_RUNNING) { 726 /* 727 * Multicast list has changed; set the hardware 728 * filter accordingly. 729 */ 730 msk_setmulti(sc); 731 } 732 } 733 break; 734 } 735 736 splx(s); 737 return error; 738 } 739 740 void 741 msk_update_int_mod(struct sk_softc *sc, int verbose) 742 { 743 u_int32_t imtimer_ticks; 744 745 /* 746 * Configure interrupt moderation. The moderation timer 747 * defers interrupts specified in the interrupt moderation 748 * timer mask based on the timeout specified in the interrupt 749 * moderation timer init register. Each bit in the timer 750 * register represents one tick, so to specify a timeout in 751 * microseconds, we have to multiply by the correct number of 752 * ticks-per-microsecond. 753 */ 754 switch (sc->sk_type) { 755 case SK_YUKON_EC: 756 case SK_YUKON_EC_U: 757 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 758 break; 759 case SK_YUKON_FE: 760 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 761 break; 762 case SK_YUKON_XL: 763 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 764 break; 765 default: 766 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 767 } 768 if (verbose) 769 aprint_verbose_dev(sc->sk_dev, 770 "interrupt moderation is %d us\n", sc->sk_int_mod); 771 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 772 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 773 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 774 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 775 sc->sk_int_mod_pending = 0; 776 } 777 778 static int 779 msk_lookup(const struct pci_attach_args *pa) 780 { 781 const struct msk_product *pmsk; 782 783 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 784 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 785 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 786 return 1; 787 } 788 return 0; 789 } 790 791 /* 792 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 793 * IDs against our list and return a device name if we find a match. 794 */ 795 int 796 mskc_probe(device_t parent, cfdata_t match, void *aux) 797 { 798 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 799 800 return msk_lookup(pa); 801 } 802 803 /* 804 * Force the GEnesis into reset, then bring it out of reset. 805 */ 806 void msk_reset(struct sk_softc *sc) 807 { 808 u_int32_t imtimer_ticks, reg1; 809 int reg; 810 811 DPRINTFN(2, ("msk_reset\n")); 812 813 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 814 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 815 816 DELAY(1000); 817 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 818 DELAY(2); 819 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 820 sk_win_write_1(sc, SK_TESTCTL1, 2); 821 822 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 823 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 824 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 825 else 826 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 827 828 if (sc->sk_type == SK_YUKON_EC_U) { 829 uint32_t our; 830 831 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 832 833 /* enable all clocks. */ 834 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 835 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 836 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 837 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 838 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 839 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 840 /* Set all bits to 0 except bits 15..12 */ 841 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 842 /* Set to default value */ 843 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 844 } 845 846 /* release PHY from PowerDown/Coma mode. */ 847 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 848 849 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 850 sk_win_write_1(sc, SK_Y2_CLKGATE, 851 SK_Y2_CLKGATE_LINK1_GATE_DIS | 852 SK_Y2_CLKGATE_LINK2_GATE_DIS | 853 SK_Y2_CLKGATE_LINK1_CORE_DIS | 854 SK_Y2_CLKGATE_LINK2_CORE_DIS | 855 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 856 else 857 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 858 859 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 860 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 861 DELAY(1000); 862 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 863 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 864 865 sk_win_write_1(sc, SK_TESTCTL1, 1); 866 867 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 868 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 869 CSR_READ_2(sc, SK_LINK_CTRL))); 870 871 /* Disable ASF */ 872 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 873 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 874 875 /* Clear I2C IRQ noise */ 876 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 877 878 /* Disable hardware timer */ 879 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 880 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 881 882 /* Disable descriptor polling */ 883 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 884 885 /* Disable time stamps */ 886 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 887 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 888 889 /* Enable RAM interface */ 890 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 891 for (reg = SK_TO0;reg <= SK_TO11; reg++) 892 sk_win_write_1(sc, reg, 36); 893 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 894 for (reg = SK_TO0;reg <= SK_TO11; reg++) 895 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 896 897 /* 898 * Configure interrupt moderation. The moderation timer 899 * defers interrupts specified in the interrupt moderation 900 * timer mask based on the timeout specified in the interrupt 901 * moderation timer init register. Each bit in the timer 902 * register represents one tick, so to specify a timeout in 903 * microseconds, we have to multiply by the correct number of 904 * ticks-per-microsecond. 905 */ 906 switch (sc->sk_type) { 907 case SK_YUKON_EC: 908 case SK_YUKON_EC_U: 909 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 910 break; 911 case SK_YUKON_FE: 912 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 913 break; 914 case SK_YUKON_XL: 915 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 916 break; 917 default: 918 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 919 } 920 921 /* Reset status ring. */ 922 memset(sc->sk_status_ring, 0, 923 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 924 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 925 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 926 sc->sk_status_idx = 0; 927 sc->sk_status_own_idx = 0; 928 929 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 930 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 931 932 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 933 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 934 sc->sk_status_map->dm_segs[0].ds_addr); 935 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 936 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 937 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 938 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 939 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 940 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 941 } else { 942 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 943 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 944 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 945 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 946 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 947 } 948 949 #if 0 950 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 951 #endif 952 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 953 954 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 955 956 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 957 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 958 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 959 960 msk_update_int_mod(sc, 0); 961 } 962 963 int 964 msk_probe(device_t parent, cfdata_t match, void *aux) 965 { 966 struct skc_attach_args *sa = aux; 967 968 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 969 return (0); 970 971 switch (sa->skc_type) { 972 case SK_YUKON_XL: 973 case SK_YUKON_EC_U: 974 case SK_YUKON_EC: 975 case SK_YUKON_FE: 976 case SK_YUKON_FE_P: 977 return (1); 978 } 979 980 return (0); 981 } 982 983 static bool 984 msk_resume(device_t dv, const pmf_qual_t *qual) 985 { 986 struct sk_if_softc *sc_if = device_private(dv); 987 988 msk_init_yukon(sc_if); 989 return true; 990 } 991 992 /* 993 * Each XMAC chip is attached as a separate logical IP interface. 994 * Single port cards will have only one logical interface of course. 995 */ 996 void 997 msk_attach(device_t parent, device_t self, void *aux) 998 { 999 struct sk_if_softc *sc_if = device_private(self); 1000 struct sk_softc *sc = device_private(parent); 1001 struct skc_attach_args *sa = aux; 1002 struct ifnet *ifp; 1003 void *kva; 1004 bus_dma_segment_t seg; 1005 int i, rseg; 1006 u_int32_t chunk, val; 1007 1008 sc_if->sk_dev = self; 1009 sc_if->sk_port = sa->skc_port; 1010 sc_if->sk_softc = sc; 1011 sc->sk_if[sa->skc_port] = sc_if; 1012 1013 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1014 1015 /* 1016 * Get station address for this interface. Note that 1017 * dual port cards actually come with three station 1018 * addresses: one for each port, plus an extra. The 1019 * extra one is used by the SysKonnect driver software 1020 * as a 'virtual' station address for when both ports 1021 * are operating in failover mode. Currently we don't 1022 * use this extra address. 1023 */ 1024 for (i = 0; i < ETHER_ADDR_LEN; i++) 1025 sc_if->sk_enaddr[i] = 1026 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1027 1028 aprint_normal(": Ethernet address %s\n", 1029 ether_sprintf(sc_if->sk_enaddr)); 1030 1031 /* 1032 * Set up RAM buffer addresses. The NIC will have a certain 1033 * amount of SRAM on it, somewhere between 512K and 2MB. We 1034 * need to divide this up a) between the transmitter and 1035 * receiver and b) between the two XMACs, if this is a 1036 * dual port NIC. Our algorithm is to divide up the memory 1037 * evenly so that everyone gets a fair share. 1038 * 1039 * Just to be contrary, Yukon2 appears to have separate memory 1040 * for each MAC. 1041 */ 1042 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3; 1043 val = sc->sk_rboff / sizeof(u_int64_t); 1044 sc_if->sk_rx_ramstart = val; 1045 val += (chunk / sizeof(u_int64_t)); 1046 sc_if->sk_rx_ramend = val - 1; 1047 chunk = sc->sk_ramsize - chunk; 1048 sc_if->sk_tx_ramstart = val; 1049 val += (chunk / sizeof(u_int64_t)); 1050 sc_if->sk_tx_ramend = val - 1; 1051 1052 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1053 " tx_ramstart=%#x tx_ramend=%#x\n", 1054 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1055 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1056 1057 /* Allocate the descriptor queues. */ 1058 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1059 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1060 aprint_error(": can't alloc rx buffers\n"); 1061 goto fail; 1062 } 1063 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1064 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1065 aprint_error(": can't map dma buffers (%zu bytes)\n", 1066 sizeof(struct msk_ring_data)); 1067 goto fail_1; 1068 } 1069 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1070 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1071 &sc_if->sk_ring_map)) { 1072 aprint_error(": can't create dma map\n"); 1073 goto fail_2; 1074 } 1075 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1076 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1077 aprint_error(": can't load dma map\n"); 1078 goto fail_3; 1079 } 1080 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1081 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1082 1083 ifp = &sc_if->sk_ethercom.ec_if; 1084 /* Try to allocate memory for jumbo buffers. */ 1085 if (msk_alloc_jumbo_mem(sc_if)) { 1086 aprint_error(": jumbo buffer allocation failed\n"); 1087 goto fail_3; 1088 } 1089 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1090 if (sc->sk_type != SK_YUKON_FE) 1091 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1092 1093 ifp->if_softc = sc_if; 1094 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1095 ifp->if_ioctl = msk_ioctl; 1096 ifp->if_start = msk_start; 1097 ifp->if_stop = msk_stop; 1098 ifp->if_init = msk_init; 1099 ifp->if_watchdog = msk_watchdog; 1100 ifp->if_baudrate = 1000000000; 1101 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1102 IFQ_SET_READY(&ifp->if_snd); 1103 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1104 1105 /* 1106 * Do miibus setup. 1107 */ 1108 msk_init_yukon(sc_if); 1109 1110 DPRINTFN(2, ("msk_attach: 1\n")); 1111 1112 sc_if->sk_mii.mii_ifp = ifp; 1113 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1114 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1115 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1116 1117 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1118 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1119 ether_mediachange, ether_mediastatus); 1120 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1121 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1122 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1123 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1124 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1125 0, NULL); 1126 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1127 } else 1128 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1129 1130 callout_init(&sc_if->sk_tick_ch, 0); 1131 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1132 callout_schedule(&sc_if->sk_tick_ch, hz); 1133 1134 /* 1135 * Call MI attach routines. 1136 */ 1137 if_attach(ifp); 1138 if_deferred_start_init(ifp, NULL); 1139 ether_ifattach(ifp, sc_if->sk_enaddr); 1140 1141 if (pmf_device_register(self, NULL, msk_resume)) 1142 pmf_class_network_register(self, ifp); 1143 else 1144 aprint_error_dev(self, "couldn't establish power handler\n"); 1145 1146 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1147 RND_TYPE_NET, RND_FLAG_DEFAULT); 1148 1149 DPRINTFN(2, ("msk_attach: end\n")); 1150 return; 1151 1152 fail_3: 1153 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1154 fail_2: 1155 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1156 fail_1: 1157 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1158 fail: 1159 sc->sk_if[sa->skc_port] = NULL; 1160 } 1161 1162 int 1163 mskcprint(void *aux, const char *pnp) 1164 { 1165 struct skc_attach_args *sa = aux; 1166 1167 if (pnp) 1168 aprint_normal("sk port %c at %s", 1169 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1170 else 1171 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1172 return (UNCONF); 1173 } 1174 1175 /* 1176 * Attach the interface. Allocate softc structures, do ifmedia 1177 * setup and ethernet/BPF attach. 1178 */ 1179 void 1180 mskc_attach(device_t parent, device_t self, void *aux) 1181 { 1182 struct sk_softc *sc = device_private(self); 1183 struct pci_attach_args *pa = aux; 1184 struct skc_attach_args skca; 1185 pci_chipset_tag_t pc = pa->pa_pc; 1186 pcireg_t command, memtype; 1187 pci_intr_handle_t ih; 1188 const char *intrstr = NULL; 1189 bus_size_t size; 1190 int rc, sk_nodenum; 1191 u_int8_t hw, skrs; 1192 const char *revstr = NULL; 1193 const struct sysctlnode *node; 1194 void *kva; 1195 bus_dma_segment_t seg; 1196 int rseg; 1197 char intrbuf[PCI_INTRSTR_LEN]; 1198 1199 DPRINTFN(2, ("begin mskc_attach\n")); 1200 1201 sc->sk_dev = self; 1202 /* 1203 * Handle power management nonsense. 1204 */ 1205 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1206 1207 if (command == 0x01) { 1208 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1209 if (command & SK_PSTATE_MASK) { 1210 u_int32_t iobase, membase, irq; 1211 1212 /* Save important PCI config data. */ 1213 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1214 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1215 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1216 1217 /* Reset the power state. */ 1218 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1219 "mode -- setting to D0\n", 1220 command & SK_PSTATE_MASK); 1221 command &= 0xFFFFFFFC; 1222 pci_conf_write(pc, pa->pa_tag, 1223 SK_PCI_PWRMGMTCTRL, command); 1224 1225 /* Restore PCI config data. */ 1226 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1227 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1228 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1229 } 1230 } 1231 1232 /* 1233 * Map control/status registers. 1234 */ 1235 1236 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1237 switch (memtype) { 1238 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1239 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1240 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1241 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1242 NULL, &size) == 0) { 1243 break; 1244 } 1245 default: 1246 aprint_error(": can't map mem space\n"); 1247 return; 1248 } 1249 1250 sc->sc_dmatag = pa->pa_dmat; 1251 1252 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1253 command |= PCI_COMMAND_MASTER_ENABLE; 1254 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1255 1256 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1257 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1258 1259 /* bail out here if chip is not recognized */ 1260 if (!(SK_IS_YUKON2(sc))) { 1261 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1262 goto fail_1; 1263 } 1264 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1265 1266 /* Allocate interrupt */ 1267 if (pci_intr_map(pa, &ih)) { 1268 aprint_error(": couldn't map interrupt\n"); 1269 goto fail_1; 1270 } 1271 1272 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1273 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1274 if (sc->sk_intrhand == NULL) { 1275 aprint_error(": couldn't establish interrupt"); 1276 if (intrstr != NULL) 1277 aprint_error(" at %s", intrstr); 1278 aprint_error("\n"); 1279 goto fail_1; 1280 } 1281 1282 if (bus_dmamem_alloc(sc->sc_dmatag, 1283 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1284 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1285 aprint_error(": can't alloc status buffers\n"); 1286 goto fail_2; 1287 } 1288 1289 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1290 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1291 &kva, BUS_DMA_NOWAIT)) { 1292 aprint_error(": can't map dma buffers (%zu bytes)\n", 1293 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1294 goto fail_3; 1295 } 1296 if (bus_dmamap_create(sc->sc_dmatag, 1297 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1298 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1299 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1300 aprint_error(": can't create dma map\n"); 1301 goto fail_4; 1302 } 1303 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1304 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1305 NULL, BUS_DMA_NOWAIT)) { 1306 aprint_error(": can't load dma map\n"); 1307 goto fail_5; 1308 } 1309 sc->sk_status_ring = (struct msk_status_desc *)kva; 1310 1311 1312 sc->sk_int_mod = SK_IM_DEFAULT; 1313 sc->sk_int_mod_pending = 0; 1314 1315 /* Reset the adapter. */ 1316 msk_reset(sc); 1317 1318 skrs = sk_win_read_1(sc, SK_EPROM0); 1319 if (skrs == 0x00) 1320 sc->sk_ramsize = 0x20000; 1321 else 1322 sc->sk_ramsize = skrs * (1<<12); 1323 sc->sk_rboff = SK_RBOFF_0; 1324 1325 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n", 1326 sc->sk_ramsize, sc->sk_ramsize / 1024, 1327 sc->sk_rboff)); 1328 1329 switch (sc->sk_type) { 1330 case SK_YUKON_XL: 1331 sc->sk_name = "Yukon-2 XL"; 1332 break; 1333 case SK_YUKON_EC_U: 1334 sc->sk_name = "Yukon-2 EC Ultra"; 1335 break; 1336 case SK_YUKON_EC: 1337 sc->sk_name = "Yukon-2 EC"; 1338 break; 1339 case SK_YUKON_FE: 1340 sc->sk_name = "Yukon-2 FE"; 1341 break; 1342 default: 1343 sc->sk_name = "Yukon (Unknown)"; 1344 } 1345 1346 if (sc->sk_type == SK_YUKON_XL) { 1347 switch (sc->sk_rev) { 1348 case SK_YUKON_XL_REV_A0: 1349 sc->sk_workaround = 0; 1350 revstr = "A0"; 1351 break; 1352 case SK_YUKON_XL_REV_A1: 1353 sc->sk_workaround = SK_WA_4109; 1354 revstr = "A1"; 1355 break; 1356 case SK_YUKON_XL_REV_A2: 1357 sc->sk_workaround = SK_WA_4109; 1358 revstr = "A2"; 1359 break; 1360 case SK_YUKON_XL_REV_A3: 1361 sc->sk_workaround = SK_WA_4109; 1362 revstr = "A3"; 1363 break; 1364 default: 1365 sc->sk_workaround = 0; 1366 break; 1367 } 1368 } 1369 1370 if (sc->sk_type == SK_YUKON_EC) { 1371 switch (sc->sk_rev) { 1372 case SK_YUKON_EC_REV_A1: 1373 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1374 revstr = "A1"; 1375 break; 1376 case SK_YUKON_EC_REV_A2: 1377 sc->sk_workaround = SK_WA_4109; 1378 revstr = "A2"; 1379 break; 1380 case SK_YUKON_EC_REV_A3: 1381 sc->sk_workaround = SK_WA_4109; 1382 revstr = "A3"; 1383 break; 1384 default: 1385 sc->sk_workaround = 0; 1386 break; 1387 } 1388 } 1389 1390 if (sc->sk_type == SK_YUKON_FE) { 1391 sc->sk_workaround = SK_WA_4109; 1392 switch (sc->sk_rev) { 1393 case SK_YUKON_FE_REV_A1: 1394 revstr = "A1"; 1395 break; 1396 case SK_YUKON_FE_REV_A2: 1397 revstr = "A2"; 1398 break; 1399 default: 1400 sc->sk_workaround = 0; 1401 break; 1402 } 1403 } 1404 1405 if (sc->sk_type == SK_YUKON_EC_U) { 1406 sc->sk_workaround = SK_WA_4109; 1407 switch (sc->sk_rev) { 1408 case SK_YUKON_EC_U_REV_A0: 1409 revstr = "A0"; 1410 break; 1411 case SK_YUKON_EC_U_REV_A1: 1412 revstr = "A1"; 1413 break; 1414 case SK_YUKON_EC_U_REV_B0: 1415 revstr = "B0"; 1416 break; 1417 default: 1418 sc->sk_workaround = 0; 1419 break; 1420 } 1421 } 1422 1423 /* Announce the product name. */ 1424 aprint_normal(", %s", sc->sk_name); 1425 if (revstr != NULL) 1426 aprint_normal(" rev. %s", revstr); 1427 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1428 1429 sc->sk_macs = 1; 1430 1431 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1432 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1433 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1434 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1435 sc->sk_macs++; 1436 } 1437 1438 skca.skc_port = SK_PORT_A; 1439 skca.skc_type = sc->sk_type; 1440 skca.skc_rev = sc->sk_rev; 1441 (void)config_found(sc->sk_dev, &skca, mskcprint); 1442 1443 if (sc->sk_macs > 1) { 1444 skca.skc_port = SK_PORT_B; 1445 skca.skc_type = sc->sk_type; 1446 skca.skc_rev = sc->sk_rev; 1447 (void)config_found(sc->sk_dev, &skca, mskcprint); 1448 } 1449 1450 /* Turn on the 'driver is loaded' LED. */ 1451 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1452 1453 /* skc sysctl setup */ 1454 1455 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1456 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1457 SYSCTL_DESCR("mskc per-controller controls"), 1458 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1459 CTL_EOL)) != 0) { 1460 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1461 goto fail_6; 1462 } 1463 1464 sk_nodenum = node->sysctl_num; 1465 1466 /* interrupt moderation time in usecs */ 1467 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1468 CTLFLAG_READWRITE, 1469 CTLTYPE_INT, "int_mod", 1470 SYSCTL_DESCR("msk interrupt moderation timer"), 1471 msk_sysctl_handler, 0, (void *)sc, 1472 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1473 CTL_EOL)) != 0) { 1474 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1475 goto fail_6; 1476 } 1477 1478 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1479 aprint_error_dev(self, "couldn't establish power handler\n"); 1480 1481 return; 1482 1483 fail_6: 1484 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1485 fail_5: 1486 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1487 fail_4: 1488 bus_dmamem_unmap(sc->sc_dmatag, kva, 1489 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1490 fail_3: 1491 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1492 fail_2: 1493 pci_intr_disestablish(pc, sc->sk_intrhand); 1494 fail_1: 1495 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1496 } 1497 1498 int 1499 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1500 { 1501 struct sk_softc *sc = sc_if->sk_softc; 1502 struct msk_tx_desc *f = NULL; 1503 u_int32_t frag, cur; 1504 int i; 1505 struct sk_txmap_entry *entry; 1506 bus_dmamap_t txmap; 1507 1508 DPRINTFN(2, ("msk_encap\n")); 1509 1510 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1511 if (entry == NULL) { 1512 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1513 return (ENOBUFS); 1514 } 1515 txmap = entry->dmamap; 1516 1517 cur = frag = *txidx; 1518 1519 #ifdef MSK_DEBUG 1520 if (mskdebug >= 2) 1521 msk_dump_mbuf(m_head); 1522 #endif 1523 1524 /* 1525 * Start packing the mbufs in this chain into 1526 * the fragment pointers. Stop when we run out 1527 * of fragments or hit the end of the mbuf chain. 1528 */ 1529 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1530 BUS_DMA_NOWAIT)) { 1531 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1532 return (ENOBUFS); 1533 } 1534 1535 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1536 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1537 bus_dmamap_unload(sc->sc_dmatag, txmap); 1538 return (ENOBUFS); 1539 } 1540 1541 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1542 1543 /* Sync the DMA map. */ 1544 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1545 BUS_DMASYNC_PREWRITE); 1546 1547 for (i = 0; i < txmap->dm_nsegs; i++) { 1548 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1549 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1550 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1551 f->sk_ctl = 0; 1552 if (i == 0) 1553 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1554 else 1555 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1556 cur = frag; 1557 SK_INC(frag, MSK_TX_RING_CNT); 1558 } 1559 1560 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1561 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1562 1563 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1564 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1565 1566 /* Sync descriptors before handing to chip */ 1567 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1568 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1569 1570 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1571 1572 /* Sync first descriptor to hand it off */ 1573 MSK_CDTXSYNC(sc_if, *txidx, 1, 1574 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1575 1576 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1577 1578 #ifdef MSK_DEBUG 1579 if (mskdebug >= 2) { 1580 struct msk_tx_desc *le; 1581 u_int32_t idx; 1582 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1583 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1584 msk_dump_txdesc(le, idx); 1585 } 1586 } 1587 #endif 1588 1589 *txidx = frag; 1590 1591 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1592 1593 return (0); 1594 } 1595 1596 void 1597 msk_start(struct ifnet *ifp) 1598 { 1599 struct sk_if_softc *sc_if = ifp->if_softc; 1600 struct mbuf *m_head = NULL; 1601 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1602 int pkts = 0; 1603 1604 DPRINTFN(2, ("msk_start\n")); 1605 1606 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1607 IFQ_POLL(&ifp->if_snd, m_head); 1608 if (m_head == NULL) 1609 break; 1610 1611 /* 1612 * Pack the data into the transmit ring. If we 1613 * don't have room, set the OACTIVE flag and wait 1614 * for the NIC to drain the ring. 1615 */ 1616 if (msk_encap(sc_if, m_head, &idx)) { 1617 ifp->if_flags |= IFF_OACTIVE; 1618 break; 1619 } 1620 1621 /* now we are committed to transmit the packet */ 1622 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1623 pkts++; 1624 1625 /* 1626 * If there's a BPF listener, bounce a copy of this frame 1627 * to him. 1628 */ 1629 bpf_mtap(ifp, m_head); 1630 } 1631 if (pkts == 0) 1632 return; 1633 1634 /* Transmit */ 1635 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1636 sc_if->sk_cdata.sk_tx_prod = idx; 1637 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1638 1639 /* Set a timeout in case the chip goes out to lunch. */ 1640 ifp->if_timer = 5; 1641 } 1642 } 1643 1644 void 1645 msk_watchdog(struct ifnet *ifp) 1646 { 1647 struct sk_if_softc *sc_if = ifp->if_softc; 1648 u_int32_t reg; 1649 int idx; 1650 1651 /* 1652 * Reclaim first as there is a possibility of losing Tx completion 1653 * interrupts. 1654 */ 1655 if (sc_if->sk_port == SK_PORT_A) 1656 reg = SK_STAT_BMU_TXA1_RIDX; 1657 else 1658 reg = SK_STAT_BMU_TXA2_RIDX; 1659 1660 idx = sk_win_read_2(sc_if->sk_softc, reg); 1661 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1662 msk_txeof(sc_if, idx); 1663 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1664 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1665 1666 ifp->if_oerrors++; 1667 1668 /* XXX Resets both ports; we shouldn't do that. */ 1669 msk_reset(sc_if->sk_softc); 1670 msk_init(ifp); 1671 } 1672 } 1673 } 1674 1675 static bool 1676 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1677 { 1678 struct sk_softc *sc = device_private(dv); 1679 1680 DPRINTFN(2, ("mskc_suspend\n")); 1681 1682 /* Turn off the 'driver is loaded' LED. */ 1683 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1684 1685 return true; 1686 } 1687 1688 static bool 1689 mskc_resume(device_t dv, const pmf_qual_t *qual) 1690 { 1691 struct sk_softc *sc = device_private(dv); 1692 1693 DPRINTFN(2, ("mskc_resume\n")); 1694 1695 msk_reset(sc); 1696 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1697 1698 return true; 1699 } 1700 1701 static __inline int 1702 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1703 { 1704 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1705 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1706 YU_RXSTAT_JABBER)) != 0 || 1707 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1708 YU_RXSTAT_BYTES(stat) != len) 1709 return (0); 1710 1711 return (1); 1712 } 1713 1714 void 1715 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1716 { 1717 struct sk_softc *sc = sc_if->sk_softc; 1718 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1719 struct mbuf *m; 1720 struct sk_chain *cur_rx; 1721 int cur, total_len = len; 1722 bus_dmamap_t dmamap; 1723 1724 DPRINTFN(2, ("msk_rxeof\n")); 1725 1726 cur = sc_if->sk_cdata.sk_rx_cons; 1727 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1728 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1729 1730 /* Sync the descriptor */ 1731 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1732 1733 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1734 if (cur_rx->sk_mbuf == NULL) 1735 return; 1736 1737 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1738 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1739 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1740 1741 m = cur_rx->sk_mbuf; 1742 cur_rx->sk_mbuf = NULL; 1743 1744 if (total_len < SK_MIN_FRAMELEN || 1745 total_len > ETHER_MAX_LEN_JUMBO || 1746 msk_rxvalid(sc, rxstat, total_len) == 0) { 1747 ifp->if_ierrors++; 1748 msk_newbuf(sc_if, cur, m, dmamap); 1749 return; 1750 } 1751 1752 /* 1753 * Try to allocate a new jumbo buffer. If that fails, copy the 1754 * packet to mbufs and put the jumbo buffer back in the ring 1755 * so it can be re-used. If allocating mbufs fails, then we 1756 * have to drop the packet. 1757 */ 1758 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1759 struct mbuf *m0; 1760 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1761 total_len + ETHER_ALIGN, 0, ifp, NULL); 1762 msk_newbuf(sc_if, cur, m, dmamap); 1763 if (m0 == NULL) { 1764 ifp->if_ierrors++; 1765 return; 1766 } 1767 m_adj(m0, ETHER_ALIGN); 1768 m = m0; 1769 } else { 1770 m_set_rcvif(m, ifp); 1771 m->m_pkthdr.len = m->m_len = total_len; 1772 } 1773 1774 /* pass it on. */ 1775 if_percpuq_enqueue(ifp->if_percpuq, m); 1776 } 1777 1778 void 1779 msk_txeof(struct sk_if_softc *sc_if, int idx) 1780 { 1781 struct sk_softc *sc = sc_if->sk_softc; 1782 struct msk_tx_desc *cur_tx; 1783 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1784 u_int32_t sk_ctl; 1785 struct sk_txmap_entry *entry; 1786 int cons, prog; 1787 1788 DPRINTFN(2, ("msk_txeof\n")); 1789 1790 /* 1791 * Go through our tx ring and free mbufs for those 1792 * frames that have been sent. 1793 */ 1794 cons = sc_if->sk_cdata.sk_tx_cons; 1795 prog = 0; 1796 while (cons != idx) { 1797 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1798 break; 1799 prog++; 1800 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1801 1802 MSK_CDTXSYNC(sc_if, cons, 1, 1803 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1804 sk_ctl = cur_tx->sk_ctl; 1805 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1806 #ifdef MSK_DEBUG 1807 if (mskdebug >= 2) 1808 msk_dump_txdesc(cur_tx, cons); 1809 #endif 1810 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1811 ifp->if_opackets++; 1812 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1813 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1814 1815 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1816 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1817 1818 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1819 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1820 link); 1821 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1822 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1823 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1824 } 1825 sc_if->sk_cdata.sk_tx_cnt--; 1826 SK_INC(cons, MSK_TX_RING_CNT); 1827 } 1828 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1829 1830 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1831 ifp->if_flags &= ~IFF_OACTIVE; 1832 1833 if (prog > 0) 1834 sc_if->sk_cdata.sk_tx_cons = cons; 1835 } 1836 1837 void 1838 msk_tick(void *xsc_if) 1839 { 1840 struct sk_if_softc *sc_if = xsc_if; 1841 struct mii_data *mii = &sc_if->sk_mii; 1842 uint16_t gpsr; 1843 int s; 1844 1845 s = splnet(); 1846 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); 1847 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { 1848 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); 1849 mii_tick(mii); 1850 } 1851 splx(s); 1852 1853 callout_schedule(&sc_if->sk_tick_ch, hz); 1854 } 1855 1856 void 1857 msk_intr_yukon(struct sk_if_softc *sc_if) 1858 { 1859 u_int8_t status; 1860 1861 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1862 /* RX overrun */ 1863 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1864 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1865 SK_RFCTL_RX_FIFO_OVER); 1866 } 1867 /* TX underrun */ 1868 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1869 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1870 SK_TFCTL_TX_FIFO_UNDER); 1871 } 1872 1873 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1874 } 1875 1876 int 1877 msk_intr(void *xsc) 1878 { 1879 struct sk_softc *sc = xsc; 1880 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1881 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1882 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1883 int claimed = 0; 1884 u_int32_t status; 1885 uint32_t st_status; 1886 uint16_t st_len; 1887 uint8_t st_opcode, st_link; 1888 struct msk_status_desc *cur_st; 1889 1890 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1891 if (status == 0) { 1892 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1893 return (0); 1894 } 1895 1896 status = CSR_READ_4(sc, SK_ISR); 1897 1898 if (sc_if0 != NULL) 1899 ifp0 = &sc_if0->sk_ethercom.ec_if; 1900 if (sc_if1 != NULL) 1901 ifp1 = &sc_if1->sk_ethercom.ec_if; 1902 1903 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1904 (ifp0->if_flags & IFF_RUNNING)) { 1905 msk_intr_yukon(sc_if0); 1906 } 1907 1908 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 1909 (ifp1->if_flags & IFF_RUNNING)) { 1910 msk_intr_yukon(sc_if1); 1911 } 1912 1913 for (;;) { 1914 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 1915 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1916 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1917 st_opcode = cur_st->sk_opcode; 1918 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 1919 MSK_CDSTSYNC(sc, sc->sk_status_idx, 1920 BUS_DMASYNC_PREREAD); 1921 break; 1922 } 1923 st_status = le32toh(cur_st->sk_status); 1924 st_len = le16toh(cur_st->sk_len); 1925 st_link = cur_st->sk_link; 1926 st_opcode &= ~SK_Y2_STOPC_OWN; 1927 1928 switch (st_opcode) { 1929 case SK_Y2_STOPC_RXSTAT: 1930 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 1931 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 1932 SK_RXQ1_Y2_PREF_PUTIDX, 1933 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 1934 break; 1935 case SK_Y2_STOPC_TXSTAT: 1936 if (sc_if0) 1937 msk_txeof(sc_if0, st_status 1938 & SK_Y2_ST_TXA1_MSKL); 1939 if (sc_if1) 1940 msk_txeof(sc_if1, 1941 ((st_status & SK_Y2_ST_TXA2_MSKL) 1942 >> SK_Y2_ST_TXA2_SHIFTL) 1943 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 1944 break; 1945 default: 1946 aprint_error("opcode=0x%x\n", st_opcode); 1947 break; 1948 } 1949 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 1950 } 1951 1952 #define MSK_STATUS_RING_OWN_CNT(sc) \ 1953 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 1954 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 1955 1956 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 1957 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 1958 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 1959 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 1960 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1961 1962 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 1963 } 1964 1965 if (status & SK_Y2_IMR_BMU) { 1966 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1967 claimed = 1; 1968 } 1969 1970 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1971 1972 if (ifp0 != NULL) 1973 if_schedule_deferred_start(ifp0); 1974 if (ifp1 != NULL) 1975 if_schedule_deferred_start(ifp1); 1976 1977 rnd_add_uint32(&sc->rnd_source, status); 1978 1979 if (sc->sk_int_mod_pending) 1980 msk_update_int_mod(sc, 1); 1981 1982 return claimed; 1983 } 1984 1985 void 1986 msk_init_yukon(struct sk_if_softc *sc_if) 1987 { 1988 u_int32_t v; 1989 u_int16_t reg; 1990 struct sk_softc *sc; 1991 int i; 1992 1993 sc = sc_if->sk_softc; 1994 1995 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 1996 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 1997 1998 DPRINTFN(6, ("msk_init_yukon: 1\n")); 1999 2000 /* GMAC and GPHY Reset */ 2001 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2002 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2003 DELAY(1000); 2004 2005 DPRINTFN(6, ("msk_init_yukon: 2\n")); 2006 2007 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 2008 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2009 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2010 2011 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2012 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2013 2014 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2015 2016 /* unused read of the interrupt source register */ 2017 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2018 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2019 2020 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2021 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2022 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2023 2024 /* MIB Counter Clear Mode set */ 2025 reg |= YU_PAR_MIB_CLR; 2026 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2027 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2028 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2029 2030 /* MIB Counter Clear Mode clear */ 2031 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2032 reg &= ~YU_PAR_MIB_CLR; 2033 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2034 2035 /* receive control reg */ 2036 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2037 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2038 2039 /* transmit control register */ 2040 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2041 2042 /* transmit flow control register */ 2043 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2044 2045 /* transmit parameter register */ 2046 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2047 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2048 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2049 2050 /* serial mode register */ 2051 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2052 reg = YU_SMR_DATA_BLIND(0x1c) | 2053 YU_SMR_MFL_VLAN | 2054 YU_SMR_IPG_DATA(0x1e); 2055 2056 if (sc->sk_type != SK_YUKON_FE) 2057 reg |= YU_SMR_MFL_JUMBO; 2058 2059 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2060 2061 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2062 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2063 /* msk_attach calls me before ether_ifattach so check null */ 2064 if (ifp != NULL && ifp->if_sadl != NULL) 2065 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2066 sizeof(sc_if->sk_enaddr)); 2067 /* Setup Yukon's address */ 2068 for (i = 0; i < 3; i++) { 2069 /* Write Source Address 1 (unicast filter) */ 2070 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2071 sc_if->sk_enaddr[i * 2] | 2072 sc_if->sk_enaddr[i * 2 + 1] << 8); 2073 } 2074 2075 for (i = 0; i < 3; i++) { 2076 reg = sk_win_read_2(sc_if->sk_softc, 2077 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2078 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2079 } 2080 2081 /* Set promiscuous mode */ 2082 msk_setpromisc(sc_if); 2083 2084 /* Set multicast filter */ 2085 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2086 msk_setmulti(sc_if); 2087 2088 /* enable interrupt mask for counter overflows */ 2089 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2090 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2091 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2092 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2093 2094 /* Configure RX MAC FIFO Flush Mask */ 2095 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2096 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2097 YU_RXSTAT_JABBER; 2098 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2099 2100 /* Configure RX MAC FIFO */ 2101 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2102 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2103 SK_RFCTL_FIFO_FLUSH_ON); 2104 2105 /* Increase flush threshould to 64 bytes */ 2106 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2107 SK_RFCTL_FIFO_THRESHOLD + 1); 2108 2109 /* Configure TX MAC FIFO */ 2110 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2111 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2112 2113 #if 1 2114 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2115 #endif 2116 DPRINTFN(6, ("msk_init_yukon: end\n")); 2117 } 2118 2119 /* 2120 * Note that to properly initialize any part of the GEnesis chip, 2121 * you first have to take it out of reset mode. 2122 */ 2123 int 2124 msk_init(struct ifnet *ifp) 2125 { 2126 struct sk_if_softc *sc_if = ifp->if_softc; 2127 struct sk_softc *sc = sc_if->sk_softc; 2128 int rc = 0, s; 2129 uint32_t imr, imtimer_ticks; 2130 2131 2132 DPRINTFN(2, ("msk_init\n")); 2133 2134 s = splnet(); 2135 2136 /* Cancel pending I/O and free all RX/TX buffers. */ 2137 msk_stop(ifp,0); 2138 2139 /* Configure I2C registers */ 2140 2141 /* Configure XMAC(s) */ 2142 msk_init_yukon(sc_if); 2143 if ((rc = ether_mediachange(ifp)) != 0) 2144 goto out; 2145 2146 /* Configure transmit arbiter(s) */ 2147 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2148 #if 0 2149 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2150 #endif 2151 2152 /* Configure RAMbuffers */ 2153 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2154 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2155 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2156 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2157 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2158 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2159 2160 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2161 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2162 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2163 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2164 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2165 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2166 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2167 2168 /* Configure BMUs */ 2169 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2170 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2171 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2172 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2173 2174 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2175 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2176 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2177 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2178 2179 /* Make sure the sync transmit queue is disabled. */ 2180 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2181 2182 /* Init descriptors */ 2183 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2184 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2185 "memory for rx buffers\n"); 2186 msk_stop(ifp,0); 2187 splx(s); 2188 return ENOBUFS; 2189 } 2190 2191 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2192 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2193 "memory for tx buffers\n"); 2194 msk_stop(ifp,0); 2195 splx(s); 2196 return ENOBUFS; 2197 } 2198 2199 /* Set interrupt moderation if changed via sysctl. */ 2200 switch (sc->sk_type) { 2201 case SK_YUKON_EC: 2202 case SK_YUKON_EC_U: 2203 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2204 break; 2205 case SK_YUKON_FE: 2206 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2207 break; 2208 case SK_YUKON_XL: 2209 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2210 break; 2211 default: 2212 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2213 } 2214 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2215 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2216 sk_win_write_4(sc, SK_IMTIMERINIT, 2217 SK_IM_USECS(sc->sk_int_mod)); 2218 aprint_verbose_dev(sc->sk_dev, 2219 "interrupt moderation is %d us\n", sc->sk_int_mod); 2220 } 2221 2222 /* Initialize prefetch engine. */ 2223 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2224 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2225 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2226 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2227 MSK_RX_RING_ADDR(sc_if, 0)); 2228 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2229 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2230 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2231 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2232 2233 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2234 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2235 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2236 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2237 MSK_TX_RING_ADDR(sc_if, 0)); 2238 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2239 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2240 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2241 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2242 2243 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2244 sc_if->sk_cdata.sk_rx_prod); 2245 2246 /* Configure interrupt handling */ 2247 if (sc_if->sk_port == SK_PORT_A) 2248 sc->sk_intrmask |= SK_Y2_INTRS1; 2249 else 2250 sc->sk_intrmask |= SK_Y2_INTRS2; 2251 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2252 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2253 2254 ifp->if_flags |= IFF_RUNNING; 2255 ifp->if_flags &= ~IFF_OACTIVE; 2256 2257 callout_schedule(&sc_if->sk_tick_ch, hz); 2258 2259 out: 2260 splx(s); 2261 return rc; 2262 } 2263 2264 void 2265 msk_stop(struct ifnet *ifp, int disable) 2266 { 2267 struct sk_if_softc *sc_if = ifp->if_softc; 2268 struct sk_softc *sc = sc_if->sk_softc; 2269 struct sk_txmap_entry *dma; 2270 int i; 2271 2272 DPRINTFN(2, ("msk_stop\n")); 2273 2274 callout_stop(&sc_if->sk_tick_ch); 2275 2276 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2277 2278 /* Stop transfer of Tx descriptors */ 2279 2280 /* Stop transfer of Rx descriptors */ 2281 2282 /* Turn off various components of this interface. */ 2283 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2284 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2285 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2286 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2287 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2288 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2289 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2290 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2291 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2292 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2293 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2294 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2295 2296 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2297 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2298 2299 /* Disable interrupts */ 2300 if (sc_if->sk_port == SK_PORT_A) 2301 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2302 else 2303 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2304 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2305 2306 SK_XM_READ_2(sc_if, XM_ISR); 2307 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2308 2309 /* Free RX and TX mbufs still in the queues. */ 2310 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2311 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2312 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2313 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2314 } 2315 } 2316 2317 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2318 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2319 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2320 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2321 #if 1 2322 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2323 sc_if->sk_cdata.sk_tx_map[i], link); 2324 sc_if->sk_cdata.sk_tx_map[i] = 0; 2325 #endif 2326 } 2327 } 2328 2329 #if 1 2330 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2331 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2332 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2333 free(dma, M_DEVBUF); 2334 } 2335 #endif 2336 } 2337 2338 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2339 NULL, NULL); 2340 2341 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2342 NULL, NULL); 2343 2344 #ifdef MSK_DEBUG 2345 void 2346 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2347 { 2348 #define DESC_PRINT(X) \ 2349 if (X) \ 2350 printf("txdesc[%d]." #X "=%#x\n", \ 2351 idx, X); 2352 2353 DESC_PRINT(letoh32(le->sk_addr)); 2354 DESC_PRINT(letoh16(le->sk_len)); 2355 DESC_PRINT(le->sk_ctl); 2356 DESC_PRINT(le->sk_opcode); 2357 #undef DESC_PRINT 2358 } 2359 2360 void 2361 msk_dump_bytes(const char *data, int len) 2362 { 2363 int c, i, j; 2364 2365 for (i = 0; i < len; i += 16) { 2366 printf("%08x ", i); 2367 c = len - i; 2368 if (c > 16) c = 16; 2369 2370 for (j = 0; j < c; j++) { 2371 printf("%02x ", data[i + j] & 0xff); 2372 if ((j & 0xf) == 7 && j > 0) 2373 printf(" "); 2374 } 2375 2376 for (; j < 16; j++) 2377 printf(" "); 2378 printf(" "); 2379 2380 for (j = 0; j < c; j++) { 2381 int ch = data[i + j] & 0xff; 2382 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2383 } 2384 2385 printf("\n"); 2386 2387 if (c < 16) 2388 break; 2389 } 2390 } 2391 2392 void 2393 msk_dump_mbuf(struct mbuf *m) 2394 { 2395 int count = m->m_pkthdr.len; 2396 2397 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2398 2399 while (count > 0 && m) { 2400 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2401 m, m->m_data, m->m_len); 2402 msk_dump_bytes(mtod(m, char *), m->m_len); 2403 2404 count -= m->m_len; 2405 m = m->m_next; 2406 } 2407 } 2408 #endif 2409 2410 static int 2411 msk_sysctl_handler(SYSCTLFN_ARGS) 2412 { 2413 int error, t; 2414 struct sysctlnode node; 2415 struct sk_softc *sc; 2416 2417 node = *rnode; 2418 sc = node.sysctl_data; 2419 t = sc->sk_int_mod; 2420 node.sysctl_data = &t; 2421 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2422 if (error || newp == NULL) 2423 return error; 2424 2425 if (t < SK_IM_MIN || t > SK_IM_MAX) 2426 return EINVAL; 2427 2428 /* update the softc with sysctl-changed value, and mark 2429 for hardware update */ 2430 sc->sk_int_mod = t; 2431 sc->sk_int_mod_pending = 1; 2432 return 0; 2433 } 2434 2435 /* 2436 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2437 * set up in skc_attach() 2438 */ 2439 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2440 { 2441 int rc; 2442 const struct sysctlnode *node; 2443 2444 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2445 0, CTLTYPE_NODE, "msk", 2446 SYSCTL_DESCR("msk interface controls"), 2447 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2448 goto err; 2449 } 2450 2451 msk_root_num = node->sysctl_num; 2452 return; 2453 2454 err: 2455 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2456 } 2457
Indexes created Thu Oct 02 10:09:58 GMT 2025