if_msk.c revision 1.55.2.1
1 /* $NetBSD: if_msk.c,v 1.55.2.1 2018/06/25 07:25:52 pgoyette Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.65 2008/09/10 14:01:22 blambert Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.55.2.1 2018/06/25 07:25:52 pgoyette Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *, int); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 124 void msk_update_int_mod(struct sk_softc *, int); 125 126 int msk_miibus_readreg(device_t, int, int); 127 void msk_miibus_writereg(device_t, int, int, int); 128 void msk_miibus_statchg(struct ifnet *); 129 130 void msk_setmulti(struct sk_if_softc *); 131 void msk_setpromisc(struct sk_if_softc *); 132 void msk_tick(void *); 133 134 /* #define MSK_DEBUG 1 */ 135 #ifdef MSK_DEBUG 136 #define DPRINTF(x) if (mskdebug) printf x 137 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 138 int mskdebug = MSK_DEBUG; 139 140 void msk_dump_txdesc(struct msk_tx_desc *, int); 141 void msk_dump_mbuf(struct mbuf *); 142 void msk_dump_bytes(const char *, int); 143 #else 144 #define DPRINTF(x) 145 #define DPRINTFN(n,x) 146 #endif 147 148 static int msk_sysctl_handler(SYSCTLFN_PROTO); 149 static int msk_root_num; 150 151 /* supported device vendors */ 152 static const struct msk_product { 153 pci_vendor_id_t msk_vendor; 154 pci_product_id_t msk_product; 155 } msk_products[] = { 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 195 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 196 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 197 }; 198 199 static inline u_int32_t 200 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 201 { 202 return CSR_READ_4(sc, reg); 203 } 204 205 static inline u_int16_t 206 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_2(sc, reg); 209 } 210 211 static inline u_int8_t 212 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 213 { 214 return CSR_READ_1(sc, reg); 215 } 216 217 static inline void 218 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 219 { 220 CSR_WRITE_4(sc, reg, x); 221 } 222 223 static inline void 224 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 225 { 226 CSR_WRITE_2(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 231 { 232 CSR_WRITE_1(sc, reg, x); 233 } 234 235 int 236 msk_miibus_readreg(device_t dev, int phy, int reg) 237 { 238 struct sk_if_softc *sc_if = device_private(dev); 239 u_int16_t val; 240 int i; 241 242 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 243 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 244 245 for (i = 0; i < SK_TIMEOUT; i++) { 246 DELAY(1); 247 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 248 if (val & YU_SMICR_READ_VALID) 249 break; 250 } 251 252 if (i == SK_TIMEOUT) { 253 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 254 return (0); 255 } 256 257 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 258 SK_TIMEOUT)); 259 260 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 261 262 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 263 phy, reg, val)); 264 265 return (val); 266 } 267 268 void 269 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 270 { 271 struct sk_if_softc *sc_if = device_private(dev); 272 int i; 273 274 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 275 phy, reg, val)); 276 277 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 278 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 279 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 280 281 for (i = 0; i < SK_TIMEOUT; i++) { 282 DELAY(1); 283 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 284 break; 285 } 286 287 if (i == SK_TIMEOUT) 288 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 289 } 290 291 void 292 msk_miibus_statchg(struct ifnet *ifp) 293 { 294 struct sk_if_softc *sc_if = ifp->if_softc; 295 struct mii_data *mii = &sc_if->sk_mii; 296 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 297 int gpcr; 298 299 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 300 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 301 302 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 303 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 304 /* Set speed. */ 305 gpcr |= YU_GPCR_SPEED_DIS; 306 switch (IFM_SUBTYPE(mii->mii_media_active)) { 307 case IFM_1000_SX: 308 case IFM_1000_LX: 309 case IFM_1000_CX: 310 case IFM_1000_T: 311 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 312 break; 313 case IFM_100_TX: 314 gpcr |= YU_GPCR_SPEED; 315 break; 316 } 317 318 /* Set duplex. */ 319 gpcr |= YU_GPCR_DPLX_DIS; 320 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 321 gpcr |= YU_GPCR_DUPLEX; 322 323 /* Disable flow control. */ 324 gpcr |= YU_GPCR_FCTL_DIS; 325 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 326 } 327 328 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 329 330 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 331 SK_YU_READ_2(sc_if, YUKON_GPCR))); 332 } 333 334 void 335 msk_setmulti(struct sk_if_softc *sc_if) 336 { 337 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 338 u_int32_t hashes[2] = { 0, 0 }; 339 int h; 340 struct ethercom *ec = &sc_if->sk_ethercom; 341 struct ether_multi *enm; 342 struct ether_multistep step; 343 u_int16_t reg; 344 345 /* First, zot all the existing filters. */ 346 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 347 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 350 351 352 /* Now program new ones. */ 353 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 354 reg |= YU_RCR_UFLEN; 355 allmulti: 356 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 357 if ((ifp->if_flags & IFF_PROMISC) != 0) 358 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 359 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 360 hashes[0] = 0xFFFFFFFF; 361 hashes[1] = 0xFFFFFFFF; 362 } 363 } else { 364 /* First find the tail of the list. */ 365 ETHER_FIRST_MULTI(step, ec, enm); 366 while (enm != NULL) { 367 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 368 ETHER_ADDR_LEN)) { 369 ifp->if_flags |= IFF_ALLMULTI; 370 goto allmulti; 371 } 372 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 373 ((1 << SK_HASH_BITS) - 1); 374 if (h < 32) 375 hashes[0] |= (1 << h); 376 else 377 hashes[1] |= (1 << (h - 32)); 378 379 ETHER_NEXT_MULTI(step, enm); 380 } 381 reg |= YU_RCR_MUFLEN; 382 } 383 384 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 385 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 389 } 390 391 void 392 msk_setpromisc(struct sk_if_softc *sc_if) 393 { 394 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 395 396 if (ifp->if_flags & IFF_PROMISC) 397 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 398 YU_RCR_UFLEN | YU_RCR_MUFLEN); 399 else 400 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 401 YU_RCR_UFLEN | YU_RCR_MUFLEN); 402 } 403 404 int 405 msk_init_rx_ring(struct sk_if_softc *sc_if) 406 { 407 struct msk_chain_data *cd = &sc_if->sk_cdata; 408 struct msk_ring_data *rd = sc_if->sk_rdata; 409 int i, nexti; 410 411 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 412 413 for (i = 0; i < MSK_RX_RING_CNT; i++) { 414 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 415 if (i == (MSK_RX_RING_CNT - 1)) 416 nexti = 0; 417 else 418 nexti = i + 1; 419 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 420 } 421 422 for (i = 0; i < MSK_RX_RING_CNT; i++) { 423 if (msk_newbuf(sc_if, i, NULL, 424 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 425 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 426 return (ENOBUFS); 427 } 428 } 429 430 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 431 sc_if->sk_cdata.sk_rx_cons = 0; 432 433 return (0); 434 } 435 436 int 437 msk_init_tx_ring(struct sk_if_softc *sc_if) 438 { 439 struct sk_softc *sc = sc_if->sk_softc; 440 struct msk_chain_data *cd = &sc_if->sk_cdata; 441 struct msk_ring_data *rd = sc_if->sk_rdata; 442 bus_dmamap_t dmamap; 443 struct sk_txmap_entry *entry; 444 int i, nexti; 445 446 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 447 448 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 449 for (i = 0; i < MSK_TX_RING_CNT; i++) { 450 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 451 if (i == (MSK_TX_RING_CNT - 1)) 452 nexti = 0; 453 else 454 nexti = i + 1; 455 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 456 457 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 458 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 459 return (ENOBUFS); 460 461 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 462 if (!entry) { 463 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 464 return (ENOBUFS); 465 } 466 entry->dmamap = dmamap; 467 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 468 } 469 470 sc_if->sk_cdata.sk_tx_prod = 0; 471 sc_if->sk_cdata.sk_tx_cons = 0; 472 sc_if->sk_cdata.sk_tx_cnt = 0; 473 474 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 475 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 476 477 return (0); 478 } 479 480 int 481 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 482 bus_dmamap_t dmamap) 483 { 484 struct mbuf *m_new = NULL; 485 struct sk_chain *c; 486 struct msk_rx_desc *r; 487 488 if (m == NULL) { 489 void *buf = NULL; 490 491 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 492 if (m_new == NULL) 493 return (ENOBUFS); 494 495 /* Allocate the jumbo buffer */ 496 buf = msk_jalloc(sc_if); 497 if (buf == NULL) { 498 m_freem(m_new); 499 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 500 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 501 return (ENOBUFS); 502 } 503 504 /* Attach the buffer to the mbuf */ 505 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 506 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 507 } else { 508 /* 509 * We're re-using a previously allocated mbuf; 510 * be sure to re-init pointers and lengths to 511 * default values. 512 */ 513 m_new = m; 514 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 515 m_new->m_data = m_new->m_ext.ext_buf; 516 } 517 m_adj(m_new, ETHER_ALIGN); 518 519 c = &sc_if->sk_cdata.sk_rx_chain[i]; 520 r = c->sk_le; 521 c->sk_mbuf = m_new; 522 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 523 (((vaddr_t)m_new->m_data 524 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 525 r->sk_len = htole16(SK_JLEN); 526 r->sk_ctl = 0; 527 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 528 529 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 530 531 return (0); 532 } 533 534 /* 535 * Memory management for jumbo frames. 536 */ 537 538 int 539 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 540 { 541 struct sk_softc *sc = sc_if->sk_softc; 542 char *ptr, *kva; 543 bus_dma_segment_t seg; 544 int i, rseg, state, error; 545 struct sk_jpool_entry *entry; 546 547 state = error = 0; 548 549 /* Grab a big chunk o' storage. */ 550 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 551 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 552 aprint_error(": can't alloc rx buffers"); 553 return (ENOBUFS); 554 } 555 556 state = 1; 557 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 558 BUS_DMA_NOWAIT)) { 559 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 560 error = ENOBUFS; 561 goto out; 562 } 563 564 state = 2; 565 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 566 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 567 aprint_error(": can't create dma map"); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 3; 573 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 574 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 575 aprint_error(": can't load dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 4; 581 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 582 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 583 584 LIST_INIT(&sc_if->sk_jfree_listhead); 585 LIST_INIT(&sc_if->sk_jinuse_listhead); 586 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 587 588 /* 589 * Now divide it up into 9K pieces and save the addresses 590 * in an array. 591 */ 592 ptr = sc_if->sk_cdata.sk_jumbo_buf; 593 for (i = 0; i < MSK_JSLOTS; i++) { 594 sc_if->sk_cdata.sk_jslots[i] = ptr; 595 ptr += SK_JLEN; 596 entry = malloc(sizeof(struct sk_jpool_entry), 597 M_DEVBUF, M_NOWAIT); 598 if (entry == NULL) { 599 sc_if->sk_cdata.sk_jumbo_buf = NULL; 600 aprint_error(": no memory for jumbo buffer queue!"); 601 error = ENOBUFS; 602 goto out; 603 } 604 entry->slot = i; 605 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 606 entry, jpool_entries); 607 } 608 out: 609 if (error != 0) { 610 switch (state) { 611 case 4: 612 bus_dmamap_unload(sc->sc_dmatag, 613 sc_if->sk_cdata.sk_rx_jumbo_map); 614 case 3: 615 bus_dmamap_destroy(sc->sc_dmatag, 616 sc_if->sk_cdata.sk_rx_jumbo_map); 617 case 2: 618 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 619 case 1: 620 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 621 break; 622 default: 623 break; 624 } 625 } 626 627 return error; 628 } 629 630 /* 631 * Allocate a jumbo buffer. 632 */ 633 void * 634 msk_jalloc(struct sk_if_softc *sc_if) 635 { 636 struct sk_jpool_entry *entry; 637 638 mutex_enter(&sc_if->sk_jpool_mtx); 639 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 640 641 if (entry == NULL) { 642 mutex_exit(&sc_if->sk_jpool_mtx); 643 return NULL; 644 } 645 646 LIST_REMOVE(entry, jpool_entries); 647 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 648 mutex_exit(&sc_if->sk_jpool_mtx); 649 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 650 } 651 652 /* 653 * Release a jumbo buffer. 654 */ 655 void 656 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 657 { 658 struct sk_jpool_entry *entry; 659 struct sk_if_softc *sc; 660 int i; 661 662 /* Extract the softc struct pointer. */ 663 sc = (struct sk_if_softc *)arg; 664 665 if (sc == NULL) 666 panic("msk_jfree: can't find softc pointer!"); 667 668 /* calculate the slot this buffer belongs to */ 669 i = ((vaddr_t)buf 670 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 671 672 if ((i < 0) || (i >= MSK_JSLOTS)) 673 panic("msk_jfree: asked to free buffer that we don't manage!"); 674 675 mutex_enter(&sc->sk_jpool_mtx); 676 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 677 if (entry == NULL) 678 panic("msk_jfree: buffer not in use!"); 679 entry->slot = i; 680 LIST_REMOVE(entry, jpool_entries); 681 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 682 mutex_exit(&sc->sk_jpool_mtx); 683 684 if (__predict_true(m != NULL)) 685 pool_cache_put(mb_cache, m); 686 } 687 688 int 689 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 690 { 691 struct sk_if_softc *sc = ifp->if_softc; 692 int s, error; 693 694 s = splnet(); 695 696 DPRINTFN(2, ("msk_ioctl ETHER\n")); 697 switch (cmd) { 698 case SIOCSIFFLAGS: 699 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 700 break; 701 702 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 703 case IFF_RUNNING: 704 msk_stop(ifp, 1); 705 break; 706 case IFF_UP: 707 msk_init(ifp); 708 break; 709 case IFF_UP | IFF_RUNNING: 710 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 711 msk_setpromisc(sc); 712 msk_setmulti(sc); 713 } else 714 msk_init(ifp); 715 break; 716 } 717 sc->sk_if_flags = ifp->if_flags; 718 break; 719 default: 720 error = ether_ioctl(ifp, cmd, data); 721 if (error == ENETRESET) { 722 error = 0; 723 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 724 ; 725 else if (ifp->if_flags & IFF_RUNNING) { 726 /* 727 * Multicast list has changed; set the hardware 728 * filter accordingly. 729 */ 730 msk_setmulti(sc); 731 } 732 } 733 break; 734 } 735 736 splx(s); 737 return error; 738 } 739 740 void 741 msk_update_int_mod(struct sk_softc *sc, int verbose) 742 { 743 u_int32_t imtimer_ticks; 744 745 /* 746 * Configure interrupt moderation. The moderation timer 747 * defers interrupts specified in the interrupt moderation 748 * timer mask based on the timeout specified in the interrupt 749 * moderation timer init register. Each bit in the timer 750 * register represents one tick, so to specify a timeout in 751 * microseconds, we have to multiply by the correct number of 752 * ticks-per-microsecond. 753 */ 754 switch (sc->sk_type) { 755 case SK_YUKON_EC: 756 case SK_YUKON_EC_U: 757 case SK_YUKON_EX: 758 case SK_YUKON_SUPR: 759 case SK_YUKON_ULTRA2: 760 case SK_YUKON_OPTIMA: 761 case SK_YUKON_PRM: 762 case SK_YUKON_OPTIMA2: 763 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 764 break; 765 case SK_YUKON_FE: 766 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 767 break; 768 case SK_YUKON_XL: 769 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 770 break; 771 default: 772 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 773 } 774 if (verbose) 775 aprint_verbose_dev(sc->sk_dev, 776 "interrupt moderation is %d us\n", sc->sk_int_mod); 777 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 778 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 779 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 780 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 781 sc->sk_int_mod_pending = 0; 782 } 783 784 static int 785 msk_lookup(const struct pci_attach_args *pa) 786 { 787 const struct msk_product *pmsk; 788 789 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 790 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 791 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 792 return 1; 793 } 794 return 0; 795 } 796 797 /* 798 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 799 * IDs against our list and return a device name if we find a match. 800 */ 801 int 802 mskc_probe(device_t parent, cfdata_t match, void *aux) 803 { 804 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 805 806 return msk_lookup(pa); 807 } 808 809 /* 810 * Force the GEnesis into reset, then bring it out of reset. 811 */ 812 void 813 mskc_reset(struct sk_softc *sc) 814 { 815 u_int32_t imtimer_ticks, reg1; 816 int reg; 817 818 DPRINTFN(2, ("mskc_reset\n")); 819 820 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 821 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 822 823 DELAY(1000); 824 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 825 DELAY(2); 826 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 827 sk_win_write_1(sc, SK_TESTCTL1, 2); 828 829 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 830 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 831 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 832 else 833 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 834 835 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 836 sc->sk_type >= SK_YUKON_FE_P) { 837 uint32_t our; 838 839 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 840 841 /* enable all clocks. */ 842 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 843 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 844 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 845 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 846 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 847 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 848 /* Set all bits to 0 except bits 15..12 */ 849 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 850 /* Set to default value */ 851 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 852 } 853 854 /* release PHY from PowerDown/Coma mode. */ 855 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 856 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 857 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 858 else 859 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 860 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 861 862 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 863 sk_win_write_1(sc, SK_Y2_CLKGATE, 864 SK_Y2_CLKGATE_LINK1_GATE_DIS | 865 SK_Y2_CLKGATE_LINK2_GATE_DIS | 866 SK_Y2_CLKGATE_LINK1_CORE_DIS | 867 SK_Y2_CLKGATE_LINK2_CORE_DIS | 868 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 869 else 870 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 871 872 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 873 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 874 DELAY(1000); 875 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 876 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 877 878 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 879 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 880 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 881 } 882 883 sk_win_write_1(sc, SK_TESTCTL1, 1); 884 885 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 886 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 887 CSR_READ_2(sc, SK_LINK_CTRL))); 888 889 /* Disable ASF */ 890 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 891 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 892 893 /* Clear I2C IRQ noise */ 894 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 895 896 /* Disable hardware timer */ 897 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 898 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 899 900 /* Disable descriptor polling */ 901 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 902 903 /* Disable time stamps */ 904 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 905 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 906 907 /* Enable RAM interface */ 908 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 909 for (reg = SK_TO0;reg <= SK_TO11; reg++) 910 sk_win_write_1(sc, reg, 36); 911 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 912 for (reg = SK_TO0;reg <= SK_TO11; reg++) 913 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 914 915 /* 916 * Configure interrupt moderation. The moderation timer 917 * defers interrupts specified in the interrupt moderation 918 * timer mask based on the timeout specified in the interrupt 919 * moderation timer init register. Each bit in the timer 920 * register represents one tick, so to specify a timeout in 921 * microseconds, we have to multiply by the correct number of 922 * ticks-per-microsecond. 923 */ 924 switch (sc->sk_type) { 925 case SK_YUKON_EC: 926 case SK_YUKON_EC_U: 927 case SK_YUKON_EX: 928 case SK_YUKON_SUPR: 929 case SK_YUKON_ULTRA2: 930 case SK_YUKON_OPTIMA: 931 case SK_YUKON_PRM: 932 case SK_YUKON_OPTIMA2: 933 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 934 break; 935 case SK_YUKON_FE: 936 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 937 break; 938 case SK_YUKON_FE_P: 939 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 940 break; 941 case SK_YUKON_XL: 942 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 943 break; 944 default: 945 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 946 break; 947 } 948 949 /* Reset status ring. */ 950 memset(sc->sk_status_ring, 0, 951 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 952 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 953 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 954 sc->sk_status_idx = 0; 955 sc->sk_status_own_idx = 0; 956 957 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 958 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 959 960 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 961 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 962 sc->sk_status_map->dm_segs[0].ds_addr); 963 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 964 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 965 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 966 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 967 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 968 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 969 } else { 970 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 971 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 972 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 973 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 974 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 975 } 976 977 #if 0 978 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 979 #endif 980 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 981 982 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 983 984 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 985 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 986 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 987 988 msk_update_int_mod(sc, 0); 989 } 990 991 int 992 msk_probe(device_t parent, cfdata_t match, void *aux) 993 { 994 struct skc_attach_args *sa = aux; 995 996 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 997 return (0); 998 999 switch (sa->skc_type) { 1000 case SK_YUKON_XL: 1001 case SK_YUKON_EC_U: 1002 case SK_YUKON_EX: 1003 case SK_YUKON_EC: 1004 case SK_YUKON_FE: 1005 case SK_YUKON_FE_P: 1006 case SK_YUKON_SUPR: 1007 case SK_YUKON_ULTRA2: 1008 case SK_YUKON_OPTIMA: 1009 case SK_YUKON_PRM: 1010 case SK_YUKON_OPTIMA2: 1011 return (1); 1012 } 1013 1014 return (0); 1015 } 1016 1017 void 1018 msk_reset(struct sk_if_softc *sc_if) 1019 { 1020 /* GMAC and GPHY Reset */ 1021 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1022 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1023 DELAY(1000); 1024 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1025 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1026 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1027 } 1028 1029 static bool 1030 msk_resume(device_t dv, const pmf_qual_t *qual) 1031 { 1032 struct sk_if_softc *sc_if = device_private(dv); 1033 1034 msk_init_yukon(sc_if); 1035 return true; 1036 } 1037 1038 /* 1039 * Each XMAC chip is attached as a separate logical IP interface. 1040 * Single port cards will have only one logical interface of course. 1041 */ 1042 void 1043 msk_attach(device_t parent, device_t self, void *aux) 1044 { 1045 struct sk_if_softc *sc_if = device_private(self); 1046 struct sk_softc *sc = device_private(parent); 1047 struct skc_attach_args *sa = aux; 1048 struct ifnet *ifp; 1049 void *kva; 1050 int i; 1051 u_int32_t chunk; 1052 int mii_flags; 1053 1054 sc_if->sk_dev = self; 1055 sc_if->sk_port = sa->skc_port; 1056 sc_if->sk_softc = sc; 1057 sc->sk_if[sa->skc_port] = sc_if; 1058 1059 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1060 1061 /* 1062 * Get station address for this interface. Note that 1063 * dual port cards actually come with three station 1064 * addresses: one for each port, plus an extra. The 1065 * extra one is used by the SysKonnect driver software 1066 * as a 'virtual' station address for when both ports 1067 * are operating in failover mode. Currently we don't 1068 * use this extra address. 1069 */ 1070 for (i = 0; i < ETHER_ADDR_LEN; i++) 1071 sc_if->sk_enaddr[i] = 1072 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1073 1074 aprint_normal(": Ethernet address %s\n", 1075 ether_sprintf(sc_if->sk_enaddr)); 1076 1077 /* 1078 * Set up RAM buffer addresses. The Yukon2 has a small amount 1079 * of SRAM on it, somewhere between 4K and 48K. We need to 1080 * divide this up between the transmitter and receiver. We 1081 * give the receiver 2/3 of the memory (rounded down), and the 1082 * transmitter whatever remains. 1083 */ 1084 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1085 sc_if->sk_rx_ramstart = 0; 1086 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1087 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1088 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1089 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1090 1091 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1092 " tx_ramstart=%#x tx_ramend=%#x\n", 1093 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1094 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1095 1096 /* Allocate the descriptor queues. */ 1097 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1098 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1099 BUS_DMA_NOWAIT)) { 1100 aprint_error(": can't alloc rx buffers\n"); 1101 goto fail; 1102 } 1103 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1104 sc_if->sk_ring_nseg, 1105 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1106 aprint_error(": can't map dma buffers (%zu bytes)\n", 1107 sizeof(struct msk_ring_data)); 1108 goto fail_1; 1109 } 1110 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1111 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1112 &sc_if->sk_ring_map)) { 1113 aprint_error(": can't create dma map\n"); 1114 goto fail_2; 1115 } 1116 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1117 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1118 aprint_error(": can't load dma map\n"); 1119 goto fail_3; 1120 } 1121 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1122 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1123 1124 ifp = &sc_if->sk_ethercom.ec_if; 1125 /* Try to allocate memory for jumbo buffers. */ 1126 if (msk_alloc_jumbo_mem(sc_if)) { 1127 aprint_error(": jumbo buffer allocation failed\n"); 1128 goto fail_3; 1129 } 1130 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1131 if (sc->sk_type != SK_YUKON_FE) 1132 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1133 1134 ifp->if_softc = sc_if; 1135 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1136 ifp->if_ioctl = msk_ioctl; 1137 ifp->if_start = msk_start; 1138 ifp->if_stop = msk_stop; 1139 ifp->if_init = msk_init; 1140 ifp->if_watchdog = msk_watchdog; 1141 ifp->if_baudrate = 1000000000; 1142 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1143 IFQ_SET_READY(&ifp->if_snd); 1144 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1145 1146 msk_reset(sc_if); 1147 1148 /* 1149 * Do miibus setup. 1150 */ 1151 msk_init_yukon(sc_if); 1152 1153 DPRINTFN(2, ("msk_attach: 1\n")); 1154 1155 sc_if->sk_mii.mii_ifp = ifp; 1156 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1157 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1158 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1159 1160 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1161 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1162 ether_mediachange, ether_mediastatus); 1163 mii_flags = MIIF_DOPAUSE; 1164 if (sc->sk_fibertype) 1165 mii_flags |= MIIF_HAVEFIBER; 1166 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1167 MII_OFFSET_ANY, mii_flags); 1168 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1169 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1170 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1171 0, NULL); 1172 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1173 } else 1174 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1175 1176 callout_init(&sc_if->sk_tick_ch, 0); 1177 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1178 callout_schedule(&sc_if->sk_tick_ch, hz); 1179 1180 /* 1181 * Call MI attach routines. 1182 */ 1183 if_attach(ifp); 1184 if_deferred_start_init(ifp, NULL); 1185 ether_ifattach(ifp, sc_if->sk_enaddr); 1186 1187 if (pmf_device_register(self, NULL, msk_resume)) 1188 pmf_class_network_register(self, ifp); 1189 else 1190 aprint_error_dev(self, "couldn't establish power handler\n"); 1191 1192 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1193 RND_TYPE_NET, RND_FLAG_DEFAULT); 1194 1195 DPRINTFN(2, ("msk_attach: end\n")); 1196 return; 1197 1198 fail_3: 1199 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1200 fail_2: 1201 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1202 fail_1: 1203 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1204 fail: 1205 sc->sk_if[sa->skc_port] = NULL; 1206 } 1207 1208 int 1209 msk_detach(device_t self, int flags) 1210 { 1211 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1212 struct sk_softc *sc = sc_if->sk_softc; 1213 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1214 1215 if (sc->sk_if[sc_if->sk_port] == NULL) 1216 return (0); 1217 1218 rnd_detach_source(&sc->rnd_source); 1219 1220 callout_halt(&sc_if->sk_tick_ch, NULL); 1221 callout_destroy(&sc_if->sk_tick_ch); 1222 1223 /* Detach any PHYs we might have. */ 1224 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1225 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1226 1227 /* Delete any remaining media. */ 1228 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1229 1230 pmf_device_deregister(self); 1231 1232 ether_ifdetach(ifp); 1233 if_detach(ifp); 1234 1235 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1236 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1237 sizeof(struct msk_ring_data)); 1238 bus_dmamem_free(sc->sc_dmatag, 1239 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1240 sc->sk_if[sc_if->sk_port] = NULL; 1241 1242 return (0); 1243 } 1244 1245 int 1246 mskcprint(void *aux, const char *pnp) 1247 { 1248 struct skc_attach_args *sa = aux; 1249 1250 if (pnp) 1251 aprint_normal("msk port %c at %s", 1252 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1253 else 1254 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1255 return (UNCONF); 1256 } 1257 1258 /* 1259 * Attach the interface. Allocate softc structures, do ifmedia 1260 * setup and ethernet/BPF attach. 1261 */ 1262 void 1263 mskc_attach(device_t parent, device_t self, void *aux) 1264 { 1265 struct sk_softc *sc = device_private(self); 1266 struct pci_attach_args *pa = aux; 1267 struct skc_attach_args skca; 1268 pci_chipset_tag_t pc = pa->pa_pc; 1269 pcireg_t command, memtype; 1270 pci_intr_handle_t ih; 1271 const char *intrstr = NULL; 1272 bus_size_t size; 1273 int rc, sk_nodenum; 1274 u_int8_t hw, pmd; 1275 const char *revstr = NULL; 1276 const struct sysctlnode *node; 1277 void *kva; 1278 char intrbuf[PCI_INTRSTR_LEN]; 1279 1280 DPRINTFN(2, ("begin mskc_attach\n")); 1281 1282 sc->sk_dev = self; 1283 /* 1284 * Handle power management nonsense. 1285 */ 1286 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1287 1288 if (command == 0x01) { 1289 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1290 if (command & SK_PSTATE_MASK) { 1291 u_int32_t iobase, membase, irq; 1292 1293 /* Save important PCI config data. */ 1294 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1295 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1296 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1297 1298 /* Reset the power state. */ 1299 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1300 "mode -- setting to D0\n", 1301 command & SK_PSTATE_MASK); 1302 command &= 0xFFFFFFFC; 1303 pci_conf_write(pc, pa->pa_tag, 1304 SK_PCI_PWRMGMTCTRL, command); 1305 1306 /* Restore PCI config data. */ 1307 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1308 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1309 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1310 } 1311 } 1312 1313 /* 1314 * Map control/status registers. 1315 */ 1316 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1317 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1318 &sc->sk_bhandle, NULL, &size)) { 1319 aprint_error(": can't map mem space\n"); 1320 return; 1321 } 1322 1323 sc->sc_dmatag = pa->pa_dmat; 1324 1325 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1326 command |= PCI_COMMAND_MASTER_ENABLE; 1327 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1328 1329 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1330 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1331 1332 /* bail out here if chip is not recognized */ 1333 if (!(SK_IS_YUKON2(sc))) { 1334 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1335 goto fail_1; 1336 } 1337 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1338 1339 /* Allocate interrupt */ 1340 if (pci_intr_map(pa, &ih)) { 1341 aprint_error(": couldn't map interrupt\n"); 1342 goto fail_1; 1343 } 1344 1345 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1346 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1347 if (sc->sk_intrhand == NULL) { 1348 aprint_error(": couldn't establish interrupt"); 1349 if (intrstr != NULL) 1350 aprint_error(" at %s", intrstr); 1351 aprint_error("\n"); 1352 goto fail_1; 1353 } 1354 sc->sk_pc = pc; 1355 1356 if (bus_dmamem_alloc(sc->sc_dmatag, 1357 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), PAGE_SIZE, 1358 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1359 aprint_error(": can't alloc status buffers\n"); 1360 goto fail_2; 1361 } 1362 1363 if (bus_dmamem_map(sc->sc_dmatag, 1364 &sc->sk_status_seg, sc->sk_status_nseg, 1365 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1366 &kva, BUS_DMA_NOWAIT)) { 1367 aprint_error(": can't map dma buffers (%zu bytes)\n", 1368 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1369 goto fail_3; 1370 } 1371 if (bus_dmamap_create(sc->sc_dmatag, 1372 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1373 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1374 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1375 aprint_error(": can't create dma map\n"); 1376 goto fail_4; 1377 } 1378 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1379 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1380 NULL, BUS_DMA_NOWAIT)) { 1381 aprint_error(": can't load dma map\n"); 1382 goto fail_5; 1383 } 1384 sc->sk_status_ring = (struct msk_status_desc *)kva; 1385 1386 sc->sk_int_mod = SK_IM_DEFAULT; 1387 sc->sk_int_mod_pending = 0; 1388 1389 /* Reset the adapter. */ 1390 mskc_reset(sc); 1391 1392 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1393 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1394 1395 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1396 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1397 sc->sk_fibertype = 1; 1398 1399 switch (sc->sk_type) { 1400 case SK_YUKON_XL: 1401 sc->sk_name = "Yukon-2 XL"; 1402 break; 1403 case SK_YUKON_EC_U: 1404 sc->sk_name = "Yukon-2 EC Ultra"; 1405 break; 1406 case SK_YUKON_EX: 1407 sc->sk_name = "Yukon-2 Extreme"; 1408 break; 1409 case SK_YUKON_EC: 1410 sc->sk_name = "Yukon-2 EC"; 1411 break; 1412 case SK_YUKON_FE: 1413 sc->sk_name = "Yukon-2 FE"; 1414 break; 1415 case SK_YUKON_FE_P: 1416 sc->sk_name = "Yukon-2 FE+"; 1417 break; 1418 case SK_YUKON_SUPR: 1419 sc->sk_name = "Yukon-2 Supreme"; 1420 break; 1421 case SK_YUKON_ULTRA2: 1422 sc->sk_name = "Yukon-2 Ultra 2"; 1423 break; 1424 case SK_YUKON_OPTIMA: 1425 sc->sk_name = "Yukon-2 Optima"; 1426 break; 1427 case SK_YUKON_PRM: 1428 sc->sk_name = "Yukon-2 Optima Prime"; 1429 break; 1430 case SK_YUKON_OPTIMA2: 1431 sc->sk_name = "Yukon-2 Optima 2"; 1432 break; 1433 default: 1434 sc->sk_name = "Yukon (Unknown)"; 1435 } 1436 1437 if (sc->sk_type == SK_YUKON_XL) { 1438 switch (sc->sk_rev) { 1439 case SK_YUKON_XL_REV_A0: 1440 sc->sk_workaround = 0; 1441 revstr = "A0"; 1442 break; 1443 case SK_YUKON_XL_REV_A1: 1444 sc->sk_workaround = SK_WA_4109; 1445 revstr = "A1"; 1446 break; 1447 case SK_YUKON_XL_REV_A2: 1448 sc->sk_workaround = SK_WA_4109; 1449 revstr = "A2"; 1450 break; 1451 case SK_YUKON_XL_REV_A3: 1452 sc->sk_workaround = SK_WA_4109; 1453 revstr = "A3"; 1454 break; 1455 default: 1456 sc->sk_workaround = 0; 1457 break; 1458 } 1459 } 1460 1461 if (sc->sk_type == SK_YUKON_EC) { 1462 switch (sc->sk_rev) { 1463 case SK_YUKON_EC_REV_A1: 1464 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1465 revstr = "A1"; 1466 break; 1467 case SK_YUKON_EC_REV_A2: 1468 sc->sk_workaround = SK_WA_4109; 1469 revstr = "A2"; 1470 break; 1471 case SK_YUKON_EC_REV_A3: 1472 sc->sk_workaround = SK_WA_4109; 1473 revstr = "A3"; 1474 break; 1475 default: 1476 sc->sk_workaround = 0; 1477 break; 1478 } 1479 } 1480 1481 if (sc->sk_type == SK_YUKON_FE) { 1482 sc->sk_workaround = SK_WA_4109; 1483 switch (sc->sk_rev) { 1484 case SK_YUKON_FE_REV_A1: 1485 revstr = "A1"; 1486 break; 1487 case SK_YUKON_FE_REV_A2: 1488 revstr = "A2"; 1489 break; 1490 default: 1491 sc->sk_workaround = 0; 1492 break; 1493 } 1494 } 1495 1496 if (sc->sk_type == SK_YUKON_EC_U) { 1497 sc->sk_workaround = SK_WA_4109; 1498 switch (sc->sk_rev) { 1499 case SK_YUKON_EC_U_REV_A0: 1500 revstr = "A0"; 1501 break; 1502 case SK_YUKON_EC_U_REV_A1: 1503 revstr = "A1"; 1504 break; 1505 case SK_YUKON_EC_U_REV_B0: 1506 revstr = "B0"; 1507 break; 1508 case SK_YUKON_EC_U_REV_B1: 1509 revstr = "B1"; 1510 break; 1511 default: 1512 sc->sk_workaround = 0; 1513 break; 1514 } 1515 } 1516 1517 if (sc->sk_type == SK_YUKON_FE) { 1518 switch (sc->sk_rev) { 1519 case SK_YUKON_FE_REV_A1: 1520 revstr = "A1"; 1521 break; 1522 case SK_YUKON_FE_REV_A2: 1523 revstr = "A2"; 1524 break; 1525 default: 1526 ; 1527 } 1528 } 1529 1530 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1531 revstr = "A0"; 1532 1533 if (sc->sk_type == SK_YUKON_EX) { 1534 switch (sc->sk_rev) { 1535 case SK_YUKON_EX_REV_A0: 1536 revstr = "A0"; 1537 break; 1538 case SK_YUKON_EX_REV_B0: 1539 revstr = "B0"; 1540 break; 1541 default: 1542 ; 1543 } 1544 } 1545 1546 if (sc->sk_type == SK_YUKON_SUPR) { 1547 switch (sc->sk_rev) { 1548 case SK_YUKON_SUPR_REV_A0: 1549 revstr = "A0"; 1550 break; 1551 case SK_YUKON_SUPR_REV_B0: 1552 revstr = "B0"; 1553 break; 1554 case SK_YUKON_SUPR_REV_B1: 1555 revstr = "B1"; 1556 break; 1557 default: 1558 ; 1559 } 1560 } 1561 1562 if (sc->sk_type == SK_YUKON_PRM) { 1563 switch (sc->sk_rev) { 1564 case SK_YUKON_PRM_REV_Z1: 1565 revstr = "Z1"; 1566 break; 1567 case SK_YUKON_PRM_REV_A0: 1568 revstr = "A0"; 1569 break; 1570 default: 1571 ; 1572 } 1573 } 1574 1575 /* Announce the product name. */ 1576 aprint_normal(", %s", sc->sk_name); 1577 if (revstr != NULL) 1578 aprint_normal(" rev. %s", revstr); 1579 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1580 1581 sc->sk_macs = 1; 1582 1583 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1584 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1585 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1586 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1587 sc->sk_macs++; 1588 } 1589 1590 skca.skc_port = SK_PORT_A; 1591 skca.skc_type = sc->sk_type; 1592 skca.skc_rev = sc->sk_rev; 1593 (void)config_found(sc->sk_dev, &skca, mskcprint); 1594 1595 if (sc->sk_macs > 1) { 1596 skca.skc_port = SK_PORT_B; 1597 skca.skc_type = sc->sk_type; 1598 skca.skc_rev = sc->sk_rev; 1599 (void)config_found(sc->sk_dev, &skca, mskcprint); 1600 } 1601 1602 /* Turn on the 'driver is loaded' LED. */ 1603 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1604 1605 /* skc sysctl setup */ 1606 1607 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1608 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1609 SYSCTL_DESCR("mskc per-controller controls"), 1610 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1611 CTL_EOL)) != 0) { 1612 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1613 goto fail_6; 1614 } 1615 1616 sk_nodenum = node->sysctl_num; 1617 1618 /* interrupt moderation time in usecs */ 1619 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1620 CTLFLAG_READWRITE, 1621 CTLTYPE_INT, "int_mod", 1622 SYSCTL_DESCR("msk interrupt moderation timer"), 1623 msk_sysctl_handler, 0, (void *)sc, 1624 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1625 CTL_EOL)) != 0) { 1626 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1627 goto fail_6; 1628 } 1629 1630 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1631 aprint_error_dev(self, "couldn't establish power handler\n"); 1632 1633 return; 1634 1635 fail_6: 1636 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1637 fail_5: 1638 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1639 fail_4: 1640 bus_dmamem_unmap(sc->sc_dmatag, kva, 1641 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1642 fail_3: 1643 bus_dmamem_free(sc->sc_dmatag, 1644 &sc->sk_status_seg, sc->sk_status_nseg); 1645 sc->sk_status_nseg = 0; 1646 fail_2: 1647 pci_intr_disestablish(pc, sc->sk_intrhand); 1648 sc->sk_intrhand = NULL; 1649 fail_1: 1650 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1651 sc->sk_bsize = 0; 1652 } 1653 1654 int 1655 mskc_detach(device_t self, int flags) 1656 { 1657 struct sk_softc *sc = (struct sk_softc *)self; 1658 int rv; 1659 1660 rv = config_detach_children(self, flags); 1661 if (rv != 0) 1662 return (rv); 1663 1664 if (sc->sk_status_nseg > 0) { 1665 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1666 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1667 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1668 bus_dmamem_free(sc->sc_dmatag, 1669 &sc->sk_status_seg, sc->sk_status_nseg); 1670 } 1671 1672 if (sc->sk_intrhand) 1673 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1674 1675 if (sc->sk_bsize > 0) 1676 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1677 1678 return(0); 1679 } 1680 1681 int 1682 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1683 { 1684 struct sk_softc *sc = sc_if->sk_softc; 1685 struct msk_tx_desc *f = NULL; 1686 u_int32_t frag, cur; 1687 int i; 1688 struct sk_txmap_entry *entry; 1689 bus_dmamap_t txmap; 1690 1691 DPRINTFN(2, ("msk_encap\n")); 1692 1693 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1694 if (entry == NULL) { 1695 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1696 return (ENOBUFS); 1697 } 1698 txmap = entry->dmamap; 1699 1700 cur = frag = *txidx; 1701 1702 #ifdef MSK_DEBUG 1703 if (mskdebug >= 2) 1704 msk_dump_mbuf(m_head); 1705 #endif 1706 1707 /* 1708 * Start packing the mbufs in this chain into 1709 * the fragment pointers. Stop when we run out 1710 * of fragments or hit the end of the mbuf chain. 1711 */ 1712 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1713 BUS_DMA_NOWAIT)) { 1714 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1715 return (ENOBUFS); 1716 } 1717 1718 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1719 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1720 bus_dmamap_unload(sc->sc_dmatag, txmap); 1721 return (ENOBUFS); 1722 } 1723 1724 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1725 1726 /* Sync the DMA map. */ 1727 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1728 BUS_DMASYNC_PREWRITE); 1729 1730 for (i = 0; i < txmap->dm_nsegs; i++) { 1731 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1732 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1733 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1734 f->sk_ctl = 0; 1735 if (i == 0) 1736 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1737 else 1738 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1739 cur = frag; 1740 SK_INC(frag, MSK_TX_RING_CNT); 1741 } 1742 1743 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1744 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1745 1746 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1747 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1748 1749 /* Sync descriptors before handing to chip */ 1750 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1751 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1752 1753 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1754 1755 /* Sync first descriptor to hand it off */ 1756 MSK_CDTXSYNC(sc_if, *txidx, 1, 1757 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1758 1759 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1760 1761 #ifdef MSK_DEBUG 1762 if (mskdebug >= 2) { 1763 struct msk_tx_desc *le; 1764 u_int32_t idx; 1765 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1766 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1767 msk_dump_txdesc(le, idx); 1768 } 1769 } 1770 #endif 1771 1772 *txidx = frag; 1773 1774 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1775 1776 return (0); 1777 } 1778 1779 void 1780 msk_start(struct ifnet *ifp) 1781 { 1782 struct sk_if_softc *sc_if = ifp->if_softc; 1783 struct mbuf *m_head = NULL; 1784 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1785 int pkts = 0; 1786 1787 DPRINTFN(2, ("msk_start\n")); 1788 1789 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1790 IFQ_POLL(&ifp->if_snd, m_head); 1791 if (m_head == NULL) 1792 break; 1793 1794 /* 1795 * Pack the data into the transmit ring. If we 1796 * don't have room, set the OACTIVE flag and wait 1797 * for the NIC to drain the ring. 1798 */ 1799 if (msk_encap(sc_if, m_head, &idx)) { 1800 ifp->if_flags |= IFF_OACTIVE; 1801 break; 1802 } 1803 1804 /* now we are committed to transmit the packet */ 1805 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1806 pkts++; 1807 1808 /* 1809 * If there's a BPF listener, bounce a copy of this frame 1810 * to him. 1811 */ 1812 bpf_mtap(ifp, m_head); 1813 } 1814 if (pkts == 0) 1815 return; 1816 1817 /* Transmit */ 1818 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1819 sc_if->sk_cdata.sk_tx_prod = idx; 1820 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1821 1822 /* Set a timeout in case the chip goes out to lunch. */ 1823 ifp->if_timer = 5; 1824 } 1825 } 1826 1827 void 1828 msk_watchdog(struct ifnet *ifp) 1829 { 1830 struct sk_if_softc *sc_if = ifp->if_softc; 1831 u_int32_t reg; 1832 int idx; 1833 1834 /* 1835 * Reclaim first as there is a possibility of losing Tx completion 1836 * interrupts. 1837 */ 1838 if (sc_if->sk_port == SK_PORT_A) 1839 reg = SK_STAT_BMU_TXA1_RIDX; 1840 else 1841 reg = SK_STAT_BMU_TXA2_RIDX; 1842 1843 idx = sk_win_read_2(sc_if->sk_softc, reg); 1844 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1845 msk_txeof(sc_if, idx); 1846 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1847 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1848 1849 ifp->if_oerrors++; 1850 1851 /* XXX Resets both ports; we shouldn't do that. */ 1852 mskc_reset(sc_if->sk_softc); 1853 msk_reset(sc_if); 1854 msk_init(ifp); 1855 } 1856 } 1857 } 1858 1859 static bool 1860 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1861 { 1862 struct sk_softc *sc = device_private(dv); 1863 1864 DPRINTFN(2, ("mskc_suspend\n")); 1865 1866 /* Turn off the 'driver is loaded' LED. */ 1867 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1868 1869 return true; 1870 } 1871 1872 static bool 1873 mskc_resume(device_t dv, const pmf_qual_t *qual) 1874 { 1875 struct sk_softc *sc = device_private(dv); 1876 1877 DPRINTFN(2, ("mskc_resume\n")); 1878 1879 mskc_reset(sc); 1880 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1881 1882 return true; 1883 } 1884 1885 static __inline int 1886 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1887 { 1888 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1889 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1890 YU_RXSTAT_JABBER)) != 0 || 1891 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1892 YU_RXSTAT_BYTES(stat) != len) 1893 return (0); 1894 1895 return (1); 1896 } 1897 1898 void 1899 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1900 { 1901 struct sk_softc *sc = sc_if->sk_softc; 1902 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1903 struct mbuf *m; 1904 struct sk_chain *cur_rx; 1905 int cur, total_len = len; 1906 bus_dmamap_t dmamap; 1907 1908 DPRINTFN(2, ("msk_rxeof\n")); 1909 1910 cur = sc_if->sk_cdata.sk_rx_cons; 1911 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1912 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1913 1914 /* Sync the descriptor */ 1915 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1916 1917 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1918 if (cur_rx->sk_mbuf == NULL) 1919 return; 1920 1921 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1922 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1923 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1924 1925 m = cur_rx->sk_mbuf; 1926 cur_rx->sk_mbuf = NULL; 1927 1928 if (total_len < SK_MIN_FRAMELEN || 1929 total_len > ETHER_MAX_LEN_JUMBO || 1930 msk_rxvalid(sc, rxstat, total_len) == 0) { 1931 ifp->if_ierrors++; 1932 msk_newbuf(sc_if, cur, m, dmamap); 1933 return; 1934 } 1935 1936 /* 1937 * Try to allocate a new jumbo buffer. If that fails, copy the 1938 * packet to mbufs and put the jumbo buffer back in the ring 1939 * so it can be re-used. If allocating mbufs fails, then we 1940 * have to drop the packet. 1941 */ 1942 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1943 struct mbuf *m0; 1944 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1945 total_len + ETHER_ALIGN, 0, ifp, NULL); 1946 msk_newbuf(sc_if, cur, m, dmamap); 1947 if (m0 == NULL) { 1948 ifp->if_ierrors++; 1949 return; 1950 } 1951 m_adj(m0, ETHER_ALIGN); 1952 m = m0; 1953 } else { 1954 m_set_rcvif(m, ifp); 1955 m->m_pkthdr.len = m->m_len = total_len; 1956 } 1957 1958 /* pass it on. */ 1959 if_percpuq_enqueue(ifp->if_percpuq, m); 1960 } 1961 1962 void 1963 msk_txeof(struct sk_if_softc *sc_if, int idx) 1964 { 1965 struct sk_softc *sc = sc_if->sk_softc; 1966 struct msk_tx_desc *cur_tx; 1967 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1968 u_int32_t sk_ctl; 1969 struct sk_txmap_entry *entry; 1970 int cons, prog; 1971 1972 DPRINTFN(2, ("msk_txeof\n")); 1973 1974 /* 1975 * Go through our tx ring and free mbufs for those 1976 * frames that have been sent. 1977 */ 1978 cons = sc_if->sk_cdata.sk_tx_cons; 1979 prog = 0; 1980 while (cons != idx) { 1981 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1982 break; 1983 prog++; 1984 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1985 1986 MSK_CDTXSYNC(sc_if, cons, 1, 1987 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1988 sk_ctl = cur_tx->sk_ctl; 1989 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1990 #ifdef MSK_DEBUG 1991 if (mskdebug >= 2) 1992 msk_dump_txdesc(cur_tx, cons); 1993 #endif 1994 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1995 ifp->if_opackets++; 1996 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1997 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1998 1999 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2000 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2001 2002 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2003 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2004 link); 2005 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 2006 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 2007 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 2008 } 2009 sc_if->sk_cdata.sk_tx_cnt--; 2010 SK_INC(cons, MSK_TX_RING_CNT); 2011 } 2012 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2013 2014 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2015 ifp->if_flags &= ~IFF_OACTIVE; 2016 2017 if (prog > 0) 2018 sc_if->sk_cdata.sk_tx_cons = cons; 2019 } 2020 2021 void 2022 msk_tick(void *xsc_if) 2023 { 2024 struct sk_if_softc *sc_if = xsc_if; 2025 struct mii_data *mii = &sc_if->sk_mii; 2026 int s; 2027 2028 s = splnet(); 2029 mii_tick(mii); 2030 splx(s); 2031 2032 callout_schedule(&sc_if->sk_tick_ch, hz); 2033 } 2034 2035 void 2036 msk_intr_yukon(struct sk_if_softc *sc_if) 2037 { 2038 u_int8_t status; 2039 2040 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2041 /* RX overrun */ 2042 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2043 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2044 SK_RFCTL_RX_FIFO_OVER); 2045 } 2046 /* TX underrun */ 2047 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2048 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2049 SK_TFCTL_TX_FIFO_UNDER); 2050 } 2051 2052 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2053 } 2054 2055 int 2056 msk_intr(void *xsc) 2057 { 2058 struct sk_softc *sc = xsc; 2059 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2060 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2061 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2062 int claimed = 0; 2063 u_int32_t status; 2064 uint32_t st_status; 2065 uint16_t st_len; 2066 uint8_t st_opcode, st_link; 2067 struct msk_status_desc *cur_st; 2068 2069 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2070 if (status == 0) { 2071 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2072 return (0); 2073 } 2074 2075 status = CSR_READ_4(sc, SK_ISR); 2076 2077 if (sc_if0 != NULL) 2078 ifp0 = &sc_if0->sk_ethercom.ec_if; 2079 if (sc_if1 != NULL) 2080 ifp1 = &sc_if1->sk_ethercom.ec_if; 2081 2082 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2083 (ifp0->if_flags & IFF_RUNNING)) { 2084 msk_intr_yukon(sc_if0); 2085 } 2086 2087 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2088 (ifp1->if_flags & IFF_RUNNING)) { 2089 msk_intr_yukon(sc_if1); 2090 } 2091 2092 for (;;) { 2093 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2094 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2095 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2096 st_opcode = cur_st->sk_opcode; 2097 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 2098 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2099 BUS_DMASYNC_PREREAD); 2100 break; 2101 } 2102 st_status = le32toh(cur_st->sk_status); 2103 st_len = le16toh(cur_st->sk_len); 2104 st_link = cur_st->sk_link; 2105 st_opcode &= ~SK_Y2_STOPC_OWN; 2106 2107 switch (st_opcode) { 2108 case SK_Y2_STOPC_RXSTAT: 2109 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 2110 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 2111 SK_RXQ1_Y2_PREF_PUTIDX, 2112 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 2113 break; 2114 case SK_Y2_STOPC_TXSTAT: 2115 if (sc_if0) 2116 msk_txeof(sc_if0, st_status 2117 & SK_Y2_ST_TXA1_MSKL); 2118 if (sc_if1) 2119 msk_txeof(sc_if1, 2120 ((st_status & SK_Y2_ST_TXA2_MSKL) 2121 >> SK_Y2_ST_TXA2_SHIFTL) 2122 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 2123 break; 2124 default: 2125 aprint_error("opcode=0x%x\n", st_opcode); 2126 break; 2127 } 2128 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2129 } 2130 2131 #define MSK_STATUS_RING_OWN_CNT(sc) \ 2132 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 2133 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 2134 2135 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 2136 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 2137 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2138 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 2139 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2140 2141 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 2142 } 2143 2144 if (status & SK_Y2_IMR_BMU) { 2145 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2146 claimed = 1; 2147 } 2148 2149 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2150 2151 if (ifp0 != NULL) 2152 if_schedule_deferred_start(ifp0); 2153 if (ifp1 != NULL) 2154 if_schedule_deferred_start(ifp1); 2155 2156 rnd_add_uint32(&sc->rnd_source, status); 2157 2158 if (sc->sk_int_mod_pending) 2159 msk_update_int_mod(sc, 1); 2160 2161 return claimed; 2162 } 2163 2164 void 2165 msk_init_yukon(struct sk_if_softc *sc_if) 2166 { 2167 u_int32_t v; 2168 u_int16_t reg; 2169 struct sk_softc *sc; 2170 int i; 2171 2172 sc = sc_if->sk_softc; 2173 2174 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2175 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2176 2177 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2178 2179 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2180 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2181 2182 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2183 2184 /* unused read of the interrupt source register */ 2185 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2186 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2187 2188 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2189 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2190 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2191 2192 /* MIB Counter Clear Mode set */ 2193 reg |= YU_PAR_MIB_CLR; 2194 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2195 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2196 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2197 2198 /* MIB Counter Clear Mode clear */ 2199 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2200 reg &= ~YU_PAR_MIB_CLR; 2201 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2202 2203 /* receive control reg */ 2204 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2205 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2206 2207 /* transmit control register */ 2208 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2209 2210 /* transmit flow control register */ 2211 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2212 2213 /* transmit parameter register */ 2214 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2215 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2216 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2217 2218 /* serial mode register */ 2219 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2220 reg = YU_SMR_DATA_BLIND(0x1c) | 2221 YU_SMR_MFL_VLAN | 2222 YU_SMR_IPG_DATA(0x1e); 2223 2224 if (sc->sk_type != SK_YUKON_FE && 2225 sc->sk_type != SK_YUKON_FE_P) 2226 reg |= YU_SMR_MFL_JUMBO; 2227 2228 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2229 2230 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2231 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2232 /* msk_attach calls me before ether_ifattach so check null */ 2233 if (ifp != NULL && ifp->if_sadl != NULL) 2234 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2235 sizeof(sc_if->sk_enaddr)); 2236 /* Setup Yukon's address */ 2237 for (i = 0; i < 3; i++) { 2238 /* Write Source Address 1 (unicast filter) */ 2239 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2240 sc_if->sk_enaddr[i * 2] | 2241 sc_if->sk_enaddr[i * 2 + 1] << 8); 2242 } 2243 2244 for (i = 0; i < 3; i++) { 2245 reg = sk_win_read_2(sc_if->sk_softc, 2246 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2247 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2248 } 2249 2250 /* Set promiscuous mode */ 2251 msk_setpromisc(sc_if); 2252 2253 /* Set multicast filter */ 2254 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2255 msk_setmulti(sc_if); 2256 2257 /* enable interrupt mask for counter overflows */ 2258 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2259 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2260 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2261 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2262 2263 /* Configure RX MAC FIFO Flush Mask */ 2264 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2265 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2266 YU_RXSTAT_JABBER; 2267 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2268 2269 /* Configure RX MAC FIFO */ 2270 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2271 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2272 SK_RFCTL_FIFO_FLUSH_ON); 2273 2274 /* Increase flush threshould to 64 bytes */ 2275 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2276 SK_RFCTL_FIFO_THRESHOLD + 1); 2277 2278 /* Configure TX MAC FIFO */ 2279 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2280 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2281 2282 #if 1 2283 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2284 #endif 2285 DPRINTFN(6, ("msk_init_yukon: end\n")); 2286 } 2287 2288 /* 2289 * Note that to properly initialize any part of the GEnesis chip, 2290 * you first have to take it out of reset mode. 2291 */ 2292 int 2293 msk_init(struct ifnet *ifp) 2294 { 2295 struct sk_if_softc *sc_if = ifp->if_softc; 2296 struct sk_softc *sc = sc_if->sk_softc; 2297 int rc = 0, s; 2298 uint32_t imr, imtimer_ticks; 2299 2300 2301 DPRINTFN(2, ("msk_init\n")); 2302 2303 s = splnet(); 2304 2305 /* Cancel pending I/O and free all RX/TX buffers. */ 2306 msk_stop(ifp, 0); 2307 2308 /* Configure I2C registers */ 2309 2310 /* Configure XMAC(s) */ 2311 msk_init_yukon(sc_if); 2312 if ((rc = ether_mediachange(ifp)) != 0) 2313 goto out; 2314 2315 /* Configure transmit arbiter(s) */ 2316 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2317 #if 0 2318 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2319 #endif 2320 2321 /* Configure RAMbuffers */ 2322 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2323 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2324 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2325 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2326 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2327 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2328 2329 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2330 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2331 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2332 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2333 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2334 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2335 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2336 2337 /* Configure BMUs */ 2338 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2339 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2341 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2342 2343 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2344 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2346 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2347 2348 /* Make sure the sync transmit queue is disabled. */ 2349 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2350 2351 /* Init descriptors */ 2352 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2353 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2354 "memory for rx buffers\n"); 2355 msk_stop(ifp, 0); 2356 splx(s); 2357 return ENOBUFS; 2358 } 2359 2360 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2361 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2362 "memory for tx buffers\n"); 2363 msk_stop(ifp, 0); 2364 splx(s); 2365 return ENOBUFS; 2366 } 2367 2368 /* Set interrupt moderation if changed via sysctl. */ 2369 switch (sc->sk_type) { 2370 case SK_YUKON_EC: 2371 case SK_YUKON_EC_U: 2372 case SK_YUKON_EX: 2373 case SK_YUKON_SUPR: 2374 case SK_YUKON_ULTRA2: 2375 case SK_YUKON_OPTIMA: 2376 case SK_YUKON_PRM: 2377 case SK_YUKON_OPTIMA2: 2378 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2379 break; 2380 case SK_YUKON_FE: 2381 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2382 break; 2383 case SK_YUKON_FE_P: 2384 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2385 break; 2386 case SK_YUKON_XL: 2387 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2388 break; 2389 default: 2390 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2391 } 2392 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2393 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2394 sk_win_write_4(sc, SK_IMTIMERINIT, 2395 SK_IM_USECS(sc->sk_int_mod)); 2396 aprint_verbose_dev(sc->sk_dev, 2397 "interrupt moderation is %d us\n", sc->sk_int_mod); 2398 } 2399 2400 /* Initialize prefetch engine. */ 2401 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2402 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2403 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2404 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2405 MSK_RX_RING_ADDR(sc_if, 0)); 2406 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2407 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2408 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2409 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2410 2411 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2412 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2413 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2414 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2415 MSK_TX_RING_ADDR(sc_if, 0)); 2416 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2417 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2418 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2419 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2420 2421 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2422 sc_if->sk_cdata.sk_rx_prod); 2423 2424 /* Configure interrupt handling */ 2425 if (sc_if->sk_port == SK_PORT_A) 2426 sc->sk_intrmask |= SK_Y2_INTRS1; 2427 else 2428 sc->sk_intrmask |= SK_Y2_INTRS2; 2429 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2430 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2431 2432 ifp->if_flags |= IFF_RUNNING; 2433 ifp->if_flags &= ~IFF_OACTIVE; 2434 2435 callout_schedule(&sc_if->sk_tick_ch, hz); 2436 2437 out: 2438 splx(s); 2439 return rc; 2440 } 2441 2442 void 2443 msk_stop(struct ifnet *ifp, int disable) 2444 { 2445 struct sk_if_softc *sc_if = ifp->if_softc; 2446 struct sk_softc *sc = sc_if->sk_softc; 2447 struct sk_txmap_entry *dma; 2448 int i; 2449 2450 DPRINTFN(2, ("msk_stop\n")); 2451 2452 callout_stop(&sc_if->sk_tick_ch); 2453 2454 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2455 2456 /* Stop transfer of Tx descriptors */ 2457 2458 /* Stop transfer of Rx descriptors */ 2459 2460 /* Turn off various components of this interface. */ 2461 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2462 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2463 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2464 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2465 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2466 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2467 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2468 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2469 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2470 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2471 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2472 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2473 2474 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2475 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2476 2477 /* Disable interrupts */ 2478 if (sc_if->sk_port == SK_PORT_A) 2479 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2480 else 2481 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2482 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2483 2484 SK_XM_READ_2(sc_if, XM_ISR); 2485 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2486 2487 /* Free RX and TX mbufs still in the queues. */ 2488 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2489 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2490 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2491 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2492 } 2493 } 2494 2495 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2496 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2497 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2498 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2499 #if 1 2500 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2501 sc_if->sk_cdata.sk_tx_map[i], link); 2502 sc_if->sk_cdata.sk_tx_map[i] = 0; 2503 #endif 2504 } 2505 } 2506 2507 #if 1 2508 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2509 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2510 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2511 free(dma, M_DEVBUF); 2512 } 2513 #endif 2514 } 2515 2516 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2517 mskc_detach, NULL); 2518 2519 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2520 msk_detach, NULL); 2521 2522 #ifdef MSK_DEBUG 2523 void 2524 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2525 { 2526 #define DESC_PRINT(X) \ 2527 if (X) \ 2528 printf("txdesc[%d]." #X "=%#x\n", \ 2529 idx, X); 2530 2531 DESC_PRINT(letoh32(le->sk_addr)); 2532 DESC_PRINT(letoh16(le->sk_len)); 2533 DESC_PRINT(le->sk_ctl); 2534 DESC_PRINT(le->sk_opcode); 2535 #undef DESC_PRINT 2536 } 2537 2538 void 2539 msk_dump_bytes(const char *data, int len) 2540 { 2541 int c, i, j; 2542 2543 for (i = 0; i < len; i += 16) { 2544 printf("%08x ", i); 2545 c = len - i; 2546 if (c > 16) c = 16; 2547 2548 for (j = 0; j < c; j++) { 2549 printf("%02x ", data[i + j] & 0xff); 2550 if ((j & 0xf) == 7 && j > 0) 2551 printf(" "); 2552 } 2553 2554 for (; j < 16; j++) 2555 printf(" "); 2556 printf(" "); 2557 2558 for (j = 0; j < c; j++) { 2559 int ch = data[i + j] & 0xff; 2560 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2561 } 2562 2563 printf("\n"); 2564 2565 if (c < 16) 2566 break; 2567 } 2568 } 2569 2570 void 2571 msk_dump_mbuf(struct mbuf *m) 2572 { 2573 int count = m->m_pkthdr.len; 2574 2575 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2576 2577 while (count > 0 && m) { 2578 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2579 m, m->m_data, m->m_len); 2580 msk_dump_bytes(mtod(m, char *), m->m_len); 2581 2582 count -= m->m_len; 2583 m = m->m_next; 2584 } 2585 } 2586 #endif 2587 2588 static int 2589 msk_sysctl_handler(SYSCTLFN_ARGS) 2590 { 2591 int error, t; 2592 struct sysctlnode node; 2593 struct sk_softc *sc; 2594 2595 node = *rnode; 2596 sc = node.sysctl_data; 2597 t = sc->sk_int_mod; 2598 node.sysctl_data = &t; 2599 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2600 if (error || newp == NULL) 2601 return error; 2602 2603 if (t < SK_IM_MIN || t > SK_IM_MAX) 2604 return EINVAL; 2605 2606 /* update the softc with sysctl-changed value, and mark 2607 for hardware update */ 2608 sc->sk_int_mod = t; 2609 sc->sk_int_mod_pending = 1; 2610 return 0; 2611 } 2612 2613 /* 2614 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2615 * set up in skc_attach() 2616 */ 2617 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2618 { 2619 int rc; 2620 const struct sysctlnode *node; 2621 2622 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2623 0, CTLTYPE_NODE, "msk", 2624 SYSCTL_DESCR("msk interface controls"), 2625 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2626 goto err; 2627 } 2628 2629 msk_root_num = node->sysctl_num; 2630 return; 2631 2632 err: 2633 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2634 } 2635
Indexes created Thu Oct 02 07:10:07 GMT 2025