if_msk.c revision 1.55.2.4
1 /* $NetBSD: if_msk.c,v 1.55.2.4 2018/09/30 01:45:50 pgoyette Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.55.2.4 2018/09/30 01:45:50 pgoyette Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 static void msk_fill_rx_tick(void *); 135 136 /* #define MSK_DEBUG 1 */ 137 #ifdef MSK_DEBUG 138 #define DPRINTF(x) if (mskdebug) printf x 139 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 140 int mskdebug = MSK_DEBUG; 141 142 void msk_dump_txdesc(struct msk_tx_desc *, int); 143 void msk_dump_mbuf(struct mbuf *); 144 void msk_dump_bytes(const char *, int); 145 #else 146 #define DPRINTF(x) 147 #define DPRINTFN(n,x) 148 #endif 149 150 static int msk_sysctl_handler(SYSCTLFN_PROTO); 151 static int msk_root_num; 152 153 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 154 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 155 156 /* supported device vendors */ 157 static const struct msk_product { 158 pci_vendor_id_t msk_vendor; 159 pci_product_id_t msk_product; 160 } msk_products[] = { 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 196 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 197 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 198 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 199 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 200 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 201 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }, 202 { 0, 0 } 203 }; 204 205 static inline u_int32_t 206 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_4(sc, reg); 209 } 210 211 static inline u_int16_t 212 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 213 { 214 return CSR_READ_2(sc, reg); 215 } 216 217 static inline u_int8_t 218 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 219 { 220 return CSR_READ_1(sc, reg); 221 } 222 223 static inline void 224 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 225 { 226 CSR_WRITE_4(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 231 { 232 CSR_WRITE_2(sc, reg, x); 233 } 234 235 static inline void 236 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 237 { 238 CSR_WRITE_1(sc, reg, x); 239 } 240 241 int 242 msk_miibus_readreg(device_t dev, int phy, int reg) 243 { 244 struct sk_if_softc *sc_if = device_private(dev); 245 u_int16_t val; 246 int i; 247 248 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 249 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 250 251 for (i = 0; i < SK_TIMEOUT; i++) { 252 DELAY(1); 253 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 254 if (val & YU_SMICR_READ_VALID) 255 break; 256 } 257 258 if (i == SK_TIMEOUT) { 259 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 260 return (0); 261 } 262 263 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 264 SK_TIMEOUT)); 265 266 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 267 268 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 269 phy, reg, val)); 270 271 return (val); 272 } 273 274 void 275 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 276 { 277 struct sk_if_softc *sc_if = device_private(dev); 278 int i; 279 280 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 281 phy, reg, val)); 282 283 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 284 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 285 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 286 287 for (i = 0; i < SK_TIMEOUT; i++) { 288 DELAY(1); 289 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 290 break; 291 } 292 293 if (i == SK_TIMEOUT) 294 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 295 } 296 297 void 298 msk_miibus_statchg(struct ifnet *ifp) 299 { 300 struct sk_if_softc *sc_if = ifp->if_softc; 301 struct mii_data *mii = &sc_if->sk_mii; 302 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 303 int gpcr; 304 305 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 306 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 307 308 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 309 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 310 /* Set speed. */ 311 gpcr |= YU_GPCR_SPEED_DIS; 312 switch (IFM_SUBTYPE(mii->mii_media_active)) { 313 case IFM_1000_SX: 314 case IFM_1000_LX: 315 case IFM_1000_CX: 316 case IFM_1000_T: 317 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 318 break; 319 case IFM_100_TX: 320 gpcr |= YU_GPCR_SPEED; 321 break; 322 } 323 324 /* Set duplex. */ 325 gpcr |= YU_GPCR_DPLX_DIS; 326 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 327 gpcr |= YU_GPCR_DUPLEX; 328 329 /* Disable flow control. */ 330 gpcr |= YU_GPCR_FCTL_DIS; 331 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 332 } 333 334 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 335 336 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 337 SK_YU_READ_2(sc_if, YUKON_GPCR))); 338 } 339 340 void 341 msk_setmulti(struct sk_if_softc *sc_if) 342 { 343 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 344 u_int32_t hashes[2] = { 0, 0 }; 345 int h; 346 struct ethercom *ec = &sc_if->sk_ethercom; 347 struct ether_multi *enm; 348 struct ether_multistep step; 349 u_int16_t reg; 350 351 /* First, zot all the existing filters. */ 352 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 356 357 358 /* Now program new ones. */ 359 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 360 reg |= YU_RCR_UFLEN; 361 allmulti: 362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 363 if ((ifp->if_flags & IFF_PROMISC) != 0) 364 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 365 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 366 hashes[0] = 0xFFFFFFFF; 367 hashes[1] = 0xFFFFFFFF; 368 } 369 } else { 370 /* First find the tail of the list. */ 371 ETHER_FIRST_MULTI(step, ec, enm); 372 while (enm != NULL) { 373 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 374 ETHER_ADDR_LEN)) { 375 ifp->if_flags |= IFF_ALLMULTI; 376 goto allmulti; 377 } 378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 379 ((1 << SK_HASH_BITS) - 1); 380 if (h < 32) 381 hashes[0] |= (1 << h); 382 else 383 hashes[1] |= (1 << (h - 32)); 384 385 ETHER_NEXT_MULTI(step, enm); 386 } 387 reg |= YU_RCR_MUFLEN; 388 } 389 390 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 395 } 396 397 void 398 msk_setpromisc(struct sk_if_softc *sc_if) 399 { 400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 401 402 if (ifp->if_flags & IFF_PROMISC) 403 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 404 YU_RCR_UFLEN | YU_RCR_MUFLEN); 405 else 406 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 407 YU_RCR_UFLEN | YU_RCR_MUFLEN); 408 } 409 410 int 411 msk_init_rx_ring(struct sk_if_softc *sc_if) 412 { 413 struct msk_chain_data *cd = &sc_if->sk_cdata; 414 struct msk_ring_data *rd = sc_if->sk_rdata; 415 struct msk_rx_desc *r; 416 int i, nexti; 417 418 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 422 if (i == (MSK_RX_RING_CNT - 1)) 423 nexti = 0; 424 else 425 nexti = i + 1; 426 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 427 } 428 429 sc_if->sk_cdata.sk_rx_prod = 0; 430 sc_if->sk_cdata.sk_rx_cons = 0; 431 sc_if->sk_cdata.sk_rx_cnt = 0; 432 433 /* Mark the first ring element to initialize the high address. */ 434 sc_if->sk_cdata.sk_rx_hiaddr = 0; 435 r = &rd->sk_rx_ring[cd->sk_rx_prod]; 436 r->sk_addr = htole32(cd->sk_rx_hiaddr); 437 r->sk_len = 0; 438 r->sk_ctl = 0; 439 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 440 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod, 441 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 442 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 443 sc_if->sk_cdata.sk_rx_cnt++; 444 445 msk_fill_rx_ring(sc_if); 446 return (0); 447 } 448 449 int 450 msk_init_tx_ring(struct sk_if_softc *sc_if) 451 { 452 struct sk_softc *sc = sc_if->sk_softc; 453 struct msk_chain_data *cd = &sc_if->sk_cdata; 454 struct msk_ring_data *rd = sc_if->sk_rdata; 455 struct msk_tx_desc *t; 456 bus_dmamap_t dmamap; 457 struct sk_txmap_entry *entry; 458 int i, nexti; 459 460 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 461 462 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 463 for (i = 0; i < MSK_TX_RING_CNT; i++) { 464 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 465 if (i == (MSK_TX_RING_CNT - 1)) 466 nexti = 0; 467 else 468 nexti = i + 1; 469 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 470 471 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 472 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 473 return (ENOBUFS); 474 475 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 476 if (!entry) { 477 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 478 return (ENOBUFS); 479 } 480 entry->dmamap = dmamap; 481 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 482 } 483 484 sc_if->sk_cdata.sk_tx_prod = 0; 485 sc_if->sk_cdata.sk_tx_cons = 0; 486 sc_if->sk_cdata.sk_tx_cnt = 0; 487 488 /* Mark the first ring element to initialize the high address. */ 489 sc_if->sk_cdata.sk_tx_hiaddr = 0; 490 t = &rd->sk_tx_ring[cd->sk_tx_prod]; 491 t->sk_addr = htole32(cd->sk_tx_hiaddr); 492 t->sk_len = 0; 493 t->sk_ctl = 0; 494 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 495 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 496 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 497 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT); 498 sc_if->sk_cdata.sk_tx_cnt++; 499 500 return (0); 501 } 502 503 int 504 msk_newbuf(struct sk_if_softc *sc_if, bus_dmamap_t dmamap) 505 { 506 struct mbuf *m_new = NULL; 507 struct sk_chain *c; 508 struct msk_rx_desc *r; 509 void *buf = NULL; 510 bus_addr_t addr; 511 512 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 513 if (m_new == NULL) 514 return (ENOBUFS); 515 516 /* Allocate the jumbo buffer */ 517 buf = msk_jalloc(sc_if); 518 if (buf == NULL) { 519 m_freem(m_new); 520 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 521 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 522 return (ENOBUFS); 523 } 524 525 /* Attach the buffer to the mbuf */ 526 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 527 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 528 529 m_adj(m_new, ETHER_ALIGN); 530 531 addr = dmamap->dm_segs[0].ds_addr + 532 ((vaddr_t)m_new->m_data - 533 (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf); 534 535 if (sc_if->sk_cdata.sk_rx_hiaddr != MSK_ADDR_HI(addr)) { 536 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 537 r = c->sk_le; 538 c->sk_mbuf = NULL; 539 r->sk_addr = htole32(MSK_ADDR_HI(addr)); 540 r->sk_len = 0; 541 r->sk_ctl = 0; 542 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN; 543 sc_if->sk_cdata.sk_rx_hiaddr = MSK_ADDR_HI(addr); 544 545 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 546 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 547 548 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 549 sc_if->sk_cdata.sk_rx_cnt++; 550 551 DPRINTFN(10, ("%s: rx ADDR64: %#x\n", 552 sc_if->sk_ethercom.ec_if.if_xname, (unsigned)MSK_ADDR_HI(addr))); 553 } 554 555 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 556 r = c->sk_le; 557 c->sk_mbuf = m_new; 558 r->sk_addr = htole32(MSK_ADDR_LO(addr)); 559 r->sk_len = htole16(SK_JLEN); 560 r->sk_ctl = 0; 561 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 562 563 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 564 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 565 566 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 567 sc_if->sk_cdata.sk_rx_cnt++; 568 569 return (0); 570 } 571 572 /* 573 * Memory management for jumbo frames. 574 */ 575 576 int 577 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 578 { 579 struct sk_softc *sc = sc_if->sk_softc; 580 char *ptr, *kva; 581 int i, state, error; 582 struct sk_jpool_entry *entry; 583 584 state = error = 0; 585 586 /* Grab a big chunk o' storage. */ 587 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 588 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 589 BUS_DMA_NOWAIT)) { 590 aprint_error(": can't alloc rx buffers"); 591 return (ENOBUFS); 592 } 593 594 state = 1; 595 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 596 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 597 BUS_DMA_NOWAIT)) { 598 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 599 error = ENOBUFS; 600 goto out; 601 } 602 603 state = 2; 604 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 605 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 606 aprint_error(": can't create dma map"); 607 error = ENOBUFS; 608 goto out; 609 } 610 611 state = 3; 612 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 613 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 614 aprint_error(": can't load dma map"); 615 error = ENOBUFS; 616 goto out; 617 } 618 619 state = 4; 620 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 621 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 622 623 LIST_INIT(&sc_if->sk_jfree_listhead); 624 LIST_INIT(&sc_if->sk_jinuse_listhead); 625 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 626 627 /* 628 * Now divide it up into 9K pieces and save the addresses 629 * in an array. 630 */ 631 ptr = sc_if->sk_cdata.sk_jumbo_buf; 632 for (i = 0; i < MSK_JSLOTS; i++) { 633 sc_if->sk_cdata.sk_jslots[i] = ptr; 634 ptr += SK_JLEN; 635 entry = malloc(sizeof(struct sk_jpool_entry), 636 M_DEVBUF, M_NOWAIT); 637 if (entry == NULL) { 638 sc_if->sk_cdata.sk_jumbo_buf = NULL; 639 aprint_error(": no memory for jumbo buffer queue!"); 640 error = ENOBUFS; 641 goto out; 642 } 643 entry->slot = i; 644 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 645 entry, jpool_entries); 646 } 647 out: 648 if (error != 0) { 649 switch (state) { 650 case 4: 651 bus_dmamap_unload(sc->sc_dmatag, 652 sc_if->sk_cdata.sk_rx_jumbo_map); 653 case 3: 654 bus_dmamap_destroy(sc->sc_dmatag, 655 sc_if->sk_cdata.sk_rx_jumbo_map); 656 case 2: 657 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 658 case 1: 659 bus_dmamem_free(sc->sc_dmatag, 660 &sc_if->sk_cdata.sk_jumbo_seg, 661 sc_if->sk_cdata.sk_jumbo_nseg); 662 break; 663 default: 664 break; 665 } 666 } 667 668 return error; 669 } 670 671 static void 672 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 673 { 674 struct sk_softc *sc = sc_if->sk_softc; 675 676 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 677 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 678 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 679 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 680 sc_if->sk_cdata.sk_jumbo_nseg); 681 } 682 683 /* 684 * Allocate a jumbo buffer. 685 */ 686 void * 687 msk_jalloc(struct sk_if_softc *sc_if) 688 { 689 struct sk_jpool_entry *entry; 690 691 mutex_enter(&sc_if->sk_jpool_mtx); 692 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 693 694 if (entry == NULL) { 695 mutex_exit(&sc_if->sk_jpool_mtx); 696 return NULL; 697 } 698 699 LIST_REMOVE(entry, jpool_entries); 700 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 701 mutex_exit(&sc_if->sk_jpool_mtx); 702 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 703 } 704 705 /* 706 * Release a jumbo buffer. 707 */ 708 void 709 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 710 { 711 struct sk_jpool_entry *entry; 712 struct sk_if_softc *sc; 713 int i; 714 715 /* Extract the softc struct pointer. */ 716 sc = (struct sk_if_softc *)arg; 717 718 if (sc == NULL) 719 panic("msk_jfree: can't find softc pointer!"); 720 721 /* calculate the slot this buffer belongs to */ 722 i = ((vaddr_t)buf 723 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 724 725 if ((i < 0) || (i >= MSK_JSLOTS)) 726 panic("msk_jfree: asked to free buffer that we don't manage!"); 727 728 mutex_enter(&sc->sk_jpool_mtx); 729 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 730 if (entry == NULL) 731 panic("msk_jfree: buffer not in use!"); 732 entry->slot = i; 733 LIST_REMOVE(entry, jpool_entries); 734 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 735 mutex_exit(&sc->sk_jpool_mtx); 736 737 if (__predict_true(m != NULL)) 738 pool_cache_put(mb_cache, m); 739 740 /* Now that we know we have a free RX buffer, refill if running out */ 741 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0 742 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 743 callout_schedule(&sc->sk_tick_rx, 0); 744 } 745 746 int 747 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 748 { 749 struct sk_if_softc *sc = ifp->if_softc; 750 int s, error; 751 752 s = splnet(); 753 754 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd)); 755 switch (cmd) { 756 case SIOCSIFFLAGS: 757 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 758 break; 759 760 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 761 case IFF_RUNNING: 762 msk_stop(ifp, 1); 763 break; 764 case IFF_UP: 765 msk_init(ifp); 766 break; 767 case IFF_UP | IFF_RUNNING: 768 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 769 msk_setpromisc(sc); 770 msk_setmulti(sc); 771 } else 772 msk_init(ifp); 773 break; 774 } 775 sc->sk_if_flags = ifp->if_flags; 776 break; 777 default: 778 error = ether_ioctl(ifp, cmd, data); 779 if (error == ENETRESET) { 780 error = 0; 781 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 782 ; 783 else if (ifp->if_flags & IFF_RUNNING) { 784 /* 785 * Multicast list has changed; set the hardware 786 * filter accordingly. 787 */ 788 msk_setmulti(sc); 789 } 790 } 791 break; 792 } 793 794 splx(s); 795 return error; 796 } 797 798 void 799 msk_update_int_mod(struct sk_softc *sc, int verbose) 800 { 801 u_int32_t imtimer_ticks; 802 803 /* 804 * Configure interrupt moderation. The moderation timer 805 * defers interrupts specified in the interrupt moderation 806 * timer mask based on the timeout specified in the interrupt 807 * moderation timer init register. Each bit in the timer 808 * register represents one tick, so to specify a timeout in 809 * microseconds, we have to multiply by the correct number of 810 * ticks-per-microsecond. 811 */ 812 switch (sc->sk_type) { 813 case SK_YUKON_EC: 814 case SK_YUKON_EC_U: 815 case SK_YUKON_EX: 816 case SK_YUKON_SUPR: 817 case SK_YUKON_ULTRA2: 818 case SK_YUKON_OPTIMA: 819 case SK_YUKON_PRM: 820 case SK_YUKON_OPTIMA2: 821 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 822 break; 823 case SK_YUKON_FE: 824 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 825 break; 826 case SK_YUKON_FE_P: 827 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 828 break; 829 case SK_YUKON_XL: 830 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 831 break; 832 default: 833 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 834 } 835 if (verbose) 836 aprint_verbose_dev(sc->sk_dev, 837 "interrupt moderation is %d us\n", sc->sk_int_mod); 838 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 839 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 840 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 841 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 842 sc->sk_int_mod_pending = 0; 843 } 844 845 static int 846 msk_lookup(const struct pci_attach_args *pa) 847 { 848 const struct msk_product *pmsk; 849 850 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 851 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 852 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 853 return 1; 854 } 855 return 0; 856 } 857 858 /* 859 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 860 * IDs against our list and return a device name if we find a match. 861 */ 862 int 863 mskc_probe(device_t parent, cfdata_t match, void *aux) 864 { 865 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 866 867 return msk_lookup(pa); 868 } 869 870 /* 871 * Force the GEnesis into reset, then bring it out of reset. 872 */ 873 void 874 mskc_reset(struct sk_softc *sc) 875 { 876 u_int32_t imtimer_ticks, reg1; 877 int reg; 878 879 DPRINTFN(2, ("mskc_reset\n")); 880 881 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 882 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 883 884 DELAY(1000); 885 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 886 DELAY(2); 887 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 888 sk_win_write_1(sc, SK_TESTCTL1, 2); 889 890 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 891 sc->sk_type >= SK_YUKON_FE_P) { 892 uint32_t our; 893 894 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 895 896 /* enable all clocks. */ 897 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 898 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 899 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 900 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 901 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 902 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 903 /* Set all bits to 0 except bits 15..12 */ 904 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 905 /* Set to default value */ 906 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 907 908 /* 909 * Disable status race, workaround for Yukon EC Ultra & 910 * Yukon EX. 911 */ 912 reg1 = sk_win_read_4(sc, SK_GPIO); 913 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS; 914 sk_win_write_4(sc, SK_GPIO, reg1); 915 sk_win_read_4(sc, SK_GPIO); 916 } 917 918 /* release PHY from PowerDown/Coma mode. */ 919 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 920 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 921 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 922 else 923 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 924 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 925 926 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 927 sk_win_write_1(sc, SK_Y2_CLKGATE, 928 SK_Y2_CLKGATE_LINK1_GATE_DIS | 929 SK_Y2_CLKGATE_LINK2_GATE_DIS | 930 SK_Y2_CLKGATE_LINK1_CORE_DIS | 931 SK_Y2_CLKGATE_LINK2_CORE_DIS | 932 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 933 else 934 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 935 936 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 937 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 938 DELAY(1000); 939 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 940 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 941 942 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 943 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 944 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 945 } 946 947 sk_win_write_1(sc, SK_TESTCTL1, 1); 948 949 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 950 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 951 CSR_READ_2(sc, SK_LINK_CTRL))); 952 953 /* Disable ASF */ 954 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 955 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 956 957 /* Clear I2C IRQ noise */ 958 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 959 960 /* Disable hardware timer */ 961 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 962 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 963 964 /* Disable descriptor polling */ 965 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 966 967 /* Disable time stamps */ 968 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 969 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 970 971 /* Enable RAM interface */ 972 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 973 for (reg = SK_TO0;reg <= SK_TO11; reg++) 974 sk_win_write_1(sc, reg, 36); 975 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 976 for (reg = SK_TO0;reg <= SK_TO11; reg++) 977 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 978 979 /* 980 * Configure interrupt moderation. The moderation timer 981 * defers interrupts specified in the interrupt moderation 982 * timer mask based on the timeout specified in the interrupt 983 * moderation timer init register. Each bit in the timer 984 * register represents one tick, so to specify a timeout in 985 * microseconds, we have to multiply by the correct number of 986 * ticks-per-microsecond. 987 */ 988 switch (sc->sk_type) { 989 case SK_YUKON_EC: 990 case SK_YUKON_EC_U: 991 case SK_YUKON_EX: 992 case SK_YUKON_SUPR: 993 case SK_YUKON_ULTRA2: 994 case SK_YUKON_OPTIMA: 995 case SK_YUKON_PRM: 996 case SK_YUKON_OPTIMA2: 997 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 998 break; 999 case SK_YUKON_FE: 1000 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 1001 break; 1002 case SK_YUKON_FE_P: 1003 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 1004 break; 1005 case SK_YUKON_XL: 1006 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 1007 break; 1008 default: 1009 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1010 break; 1011 } 1012 1013 /* Reset status ring. */ 1014 memset(sc->sk_status_ring, 0, 1015 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1016 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 1017 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1018 sc->sk_status_idx = 0; 1019 1020 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 1021 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 1022 1023 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 1024 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 1025 sc->sk_status_map->dm_segs[0].ds_addr); 1026 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 1027 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 1028 if (sc->sk_type == SK_YUKON_EC && 1029 sc->sk_rev == SK_YUKON_EC_REV_A1) { 1030 /* WA for dev. #4.3 */ 1031 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 1032 /* WA for dev. #4.18 */ 1033 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 1034 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 1035 } else { 1036 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 1037 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 1038 if (sc->sk_type == SK_YUKON_XL) 1039 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04); 1040 else 1041 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10); 1042 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 1043 } 1044 1045 #if 0 1046 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 1047 #endif 1048 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 1049 1050 /* Enable status unit. */ 1051 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1052 1053 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1054 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1055 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1056 1057 msk_update_int_mod(sc, 0); 1058 } 1059 1060 int 1061 msk_probe(device_t parent, cfdata_t match, void *aux) 1062 { 1063 struct skc_attach_args *sa = aux; 1064 1065 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1066 return (0); 1067 1068 switch (sa->skc_type) { 1069 case SK_YUKON_XL: 1070 case SK_YUKON_EC_U: 1071 case SK_YUKON_EX: 1072 case SK_YUKON_EC: 1073 case SK_YUKON_FE: 1074 case SK_YUKON_FE_P: 1075 case SK_YUKON_SUPR: 1076 case SK_YUKON_ULTRA2: 1077 case SK_YUKON_OPTIMA: 1078 case SK_YUKON_PRM: 1079 case SK_YUKON_OPTIMA2: 1080 return (1); 1081 } 1082 1083 return (0); 1084 } 1085 1086 void 1087 msk_reset(struct sk_if_softc *sc_if) 1088 { 1089 /* GMAC and GPHY Reset */ 1090 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1091 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1092 DELAY(1000); 1093 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1094 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1095 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1096 } 1097 1098 static bool 1099 msk_resume(device_t dv, const pmf_qual_t *qual) 1100 { 1101 struct sk_if_softc *sc_if = device_private(dv); 1102 1103 msk_init_yukon(sc_if); 1104 return true; 1105 } 1106 1107 /* 1108 * Each XMAC chip is attached as a separate logical IP interface. 1109 * Single port cards will have only one logical interface of course. 1110 */ 1111 void 1112 msk_attach(device_t parent, device_t self, void *aux) 1113 { 1114 struct sk_if_softc *sc_if = device_private(self); 1115 struct sk_softc *sc = device_private(parent); 1116 struct skc_attach_args *sa = aux; 1117 struct ifnet *ifp; 1118 void *kva; 1119 int i; 1120 u_int32_t chunk; 1121 int mii_flags; 1122 1123 sc_if->sk_dev = self; 1124 sc_if->sk_port = sa->skc_port; 1125 sc_if->sk_softc = sc; 1126 sc->sk_if[sa->skc_port] = sc_if; 1127 1128 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1129 1130 /* 1131 * Get station address for this interface. Note that 1132 * dual port cards actually come with three station 1133 * addresses: one for each port, plus an extra. The 1134 * extra one is used by the SysKonnect driver software 1135 * as a 'virtual' station address for when both ports 1136 * are operating in failover mode. Currently we don't 1137 * use this extra address. 1138 */ 1139 for (i = 0; i < ETHER_ADDR_LEN; i++) 1140 sc_if->sk_enaddr[i] = 1141 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1142 1143 aprint_normal(": Ethernet address %s\n", 1144 ether_sprintf(sc_if->sk_enaddr)); 1145 1146 /* 1147 * Set up RAM buffer addresses. The Yukon2 has a small amount 1148 * of SRAM on it, somewhere between 4K and 48K. We need to 1149 * divide this up between the transmitter and receiver. We 1150 * give the receiver 2/3 of the memory (rounded down), and the 1151 * transmitter whatever remains. 1152 */ 1153 if (sc->sk_ramsize) { 1154 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1155 sc_if->sk_rx_ramstart = 0; 1156 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1157 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1158 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1159 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1160 1161 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1162 " tx_ramstart=%#x tx_ramend=%#x\n", 1163 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1164 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1165 } 1166 1167 /* Allocate the descriptor queues. */ 1168 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1169 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1170 BUS_DMA_NOWAIT)) { 1171 aprint_error(": can't alloc rx buffers\n"); 1172 goto fail; 1173 } 1174 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1175 sc_if->sk_ring_nseg, 1176 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1177 aprint_error(": can't map dma buffers (%zu bytes)\n", 1178 sizeof(struct msk_ring_data)); 1179 goto fail_1; 1180 } 1181 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1182 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1183 &sc_if->sk_ring_map)) { 1184 aprint_error(": can't create dma map\n"); 1185 goto fail_2; 1186 } 1187 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1188 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1189 aprint_error(": can't load dma map\n"); 1190 goto fail_3; 1191 } 1192 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1193 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1194 1195 if (sc->sk_type != SK_YUKON_FE && 1196 sc->sk_type != SK_YUKON_FE_P) 1197 sc_if->sk_pktlen = SK_JLEN; 1198 else 1199 sc_if->sk_pktlen = MCLBYTES; 1200 1201 /* Try to allocate memory for jumbo buffers. */ 1202 if (msk_alloc_jumbo_mem(sc_if)) { 1203 aprint_error(": jumbo buffer allocation failed\n"); 1204 goto fail_3; 1205 } 1206 1207 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1208 if (sc->sk_type != SK_YUKON_FE && 1209 sc->sk_type != SK_YUKON_FE_P) 1210 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1211 1212 ifp = &sc_if->sk_ethercom.ec_if; 1213 ifp->if_softc = sc_if; 1214 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1215 ifp->if_ioctl = msk_ioctl; 1216 ifp->if_start = msk_start; 1217 ifp->if_stop = msk_stop; 1218 ifp->if_init = msk_init; 1219 ifp->if_watchdog = msk_watchdog; 1220 ifp->if_baudrate = 1000000000; 1221 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1222 IFQ_SET_READY(&ifp->if_snd); 1223 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1224 1225 msk_reset(sc_if); 1226 1227 /* 1228 * Do miibus setup. 1229 */ 1230 msk_init_yukon(sc_if); 1231 1232 DPRINTFN(2, ("msk_attach: 1\n")); 1233 1234 sc_if->sk_mii.mii_ifp = ifp; 1235 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1236 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1237 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1238 1239 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1240 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1241 ether_mediachange, ether_mediastatus); 1242 mii_flags = MIIF_DOPAUSE; 1243 if (sc->sk_fibertype) 1244 mii_flags |= MIIF_HAVEFIBER; 1245 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1246 MII_OFFSET_ANY, mii_flags); 1247 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1248 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1249 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1250 0, NULL); 1251 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1252 } else 1253 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1254 1255 callout_init(&sc_if->sk_tick_ch, 0); 1256 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1257 callout_schedule(&sc_if->sk_tick_ch, hz); 1258 1259 callout_init(&sc_if->sk_tick_rx, 0); 1260 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if); 1261 1262 /* 1263 * Call MI attach routines. 1264 */ 1265 if_attach(ifp); 1266 if_deferred_start_init(ifp, NULL); 1267 ether_ifattach(ifp, sc_if->sk_enaddr); 1268 1269 if (pmf_device_register(self, NULL, msk_resume)) 1270 pmf_class_network_register(self, ifp); 1271 else 1272 aprint_error_dev(self, "couldn't establish power handler\n"); 1273 1274 if (sc->rnd_attached++ == 0) { 1275 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1276 RND_TYPE_NET, RND_FLAG_DEFAULT); 1277 } 1278 1279 DPRINTFN(2, ("msk_attach: end\n")); 1280 return; 1281 1282 fail_3: 1283 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1284 fail_2: 1285 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1286 fail_1: 1287 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1288 fail: 1289 sc->sk_if[sa->skc_port] = NULL; 1290 } 1291 1292 int 1293 msk_detach(device_t self, int flags) 1294 { 1295 struct sk_if_softc *sc_if = device_private(self); 1296 struct sk_softc *sc = sc_if->sk_softc; 1297 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1298 1299 if (sc->sk_if[sc_if->sk_port] == NULL) 1300 return (0); 1301 1302 msk_stop(ifp, 0); 1303 1304 if (--sc->rnd_attached == 0) 1305 rnd_detach_source(&sc->rnd_source); 1306 1307 callout_halt(&sc_if->sk_tick_ch, NULL); 1308 callout_destroy(&sc_if->sk_tick_ch); 1309 1310 callout_halt(&sc_if->sk_tick_rx, NULL); 1311 callout_destroy(&sc_if->sk_tick_rx); 1312 1313 /* Detach any PHYs we might have. */ 1314 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1315 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1316 1317 /* Delete any remaining media. */ 1318 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1319 1320 pmf_device_deregister(self); 1321 1322 ether_ifdetach(ifp); 1323 if_detach(ifp); 1324 1325 msk_free_jumbo_mem(sc_if); 1326 1327 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1328 sizeof(struct msk_ring_data)); 1329 bus_dmamem_free(sc->sc_dmatag, 1330 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1331 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1332 sc->sk_if[sc_if->sk_port] = NULL; 1333 1334 return (0); 1335 } 1336 1337 int 1338 mskcprint(void *aux, const char *pnp) 1339 { 1340 struct skc_attach_args *sa = aux; 1341 1342 if (pnp) 1343 aprint_normal("msk port %c at %s", 1344 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1345 else 1346 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1347 return (UNCONF); 1348 } 1349 1350 /* 1351 * Attach the interface. Allocate softc structures, do ifmedia 1352 * setup and ethernet/BPF attach. 1353 */ 1354 void 1355 mskc_attach(device_t parent, device_t self, void *aux) 1356 { 1357 struct sk_softc *sc = device_private(self); 1358 struct pci_attach_args *pa = aux; 1359 struct skc_attach_args skca; 1360 pci_chipset_tag_t pc = pa->pa_pc; 1361 pcireg_t command, memtype; 1362 pci_intr_handle_t ih; 1363 const char *intrstr = NULL; 1364 int rc, sk_nodenum; 1365 u_int8_t hw, pmd; 1366 const char *revstr = NULL; 1367 const struct sysctlnode *node; 1368 void *kva; 1369 char intrbuf[PCI_INTRSTR_LEN]; 1370 1371 DPRINTFN(2, ("begin mskc_attach\n")); 1372 1373 sc->sk_dev = self; 1374 /* 1375 * Handle power management nonsense. 1376 */ 1377 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1378 1379 if (command == 0x01) { 1380 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1381 if (command & SK_PSTATE_MASK) { 1382 u_int32_t iobase, membase, irq; 1383 1384 /* Save important PCI config data. */ 1385 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1386 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1387 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1388 1389 /* Reset the power state. */ 1390 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1391 "mode -- setting to D0\n", 1392 command & SK_PSTATE_MASK); 1393 command &= 0xFFFFFFFC; 1394 pci_conf_write(pc, pa->pa_tag, 1395 SK_PCI_PWRMGMTCTRL, command); 1396 1397 /* Restore PCI config data. */ 1398 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1399 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1400 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1401 } 1402 } 1403 1404 /* 1405 * Map control/status registers. 1406 */ 1407 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1408 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1409 &sc->sk_bhandle, NULL, &sc->sk_bsize)) { 1410 aprint_error(": can't map mem space\n"); 1411 return; 1412 } 1413 1414 if (pci_dma64_available(pa)) 1415 sc->sc_dmatag = pa->pa_dmat64; 1416 else 1417 sc->sc_dmatag = pa->pa_dmat; 1418 1419 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1420 command |= PCI_COMMAND_MASTER_ENABLE; 1421 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1422 1423 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1424 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1425 1426 /* bail out here if chip is not recognized */ 1427 if (!(SK_IS_YUKON2(sc))) { 1428 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1429 goto fail_1; 1430 } 1431 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1432 1433 /* Allocate interrupt */ 1434 if (pci_intr_map(pa, &ih)) { 1435 aprint_error(": couldn't map interrupt\n"); 1436 goto fail_1; 1437 } 1438 1439 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1440 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, msk_intr, 1441 sc, device_xname(sc->sk_dev)); 1442 if (sc->sk_intrhand == NULL) { 1443 aprint_error(": couldn't establish interrupt"); 1444 if (intrstr != NULL) 1445 aprint_error(" at %s", intrstr); 1446 aprint_error("\n"); 1447 goto fail_1; 1448 } 1449 sc->sk_pc = pc; 1450 1451 if (bus_dmamem_alloc(sc->sc_dmatag, 1452 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1453 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1454 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1455 aprint_error(": can't alloc status buffers\n"); 1456 goto fail_2; 1457 } 1458 1459 if (bus_dmamem_map(sc->sc_dmatag, 1460 &sc->sk_status_seg, sc->sk_status_nseg, 1461 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1462 &kva, BUS_DMA_NOWAIT)) { 1463 aprint_error(": can't map dma buffers (%zu bytes)\n", 1464 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1465 goto fail_3; 1466 } 1467 if (bus_dmamap_create(sc->sc_dmatag, 1468 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1469 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1470 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1471 aprint_error(": can't create dma map\n"); 1472 goto fail_4; 1473 } 1474 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1475 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1476 NULL, BUS_DMA_NOWAIT)) { 1477 aprint_error(": can't load dma map\n"); 1478 goto fail_5; 1479 } 1480 sc->sk_status_ring = (struct msk_status_desc *)kva; 1481 1482 sc->sk_int_mod = SK_IM_DEFAULT; 1483 sc->sk_int_mod_pending = 0; 1484 1485 /* Reset the adapter. */ 1486 mskc_reset(sc); 1487 1488 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1489 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1490 1491 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1492 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1493 sc->sk_fibertype = 1; 1494 1495 switch (sc->sk_type) { 1496 case SK_YUKON_XL: 1497 sc->sk_name = "Yukon-2 XL"; 1498 break; 1499 case SK_YUKON_EC_U: 1500 sc->sk_name = "Yukon-2 EC Ultra"; 1501 break; 1502 case SK_YUKON_EX: 1503 sc->sk_name = "Yukon-2 Extreme"; 1504 break; 1505 case SK_YUKON_EC: 1506 sc->sk_name = "Yukon-2 EC"; 1507 break; 1508 case SK_YUKON_FE: 1509 sc->sk_name = "Yukon-2 FE"; 1510 break; 1511 case SK_YUKON_FE_P: 1512 sc->sk_name = "Yukon-2 FE+"; 1513 break; 1514 case SK_YUKON_SUPR: 1515 sc->sk_name = "Yukon-2 Supreme"; 1516 break; 1517 case SK_YUKON_ULTRA2: 1518 sc->sk_name = "Yukon-2 Ultra 2"; 1519 break; 1520 case SK_YUKON_OPTIMA: 1521 sc->sk_name = "Yukon-2 Optima"; 1522 break; 1523 case SK_YUKON_PRM: 1524 sc->sk_name = "Yukon-2 Optima Prime"; 1525 break; 1526 case SK_YUKON_OPTIMA2: 1527 sc->sk_name = "Yukon-2 Optima 2"; 1528 break; 1529 default: 1530 sc->sk_name = "Yukon (Unknown)"; 1531 } 1532 1533 if (sc->sk_type == SK_YUKON_XL) { 1534 switch (sc->sk_rev) { 1535 case SK_YUKON_XL_REV_A0: 1536 revstr = "A0"; 1537 break; 1538 case SK_YUKON_XL_REV_A1: 1539 revstr = "A1"; 1540 break; 1541 case SK_YUKON_XL_REV_A2: 1542 revstr = "A2"; 1543 break; 1544 case SK_YUKON_XL_REV_A3: 1545 revstr = "A3"; 1546 break; 1547 default: 1548 break; 1549 } 1550 } 1551 1552 if (sc->sk_type == SK_YUKON_EC) { 1553 switch (sc->sk_rev) { 1554 case SK_YUKON_EC_REV_A1: 1555 revstr = "A1"; 1556 break; 1557 case SK_YUKON_EC_REV_A2: 1558 revstr = "A2"; 1559 break; 1560 case SK_YUKON_EC_REV_A3: 1561 revstr = "A3"; 1562 break; 1563 default: 1564 break; 1565 } 1566 } 1567 1568 if (sc->sk_type == SK_YUKON_FE) { 1569 switch (sc->sk_rev) { 1570 case SK_YUKON_FE_REV_A1: 1571 revstr = "A1"; 1572 break; 1573 case SK_YUKON_FE_REV_A2: 1574 revstr = "A2"; 1575 break; 1576 default: 1577 break; 1578 } 1579 } 1580 1581 if (sc->sk_type == SK_YUKON_EC_U) { 1582 switch (sc->sk_rev) { 1583 case SK_YUKON_EC_U_REV_A0: 1584 revstr = "A0"; 1585 break; 1586 case SK_YUKON_EC_U_REV_A1: 1587 revstr = "A1"; 1588 break; 1589 case SK_YUKON_EC_U_REV_B0: 1590 revstr = "B0"; 1591 break; 1592 case SK_YUKON_EC_U_REV_B1: 1593 revstr = "B1"; 1594 break; 1595 default: 1596 break; 1597 } 1598 } 1599 1600 if (sc->sk_type == SK_YUKON_FE) { 1601 switch (sc->sk_rev) { 1602 case SK_YUKON_FE_REV_A1: 1603 revstr = "A1"; 1604 break; 1605 case SK_YUKON_FE_REV_A2: 1606 revstr = "A2"; 1607 break; 1608 default: 1609 ; 1610 } 1611 } 1612 1613 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1614 revstr = "A0"; 1615 1616 if (sc->sk_type == SK_YUKON_EX) { 1617 switch (sc->sk_rev) { 1618 case SK_YUKON_EX_REV_A0: 1619 revstr = "A0"; 1620 break; 1621 case SK_YUKON_EX_REV_B0: 1622 revstr = "B0"; 1623 break; 1624 default: 1625 ; 1626 } 1627 } 1628 1629 if (sc->sk_type == SK_YUKON_SUPR) { 1630 switch (sc->sk_rev) { 1631 case SK_YUKON_SUPR_REV_A0: 1632 revstr = "A0"; 1633 break; 1634 case SK_YUKON_SUPR_REV_B0: 1635 revstr = "B0"; 1636 break; 1637 case SK_YUKON_SUPR_REV_B1: 1638 revstr = "B1"; 1639 break; 1640 default: 1641 ; 1642 } 1643 } 1644 1645 if (sc->sk_type == SK_YUKON_PRM) { 1646 switch (sc->sk_rev) { 1647 case SK_YUKON_PRM_REV_Z1: 1648 revstr = "Z1"; 1649 break; 1650 case SK_YUKON_PRM_REV_A0: 1651 revstr = "A0"; 1652 break; 1653 default: 1654 ; 1655 } 1656 } 1657 1658 /* Announce the product name. */ 1659 aprint_normal(", %s", sc->sk_name); 1660 if (revstr != NULL) 1661 aprint_normal(" rev. %s", revstr); 1662 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1663 1664 sc->sk_macs = 1; 1665 1666 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1667 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1668 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1669 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1670 sc->sk_macs++; 1671 } 1672 1673 skca.skc_port = SK_PORT_A; 1674 skca.skc_type = sc->sk_type; 1675 skca.skc_rev = sc->sk_rev; 1676 (void)config_found(sc->sk_dev, &skca, mskcprint); 1677 1678 if (sc->sk_macs > 1) { 1679 skca.skc_port = SK_PORT_B; 1680 skca.skc_type = sc->sk_type; 1681 skca.skc_rev = sc->sk_rev; 1682 (void)config_found(sc->sk_dev, &skca, mskcprint); 1683 } 1684 1685 /* Turn on the 'driver is loaded' LED. */ 1686 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1687 1688 /* skc sysctl setup */ 1689 1690 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1691 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1692 SYSCTL_DESCR("mskc per-controller controls"), 1693 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1694 CTL_EOL)) != 0) { 1695 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1696 goto fail_6; 1697 } 1698 1699 sk_nodenum = node->sysctl_num; 1700 1701 /* interrupt moderation time in usecs */ 1702 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1703 CTLFLAG_READWRITE, 1704 CTLTYPE_INT, "int_mod", 1705 SYSCTL_DESCR("msk interrupt moderation timer"), 1706 msk_sysctl_handler, 0, (void *)sc, 1707 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1708 CTL_EOL)) != 0) { 1709 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1710 goto fail_6; 1711 } 1712 1713 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1714 aprint_error_dev(self, "couldn't establish power handler\n"); 1715 1716 return; 1717 1718 fail_6: 1719 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1720 fail_4: 1721 bus_dmamem_unmap(sc->sc_dmatag, kva, 1722 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1723 fail_3: 1724 bus_dmamem_free(sc->sc_dmatag, 1725 &sc->sk_status_seg, sc->sk_status_nseg); 1726 sc->sk_status_nseg = 0; 1727 fail_5: 1728 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1729 fail_2: 1730 pci_intr_disestablish(pc, sc->sk_intrhand); 1731 sc->sk_intrhand = NULL; 1732 fail_1: 1733 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1734 sc->sk_bsize = 0; 1735 } 1736 1737 int 1738 mskc_detach(device_t self, int flags) 1739 { 1740 struct sk_softc *sc = device_private(self); 1741 int rv; 1742 1743 if (sc->sk_intrhand) { 1744 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1745 sc->sk_intrhand = NULL; 1746 } 1747 1748 rv = config_detach_children(self, flags); 1749 if (rv != 0) 1750 return (rv); 1751 1752 if (sc->sk_status_nseg > 0) { 1753 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1754 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1755 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1756 bus_dmamem_free(sc->sc_dmatag, 1757 &sc->sk_status_seg, sc->sk_status_nseg); 1758 } 1759 1760 if (sc->sk_bsize > 0) 1761 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1762 1763 return(0); 1764 } 1765 1766 int 1767 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1768 { 1769 struct sk_softc *sc = sc_if->sk_softc; 1770 struct msk_tx_desc *f = NULL; 1771 u_int32_t frag, cur, hiaddr, old_hiaddr, total; 1772 u_int32_t entries = 0; 1773 size_t i; 1774 struct sk_txmap_entry *entry; 1775 bus_dmamap_t txmap; 1776 bus_addr_t addr; 1777 1778 DPRINTFN(2, ("msk_encap\n")); 1779 1780 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1781 if (entry == NULL) { 1782 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1783 return (ENOBUFS); 1784 } 1785 txmap = entry->dmamap; 1786 1787 cur = frag = *txidx; 1788 1789 #ifdef MSK_DEBUG 1790 if (mskdebug >= 2) 1791 msk_dump_mbuf(m_head); 1792 #endif 1793 1794 /* 1795 * Start packing the mbufs in this chain into 1796 * the fragment pointers. Stop when we run out 1797 * of fragments or hit the end of the mbuf chain. 1798 */ 1799 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1800 BUS_DMA_NOWAIT)) { 1801 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1802 return (ENOBUFS); 1803 } 1804 1805 /* Count how many tx descriptors needed. */ 1806 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1807 for (total = i = 0; i < txmap->dm_nsegs; i++) { 1808 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) { 1809 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr); 1810 total++; 1811 } 1812 total++; 1813 } 1814 1815 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) { 1816 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1817 bus_dmamap_unload(sc->sc_dmatag, txmap); 1818 return (ENOBUFS); 1819 } 1820 1821 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n", 1822 txmap->dm_nsegs, total)); 1823 1824 /* Sync the DMA map. */ 1825 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1826 BUS_DMASYNC_PREWRITE); 1827 1828 old_hiaddr = sc_if->sk_cdata.sk_tx_hiaddr; 1829 for (i = 0; i < txmap->dm_nsegs; i++) { 1830 addr = txmap->dm_segs[i].ds_addr; 1831 DPRINTFN(2, ("msk_encap: addr %llx\n", 1832 (unsigned long long)addr)); 1833 hiaddr = MSK_ADDR_HI(addr); 1834 1835 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) { 1836 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1837 f->sk_addr = htole32(hiaddr); 1838 f->sk_len = 0; 1839 f->sk_ctl = 0; 1840 if (i == 0) 1841 f->sk_opcode = SK_Y2_BMUOPC_ADDR64; 1842 else 1843 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN; 1844 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr; 1845 SK_INC(frag, MSK_TX_RING_CNT); 1846 entries++; 1847 DPRINTFN(10, ("%s: tx ADDR64: %#x\n", 1848 sc_if->sk_ethercom.ec_if.if_xname, hiaddr)); 1849 } 1850 1851 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1852 f->sk_addr = htole32(MSK_ADDR_LO(addr)); 1853 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1854 f->sk_ctl = 0; 1855 if (i == 0) { 1856 if (hiaddr != old_hiaddr) 1857 f->sk_opcode = SK_Y2_TXOPC_PACKET | SK_Y2_TXOPC_OWN; 1858 else 1859 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1860 } else 1861 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1862 cur = frag; 1863 SK_INC(frag, MSK_TX_RING_CNT); 1864 entries++; 1865 } 1866 KASSERTMSG(entries == total, "entries %u total %u", entries, total); 1867 1868 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1869 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1870 1871 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1872 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1873 1874 /* Sync descriptors before handing to chip */ 1875 MSK_CDTXSYNC(sc_if, *txidx, entries, 1876 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1877 1878 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1879 1880 /* Sync first descriptor to hand it off */ 1881 MSK_CDTXSYNC(sc_if, *txidx, 1, 1882 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1883 1884 sc_if->sk_cdata.sk_tx_cnt += entries; 1885 1886 #ifdef MSK_DEBUG 1887 if (mskdebug >= 2) { 1888 struct msk_tx_desc *le; 1889 u_int32_t idx; 1890 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1891 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1892 msk_dump_txdesc(le, idx); 1893 } 1894 } 1895 #endif 1896 1897 *txidx = frag; 1898 1899 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1900 1901 return (0); 1902 } 1903 1904 void 1905 msk_start(struct ifnet *ifp) 1906 { 1907 struct sk_if_softc *sc_if = ifp->if_softc; 1908 struct mbuf *m_head = NULL; 1909 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1910 int pkts = 0; 1911 1912 DPRINTFN(2, ("msk_start\n")); 1913 1914 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1915 IFQ_POLL(&ifp->if_snd, m_head); 1916 if (m_head == NULL) 1917 break; 1918 1919 /* 1920 * Pack the data into the transmit ring. If we 1921 * don't have room, set the OACTIVE flag and wait 1922 * for the NIC to drain the ring. 1923 */ 1924 if (msk_encap(sc_if, m_head, &idx)) { 1925 ifp->if_flags |= IFF_OACTIVE; 1926 break; 1927 } 1928 1929 /* now we are committed to transmit the packet */ 1930 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1931 pkts++; 1932 1933 /* 1934 * If there's a BPF listener, bounce a copy of this frame 1935 * to him. 1936 */ 1937 bpf_mtap(ifp, m_head, BPF_D_OUT); 1938 } 1939 if (pkts == 0) 1940 return; 1941 1942 /* Transmit */ 1943 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1944 sc_if->sk_cdata.sk_tx_prod = idx; 1945 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1946 1947 /* Set a timeout in case the chip goes out to lunch. */ 1948 ifp->if_timer = 5; 1949 } 1950 } 1951 1952 void 1953 msk_watchdog(struct ifnet *ifp) 1954 { 1955 struct sk_if_softc *sc_if = ifp->if_softc; 1956 1957 /* 1958 * Reclaim first as there is a possibility of losing Tx completion 1959 * interrupts. 1960 */ 1961 msk_txeof(sc_if); 1962 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1963 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1964 1965 ifp->if_oerrors++; 1966 1967 /* XXX Resets both ports; we shouldn't do that. */ 1968 mskc_reset(sc_if->sk_softc); 1969 msk_reset(sc_if); 1970 msk_init(ifp); 1971 } 1972 } 1973 1974 static bool 1975 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1976 { 1977 struct sk_softc *sc = device_private(dv); 1978 1979 DPRINTFN(2, ("mskc_suspend\n")); 1980 1981 /* Turn off the 'driver is loaded' LED. */ 1982 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1983 1984 return true; 1985 } 1986 1987 static bool 1988 mskc_resume(device_t dv, const pmf_qual_t *qual) 1989 { 1990 struct sk_softc *sc = device_private(dv); 1991 1992 DPRINTFN(2, ("mskc_resume\n")); 1993 1994 mskc_reset(sc); 1995 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1996 1997 return true; 1998 } 1999 2000 static __inline int 2001 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 2002 { 2003 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2004 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2005 YU_RXSTAT_JABBER)) != 0 || 2006 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2007 YU_RXSTAT_BYTES(stat) != len) 2008 return (0); 2009 2010 return (1); 2011 } 2012 2013 void 2014 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 2015 { 2016 struct sk_softc *sc = sc_if->sk_softc; 2017 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2018 struct mbuf *m; 2019 unsigned cur, prod, tail, total_len = len; 2020 bus_dmamap_t dmamap; 2021 2022 cur = sc_if->sk_cdata.sk_rx_cons; 2023 prod = sc_if->sk_cdata.sk_rx_prod; 2024 2025 /* Sync the descriptor */ 2026 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2027 2028 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod, sc_if->sk_cdata.sk_rx_cnt)); 2029 2030 while (prod != cur) { 2031 tail = cur; 2032 SK_INC(cur, MSK_RX_RING_CNT); 2033 2034 sc_if->sk_cdata.sk_rx_cnt--; 2035 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf; 2036 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL; 2037 if (m != NULL) 2038 break; /* found it */ 2039 } 2040 sc_if->sk_cdata.sk_rx_cons = cur; 2041 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur, sc_if->sk_cdata.sk_rx_cnt, m)); 2042 2043 if (m == NULL) 2044 return; 2045 2046 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2047 2048 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2049 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2050 2051 if (total_len < SK_MIN_FRAMELEN || 2052 total_len > ETHER_MAX_LEN_JUMBO || 2053 msk_rxvalid(sc, rxstat, total_len) == 0) { 2054 ifp->if_ierrors++; 2055 m_freem(m); 2056 return; 2057 } 2058 2059 m_set_rcvif(m, ifp); 2060 m->m_pkthdr.len = m->m_len = total_len; 2061 2062 /* pass it on. */ 2063 if_percpuq_enqueue(ifp->if_percpuq, m); 2064 } 2065 2066 void 2067 msk_txeof(struct sk_if_softc *sc_if) 2068 { 2069 struct sk_softc *sc = sc_if->sk_softc; 2070 struct msk_tx_desc *cur_tx; 2071 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2072 u_int32_t idx, reg, sk_ctl; 2073 struct sk_txmap_entry *entry; 2074 2075 DPRINTFN(2, ("msk_txeof\n")); 2076 2077 if (sc_if->sk_port == SK_PORT_A) 2078 reg = SK_STAT_BMU_TXA1_RIDX; 2079 else 2080 reg = SK_STAT_BMU_TXA2_RIDX; 2081 2082 /* 2083 * Go through our tx ring and free mbufs for those 2084 * frames that have been sent. 2085 */ 2086 idx = sc_if->sk_cdata.sk_tx_cons; 2087 while (idx != sk_win_read_2(sc, reg)) { 2088 MSK_CDTXSYNC(sc_if, idx, 1, 2089 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2090 2091 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2092 sk_ctl = cur_tx->sk_ctl; 2093 #ifdef MSK_DEBUG 2094 if (mskdebug >= 2) 2095 msk_dump_txdesc(cur_tx, idx); 2096 #endif 2097 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2098 ifp->if_opackets++; 2099 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2100 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2101 2102 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2103 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2104 2105 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2106 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2107 2108 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2109 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2110 link); 2111 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2112 } 2113 sc_if->sk_cdata.sk_tx_cnt--; 2114 SK_INC(idx, MSK_TX_RING_CNT); 2115 } 2116 if (idx == sc_if->sk_cdata.sk_tx_cons) 2117 return; 2118 2119 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2120 2121 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2122 ifp->if_flags &= ~IFF_OACTIVE; 2123 2124 sc_if->sk_cdata.sk_tx_cons = idx; 2125 } 2126 2127 void 2128 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2129 { 2130 /* Make sure to not completely wrap around */ 2131 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2132 if (msk_newbuf(sc_if, 2133 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2134 goto schedretry; 2135 } 2136 } 2137 2138 return; 2139 2140 schedretry: 2141 /* Try later */ 2142 callout_schedule(&sc_if->sk_tick_rx, hz/2); 2143 } 2144 2145 static void 2146 msk_fill_rx_tick(void *xsc_if) 2147 { 2148 struct sk_if_softc *sc_if = xsc_if; 2149 int s, rx_prod; 2150 2151 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */ 2152 2153 s = splnet(); 2154 rx_prod = sc_if->sk_cdata.sk_rx_prod; 2155 msk_fill_rx_ring(sc_if); 2156 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) { 2157 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2158 sc_if->sk_cdata.sk_rx_prod); 2159 } 2160 splx(s); 2161 } 2162 2163 void 2164 msk_tick(void *xsc_if) 2165 { 2166 struct sk_if_softc *sc_if = xsc_if; 2167 struct mii_data *mii = &sc_if->sk_mii; 2168 int s; 2169 2170 s = splnet(); 2171 mii_tick(mii); 2172 splx(s); 2173 2174 callout_schedule(&sc_if->sk_tick_ch, hz); 2175 } 2176 2177 void 2178 msk_intr_yukon(struct sk_if_softc *sc_if) 2179 { 2180 u_int8_t status; 2181 2182 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2183 /* RX overrun */ 2184 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2185 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2186 SK_RFCTL_RX_FIFO_OVER); 2187 } 2188 /* TX underrun */ 2189 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2190 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2191 SK_TFCTL_TX_FIFO_UNDER); 2192 } 2193 2194 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2195 } 2196 2197 int 2198 msk_intr(void *xsc) 2199 { 2200 struct sk_softc *sc = xsc; 2201 struct sk_if_softc *sc_if; 2202 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2203 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2204 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2205 int claimed = 0; 2206 u_int32_t status; 2207 struct msk_status_desc *cur_st; 2208 2209 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2210 if (status == 0xffffffff) 2211 return (0); 2212 if (status == 0) { 2213 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2214 return (0); 2215 } 2216 2217 status = CSR_READ_4(sc, SK_ISR); 2218 2219 if (sc_if0 != NULL) 2220 ifp0 = &sc_if0->sk_ethercom.ec_if; 2221 if (sc_if1 != NULL) 2222 ifp1 = &sc_if1->sk_ethercom.ec_if; 2223 2224 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2225 (ifp0->if_flags & IFF_RUNNING)) { 2226 msk_intr_yukon(sc_if0); 2227 } 2228 2229 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2230 (ifp1->if_flags & IFF_RUNNING)) { 2231 msk_intr_yukon(sc_if1); 2232 } 2233 2234 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2235 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2236 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2237 2238 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2239 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2240 switch (cur_st->sk_opcode) { 2241 case SK_Y2_STOPC_RXSTAT: 2242 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2243 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2244 letoh32(cur_st->sk_status)); 2245 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3)) 2246 msk_fill_rx_tick(sc_if); 2247 break; 2248 case SK_Y2_STOPC_TXSTAT: 2249 if (sc_if0) 2250 msk_txeof(sc_if0); 2251 if (sc_if1) 2252 msk_txeof(sc_if1); 2253 break; 2254 default: 2255 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2256 break; 2257 } 2258 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2259 2260 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2261 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2262 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2263 } 2264 2265 if (status & SK_Y2_IMR_BMU) { 2266 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2267 claimed = 1; 2268 } 2269 2270 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2271 2272 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2273 if_schedule_deferred_start(ifp0); 2274 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2275 if_schedule_deferred_start(ifp1); 2276 2277 KASSERT(sc->rnd_attached > 0); 2278 rnd_add_uint32(&sc->rnd_source, status); 2279 2280 if (sc->sk_int_mod_pending) 2281 msk_update_int_mod(sc, 1); 2282 2283 return claimed; 2284 } 2285 2286 void 2287 msk_init_yukon(struct sk_if_softc *sc_if) 2288 { 2289 u_int32_t v; 2290 u_int16_t reg; 2291 struct sk_softc *sc; 2292 int i; 2293 2294 sc = sc_if->sk_softc; 2295 2296 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2297 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2298 2299 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2300 2301 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2302 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2303 2304 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2305 2306 /* unused read of the interrupt source register */ 2307 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2308 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2309 2310 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2311 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2312 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2313 2314 /* MIB Counter Clear Mode set */ 2315 reg |= YU_PAR_MIB_CLR; 2316 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2317 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2318 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2319 2320 /* MIB Counter Clear Mode clear */ 2321 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2322 reg &= ~YU_PAR_MIB_CLR; 2323 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2324 2325 /* receive control reg */ 2326 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2327 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2328 2329 /* transmit control register */ 2330 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2331 2332 /* transmit flow control register */ 2333 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2334 2335 /* transmit parameter register */ 2336 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2337 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2338 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2339 2340 /* serial mode register */ 2341 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2342 reg = YU_SMR_DATA_BLIND(0x1c) | 2343 YU_SMR_MFL_VLAN | 2344 YU_SMR_IPG_DATA(0x1e); 2345 2346 if (sc->sk_type != SK_YUKON_FE && 2347 sc->sk_type != SK_YUKON_FE_P) 2348 reg |= YU_SMR_MFL_JUMBO; 2349 2350 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2351 2352 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2353 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2354 /* msk_attach calls me before ether_ifattach so check null */ 2355 if (ifp != NULL && ifp->if_sadl != NULL) 2356 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2357 sizeof(sc_if->sk_enaddr)); 2358 /* Setup Yukon's address */ 2359 for (i = 0; i < 3; i++) { 2360 /* Write Source Address 1 (unicast filter) */ 2361 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2362 sc_if->sk_enaddr[i * 2] | 2363 sc_if->sk_enaddr[i * 2 + 1] << 8); 2364 } 2365 2366 for (i = 0; i < 3; i++) { 2367 reg = sk_win_read_2(sc_if->sk_softc, 2368 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2369 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2370 } 2371 2372 /* Set promiscuous mode */ 2373 msk_setpromisc(sc_if); 2374 2375 /* Set multicast filter */ 2376 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2377 msk_setmulti(sc_if); 2378 2379 /* enable interrupt mask for counter overflows */ 2380 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2381 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2382 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2383 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2384 2385 /* Configure RX MAC FIFO Flush Mask */ 2386 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2387 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2388 YU_RXSTAT_JABBER; 2389 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2390 2391 /* Configure RX MAC FIFO */ 2392 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2393 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2394 SK_RFCTL_FIFO_FLUSH_ON); 2395 2396 /* Increase flush threshold to 64 bytes */ 2397 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2398 SK_RFCTL_FIFO_THRESHOLD + 1); 2399 2400 /* Configure TX MAC FIFO */ 2401 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2402 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2403 2404 #if 1 2405 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2406 #endif 2407 DPRINTFN(6, ("msk_init_yukon: end\n")); 2408 } 2409 2410 /* 2411 * Note that to properly initialize any part of the GEnesis chip, 2412 * you first have to take it out of reset mode. 2413 */ 2414 int 2415 msk_init(struct ifnet *ifp) 2416 { 2417 struct sk_if_softc *sc_if = ifp->if_softc; 2418 struct sk_softc *sc = sc_if->sk_softc; 2419 int rc = 0, s; 2420 uint32_t imr, imtimer_ticks; 2421 2422 2423 DPRINTFN(2, ("msk_init\n")); 2424 2425 s = splnet(); 2426 2427 /* Cancel pending I/O and free all RX/TX buffers. */ 2428 msk_stop(ifp, 1); 2429 2430 /* Configure I2C registers */ 2431 2432 /* Configure XMAC(s) */ 2433 msk_init_yukon(sc_if); 2434 if ((rc = ether_mediachange(ifp)) != 0) 2435 goto out; 2436 2437 /* Configure transmit arbiter(s) */ 2438 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2439 #if 0 2440 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2441 #endif 2442 2443 if (sc->sk_ramsize) { 2444 /* Configure RAMbuffers */ 2445 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2446 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2447 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2448 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2449 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2450 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2451 2452 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2453 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2454 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2455 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2456 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2457 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2458 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2459 } 2460 2461 /* Configure BMUs */ 2462 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2463 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2464 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2465 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2466 2467 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2468 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2469 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2470 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2471 2472 /* Make sure the sync transmit queue is disabled. */ 2473 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2474 2475 /* Init descriptors */ 2476 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2477 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2478 "memory for rx buffers\n"); 2479 msk_stop(ifp, 1); 2480 splx(s); 2481 return ENOBUFS; 2482 } 2483 2484 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2485 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2486 "memory for tx buffers\n"); 2487 msk_stop(ifp, 1); 2488 splx(s); 2489 return ENOBUFS; 2490 } 2491 2492 /* Set interrupt moderation if changed via sysctl. */ 2493 switch (sc->sk_type) { 2494 case SK_YUKON_EC: 2495 case SK_YUKON_EC_U: 2496 case SK_YUKON_EX: 2497 case SK_YUKON_SUPR: 2498 case SK_YUKON_ULTRA2: 2499 case SK_YUKON_OPTIMA: 2500 case SK_YUKON_PRM: 2501 case SK_YUKON_OPTIMA2: 2502 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2503 break; 2504 case SK_YUKON_FE: 2505 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2506 break; 2507 case SK_YUKON_FE_P: 2508 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2509 break; 2510 case SK_YUKON_XL: 2511 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2512 break; 2513 default: 2514 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2515 } 2516 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2517 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2518 sk_win_write_4(sc, SK_IMTIMERINIT, 2519 SK_IM_USECS(sc->sk_int_mod)); 2520 aprint_verbose_dev(sc->sk_dev, 2521 "interrupt moderation is %d us\n", sc->sk_int_mod); 2522 } 2523 2524 /* Initialize prefetch engine. */ 2525 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2526 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2527 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2528 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2529 MSK_RX_RING_ADDR(sc_if, 0)); 2530 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2531 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2532 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2533 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2534 2535 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2536 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2537 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2538 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2539 MSK_TX_RING_ADDR(sc_if, 0)); 2540 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2541 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2542 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2543 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2544 2545 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2546 sc_if->sk_cdata.sk_rx_prod); 2547 2548 /* Configure interrupt handling */ 2549 if (sc_if->sk_port == SK_PORT_A) 2550 sc->sk_intrmask |= SK_Y2_INTRS1; 2551 else 2552 sc->sk_intrmask |= SK_Y2_INTRS2; 2553 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2554 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2555 2556 ifp->if_flags |= IFF_RUNNING; 2557 ifp->if_flags &= ~IFF_OACTIVE; 2558 2559 callout_schedule(&sc_if->sk_tick_ch, hz); 2560 2561 out: 2562 splx(s); 2563 return rc; 2564 } 2565 2566 /* 2567 * Note: the logic of second parameter is inverted compared to OpenBSD 2568 * code, since this code uses the function as if_stop hook too. 2569 */ 2570 void 2571 msk_stop(struct ifnet *ifp, int disable) 2572 { 2573 struct sk_if_softc *sc_if = ifp->if_softc; 2574 struct sk_softc *sc = sc_if->sk_softc; 2575 struct sk_txmap_entry *dma; 2576 int i; 2577 2578 DPRINTFN(2, ("msk_stop\n")); 2579 2580 callout_stop(&sc_if->sk_tick_ch); 2581 callout_stop(&sc_if->sk_tick_rx); 2582 2583 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2584 2585 /* Stop transfer of Tx descriptors */ 2586 2587 /* Stop transfer of Rx descriptors */ 2588 2589 if (disable) { 2590 /* Turn off various components of this interface. */ 2591 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2592 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2593 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2594 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2595 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2596 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2597 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2598 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2599 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2600 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2601 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2602 2603 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2604 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2605 2606 /* Disable interrupts */ 2607 if (sc_if->sk_port == SK_PORT_A) 2608 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2609 else 2610 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2611 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2612 } 2613 2614 /* Free RX and TX mbufs still in the queues. */ 2615 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2616 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2617 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2618 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2619 } 2620 } 2621 2622 sc_if->sk_cdata.sk_rx_prod = 0; 2623 sc_if->sk_cdata.sk_rx_cons = 0; 2624 sc_if->sk_cdata.sk_rx_cnt = 0; 2625 2626 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2627 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2628 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2629 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2630 #if 1 2631 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2632 sc_if->sk_cdata.sk_tx_map[i], link); 2633 sc_if->sk_cdata.sk_tx_map[i] = 0; 2634 #endif 2635 } 2636 } 2637 2638 #if 1 2639 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2640 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2641 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2642 free(dma, M_DEVBUF); 2643 } 2644 #endif 2645 } 2646 2647 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2648 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2649 2650 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2651 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2652 2653 #ifdef MSK_DEBUG 2654 void 2655 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2656 { 2657 #define DESC_PRINT(X) \ 2658 if (X) \ 2659 printf("txdesc[%d]." #X "=%#x\n", \ 2660 idx, X); 2661 2662 DESC_PRINT(letoh32(le->sk_addr)); 2663 DESC_PRINT(letoh16(le->sk_len)); 2664 DESC_PRINT(le->sk_ctl); 2665 DESC_PRINT(le->sk_opcode); 2666 #undef DESC_PRINT 2667 } 2668 2669 void 2670 msk_dump_bytes(const char *data, int len) 2671 { 2672 int c, i, j; 2673 2674 for (i = 0; i < len; i += 16) { 2675 printf("%08x ", i); 2676 c = len - i; 2677 if (c > 16) c = 16; 2678 2679 for (j = 0; j < c; j++) { 2680 printf("%02x ", data[i + j] & 0xff); 2681 if ((j & 0xf) == 7 && j > 0) 2682 printf(" "); 2683 } 2684 2685 for (; j < 16; j++) 2686 printf(" "); 2687 printf(" "); 2688 2689 for (j = 0; j < c; j++) { 2690 int ch = data[i + j] & 0xff; 2691 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2692 } 2693 2694 printf("\n"); 2695 2696 if (c < 16) 2697 break; 2698 } 2699 } 2700 2701 void 2702 msk_dump_mbuf(struct mbuf *m) 2703 { 2704 int count = m->m_pkthdr.len; 2705 2706 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2707 2708 while (count > 0 && m) { 2709 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2710 m, m->m_data, m->m_len); 2711 if (mskdebug >= 4) 2712 msk_dump_bytes(mtod(m, char *), m->m_len); 2713 2714 count -= m->m_len; 2715 m = m->m_next; 2716 } 2717 } 2718 #endif 2719 2720 static int 2721 msk_sysctl_handler(SYSCTLFN_ARGS) 2722 { 2723 int error, t; 2724 struct sysctlnode node; 2725 struct sk_softc *sc; 2726 2727 node = *rnode; 2728 sc = node.sysctl_data; 2729 t = sc->sk_int_mod; 2730 node.sysctl_data = &t; 2731 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2732 if (error || newp == NULL) 2733 return error; 2734 2735 if (t < SK_IM_MIN || t > SK_IM_MAX) 2736 return EINVAL; 2737 2738 /* update the softc with sysctl-changed value, and mark 2739 for hardware update */ 2740 sc->sk_int_mod = t; 2741 sc->sk_int_mod_pending = 1; 2742 return 0; 2743 } 2744 2745 /* 2746 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2747 * set up in mskc_attach() 2748 */ 2749 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2750 { 2751 int rc; 2752 const struct sysctlnode *node; 2753 2754 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2755 0, CTLTYPE_NODE, "msk", 2756 SYSCTL_DESCR("msk interface controls"), 2757 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2758 goto err; 2759 } 2760 2761 msk_root_num = node->sysctl_num; 2762 return; 2763 2764 err: 2765 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2766 } 2767
Indexes created Thu Oct 02 07:10:07 GMT 2025