if_msk.c revision 1.57
1 /* $NetBSD: if_msk.c,v 1.57 2018/06/11 19:13:38 jdolecek Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.57 2018/06/11 19:13:38 jdolecek Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 static bool mskc_suspend(device_t, const pmf_qual_t *); 98 static bool mskc_resume(device_t, const pmf_qual_t *); 99 int msk_probe(device_t, cfdata_t, void *); 100 void msk_attach(device_t, device_t, void *); 101 int mskcprint(void *, const char *); 102 int msk_intr(void *); 103 void msk_intr_yukon(struct sk_if_softc *); 104 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 105 void msk_txeof(struct sk_if_softc *, int); 106 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 107 void msk_start(struct ifnet *); 108 int msk_ioctl(struct ifnet *, u_long, void *); 109 int msk_init(struct ifnet *); 110 void msk_init_yukon(struct sk_if_softc *); 111 void msk_stop(struct ifnet *, int); 112 void msk_watchdog(struct ifnet *); 113 void msk_reset(struct sk_softc *); 114 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 115 int msk_alloc_jumbo_mem(struct sk_if_softc *); 116 void *msk_jalloc(struct sk_if_softc *); 117 void msk_jfree(struct mbuf *, void *, size_t, void *); 118 int msk_init_rx_ring(struct sk_if_softc *); 119 int msk_init_tx_ring(struct sk_if_softc *); 120 121 void msk_update_int_mod(struct sk_softc *, int); 122 123 int msk_miibus_readreg(device_t, int, int); 124 void msk_miibus_writereg(device_t, int, int, int); 125 void msk_miibus_statchg(struct ifnet *); 126 127 void msk_setfilt(struct sk_if_softc *, void *, int); 128 void msk_setmulti(struct sk_if_softc *); 129 void msk_setpromisc(struct sk_if_softc *); 130 void msk_tick(void *); 131 132 /* #define MSK_DEBUG 1 */ 133 #ifdef MSK_DEBUG 134 #define DPRINTF(x) if (mskdebug) printf x 135 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 136 int mskdebug = MSK_DEBUG; 137 138 void msk_dump_txdesc(struct msk_tx_desc *, int); 139 void msk_dump_mbuf(struct mbuf *); 140 void msk_dump_bytes(const char *, int); 141 #else 142 #define DPRINTF(x) 143 #define DPRINTFN(n,x) 144 #endif 145 146 static int msk_sysctl_handler(SYSCTLFN_PROTO); 147 static int msk_root_num; 148 149 /* supported device vendors */ 150 static const struct msk_product { 151 pci_vendor_id_t msk_vendor; 152 pci_product_id_t msk_product; 153 } msk_products[] = { 154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 157 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 158 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 159 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 190 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 191 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 192 }; 193 194 static inline u_int32_t 195 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 196 { 197 return CSR_READ_4(sc, reg); 198 } 199 200 static inline u_int16_t 201 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 202 { 203 return CSR_READ_2(sc, reg); 204 } 205 206 static inline u_int8_t 207 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 208 { 209 return CSR_READ_1(sc, reg); 210 } 211 212 static inline void 213 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 214 { 215 CSR_WRITE_4(sc, reg, x); 216 } 217 218 static inline void 219 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 220 { 221 CSR_WRITE_2(sc, reg, x); 222 } 223 224 static inline void 225 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 226 { 227 CSR_WRITE_1(sc, reg, x); 228 } 229 230 int 231 msk_miibus_readreg(device_t dev, int phy, int reg) 232 { 233 struct sk_if_softc *sc_if = device_private(dev); 234 u_int16_t val; 235 int i; 236 237 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 238 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 239 240 for (i = 0; i < SK_TIMEOUT; i++) { 241 DELAY(1); 242 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 243 if (val & YU_SMICR_READ_VALID) 244 break; 245 } 246 247 if (i == SK_TIMEOUT) { 248 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 249 return (0); 250 } 251 252 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 253 SK_TIMEOUT)); 254 255 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 256 257 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 258 phy, reg, val)); 259 260 return (val); 261 } 262 263 void 264 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 265 { 266 struct sk_if_softc *sc_if = device_private(dev); 267 int i; 268 269 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 270 phy, reg, val)); 271 272 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 273 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 274 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 275 276 for (i = 0; i < SK_TIMEOUT; i++) { 277 DELAY(1); 278 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 279 break; 280 } 281 282 if (i == SK_TIMEOUT) 283 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 284 } 285 286 void 287 msk_miibus_statchg(struct ifnet *ifp) 288 { 289 struct sk_if_softc *sc_if = ifp->if_softc; 290 struct mii_data *mii = &sc_if->sk_mii; 291 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 292 int gpcr; 293 294 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 295 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 296 297 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 298 /* Set speed. */ 299 gpcr |= YU_GPCR_SPEED_DIS; 300 switch (IFM_SUBTYPE(mii->mii_media_active)) { 301 case IFM_1000_SX: 302 case IFM_1000_LX: 303 case IFM_1000_CX: 304 case IFM_1000_T: 305 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 306 break; 307 case IFM_100_TX: 308 gpcr |= YU_GPCR_SPEED; 309 break; 310 } 311 312 /* Set duplex. */ 313 gpcr |= YU_GPCR_DPLX_DIS; 314 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 315 gpcr |= YU_GPCR_DUPLEX; 316 317 /* Disable flow control. */ 318 gpcr |= YU_GPCR_FCTL_DIS; 319 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 320 } 321 322 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 323 324 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 325 SK_YU_READ_2(sc_if, YUKON_GPCR))); 326 } 327 328 #define HASH_BITS 6 329 330 void 331 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 332 { 333 char *addr = addrv; 334 int base = XM_RXFILT_ENTRY(slot); 335 336 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 337 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 338 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 339 } 340 341 void 342 msk_setmulti(struct sk_if_softc *sc_if) 343 { 344 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 345 u_int32_t hashes[2] = { 0, 0 }; 346 int h; 347 struct ethercom *ec = &sc_if->sk_ethercom; 348 struct ether_multi *enm; 349 struct ether_multistep step; 350 u_int16_t reg; 351 352 /* First, zot all the existing filters. */ 353 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 354 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 355 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 356 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 357 358 359 /* Now program new ones. */ 360 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 361 reg |= YU_RCR_UFLEN; 362 allmulti: 363 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 364 if ((ifp->if_flags & IFF_PROMISC) != 0) 365 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 366 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 367 hashes[0] = 0xFFFFFFFF; 368 hashes[1] = 0xFFFFFFFF; 369 } 370 } else { 371 /* First find the tail of the list. */ 372 ETHER_FIRST_MULTI(step, ec, enm); 373 while (enm != NULL) { 374 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 375 ETHER_ADDR_LEN)) { 376 ifp->if_flags |= IFF_ALLMULTI; 377 goto allmulti; 378 } 379 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 380 ((1 << HASH_BITS) - 1); 381 if (h < 32) 382 hashes[0] |= (1 << h); 383 else 384 hashes[1] |= (1 << (h - 32)); 385 386 ETHER_NEXT_MULTI(step, enm); 387 } 388 reg |= YU_RCR_MUFLEN; 389 } 390 391 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 392 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 393 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 394 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 395 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 396 } 397 398 void 399 msk_setpromisc(struct sk_if_softc *sc_if) 400 { 401 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 402 403 if (ifp->if_flags & IFF_PROMISC) 404 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 405 YU_RCR_UFLEN | YU_RCR_MUFLEN); 406 else 407 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 408 YU_RCR_UFLEN | YU_RCR_MUFLEN); 409 } 410 411 int 412 msk_init_rx_ring(struct sk_if_softc *sc_if) 413 { 414 struct msk_chain_data *cd = &sc_if->sk_cdata; 415 struct msk_ring_data *rd = sc_if->sk_rdata; 416 int i, nexti; 417 418 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 419 420 for (i = 0; i < MSK_RX_RING_CNT; i++) { 421 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 422 if (i == (MSK_RX_RING_CNT - 1)) 423 nexti = 0; 424 else 425 nexti = i + 1; 426 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 427 } 428 429 for (i = 0; i < MSK_RX_RING_CNT; i++) { 430 if (msk_newbuf(sc_if, i, NULL, 431 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 432 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 433 return (ENOBUFS); 434 } 435 } 436 437 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 438 sc_if->sk_cdata.sk_rx_cons = 0; 439 440 return (0); 441 } 442 443 int 444 msk_init_tx_ring(struct sk_if_softc *sc_if) 445 { 446 struct sk_softc *sc = sc_if->sk_softc; 447 struct msk_chain_data *cd = &sc_if->sk_cdata; 448 struct msk_ring_data *rd = sc_if->sk_rdata; 449 bus_dmamap_t dmamap; 450 struct sk_txmap_entry *entry; 451 int i, nexti; 452 453 memset(sc_if->sk_rdata->sk_tx_ring, 0, 454 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 455 456 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 457 for (i = 0; i < MSK_TX_RING_CNT; i++) { 458 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 459 if (i == (MSK_TX_RING_CNT - 1)) 460 nexti = 0; 461 else 462 nexti = i + 1; 463 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 464 465 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 466 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 467 return (ENOBUFS); 468 469 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 470 if (!entry) { 471 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 472 return (ENOBUFS); 473 } 474 entry->dmamap = dmamap; 475 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 476 } 477 478 sc_if->sk_cdata.sk_tx_prod = 0; 479 sc_if->sk_cdata.sk_tx_cons = 0; 480 sc_if->sk_cdata.sk_tx_cnt = 0; 481 482 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 485 return (0); 486 } 487 488 int 489 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 490 bus_dmamap_t dmamap) 491 { 492 struct mbuf *m_new = NULL; 493 struct sk_chain *c; 494 struct msk_rx_desc *r; 495 496 if (m == NULL) { 497 void *buf = NULL; 498 499 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 500 if (m_new == NULL) 501 return (ENOBUFS); 502 503 /* Allocate the jumbo buffer */ 504 buf = msk_jalloc(sc_if); 505 if (buf == NULL) { 506 m_freem(m_new); 507 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 508 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 509 return (ENOBUFS); 510 } 511 512 /* Attach the buffer to the mbuf */ 513 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 514 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 515 } else { 516 /* 517 * We're re-using a previously allocated mbuf; 518 * be sure to re-init pointers and lengths to 519 * default values. 520 */ 521 m_new = m; 522 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 523 m_new->m_data = m_new->m_ext.ext_buf; 524 } 525 m_adj(m_new, ETHER_ALIGN); 526 527 c = &sc_if->sk_cdata.sk_rx_chain[i]; 528 r = c->sk_le; 529 c->sk_mbuf = m_new; 530 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 531 (((vaddr_t)m_new->m_data 532 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 533 r->sk_len = htole16(SK_JLEN); 534 r->sk_ctl = 0; 535 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 536 537 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 538 539 return (0); 540 } 541 542 /* 543 * Memory management for jumbo frames. 544 */ 545 546 int 547 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 548 { 549 struct sk_softc *sc = sc_if->sk_softc; 550 char *ptr, *kva; 551 bus_dma_segment_t seg; 552 int i, rseg, state, error; 553 struct sk_jpool_entry *entry; 554 555 state = error = 0; 556 557 /* Grab a big chunk o' storage. */ 558 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 559 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 560 aprint_error(": can't alloc rx buffers"); 561 return (ENOBUFS); 562 } 563 564 state = 1; 565 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 566 BUS_DMA_NOWAIT)) { 567 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 2; 573 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 574 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 575 aprint_error(": can't create dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 3; 581 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 582 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 583 aprint_error(": can't load dma map"); 584 error = ENOBUFS; 585 goto out; 586 } 587 588 state = 4; 589 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 590 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 591 592 LIST_INIT(&sc_if->sk_jfree_listhead); 593 LIST_INIT(&sc_if->sk_jinuse_listhead); 594 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 595 596 /* 597 * Now divide it up into 9K pieces and save the addresses 598 * in an array. 599 */ 600 ptr = sc_if->sk_cdata.sk_jumbo_buf; 601 for (i = 0; i < MSK_JSLOTS; i++) { 602 sc_if->sk_cdata.sk_jslots[i] = ptr; 603 ptr += SK_JLEN; 604 entry = malloc(sizeof(struct sk_jpool_entry), 605 M_DEVBUF, M_NOWAIT); 606 if (entry == NULL) { 607 sc_if->sk_cdata.sk_jumbo_buf = NULL; 608 aprint_error(": no memory for jumbo buffer queue!"); 609 error = ENOBUFS; 610 goto out; 611 } 612 entry->slot = i; 613 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 614 entry, jpool_entries); 615 } 616 out: 617 if (error != 0) { 618 switch (state) { 619 case 4: 620 bus_dmamap_unload(sc->sc_dmatag, 621 sc_if->sk_cdata.sk_rx_jumbo_map); 622 case 3: 623 bus_dmamap_destroy(sc->sc_dmatag, 624 sc_if->sk_cdata.sk_rx_jumbo_map); 625 case 2: 626 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 627 case 1: 628 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 629 break; 630 default: 631 break; 632 } 633 } 634 635 return error; 636 } 637 638 /* 639 * Allocate a jumbo buffer. 640 */ 641 void * 642 msk_jalloc(struct sk_if_softc *sc_if) 643 { 644 struct sk_jpool_entry *entry; 645 646 mutex_enter(&sc_if->sk_jpool_mtx); 647 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 648 649 if (entry == NULL) { 650 mutex_exit(&sc_if->sk_jpool_mtx); 651 return NULL; 652 } 653 654 LIST_REMOVE(entry, jpool_entries); 655 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 656 mutex_exit(&sc_if->sk_jpool_mtx); 657 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 void 664 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 665 { 666 struct sk_jpool_entry *entry; 667 struct sk_if_softc *sc; 668 int i; 669 670 /* Extract the softc struct pointer. */ 671 sc = (struct sk_if_softc *)arg; 672 673 if (sc == NULL) 674 panic("msk_jfree: can't find softc pointer!"); 675 676 /* calculate the slot this buffer belongs to */ 677 i = ((vaddr_t)buf 678 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 679 680 if ((i < 0) || (i >= MSK_JSLOTS)) 681 panic("msk_jfree: asked to free buffer that we don't manage!"); 682 683 mutex_enter(&sc->sk_jpool_mtx); 684 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 685 if (entry == NULL) 686 panic("msk_jfree: buffer not in use!"); 687 entry->slot = i; 688 LIST_REMOVE(entry, jpool_entries); 689 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 690 mutex_exit(&sc->sk_jpool_mtx); 691 692 if (__predict_true(m != NULL)) 693 pool_cache_put(mb_cache, m); 694 } 695 696 int 697 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 698 { 699 struct sk_if_softc *sc = ifp->if_softc; 700 int s, error; 701 702 s = splnet(); 703 704 DPRINTFN(2, ("msk_ioctl ETHER\n")); 705 switch (cmd) { 706 case SIOCSIFFLAGS: 707 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 708 break; 709 710 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 711 case IFF_RUNNING: 712 msk_stop(ifp, 1); 713 break; 714 case IFF_UP: 715 msk_init(ifp); 716 break; 717 case IFF_UP | IFF_RUNNING: 718 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 719 msk_setpromisc(sc); 720 msk_setmulti(sc); 721 } else 722 msk_init(ifp); 723 break; 724 } 725 sc->sk_if_flags = ifp->if_flags; 726 break; 727 default: 728 error = ether_ioctl(ifp, cmd, data); 729 if (error == ENETRESET) { 730 error = 0; 731 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 732 ; 733 else if (ifp->if_flags & IFF_RUNNING) { 734 /* 735 * Multicast list has changed; set the hardware 736 * filter accordingly. 737 */ 738 msk_setmulti(sc); 739 } 740 } 741 break; 742 } 743 744 splx(s); 745 return error; 746 } 747 748 void 749 msk_update_int_mod(struct sk_softc *sc, int verbose) 750 { 751 u_int32_t imtimer_ticks; 752 753 /* 754 * Configure interrupt moderation. The moderation timer 755 * defers interrupts specified in the interrupt moderation 756 * timer mask based on the timeout specified in the interrupt 757 * moderation timer init register. Each bit in the timer 758 * register represents one tick, so to specify a timeout in 759 * microseconds, we have to multiply by the correct number of 760 * ticks-per-microsecond. 761 */ 762 switch (sc->sk_type) { 763 case SK_YUKON_EC: 764 case SK_YUKON_EC_U: 765 case SK_YUKON_EX: 766 case SK_YUKON_SUPR: 767 case SK_YUKON_ULTRA2: 768 case SK_YUKON_OPTIMA: 769 case SK_YUKON_PRM: 770 case SK_YUKON_OPTIMA2: 771 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 772 break; 773 case SK_YUKON_FE: 774 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 775 break; 776 case SK_YUKON_XL: 777 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 778 break; 779 default: 780 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 781 } 782 if (verbose) 783 aprint_verbose_dev(sc->sk_dev, 784 "interrupt moderation is %d us\n", sc->sk_int_mod); 785 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 786 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 787 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 788 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 789 sc->sk_int_mod_pending = 0; 790 } 791 792 static int 793 msk_lookup(const struct pci_attach_args *pa) 794 { 795 const struct msk_product *pmsk; 796 797 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 798 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 799 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 800 return 1; 801 } 802 return 0; 803 } 804 805 /* 806 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 807 * IDs against our list and return a device name if we find a match. 808 */ 809 int 810 mskc_probe(device_t parent, cfdata_t match, void *aux) 811 { 812 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 813 814 return msk_lookup(pa); 815 } 816 817 /* 818 * Force the GEnesis into reset, then bring it out of reset. 819 */ 820 void msk_reset(struct sk_softc *sc) 821 { 822 u_int32_t imtimer_ticks, reg1; 823 int reg; 824 825 DPRINTFN(2, ("msk_reset\n")); 826 827 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 828 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 829 830 DELAY(1000); 831 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 832 DELAY(2); 833 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 834 sk_win_write_1(sc, SK_TESTCTL1, 2); 835 836 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 837 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 838 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 839 else 840 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 841 842 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 843 sc->sk_type >= SK_YUKON_FE_P) { 844 uint32_t our; 845 846 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 847 848 /* enable all clocks. */ 849 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 850 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 851 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 852 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 853 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 854 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 855 /* Set all bits to 0 except bits 15..12 */ 856 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 857 /* Set to default value */ 858 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 859 } 860 861 /* release PHY from PowerDown/Coma mode. */ 862 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 863 864 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 865 sk_win_write_1(sc, SK_Y2_CLKGATE, 866 SK_Y2_CLKGATE_LINK1_GATE_DIS | 867 SK_Y2_CLKGATE_LINK2_GATE_DIS | 868 SK_Y2_CLKGATE_LINK1_CORE_DIS | 869 SK_Y2_CLKGATE_LINK2_CORE_DIS | 870 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 871 else 872 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 873 874 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 875 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 876 DELAY(1000); 877 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 878 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 879 880 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 881 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 882 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 883 } 884 885 sk_win_write_1(sc, SK_TESTCTL1, 1); 886 887 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 888 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n", 889 CSR_READ_2(sc, SK_LINK_CTRL))); 890 891 /* Disable ASF */ 892 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 893 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 894 895 /* Clear I2C IRQ noise */ 896 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 897 898 /* Disable hardware timer */ 899 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 900 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 901 902 /* Disable descriptor polling */ 903 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 904 905 /* Disable time stamps */ 906 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 907 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 908 909 /* Enable RAM interface */ 910 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 911 for (reg = SK_TO0;reg <= SK_TO11; reg++) 912 sk_win_write_1(sc, reg, 36); 913 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 914 for (reg = SK_TO0;reg <= SK_TO11; reg++) 915 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 916 917 /* 918 * Configure interrupt moderation. The moderation timer 919 * defers interrupts specified in the interrupt moderation 920 * timer mask based on the timeout specified in the interrupt 921 * moderation timer init register. Each bit in the timer 922 * register represents one tick, so to specify a timeout in 923 * microseconds, we have to multiply by the correct number of 924 * ticks-per-microsecond. 925 */ 926 switch (sc->sk_type) { 927 case SK_YUKON_EC: 928 case SK_YUKON_EC_U: 929 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 930 break; 931 case SK_YUKON_FE: 932 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 933 break; 934 case SK_YUKON_XL: 935 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 936 break; 937 default: 938 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 939 } 940 941 /* Reset status ring. */ 942 memset(sc->sk_status_ring, 0, 943 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 944 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 945 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 946 sc->sk_status_idx = 0; 947 sc->sk_status_own_idx = 0; 948 949 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 950 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 951 952 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 953 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 954 sc->sk_status_map->dm_segs[0].ds_addr); 955 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 956 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 957 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 958 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 959 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 960 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 961 } else { 962 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 963 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 964 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 965 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 966 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 967 } 968 969 #if 0 970 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 971 #endif 972 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 973 974 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 975 976 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 977 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 978 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 979 980 msk_update_int_mod(sc, 0); 981 } 982 983 int 984 msk_probe(device_t parent, cfdata_t match, void *aux) 985 { 986 struct skc_attach_args *sa = aux; 987 988 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 989 return (0); 990 991 switch (sa->skc_type) { 992 case SK_YUKON_XL: 993 case SK_YUKON_EC_U: 994 case SK_YUKON_EX: 995 case SK_YUKON_EC: 996 case SK_YUKON_FE: 997 case SK_YUKON_FE_P: 998 case SK_YUKON_SUPR: 999 case SK_YUKON_ULTRA2: 1000 case SK_YUKON_OPTIMA: 1001 case SK_YUKON_PRM: 1002 case SK_YUKON_OPTIMA2: 1003 return (1); 1004 } 1005 1006 return (0); 1007 } 1008 1009 static bool 1010 msk_resume(device_t dv, const pmf_qual_t *qual) 1011 { 1012 struct sk_if_softc *sc_if = device_private(dv); 1013 1014 msk_init_yukon(sc_if); 1015 return true; 1016 } 1017 1018 /* 1019 * Each XMAC chip is attached as a separate logical IP interface. 1020 * Single port cards will have only one logical interface of course. 1021 */ 1022 void 1023 msk_attach(device_t parent, device_t self, void *aux) 1024 { 1025 struct sk_if_softc *sc_if = device_private(self); 1026 struct sk_softc *sc = device_private(parent); 1027 struct skc_attach_args *sa = aux; 1028 struct ifnet *ifp; 1029 void *kva; 1030 bus_dma_segment_t seg; 1031 int i, rseg; 1032 u_int32_t chunk; 1033 1034 sc_if->sk_dev = self; 1035 sc_if->sk_port = sa->skc_port; 1036 sc_if->sk_softc = sc; 1037 sc->sk_if[sa->skc_port] = sc_if; 1038 1039 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1040 1041 /* 1042 * Get station address for this interface. Note that 1043 * dual port cards actually come with three station 1044 * addresses: one for each port, plus an extra. The 1045 * extra one is used by the SysKonnect driver software 1046 * as a 'virtual' station address for when both ports 1047 * are operating in failover mode. Currently we don't 1048 * use this extra address. 1049 */ 1050 for (i = 0; i < ETHER_ADDR_LEN; i++) 1051 sc_if->sk_enaddr[i] = 1052 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1053 1054 aprint_normal(": Ethernet address %s\n", 1055 ether_sprintf(sc_if->sk_enaddr)); 1056 1057 /* 1058 * Set up RAM buffer addresses. The Yukon2 has a small amount 1059 * of SRAM on it, somewhere between 4K and 48K. We need to 1060 * divide this up between the transmitter and receiver. We 1061 * give the receiver 2/3 of the memory (rounded down), and the 1062 * transmitter whatever remains. 1063 */ 1064 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1065 sc_if->sk_rx_ramstart = 0; 1066 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1067 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1068 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1069 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1070 1071 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1072 " tx_ramstart=%#x tx_ramend=%#x\n", 1073 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1074 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1075 1076 /* Allocate the descriptor queues. */ 1077 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1078 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1079 aprint_error(": can't alloc rx buffers\n"); 1080 goto fail; 1081 } 1082 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1083 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1084 aprint_error(": can't map dma buffers (%zu bytes)\n", 1085 sizeof(struct msk_ring_data)); 1086 goto fail_1; 1087 } 1088 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1089 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1090 &sc_if->sk_ring_map)) { 1091 aprint_error(": can't create dma map\n"); 1092 goto fail_2; 1093 } 1094 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1095 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1096 aprint_error(": can't load dma map\n"); 1097 goto fail_3; 1098 } 1099 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1100 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1101 1102 ifp = &sc_if->sk_ethercom.ec_if; 1103 /* Try to allocate memory for jumbo buffers. */ 1104 if (msk_alloc_jumbo_mem(sc_if)) { 1105 aprint_error(": jumbo buffer allocation failed\n"); 1106 goto fail_3; 1107 } 1108 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1109 if (sc->sk_type != SK_YUKON_FE) 1110 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1111 1112 ifp->if_softc = sc_if; 1113 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1114 ifp->if_ioctl = msk_ioctl; 1115 ifp->if_start = msk_start; 1116 ifp->if_stop = msk_stop; 1117 ifp->if_init = msk_init; 1118 ifp->if_watchdog = msk_watchdog; 1119 ifp->if_baudrate = 1000000000; 1120 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1121 IFQ_SET_READY(&ifp->if_snd); 1122 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1123 1124 /* 1125 * Do miibus setup. 1126 */ 1127 msk_init_yukon(sc_if); 1128 1129 DPRINTFN(2, ("msk_attach: 1\n")); 1130 1131 sc_if->sk_mii.mii_ifp = ifp; 1132 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1133 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1134 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1135 1136 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1137 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1138 ether_mediachange, ether_mediastatus); 1139 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1140 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG); 1141 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1142 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1143 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1144 0, NULL); 1145 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1146 } else 1147 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1148 1149 callout_init(&sc_if->sk_tick_ch, 0); 1150 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1151 callout_schedule(&sc_if->sk_tick_ch, hz); 1152 1153 /* 1154 * Call MI attach routines. 1155 */ 1156 if_attach(ifp); 1157 if_deferred_start_init(ifp, NULL); 1158 ether_ifattach(ifp, sc_if->sk_enaddr); 1159 1160 if (pmf_device_register(self, NULL, msk_resume)) 1161 pmf_class_network_register(self, ifp); 1162 else 1163 aprint_error_dev(self, "couldn't establish power handler\n"); 1164 1165 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1166 RND_TYPE_NET, RND_FLAG_DEFAULT); 1167 1168 DPRINTFN(2, ("msk_attach: end\n")); 1169 return; 1170 1171 fail_3: 1172 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1173 fail_2: 1174 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1175 fail_1: 1176 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1177 fail: 1178 sc->sk_if[sa->skc_port] = NULL; 1179 } 1180 1181 int 1182 mskcprint(void *aux, const char *pnp) 1183 { 1184 struct skc_attach_args *sa = aux; 1185 1186 if (pnp) 1187 aprint_normal("sk port %c at %s", 1188 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1189 else 1190 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1191 return (UNCONF); 1192 } 1193 1194 /* 1195 * Attach the interface. Allocate softc structures, do ifmedia 1196 * setup and ethernet/BPF attach. 1197 */ 1198 void 1199 mskc_attach(device_t parent, device_t self, void *aux) 1200 { 1201 struct sk_softc *sc = device_private(self); 1202 struct pci_attach_args *pa = aux; 1203 struct skc_attach_args skca; 1204 pci_chipset_tag_t pc = pa->pa_pc; 1205 pcireg_t command, memtype; 1206 pci_intr_handle_t ih; 1207 const char *intrstr = NULL; 1208 bus_size_t size; 1209 int rc, sk_nodenum; 1210 u_int8_t hw; 1211 const char *revstr = NULL; 1212 const struct sysctlnode *node; 1213 void *kva; 1214 bus_dma_segment_t seg; 1215 int rseg; 1216 char intrbuf[PCI_INTRSTR_LEN]; 1217 1218 DPRINTFN(2, ("begin mskc_attach\n")); 1219 1220 sc->sk_dev = self; 1221 /* 1222 * Handle power management nonsense. 1223 */ 1224 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1225 1226 if (command == 0x01) { 1227 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1228 if (command & SK_PSTATE_MASK) { 1229 u_int32_t iobase, membase, irq; 1230 1231 /* Save important PCI config data. */ 1232 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1233 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1234 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1235 1236 /* Reset the power state. */ 1237 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1238 "mode -- setting to D0\n", 1239 command & SK_PSTATE_MASK); 1240 command &= 0xFFFFFFFC; 1241 pci_conf_write(pc, pa->pa_tag, 1242 SK_PCI_PWRMGMTCTRL, command); 1243 1244 /* Restore PCI config data. */ 1245 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1246 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1247 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1248 } 1249 } 1250 1251 /* 1252 * Map control/status registers. 1253 */ 1254 1255 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1256 switch (memtype) { 1257 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1258 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1259 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1260 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1261 NULL, &size) == 0) { 1262 break; 1263 } 1264 default: 1265 aprint_error(": can't map mem space\n"); 1266 return; 1267 } 1268 1269 sc->sc_dmatag = pa->pa_dmat; 1270 1271 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1272 command |= PCI_COMMAND_MASTER_ENABLE; 1273 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1274 1275 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1276 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1277 1278 /* bail out here if chip is not recognized */ 1279 if (!(SK_IS_YUKON2(sc))) { 1280 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1281 goto fail_1; 1282 } 1283 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1284 1285 /* Allocate interrupt */ 1286 if (pci_intr_map(pa, &ih)) { 1287 aprint_error(": couldn't map interrupt\n"); 1288 goto fail_1; 1289 } 1290 1291 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1292 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1293 if (sc->sk_intrhand == NULL) { 1294 aprint_error(": couldn't establish interrupt"); 1295 if (intrstr != NULL) 1296 aprint_error(" at %s", intrstr); 1297 aprint_error("\n"); 1298 goto fail_1; 1299 } 1300 1301 if (bus_dmamem_alloc(sc->sc_dmatag, 1302 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1303 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1304 aprint_error(": can't alloc status buffers\n"); 1305 goto fail_2; 1306 } 1307 1308 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1309 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1310 &kva, BUS_DMA_NOWAIT)) { 1311 aprint_error(": can't map dma buffers (%zu bytes)\n", 1312 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1313 goto fail_3; 1314 } 1315 if (bus_dmamap_create(sc->sc_dmatag, 1316 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1317 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1318 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1319 aprint_error(": can't create dma map\n"); 1320 goto fail_4; 1321 } 1322 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1323 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1324 NULL, BUS_DMA_NOWAIT)) { 1325 aprint_error(": can't load dma map\n"); 1326 goto fail_5; 1327 } 1328 sc->sk_status_ring = (struct msk_status_desc *)kva; 1329 1330 sc->sk_int_mod = SK_IM_DEFAULT; 1331 sc->sk_int_mod_pending = 0; 1332 1333 /* Reset the adapter. */ 1334 msk_reset(sc); 1335 1336 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1337 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1338 1339 switch (sc->sk_type) { 1340 case SK_YUKON_XL: 1341 sc->sk_name = "Yukon-2 XL"; 1342 break; 1343 case SK_YUKON_EC_U: 1344 sc->sk_name = "Yukon-2 EC Ultra"; 1345 break; 1346 case SK_YUKON_EX: 1347 sc->sk_name = "Yukon-2 Extreme"; 1348 break; 1349 case SK_YUKON_EC: 1350 sc->sk_name = "Yukon-2 EC"; 1351 break; 1352 case SK_YUKON_FE: 1353 sc->sk_name = "Yukon-2 FE"; 1354 break; 1355 case SK_YUKON_FE_P: 1356 sc->sk_name = "Yukon-2 FE+"; 1357 break; 1358 case SK_YUKON_SUPR: 1359 sc->sk_name = "Yukon-2 Supreme"; 1360 break; 1361 case SK_YUKON_ULTRA2: 1362 sc->sk_name = "Yukon-2 Ultra 2"; 1363 break; 1364 case SK_YUKON_OPTIMA: 1365 sc->sk_name = "Yukon-2 Optima"; 1366 break; 1367 case SK_YUKON_PRM: 1368 sc->sk_name = "Yukon-2 Optima Prime"; 1369 break; 1370 case SK_YUKON_OPTIMA2: 1371 sc->sk_name = "Yukon-2 Optima 2"; 1372 break; 1373 default: 1374 sc->sk_name = "Yukon (Unknown)"; 1375 } 1376 1377 if (sc->sk_type == SK_YUKON_XL) { 1378 switch (sc->sk_rev) { 1379 case SK_YUKON_XL_REV_A0: 1380 sc->sk_workaround = 0; 1381 revstr = "A0"; 1382 break; 1383 case SK_YUKON_XL_REV_A1: 1384 sc->sk_workaround = SK_WA_4109; 1385 revstr = "A1"; 1386 break; 1387 case SK_YUKON_XL_REV_A2: 1388 sc->sk_workaround = SK_WA_4109; 1389 revstr = "A2"; 1390 break; 1391 case SK_YUKON_XL_REV_A3: 1392 sc->sk_workaround = SK_WA_4109; 1393 revstr = "A3"; 1394 break; 1395 default: 1396 sc->sk_workaround = 0; 1397 break; 1398 } 1399 } 1400 1401 if (sc->sk_type == SK_YUKON_EC) { 1402 switch (sc->sk_rev) { 1403 case SK_YUKON_EC_REV_A1: 1404 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1405 revstr = "A1"; 1406 break; 1407 case SK_YUKON_EC_REV_A2: 1408 sc->sk_workaround = SK_WA_4109; 1409 revstr = "A2"; 1410 break; 1411 case SK_YUKON_EC_REV_A3: 1412 sc->sk_workaround = SK_WA_4109; 1413 revstr = "A3"; 1414 break; 1415 default: 1416 sc->sk_workaround = 0; 1417 break; 1418 } 1419 } 1420 1421 if (sc->sk_type == SK_YUKON_FE) { 1422 sc->sk_workaround = SK_WA_4109; 1423 switch (sc->sk_rev) { 1424 case SK_YUKON_FE_REV_A1: 1425 revstr = "A1"; 1426 break; 1427 case SK_YUKON_FE_REV_A2: 1428 revstr = "A2"; 1429 break; 1430 default: 1431 sc->sk_workaround = 0; 1432 break; 1433 } 1434 } 1435 1436 if (sc->sk_type == SK_YUKON_EC_U) { 1437 sc->sk_workaround = SK_WA_4109; 1438 switch (sc->sk_rev) { 1439 case SK_YUKON_EC_U_REV_A0: 1440 revstr = "A0"; 1441 break; 1442 case SK_YUKON_EC_U_REV_A1: 1443 revstr = "A1"; 1444 break; 1445 case SK_YUKON_EC_U_REV_B0: 1446 revstr = "B0"; 1447 break; 1448 case SK_YUKON_EC_U_REV_B1: 1449 revstr = "B1"; 1450 break; 1451 default: 1452 sc->sk_workaround = 0; 1453 break; 1454 } 1455 } 1456 1457 if (sc->sk_type == SK_YUKON_FE) { 1458 switch (sc->sk_rev) { 1459 case SK_YUKON_FE_REV_A1: 1460 revstr = "A1"; 1461 break; 1462 case SK_YUKON_FE_REV_A2: 1463 revstr = "A2"; 1464 break; 1465 default: 1466 ; 1467 } 1468 } 1469 1470 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1471 revstr = "A0"; 1472 1473 if (sc->sk_type == SK_YUKON_EX) { 1474 switch (sc->sk_rev) { 1475 case SK_YUKON_EX_REV_A0: 1476 revstr = "A0"; 1477 break; 1478 case SK_YUKON_EX_REV_B0: 1479 revstr = "B0"; 1480 break; 1481 default: 1482 ; 1483 } 1484 } 1485 1486 if (sc->sk_type == SK_YUKON_SUPR) { 1487 switch (sc->sk_rev) { 1488 case SK_YUKON_SUPR_REV_A0: 1489 revstr = "A0"; 1490 break; 1491 case SK_YUKON_SUPR_REV_B0: 1492 revstr = "B0"; 1493 break; 1494 case SK_YUKON_SUPR_REV_B1: 1495 revstr = "B1"; 1496 break; 1497 default: 1498 ; 1499 } 1500 } 1501 1502 if (sc->sk_type == SK_YUKON_PRM) { 1503 switch (sc->sk_rev) { 1504 case SK_YUKON_PRM_REV_Z1: 1505 revstr = "Z1"; 1506 break; 1507 case SK_YUKON_PRM_REV_A0: 1508 revstr = "A0"; 1509 break; 1510 default: 1511 ; 1512 } 1513 } 1514 1515 /* Announce the product name. */ 1516 aprint_normal(", %s", sc->sk_name); 1517 if (revstr != NULL) 1518 aprint_normal(" rev. %s", revstr); 1519 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1520 1521 sc->sk_macs = 1; 1522 1523 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1524 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1525 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1526 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1527 sc->sk_macs++; 1528 } 1529 1530 skca.skc_port = SK_PORT_A; 1531 skca.skc_type = sc->sk_type; 1532 skca.skc_rev = sc->sk_rev; 1533 (void)config_found(sc->sk_dev, &skca, mskcprint); 1534 1535 if (sc->sk_macs > 1) { 1536 skca.skc_port = SK_PORT_B; 1537 skca.skc_type = sc->sk_type; 1538 skca.skc_rev = sc->sk_rev; 1539 (void)config_found(sc->sk_dev, &skca, mskcprint); 1540 } 1541 1542 /* Turn on the 'driver is loaded' LED. */ 1543 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1544 1545 /* skc sysctl setup */ 1546 1547 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1548 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1549 SYSCTL_DESCR("mskc per-controller controls"), 1550 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1551 CTL_EOL)) != 0) { 1552 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1553 goto fail_6; 1554 } 1555 1556 sk_nodenum = node->sysctl_num; 1557 1558 /* interrupt moderation time in usecs */ 1559 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1560 CTLFLAG_READWRITE, 1561 CTLTYPE_INT, "int_mod", 1562 SYSCTL_DESCR("msk interrupt moderation timer"), 1563 msk_sysctl_handler, 0, (void *)sc, 1564 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1565 CTL_EOL)) != 0) { 1566 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1567 goto fail_6; 1568 } 1569 1570 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1571 aprint_error_dev(self, "couldn't establish power handler\n"); 1572 1573 return; 1574 1575 fail_6: 1576 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1577 fail_5: 1578 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1579 fail_4: 1580 bus_dmamem_unmap(sc->sc_dmatag, kva, 1581 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1582 fail_3: 1583 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1584 fail_2: 1585 pci_intr_disestablish(pc, sc->sk_intrhand); 1586 fail_1: 1587 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1588 } 1589 1590 int 1591 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1592 { 1593 struct sk_softc *sc = sc_if->sk_softc; 1594 struct msk_tx_desc *f = NULL; 1595 u_int32_t frag, cur; 1596 int i; 1597 struct sk_txmap_entry *entry; 1598 bus_dmamap_t txmap; 1599 1600 DPRINTFN(2, ("msk_encap\n")); 1601 1602 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1603 if (entry == NULL) { 1604 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1605 return (ENOBUFS); 1606 } 1607 txmap = entry->dmamap; 1608 1609 cur = frag = *txidx; 1610 1611 #ifdef MSK_DEBUG 1612 if (mskdebug >= 2) 1613 msk_dump_mbuf(m_head); 1614 #endif 1615 1616 /* 1617 * Start packing the mbufs in this chain into 1618 * the fragment pointers. Stop when we run out 1619 * of fragments or hit the end of the mbuf chain. 1620 */ 1621 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1622 BUS_DMA_NOWAIT)) { 1623 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1624 return (ENOBUFS); 1625 } 1626 1627 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1628 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1629 bus_dmamap_unload(sc->sc_dmatag, txmap); 1630 return (ENOBUFS); 1631 } 1632 1633 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1634 1635 /* Sync the DMA map. */ 1636 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1637 BUS_DMASYNC_PREWRITE); 1638 1639 for (i = 0; i < txmap->dm_nsegs; i++) { 1640 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1641 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1642 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1643 f->sk_ctl = 0; 1644 if (i == 0) 1645 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1646 else 1647 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1648 cur = frag; 1649 SK_INC(frag, MSK_TX_RING_CNT); 1650 } 1651 1652 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1653 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1654 1655 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1656 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1657 1658 /* Sync descriptors before handing to chip */ 1659 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1660 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1661 1662 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1663 1664 /* Sync first descriptor to hand it off */ 1665 MSK_CDTXSYNC(sc_if, *txidx, 1, 1666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1667 1668 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1669 1670 #ifdef MSK_DEBUG 1671 if (mskdebug >= 2) { 1672 struct msk_tx_desc *le; 1673 u_int32_t idx; 1674 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1675 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1676 msk_dump_txdesc(le, idx); 1677 } 1678 } 1679 #endif 1680 1681 *txidx = frag; 1682 1683 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1684 1685 return (0); 1686 } 1687 1688 void 1689 msk_start(struct ifnet *ifp) 1690 { 1691 struct sk_if_softc *sc_if = ifp->if_softc; 1692 struct mbuf *m_head = NULL; 1693 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1694 int pkts = 0; 1695 1696 DPRINTFN(2, ("msk_start\n")); 1697 1698 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1699 IFQ_POLL(&ifp->if_snd, m_head); 1700 if (m_head == NULL) 1701 break; 1702 1703 /* 1704 * Pack the data into the transmit ring. If we 1705 * don't have room, set the OACTIVE flag and wait 1706 * for the NIC to drain the ring. 1707 */ 1708 if (msk_encap(sc_if, m_head, &idx)) { 1709 ifp->if_flags |= IFF_OACTIVE; 1710 break; 1711 } 1712 1713 /* now we are committed to transmit the packet */ 1714 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1715 pkts++; 1716 1717 /* 1718 * If there's a BPF listener, bounce a copy of this frame 1719 * to him. 1720 */ 1721 bpf_mtap(ifp, m_head); 1722 } 1723 if (pkts == 0) 1724 return; 1725 1726 /* Transmit */ 1727 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1728 sc_if->sk_cdata.sk_tx_prod = idx; 1729 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1730 1731 /* Set a timeout in case the chip goes out to lunch. */ 1732 ifp->if_timer = 5; 1733 } 1734 } 1735 1736 void 1737 msk_watchdog(struct ifnet *ifp) 1738 { 1739 struct sk_if_softc *sc_if = ifp->if_softc; 1740 u_int32_t reg; 1741 int idx; 1742 1743 /* 1744 * Reclaim first as there is a possibility of losing Tx completion 1745 * interrupts. 1746 */ 1747 if (sc_if->sk_port == SK_PORT_A) 1748 reg = SK_STAT_BMU_TXA1_RIDX; 1749 else 1750 reg = SK_STAT_BMU_TXA2_RIDX; 1751 1752 idx = sk_win_read_2(sc_if->sk_softc, reg); 1753 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1754 msk_txeof(sc_if, idx); 1755 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1756 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1757 1758 ifp->if_oerrors++; 1759 1760 /* XXX Resets both ports; we shouldn't do that. */ 1761 msk_reset(sc_if->sk_softc); 1762 msk_init(ifp); 1763 } 1764 } 1765 } 1766 1767 static bool 1768 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1769 { 1770 struct sk_softc *sc = device_private(dv); 1771 1772 DPRINTFN(2, ("mskc_suspend\n")); 1773 1774 /* Turn off the 'driver is loaded' LED. */ 1775 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1776 1777 return true; 1778 } 1779 1780 static bool 1781 mskc_resume(device_t dv, const pmf_qual_t *qual) 1782 { 1783 struct sk_softc *sc = device_private(dv); 1784 1785 DPRINTFN(2, ("mskc_resume\n")); 1786 1787 msk_reset(sc); 1788 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1789 1790 return true; 1791 } 1792 1793 static __inline int 1794 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1795 { 1796 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1797 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1798 YU_RXSTAT_JABBER)) != 0 || 1799 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1800 YU_RXSTAT_BYTES(stat) != len) 1801 return (0); 1802 1803 return (1); 1804 } 1805 1806 void 1807 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1808 { 1809 struct sk_softc *sc = sc_if->sk_softc; 1810 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1811 struct mbuf *m; 1812 struct sk_chain *cur_rx; 1813 int cur, total_len = len; 1814 bus_dmamap_t dmamap; 1815 1816 DPRINTFN(2, ("msk_rxeof\n")); 1817 1818 cur = sc_if->sk_cdata.sk_rx_cons; 1819 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1820 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1821 1822 /* Sync the descriptor */ 1823 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1824 1825 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1826 if (cur_rx->sk_mbuf == NULL) 1827 return; 1828 1829 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1830 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1831 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1832 1833 m = cur_rx->sk_mbuf; 1834 cur_rx->sk_mbuf = NULL; 1835 1836 if (total_len < SK_MIN_FRAMELEN || 1837 total_len > ETHER_MAX_LEN_JUMBO || 1838 msk_rxvalid(sc, rxstat, total_len) == 0) { 1839 ifp->if_ierrors++; 1840 msk_newbuf(sc_if, cur, m, dmamap); 1841 return; 1842 } 1843 1844 /* 1845 * Try to allocate a new jumbo buffer. If that fails, copy the 1846 * packet to mbufs and put the jumbo buffer back in the ring 1847 * so it can be re-used. If allocating mbufs fails, then we 1848 * have to drop the packet. 1849 */ 1850 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1851 struct mbuf *m0; 1852 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1853 total_len + ETHER_ALIGN, 0, ifp, NULL); 1854 msk_newbuf(sc_if, cur, m, dmamap); 1855 if (m0 == NULL) { 1856 ifp->if_ierrors++; 1857 return; 1858 } 1859 m_adj(m0, ETHER_ALIGN); 1860 m = m0; 1861 } else { 1862 m_set_rcvif(m, ifp); 1863 m->m_pkthdr.len = m->m_len = total_len; 1864 } 1865 1866 /* pass it on. */ 1867 if_percpuq_enqueue(ifp->if_percpuq, m); 1868 } 1869 1870 void 1871 msk_txeof(struct sk_if_softc *sc_if, int idx) 1872 { 1873 struct sk_softc *sc = sc_if->sk_softc; 1874 struct msk_tx_desc *cur_tx; 1875 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1876 u_int32_t sk_ctl; 1877 struct sk_txmap_entry *entry; 1878 int cons, prog; 1879 1880 DPRINTFN(2, ("msk_txeof\n")); 1881 1882 /* 1883 * Go through our tx ring and free mbufs for those 1884 * frames that have been sent. 1885 */ 1886 cons = sc_if->sk_cdata.sk_tx_cons; 1887 prog = 0; 1888 while (cons != idx) { 1889 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1890 break; 1891 prog++; 1892 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1893 1894 MSK_CDTXSYNC(sc_if, cons, 1, 1895 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1896 sk_ctl = cur_tx->sk_ctl; 1897 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1898 #ifdef MSK_DEBUG 1899 if (mskdebug >= 2) 1900 msk_dump_txdesc(cur_tx, cons); 1901 #endif 1902 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1903 ifp->if_opackets++; 1904 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1905 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1906 1907 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1908 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1909 1910 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1911 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1912 link); 1913 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 1914 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 1915 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 1916 } 1917 sc_if->sk_cdata.sk_tx_cnt--; 1918 SK_INC(cons, MSK_TX_RING_CNT); 1919 } 1920 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 1921 1922 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 1923 ifp->if_flags &= ~IFF_OACTIVE; 1924 1925 if (prog > 0) 1926 sc_if->sk_cdata.sk_tx_cons = cons; 1927 } 1928 1929 void 1930 msk_tick(void *xsc_if) 1931 { 1932 struct sk_if_softc *sc_if = xsc_if; 1933 struct mii_data *mii = &sc_if->sk_mii; 1934 uint16_t gpsr; 1935 int s; 1936 1937 s = splnet(); 1938 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR); 1939 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) { 1940 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC); 1941 mii_tick(mii); 1942 } 1943 splx(s); 1944 1945 callout_schedule(&sc_if->sk_tick_ch, hz); 1946 } 1947 1948 void 1949 msk_intr_yukon(struct sk_if_softc *sc_if) 1950 { 1951 u_int8_t status; 1952 1953 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 1954 /* RX overrun */ 1955 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 1956 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 1957 SK_RFCTL_RX_FIFO_OVER); 1958 } 1959 /* TX underrun */ 1960 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 1961 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 1962 SK_TFCTL_TX_FIFO_UNDER); 1963 } 1964 1965 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 1966 } 1967 1968 int 1969 msk_intr(void *xsc) 1970 { 1971 struct sk_softc *sc = xsc; 1972 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1973 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1974 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1975 int claimed = 0; 1976 u_int32_t status; 1977 uint32_t st_status; 1978 uint16_t st_len; 1979 uint8_t st_opcode, st_link; 1980 struct msk_status_desc *cur_st; 1981 1982 status = CSR_READ_4(sc, SK_Y2_ISSR2); 1983 if (status == 0) { 1984 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1985 return (0); 1986 } 1987 1988 status = CSR_READ_4(sc, SK_ISR); 1989 1990 if (sc_if0 != NULL) 1991 ifp0 = &sc_if0->sk_ethercom.ec_if; 1992 if (sc_if1 != NULL) 1993 ifp1 = &sc_if1->sk_ethercom.ec_if; 1994 1995 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 1996 (ifp0->if_flags & IFF_RUNNING)) { 1997 msk_intr_yukon(sc_if0); 1998 } 1999 2000 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2001 (ifp1->if_flags & IFF_RUNNING)) { 2002 msk_intr_yukon(sc_if1); 2003 } 2004 2005 for (;;) { 2006 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2007 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2008 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2009 st_opcode = cur_st->sk_opcode; 2010 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 2011 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2012 BUS_DMASYNC_PREREAD); 2013 break; 2014 } 2015 st_status = le32toh(cur_st->sk_status); 2016 st_len = le16toh(cur_st->sk_len); 2017 st_link = cur_st->sk_link; 2018 st_opcode &= ~SK_Y2_STOPC_OWN; 2019 2020 switch (st_opcode) { 2021 case SK_Y2_STOPC_RXSTAT: 2022 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 2023 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 2024 SK_RXQ1_Y2_PREF_PUTIDX, 2025 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 2026 break; 2027 case SK_Y2_STOPC_TXSTAT: 2028 if (sc_if0) 2029 msk_txeof(sc_if0, st_status 2030 & SK_Y2_ST_TXA1_MSKL); 2031 if (sc_if1) 2032 msk_txeof(sc_if1, 2033 ((st_status & SK_Y2_ST_TXA2_MSKL) 2034 >> SK_Y2_ST_TXA2_SHIFTL) 2035 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 2036 break; 2037 default: 2038 aprint_error("opcode=0x%x\n", st_opcode); 2039 break; 2040 } 2041 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2042 } 2043 2044 #define MSK_STATUS_RING_OWN_CNT(sc) \ 2045 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 2046 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 2047 2048 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 2049 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 2050 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2051 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 2052 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2053 2054 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 2055 } 2056 2057 if (status & SK_Y2_IMR_BMU) { 2058 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2059 claimed = 1; 2060 } 2061 2062 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2063 2064 if (ifp0 != NULL) 2065 if_schedule_deferred_start(ifp0); 2066 if (ifp1 != NULL) 2067 if_schedule_deferred_start(ifp1); 2068 2069 rnd_add_uint32(&sc->rnd_source, status); 2070 2071 if (sc->sk_int_mod_pending) 2072 msk_update_int_mod(sc, 1); 2073 2074 return claimed; 2075 } 2076 2077 void 2078 msk_init_yukon(struct sk_if_softc *sc_if) 2079 { 2080 u_int32_t v; 2081 u_int16_t reg; 2082 struct sk_softc *sc; 2083 int i; 2084 2085 sc = sc_if->sk_softc; 2086 2087 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2088 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2089 2090 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2091 2092 /* GMAC and GPHY Reset */ 2093 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2094 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2095 DELAY(1000); 2096 2097 DPRINTFN(6, ("msk_init_yukon: 2\n")); 2098 2099 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 2100 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2101 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2102 2103 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2104 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2105 2106 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2107 2108 /* unused read of the interrupt source register */ 2109 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2110 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2111 2112 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2113 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2114 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2115 2116 /* MIB Counter Clear Mode set */ 2117 reg |= YU_PAR_MIB_CLR; 2118 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2119 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2120 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2121 2122 /* MIB Counter Clear Mode clear */ 2123 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2124 reg &= ~YU_PAR_MIB_CLR; 2125 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2126 2127 /* receive control reg */ 2128 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2129 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2130 2131 /* transmit control register */ 2132 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2133 2134 /* transmit flow control register */ 2135 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2136 2137 /* transmit parameter register */ 2138 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2139 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2140 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2141 2142 /* serial mode register */ 2143 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2144 reg = YU_SMR_DATA_BLIND(0x1c) | 2145 YU_SMR_MFL_VLAN | 2146 YU_SMR_IPG_DATA(0x1e); 2147 2148 if (sc->sk_type != SK_YUKON_FE && 2149 sc->sk_type != SK_YUKON_FE) 2150 reg |= YU_SMR_MFL_JUMBO; 2151 2152 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2153 2154 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2155 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2156 /* msk_attach calls me before ether_ifattach so check null */ 2157 if (ifp != NULL && ifp->if_sadl != NULL) 2158 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2159 sizeof(sc_if->sk_enaddr)); 2160 /* Setup Yukon's address */ 2161 for (i = 0; i < 3; i++) { 2162 /* Write Source Address 1 (unicast filter) */ 2163 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2164 sc_if->sk_enaddr[i * 2] | 2165 sc_if->sk_enaddr[i * 2 + 1] << 8); 2166 } 2167 2168 for (i = 0; i < 3; i++) { 2169 reg = sk_win_read_2(sc_if->sk_softc, 2170 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2171 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2172 } 2173 2174 /* Set promiscuous mode */ 2175 msk_setpromisc(sc_if); 2176 2177 /* Set multicast filter */ 2178 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2179 msk_setmulti(sc_if); 2180 2181 /* enable interrupt mask for counter overflows */ 2182 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2183 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2184 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2185 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2186 2187 /* Configure RX MAC FIFO Flush Mask */ 2188 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2189 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2190 YU_RXSTAT_JABBER; 2191 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2192 2193 /* Configure RX MAC FIFO */ 2194 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2195 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2196 SK_RFCTL_FIFO_FLUSH_ON); 2197 2198 /* Increase flush threshould to 64 bytes */ 2199 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2200 SK_RFCTL_FIFO_THRESHOLD + 1); 2201 2202 /* Configure TX MAC FIFO */ 2203 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2204 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2205 2206 #if 1 2207 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2208 #endif 2209 DPRINTFN(6, ("msk_init_yukon: end\n")); 2210 } 2211 2212 /* 2213 * Note that to properly initialize any part of the GEnesis chip, 2214 * you first have to take it out of reset mode. 2215 */ 2216 int 2217 msk_init(struct ifnet *ifp) 2218 { 2219 struct sk_if_softc *sc_if = ifp->if_softc; 2220 struct sk_softc *sc = sc_if->sk_softc; 2221 int rc = 0, s; 2222 uint32_t imr, imtimer_ticks; 2223 2224 2225 DPRINTFN(2, ("msk_init\n")); 2226 2227 s = splnet(); 2228 2229 /* Cancel pending I/O and free all RX/TX buffers. */ 2230 msk_stop(ifp,0); 2231 2232 /* Configure I2C registers */ 2233 2234 /* Configure XMAC(s) */ 2235 msk_init_yukon(sc_if); 2236 if ((rc = ether_mediachange(ifp)) != 0) 2237 goto out; 2238 2239 /* Configure transmit arbiter(s) */ 2240 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2241 #if 0 2242 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2243 #endif 2244 2245 /* Configure RAMbuffers */ 2246 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2247 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2248 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2249 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2250 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2251 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2252 2253 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2254 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2255 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2256 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2257 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2258 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2259 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2260 2261 /* Configure BMUs */ 2262 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2263 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2264 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2265 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2266 2267 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2268 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2269 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2270 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2271 2272 /* Make sure the sync transmit queue is disabled. */ 2273 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2274 2275 /* Init descriptors */ 2276 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2277 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2278 "memory for rx buffers\n"); 2279 msk_stop(ifp,0); 2280 splx(s); 2281 return ENOBUFS; 2282 } 2283 2284 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2285 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2286 "memory for tx buffers\n"); 2287 msk_stop(ifp,0); 2288 splx(s); 2289 return ENOBUFS; 2290 } 2291 2292 /* Set interrupt moderation if changed via sysctl. */ 2293 switch (sc->sk_type) { 2294 case SK_YUKON_EC: 2295 case SK_YUKON_EC_U: 2296 case SK_YUKON_EX: 2297 case SK_YUKON_SUPR: 2298 case SK_YUKON_ULTRA2: 2299 case SK_YUKON_OPTIMA: 2300 case SK_YUKON_PRM: 2301 case SK_YUKON_OPTIMA2: 2302 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2303 break; 2304 case SK_YUKON_FE: 2305 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2306 break; 2307 case SK_YUKON_XL: 2308 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2309 break; 2310 default: 2311 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2312 } 2313 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2314 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2315 sk_win_write_4(sc, SK_IMTIMERINIT, 2316 SK_IM_USECS(sc->sk_int_mod)); 2317 aprint_verbose_dev(sc->sk_dev, 2318 "interrupt moderation is %d us\n", sc->sk_int_mod); 2319 } 2320 2321 /* Initialize prefetch engine. */ 2322 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2323 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2324 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2325 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2326 MSK_RX_RING_ADDR(sc_if, 0)); 2327 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2328 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2329 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2330 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2331 2332 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2333 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2334 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2335 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2336 MSK_TX_RING_ADDR(sc_if, 0)); 2337 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2338 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2339 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2340 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2341 2342 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2343 sc_if->sk_cdata.sk_rx_prod); 2344 2345 /* Configure interrupt handling */ 2346 if (sc_if->sk_port == SK_PORT_A) 2347 sc->sk_intrmask |= SK_Y2_INTRS1; 2348 else 2349 sc->sk_intrmask |= SK_Y2_INTRS2; 2350 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2351 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2352 2353 ifp->if_flags |= IFF_RUNNING; 2354 ifp->if_flags &= ~IFF_OACTIVE; 2355 2356 callout_schedule(&sc_if->sk_tick_ch, hz); 2357 2358 out: 2359 splx(s); 2360 return rc; 2361 } 2362 2363 void 2364 msk_stop(struct ifnet *ifp, int disable) 2365 { 2366 struct sk_if_softc *sc_if = ifp->if_softc; 2367 struct sk_softc *sc = sc_if->sk_softc; 2368 struct sk_txmap_entry *dma; 2369 int i; 2370 2371 DPRINTFN(2, ("msk_stop\n")); 2372 2373 callout_stop(&sc_if->sk_tick_ch); 2374 2375 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2376 2377 /* Stop transfer of Tx descriptors */ 2378 2379 /* Stop transfer of Rx descriptors */ 2380 2381 /* Turn off various components of this interface. */ 2382 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2383 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2384 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2385 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2386 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2387 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2388 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2389 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2390 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2391 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2392 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2393 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2394 2395 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2396 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2397 2398 /* Disable interrupts */ 2399 if (sc_if->sk_port == SK_PORT_A) 2400 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2401 else 2402 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2403 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2404 2405 SK_XM_READ_2(sc_if, XM_ISR); 2406 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2407 2408 /* Free RX and TX mbufs still in the queues. */ 2409 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2410 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2411 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2412 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2413 } 2414 } 2415 2416 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2417 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2418 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2419 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2420 #if 1 2421 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2422 sc_if->sk_cdata.sk_tx_map[i], link); 2423 sc_if->sk_cdata.sk_tx_map[i] = 0; 2424 #endif 2425 } 2426 } 2427 2428 #if 1 2429 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2430 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2431 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2432 free(dma, M_DEVBUF); 2433 } 2434 #endif 2435 } 2436 2437 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2438 NULL, NULL); 2439 2440 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2441 NULL, NULL); 2442 2443 #ifdef MSK_DEBUG 2444 void 2445 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2446 { 2447 #define DESC_PRINT(X) \ 2448 if (X) \ 2449 printf("txdesc[%d]." #X "=%#x\n", \ 2450 idx, X); 2451 2452 DESC_PRINT(letoh32(le->sk_addr)); 2453 DESC_PRINT(letoh16(le->sk_len)); 2454 DESC_PRINT(le->sk_ctl); 2455 DESC_PRINT(le->sk_opcode); 2456 #undef DESC_PRINT 2457 } 2458 2459 void 2460 msk_dump_bytes(const char *data, int len) 2461 { 2462 int c, i, j; 2463 2464 for (i = 0; i < len; i += 16) { 2465 printf("%08x ", i); 2466 c = len - i; 2467 if (c > 16) c = 16; 2468 2469 for (j = 0; j < c; j++) { 2470 printf("%02x ", data[i + j] & 0xff); 2471 if ((j & 0xf) == 7 && j > 0) 2472 printf(" "); 2473 } 2474 2475 for (; j < 16; j++) 2476 printf(" "); 2477 printf(" "); 2478 2479 for (j = 0; j < c; j++) { 2480 int ch = data[i + j] & 0xff; 2481 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2482 } 2483 2484 printf("\n"); 2485 2486 if (c < 16) 2487 break; 2488 } 2489 } 2490 2491 void 2492 msk_dump_mbuf(struct mbuf *m) 2493 { 2494 int count = m->m_pkthdr.len; 2495 2496 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2497 2498 while (count > 0 && m) { 2499 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2500 m, m->m_data, m->m_len); 2501 msk_dump_bytes(mtod(m, char *), m->m_len); 2502 2503 count -= m->m_len; 2504 m = m->m_next; 2505 } 2506 } 2507 #endif 2508 2509 static int 2510 msk_sysctl_handler(SYSCTLFN_ARGS) 2511 { 2512 int error, t; 2513 struct sysctlnode node; 2514 struct sk_softc *sc; 2515 2516 node = *rnode; 2517 sc = node.sysctl_data; 2518 t = sc->sk_int_mod; 2519 node.sysctl_data = &t; 2520 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2521 if (error || newp == NULL) 2522 return error; 2523 2524 if (t < SK_IM_MIN || t > SK_IM_MAX) 2525 return EINVAL; 2526 2527 /* update the softc with sysctl-changed value, and mark 2528 for hardware update */ 2529 sc->sk_int_mod = t; 2530 sc->sk_int_mod_pending = 1; 2531 return 0; 2532 } 2533 2534 /* 2535 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2536 * set up in skc_attach() 2537 */ 2538 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2539 { 2540 int rc; 2541 const struct sysctlnode *node; 2542 2543 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2544 0, CTLTYPE_NODE, "msk", 2545 SYSCTL_DESCR("msk interface controls"), 2546 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2547 goto err; 2548 } 2549 2550 msk_root_num = node->sysctl_num; 2551 return; 2552 2553 err: 2554 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2555 } 2556
Indexes created Mon Sep 22 13:09:51 GMT 2025