if_msk.c revision 1.63
1 /* $NetBSD: if_msk.c,v 1.63 2018/06/13 19:37:23 jdolecek Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.65 2008/09/10 14:01:22 blambert Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.63 2018/06/13 19:37:23 jdolecek Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *, int); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 124 void msk_update_int_mod(struct sk_softc *, int); 125 126 int msk_miibus_readreg(device_t, int, int); 127 void msk_miibus_writereg(device_t, int, int, int); 128 void msk_miibus_statchg(struct ifnet *); 129 130 void msk_setmulti(struct sk_if_softc *); 131 void msk_setpromisc(struct sk_if_softc *); 132 void msk_tick(void *); 133 134 /* #define MSK_DEBUG 1 */ 135 #ifdef MSK_DEBUG 136 #define DPRINTF(x) if (mskdebug) printf x 137 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 138 int mskdebug = MSK_DEBUG; 139 140 void msk_dump_txdesc(struct msk_tx_desc *, int); 141 void msk_dump_mbuf(struct mbuf *); 142 void msk_dump_bytes(const char *, int); 143 #else 144 #define DPRINTF(x) 145 #define DPRINTFN(n,x) 146 #endif 147 148 static int msk_sysctl_handler(SYSCTLFN_PROTO); 149 static int msk_root_num; 150 151 /* supported device vendors */ 152 static const struct msk_product { 153 pci_vendor_id_t msk_vendor; 154 pci_product_id_t msk_product; 155 } msk_products[] = { 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 160 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 195 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 196 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 197 }; 198 199 static inline u_int32_t 200 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 201 { 202 return CSR_READ_4(sc, reg); 203 } 204 205 static inline u_int16_t 206 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 207 { 208 return CSR_READ_2(sc, reg); 209 } 210 211 static inline u_int8_t 212 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 213 { 214 return CSR_READ_1(sc, reg); 215 } 216 217 static inline void 218 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 219 { 220 CSR_WRITE_4(sc, reg, x); 221 } 222 223 static inline void 224 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 225 { 226 CSR_WRITE_2(sc, reg, x); 227 } 228 229 static inline void 230 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 231 { 232 CSR_WRITE_1(sc, reg, x); 233 } 234 235 int 236 msk_miibus_readreg(device_t dev, int phy, int reg) 237 { 238 struct sk_if_softc *sc_if = device_private(dev); 239 u_int16_t val; 240 int i; 241 242 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 243 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 244 245 for (i = 0; i < SK_TIMEOUT; i++) { 246 DELAY(1); 247 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 248 if (val & YU_SMICR_READ_VALID) 249 break; 250 } 251 252 if (i == SK_TIMEOUT) { 253 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 254 return (0); 255 } 256 257 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 258 SK_TIMEOUT)); 259 260 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 261 262 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 263 phy, reg, val)); 264 265 return (val); 266 } 267 268 void 269 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 270 { 271 struct sk_if_softc *sc_if = device_private(dev); 272 int i; 273 274 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 275 phy, reg, val)); 276 277 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 278 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 279 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 280 281 for (i = 0; i < SK_TIMEOUT; i++) { 282 DELAY(1); 283 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 284 break; 285 } 286 287 if (i == SK_TIMEOUT) 288 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 289 } 290 291 void 292 msk_miibus_statchg(struct ifnet *ifp) 293 { 294 struct sk_if_softc *sc_if = ifp->if_softc; 295 struct mii_data *mii = &sc_if->sk_mii; 296 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 297 int gpcr; 298 299 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 300 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 301 302 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 303 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 304 /* Set speed. */ 305 gpcr |= YU_GPCR_SPEED_DIS; 306 switch (IFM_SUBTYPE(mii->mii_media_active)) { 307 case IFM_1000_SX: 308 case IFM_1000_LX: 309 case IFM_1000_CX: 310 case IFM_1000_T: 311 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 312 break; 313 case IFM_100_TX: 314 gpcr |= YU_GPCR_SPEED; 315 break; 316 } 317 318 /* Set duplex. */ 319 gpcr |= YU_GPCR_DPLX_DIS; 320 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 321 gpcr |= YU_GPCR_DUPLEX; 322 323 /* Disable flow control. */ 324 gpcr |= YU_GPCR_FCTL_DIS; 325 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 326 } 327 328 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 329 330 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 331 SK_YU_READ_2(sc_if, YUKON_GPCR))); 332 } 333 334 void 335 msk_setmulti(struct sk_if_softc *sc_if) 336 { 337 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 338 u_int32_t hashes[2] = { 0, 0 }; 339 int h; 340 struct ethercom *ec = &sc_if->sk_ethercom; 341 struct ether_multi *enm; 342 struct ether_multistep step; 343 u_int16_t reg; 344 345 /* First, zot all the existing filters. */ 346 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 347 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 350 351 352 /* Now program new ones. */ 353 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 354 reg |= YU_RCR_UFLEN; 355 allmulti: 356 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 357 if ((ifp->if_flags & IFF_PROMISC) != 0) 358 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 359 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 360 hashes[0] = 0xFFFFFFFF; 361 hashes[1] = 0xFFFFFFFF; 362 } 363 } else { 364 /* First find the tail of the list. */ 365 ETHER_FIRST_MULTI(step, ec, enm); 366 while (enm != NULL) { 367 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 368 ETHER_ADDR_LEN)) { 369 ifp->if_flags |= IFF_ALLMULTI; 370 goto allmulti; 371 } 372 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 373 ((1 << SK_HASH_BITS) - 1); 374 if (h < 32) 375 hashes[0] |= (1 << h); 376 else 377 hashes[1] |= (1 << (h - 32)); 378 379 ETHER_NEXT_MULTI(step, enm); 380 } 381 reg |= YU_RCR_MUFLEN; 382 } 383 384 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 385 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 389 } 390 391 void 392 msk_setpromisc(struct sk_if_softc *sc_if) 393 { 394 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 395 396 if (ifp->if_flags & IFF_PROMISC) 397 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 398 YU_RCR_UFLEN | YU_RCR_MUFLEN); 399 else 400 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 401 YU_RCR_UFLEN | YU_RCR_MUFLEN); 402 } 403 404 int 405 msk_init_rx_ring(struct sk_if_softc *sc_if) 406 { 407 struct msk_chain_data *cd = &sc_if->sk_cdata; 408 struct msk_ring_data *rd = sc_if->sk_rdata; 409 int i, nexti; 410 411 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 412 413 for (i = 0; i < MSK_RX_RING_CNT; i++) { 414 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 415 if (i == (MSK_RX_RING_CNT - 1)) 416 nexti = 0; 417 else 418 nexti = i + 1; 419 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 420 } 421 422 for (i = 0; i < MSK_RX_RING_CNT; i++) { 423 if (msk_newbuf(sc_if, i, NULL, 424 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 425 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 426 return (ENOBUFS); 427 } 428 } 429 430 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1; 431 sc_if->sk_cdata.sk_rx_cons = 0; 432 433 return (0); 434 } 435 436 int 437 msk_init_tx_ring(struct sk_if_softc *sc_if) 438 { 439 struct sk_softc *sc = sc_if->sk_softc; 440 struct msk_chain_data *cd = &sc_if->sk_cdata; 441 struct msk_ring_data *rd = sc_if->sk_rdata; 442 bus_dmamap_t dmamap; 443 struct sk_txmap_entry *entry; 444 int i, nexti; 445 446 memset(sc_if->sk_rdata->sk_tx_ring, 0, 447 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 448 449 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 450 for (i = 0; i < MSK_TX_RING_CNT; i++) { 451 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 452 if (i == (MSK_TX_RING_CNT - 1)) 453 nexti = 0; 454 else 455 nexti = i + 1; 456 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 457 458 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 459 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 460 return (ENOBUFS); 461 462 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 463 if (!entry) { 464 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 465 return (ENOBUFS); 466 } 467 entry->dmamap = dmamap; 468 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 469 } 470 471 sc_if->sk_cdata.sk_tx_prod = 0; 472 sc_if->sk_cdata.sk_tx_cons = 0; 473 sc_if->sk_cdata.sk_tx_cnt = 0; 474 475 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 476 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 477 478 return (0); 479 } 480 481 int 482 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 483 bus_dmamap_t dmamap) 484 { 485 struct mbuf *m_new = NULL; 486 struct sk_chain *c; 487 struct msk_rx_desc *r; 488 489 if (m == NULL) { 490 void *buf = NULL; 491 492 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 493 if (m_new == NULL) 494 return (ENOBUFS); 495 496 /* Allocate the jumbo buffer */ 497 buf = msk_jalloc(sc_if); 498 if (buf == NULL) { 499 m_freem(m_new); 500 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 501 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 502 return (ENOBUFS); 503 } 504 505 /* Attach the buffer to the mbuf */ 506 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 507 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 508 } else { 509 /* 510 * We're re-using a previously allocated mbuf; 511 * be sure to re-init pointers and lengths to 512 * default values. 513 */ 514 m_new = m; 515 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 516 m_new->m_data = m_new->m_ext.ext_buf; 517 } 518 m_adj(m_new, ETHER_ALIGN); 519 520 c = &sc_if->sk_cdata.sk_rx_chain[i]; 521 r = c->sk_le; 522 c->sk_mbuf = m_new; 523 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 524 (((vaddr_t)m_new->m_data 525 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 526 r->sk_len = htole16(SK_JLEN); 527 r->sk_ctl = 0; 528 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 529 530 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 531 532 return (0); 533 } 534 535 /* 536 * Memory management for jumbo frames. 537 */ 538 539 int 540 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 541 { 542 struct sk_softc *sc = sc_if->sk_softc; 543 char *ptr, *kva; 544 bus_dma_segment_t seg; 545 int i, rseg, state, error; 546 struct sk_jpool_entry *entry; 547 548 state = error = 0; 549 550 /* Grab a big chunk o' storage. */ 551 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 552 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 553 aprint_error(": can't alloc rx buffers"); 554 return (ENOBUFS); 555 } 556 557 state = 1; 558 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva, 559 BUS_DMA_NOWAIT)) { 560 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 561 error = ENOBUFS; 562 goto out; 563 } 564 565 state = 2; 566 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 567 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 568 aprint_error(": can't create dma map"); 569 error = ENOBUFS; 570 goto out; 571 } 572 573 state = 3; 574 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 575 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 576 aprint_error(": can't load dma map"); 577 error = ENOBUFS; 578 goto out; 579 } 580 581 state = 4; 582 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 583 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 584 585 LIST_INIT(&sc_if->sk_jfree_listhead); 586 LIST_INIT(&sc_if->sk_jinuse_listhead); 587 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 588 589 /* 590 * Now divide it up into 9K pieces and save the addresses 591 * in an array. 592 */ 593 ptr = sc_if->sk_cdata.sk_jumbo_buf; 594 for (i = 0; i < MSK_JSLOTS; i++) { 595 sc_if->sk_cdata.sk_jslots[i] = ptr; 596 ptr += SK_JLEN; 597 entry = malloc(sizeof(struct sk_jpool_entry), 598 M_DEVBUF, M_NOWAIT); 599 if (entry == NULL) { 600 sc_if->sk_cdata.sk_jumbo_buf = NULL; 601 aprint_error(": no memory for jumbo buffer queue!"); 602 error = ENOBUFS; 603 goto out; 604 } 605 entry->slot = i; 606 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 607 entry, jpool_entries); 608 } 609 out: 610 if (error != 0) { 611 switch (state) { 612 case 4: 613 bus_dmamap_unload(sc->sc_dmatag, 614 sc_if->sk_cdata.sk_rx_jumbo_map); 615 case 3: 616 bus_dmamap_destroy(sc->sc_dmatag, 617 sc_if->sk_cdata.sk_rx_jumbo_map); 618 case 2: 619 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 620 case 1: 621 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 622 break; 623 default: 624 break; 625 } 626 } 627 628 return error; 629 } 630 631 /* 632 * Allocate a jumbo buffer. 633 */ 634 void * 635 msk_jalloc(struct sk_if_softc *sc_if) 636 { 637 struct sk_jpool_entry *entry; 638 639 mutex_enter(&sc_if->sk_jpool_mtx); 640 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 641 642 if (entry == NULL) { 643 mutex_exit(&sc_if->sk_jpool_mtx); 644 return NULL; 645 } 646 647 LIST_REMOVE(entry, jpool_entries); 648 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 649 mutex_exit(&sc_if->sk_jpool_mtx); 650 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 651 } 652 653 /* 654 * Release a jumbo buffer. 655 */ 656 void 657 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 658 { 659 struct sk_jpool_entry *entry; 660 struct sk_if_softc *sc; 661 int i; 662 663 /* Extract the softc struct pointer. */ 664 sc = (struct sk_if_softc *)arg; 665 666 if (sc == NULL) 667 panic("msk_jfree: can't find softc pointer!"); 668 669 /* calculate the slot this buffer belongs to */ 670 i = ((vaddr_t)buf 671 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 672 673 if ((i < 0) || (i >= MSK_JSLOTS)) 674 panic("msk_jfree: asked to free buffer that we don't manage!"); 675 676 mutex_enter(&sc->sk_jpool_mtx); 677 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 678 if (entry == NULL) 679 panic("msk_jfree: buffer not in use!"); 680 entry->slot = i; 681 LIST_REMOVE(entry, jpool_entries); 682 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 683 mutex_exit(&sc->sk_jpool_mtx); 684 685 if (__predict_true(m != NULL)) 686 pool_cache_put(mb_cache, m); 687 } 688 689 int 690 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 691 { 692 struct sk_if_softc *sc = ifp->if_softc; 693 int s, error; 694 695 s = splnet(); 696 697 DPRINTFN(2, ("msk_ioctl ETHER\n")); 698 switch (cmd) { 699 case SIOCSIFFLAGS: 700 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 701 break; 702 703 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 704 case IFF_RUNNING: 705 msk_stop(ifp, 1); 706 break; 707 case IFF_UP: 708 msk_init(ifp); 709 break; 710 case IFF_UP | IFF_RUNNING: 711 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 712 msk_setpromisc(sc); 713 msk_setmulti(sc); 714 } else 715 msk_init(ifp); 716 break; 717 } 718 sc->sk_if_flags = ifp->if_flags; 719 break; 720 default: 721 error = ether_ioctl(ifp, cmd, data); 722 if (error == ENETRESET) { 723 error = 0; 724 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 725 ; 726 else if (ifp->if_flags & IFF_RUNNING) { 727 /* 728 * Multicast list has changed; set the hardware 729 * filter accordingly. 730 */ 731 msk_setmulti(sc); 732 } 733 } 734 break; 735 } 736 737 splx(s); 738 return error; 739 } 740 741 void 742 msk_update_int_mod(struct sk_softc *sc, int verbose) 743 { 744 u_int32_t imtimer_ticks; 745 746 /* 747 * Configure interrupt moderation. The moderation timer 748 * defers interrupts specified in the interrupt moderation 749 * timer mask based on the timeout specified in the interrupt 750 * moderation timer init register. Each bit in the timer 751 * register represents one tick, so to specify a timeout in 752 * microseconds, we have to multiply by the correct number of 753 * ticks-per-microsecond. 754 */ 755 switch (sc->sk_type) { 756 case SK_YUKON_EC: 757 case SK_YUKON_EC_U: 758 case SK_YUKON_EX: 759 case SK_YUKON_SUPR: 760 case SK_YUKON_ULTRA2: 761 case SK_YUKON_OPTIMA: 762 case SK_YUKON_PRM: 763 case SK_YUKON_OPTIMA2: 764 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 765 break; 766 case SK_YUKON_FE: 767 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 768 break; 769 case SK_YUKON_XL: 770 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 771 break; 772 default: 773 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 774 } 775 if (verbose) 776 aprint_verbose_dev(sc->sk_dev, 777 "interrupt moderation is %d us\n", sc->sk_int_mod); 778 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 779 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 780 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 781 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 782 sc->sk_int_mod_pending = 0; 783 } 784 785 static int 786 msk_lookup(const struct pci_attach_args *pa) 787 { 788 const struct msk_product *pmsk; 789 790 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 791 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 792 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 793 return 1; 794 } 795 return 0; 796 } 797 798 /* 799 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 800 * IDs against our list and return a device name if we find a match. 801 */ 802 int 803 mskc_probe(device_t parent, cfdata_t match, void *aux) 804 { 805 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 806 807 return msk_lookup(pa); 808 } 809 810 /* 811 * Force the GEnesis into reset, then bring it out of reset. 812 */ 813 void 814 mskc_reset(struct sk_softc *sc) 815 { 816 u_int32_t imtimer_ticks, reg1; 817 int reg; 818 819 DPRINTFN(2, ("mskc_reset\n")); 820 821 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 822 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 823 824 DELAY(1000); 825 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 826 DELAY(2); 827 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 828 sk_win_write_1(sc, SK_TESTCTL1, 2); 829 830 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 831 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 832 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 833 else 834 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 835 836 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 837 sc->sk_type >= SK_YUKON_FE_P) { 838 uint32_t our; 839 840 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 841 842 /* enable all clocks. */ 843 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 844 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 845 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 846 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 847 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 848 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 849 /* Set all bits to 0 except bits 15..12 */ 850 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 851 /* Set to default value */ 852 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 853 } 854 855 /* release PHY from PowerDown/Coma mode. */ 856 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 857 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 858 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 859 else 860 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 861 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 862 863 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 864 sk_win_write_1(sc, SK_Y2_CLKGATE, 865 SK_Y2_CLKGATE_LINK1_GATE_DIS | 866 SK_Y2_CLKGATE_LINK2_GATE_DIS | 867 SK_Y2_CLKGATE_LINK1_CORE_DIS | 868 SK_Y2_CLKGATE_LINK2_CORE_DIS | 869 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 870 else 871 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 872 873 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 874 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 875 DELAY(1000); 876 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 877 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 878 879 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 880 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 881 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 882 } 883 884 sk_win_write_1(sc, SK_TESTCTL1, 1); 885 886 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 887 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 888 CSR_READ_2(sc, SK_LINK_CTRL))); 889 890 /* Disable ASF */ 891 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 892 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 893 894 /* Clear I2C IRQ noise */ 895 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 896 897 /* Disable hardware timer */ 898 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 899 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 900 901 /* Disable descriptor polling */ 902 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 903 904 /* Disable time stamps */ 905 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 906 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 907 908 /* Enable RAM interface */ 909 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 910 for (reg = SK_TO0;reg <= SK_TO11; reg++) 911 sk_win_write_1(sc, reg, 36); 912 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 913 for (reg = SK_TO0;reg <= SK_TO11; reg++) 914 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 915 916 /* 917 * Configure interrupt moderation. The moderation timer 918 * defers interrupts specified in the interrupt moderation 919 * timer mask based on the timeout specified in the interrupt 920 * moderation timer init register. Each bit in the timer 921 * register represents one tick, so to specify a timeout in 922 * microseconds, we have to multiply by the correct number of 923 * ticks-per-microsecond. 924 */ 925 switch (sc->sk_type) { 926 case SK_YUKON_EC: 927 case SK_YUKON_EC_U: 928 case SK_YUKON_EX: 929 case SK_YUKON_SUPR: 930 case SK_YUKON_ULTRA2: 931 case SK_YUKON_OPTIMA: 932 case SK_YUKON_PRM: 933 case SK_YUKON_OPTIMA2: 934 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 935 break; 936 case SK_YUKON_FE: 937 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 938 break; 939 case SK_YUKON_FE_P: 940 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 941 break; 942 case SK_YUKON_XL: 943 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 944 break; 945 default: 946 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 947 break; 948 } 949 950 /* Reset status ring. */ 951 memset(sc->sk_status_ring, 0, 952 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 953 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 954 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 955 sc->sk_status_idx = 0; 956 sc->sk_status_own_idx = 0; 957 958 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 959 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 960 961 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 962 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 963 sc->sk_status_map->dm_segs[0].ds_addr); 964 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 965 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 966 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 967 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 968 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 969 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 970 } else { 971 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 972 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 973 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 974 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 975 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 976 } 977 978 #if 0 979 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 980 #endif 981 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 982 983 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 984 985 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 986 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 987 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 988 989 msk_update_int_mod(sc, 0); 990 } 991 992 int 993 msk_probe(device_t parent, cfdata_t match, void *aux) 994 { 995 struct skc_attach_args *sa = aux; 996 997 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 998 return (0); 999 1000 switch (sa->skc_type) { 1001 case SK_YUKON_XL: 1002 case SK_YUKON_EC_U: 1003 case SK_YUKON_EX: 1004 case SK_YUKON_EC: 1005 case SK_YUKON_FE: 1006 case SK_YUKON_FE_P: 1007 case SK_YUKON_SUPR: 1008 case SK_YUKON_ULTRA2: 1009 case SK_YUKON_OPTIMA: 1010 case SK_YUKON_PRM: 1011 case SK_YUKON_OPTIMA2: 1012 return (1); 1013 } 1014 1015 return (0); 1016 } 1017 1018 void 1019 msk_reset(struct sk_if_softc *sc_if) 1020 { 1021 /* GMAC and GPHY Reset */ 1022 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1023 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1024 DELAY(1000); 1025 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1026 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1027 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1028 } 1029 1030 static bool 1031 msk_resume(device_t dv, const pmf_qual_t *qual) 1032 { 1033 struct sk_if_softc *sc_if = device_private(dv); 1034 1035 msk_init_yukon(sc_if); 1036 return true; 1037 } 1038 1039 /* 1040 * Each XMAC chip is attached as a separate logical IP interface. 1041 * Single port cards will have only one logical interface of course. 1042 */ 1043 void 1044 msk_attach(device_t parent, device_t self, void *aux) 1045 { 1046 struct sk_if_softc *sc_if = device_private(self); 1047 struct sk_softc *sc = device_private(parent); 1048 struct skc_attach_args *sa = aux; 1049 struct ifnet *ifp; 1050 void *kva; 1051 int i; 1052 u_int32_t chunk; 1053 int mii_flags; 1054 1055 sc_if->sk_dev = self; 1056 sc_if->sk_port = sa->skc_port; 1057 sc_if->sk_softc = sc; 1058 sc->sk_if[sa->skc_port] = sc_if; 1059 1060 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1061 1062 /* 1063 * Get station address for this interface. Note that 1064 * dual port cards actually come with three station 1065 * addresses: one for each port, plus an extra. The 1066 * extra one is used by the SysKonnect driver software 1067 * as a 'virtual' station address for when both ports 1068 * are operating in failover mode. Currently we don't 1069 * use this extra address. 1070 */ 1071 for (i = 0; i < ETHER_ADDR_LEN; i++) 1072 sc_if->sk_enaddr[i] = 1073 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1074 1075 aprint_normal(": Ethernet address %s\n", 1076 ether_sprintf(sc_if->sk_enaddr)); 1077 1078 /* 1079 * Set up RAM buffer addresses. The Yukon2 has a small amount 1080 * of SRAM on it, somewhere between 4K and 48K. We need to 1081 * divide this up between the transmitter and receiver. We 1082 * give the receiver 2/3 of the memory (rounded down), and the 1083 * transmitter whatever remains. 1084 */ 1085 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1086 sc_if->sk_rx_ramstart = 0; 1087 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1088 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1089 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1090 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1091 1092 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1093 " tx_ramstart=%#x tx_ramend=%#x\n", 1094 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1095 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1096 1097 /* Allocate the descriptor queues. */ 1098 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1099 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1100 BUS_DMA_NOWAIT)) { 1101 aprint_error(": can't alloc rx buffers\n"); 1102 goto fail; 1103 } 1104 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1105 sc_if->sk_ring_nseg, 1106 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1107 aprint_error(": can't map dma buffers (%zu bytes)\n", 1108 sizeof(struct msk_ring_data)); 1109 goto fail_1; 1110 } 1111 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1112 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1113 &sc_if->sk_ring_map)) { 1114 aprint_error(": can't create dma map\n"); 1115 goto fail_2; 1116 } 1117 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1118 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1119 aprint_error(": can't load dma map\n"); 1120 goto fail_3; 1121 } 1122 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1123 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1124 1125 ifp = &sc_if->sk_ethercom.ec_if; 1126 /* Try to allocate memory for jumbo buffers. */ 1127 if (msk_alloc_jumbo_mem(sc_if)) { 1128 aprint_error(": jumbo buffer allocation failed\n"); 1129 goto fail_3; 1130 } 1131 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1132 if (sc->sk_type != SK_YUKON_FE) 1133 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1134 1135 ifp->if_softc = sc_if; 1136 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1137 ifp->if_ioctl = msk_ioctl; 1138 ifp->if_start = msk_start; 1139 ifp->if_stop = msk_stop; 1140 ifp->if_init = msk_init; 1141 ifp->if_watchdog = msk_watchdog; 1142 ifp->if_baudrate = 1000000000; 1143 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1144 IFQ_SET_READY(&ifp->if_snd); 1145 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1146 1147 msk_reset(sc_if); 1148 1149 /* 1150 * Do miibus setup. 1151 */ 1152 msk_init_yukon(sc_if); 1153 1154 DPRINTFN(2, ("msk_attach: 1\n")); 1155 1156 sc_if->sk_mii.mii_ifp = ifp; 1157 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1158 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1159 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1160 1161 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1162 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1163 ether_mediachange, ether_mediastatus); 1164 mii_flags = MIIF_DOPAUSE; 1165 if (sc->sk_fibertype) 1166 mii_flags |= MIIF_HAVEFIBER; 1167 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1168 MII_OFFSET_ANY, mii_flags); 1169 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1170 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1171 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1172 0, NULL); 1173 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1174 } else 1175 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1176 1177 callout_init(&sc_if->sk_tick_ch, 0); 1178 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1179 callout_schedule(&sc_if->sk_tick_ch, hz); 1180 1181 /* 1182 * Call MI attach routines. 1183 */ 1184 if_attach(ifp); 1185 if_deferred_start_init(ifp, NULL); 1186 ether_ifattach(ifp, sc_if->sk_enaddr); 1187 1188 if (pmf_device_register(self, NULL, msk_resume)) 1189 pmf_class_network_register(self, ifp); 1190 else 1191 aprint_error_dev(self, "couldn't establish power handler\n"); 1192 1193 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1194 RND_TYPE_NET, RND_FLAG_DEFAULT); 1195 1196 DPRINTFN(2, ("msk_attach: end\n")); 1197 return; 1198 1199 fail_3: 1200 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1201 fail_2: 1202 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1203 fail_1: 1204 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1205 fail: 1206 sc->sk_if[sa->skc_port] = NULL; 1207 } 1208 1209 int 1210 msk_detach(device_t self, int flags) 1211 { 1212 struct sk_if_softc *sc_if = (struct sk_if_softc *)self; 1213 struct sk_softc *sc = sc_if->sk_softc; 1214 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1215 1216 if (sc->sk_if[sc_if->sk_port] == NULL) 1217 return (0); 1218 1219 rnd_detach_source(&sc->rnd_source); 1220 1221 callout_halt(&sc_if->sk_tick_ch, NULL); 1222 callout_destroy(&sc_if->sk_tick_ch); 1223 1224 /* Detach any PHYs we might have. */ 1225 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1226 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1227 1228 /* Delete any remaining media. */ 1229 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1230 1231 pmf_device_deregister(self); 1232 1233 ether_ifdetach(ifp); 1234 if_detach(ifp); 1235 1236 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1237 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1238 sizeof(struct msk_ring_data)); 1239 bus_dmamem_free(sc->sc_dmatag, 1240 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1241 sc->sk_if[sc_if->sk_port] = NULL; 1242 1243 return (0); 1244 } 1245 1246 int 1247 mskcprint(void *aux, const char *pnp) 1248 { 1249 struct skc_attach_args *sa = aux; 1250 1251 if (pnp) 1252 aprint_normal("sk port %c at %s", 1253 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1254 else 1255 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1256 return (UNCONF); 1257 } 1258 1259 /* 1260 * Attach the interface. Allocate softc structures, do ifmedia 1261 * setup and ethernet/BPF attach. 1262 */ 1263 void 1264 mskc_attach(device_t parent, device_t self, void *aux) 1265 { 1266 struct sk_softc *sc = device_private(self); 1267 struct pci_attach_args *pa = aux; 1268 struct skc_attach_args skca; 1269 pci_chipset_tag_t pc = pa->pa_pc; 1270 pcireg_t command, memtype; 1271 pci_intr_handle_t ih; 1272 const char *intrstr = NULL; 1273 bus_size_t size; 1274 int rc, sk_nodenum; 1275 u_int8_t hw, pmd; 1276 const char *revstr = NULL; 1277 const struct sysctlnode *node; 1278 void *kva; 1279 char intrbuf[PCI_INTRSTR_LEN]; 1280 1281 DPRINTFN(2, ("begin mskc_attach\n")); 1282 1283 sc->sk_dev = self; 1284 /* 1285 * Handle power management nonsense. 1286 */ 1287 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1288 1289 if (command == 0x01) { 1290 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1291 if (command & SK_PSTATE_MASK) { 1292 u_int32_t iobase, membase, irq; 1293 1294 /* Save important PCI config data. */ 1295 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1296 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1297 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1298 1299 /* Reset the power state. */ 1300 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1301 "mode -- setting to D0\n", 1302 command & SK_PSTATE_MASK); 1303 command &= 0xFFFFFFFC; 1304 pci_conf_write(pc, pa->pa_tag, 1305 SK_PCI_PWRMGMTCTRL, command); 1306 1307 /* Restore PCI config data. */ 1308 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1309 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1310 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1311 } 1312 } 1313 1314 /* 1315 * Map control/status registers. 1316 */ 1317 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1318 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1319 &sc->sk_bhandle, NULL, &size)) { 1320 aprint_error(": can't map mem space\n"); 1321 return; 1322 } 1323 1324 sc->sc_dmatag = pa->pa_dmat; 1325 1326 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1327 command |= PCI_COMMAND_MASTER_ENABLE; 1328 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1329 1330 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1331 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1332 1333 /* bail out here if chip is not recognized */ 1334 if (!(SK_IS_YUKON2(sc))) { 1335 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1336 goto fail_1; 1337 } 1338 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1339 1340 /* Allocate interrupt */ 1341 if (pci_intr_map(pa, &ih)) { 1342 aprint_error(": couldn't map interrupt\n"); 1343 goto fail_1; 1344 } 1345 1346 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1347 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1348 if (sc->sk_intrhand == NULL) { 1349 aprint_error(": couldn't establish interrupt"); 1350 if (intrstr != NULL) 1351 aprint_error(" at %s", intrstr); 1352 aprint_error("\n"); 1353 goto fail_1; 1354 } 1355 sc->sk_pc = pc; 1356 1357 if (bus_dmamem_alloc(sc->sc_dmatag, 1358 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), PAGE_SIZE, 1359 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1360 aprint_error(": can't alloc status buffers\n"); 1361 goto fail_2; 1362 } 1363 1364 if (bus_dmamem_map(sc->sc_dmatag, 1365 &sc->sk_status_seg, sc->sk_status_nseg, 1366 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1367 &kva, BUS_DMA_NOWAIT)) { 1368 aprint_error(": can't map dma buffers (%zu bytes)\n", 1369 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1370 goto fail_3; 1371 } 1372 if (bus_dmamap_create(sc->sc_dmatag, 1373 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1374 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1375 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1376 aprint_error(": can't create dma map\n"); 1377 goto fail_4; 1378 } 1379 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1380 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1381 NULL, BUS_DMA_NOWAIT)) { 1382 aprint_error(": can't load dma map\n"); 1383 goto fail_5; 1384 } 1385 sc->sk_status_ring = (struct msk_status_desc *)kva; 1386 1387 sc->sk_int_mod = SK_IM_DEFAULT; 1388 sc->sk_int_mod_pending = 0; 1389 1390 /* Reset the adapter. */ 1391 mskc_reset(sc); 1392 1393 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1394 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1395 1396 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1397 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1398 sc->sk_fibertype = 1; 1399 1400 switch (sc->sk_type) { 1401 case SK_YUKON_XL: 1402 sc->sk_name = "Yukon-2 XL"; 1403 break; 1404 case SK_YUKON_EC_U: 1405 sc->sk_name = "Yukon-2 EC Ultra"; 1406 break; 1407 case SK_YUKON_EX: 1408 sc->sk_name = "Yukon-2 Extreme"; 1409 break; 1410 case SK_YUKON_EC: 1411 sc->sk_name = "Yukon-2 EC"; 1412 break; 1413 case SK_YUKON_FE: 1414 sc->sk_name = "Yukon-2 FE"; 1415 break; 1416 case SK_YUKON_FE_P: 1417 sc->sk_name = "Yukon-2 FE+"; 1418 break; 1419 case SK_YUKON_SUPR: 1420 sc->sk_name = "Yukon-2 Supreme"; 1421 break; 1422 case SK_YUKON_ULTRA2: 1423 sc->sk_name = "Yukon-2 Ultra 2"; 1424 break; 1425 case SK_YUKON_OPTIMA: 1426 sc->sk_name = "Yukon-2 Optima"; 1427 break; 1428 case SK_YUKON_PRM: 1429 sc->sk_name = "Yukon-2 Optima Prime"; 1430 break; 1431 case SK_YUKON_OPTIMA2: 1432 sc->sk_name = "Yukon-2 Optima 2"; 1433 break; 1434 default: 1435 sc->sk_name = "Yukon (Unknown)"; 1436 } 1437 1438 if (sc->sk_type == SK_YUKON_XL) { 1439 switch (sc->sk_rev) { 1440 case SK_YUKON_XL_REV_A0: 1441 sc->sk_workaround = 0; 1442 revstr = "A0"; 1443 break; 1444 case SK_YUKON_XL_REV_A1: 1445 sc->sk_workaround = SK_WA_4109; 1446 revstr = "A1"; 1447 break; 1448 case SK_YUKON_XL_REV_A2: 1449 sc->sk_workaround = SK_WA_4109; 1450 revstr = "A2"; 1451 break; 1452 case SK_YUKON_XL_REV_A3: 1453 sc->sk_workaround = SK_WA_4109; 1454 revstr = "A3"; 1455 break; 1456 default: 1457 sc->sk_workaround = 0; 1458 break; 1459 } 1460 } 1461 1462 if (sc->sk_type == SK_YUKON_EC) { 1463 switch (sc->sk_rev) { 1464 case SK_YUKON_EC_REV_A1: 1465 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1466 revstr = "A1"; 1467 break; 1468 case SK_YUKON_EC_REV_A2: 1469 sc->sk_workaround = SK_WA_4109; 1470 revstr = "A2"; 1471 break; 1472 case SK_YUKON_EC_REV_A3: 1473 sc->sk_workaround = SK_WA_4109; 1474 revstr = "A3"; 1475 break; 1476 default: 1477 sc->sk_workaround = 0; 1478 break; 1479 } 1480 } 1481 1482 if (sc->sk_type == SK_YUKON_FE) { 1483 sc->sk_workaround = SK_WA_4109; 1484 switch (sc->sk_rev) { 1485 case SK_YUKON_FE_REV_A1: 1486 revstr = "A1"; 1487 break; 1488 case SK_YUKON_FE_REV_A2: 1489 revstr = "A2"; 1490 break; 1491 default: 1492 sc->sk_workaround = 0; 1493 break; 1494 } 1495 } 1496 1497 if (sc->sk_type == SK_YUKON_EC_U) { 1498 sc->sk_workaround = SK_WA_4109; 1499 switch (sc->sk_rev) { 1500 case SK_YUKON_EC_U_REV_A0: 1501 revstr = "A0"; 1502 break; 1503 case SK_YUKON_EC_U_REV_A1: 1504 revstr = "A1"; 1505 break; 1506 case SK_YUKON_EC_U_REV_B0: 1507 revstr = "B0"; 1508 break; 1509 case SK_YUKON_EC_U_REV_B1: 1510 revstr = "B1"; 1511 break; 1512 default: 1513 sc->sk_workaround = 0; 1514 break; 1515 } 1516 } 1517 1518 if (sc->sk_type == SK_YUKON_FE) { 1519 switch (sc->sk_rev) { 1520 case SK_YUKON_FE_REV_A1: 1521 revstr = "A1"; 1522 break; 1523 case SK_YUKON_FE_REV_A2: 1524 revstr = "A2"; 1525 break; 1526 default: 1527 ; 1528 } 1529 } 1530 1531 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1532 revstr = "A0"; 1533 1534 if (sc->sk_type == SK_YUKON_EX) { 1535 switch (sc->sk_rev) { 1536 case SK_YUKON_EX_REV_A0: 1537 revstr = "A0"; 1538 break; 1539 case SK_YUKON_EX_REV_B0: 1540 revstr = "B0"; 1541 break; 1542 default: 1543 ; 1544 } 1545 } 1546 1547 if (sc->sk_type == SK_YUKON_SUPR) { 1548 switch (sc->sk_rev) { 1549 case SK_YUKON_SUPR_REV_A0: 1550 revstr = "A0"; 1551 break; 1552 case SK_YUKON_SUPR_REV_B0: 1553 revstr = "B0"; 1554 break; 1555 case SK_YUKON_SUPR_REV_B1: 1556 revstr = "B1"; 1557 break; 1558 default: 1559 ; 1560 } 1561 } 1562 1563 if (sc->sk_type == SK_YUKON_PRM) { 1564 switch (sc->sk_rev) { 1565 case SK_YUKON_PRM_REV_Z1: 1566 revstr = "Z1"; 1567 break; 1568 case SK_YUKON_PRM_REV_A0: 1569 revstr = "A0"; 1570 break; 1571 default: 1572 ; 1573 } 1574 } 1575 1576 /* Announce the product name. */ 1577 aprint_normal(", %s", sc->sk_name); 1578 if (revstr != NULL) 1579 aprint_normal(" rev. %s", revstr); 1580 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1581 1582 sc->sk_macs = 1; 1583 1584 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1585 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1586 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1587 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1588 sc->sk_macs++; 1589 } 1590 1591 skca.skc_port = SK_PORT_A; 1592 skca.skc_type = sc->sk_type; 1593 skca.skc_rev = sc->sk_rev; 1594 (void)config_found(sc->sk_dev, &skca, mskcprint); 1595 1596 if (sc->sk_macs > 1) { 1597 skca.skc_port = SK_PORT_B; 1598 skca.skc_type = sc->sk_type; 1599 skca.skc_rev = sc->sk_rev; 1600 (void)config_found(sc->sk_dev, &skca, mskcprint); 1601 } 1602 1603 /* Turn on the 'driver is loaded' LED. */ 1604 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1605 1606 /* skc sysctl setup */ 1607 1608 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1609 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1610 SYSCTL_DESCR("mskc per-controller controls"), 1611 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1612 CTL_EOL)) != 0) { 1613 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1614 goto fail_6; 1615 } 1616 1617 sk_nodenum = node->sysctl_num; 1618 1619 /* interrupt moderation time in usecs */ 1620 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1621 CTLFLAG_READWRITE, 1622 CTLTYPE_INT, "int_mod", 1623 SYSCTL_DESCR("msk interrupt moderation timer"), 1624 msk_sysctl_handler, 0, (void *)sc, 1625 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1626 CTL_EOL)) != 0) { 1627 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1628 goto fail_6; 1629 } 1630 1631 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1632 aprint_error_dev(self, "couldn't establish power handler\n"); 1633 1634 return; 1635 1636 fail_6: 1637 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1638 fail_5: 1639 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1640 fail_4: 1641 bus_dmamem_unmap(sc->sc_dmatag, kva, 1642 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1643 fail_3: 1644 bus_dmamem_free(sc->sc_dmatag, 1645 &sc->sk_status_seg, sc->sk_status_nseg); 1646 sc->sk_status_nseg = 0; 1647 fail_2: 1648 pci_intr_disestablish(pc, sc->sk_intrhand); 1649 sc->sk_intrhand = NULL; 1650 fail_1: 1651 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1652 sc->sk_bsize = 0; 1653 } 1654 1655 int 1656 mskc_detach(device_t self, int flags) 1657 { 1658 struct sk_softc *sc = (struct sk_softc *)self; 1659 int rv; 1660 1661 rv = config_detach_children(self, flags); 1662 if (rv != 0) 1663 return (rv); 1664 1665 if (sc->sk_status_nseg > 0) { 1666 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1667 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1668 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1669 bus_dmamem_free(sc->sc_dmatag, 1670 &sc->sk_status_seg, sc->sk_status_nseg); 1671 } 1672 1673 if (sc->sk_intrhand) 1674 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1675 1676 if (sc->sk_bsize > 0) 1677 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1678 1679 return(0); 1680 } 1681 1682 int 1683 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1684 { 1685 struct sk_softc *sc = sc_if->sk_softc; 1686 struct msk_tx_desc *f = NULL; 1687 u_int32_t frag, cur; 1688 int i; 1689 struct sk_txmap_entry *entry; 1690 bus_dmamap_t txmap; 1691 1692 DPRINTFN(2, ("msk_encap\n")); 1693 1694 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1695 if (entry == NULL) { 1696 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1697 return (ENOBUFS); 1698 } 1699 txmap = entry->dmamap; 1700 1701 cur = frag = *txidx; 1702 1703 #ifdef MSK_DEBUG 1704 if (mskdebug >= 2) 1705 msk_dump_mbuf(m_head); 1706 #endif 1707 1708 /* 1709 * Start packing the mbufs in this chain into 1710 * the fragment pointers. Stop when we run out 1711 * of fragments or hit the end of the mbuf chain. 1712 */ 1713 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1714 BUS_DMA_NOWAIT)) { 1715 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1716 return (ENOBUFS); 1717 } 1718 1719 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1720 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1721 bus_dmamap_unload(sc->sc_dmatag, txmap); 1722 return (ENOBUFS); 1723 } 1724 1725 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1726 1727 /* Sync the DMA map. */ 1728 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1729 BUS_DMASYNC_PREWRITE); 1730 1731 for (i = 0; i < txmap->dm_nsegs; i++) { 1732 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1733 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1734 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1735 f->sk_ctl = 0; 1736 if (i == 0) 1737 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1738 else 1739 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1740 cur = frag; 1741 SK_INC(frag, MSK_TX_RING_CNT); 1742 } 1743 1744 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1745 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1746 1747 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1748 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1749 1750 /* Sync descriptors before handing to chip */ 1751 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1753 1754 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1755 1756 /* Sync first descriptor to hand it off */ 1757 MSK_CDTXSYNC(sc_if, *txidx, 1, 1758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1759 1760 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1761 1762 #ifdef MSK_DEBUG 1763 if (mskdebug >= 2) { 1764 struct msk_tx_desc *le; 1765 u_int32_t idx; 1766 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1767 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1768 msk_dump_txdesc(le, idx); 1769 } 1770 } 1771 #endif 1772 1773 *txidx = frag; 1774 1775 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1776 1777 return (0); 1778 } 1779 1780 void 1781 msk_start(struct ifnet *ifp) 1782 { 1783 struct sk_if_softc *sc_if = ifp->if_softc; 1784 struct mbuf *m_head = NULL; 1785 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1786 int pkts = 0; 1787 1788 DPRINTFN(2, ("msk_start\n")); 1789 1790 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1791 IFQ_POLL(&ifp->if_snd, m_head); 1792 if (m_head == NULL) 1793 break; 1794 1795 /* 1796 * Pack the data into the transmit ring. If we 1797 * don't have room, set the OACTIVE flag and wait 1798 * for the NIC to drain the ring. 1799 */ 1800 if (msk_encap(sc_if, m_head, &idx)) { 1801 ifp->if_flags |= IFF_OACTIVE; 1802 break; 1803 } 1804 1805 /* now we are committed to transmit the packet */ 1806 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1807 pkts++; 1808 1809 /* 1810 * If there's a BPF listener, bounce a copy of this frame 1811 * to him. 1812 */ 1813 bpf_mtap(ifp, m_head); 1814 } 1815 if (pkts == 0) 1816 return; 1817 1818 /* Transmit */ 1819 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1820 sc_if->sk_cdata.sk_tx_prod = idx; 1821 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1822 1823 /* Set a timeout in case the chip goes out to lunch. */ 1824 ifp->if_timer = 5; 1825 } 1826 } 1827 1828 void 1829 msk_watchdog(struct ifnet *ifp) 1830 { 1831 struct sk_if_softc *sc_if = ifp->if_softc; 1832 u_int32_t reg; 1833 int idx; 1834 1835 /* 1836 * Reclaim first as there is a possibility of losing Tx completion 1837 * interrupts. 1838 */ 1839 if (sc_if->sk_port == SK_PORT_A) 1840 reg = SK_STAT_BMU_TXA1_RIDX; 1841 else 1842 reg = SK_STAT_BMU_TXA2_RIDX; 1843 1844 idx = sk_win_read_2(sc_if->sk_softc, reg); 1845 if (sc_if->sk_cdata.sk_tx_cons != idx) { 1846 msk_txeof(sc_if, idx); 1847 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1848 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1849 1850 ifp->if_oerrors++; 1851 1852 /* XXX Resets both ports; we shouldn't do that. */ 1853 mskc_reset(sc_if->sk_softc); 1854 msk_reset(sc_if); 1855 msk_init(ifp); 1856 } 1857 } 1858 } 1859 1860 static bool 1861 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1862 { 1863 struct sk_softc *sc = device_private(dv); 1864 1865 DPRINTFN(2, ("mskc_suspend\n")); 1866 1867 /* Turn off the 'driver is loaded' LED. */ 1868 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1869 1870 return true; 1871 } 1872 1873 static bool 1874 mskc_resume(device_t dv, const pmf_qual_t *qual) 1875 { 1876 struct sk_softc *sc = device_private(dv); 1877 1878 DPRINTFN(2, ("mskc_resume\n")); 1879 1880 mskc_reset(sc); 1881 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1882 1883 return true; 1884 } 1885 1886 static __inline int 1887 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1888 { 1889 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1890 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1891 YU_RXSTAT_JABBER)) != 0 || 1892 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1893 YU_RXSTAT_BYTES(stat) != len) 1894 return (0); 1895 1896 return (1); 1897 } 1898 1899 void 1900 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1901 { 1902 struct sk_softc *sc = sc_if->sk_softc; 1903 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1904 struct mbuf *m; 1905 struct sk_chain *cur_rx; 1906 int cur, total_len = len; 1907 bus_dmamap_t dmamap; 1908 1909 DPRINTFN(2, ("msk_rxeof\n")); 1910 1911 cur = sc_if->sk_cdata.sk_rx_cons; 1912 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1913 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 1914 1915 /* Sync the descriptor */ 1916 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1917 1918 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1919 if (cur_rx->sk_mbuf == NULL) 1920 return; 1921 1922 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1923 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1924 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1925 1926 m = cur_rx->sk_mbuf; 1927 cur_rx->sk_mbuf = NULL; 1928 1929 if (total_len < SK_MIN_FRAMELEN || 1930 total_len > ETHER_MAX_LEN_JUMBO || 1931 msk_rxvalid(sc, rxstat, total_len) == 0) { 1932 ifp->if_ierrors++; 1933 msk_newbuf(sc_if, cur, m, dmamap); 1934 return; 1935 } 1936 1937 /* 1938 * Try to allocate a new jumbo buffer. If that fails, copy the 1939 * packet to mbufs and put the jumbo buffer back in the ring 1940 * so it can be re-used. If allocating mbufs fails, then we 1941 * have to drop the packet. 1942 */ 1943 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1944 struct mbuf *m0; 1945 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1946 total_len + ETHER_ALIGN, 0, ifp, NULL); 1947 msk_newbuf(sc_if, cur, m, dmamap); 1948 if (m0 == NULL) { 1949 ifp->if_ierrors++; 1950 return; 1951 } 1952 m_adj(m0, ETHER_ALIGN); 1953 m = m0; 1954 } else { 1955 m_set_rcvif(m, ifp); 1956 m->m_pkthdr.len = m->m_len = total_len; 1957 } 1958 1959 /* pass it on. */ 1960 if_percpuq_enqueue(ifp->if_percpuq, m); 1961 } 1962 1963 void 1964 msk_txeof(struct sk_if_softc *sc_if, int idx) 1965 { 1966 struct sk_softc *sc = sc_if->sk_softc; 1967 struct msk_tx_desc *cur_tx; 1968 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1969 u_int32_t sk_ctl; 1970 struct sk_txmap_entry *entry; 1971 int cons, prog; 1972 1973 DPRINTFN(2, ("msk_txeof\n")); 1974 1975 /* 1976 * Go through our tx ring and free mbufs for those 1977 * frames that have been sent. 1978 */ 1979 cons = sc_if->sk_cdata.sk_tx_cons; 1980 prog = 0; 1981 while (cons != idx) { 1982 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 1983 break; 1984 prog++; 1985 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons]; 1986 1987 MSK_CDTXSYNC(sc_if, cons, 1, 1988 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1989 sk_ctl = cur_tx->sk_ctl; 1990 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD); 1991 #ifdef MSK_DEBUG 1992 if (mskdebug >= 2) 1993 msk_dump_txdesc(cur_tx, cons); 1994 #endif 1995 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 1996 ifp->if_opackets++; 1997 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) { 1998 entry = sc_if->sk_cdata.sk_tx_map[cons]; 1999 2000 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2001 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2002 2003 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2004 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2005 link); 2006 sc_if->sk_cdata.sk_tx_map[cons] = NULL; 2007 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf); 2008 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL; 2009 } 2010 sc_if->sk_cdata.sk_tx_cnt--; 2011 SK_INC(cons, MSK_TX_RING_CNT); 2012 } 2013 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2014 2015 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2016 ifp->if_flags &= ~IFF_OACTIVE; 2017 2018 if (prog > 0) 2019 sc_if->sk_cdata.sk_tx_cons = cons; 2020 } 2021 2022 void 2023 msk_tick(void *xsc_if) 2024 { 2025 struct sk_if_softc *sc_if = xsc_if; 2026 struct mii_data *mii = &sc_if->sk_mii; 2027 int s; 2028 2029 s = splnet(); 2030 mii_tick(mii); 2031 splx(s); 2032 2033 callout_schedule(&sc_if->sk_tick_ch, hz); 2034 } 2035 2036 void 2037 msk_intr_yukon(struct sk_if_softc *sc_if) 2038 { 2039 u_int8_t status; 2040 2041 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2042 /* RX overrun */ 2043 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2044 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2045 SK_RFCTL_RX_FIFO_OVER); 2046 } 2047 /* TX underrun */ 2048 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2049 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2050 SK_TFCTL_TX_FIFO_UNDER); 2051 } 2052 2053 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2054 } 2055 2056 int 2057 msk_intr(void *xsc) 2058 { 2059 struct sk_softc *sc = xsc; 2060 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2061 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2062 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2063 int claimed = 0; 2064 u_int32_t status; 2065 uint32_t st_status; 2066 uint16_t st_len; 2067 uint8_t st_opcode, st_link; 2068 struct msk_status_desc *cur_st; 2069 2070 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2071 if (status == 0) { 2072 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2073 return (0); 2074 } 2075 2076 status = CSR_READ_4(sc, SK_ISR); 2077 2078 if (sc_if0 != NULL) 2079 ifp0 = &sc_if0->sk_ethercom.ec_if; 2080 if (sc_if1 != NULL) 2081 ifp1 = &sc_if1->sk_ethercom.ec_if; 2082 2083 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2084 (ifp0->if_flags & IFF_RUNNING)) { 2085 msk_intr_yukon(sc_if0); 2086 } 2087 2088 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2089 (ifp1->if_flags & IFF_RUNNING)) { 2090 msk_intr_yukon(sc_if1); 2091 } 2092 2093 for (;;) { 2094 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2095 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2096 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2097 st_opcode = cur_st->sk_opcode; 2098 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) { 2099 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2100 BUS_DMASYNC_PREREAD); 2101 break; 2102 } 2103 st_status = le32toh(cur_st->sk_status); 2104 st_len = le16toh(cur_st->sk_len); 2105 st_link = cur_st->sk_link; 2106 st_opcode &= ~SK_Y2_STOPC_OWN; 2107 2108 switch (st_opcode) { 2109 case SK_Y2_STOPC_RXSTAT: 2110 msk_rxeof(sc->sk_if[st_link], st_len, st_status); 2111 SK_IF_WRITE_2(sc->sk_if[st_link], 0, 2112 SK_RXQ1_Y2_PREF_PUTIDX, 2113 sc->sk_if[st_link]->sk_cdata.sk_rx_prod); 2114 break; 2115 case SK_Y2_STOPC_TXSTAT: 2116 if (sc_if0) 2117 msk_txeof(sc_if0, st_status 2118 & SK_Y2_ST_TXA1_MSKL); 2119 if (sc_if1) 2120 msk_txeof(sc_if1, 2121 ((st_status & SK_Y2_ST_TXA2_MSKL) 2122 >> SK_Y2_ST_TXA2_SHIFTL) 2123 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH)); 2124 break; 2125 default: 2126 aprint_error("opcode=0x%x\n", st_opcode); 2127 break; 2128 } 2129 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2130 } 2131 2132 #define MSK_STATUS_RING_OWN_CNT(sc) \ 2133 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \ 2134 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT) 2135 2136 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) { 2137 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx]; 2138 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2139 MSK_CDSTSYNC(sc, sc->sk_status_own_idx, 2140 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2141 2142 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT); 2143 } 2144 2145 if (status & SK_Y2_IMR_BMU) { 2146 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2147 claimed = 1; 2148 } 2149 2150 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2151 2152 if (ifp0 != NULL) 2153 if_schedule_deferred_start(ifp0); 2154 if (ifp1 != NULL) 2155 if_schedule_deferred_start(ifp1); 2156 2157 rnd_add_uint32(&sc->rnd_source, status); 2158 2159 if (sc->sk_int_mod_pending) 2160 msk_update_int_mod(sc, 1); 2161 2162 return claimed; 2163 } 2164 2165 void 2166 msk_init_yukon(struct sk_if_softc *sc_if) 2167 { 2168 u_int32_t v; 2169 u_int16_t reg; 2170 struct sk_softc *sc; 2171 int i; 2172 2173 sc = sc_if->sk_softc; 2174 2175 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2176 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2177 2178 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2179 2180 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2181 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2182 2183 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2184 2185 /* unused read of the interrupt source register */ 2186 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2187 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2188 2189 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2190 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2191 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2192 2193 /* MIB Counter Clear Mode set */ 2194 reg |= YU_PAR_MIB_CLR; 2195 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2196 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2197 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2198 2199 /* MIB Counter Clear Mode clear */ 2200 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2201 reg &= ~YU_PAR_MIB_CLR; 2202 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2203 2204 /* receive control reg */ 2205 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2206 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2207 2208 /* transmit control register */ 2209 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2210 2211 /* transmit flow control register */ 2212 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2213 2214 /* transmit parameter register */ 2215 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2216 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2217 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2218 2219 /* serial mode register */ 2220 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2221 reg = YU_SMR_DATA_BLIND(0x1c) | 2222 YU_SMR_MFL_VLAN | 2223 YU_SMR_IPG_DATA(0x1e); 2224 2225 if (sc->sk_type != SK_YUKON_FE && 2226 sc->sk_type != SK_YUKON_FE_P) 2227 reg |= YU_SMR_MFL_JUMBO; 2228 2229 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2230 2231 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2232 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2233 /* msk_attach calls me before ether_ifattach so check null */ 2234 if (ifp != NULL && ifp->if_sadl != NULL) 2235 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2236 sizeof(sc_if->sk_enaddr)); 2237 /* Setup Yukon's address */ 2238 for (i = 0; i < 3; i++) { 2239 /* Write Source Address 1 (unicast filter) */ 2240 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2241 sc_if->sk_enaddr[i * 2] | 2242 sc_if->sk_enaddr[i * 2 + 1] << 8); 2243 } 2244 2245 for (i = 0; i < 3; i++) { 2246 reg = sk_win_read_2(sc_if->sk_softc, 2247 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2248 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2249 } 2250 2251 /* Set promiscuous mode */ 2252 msk_setpromisc(sc_if); 2253 2254 /* Set multicast filter */ 2255 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2256 msk_setmulti(sc_if); 2257 2258 /* enable interrupt mask for counter overflows */ 2259 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2260 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2261 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2262 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2263 2264 /* Configure RX MAC FIFO Flush Mask */ 2265 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2266 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2267 YU_RXSTAT_JABBER; 2268 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2269 2270 /* Configure RX MAC FIFO */ 2271 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2272 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2273 SK_RFCTL_FIFO_FLUSH_ON); 2274 2275 /* Increase flush threshould to 64 bytes */ 2276 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2277 SK_RFCTL_FIFO_THRESHOLD + 1); 2278 2279 /* Configure TX MAC FIFO */ 2280 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2281 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2282 2283 #if 1 2284 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2285 #endif 2286 DPRINTFN(6, ("msk_init_yukon: end\n")); 2287 } 2288 2289 /* 2290 * Note that to properly initialize any part of the GEnesis chip, 2291 * you first have to take it out of reset mode. 2292 */ 2293 int 2294 msk_init(struct ifnet *ifp) 2295 { 2296 struct sk_if_softc *sc_if = ifp->if_softc; 2297 struct sk_softc *sc = sc_if->sk_softc; 2298 int rc = 0, s; 2299 uint32_t imr, imtimer_ticks; 2300 2301 2302 DPRINTFN(2, ("msk_init\n")); 2303 2304 s = splnet(); 2305 2306 /* Cancel pending I/O and free all RX/TX buffers. */ 2307 msk_stop(ifp,0); 2308 2309 /* Configure I2C registers */ 2310 2311 /* Configure XMAC(s) */ 2312 msk_init_yukon(sc_if); 2313 if ((rc = ether_mediachange(ifp)) != 0) 2314 goto out; 2315 2316 /* Configure transmit arbiter(s) */ 2317 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2318 #if 0 2319 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2320 #endif 2321 2322 /* Configure RAMbuffers */ 2323 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2324 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2325 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2326 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2327 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2328 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2329 2330 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2331 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2332 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2333 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2334 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2335 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2336 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2337 2338 /* Configure BMUs */ 2339 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2341 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2342 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2343 2344 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2346 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2347 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2348 2349 /* Make sure the sync transmit queue is disabled. */ 2350 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2351 2352 /* Init descriptors */ 2353 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2354 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2355 "memory for rx buffers\n"); 2356 msk_stop(ifp,0); 2357 splx(s); 2358 return ENOBUFS; 2359 } 2360 2361 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2362 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2363 "memory for tx buffers\n"); 2364 msk_stop(ifp,0); 2365 splx(s); 2366 return ENOBUFS; 2367 } 2368 2369 /* Set interrupt moderation if changed via sysctl. */ 2370 switch (sc->sk_type) { 2371 case SK_YUKON_EC: 2372 case SK_YUKON_EC_U: 2373 case SK_YUKON_EX: 2374 case SK_YUKON_SUPR: 2375 case SK_YUKON_ULTRA2: 2376 case SK_YUKON_OPTIMA: 2377 case SK_YUKON_PRM: 2378 case SK_YUKON_OPTIMA2: 2379 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2380 break; 2381 case SK_YUKON_FE: 2382 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2383 break; 2384 case SK_YUKON_FE_P: 2385 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2386 break; 2387 case SK_YUKON_XL: 2388 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2389 break; 2390 default: 2391 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2392 } 2393 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2394 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2395 sk_win_write_4(sc, SK_IMTIMERINIT, 2396 SK_IM_USECS(sc->sk_int_mod)); 2397 aprint_verbose_dev(sc->sk_dev, 2398 "interrupt moderation is %d us\n", sc->sk_int_mod); 2399 } 2400 2401 /* Initialize prefetch engine. */ 2402 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2403 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2404 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2405 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2406 MSK_RX_RING_ADDR(sc_if, 0)); 2407 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2408 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2409 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2410 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2411 2412 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2413 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2414 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2415 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2416 MSK_TX_RING_ADDR(sc_if, 0)); 2417 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2418 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2419 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2420 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2421 2422 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2423 sc_if->sk_cdata.sk_rx_prod); 2424 2425 /* Configure interrupt handling */ 2426 if (sc_if->sk_port == SK_PORT_A) 2427 sc->sk_intrmask |= SK_Y2_INTRS1; 2428 else 2429 sc->sk_intrmask |= SK_Y2_INTRS2; 2430 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2431 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2432 2433 ifp->if_flags |= IFF_RUNNING; 2434 ifp->if_flags &= ~IFF_OACTIVE; 2435 2436 callout_schedule(&sc_if->sk_tick_ch, hz); 2437 2438 out: 2439 splx(s); 2440 return rc; 2441 } 2442 2443 void 2444 msk_stop(struct ifnet *ifp, int disable) 2445 { 2446 struct sk_if_softc *sc_if = ifp->if_softc; 2447 struct sk_softc *sc = sc_if->sk_softc; 2448 struct sk_txmap_entry *dma; 2449 int i; 2450 2451 DPRINTFN(2, ("msk_stop\n")); 2452 2453 callout_stop(&sc_if->sk_tick_ch); 2454 2455 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2456 2457 /* Stop transfer of Tx descriptors */ 2458 2459 /* Stop transfer of Rx descriptors */ 2460 2461 /* Turn off various components of this interface. */ 2462 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2463 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2464 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2465 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2466 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2467 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2468 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2469 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2470 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2471 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2472 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2473 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2474 2475 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2476 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2477 2478 /* Disable interrupts */ 2479 if (sc_if->sk_port == SK_PORT_A) 2480 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2481 else 2482 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2483 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2484 2485 SK_XM_READ_2(sc_if, XM_ISR); 2486 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2487 2488 /* Free RX and TX mbufs still in the queues. */ 2489 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2490 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2491 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2492 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2493 } 2494 } 2495 2496 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2497 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2498 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2499 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2500 #if 1 2501 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2502 sc_if->sk_cdata.sk_tx_map[i], link); 2503 sc_if->sk_cdata.sk_tx_map[i] = 0; 2504 #endif 2505 } 2506 } 2507 2508 #if 1 2509 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2510 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2511 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2512 free(dma, M_DEVBUF); 2513 } 2514 #endif 2515 } 2516 2517 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2518 mskc_detach, NULL); 2519 2520 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2521 msk_detach, NULL); 2522 2523 #ifdef MSK_DEBUG 2524 void 2525 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2526 { 2527 #define DESC_PRINT(X) \ 2528 if (X) \ 2529 printf("txdesc[%d]." #X "=%#x\n", \ 2530 idx, X); 2531 2532 DESC_PRINT(letoh32(le->sk_addr)); 2533 DESC_PRINT(letoh16(le->sk_len)); 2534 DESC_PRINT(le->sk_ctl); 2535 DESC_PRINT(le->sk_opcode); 2536 #undef DESC_PRINT 2537 } 2538 2539 void 2540 msk_dump_bytes(const char *data, int len) 2541 { 2542 int c, i, j; 2543 2544 for (i = 0; i < len; i += 16) { 2545 printf("%08x ", i); 2546 c = len - i; 2547 if (c > 16) c = 16; 2548 2549 for (j = 0; j < c; j++) { 2550 printf("%02x ", data[i + j] & 0xff); 2551 if ((j & 0xf) == 7 && j > 0) 2552 printf(" "); 2553 } 2554 2555 for (; j < 16; j++) 2556 printf(" "); 2557 printf(" "); 2558 2559 for (j = 0; j < c; j++) { 2560 int ch = data[i + j] & 0xff; 2561 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2562 } 2563 2564 printf("\n"); 2565 2566 if (c < 16) 2567 break; 2568 } 2569 } 2570 2571 void 2572 msk_dump_mbuf(struct mbuf *m) 2573 { 2574 int count = m->m_pkthdr.len; 2575 2576 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2577 2578 while (count > 0 && m) { 2579 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2580 m, m->m_data, m->m_len); 2581 msk_dump_bytes(mtod(m, char *), m->m_len); 2582 2583 count -= m->m_len; 2584 m = m->m_next; 2585 } 2586 } 2587 #endif 2588 2589 static int 2590 msk_sysctl_handler(SYSCTLFN_ARGS) 2591 { 2592 int error, t; 2593 struct sysctlnode node; 2594 struct sk_softc *sc; 2595 2596 node = *rnode; 2597 sc = node.sysctl_data; 2598 t = sc->sk_int_mod; 2599 node.sysctl_data = &t; 2600 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2601 if (error || newp == NULL) 2602 return error; 2603 2604 if (t < SK_IM_MIN || t > SK_IM_MAX) 2605 return EINVAL; 2606 2607 /* update the softc with sysctl-changed value, and mark 2608 for hardware update */ 2609 sc->sk_int_mod = t; 2610 sc->sk_int_mod_pending = 1; 2611 return 0; 2612 } 2613 2614 /* 2615 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2616 * set up in skc_attach() 2617 */ 2618 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2619 { 2620 int rc; 2621 const struct sysctlnode *node; 2622 2623 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2624 0, CTLTYPE_NODE, "msk", 2625 SYSCTL_DESCR("msk interface controls"), 2626 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2627 goto err; 2628 } 2629 2630 msk_root_num = node->sysctl_num; 2631 return; 2632 2633 err: 2634 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2635 } 2636
Indexes created Wed Sep 24 15:09:51 GMT 2025