if_msk.c revision 1.70
1 /* $NetBSD: if_msk.c,v 1.70 2018/07/03 19:56:01 jdolecek Exp $ */ 2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.70 2018/07/03 19:56:01 jdolecek Exp $"); 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/mutex.h> 63 #include <sys/kernel.h> 64 #include <sys/socket.h> 65 #include <sys/device.h> 66 #include <sys/queue.h> 67 #include <sys/callout.h> 68 #include <sys/sysctl.h> 69 #include <sys/endian.h> 70 #ifdef __NetBSD__ 71 #define letoh16 htole16 72 #define letoh32 htole32 73 #endif 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_types.h> 78 79 #include <net/if_media.h> 80 81 #include <net/bpf.h> 82 #include <sys/rndsource.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/brgphyreg.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 92 #include <dev/pci/if_skreg.h> 93 #include <dev/pci/if_mskvar.h> 94 95 int mskc_probe(device_t, cfdata_t, void *); 96 void mskc_attach(device_t, device_t, void *); 97 int mskc_detach(device_t, int); 98 void mskc_reset(struct sk_softc *); 99 static bool mskc_suspend(device_t, const pmf_qual_t *); 100 static bool mskc_resume(device_t, const pmf_qual_t *); 101 int msk_probe(device_t, cfdata_t, void *); 102 void msk_attach(device_t, device_t, void *); 103 int msk_detach(device_t, int); 104 void msk_reset(struct sk_if_softc *); 105 int mskcprint(void *, const char *); 106 int msk_intr(void *); 107 void msk_intr_yukon(struct sk_if_softc *); 108 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t); 109 void msk_txeof(struct sk_if_softc *); 110 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 111 void msk_start(struct ifnet *); 112 int msk_ioctl(struct ifnet *, u_long, void *); 113 int msk_init(struct ifnet *); 114 void msk_init_yukon(struct sk_if_softc *); 115 void msk_stop(struct ifnet *, int); 116 void msk_watchdog(struct ifnet *); 117 int msk_newbuf(struct sk_if_softc *, struct mbuf *, bus_dmamap_t); 118 int msk_alloc_jumbo_mem(struct sk_if_softc *); 119 void *msk_jalloc(struct sk_if_softc *); 120 void msk_jfree(struct mbuf *, void *, size_t, void *); 121 int msk_init_rx_ring(struct sk_if_softc *); 122 int msk_init_tx_ring(struct sk_if_softc *); 123 void msk_fill_rx_ring(struct sk_if_softc *); 124 125 void msk_update_int_mod(struct sk_softc *, int); 126 127 int msk_miibus_readreg(device_t, int, int); 128 void msk_miibus_writereg(device_t, int, int, int); 129 void msk_miibus_statchg(struct ifnet *); 130 131 void msk_setmulti(struct sk_if_softc *); 132 void msk_setpromisc(struct sk_if_softc *); 133 void msk_tick(void *); 134 135 /* #define MSK_DEBUG 1 */ 136 #ifdef MSK_DEBUG 137 #define DPRINTF(x) if (mskdebug) printf x 138 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x 139 int mskdebug = MSK_DEBUG; 140 141 void msk_dump_txdesc(struct msk_tx_desc *, int); 142 void msk_dump_mbuf(struct mbuf *); 143 void msk_dump_bytes(const char *, int); 144 #else 145 #define DPRINTF(x) 146 #define DPRINTFN(n,x) 147 #endif 148 149 static int msk_sysctl_handler(SYSCTLFN_PROTO); 150 static int msk_root_num; 151 152 /* supported device vendors */ 153 static const struct msk_product { 154 pci_vendor_id_t msk_vendor; 155 pci_product_id_t msk_product; 156 } msk_products[] = { 157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX }, 158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550T_B1 }, 159 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX }, 160 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T }, 161 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU }, 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X }, 163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X }, 165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 }, 166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 }, 167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 }, 168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 }, 169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040 }, 170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8040T }, 171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8042 }, 172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8048 }, 173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 }, 174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 }, 175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 }, 176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 }, 177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055_2 }, 178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 }, 179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8057 }, 180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8058 }, 181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8059 }, 182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU }, 183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X }, 184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU }, 185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X }, 186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8070 }, 187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8071 }, 188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8072 }, 189 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8075 }, 190 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8079 }, 191 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 }, 192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 }, 193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 }, 194 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 }, 195 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 }, 196 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX }, 197 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 } 198 }; 199 200 static inline u_int32_t 201 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 202 { 203 return CSR_READ_4(sc, reg); 204 } 205 206 static inline u_int16_t 207 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 208 { 209 return CSR_READ_2(sc, reg); 210 } 211 212 static inline u_int8_t 213 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 214 { 215 return CSR_READ_1(sc, reg); 216 } 217 218 static inline void 219 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 220 { 221 CSR_WRITE_4(sc, reg, x); 222 } 223 224 static inline void 225 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 226 { 227 CSR_WRITE_2(sc, reg, x); 228 } 229 230 static inline void 231 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 232 { 233 CSR_WRITE_1(sc, reg, x); 234 } 235 236 int 237 msk_miibus_readreg(device_t dev, int phy, int reg) 238 { 239 struct sk_if_softc *sc_if = device_private(dev); 240 u_int16_t val; 241 int i; 242 243 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 244 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 245 246 for (i = 0; i < SK_TIMEOUT; i++) { 247 DELAY(1); 248 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 249 if (val & YU_SMICR_READ_VALID) 250 break; 251 } 252 253 if (i == SK_TIMEOUT) { 254 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 255 return (0); 256 } 257 258 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, 259 SK_TIMEOUT)); 260 261 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 262 263 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 264 phy, reg, val)); 265 266 return (val); 267 } 268 269 void 270 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 271 { 272 struct sk_if_softc *sc_if = device_private(dev); 273 int i; 274 275 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n", 276 phy, reg, val)); 277 278 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 279 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 280 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 281 282 for (i = 0; i < SK_TIMEOUT; i++) { 283 DELAY(1); 284 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 285 break; 286 } 287 288 if (i == SK_TIMEOUT) 289 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 290 } 291 292 void 293 msk_miibus_statchg(struct ifnet *ifp) 294 { 295 struct sk_if_softc *sc_if = ifp->if_softc; 296 struct mii_data *mii = &sc_if->sk_mii; 297 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 298 int gpcr; 299 300 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR); 301 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN); 302 303 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO || 304 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) { 305 /* Set speed. */ 306 gpcr |= YU_GPCR_SPEED_DIS; 307 switch (IFM_SUBTYPE(mii->mii_media_active)) { 308 case IFM_1000_SX: 309 case IFM_1000_LX: 310 case IFM_1000_CX: 311 case IFM_1000_T: 312 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED); 313 break; 314 case IFM_100_TX: 315 gpcr |= YU_GPCR_SPEED; 316 break; 317 } 318 319 /* Set duplex. */ 320 gpcr |= YU_GPCR_DPLX_DIS; 321 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 322 gpcr |= YU_GPCR_DUPLEX; 323 324 /* Disable flow control. */ 325 gpcr |= YU_GPCR_FCTL_DIS; 326 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS); 327 } 328 329 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr); 330 331 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n", 332 SK_YU_READ_2(sc_if, YUKON_GPCR))); 333 } 334 335 void 336 msk_setmulti(struct sk_if_softc *sc_if) 337 { 338 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 339 u_int32_t hashes[2] = { 0, 0 }; 340 int h; 341 struct ethercom *ec = &sc_if->sk_ethercom; 342 struct ether_multi *enm; 343 struct ether_multistep step; 344 u_int16_t reg; 345 346 /* First, zot all the existing filters. */ 347 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 348 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 349 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 350 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 351 352 353 /* Now program new ones. */ 354 reg = SK_YU_READ_2(sc_if, YUKON_RCR); 355 reg |= YU_RCR_UFLEN; 356 allmulti: 357 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 358 if ((ifp->if_flags & IFF_PROMISC) != 0) 359 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 360 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 361 hashes[0] = 0xFFFFFFFF; 362 hashes[1] = 0xFFFFFFFF; 363 } 364 } else { 365 /* First find the tail of the list. */ 366 ETHER_FIRST_MULTI(step, ec, enm); 367 while (enm != NULL) { 368 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 369 ETHER_ADDR_LEN)) { 370 ifp->if_flags |= IFF_ALLMULTI; 371 goto allmulti; 372 } 373 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 374 ((1 << SK_HASH_BITS) - 1); 375 if (h < 32) 376 hashes[0] |= (1 << h); 377 else 378 hashes[1] |= (1 << (h - 32)); 379 380 ETHER_NEXT_MULTI(step, enm); 381 } 382 reg |= YU_RCR_MUFLEN; 383 } 384 385 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 386 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 387 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 388 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 389 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg); 390 } 391 392 void 393 msk_setpromisc(struct sk_if_softc *sc_if) 394 { 395 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 396 397 if (ifp->if_flags & IFF_PROMISC) 398 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 399 YU_RCR_UFLEN | YU_RCR_MUFLEN); 400 else 401 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 402 YU_RCR_UFLEN | YU_RCR_MUFLEN); 403 } 404 405 int 406 msk_init_rx_ring(struct sk_if_softc *sc_if) 407 { 408 struct msk_chain_data *cd = &sc_if->sk_cdata; 409 struct msk_ring_data *rd = sc_if->sk_rdata; 410 int i, nexti; 411 412 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 413 414 for (i = 0; i < MSK_RX_RING_CNT; i++) { 415 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i]; 416 if (i == (MSK_RX_RING_CNT - 1)) 417 nexti = 0; 418 else 419 nexti = i + 1; 420 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti]; 421 } 422 423 sc_if->sk_cdata.sk_rx_prod = 0; 424 sc_if->sk_cdata.sk_rx_cons = 0; 425 sc_if->sk_cdata.sk_rx_cnt = 0; 426 427 msk_fill_rx_ring(sc_if); 428 return (0); 429 } 430 431 int 432 msk_init_tx_ring(struct sk_if_softc *sc_if) 433 { 434 struct sk_softc *sc = sc_if->sk_softc; 435 struct msk_chain_data *cd = &sc_if->sk_cdata; 436 struct msk_ring_data *rd = sc_if->sk_rdata; 437 bus_dmamap_t dmamap; 438 struct sk_txmap_entry *entry; 439 int i, nexti; 440 441 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 442 443 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 444 for (i = 0; i < MSK_TX_RING_CNT; i++) { 445 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i]; 446 if (i == (MSK_TX_RING_CNT - 1)) 447 nexti = 0; 448 else 449 nexti = i + 1; 450 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 451 452 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 453 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) 454 return (ENOBUFS); 455 456 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 457 if (!entry) { 458 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 459 return (ENOBUFS); 460 } 461 entry->dmamap = dmamap; 462 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 463 } 464 465 sc_if->sk_cdata.sk_tx_prod = 0; 466 sc_if->sk_cdata.sk_tx_cons = 0; 467 sc_if->sk_cdata.sk_tx_cnt = 0; 468 469 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT, 470 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 471 472 return (0); 473 } 474 475 int 476 msk_newbuf(struct sk_if_softc *sc_if, struct mbuf *m, 477 bus_dmamap_t dmamap) 478 { 479 struct mbuf *m_new = NULL; 480 struct sk_chain *c; 481 struct msk_rx_desc *r; 482 483 if (m == NULL) { 484 void *buf = NULL; 485 486 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 487 if (m_new == NULL) 488 return (ENOBUFS); 489 490 /* Allocate the jumbo buffer */ 491 buf = msk_jalloc(sc_if); 492 if (buf == NULL) { 493 m_freem(m_new); 494 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 495 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 496 return (ENOBUFS); 497 } 498 499 /* Attach the buffer to the mbuf */ 500 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 501 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if); 502 } else { 503 /* 504 * We're re-using a previously allocated mbuf; 505 * be sure to re-init pointers and lengths to 506 * default values. 507 */ 508 m_new = m; 509 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 510 m_new->m_data = m_new->m_ext.ext_buf; 511 } 512 m_adj(m_new, ETHER_ALIGN); 513 514 c = &sc_if->sk_cdata.sk_rx_chain[sc_if->sk_cdata.sk_rx_prod]; 515 r = c->sk_le; 516 c->sk_mbuf = m_new; 517 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr + 518 (((vaddr_t)m_new->m_data 519 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 520 r->sk_len = htole16(SK_JLEN); 521 r->sk_ctl = 0; 522 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN; 523 524 MSK_CDRXSYNC(sc_if, sc_if->sk_cdata.sk_rx_prod, 525 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 526 527 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT); 528 sc_if->sk_cdata.sk_rx_cnt++; 529 530 return (0); 531 } 532 533 /* 534 * Memory management for jumbo frames. 535 */ 536 537 int 538 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 539 { 540 struct sk_softc *sc = sc_if->sk_softc; 541 char *ptr, *kva; 542 int i, state, error; 543 struct sk_jpool_entry *entry; 544 545 state = error = 0; 546 547 /* Grab a big chunk o' storage. */ 548 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0, 549 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg, 550 BUS_DMA_NOWAIT)) { 551 aprint_error(": can't alloc rx buffers"); 552 return (ENOBUFS); 553 } 554 555 state = 1; 556 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 557 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva, 558 BUS_DMA_NOWAIT)) { 559 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM); 560 error = ENOBUFS; 561 goto out; 562 } 563 564 state = 2; 565 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0, 566 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 567 aprint_error(": can't create dma map"); 568 error = ENOBUFS; 569 goto out; 570 } 571 572 state = 3; 573 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 574 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) { 575 aprint_error(": can't load dma map"); 576 error = ENOBUFS; 577 goto out; 578 } 579 580 state = 4; 581 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 582 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf)); 583 584 LIST_INIT(&sc_if->sk_jfree_listhead); 585 LIST_INIT(&sc_if->sk_jinuse_listhead); 586 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 587 588 /* 589 * Now divide it up into 9K pieces and save the addresses 590 * in an array. 591 */ 592 ptr = sc_if->sk_cdata.sk_jumbo_buf; 593 for (i = 0; i < MSK_JSLOTS; i++) { 594 sc_if->sk_cdata.sk_jslots[i] = ptr; 595 ptr += SK_JLEN; 596 entry = malloc(sizeof(struct sk_jpool_entry), 597 M_DEVBUF, M_NOWAIT); 598 if (entry == NULL) { 599 sc_if->sk_cdata.sk_jumbo_buf = NULL; 600 aprint_error(": no memory for jumbo buffer queue!"); 601 error = ENOBUFS; 602 goto out; 603 } 604 entry->slot = i; 605 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 606 entry, jpool_entries); 607 } 608 out: 609 if (error != 0) { 610 switch (state) { 611 case 4: 612 bus_dmamap_unload(sc->sc_dmatag, 613 sc_if->sk_cdata.sk_rx_jumbo_map); 614 case 3: 615 bus_dmamap_destroy(sc->sc_dmatag, 616 sc_if->sk_cdata.sk_rx_jumbo_map); 617 case 2: 618 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM); 619 case 1: 620 bus_dmamem_free(sc->sc_dmatag, 621 &sc_if->sk_cdata.sk_jumbo_seg, 622 sc_if->sk_cdata.sk_jumbo_nseg); 623 break; 624 default: 625 break; 626 } 627 } 628 629 return error; 630 } 631 632 static void 633 msk_free_jumbo_mem(struct sk_if_softc *sc_if) 634 { 635 struct sk_softc *sc = sc_if->sk_softc; 636 637 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 638 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map); 639 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM); 640 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg, 641 sc_if->sk_cdata.sk_jumbo_nseg); 642 } 643 644 /* 645 * Allocate a jumbo buffer. 646 */ 647 void * 648 msk_jalloc(struct sk_if_softc *sc_if) 649 { 650 struct sk_jpool_entry *entry; 651 652 mutex_enter(&sc_if->sk_jpool_mtx); 653 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 654 655 if (entry == NULL) { 656 mutex_exit(&sc_if->sk_jpool_mtx); 657 return NULL; 658 } 659 660 LIST_REMOVE(entry, jpool_entries); 661 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 662 mutex_exit(&sc_if->sk_jpool_mtx); 663 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 664 } 665 666 /* 667 * Release a jumbo buffer. 668 */ 669 void 670 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 671 { 672 struct sk_jpool_entry *entry; 673 struct sk_if_softc *sc; 674 int i; 675 676 /* Extract the softc struct pointer. */ 677 sc = (struct sk_if_softc *)arg; 678 679 if (sc == NULL) 680 panic("msk_jfree: can't find softc pointer!"); 681 682 /* calculate the slot this buffer belongs to */ 683 i = ((vaddr_t)buf 684 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 685 686 if ((i < 0) || (i >= MSK_JSLOTS)) 687 panic("msk_jfree: asked to free buffer that we don't manage!"); 688 689 mutex_enter(&sc->sk_jpool_mtx); 690 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 691 if (entry == NULL) 692 panic("msk_jfree: buffer not in use!"); 693 entry->slot = i; 694 LIST_REMOVE(entry, jpool_entries); 695 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 696 mutex_exit(&sc->sk_jpool_mtx); 697 698 if (__predict_true(m != NULL)) 699 pool_cache_put(mb_cache, m); 700 } 701 702 int 703 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data) 704 { 705 struct sk_if_softc *sc = ifp->if_softc; 706 int s, error; 707 708 s = splnet(); 709 710 DPRINTFN(2, ("msk_ioctl ETHER\n")); 711 switch (cmd) { 712 case SIOCSIFFLAGS: 713 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 714 break; 715 716 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 717 case IFF_RUNNING: 718 msk_stop(ifp, 1); 719 break; 720 case IFF_UP: 721 msk_init(ifp); 722 break; 723 case IFF_UP | IFF_RUNNING: 724 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) { 725 msk_setpromisc(sc); 726 msk_setmulti(sc); 727 } else 728 msk_init(ifp); 729 break; 730 } 731 sc->sk_if_flags = ifp->if_flags; 732 break; 733 default: 734 error = ether_ioctl(ifp, cmd, data); 735 if (error == ENETRESET) { 736 error = 0; 737 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 738 ; 739 else if (ifp->if_flags & IFF_RUNNING) { 740 /* 741 * Multicast list has changed; set the hardware 742 * filter accordingly. 743 */ 744 msk_setmulti(sc); 745 } 746 } 747 break; 748 } 749 750 splx(s); 751 return error; 752 } 753 754 void 755 msk_update_int_mod(struct sk_softc *sc, int verbose) 756 { 757 u_int32_t imtimer_ticks; 758 759 /* 760 * Configure interrupt moderation. The moderation timer 761 * defers interrupts specified in the interrupt moderation 762 * timer mask based on the timeout specified in the interrupt 763 * moderation timer init register. Each bit in the timer 764 * register represents one tick, so to specify a timeout in 765 * microseconds, we have to multiply by the correct number of 766 * ticks-per-microsecond. 767 */ 768 switch (sc->sk_type) { 769 case SK_YUKON_EC: 770 case SK_YUKON_EC_U: 771 case SK_YUKON_EX: 772 case SK_YUKON_SUPR: 773 case SK_YUKON_ULTRA2: 774 case SK_YUKON_OPTIMA: 775 case SK_YUKON_PRM: 776 case SK_YUKON_OPTIMA2: 777 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 778 break; 779 case SK_YUKON_FE: 780 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 781 break; 782 case SK_YUKON_FE_P: 783 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 784 break; 785 case SK_YUKON_XL: 786 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 787 break; 788 default: 789 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 790 } 791 if (verbose) 792 aprint_verbose_dev(sc->sk_dev, 793 "interrupt moderation is %d us\n", sc->sk_int_mod); 794 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 795 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 796 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 797 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 798 sc->sk_int_mod_pending = 0; 799 } 800 801 static int 802 msk_lookup(const struct pci_attach_args *pa) 803 { 804 const struct msk_product *pmsk; 805 806 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) { 807 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor && 808 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product) 809 return 1; 810 } 811 return 0; 812 } 813 814 /* 815 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 816 * IDs against our list and return a device name if we find a match. 817 */ 818 int 819 mskc_probe(device_t parent, cfdata_t match, void *aux) 820 { 821 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 822 823 return msk_lookup(pa); 824 } 825 826 /* 827 * Force the GEnesis into reset, then bring it out of reset. 828 */ 829 void 830 mskc_reset(struct sk_softc *sc) 831 { 832 u_int32_t imtimer_ticks, reg1; 833 int reg; 834 835 DPRINTFN(2, ("mskc_reset\n")); 836 837 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); 838 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); 839 840 DELAY(1000); 841 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); 842 DELAY(2); 843 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 844 sk_win_write_1(sc, SK_TESTCTL1, 2); 845 846 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 847 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 848 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 849 else 850 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 851 852 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX || 853 sc->sk_type >= SK_YUKON_FE_P) { 854 uint32_t our; 855 856 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON); 857 858 /* enable all clocks. */ 859 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0); 860 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4)); 861 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST| 862 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN| 863 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY| 864 SK_Y2_REG4_ASPM_CLKRUN_REQUEST); 865 /* Set all bits to 0 except bits 15..12 */ 866 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our); 867 /* Set to default value */ 868 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0); 869 } 870 871 /* release PHY from PowerDown/Coma mode. */ 872 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1)); 873 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 874 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 875 else 876 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA); 877 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1); 878 879 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1) 880 sk_win_write_1(sc, SK_Y2_CLKGATE, 881 SK_Y2_CLKGATE_LINK1_GATE_DIS | 882 SK_Y2_CLKGATE_LINK2_GATE_DIS | 883 SK_Y2_CLKGATE_LINK1_CORE_DIS | 884 SK_Y2_CLKGATE_LINK2_CORE_DIS | 885 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS); 886 else 887 sk_win_write_1(sc, SK_Y2_CLKGATE, 0); 888 889 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 890 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); 891 DELAY(1000); 892 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 893 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); 894 895 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) { 896 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX | 897 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO); 898 } 899 900 sk_win_write_1(sc, SK_TESTCTL1, 1); 901 902 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR))); 903 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n", 904 CSR_READ_2(sc, SK_LINK_CTRL))); 905 906 /* Disable ASF */ 907 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); 908 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); 909 910 /* Clear I2C IRQ noise */ 911 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 912 913 /* Disable hardware timer */ 914 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); 915 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); 916 917 /* Disable descriptor polling */ 918 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 919 920 /* Disable time stamps */ 921 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); 922 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); 923 924 /* Enable RAM interface */ 925 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 926 for (reg = SK_TO0;reg <= SK_TO11; reg++) 927 sk_win_write_1(sc, reg, 36); 928 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET); 929 for (reg = SK_TO0;reg <= SK_TO11; reg++) 930 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36); 931 932 /* 933 * Configure interrupt moderation. The moderation timer 934 * defers interrupts specified in the interrupt moderation 935 * timer mask based on the timeout specified in the interrupt 936 * moderation timer init register. Each bit in the timer 937 * register represents one tick, so to specify a timeout in 938 * microseconds, we have to multiply by the correct number of 939 * ticks-per-microsecond. 940 */ 941 switch (sc->sk_type) { 942 case SK_YUKON_EC: 943 case SK_YUKON_EC_U: 944 case SK_YUKON_EX: 945 case SK_YUKON_SUPR: 946 case SK_YUKON_ULTRA2: 947 case SK_YUKON_OPTIMA: 948 case SK_YUKON_PRM: 949 case SK_YUKON_OPTIMA2: 950 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 951 break; 952 case SK_YUKON_FE: 953 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 954 break; 955 case SK_YUKON_FE_P: 956 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 957 break; 958 case SK_YUKON_XL: 959 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 960 break; 961 default: 962 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 963 break; 964 } 965 966 /* Reset status ring. */ 967 memset(sc->sk_status_ring, 0, 968 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 969 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0, 970 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD); 971 sc->sk_status_idx = 0; 972 sc->sk_status_own_idx = 0; 973 974 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET); 975 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET); 976 977 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1); 978 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO, 979 sc->sk_status_map->dm_segs[0].ds_addr); 980 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI, 981 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32); 982 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) { 983 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK); 984 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21); 985 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07); 986 } else { 987 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a); 988 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10); 989 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 990 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04); 991 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */ 992 } 993 994 #if 0 995 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100)); 996 #endif 997 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000)); 998 999 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON); 1000 1001 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START); 1002 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START); 1003 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START); 1004 1005 msk_update_int_mod(sc, 0); 1006 } 1007 1008 int 1009 msk_probe(device_t parent, cfdata_t match, void *aux) 1010 { 1011 struct skc_attach_args *sa = aux; 1012 1013 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1014 return (0); 1015 1016 switch (sa->skc_type) { 1017 case SK_YUKON_XL: 1018 case SK_YUKON_EC_U: 1019 case SK_YUKON_EX: 1020 case SK_YUKON_EC: 1021 case SK_YUKON_FE: 1022 case SK_YUKON_FE_P: 1023 case SK_YUKON_SUPR: 1024 case SK_YUKON_ULTRA2: 1025 case SK_YUKON_OPTIMA: 1026 case SK_YUKON_PRM: 1027 case SK_YUKON_OPTIMA2: 1028 return (1); 1029 } 1030 1031 return (0); 1032 } 1033 1034 void 1035 msk_reset(struct sk_if_softc *sc_if) 1036 { 1037 /* GMAC and GPHY Reset */ 1038 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 1039 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 1040 DELAY(1000); 1041 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR); 1042 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 1043 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 1044 } 1045 1046 static bool 1047 msk_resume(device_t dv, const pmf_qual_t *qual) 1048 { 1049 struct sk_if_softc *sc_if = device_private(dv); 1050 1051 msk_init_yukon(sc_if); 1052 return true; 1053 } 1054 1055 /* 1056 * Each XMAC chip is attached as a separate logical IP interface. 1057 * Single port cards will have only one logical interface of course. 1058 */ 1059 void 1060 msk_attach(device_t parent, device_t self, void *aux) 1061 { 1062 struct sk_if_softc *sc_if = device_private(self); 1063 struct sk_softc *sc = device_private(parent); 1064 struct skc_attach_args *sa = aux; 1065 struct ifnet *ifp; 1066 void *kva; 1067 int i; 1068 u_int32_t chunk; 1069 int mii_flags; 1070 1071 sc_if->sk_dev = self; 1072 sc_if->sk_port = sa->skc_port; 1073 sc_if->sk_softc = sc; 1074 sc->sk_if[sa->skc_port] = sc_if; 1075 1076 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port)); 1077 1078 /* 1079 * Get station address for this interface. Note that 1080 * dual port cards actually come with three station 1081 * addresses: one for each port, plus an extra. The 1082 * extra one is used by the SysKonnect driver software 1083 * as a 'virtual' station address for when both ports 1084 * are operating in failover mode. Currently we don't 1085 * use this extra address. 1086 */ 1087 for (i = 0; i < ETHER_ADDR_LEN; i++) 1088 sc_if->sk_enaddr[i] = 1089 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1090 1091 aprint_normal(": Ethernet address %s\n", 1092 ether_sprintf(sc_if->sk_enaddr)); 1093 1094 /* 1095 * Set up RAM buffer addresses. The Yukon2 has a small amount 1096 * of SRAM on it, somewhere between 4K and 48K. We need to 1097 * divide this up between the transmitter and receiver. We 1098 * give the receiver 2/3 of the memory (rounded down), and the 1099 * transmitter whatever remains. 1100 */ 1101 chunk = (2 * (sc->sk_ramsize / sizeof(u_int64_t)) / 3) & ~0xff; 1102 sc_if->sk_rx_ramstart = 0; 1103 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1; 1104 chunk = (sc->sk_ramsize / sizeof(u_int64_t)) - chunk; 1105 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1; 1106 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1; 1107 1108 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1109 " tx_ramstart=%#x tx_ramend=%#x\n", 1110 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1111 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1112 1113 /* Allocate the descriptor queues. */ 1114 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data), 1115 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg, 1116 BUS_DMA_NOWAIT)) { 1117 aprint_error(": can't alloc rx buffers\n"); 1118 goto fail; 1119 } 1120 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg, 1121 sc_if->sk_ring_nseg, 1122 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1123 aprint_error(": can't map dma buffers (%zu bytes)\n", 1124 sizeof(struct msk_ring_data)); 1125 goto fail_1; 1126 } 1127 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1, 1128 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT, 1129 &sc_if->sk_ring_map)) { 1130 aprint_error(": can't create dma map\n"); 1131 goto fail_2; 1132 } 1133 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1134 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1135 aprint_error(": can't load dma map\n"); 1136 goto fail_3; 1137 } 1138 sc_if->sk_rdata = (struct msk_ring_data *)kva; 1139 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data)); 1140 1141 if (sc->sk_type != SK_YUKON_FE && 1142 sc->sk_type != SK_YUKON_FE_P) 1143 sc_if->sk_pktlen = SK_JLEN; 1144 else 1145 sc_if->sk_pktlen = MCLBYTES; 1146 1147 /* Try to allocate memory for jumbo buffers. */ 1148 if (msk_alloc_jumbo_mem(sc_if)) { 1149 aprint_error(": jumbo buffer allocation failed\n"); 1150 goto fail_3; 1151 } 1152 1153 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1154 if (sc->sk_type != SK_YUKON_FE && 1155 sc->sk_type != SK_YUKON_FE_P) 1156 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1157 1158 ifp = &sc_if->sk_ethercom.ec_if; 1159 ifp->if_softc = sc_if; 1160 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1161 ifp->if_ioctl = msk_ioctl; 1162 ifp->if_start = msk_start; 1163 ifp->if_stop = msk_stop; 1164 ifp->if_init = msk_init; 1165 ifp->if_watchdog = msk_watchdog; 1166 ifp->if_baudrate = 1000000000; 1167 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1168 IFQ_SET_READY(&ifp->if_snd); 1169 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1170 1171 msk_reset(sc_if); 1172 1173 /* 1174 * Do miibus setup. 1175 */ 1176 msk_init_yukon(sc_if); 1177 1178 DPRINTFN(2, ("msk_attach: 1\n")); 1179 1180 sc_if->sk_mii.mii_ifp = ifp; 1181 sc_if->sk_mii.mii_readreg = msk_miibus_readreg; 1182 sc_if->sk_mii.mii_writereg = msk_miibus_writereg; 1183 sc_if->sk_mii.mii_statchg = msk_miibus_statchg; 1184 1185 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1186 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1187 ether_mediachange, ether_mediastatus); 1188 mii_flags = MIIF_DOPAUSE; 1189 if (sc->sk_fibertype) 1190 mii_flags |= MIIF_HAVEFIBER; 1191 mii_attach(self, &sc_if->sk_mii, 0xffffffff, 0, 1192 MII_OFFSET_ANY, mii_flags); 1193 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1194 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1195 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1196 0, NULL); 1197 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1198 } else 1199 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1200 1201 callout_init(&sc_if->sk_tick_ch, 0); 1202 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if); 1203 callout_schedule(&sc_if->sk_tick_ch, hz); 1204 1205 /* 1206 * Call MI attach routines. 1207 */ 1208 if_attach(ifp); 1209 if_deferred_start_init(ifp, NULL); 1210 ether_ifattach(ifp, sc_if->sk_enaddr); 1211 1212 if (pmf_device_register(self, NULL, msk_resume)) 1213 pmf_class_network_register(self, ifp); 1214 else 1215 aprint_error_dev(self, "couldn't establish power handler\n"); 1216 1217 if (sc->rnd_attached++ == 0) { 1218 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1219 RND_TYPE_NET, RND_FLAG_DEFAULT); 1220 } 1221 1222 DPRINTFN(2, ("msk_attach: end\n")); 1223 return; 1224 1225 fail_3: 1226 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1227 fail_2: 1228 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data)); 1229 fail_1: 1230 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1231 fail: 1232 sc->sk_if[sa->skc_port] = NULL; 1233 } 1234 1235 int 1236 msk_detach(device_t self, int flags) 1237 { 1238 struct sk_if_softc *sc_if = device_private(self); 1239 struct sk_softc *sc = sc_if->sk_softc; 1240 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1241 1242 if (sc->sk_if[sc_if->sk_port] == NULL) 1243 return (0); 1244 1245 msk_stop(ifp, 0); 1246 1247 if (--sc->rnd_attached == 0) 1248 rnd_detach_source(&sc->rnd_source); 1249 1250 callout_halt(&sc_if->sk_tick_ch, NULL); 1251 callout_destroy(&sc_if->sk_tick_ch); 1252 1253 /* Detach any PHYs we might have. */ 1254 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL) 1255 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1256 1257 /* Delete any remaining media. */ 1258 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY); 1259 1260 pmf_device_deregister(self); 1261 1262 ether_ifdetach(ifp); 1263 if_detach(ifp); 1264 1265 msk_free_jumbo_mem(sc_if); 1266 1267 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata, 1268 sizeof(struct msk_ring_data)); 1269 bus_dmamem_free(sc->sc_dmatag, 1270 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg); 1271 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1272 sc->sk_if[sc_if->sk_port] = NULL; 1273 1274 return (0); 1275 } 1276 1277 int 1278 mskcprint(void *aux, const char *pnp) 1279 { 1280 struct skc_attach_args *sa = aux; 1281 1282 if (pnp) 1283 aprint_normal("msk port %c at %s", 1284 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1285 else 1286 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1287 return (UNCONF); 1288 } 1289 1290 /* 1291 * Attach the interface. Allocate softc structures, do ifmedia 1292 * setup and ethernet/BPF attach. 1293 */ 1294 void 1295 mskc_attach(device_t parent, device_t self, void *aux) 1296 { 1297 struct sk_softc *sc = device_private(self); 1298 struct pci_attach_args *pa = aux; 1299 struct skc_attach_args skca; 1300 pci_chipset_tag_t pc = pa->pa_pc; 1301 pcireg_t command, memtype; 1302 pci_intr_handle_t ih; 1303 const char *intrstr = NULL; 1304 bus_size_t size; 1305 int rc, sk_nodenum; 1306 u_int8_t hw, pmd; 1307 const char *revstr = NULL; 1308 const struct sysctlnode *node; 1309 void *kva; 1310 char intrbuf[PCI_INTRSTR_LEN]; 1311 1312 DPRINTFN(2, ("begin mskc_attach\n")); 1313 1314 sc->sk_dev = self; 1315 /* 1316 * Handle power management nonsense. 1317 */ 1318 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1319 1320 if (command == 0x01) { 1321 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1322 if (command & SK_PSTATE_MASK) { 1323 u_int32_t iobase, membase, irq; 1324 1325 /* Save important PCI config data. */ 1326 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1327 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1328 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1329 1330 /* Reset the power state. */ 1331 aprint_normal_dev(sc->sk_dev, "chip is in D%d power " 1332 "mode -- setting to D0\n", 1333 command & SK_PSTATE_MASK); 1334 command &= 0xFFFFFFFC; 1335 pci_conf_write(pc, pa->pa_tag, 1336 SK_PCI_PWRMGMTCTRL, command); 1337 1338 /* Restore PCI config data. */ 1339 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1340 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1341 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1342 } 1343 } 1344 1345 /* 1346 * Map control/status registers. 1347 */ 1348 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1349 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag, 1350 &sc->sk_bhandle, NULL, &size)) { 1351 aprint_error(": can't map mem space\n"); 1352 return; 1353 } 1354 1355 sc->sc_dmatag = pa->pa_dmat; 1356 1357 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1358 command |= PCI_COMMAND_MASTER_ENABLE; 1359 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1360 1361 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1362 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1363 1364 /* bail out here if chip is not recognized */ 1365 if (!(SK_IS_YUKON2(sc))) { 1366 aprint_error(": unknown chip type: %d\n", sc->sk_type); 1367 goto fail_1; 1368 } 1369 DPRINTFN(2, ("mskc_attach: allocate interrupt\n")); 1370 1371 /* Allocate interrupt */ 1372 if (pci_intr_map(pa, &ih)) { 1373 aprint_error(": couldn't map interrupt\n"); 1374 goto fail_1; 1375 } 1376 1377 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1378 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc); 1379 if (sc->sk_intrhand == NULL) { 1380 aprint_error(": couldn't establish interrupt"); 1381 if (intrstr != NULL) 1382 aprint_error(" at %s", intrstr); 1383 aprint_error("\n"); 1384 goto fail_1; 1385 } 1386 sc->sk_pc = pc; 1387 1388 if (bus_dmamem_alloc(sc->sc_dmatag, 1389 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1390 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1391 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) { 1392 aprint_error(": can't alloc status buffers\n"); 1393 goto fail_2; 1394 } 1395 1396 if (bus_dmamem_map(sc->sc_dmatag, 1397 &sc->sk_status_seg, sc->sk_status_nseg, 1398 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1399 &kva, BUS_DMA_NOWAIT)) { 1400 aprint_error(": can't map dma buffers (%zu bytes)\n", 1401 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1402 goto fail_3; 1403 } 1404 if (bus_dmamap_create(sc->sc_dmatag, 1405 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1, 1406 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0, 1407 BUS_DMA_NOWAIT, &sc->sk_status_map)) { 1408 aprint_error(": can't create dma map\n"); 1409 goto fail_4; 1410 } 1411 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva, 1412 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1413 NULL, BUS_DMA_NOWAIT)) { 1414 aprint_error(": can't load dma map\n"); 1415 goto fail_5; 1416 } 1417 sc->sk_status_ring = (struct msk_status_desc *)kva; 1418 1419 sc->sk_int_mod = SK_IM_DEFAULT; 1420 sc->sk_int_mod_pending = 0; 1421 1422 /* Reset the adapter. */ 1423 mskc_reset(sc); 1424 1425 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096; 1426 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024)); 1427 1428 pmd = sk_win_read_1(sc, SK_PMDTYPE); 1429 if (pmd == 'L' || pmd == 'S' || pmd == 'P') 1430 sc->sk_fibertype = 1; 1431 1432 switch (sc->sk_type) { 1433 case SK_YUKON_XL: 1434 sc->sk_name = "Yukon-2 XL"; 1435 break; 1436 case SK_YUKON_EC_U: 1437 sc->sk_name = "Yukon-2 EC Ultra"; 1438 break; 1439 case SK_YUKON_EX: 1440 sc->sk_name = "Yukon-2 Extreme"; 1441 break; 1442 case SK_YUKON_EC: 1443 sc->sk_name = "Yukon-2 EC"; 1444 break; 1445 case SK_YUKON_FE: 1446 sc->sk_name = "Yukon-2 FE"; 1447 break; 1448 case SK_YUKON_FE_P: 1449 sc->sk_name = "Yukon-2 FE+"; 1450 break; 1451 case SK_YUKON_SUPR: 1452 sc->sk_name = "Yukon-2 Supreme"; 1453 break; 1454 case SK_YUKON_ULTRA2: 1455 sc->sk_name = "Yukon-2 Ultra 2"; 1456 break; 1457 case SK_YUKON_OPTIMA: 1458 sc->sk_name = "Yukon-2 Optima"; 1459 break; 1460 case SK_YUKON_PRM: 1461 sc->sk_name = "Yukon-2 Optima Prime"; 1462 break; 1463 case SK_YUKON_OPTIMA2: 1464 sc->sk_name = "Yukon-2 Optima 2"; 1465 break; 1466 default: 1467 sc->sk_name = "Yukon (Unknown)"; 1468 } 1469 1470 if (sc->sk_type == SK_YUKON_XL) { 1471 switch (sc->sk_rev) { 1472 case SK_YUKON_XL_REV_A0: 1473 sc->sk_workaround = 0; 1474 revstr = "A0"; 1475 break; 1476 case SK_YUKON_XL_REV_A1: 1477 sc->sk_workaround = SK_WA_4109; 1478 revstr = "A1"; 1479 break; 1480 case SK_YUKON_XL_REV_A2: 1481 sc->sk_workaround = SK_WA_4109; 1482 revstr = "A2"; 1483 break; 1484 case SK_YUKON_XL_REV_A3: 1485 sc->sk_workaround = SK_WA_4109; 1486 revstr = "A3"; 1487 break; 1488 default: 1489 sc->sk_workaround = 0; 1490 break; 1491 } 1492 } 1493 1494 if (sc->sk_type == SK_YUKON_EC) { 1495 switch (sc->sk_rev) { 1496 case SK_YUKON_EC_REV_A1: 1497 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109; 1498 revstr = "A1"; 1499 break; 1500 case SK_YUKON_EC_REV_A2: 1501 sc->sk_workaround = SK_WA_4109; 1502 revstr = "A2"; 1503 break; 1504 case SK_YUKON_EC_REV_A3: 1505 sc->sk_workaround = SK_WA_4109; 1506 revstr = "A3"; 1507 break; 1508 default: 1509 sc->sk_workaround = 0; 1510 break; 1511 } 1512 } 1513 1514 if (sc->sk_type == SK_YUKON_FE) { 1515 sc->sk_workaround = SK_WA_4109; 1516 switch (sc->sk_rev) { 1517 case SK_YUKON_FE_REV_A1: 1518 revstr = "A1"; 1519 break; 1520 case SK_YUKON_FE_REV_A2: 1521 revstr = "A2"; 1522 break; 1523 default: 1524 sc->sk_workaround = 0; 1525 break; 1526 } 1527 } 1528 1529 if (sc->sk_type == SK_YUKON_EC_U) { 1530 sc->sk_workaround = SK_WA_4109; 1531 switch (sc->sk_rev) { 1532 case SK_YUKON_EC_U_REV_A0: 1533 revstr = "A0"; 1534 break; 1535 case SK_YUKON_EC_U_REV_A1: 1536 revstr = "A1"; 1537 break; 1538 case SK_YUKON_EC_U_REV_B0: 1539 revstr = "B0"; 1540 break; 1541 case SK_YUKON_EC_U_REV_B1: 1542 revstr = "B1"; 1543 break; 1544 default: 1545 sc->sk_workaround = 0; 1546 break; 1547 } 1548 } 1549 1550 if (sc->sk_type == SK_YUKON_FE) { 1551 switch (sc->sk_rev) { 1552 case SK_YUKON_FE_REV_A1: 1553 revstr = "A1"; 1554 break; 1555 case SK_YUKON_FE_REV_A2: 1556 revstr = "A2"; 1557 break; 1558 default: 1559 ; 1560 } 1561 } 1562 1563 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0) 1564 revstr = "A0"; 1565 1566 if (sc->sk_type == SK_YUKON_EX) { 1567 switch (sc->sk_rev) { 1568 case SK_YUKON_EX_REV_A0: 1569 revstr = "A0"; 1570 break; 1571 case SK_YUKON_EX_REV_B0: 1572 revstr = "B0"; 1573 break; 1574 default: 1575 ; 1576 } 1577 } 1578 1579 if (sc->sk_type == SK_YUKON_SUPR) { 1580 switch (sc->sk_rev) { 1581 case SK_YUKON_SUPR_REV_A0: 1582 revstr = "A0"; 1583 break; 1584 case SK_YUKON_SUPR_REV_B0: 1585 revstr = "B0"; 1586 break; 1587 case SK_YUKON_SUPR_REV_B1: 1588 revstr = "B1"; 1589 break; 1590 default: 1591 ; 1592 } 1593 } 1594 1595 if (sc->sk_type == SK_YUKON_PRM) { 1596 switch (sc->sk_rev) { 1597 case SK_YUKON_PRM_REV_Z1: 1598 revstr = "Z1"; 1599 break; 1600 case SK_YUKON_PRM_REV_A0: 1601 revstr = "A0"; 1602 break; 1603 default: 1604 ; 1605 } 1606 } 1607 1608 /* Announce the product name. */ 1609 aprint_normal(", %s", sc->sk_name); 1610 if (revstr != NULL) 1611 aprint_normal(" rev. %s", revstr); 1612 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr); 1613 1614 sc->sk_macs = 1; 1615 1616 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1617 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1618 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1619 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1620 sc->sk_macs++; 1621 } 1622 1623 skca.skc_port = SK_PORT_A; 1624 skca.skc_type = sc->sk_type; 1625 skca.skc_rev = sc->sk_rev; 1626 (void)config_found(sc->sk_dev, &skca, mskcprint); 1627 1628 if (sc->sk_macs > 1) { 1629 skca.skc_port = SK_PORT_B; 1630 skca.skc_type = sc->sk_type; 1631 skca.skc_rev = sc->sk_rev; 1632 (void)config_found(sc->sk_dev, &skca, mskcprint); 1633 } 1634 1635 /* Turn on the 'driver is loaded' LED. */ 1636 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1637 1638 /* skc sysctl setup */ 1639 1640 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1641 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1642 SYSCTL_DESCR("mskc per-controller controls"), 1643 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE, 1644 CTL_EOL)) != 0) { 1645 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1646 goto fail_6; 1647 } 1648 1649 sk_nodenum = node->sysctl_num; 1650 1651 /* interrupt moderation time in usecs */ 1652 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1653 CTLFLAG_READWRITE, 1654 CTLTYPE_INT, "int_mod", 1655 SYSCTL_DESCR("msk interrupt moderation timer"), 1656 msk_sysctl_handler, 0, (void *)sc, 1657 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE, 1658 CTL_EOL)) != 0) { 1659 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1660 goto fail_6; 1661 } 1662 1663 if (!pmf_device_register(self, mskc_suspend, mskc_resume)) 1664 aprint_error_dev(self, "couldn't establish power handler\n"); 1665 1666 return; 1667 1668 fail_6: 1669 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map); 1670 fail_4: 1671 bus_dmamem_unmap(sc->sc_dmatag, kva, 1672 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1673 fail_3: 1674 bus_dmamem_free(sc->sc_dmatag, 1675 &sc->sk_status_seg, sc->sk_status_nseg); 1676 sc->sk_status_nseg = 0; 1677 fail_5: 1678 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1679 fail_2: 1680 pci_intr_disestablish(pc, sc->sk_intrhand); 1681 sc->sk_intrhand = NULL; 1682 fail_1: 1683 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size); 1684 sc->sk_bsize = 0; 1685 } 1686 1687 int 1688 mskc_detach(device_t self, int flags) 1689 { 1690 struct sk_softc *sc = device_private(self); 1691 int rv; 1692 1693 if (sc->sk_intrhand) 1694 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand); 1695 1696 rv = config_detach_children(self, flags); 1697 if (rv != 0) 1698 return (rv); 1699 1700 if (sc->sk_status_nseg > 0) { 1701 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map); 1702 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring, 1703 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc)); 1704 bus_dmamem_free(sc->sc_dmatag, 1705 &sc->sk_status_seg, sc->sk_status_nseg); 1706 } 1707 1708 if (sc->sk_bsize > 0) 1709 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize); 1710 1711 return(0); 1712 } 1713 1714 int 1715 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1716 { 1717 struct sk_softc *sc = sc_if->sk_softc; 1718 struct msk_tx_desc *f = NULL; 1719 u_int32_t frag, cur; 1720 int i; 1721 struct sk_txmap_entry *entry; 1722 bus_dmamap_t txmap; 1723 1724 DPRINTFN(2, ("msk_encap\n")); 1725 1726 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1727 if (entry == NULL) { 1728 DPRINTFN(2, ("msk_encap: no txmap available\n")); 1729 return (ENOBUFS); 1730 } 1731 txmap = entry->dmamap; 1732 1733 cur = frag = *txidx; 1734 1735 #ifdef MSK_DEBUG 1736 if (mskdebug >= 2) 1737 msk_dump_mbuf(m_head); 1738 #endif 1739 1740 /* 1741 * Start packing the mbufs in this chain into 1742 * the fragment pointers. Stop when we run out 1743 * of fragments or hit the end of the mbuf chain. 1744 */ 1745 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1746 BUS_DMA_NOWAIT)) { 1747 DPRINTFN(2, ("msk_encap: dmamap failed\n")); 1748 return (ENOBUFS); 1749 } 1750 1751 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) { 1752 DPRINTFN(2, ("msk_encap: too few descriptors free\n")); 1753 bus_dmamap_unload(sc->sc_dmatag, txmap); 1754 return (ENOBUFS); 1755 } 1756 1757 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1758 1759 /* Sync the DMA map. */ 1760 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1761 BUS_DMASYNC_PREWRITE); 1762 1763 for (i = 0; i < txmap->dm_nsegs; i++) { 1764 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1765 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr); 1766 f->sk_len = htole16(txmap->dm_segs[i].ds_len); 1767 f->sk_ctl = 0; 1768 if (i == 0) 1769 f->sk_opcode = SK_Y2_TXOPC_PACKET; 1770 else 1771 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN; 1772 cur = frag; 1773 SK_INC(frag, MSK_TX_RING_CNT); 1774 } 1775 1776 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1777 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1778 1779 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1780 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG; 1781 1782 /* Sync descriptors before handing to chip */ 1783 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1784 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1785 1786 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN; 1787 1788 /* Sync first descriptor to hand it off */ 1789 MSK_CDTXSYNC(sc_if, *txidx, 1, 1790 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1791 1792 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs; 1793 1794 #ifdef MSK_DEBUG 1795 if (mskdebug >= 2) { 1796 struct msk_tx_desc *le; 1797 u_int32_t idx; 1798 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) { 1799 le = &sc_if->sk_rdata->sk_tx_ring[idx]; 1800 msk_dump_txdesc(le, idx); 1801 } 1802 } 1803 #endif 1804 1805 *txidx = frag; 1806 1807 DPRINTFN(2, ("msk_encap: completed successfully\n")); 1808 1809 return (0); 1810 } 1811 1812 void 1813 msk_start(struct ifnet *ifp) 1814 { 1815 struct sk_if_softc *sc_if = ifp->if_softc; 1816 struct mbuf *m_head = NULL; 1817 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1818 int pkts = 0; 1819 1820 DPRINTFN(2, ("msk_start\n")); 1821 1822 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1823 IFQ_POLL(&ifp->if_snd, m_head); 1824 if (m_head == NULL) 1825 break; 1826 1827 /* 1828 * Pack the data into the transmit ring. If we 1829 * don't have room, set the OACTIVE flag and wait 1830 * for the NIC to drain the ring. 1831 */ 1832 if (msk_encap(sc_if, m_head, &idx)) { 1833 ifp->if_flags |= IFF_OACTIVE; 1834 break; 1835 } 1836 1837 /* now we are committed to transmit the packet */ 1838 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1839 pkts++; 1840 1841 /* 1842 * If there's a BPF listener, bounce a copy of this frame 1843 * to him. 1844 */ 1845 bpf_mtap(ifp, m_head, BPF_D_OUT); 1846 } 1847 if (pkts == 0) 1848 return; 1849 1850 /* Transmit */ 1851 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1852 sc_if->sk_cdata.sk_tx_prod = idx; 1853 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx); 1854 1855 /* Set a timeout in case the chip goes out to lunch. */ 1856 ifp->if_timer = 5; 1857 } 1858 } 1859 1860 void 1861 msk_watchdog(struct ifnet *ifp) 1862 { 1863 struct sk_if_softc *sc_if = ifp->if_softc; 1864 1865 /* 1866 * Reclaim first as there is a possibility of losing Tx completion 1867 * interrupts. 1868 */ 1869 msk_txeof(sc_if); 1870 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1871 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1872 1873 ifp->if_oerrors++; 1874 1875 /* XXX Resets both ports; we shouldn't do that. */ 1876 mskc_reset(sc_if->sk_softc); 1877 msk_reset(sc_if); 1878 msk_init(ifp); 1879 } 1880 } 1881 1882 static bool 1883 mskc_suspend(device_t dv, const pmf_qual_t *qual) 1884 { 1885 struct sk_softc *sc = device_private(dv); 1886 1887 DPRINTFN(2, ("mskc_suspend\n")); 1888 1889 /* Turn off the 'driver is loaded' LED. */ 1890 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1891 1892 return true; 1893 } 1894 1895 static bool 1896 mskc_resume(device_t dv, const pmf_qual_t *qual) 1897 { 1898 struct sk_softc *sc = device_private(dv); 1899 1900 DPRINTFN(2, ("mskc_resume\n")); 1901 1902 mskc_reset(sc); 1903 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1904 1905 return true; 1906 } 1907 1908 static __inline int 1909 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 1910 { 1911 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1912 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1913 YU_RXSTAT_JABBER)) != 0 || 1914 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1915 YU_RXSTAT_BYTES(stat) != len) 1916 return (0); 1917 1918 return (1); 1919 } 1920 1921 void 1922 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat) 1923 { 1924 struct sk_softc *sc = sc_if->sk_softc; 1925 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1926 struct mbuf *m; 1927 struct sk_chain *cur_rx; 1928 int cur, total_len = len; 1929 bus_dmamap_t dmamap; 1930 1931 DPRINTFN(2, ("msk_rxeof\n")); 1932 1933 cur = sc_if->sk_cdata.sk_rx_cons; 1934 1935 /* Sync the descriptor */ 1936 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1937 1938 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1939 if (cur_rx->sk_mbuf == NULL) 1940 return; 1941 1942 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 1943 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT); 1944 sc_if->sk_cdata.sk_rx_cnt--; 1945 1946 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1947 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1948 1949 m = cur_rx->sk_mbuf; 1950 cur_rx->sk_mbuf = NULL; 1951 1952 if (total_len < SK_MIN_FRAMELEN || 1953 total_len > ETHER_MAX_LEN_JUMBO || 1954 msk_rxvalid(sc, rxstat, total_len) == 0) { 1955 ifp->if_ierrors++; 1956 msk_newbuf(sc_if, m, dmamap); 1957 return; 1958 } 1959 1960 /* 1961 * Try to allocate a new jumbo buffer. If that fails, copy the 1962 * packet to mbufs and put the jumbo buffer back in the ring 1963 * so it can be re-used. If allocating mbufs fails, then we 1964 * have to drop the packet. 1965 */ 1966 if (msk_newbuf(sc_if, NULL, dmamap) == ENOBUFS) { 1967 struct mbuf *m0; 1968 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1969 total_len + ETHER_ALIGN, 0, ifp, NULL); 1970 msk_newbuf(sc_if, m, dmamap); 1971 if (m0 == NULL) { 1972 ifp->if_ierrors++; 1973 return; 1974 } 1975 m_adj(m0, ETHER_ALIGN); 1976 m = m0; 1977 } else { 1978 m_set_rcvif(m, ifp); 1979 m->m_pkthdr.len = m->m_len = total_len; 1980 } 1981 1982 /* pass it on. */ 1983 if_percpuq_enqueue(ifp->if_percpuq, m); 1984 } 1985 1986 void 1987 msk_txeof(struct sk_if_softc *sc_if) 1988 { 1989 struct sk_softc *sc = sc_if->sk_softc; 1990 struct msk_tx_desc *cur_tx; 1991 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1992 u_int32_t idx, reg, sk_ctl; 1993 struct sk_txmap_entry *entry; 1994 1995 DPRINTFN(2, ("msk_txeof\n")); 1996 1997 if (sc_if->sk_port == SK_PORT_A) 1998 reg = SK_STAT_BMU_TXA1_RIDX; 1999 else 2000 reg = SK_STAT_BMU_TXA2_RIDX; 2001 2002 /* 2003 * Go through our tx ring and free mbufs for those 2004 * frames that have been sent. 2005 */ 2006 idx = sc_if->sk_cdata.sk_tx_cons; 2007 while (idx != sk_win_read_2(sc, reg)) { 2008 MSK_CDTXSYNC(sc_if, idx, 1, 2009 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2010 2011 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2012 sk_ctl = cur_tx->sk_ctl; 2013 #ifdef MSK_DEBUG 2014 if (mskdebug >= 2) 2015 msk_dump_txdesc(cur_tx, idx); 2016 #endif 2017 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG) 2018 ifp->if_opackets++; 2019 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2020 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2021 2022 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2023 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2024 2025 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2026 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2027 2028 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2029 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2030 link); 2031 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2032 } 2033 sc_if->sk_cdata.sk_tx_cnt--; 2034 SK_INC(idx, MSK_TX_RING_CNT); 2035 } 2036 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2037 2038 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2) 2039 ifp->if_flags &= ~IFF_OACTIVE; 2040 2041 sc_if->sk_cdata.sk_tx_cons = idx; 2042 } 2043 2044 void 2045 msk_fill_rx_ring(struct sk_if_softc *sc_if) 2046 { 2047 /* Make sure to not completely wrap around */ 2048 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) { 2049 if (msk_newbuf(sc_if, NULL, 2050 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 2051 break; 2052 } 2053 } 2054 } 2055 2056 void 2057 msk_tick(void *xsc_if) 2058 { 2059 struct sk_if_softc *sc_if = xsc_if; 2060 struct mii_data *mii = &sc_if->sk_mii; 2061 int s; 2062 2063 s = splnet(); 2064 mii_tick(mii); 2065 splx(s); 2066 2067 callout_schedule(&sc_if->sk_tick_ch, hz); 2068 } 2069 2070 void 2071 msk_intr_yukon(struct sk_if_softc *sc_if) 2072 { 2073 u_int8_t status; 2074 2075 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2076 /* RX overrun */ 2077 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2078 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2079 SK_RFCTL_RX_FIFO_OVER); 2080 } 2081 /* TX underrun */ 2082 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2083 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, 2084 SK_TFCTL_TX_FIFO_UNDER); 2085 } 2086 2087 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status)); 2088 } 2089 2090 int 2091 msk_intr(void *xsc) 2092 { 2093 struct sk_softc *sc = xsc; 2094 struct sk_if_softc *sc_if; 2095 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2096 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2097 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2098 int claimed = 0; 2099 u_int32_t status; 2100 struct msk_status_desc *cur_st; 2101 2102 status = CSR_READ_4(sc, SK_Y2_ISSR2); 2103 if (status == 0xffffffff) 2104 return (0); 2105 if (status == 0) { 2106 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2107 return (0); 2108 } 2109 2110 status = CSR_READ_4(sc, SK_ISR); 2111 2112 if (sc_if0 != NULL) 2113 ifp0 = &sc_if0->sk_ethercom.ec_if; 2114 if (sc_if1 != NULL) 2115 ifp1 = &sc_if1->sk_ethercom.ec_if; 2116 2117 if (sc_if0 && (status & SK_Y2_IMR_MAC1) && 2118 (ifp0->if_flags & IFF_RUNNING)) { 2119 msk_intr_yukon(sc_if0); 2120 } 2121 2122 if (sc_if1 && (status & SK_Y2_IMR_MAC2) && 2123 (ifp1->if_flags & IFF_RUNNING)) { 2124 msk_intr_yukon(sc_if1); 2125 } 2126 2127 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2128 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2129 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2130 2131 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) { 2132 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN; 2133 switch (cur_st->sk_opcode) { 2134 case SK_Y2_STOPC_RXSTAT: 2135 sc_if = sc->sk_if[cur_st->sk_link & 0x01]; 2136 msk_rxeof(sc_if, letoh16(cur_st->sk_len), 2137 letoh32(cur_st->sk_status)); 2138 msk_fill_rx_ring(sc_if); 2139 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2140 sc_if->sk_cdata.sk_rx_prod); 2141 break; 2142 case SK_Y2_STOPC_TXSTAT: 2143 if (sc_if0) 2144 msk_txeof(sc_if0); 2145 if (sc_if1) 2146 msk_txeof(sc_if1); 2147 break; 2148 default: 2149 aprint_error("opcode=0x%x\n", cur_st->sk_opcode); 2150 break; 2151 } 2152 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT); 2153 2154 MSK_CDSTSYNC(sc, sc->sk_status_idx, 2155 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2156 cur_st = &sc->sk_status_ring[sc->sk_status_idx]; 2157 } 2158 2159 if (status & SK_Y2_IMR_BMU) { 2160 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 2161 claimed = 1; 2162 } 2163 2164 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2165 2166 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2167 if_schedule_deferred_start(ifp0); 2168 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2169 if_schedule_deferred_start(ifp1); 2170 2171 KASSERT(sc->rnd_attached > 0); 2172 rnd_add_uint32(&sc->rnd_source, status); 2173 2174 if (sc->sk_int_mod_pending) 2175 msk_update_int_mod(sc, 1); 2176 2177 return claimed; 2178 } 2179 2180 void 2181 msk_init_yukon(struct sk_if_softc *sc_if) 2182 { 2183 u_int32_t v; 2184 u_int16_t reg; 2185 struct sk_softc *sc; 2186 int i; 2187 2188 sc = sc_if->sk_softc; 2189 2190 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n", 2191 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2192 2193 DPRINTFN(6, ("msk_init_yukon: 1\n")); 2194 2195 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n", 2196 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2197 2198 DPRINTFN(6, ("msk_init_yukon: 3\n")); 2199 2200 /* unused read of the interrupt source register */ 2201 DPRINTFN(6, ("msk_init_yukon: 4\n")); 2202 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2203 2204 DPRINTFN(6, ("msk_init_yukon: 4a\n")); 2205 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2206 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2207 2208 /* MIB Counter Clear Mode set */ 2209 reg |= YU_PAR_MIB_CLR; 2210 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg)); 2211 DPRINTFN(6, ("msk_init_yukon: 4b\n")); 2212 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2213 2214 /* MIB Counter Clear Mode clear */ 2215 DPRINTFN(6, ("msk_init_yukon: 5\n")); 2216 reg &= ~YU_PAR_MIB_CLR; 2217 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2218 2219 /* receive control reg */ 2220 DPRINTFN(6, ("msk_init_yukon: 7\n")); 2221 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2222 2223 /* transmit control register */ 2224 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10)); 2225 2226 /* transmit flow control register */ 2227 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff); 2228 2229 /* transmit parameter register */ 2230 DPRINTFN(6, ("msk_init_yukon: 8\n")); 2231 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2232 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04); 2233 2234 /* serial mode register */ 2235 DPRINTFN(6, ("msk_init_yukon: 9\n")); 2236 reg = YU_SMR_DATA_BLIND(0x1c) | 2237 YU_SMR_MFL_VLAN | 2238 YU_SMR_IPG_DATA(0x1e); 2239 2240 if (sc->sk_type != SK_YUKON_FE && 2241 sc->sk_type != SK_YUKON_FE_P) 2242 reg |= YU_SMR_MFL_JUMBO; 2243 2244 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2245 2246 DPRINTFN(6, ("msk_init_yukon: 10\n")); 2247 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2248 /* msk_attach calls me before ether_ifattach so check null */ 2249 if (ifp != NULL && ifp->if_sadl != NULL) 2250 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl), 2251 sizeof(sc_if->sk_enaddr)); 2252 /* Setup Yukon's address */ 2253 for (i = 0; i < 3; i++) { 2254 /* Write Source Address 1 (unicast filter) */ 2255 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2256 sc_if->sk_enaddr[i * 2] | 2257 sc_if->sk_enaddr[i * 2 + 1] << 8); 2258 } 2259 2260 for (i = 0; i < 3; i++) { 2261 reg = sk_win_read_2(sc_if->sk_softc, 2262 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2263 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2264 } 2265 2266 /* Set promiscuous mode */ 2267 msk_setpromisc(sc_if); 2268 2269 /* Set multicast filter */ 2270 DPRINTFN(6, ("msk_init_yukon: 11\n")); 2271 msk_setmulti(sc_if); 2272 2273 /* enable interrupt mask for counter overflows */ 2274 DPRINTFN(6, ("msk_init_yukon: 12\n")); 2275 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2276 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2277 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2278 2279 /* Configure RX MAC FIFO Flush Mask */ 2280 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2281 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2282 YU_RXSTAT_JABBER; 2283 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2284 2285 /* Configure RX MAC FIFO */ 2286 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2287 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON | 2288 SK_RFCTL_FIFO_FLUSH_ON); 2289 2290 /* Increase flush threshould to 64 bytes */ 2291 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2292 SK_RFCTL_FIFO_THRESHOLD + 1); 2293 2294 /* Configure TX MAC FIFO */ 2295 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2296 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2297 2298 #if 1 2299 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN); 2300 #endif 2301 DPRINTFN(6, ("msk_init_yukon: end\n")); 2302 } 2303 2304 /* 2305 * Note that to properly initialize any part of the GEnesis chip, 2306 * you first have to take it out of reset mode. 2307 */ 2308 int 2309 msk_init(struct ifnet *ifp) 2310 { 2311 struct sk_if_softc *sc_if = ifp->if_softc; 2312 struct sk_softc *sc = sc_if->sk_softc; 2313 int rc = 0, s; 2314 uint32_t imr, imtimer_ticks; 2315 2316 2317 DPRINTFN(2, ("msk_init\n")); 2318 2319 s = splnet(); 2320 2321 /* Cancel pending I/O and free all RX/TX buffers. */ 2322 msk_stop(ifp, 1); 2323 2324 /* Configure I2C registers */ 2325 2326 /* Configure XMAC(s) */ 2327 msk_init_yukon(sc_if); 2328 if ((rc = ether_mediachange(ifp)) != 0) 2329 goto out; 2330 2331 /* Configure transmit arbiter(s) */ 2332 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON); 2333 #if 0 2334 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2335 #endif 2336 2337 /* Configure RAMbuffers */ 2338 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2339 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2341 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2342 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2343 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2344 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET); 2346 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON); 2347 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart); 2348 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart); 2349 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart); 2350 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend); 2351 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON); 2352 2353 /* Configure BMUs */ 2354 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016); 2355 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28); 2356 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080); 2357 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */ 2358 2359 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016); 2360 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28); 2361 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080); 2362 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */ 2363 2364 /* Make sure the sync transmit queue is disabled. */ 2365 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET); 2366 2367 /* Init descriptors */ 2368 if (msk_init_rx_ring(sc_if) == ENOBUFS) { 2369 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2370 "memory for rx buffers\n"); 2371 msk_stop(ifp, 1); 2372 splx(s); 2373 return ENOBUFS; 2374 } 2375 2376 if (msk_init_tx_ring(sc_if) == ENOBUFS) { 2377 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2378 "memory for tx buffers\n"); 2379 msk_stop(ifp, 1); 2380 splx(s); 2381 return ENOBUFS; 2382 } 2383 2384 /* Set interrupt moderation if changed via sysctl. */ 2385 switch (sc->sk_type) { 2386 case SK_YUKON_EC: 2387 case SK_YUKON_EC_U: 2388 case SK_YUKON_EX: 2389 case SK_YUKON_SUPR: 2390 case SK_YUKON_ULTRA2: 2391 case SK_YUKON_OPTIMA: 2392 case SK_YUKON_PRM: 2393 case SK_YUKON_OPTIMA2: 2394 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2395 break; 2396 case SK_YUKON_FE: 2397 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE; 2398 break; 2399 case SK_YUKON_FE_P: 2400 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P; 2401 break; 2402 case SK_YUKON_XL: 2403 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL; 2404 break; 2405 default: 2406 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2407 } 2408 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2409 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2410 sk_win_write_4(sc, SK_IMTIMERINIT, 2411 SK_IM_USECS(sc->sk_int_mod)); 2412 aprint_verbose_dev(sc->sk_dev, 2413 "interrupt moderation is %d us\n", sc->sk_int_mod); 2414 } 2415 2416 /* Initialize prefetch engine. */ 2417 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2418 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002); 2419 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1); 2420 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO, 2421 MSK_RX_RING_ADDR(sc_if, 0)); 2422 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI, 2423 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32); 2424 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008); 2425 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR); 2426 2427 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2428 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002); 2429 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1); 2430 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO, 2431 MSK_TX_RING_ADDR(sc_if, 0)); 2432 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI, 2433 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32); 2434 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008); 2435 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR); 2436 2437 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX, 2438 sc_if->sk_cdata.sk_rx_prod); 2439 2440 /* Configure interrupt handling */ 2441 if (sc_if->sk_port == SK_PORT_A) 2442 sc->sk_intrmask |= SK_Y2_INTRS1; 2443 else 2444 sc->sk_intrmask |= SK_Y2_INTRS2; 2445 sc->sk_intrmask |= SK_Y2_IMR_BMU; 2446 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2447 2448 ifp->if_flags |= IFF_RUNNING; 2449 ifp->if_flags &= ~IFF_OACTIVE; 2450 2451 callout_schedule(&sc_if->sk_tick_ch, hz); 2452 2453 out: 2454 splx(s); 2455 return rc; 2456 } 2457 2458 /* 2459 * Note: the logic of second parameter is inverted compared to OpenBSD 2460 * code, since this code uses the function as if_stop hook too. 2461 */ 2462 void 2463 msk_stop(struct ifnet *ifp, int disable) 2464 { 2465 struct sk_if_softc *sc_if = ifp->if_softc; 2466 struct sk_softc *sc = sc_if->sk_softc; 2467 struct sk_txmap_entry *dma; 2468 int i; 2469 2470 DPRINTFN(2, ("msk_stop\n")); 2471 2472 callout_stop(&sc_if->sk_tick_ch); 2473 2474 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2475 2476 /* Stop transfer of Tx descriptors */ 2477 2478 /* Stop transfer of Rx descriptors */ 2479 2480 if (disable) { 2481 /* Turn off various components of this interface. */ 2482 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2483 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2484 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2485 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2486 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE); 2487 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2488 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2489 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2490 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP); 2491 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2492 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2493 2494 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001); 2495 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001); 2496 2497 /* Disable interrupts */ 2498 if (sc_if->sk_port == SK_PORT_A) 2499 sc->sk_intrmask &= ~SK_Y2_INTRS1; 2500 else 2501 sc->sk_intrmask &= ~SK_Y2_INTRS2; 2502 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2503 } 2504 2505 /* Free RX and TX mbufs still in the queues. */ 2506 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2507 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2508 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2509 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2510 } 2511 } 2512 2513 sc_if->sk_cdata.sk_rx_prod = 0; 2514 sc_if->sk_cdata.sk_rx_cons = 0; 2515 sc_if->sk_cdata.sk_rx_cnt = 0; 2516 2517 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2518 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2519 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2520 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2521 #if 1 2522 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, 2523 sc_if->sk_cdata.sk_tx_map[i], link); 2524 sc_if->sk_cdata.sk_tx_map[i] = 0; 2525 #endif 2526 } 2527 } 2528 2529 #if 1 2530 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) { 2531 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 2532 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap); 2533 free(dma, M_DEVBUF); 2534 } 2535 #endif 2536 } 2537 2538 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach, 2539 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2540 2541 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach, 2542 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 2543 2544 #ifdef MSK_DEBUG 2545 void 2546 msk_dump_txdesc(struct msk_tx_desc *le, int idx) 2547 { 2548 #define DESC_PRINT(X) \ 2549 if (X) \ 2550 printf("txdesc[%d]." #X "=%#x\n", \ 2551 idx, X); 2552 2553 DESC_PRINT(letoh32(le->sk_addr)); 2554 DESC_PRINT(letoh16(le->sk_len)); 2555 DESC_PRINT(le->sk_ctl); 2556 DESC_PRINT(le->sk_opcode); 2557 #undef DESC_PRINT 2558 } 2559 2560 void 2561 msk_dump_bytes(const char *data, int len) 2562 { 2563 int c, i, j; 2564 2565 for (i = 0; i < len; i += 16) { 2566 printf("%08x ", i); 2567 c = len - i; 2568 if (c > 16) c = 16; 2569 2570 for (j = 0; j < c; j++) { 2571 printf("%02x ", data[i + j] & 0xff); 2572 if ((j & 0xf) == 7 && j > 0) 2573 printf(" "); 2574 } 2575 2576 for (; j < 16; j++) 2577 printf(" "); 2578 printf(" "); 2579 2580 for (j = 0; j < c; j++) { 2581 int ch = data[i + j] & 0xff; 2582 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2583 } 2584 2585 printf("\n"); 2586 2587 if (c < 16) 2588 break; 2589 } 2590 } 2591 2592 void 2593 msk_dump_mbuf(struct mbuf *m) 2594 { 2595 int count = m->m_pkthdr.len; 2596 2597 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2598 2599 while (count > 0 && m) { 2600 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2601 m, m->m_data, m->m_len); 2602 msk_dump_bytes(mtod(m, char *), m->m_len); 2603 2604 count -= m->m_len; 2605 m = m->m_next; 2606 } 2607 } 2608 #endif 2609 2610 static int 2611 msk_sysctl_handler(SYSCTLFN_ARGS) 2612 { 2613 int error, t; 2614 struct sysctlnode node; 2615 struct sk_softc *sc; 2616 2617 node = *rnode; 2618 sc = node.sysctl_data; 2619 t = sc->sk_int_mod; 2620 node.sysctl_data = &t; 2621 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2622 if (error || newp == NULL) 2623 return error; 2624 2625 if (t < SK_IM_MIN || t > SK_IM_MAX) 2626 return EINVAL; 2627 2628 /* update the softc with sysctl-changed value, and mark 2629 for hardware update */ 2630 sc->sk_int_mod = t; 2631 sc->sk_int_mod_pending = 1; 2632 return 0; 2633 } 2634 2635 /* 2636 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be 2637 * set up in mskc_attach() 2638 */ 2639 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup") 2640 { 2641 int rc; 2642 const struct sysctlnode *node; 2643 2644 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2645 0, CTLTYPE_NODE, "msk", 2646 SYSCTL_DESCR("msk interface controls"), 2647 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2648 goto err; 2649 } 2650 2651 msk_root_num = node->sysctl_num; 2652 return; 2653 2654 err: 2655 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2656 } 2657
Indexes created Sun Sep 21 20:09:37 GMT 2025